| Commit message (Collapse) | Author | Age | Files | Lines |
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Update #4180
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Update #4180
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Update #3910.
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This breaks out AArch32-specific code so that the shared GICv3 code can
be reused by other architectures.
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This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
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This UART driver is now needed for BSPs other than ARM.
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In a multi-processor system we must broadcast the TLB maintenance operation to
the Inner Shareable domain to ensure that the other processors update their TLB
caches accordingly.
Close #4068.
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Closes #4055
Closes #4056
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_CPU_Counter_frequency() can be called by the rtems_counter
initialization before arm_gt_clock_initialize() initializes the value
used in _CPU_Counter_frequency().
Closes #3961.
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Statically initialize the ARMv7-M vector table to allow a placement in
ROM with read-only MPU settings.
Change licence to BSD-2-Clause in some files.
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At least on GICv1 the interrupts 0 up to including 31 are so called
Peripheral Private Interrupts (PPIs). We have to initialize the
priority of the PPIs on secondary processors.
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Place idle and MPCI stacks into extra linker sections. This can be
optionally used by applications to control the placement of the stacks.
Update #3835.
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This avoids to pull in via printk() the Termios support which pulls in
the file system support. This fixes a spconfig02 test failure.
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Update #3838.
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This adds support for the GICv3 interrupt controller along with the
redistributor to control SGIs and PPIs which wasn't present in GICv2
implementations. GICv3 implementations only optionally support
memory-mapped GICC interface interaction and require system register
access be implemented, so the GICC interface is accessed only
through system registers.
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Close #3789.
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Xen will mask the virtual timer before injecting the interrupt to the
guest.
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Xen currently only supports the zImage loader for 32 bit guests on ARM
targets.
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The small page MMU support reduces the granularity for memory settings
through the MMU from 1MiB sections to 4KiB small pages.
Enable it by default on the realview_pbx_a9_qemu BSP.
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- The TI's CortexA7 MP MPIDR register returns 0
Updates #3760
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Closes #3760
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This fixes the corruption of r3 by the call to
bsp_start_arm_drop_hyp_mode().
Moving the code makes it easier to review changes in start.S.
Close #3773.
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This makes it easier to review changes in start.S.
Update #3773.
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There are no known ARMv7-M chips with a dual lockstep mode.
Update #3773.
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Closes #3762
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Use _SMP_Multicast_action() instead.
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This driver will be shared with the xilinx-zynqmp BSP.
Update #3682.
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Update #3706.
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Update #3706.
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- Use CamelCase as it is not used in our C code. Enables simple search and
replace.
- Prefix with "RTEMS" to aid deployment and integration. It aids
searching and sorting.
Update #3706.
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The following variants
* GICv1 with Security Extensions,
* GICv2 without Security Extensions, or
* within Secure processor mode
have the ability to assign group 0 or 1 to individual interrupts. Group
0 interrupts can be configured to raise an FIQ exception. This enables
the use of NMIs with respect to RTEMS.
BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
define. Use arm_gic_irq_set_group() to change the group of an
interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is
defined).
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This makes the @file documentation independent of the actual file name.
Update #3707.
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Move device tree copy operation after the mode initialization so that
bsp_fdt_copy() uses the initialization stack and not the stack provided
up by the boot loader.
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Update #3456.
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Update #3459.
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Update #3667.
Close #3674.
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Update #3667.
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Close #3667.
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Remove this superfluous define.
Update #3667.
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The boot_card() function does not return.
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Rename
* _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin,
* _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and
* _Configuration_Interrupt_stack_size in _ISR_Stack_size.
Move definitions to <rtems/score/isr.h>. The new names are considerable
shorter and in the right namespace.
Update #3459.
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