| Commit message (Collapse) | Author | Age | Files | Lines |
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RTEMS may be booted from a dirty environment. Ensure that FPU trap
settings are consistent.
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Always start the executive in Exception Level 1, Non-Secure mode.
If we boot in EL3 Secure with GICv3 then we have to initialize
the distributor and redistributor to set up G1NS interrupts
early in the boot sequence before stepping down from EL3S to EL1NS.
Now there is no need to distinguish between secure and non-secure
world execution after the primary core boots, so get rid of the
AARCH64_IS_NONSECURE configuration option.
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Debug events should be masked at least until after the first context
switch and should usually be masked until a debugger is attached for
application debugging.
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This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
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Add the stub necessary to boot on AArch64 under EL2 and drop to EL1 for
normal operation.
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Run with stack alignment faults enabled under RTEMS_DEBUG to catch any
stack misalignments early. This makes it easier to track them down
should they ever occur.
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This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53
emulation with interrupt support using GICv3 and clock support using
the ARM GPT.
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This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
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