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* bsps/aarch64: Ensure FPU trap state is consistentKinsey Moore2022-11-091-0/+6
| | | | | RTEMS may be booted from a dirty environment. Ensure that FPU trap settings are consistent.
* aarch64: always boot into EL1NSGedare Bloom2022-01-121-19/+27
| | | | | | | | | | | Always start the executive in Exception Level 1, Non-Secure mode. If we boot in EL3 Secure with GICv3 then we have to initialize the distributor and redistributor to set up G1NS interrupts early in the boot sequence before stepping down from EL3S to EL1NS. Now there is no need to distinguish between secure and non-secure world execution after the primary core boots, so get rid of the AARCH64_IS_NONSECURE configuration option.
* bsps/aarch64: refactor register init and hooksGedare Bloom2022-01-121-40/+41
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* bsps/aarch64: Mask debug events from startupKinsey Moore2021-11-011-2/+2
| | | | | | Debug events should be masked at least until after the first context switch and should usually be masked until a debugger is attached for application debugging.
* cpukit: Add AArch64 SMP SupportKinsey Moore2021-09-211-6/+6
| | | | This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
* aarch64: whitespace fixes in start.SGedare Bloom2021-06-241-166/+166
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* bsps/aarch64: replace boot options with asm switch codeGedare Bloom2021-06-241-7/+8
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* bsps/aarch64: add non-secure mode and versal supportGedare Bloom2021-06-241-2/+16
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* aarch64: add support to drop EL3 to EL2Kinsey Moore2021-06-241-1/+26
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* bsps/aarch64: Add support for EL2 startKinsey Moore2021-03-051-0/+25
| | | | | Add the stub necessary to boot on AArch64 under EL2 and drop to EL1 for normal operation.
* bsps/aarch64: RTEMS_DEBUG stack alignment faultsKinsey Moore2021-03-051-0/+8
| | | | | | Run with stack alignment faults enabled under RTEMS_DEBUG to catch any stack misalignments early. This makes it easier to track them down should they ever occur.
* bsps: Add Cortex-A53 ILP32 BSP variantKinsey Moore2020-10-051-0/+16
| | | | | | This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53 emulation with interrupt support using GICv3 and clock support using the ARM GPT.
* bsps: Add Cortex-A53 LP64 basic BSPKinsey Moore2020-10-051-0/+219
This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with interrupt support using GICv3 and clock support using the ARM GPT.