summaryrefslogtreecommitdiffstats
path: root/bsps/aarch64/shared (follow)
Commit message (Collapse)AuthorAgeFilesLines
* bsps/aarch64/cache: Clean up unused fuctionsKinsey Moore2024-01-101-27/+2
| | | | | | | | | When the CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS definition was added to AArch64 cache management, it obsoleted the *_1_data/instruction_line functions. These have been removed since they are no longer referenced. The AArch64_instruction_cache_inner_shareable_invalidate_all function is only used when RTEMS_SMP is defined, so only define it in that circumstance.
* bsps: Remove unused includesKinsey Moore2023-10-131-1/+0
|
* bsps/aarch64: Enable MMU during remapsKinsey Moore2023-04-181-3/+4
| | | | | | | | The MMU must be enabled during mapping changes and TLB invalidations. When this is not the case, TLB updates do not occur correctly in all cases. This is especially apparent when changing a block entry to a table entry when remapping small memory ranges in an otherwise contiguous block.
* bsps/aarch64: Disable interrupts during MMU remapKinsey Moore2023-02-271-0/+6
| | | | | | Interrupts must be disabled during MMU remapping since the majority of RTEMS including interrupts expects normal memory mapping semantics such as unaligned accesses.
* bsps/aarch64: Fix off-by-one cache bugKinsey Moore2023-02-141-16/+16
| | | | | | | The whole cache invalidation and flushing functions only ended up flusing the first N-1 levels of cache due to an off by one error. This resovles that issue and makes consistent the usage of levels as they relate to caching.
* bsps/aarch64: Ensure FPU trap state is consistentKinsey Moore2022-11-091-0/+6
| | | | | RTEMS may be booted from a dirty environment. Ensure that FPU trap settings are consistent.
* bsps: Fix .data.rel.ro placementSebastian Huber2022-08-121-1/+1
| | | | | | | The .data.rel.ro* linker input section pattern accidentally matches with writeable data those symbol name starts with "ro". Close #4701.
* basp/aarch64: Make the unexpected sections origin address 64bitChris Johns2022-07-281-1/+1
| | | | Update #4684
* aarch64: Use page table level 0Kinsey Moore2022-07-211-1/+6
| | | | | | | | | This alters the AArch64 page table generation and mapping code and MMU configuration to use page table level 0 in addition to levels 1, 2, and 3. This allows the mapping of up to 48 bits of memory space and is the maximum that can be mapped without relying on additional processor extensions. Mappings are restricted based on the number of physical address bits that the CPU supports.
* bsps: Sort .noinit* sectionsSebastian Huber2022-07-151-1/+1
| | | | | | | | Sort the .noinit* input sections by name first, then by alignment if two sections have the same name. This allows the placement of begin/end symbols to initialize some areas with a special value. Update #4678.
* aarch64: always boot into EL1NSGedare Bloom2022-01-121-19/+27
| | | | | | | | | | | Always start the executive in Exception Level 1, Non-Secure mode. If we boot in EL3 Secure with GICv3 then we have to initialize the distributor and redistributor to set up G1NS interrupts early in the boot sequence before stepping down from EL3S to EL1NS. Now there is no need to distinguish between secure and non-secure world execution after the primary core boots, so get rid of the AARCH64_IS_NONSECURE configuration option.
* bsps/aarch64: refactor register init and hooksGedare Bloom2022-01-121-40/+41
|
* bsps/aarch64: Support .noinit linker sectionSebastian Huber2021-12-131-0/+7
|
* bsps/aarch64: Remove erroneous cache featureKinsey Moore2021-12-121-2/+0
| | | | | | | | | | The AArch64 cache implementation does not define rtems_cache_disable_data(), but declares that it does via CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA. The existing implementation of _CPU_cache_disable_data() is sufficient to enable this functionality without the erroneous cache feature flag. Closes #4569
* bsps/aarch64: Mask debug events from startupKinsey Moore2021-11-011-2/+2
| | | | | | Debug events should be masked at least until after the first context switch and should usually be masked until a debugger is attached for application debugging.
* aarch64: Break out MMU definitionsKinsey Moore2021-11-012-0/+118
| | | | | | This moves the AArch64 MMU memory type definitions into cpukit for use by libdebugger since remapping of memory is required to insert software breakpoints.
* cpukit: Add AArch64 SMP SupportKinsey Moore2021-09-212-6/+91
| | | | This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
* aarch64: whitespace fixes in start.SGedare Bloom2021-06-241-166/+166
|
* bsps/aarch64: replace boot options with asm switch codeGedare Bloom2021-06-241-7/+8
|
* bsps/aarch64: add non-secure mode and versal supportGedare Bloom2021-06-241-2/+16
|
* bsps/aarch64: add physical secure timerGedare Bloom2021-06-241-0/+8
|
* aarch64: add support to drop EL3 to EL2Kinsey Moore2021-06-241-1/+26
|
* bsps/aarch64: Advertise cache function supportKinsey Moore2021-05-271-0/+10
| | | | | Ensure that cache functions are flagged as usable by the generic cache implementation code.
* bsps/aarch64: Align MVAs consistentlyKinsey Moore2021-05-271-8/+5
| | | | | | This fixes a bug where addresses were not being aligned correctly. Addresses used in cache functions are now aligned consistently using RTEMS_ALIGN_DOWN.
* bsps/aarch64: Break out system registersKinsey Moore2021-05-271-180/+33
| | | | | Break out system register definitions and accessors so that they're usable by other parts of RTEMS.
* bsps/aarch64: Add support for EL2 startKinsey Moore2021-03-051-0/+25
| | | | | Add the stub necessary to boot on AArch64 under EL2 and drop to EL1 for normal operation.
* bsps/aarch64: RTEMS_DEBUG stack alignment faultsKinsey Moore2021-03-051-0/+8
| | | | | | Run with stack alignment faults enabled under RTEMS_DEBUG to catch any stack misalignments early. This makes it easier to track them down should they ever occur.
* bsps/aarch64: Resolve usage of SUBALIGN()Kinsey Moore2021-03-051-4/+2
| | | | | | | | Remove usage of SUBALIGN() in aarch64 linkcmds which works around a difference in behavior on AArch64 platforms. This is no longer necessary since alignment is now enforced explicitly. Closes #4178.
* bsps: Add missing DWARF 5 sectionsSebastian Huber2021-01-261-3/+5
| | | | Sort alphabetically.
* bsps: Support DWARF 5 sectionsSebastian Huber2021-01-251-8/+13
| | | | GCC 11 uses DWARF 5 by default.
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-231-58/+0
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
* bsps: Fix includesSebastian Huber2020-12-221-1/+0
| | | | Update #4202.
* bsps: Remove gicvx_interrupt_dispatch()Sebastian Huber2020-12-161-5/+0
| | | | | | Avoid one level of indirection. Update #4202.
* bsps: Move ARM GICv2 driver to bsps/sharedKinsey Moore2020-12-021-1/+1
| | | | | This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64 code.
* spec/aarch64: Only apply SUBALIGN(4) to ILP32Kinsey Moore2020-11-231-2/+4
| | | | | | | The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds was previously present on LP64 builds and causes no issues within RTEMS, but causes relocation/alignment issues when building libbsd. This restricts those alignment changes to ILP32 builds.
* bsps: Add Cortex-A53 ILP32 BSP variantKinsey Moore2020-10-051-0/+16
| | | | | | This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53 emulation with interrupt support using GICv3 and clock support using the ARM GPT.
* bsps: Add Cortex-A53 LP64 basic BSPKinsey Moore2020-10-055-0/+1432
This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with interrupt support using GICv3 and clock support using the ARM GPT.
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-23 14:23:10 +0000