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* bsp/tms570: correct baudrate calculation.Pavel Pisa2018-11-141-1/+1
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* bsp/tms570: correct inclusion of header files for build with HW init.Pavel Pisa2018-11-1412-21/+21
The build fails when TMS570_USE_HWINIT_STARTUP=1 option is set.
* bsp/tms570: Simple fix to resolve macro redefinitions.Pavel Pisa2018-10-151-34/+46
closes #3347
* bsp/tms570: remove duplicate of TMS570_SCI_FLR_TX_EMPTY in console driver.Pavel Pisa2017-10-131-1/+7
Initial idea has been that check for both, TMS570_SCI_FLR_TX_EMPTY and TMS570_SCI_FLR_TXRDY is required before console driver parameters update. closes #2883.
* bsp/tms570: include package balls and PINMMR registers mapping for ↵Pavel Pisa2017-04-292-0/+1115
TMS5704357 ZWT chip. The extended mechanism for switching input path by separated alternative registers is already implemented in TMS570 pin multiplexer driver used for TMS570LS31xx rtems/c/src/lib/libbsp/arm/tms570/pinmux/pinmux.c But the code has not been tested on real TMS570LC43xx hardware yet.
* libchip/network/if_fxp.c: do not use rtems_interrupt_disable.Pavel Pisa2016-10-171-7/+4
| | | | | | | | | | The single write to memory or ioport output are mostly atomic operations already. The proper memory synchronization barrier should be used around them to guarantee ordering (sync or eieio on PowerPC for example) but because I have not found settable portable primitive only compiler barrier is used. It should be enough on x86 because the externally visible order should be/is guaranteed to be preserved on x86 architecture.
* bsps/i386: use Pentimum instructions for pc586 and pc686 builds.Pavel Pisa2016-10-172-2/+2
| | | | | | | | | | | | | | | | | | When GCC option -march is not specifies i386-rtems toolchain defaults to i386 architecture instruction set. It does not provide atomic instructions which results in really inefficient atomic_fetch_or even on UP build. SMP build is broken with i386 set because libatomic and GCC generate infinite loop for __atomic_fetch_add_4 used in rtems_interrupt_lock_acquire __atomic_fetch_add_4: push %ebp mov %esp,%ebp movl $0x5,0x10(%ebp) pop %ebp jmp __atomic_fetch_add_4
* bsps/i386: replace global interrupt disable by SMP build supporting locking.Pavel Pisa2016-10-179-72/+148
* bsps/i386: Separate variable for i8259 IRQs disable due to in progress state.Pavel Pisa2016-10-111-19/+36
| | | | | | | | The global state of enabled and disabled interrupts has to hold interrupts really disabled by drivers and system. If the state is combined with interrupts temporarily disabled because they are processed at given time then it is impossible to maintain state by interrupt handlers in drivers.
* pci.h add PCI_COMMAND_INTX_DISABLE definition.Pavel Pisa2016-10-111-0/+1
* score/arm: Correct logic to select 64 byte cache line maximum size for Cortex-A.Pavel Pisa2016-10-041-2/+2
| | | | | | | | The use of actual cache line max bytes and minimum required alignment in architecture but not-BSP dependent code could be problematic because there exists even ARM instruction set implementations with 128 byte line length and real maximum can be quite problematic to say. But actually supported ARM BSPs should be OK with these values.
* libdl/rtl-obj.c: synchronize cache should not depend on CPU_CACHE_LINE_BYTES.Pavel Pisa2016-10-041-3/+6
Use of rtems_cache_get_maximal_line_size() is more descriptive choice. The min/max data/instruction cache line size is not critical there, value is used for optimization only to use single operation for directly following sections.
* arm/tms570: document BSP setup with included hardware initialization.Pavel Pisa2016-09-221-22/+100
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* arm/tms570: update bootstrap generated preinstall.amPavel Pisa2016-09-221-0/+13
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* arm/tms570: include TMS570_USE_HWINIT_STARTUP option to select bare metal ↵Pavel Pisa2016-09-222-0/+26
| | | | startup and selftest.
* arm/tms570: include hardware initialization and selftest based on Ti ↵Pavel Pisa2016-09-2216-0/+3519
| | | | | | | | | | | | | | | | | | | | HalCoGen generated files. The configuration is specific for TMS570LS3137 based HDK. Pins configuration can be easily changed in rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c file. The list tms570_selftest_par_list in the file rtems/c/src/lib/libbsp/arm/tms570/hwinit/bspstarthooks-hwinit.c specifies peripherals which health status is examined by parity self-test at BSP start-up. It can be easily modified for other TMS570 family members variants same as the selection of other tests in bspstarthooks-hwinit.c.
* arm/tms570: define base addresses of all TMS570LS3137 SPI interfaces.Pavel Pisa2016-09-221-1/+5
| | | | | | | | Generated header file ti_herc/reg_spi.h contains complete registers and fields set for Ti MibSPI peripheral. Care has to be taken that only TMS570_SPI1, TMS570_SPI3 and TMS570_SPI5 are of this complete multibuffer type. TMS570_SPI2 and TMS570_SPI4 have substantial part of registers removed but else they are compatible.
* bsps/arm: Export bsp_start_hook_0_done symbol from ARM start.S.Pavel Pisa2016-09-221-0/+1
| | | | | | | | The symbol can be used by bsp_start_hook_0 when complete RAM memory is initialization and overwritten during BSP self-test. The test overwrites even memory used to store return address / link register and regular resturn from bsp_start_hook_0 is not possible then.
* classic networking: adapt FXP driver to work with actual PCI and IRQ code.Pavel Pisa2016-09-212-106/+98
Tested to work with QEMU provided Intel i82557b network controller emulation. qemu-system-x86_64 -enable-kvm -kernel $APP_BINARY \ -vga cirrus \ -append "--console=/dev/com1" \ -serial stdio \ -net nic,vlan=1,macaddr=be:be:be:10:00:01,model=i82557b \ -net tap,ifname=tap1,vlan=1,script=no,downscript=no
* classic networking: do not reference BSP_irq_enabled_at_i8259s which is no ↵Pavel Pisa2016-09-205-40/+5
more available on i386. This change is required to build RTEMS with classic "--enable-networking" and link applications/tests which reference RTEMS_BSP_NETWORK_DRIVER_ATTACH.
* arm/raspberrypi: define bsp_reset to restart board by watchdog.Pavel Pisa2016-09-083-1/+82
Whether the board is restarted after application finish/exit is controlled by BSP_RESET_BOARD_AT_EXIT configure option.
* arm/raspberrypi: use GPU/system timer as clock source.Pavel Pisa2016-09-071-36/+62
| | | | | | It has advantage that it is designed as free-running counter with compare registers and can easily serve for for both timecounter and tick interrupt.
* arm/raspberrypi: correct and extend definitions for GPU timer.Pavel Pisa2016-09-072-7/+16
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* arm/raspberrypi: basic BCM2836 SMP implementation.Pavel Pisa2016-09-078-4/+230
| | | | | | | | The BSP support is divided to startup/bspsmp_api.c file where functions required by SuperCore are defined and BCM2836 hardware initialization part in startup/bspsmp_init.c. Separation is done to prevent smpfatal08 test build failure.
* arm/raspberrypi: propagate number of configured CPUs into linker script.Pavel Pisa2016-09-072-0/+16
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* arm/raspberrypi: rename linkcmds to linkcmds.in to allow their configure ↵Pavel Pisa2016-09-073-4/+3
| | | | processing.
* arm/raspberrypi: more definitions of BCM2836 core local peripherals.Pavel Pisa2016-09-071-2/+140
* bsps/arm: reorganize CP15 code to allow clean and invalidate ARMv7 cache by ↵Pavel Pisa2016-09-071-48/+60
| | | | | | | level. New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level can be used to maintain single cache level (instruction or data).
* bsps/arm: remove lock in arm_cp15_set_translation_table_entries().Pavel Pisa2016-09-071-9/+1
| | | | | | | | | | | Protection by rtems_interrupt_disable() is incompatible with SMP build. Actual page table entries manipulation function does not need locking and disabling cache and can be run concurrently even on multiple CPUs as long as changes do not modify same region. If the function is called from more threads/CPUs to modify same region with different mapping options concurrently then there is problem at another level of virtual address space management and has to be solved by mutex or other locking at that level.
* bsps/arm: use defines for cache type register format field.Pavel Pisa2016-09-071-9/+30
The change documents meaning of codes and opens well defined way to use cache type format for cache examination/debugging outside of arm-cp15.h file.
* arm/xilinx_zynq: ensure that cache is cleaned and MMU disabled when ↵Pavel Pisa2016-09-011-0/+35
initialization starts. The u-boot loader enables the MMU plus the data and instruction caches in some versions which results in RTEMS boot failure. Closes #2774.
* arm/raspberrypi: framebuffer driver checks for initialization and tries ↵Pavel Pisa2016-07-311-1/+11
| | | | | | | | | | | | | | | runtime init if required. Code works but there is problem how to setup caching for the regions (arm_cp15_set_translation_table_entries arguments). If ARMV7_MMU_DATA_READ_WRITE_CACHED is used then CPU accesses are noncoherent with VideoCore and some part of image update are not visible until pushed from cache by other activities. If ARMV7_MMU_DATA_READ_WRITE is used then access is extremely slow. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* arm/raspberrypi: VideoCore access corrections in cache operation and more ↵Pavel Pisa2016-07-316-48/+112
error checking. The first, mistake in buffer size computation for cache flush and invalidate has been corrected. GCC __attribute__( ( aligned( 64 ) ) ) should work and works for local variables. Code ensures right stack alignment. But attribute has to be moved to type declaration to ensure that structure size is affected by attribute. But even this seems to not work reliably for some reason. May it be, the stack area between frame start and end of local variable buffer accessed during context switch or some stack prefetch during resturn such way that some cache lines belonging to buffer are filled to cache. Extending buffer by one more cache line padding helps there. In the longer term perspective, buffer should be moved to some static area or cache aligned dynamic memory allocated. Concurrent calls to the VideoCore operations and access serialization should be added too but problem is that some calls are required during workspace and MMU setup so variant without need of mutex would be required as well. Framebuffer setup code and other VideoCore calls check more precisely for errors and do not proceed forward with incorrect data now. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* arm/raspberrypi: add Secure Digital (SD) controller interrupt source ID from ↵Pavel Pisa2016-07-231-1/+1
| | | | Mudit Jain'a tree.
* arm/raspberrypi: change interrupt dispatch and enable to generic vector id ↵Pavel Pisa2016-07-232-141/+89
| | | | | | | | based approach. Using conditional branches to find bits is extremely inefficient and for asynchronous delivery of different interrupt sources lead to total confusion of branch prediction unit.
* arm/raspberrypi: remove duplicate setup of IRQ handler in the main ARM ↵Pavel Pisa2016-07-232-21/+0
exception table. Exception table setup is processed by common CPU architecture support. For ARM architecture, it can be found in the file rtems/c/src/lib/libbsp/arm/shared/start/start.S and ends by bsp_vector_table_copy_done label. The actual tabel content can be found at bsp_start_vector_table_begin For ARMv7-A and even other variant with hypervisor mode support, it is even not necessary to copy table to address 0 at all because CP15 register can be used to specify alternative table start address arm_cp15_set_vector_base_address(&)bsp_start_vector_table_begin; ARMv7-M have register to set exception table base as well.
* bsp/tms570: ensure that change of SCI baudrate is not applied in the middle ↵Pavel Pisa2016-07-221-2/+23
of character Tx. The rtems_monitor_task() setups/updates termios attributes of the opened TTY and if there is ongoing some other output it leads to the stuck. It would be better to use some termios API function which would call drainOutput() in rtems/cpukit/libcsupport/src/termios.c. But functionality is not accessible outside of core termios implementation. The loop waiting for last character to be sent has to be there anyway because hardware does not provide Tx machine/shift register empty interrupt.
* libdl/rtl-obj.c: synchronize cache after code relocation.Pavel Pisa2016-07-214-2/+74
| | | | | | | | Memory content changes caused by relocation has to be propagated to memory/cache level which is used/snooped during instruction cache fill. Closes #2438
* arm/raspberrypi: reorder and update MMU config table to nor force RW section ↵Pavel Pisa2016-07-201-9/+22
| | | | | | | | | later to RO. Enable even the first megabyte of SDRAM to be cache-able after problems with stale cache content has been resolved by previous commit. Because major part of application usually fits to the first megabyte this speedups test dhrystone application by factor 40.
* arm/raspberrypi: use cache manager operations to flush/invalidate all cache ↵Pavel Pisa2016-07-201-7/+7
| | | | | | | | | levels. This fix strange behavior where some stale content has been stored in level 2 cache before RTEMS has been start from U-boot which has reappeared after MMU enable and shadow vector table at start of SDRAM.
* arm/bsps: CP15 and basic cache support entire cache clean for more ↵Pavel Pisa2016-07-203-6/+66
| | | | | | | | | | | | | | | | | architecture variants now. Next cache operations should work on most of cores now rtems_cache_flush_entire_data() rtems_cache_invalidate_entire_data() rtems_cache_invalidate_entire_instruction() Instruction cache invalidate works on the first level for now only. Data cacache operations are extended to ensure flush/invalidate on all cache levels. The CP15 arm_cp15_data_cache_clean_all_levels() function extended to continue through unified levels too (ctype = 4).
* bsps/arm: do not disable MMU during translation table management operations.Pavel Pisa2016-07-202-8/+58
| | | | | | | | | | | | | | | | | | | | Disabling MMU requires complex cache flushing and invalidation operations. There is almost no way how to do that right on SMP system without stopping all other CPUs. On the other hand, there is documented sequence of operations which should be used according to ARM manual and it guarantees even distribution of maintenance operations to other cores for last generation of Cortex-A cores with multiprocessor extension. This change could require addition of appropriate entry to arm_cp15_start_mmu_config_table for some BSPs to ensure that MMU table stays accessible after MMU is enabled { .begin = (uint32_t) bsp_translation_table_base, .end = (uint32_t) bsp_translation_table_base + 0x4000, .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED }
* arm/raspberrypi: cache manager can be used for mailbox synchronization now. ↵Pavel Pisa2016-07-201-33/+2
Remove workarounds. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsps/arm: basic on core cache support changed to use l1 functions.Pavel Pisa2016-07-043-48/+97
| | | | | | | | | | | | | | The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem.
* libdl/rtl-obj.c: ensure that loaded code is synchronized through caches.Pavel Pisa2016-07-041-0/+2
| | | | | | | | | | | | Synchronize each cluster of sections of the same type separately to support even cases where text and data are allocated from different areas (for example due allocation from different MPU protection regions). rtems_cache_instruction_sync_after_code_change is called even to data sections. Propagation of data only changes should not require cache maintenance operation on sane SMP mutithread capable systems if barrier instruction is added but be on safe side even for case where self modifying code uses data sections initial values etc.
* bsps/arm: Change code to explicit selection of cache implementation for ARM ↵Pavel Pisa2016-07-0410-124/+190
| | | | | | | | | | | | | | | | | | | | | | | BSPs. The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support
* bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.Pavel Pisa2016-07-041-0/+4
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* rtems+bsps/cache: Define cache manager operations for code synchronization ↵Pavel Pisa2016-07-043-1/+72
| | | | | | | | | | | | | | and maximal alignment. There is need for unambiguous named and defined cache function which should be called when code is updated, loaded or is self-modifying. There should be function to obtain maximal cache line length as well. This function can and should be used for allocations which can be used for data and or code and ensures that there are no partial cache lines overlaps on start and end of allocated region.
* arm/raspberrypi: update VideoCore cache flush workaround to work on RPi2.Pavel Pisa2016-07-041-2/+13
| | | | | The arm_cp15_data_cache_clean_and_invalidate leads to hang on RPi2, clean by individual lines works on RPi1 and RPi2.
* score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib.Pavel Pisa2016-07-042-2/+9
| | | | | Some/many Cortex-A cores have data cache line length 64 bytes and maximum value has to be used for system structures alignment.
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