diff options
| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-10-04 23:30:22 +0200 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-10-04 23:30:22 +0200 |
| commit | 8714684129e69b6bec7ca56b4e4243854208a976 (patch) | |
| tree | d294584bac689d634dc31ea981754c96515bfb29 | |
| parent | libdl/rtl-obj.c: synchronize cache should not depend on CPU_CACHE_LINE_BYTES. (diff) | |
| download | rtems-8714684129e69b6bec7ca56b4e4243854208a976.tar.bz2 | |
score/arm: Correct logic to select 64 byte cache line maximum size for Cortex-A.
The use of actual cache line max bytes and minimum required alignment
in architecture but not-BSP dependent code could be problematic
because there exists even ARM instruction set implementations
with 128 byte line length and real maximum can be quite problematic
to say. But actually supported ARM BSPs should be OK with these values.
| -rw-r--r-- | cpukit/score/cpu/arm/rtems/score/cpu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h index 9fe28c4a3f..4cdca73838 100644 --- a/cpukit/score/cpu/arm/rtems/score/cpu.h +++ b/cpukit/score/cpu/arm/rtems/score/cpu.h @@ -146,9 +146,9 @@ #define CPU_STACK_GROWS_UP FALSE #if defined(ARM_MULTILIB_CACHE_LINE_MAX_64) - #define CPU_CACHE_LINE_BYTES 32 -#else #define CPU_CACHE_LINE_BYTES 64 +#else + #define CPU_CACHE_LINE_BYTES 32 #endif #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |