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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-07-03 09:30:20 +0200 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-07-04 15:55:57 +0200 |
| commit | abea02a832a2693b01e77bca91ea3c98ee149e92 (patch) | |
| tree | d0651989303d1eb2a66b76b784902a8ee485b849 | |
| parent | rtems+bsps/cache: Define cache manager operations for code synchronization an... (diff) | |
| download | rtems-abea02a832a2693b01e77bca91ea3c98ee149e92.tar.bz2 | |
bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.
| -rw-r--r-- | c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h index 35c80026d4..e83b55cfa6 100644 --- a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h +++ b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h @@ -72,6 +72,10 @@ extern "C" { /* These two defines also ensure that the rtems_cache_* functions have bodies */ #define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT #define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT +#if defined(__ARM_ARCH_7A__) +/* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */ +#define CPU_MAXIMAL_CACHE_ALIGNMENT 64 +#endif #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \ ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS |