summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--cpukit/score/cpu/epiphany/include/rtems/score/cpu.h15
-rw-r--r--cpukit/score/cpu/or1k/include/rtems/score/cpu.h15
-rw-r--r--cpukit/score/cpu/riscv/include/rtems/score/cpu.h4
3 files changed, 0 insertions, 34 deletions
diff --git a/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h b/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h
index 9167c09..eaedc31 100644
--- a/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h
@@ -187,21 +187,6 @@ extern "C" {
#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
/*
- * Define what is required to specify how the network to host conversion
- * routines are handled.
- *
- * epiphany Specific Information:
- *
- * This version of RTEMS is designed specifically to run with
- * big endian architectures. If you want little endian, you'll
- * have to make the appropriate adjustments here and write
- * efficient routines for byte swapping. The epiphany architecture
- * doesn't do this very well.
- */
-
-#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
-
-/*
* The following defines the number of bits actually used in the
* interrupt field of the task mode. How those bits map to the
* CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
index bd1b6bc..333bdf8 100644
--- a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
@@ -179,21 +179,6 @@ extern "C" {
#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
/*
- * Define what is required to specify how the network to host conversion
- * routines are handled.
- *
- * Or1k Specific Information:
- *
- * This version of RTEMS is designed specifically to run with
- * big endian architectures. If you want little endian, you'll
- * have to make the appropriate adjustments here and write
- * efficient routines for byte swapping. The Or1k architecture
- * doesn't do this very well.
- */
-
-#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
-
-/*
* The following defines the number of bits actually used in the
* interrupt field of the task mode. How those bits map to the
* CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index f84395c..ab13cb6 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -45,9 +45,6 @@ extern "C" {
#define RISCV_MSTATUS_MIE 0x8
-#define CPU_INLINE_ENABLE_DISPATCH FALSE
-#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
-
#define CPU_ISR_PASSES_FRAME_POINTER FALSE
#define CPU_HARDWARE_FP FALSE
@@ -59,7 +56,6 @@ extern "C" {
#define CPU_STACK_GROWS_UP FALSE
#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64)))
-#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
#define CPU_BIG_ENDIAN FALSE
#define CPU_LITTLE_ENDIAN TRUE
#define CPU_MODES_INTERRUPT_MASK 0x0000000000000001