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* DOSFS - LENGHT -> LENGTHJoel Sherrill2016-07-124-6/+6
| | | | closes #2756,
* bsps/powerpc: Fix AltiVec enableSebastian Huber2016-07-123-0/+3
| | | | | There must be an isync after the mtmsr to ensure that the AltiVec is enabled for subsequent instructions.
* score: Postpone SMP shutdown in _Terminate()Sebastian Huber2016-07-063-25/+24
| | | | | This enables fatal extensions to continue program execution after some fatal errors.
* score: Do not disable ISR in _Terminate()Sebastian Huber2016-07-062-9/+1
| | | | | | | This partially reverts 38ee75853f674977609bd078c69fb53420afdd08. Let the calling context decide if interrupts must be disabled or not. The goal is to enable fatal extensions to continue program execution after some fatal errors.
* Config (.cfg) files are only valid if deeper than 5.Chris Johns2016-07-061-1/+1
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* rtems-bsps: Update 4.11 to 4.12Joel Sherrill2016-07-051-1/+1
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* shared/console-polled.c: Use standard fatal error codesJoel Sherrill2016-07-051-3/+3
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* bsps/arm: Fix basic cache support for SMPSebastian Huber2016-07-051-8/+8
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* Beaglebone: Update PWM driver imported from BBBIOPunit Vara2016-07-044-386/+611
| | | | | | This patch adapts the previously added Beaglebone PWM code from BBBIO to RTEMS. This work was done in the context of the Google Summer of Code 2016, and further patches will follow to improve the code quality and documentation.
* Beaglebone: Add original BBBIO PWM driverPunit Vara2016-07-042-0/+448
| | | | | | | | | This patch adds the PWM driver code for the Beaglebone Black from BBBIO: https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.c This commit is for tracking purposes only; the next commit will adapt the code for RTEMS.
* bsps/arm: basic on core cache support changed to use l1 functions.Pavel Pisa2016-07-043-48/+97
| | | | | | | | | | | | | | The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem.
* libdl/rtl-obj.c: ensure that loaded code is synchronized through caches.Pavel Pisa2016-07-041-0/+2
| | | | | | | | | | | | Synchronize each cluster of sections of the same type separately to support even cases where text and data are allocated from different areas (for example due allocation from different MPU protection regions). rtems_cache_instruction_sync_after_code_change is called even to data sections. Propagation of data only changes should not require cache maintenance operation on sane SMP mutithread capable systems if barrier instruction is added but be on safe side even for case where self modifying code uses data sections initial values etc.
* bsps/arm: Change code to explicit selection of cache implementation for ARM ↵Pavel Pisa2016-07-0410-124/+190
| | | | | | | | | | | | | | | | | | | | | | | BSPs. The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support
* bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.Pavel Pisa2016-07-041-0/+4
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* rtems+bsps/cache: Define cache manager operations for code synchronization ↵Pavel Pisa2016-07-043-1/+72
| | | | | | | | | | | | | | and maximal alignment. There is need for unambiguous named and defined cache function which should be called when code is updated, loaded or is self-modifying. There should be function to obtain maximal cache line length as well. This function can and should be used for allocations which can be used for data and or code and ensures that there are no partial cache lines overlaps on start and end of allocated region.
* arm/raspberrypi: update VideoCore cache flush workaround to work on RPi2.Pavel Pisa2016-07-041-2/+13
| | | | | The arm_cp15_data_cache_clean_and_invalidate leads to hang on RPi2, clean by individual lines works on RPi1 and RPi2.
* score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib.Pavel Pisa2016-07-042-2/+9
| | | | | Some/many Cortex-A cores have data cache line length 64 bytes and maximum value has to be used for system structures alignment.
* arm/raspberrypi: Enable HYP to SVC switch for this BSP.Pavel Pisa2016-07-042-0/+7
| | | | | This support is required when newer firmware is used on Raspberry Pi 2 boards.
* bsps/arm: Support recent bootloaders starting kernel in HYP modePavel Pisa2016-07-045-7/+175
| | | | | | | | | | | | | | | | | | | When HYP mode is detected at startup then setup HYP mode vectors table (for future extensions) clean exceptions switching to HYP mode and switch CPU to ARM SVC mode. BSPs which want to use this support need to include next option in their configure.ac RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1]) RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode]) AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" = "1") and need to include next lines in corresponding Makefile.am if BSP_START_IN_HYP_SUPPORT libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S endif
* arm/score and shared: define ARM hypervisor mode and alternate vector table ↵Pavel Pisa2016-07-042-0/+31
| | | | | | | | | base access. The main reason for inclusion of minimum hypervisor related defines is that current ARM boards firmware and loaders (U-boot for example) start loaded operating system kernel in HYP mode to allow it take control of virtualization (Linux/KVM for example).
* bsp/atsam: Add RTC driverAlexander Krutwig2016-07-042-1/+104
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* libchip: Simplify RTC driverSebastian Huber2016-07-0414-39/+13
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* net: Fix byte order issue for getnameinfo()Sebastian Huber2016-07-012-15/+13
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* score: Change scheduler node init and destroySebastian Huber2016-07-0123-64/+107
| | | | | | Provide the scheduler node to initialize or destroy to the corresponding operations. This makes it possible to have more than one scheduler node per thread.
* score: Fix MPCI message layoutSebastian Huber2016-07-011-1/+1
| | | | | | | | Restore the 32-bit priority field in MP_packet_Prefix. Bug introduced by 254dc82daf8cbd6922376fcbb81c31e21cbf4d16. Close #2750.
* rtems: Fix rtems_task_set_scheduler() APISebastian Huber2016-07-0113-102/+306
| | | | | | | | | | | Task priorities are only valid within a scheduler instance. The rtems_task_set_scheduler() directive moves a task from one scheduler instance to another using the current priority of the thread. However, the current task priority of the source scheduler instance is undefined in the target scheduler instance. Add a third parameter to specify the priority. Close #2749.
* score: Workaround for #2751Sebastian Huber2016-07-011-0/+4
| | | | | | | | | | | | | | | The ARM and PowerPC interrupt epilogues call _Thread_Dispatch() with interrupts disabled (counter example: SPARC). On SMP configurations, since inter-processor interrupts set the thread dispatch necessary indicator this prevents a thread dispatch notification in post-switch handlers (which all run with interrupts disabled). On all configurations, this is a serious issue for the interrupt latency. Update #2751
* score: Next try to fix thread lock on SMPSebastian Huber2016-07-011-6/+16
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* score: Fix priority affinity SMP schedulerSebastian Huber2016-07-011-2/+10
| | | | Bug introduced by 9bfad8cd519f17cbb26a672868169fcd304d5bd5.
* smptests/smpstrongapa01: SimplifySebastian Huber2016-06-301-5/+1
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* smptests/smpstrongapa01: Add test casesSebastian Huber2016-06-301-3/+300
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* bsps: Do not use fast idle clock for SMPSebastian Huber2016-06-301-13/+15
| | | | | We may have more than one idle thread. Thus, the clock driver fast idle logic would be a bit more complicated.
* score: Strong APA scheduler processor allocationSebastian Huber2016-06-303-24/+24
| | | | | Use _Scheduler_SMP_Allocate_processor_exact() to prevent unexpected migrations.
* score: Avoid atomic fences for thread wait flagsSebastian Huber2016-06-307-34/+37
| | | | | The use of atomic fences is brittle and may break due to changes in different areas which is hard to manage.
* score: Fix thread lock on SMP configurationsSebastian Huber2016-06-304-12/+46
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* score: _CPU_SMP_Send_interrupt() documentationSebastian Huber2016-06-291-4/+0
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* bsp/atsam: Add support for TCMAlexander Krutwig2016-06-295-0/+150
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* score: Fix SMP message handlingSebastian Huber2016-06-297-34/+37
| | | | | | | | According to the C11 standard only atomic read-modify-write operations guarantee that the last value written in modification order is read, see "7.17.3 Order and consistency". Thus we must use a read-modify-write in _SMP_Inter_processor_interrupt_handler() to make sure we read an up-to-date message.
* arm/raspberrypi: resolve BSP warnings.Pavel Pisa2016-06-285-2/+8
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* arm/raspberrypi: run VideoCore and mailbox code through rtems.uncrustify.Pavel Pisa2016-06-285-246/+266
| | | | | | Some changes have been reverted to keep readability. For example squash of BCM2835_MBOX_TAG_* defines which are visually aligned in column.
* arm/raspberrypi: Adding functionalities to Mailbox RPiMudit Jain2016-06-283-0/+99
| | | | | Added functions for retrieving firmware revision, board model and board revision.
* bsp/mvme162: Include missing <rtems/bspIo.h>Sebastian Huber2016-06-281-0/+1
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* libnetworking: Import current <sys/socket.h>Christian Mauderer2016-06-281-73/+373
| | | | | Import the <sys/socket.h> from current FreeBSD. This allows to build some current software (e.g. libressl).
* libnetworking: Move RTEMS-specific socket wake-upSebastian Huber2016-06-283-15/+18
| | | | Close #2748.
* libnetworking: Hide SO_PRIVSTATEChristian Mauderer2016-06-282-1/+7
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* libnetworking: Add <machine/_align.h>Christian Mauderer2016-06-283-1/+29
| | | | This is necessary for new <sys/socket.h>.
* libnetworking: Import current <arpa/inet.h>Christian Mauderer2016-06-2816-46/+73
| | | | | | | | | | Import the <arpa/inet.h> from current FreeBSD. Necessary due to changes in <netinet/in.h>. Remove BSD hack from <arpa/inet.h>. Clean up problems with htonl(). These functions are defined in <arpa/inet.h>. This lead to some problems because they are defined in <rtems/endian.h> too. Add NTOHL, ... to <rtems/rtems_bsdnet_internal.h>.
* libnetworking: Import current <netinet/in.h>Christian Mauderer2016-06-2818-135/+443
| | | | | | | | | | | | | | | | Import the <netinet/in.h> from current FreeBSD. This allows to build some current software (e.g. libressl). Add legacy support like * prototype for in_cksum(), * IPPORT_USERRESERVED, * deprecated IPCTL_RT* defines, * ip_fw_chk_t and ip_fw_ctl_t, * ip_nat_... (IP NAT hooks), and * IP_NAT option for get/setsockopt() to new <rtems/rtems_netinet_in.h>.
* libnetworking: Import current <netinet6/in6.h>Christian Mauderer2016-06-283-0/+760
| | | | | Import the <netinet6/in6.h> from current FreeBSD. This allows to build some current software (e.g. libressl).
* libnetworking: Import <sys/_sockaddr_storage.h>Christian Mauderer2016-06-283-1/+60
| | | | | Import the <sys/_sockaddr_storage.h> from current FreeBSD. Necessary for <netinet/in.h> update.
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