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authorPunit Vara <punitvara@gmail.com>2016-07-04 18:05:43 (UTC)
committerMartin Galvan <martin.galvan@tallertechnologies.com>2016-07-04 18:09:06 (UTC)
commit5e3096db5a1d766ece4068fbfe625c8a3db31b23 (patch)
treeba4c87be0e05ac62e5474a3ccb0d2412ce965ffe
parent6dc5c03fad3ddd51423d21b5d60d24b62bb653e9 (diff)
downloadrtems-5e3096db5a1d766ece4068fbfe625c8a3db31b23.tar.bz2
Beaglebone: Update PWM driver imported from BBBIO
This patch adapts the previously added Beaglebone PWM code from BBBIO to RTEMS. This work was done in the context of the Google Summer of Code 2016, and further patches will follow to improve the code quality and documentation.
-rw-r--r--c/src/lib/libbsp/arm/beagle/Makefile.am4
-rw-r--r--c/src/lib/libbsp/arm/beagle/include/bbb-pwm.h162
-rw-r--r--c/src/lib/libbsp/arm/beagle/pwm/pwm.c734
-rw-r--r--c/src/lib/libcpu/arm/shared/include/am335x.h97
4 files changed, 611 insertions, 386 deletions
diff --git a/c/src/lib/libbsp/arm/beagle/Makefile.am b/c/src/lib/libbsp/arm/beagle/Makefile.am
index 904cb84..aa28f36 100644
--- a/c/src/lib/libbsp/arm/beagle/Makefile.am
+++ b/c/src/lib/libbsp/arm/beagle/Makefile.am
@@ -41,6 +41,7 @@ include_bsp_HEADERS += include/irq.h
include_bsp_HEADERS += include/i2c.h
include_bsp_HEADERS += include/beagleboneblack.h
include_bsp_HEADERS += include/bbb-gpio.h
+include_bsp_HEADERS += include/bbb-pwm.h
include_libcpu_HEADERS =
include_libcpu_HEADERS += ../../../libcpu/arm/shared/include/arm-cp15.h
@@ -117,6 +118,9 @@ libbsp_a_SOURCES += misc/i2c.c
# GPIO
libbsp_a_SOURCES += gpio/bbb-gpio.c
+#pwm
+libbsp_a_SOURCES += pwm/pwm.c
+
#RTC
libbsp_a_SOURCES += rtc.c
libbsp_a_SOURCES += ../../shared/tod.c
diff --git a/c/src/lib/libbsp/arm/beagle/include/bbb-pwm.h b/c/src/lib/libbsp/arm/beagle/include/bbb-pwm.h
index 761eae2..ef016f0 100644
--- a/c/src/lib/libbsp/arm/beagle/include/bbb-pwm.h
+++ b/c/src/lib/libbsp/arm/beagle/include/bbb-pwm.h
@@ -1,3 +1,23 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief BeagleBone Black BSP definitions.
+ */
+
+/**
+ * Copyright (c) 2016 Punit Vara <punitvara at gmail.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+/** Some constants are taken from
+ * https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.h
+ */
+
#ifndef LIBBSP_ARM_BEAGLE_BBB_PWM_H
#define LIBBSP_ARM_BEAGLE_BBB_PWM_H
@@ -8,31 +28,125 @@ extern "C" {
/**
* @brief BeagleBone Black PWM Macros.
*/
-#define BBBIO_PWMSS_COUNT 3
-#define BBBIO_PWMSS0 0
-#define BBBIO_PWMSS1 1
-#define BBBIO_PWMSS2 2
-
-#define MUXMODE0 0
-#define MUXMODE1 1
-#define MUXMODE2 2
-#define MUXMODE3 3
-#define MUXMODE4 4
-#define MUXMODE5 5
-#define MUXMODE6 6
-#define MUXMODE7 7
-
-#define EPWM_GROUP1 1
-#define EPWM_GROUP2 2
-#define EPWM_GROUP0 0
-
-int BBBIO_PWMSS_Setting(unsigned int PWMID , float HZ ,float dutyA ,float dutyB);
-int BBBIO_PWM_Init();
-void BBBIO_PWM_Release();
-int BBBIO_PWMSS_Status(unsigned int PWMID);
-void BBBIO_ehrPWM_Enable(unsigned int PWMSS_ID);
-void BBBIO_ehrPWM_Disable(unsigned int PWMSS_ID);
+#define BBB_CONTROL_CONF_GPMC_AD(n) (0x800 + (n * 4))
+#define BBB_CONTROL_CONF_LCD_DATA(n) (0x8a0 + (n * 4))
+
+#define BBB_PWMSS_COUNT 3
+#define BBB_PWMSS0 0
+#define BBB_PWMSS1 1
+#define BBB_PWMSS2 2
+
+#define BBB_P8_13_2B 3
+#define BBB_P8_19_2A 4
+#define BBB_P8_45_2A 5
+#define BBB_P8_46_2B 6
+#define BBB_P8_34_1B 7
+#define BBB_P8_36_1A 8
+#define BBB_P9_14_1A 9
+#define BBB_P9_16_1B 10
+#define BBB_P9_21_0B 11
+#define BBB_P9_22_0A 12
+#define BBB_P9_29_0B 13
+#define BBB_P9_31_0A 14
+
+#define BBB_MUX0 0
+#define BBB_MUX1 1
+#define BBB_MUX2 2
+#define BBB_MUX3 3
+#define BBB_MUX4 4
+#define BBB_MUX5 5
+#define BBB_MUX6 6
+#define BBB_MUX7 7
+
+#define BBB_EPWM1 1
+#define BBB_EPWM2 2
+#define BBB_EPWM0 0
+
+/**
+ * @brief BeagleBone Black PWM API.
+ */
+
+/**
+ * @brief This function intilize clock and pinmuxing for pwm sub system.
+ *
+ * @param PWMSS_ID It is the instance number of EPWM of pwm sub system.
+ *
+ * @return true if successful
+ * @return false if not successful
+ *
+ **/
+bool beagle_pwm_init(uint32_t pwmss_id);
+
+/* PWMSS setting
+ * set pulse argument of epwm module
+ *
+ * @param pwm_id : EPWMSS number , 0~2
+ * @param pwm_freq : frequency to be generated
+ * @param dutyA : Duty Cycle in ePWM A
+ * @param dutyB : Duty Cycle in ePWM B
+ *
+ * @return : 1 for success
+ * @return : 0 for failed
+ *
+ * @example : PWMSS_Setting(0 , 50.0f , 50.0f , 25.0f); // Generate 50HZ pwm in PWM0 ,
+ * // duty cycle is 50% for ePWM0A , 25% for ePWM0B
+ *
+ * @Note :
+ * find an number nearst 65535 for TBPRD , to improve duty precision,
+ *
+ * Using big TBPRD can increase the range of CMPA and CMPB ,
+ * and it means we can get better precision on duty cycle.
+ *
+ * EX : 20.25% duty cycle
+ * on TBPRD = 62500 , CMPA = 12656.25 ( .25 rejection) , real duty : 20.2496% (12656 /62500)
+ * on TBPRD = 6250 , CMPA = 1265.625 ( .625 rejection), real duty : 20.24% (1265 6250)
+ * on TBPRD = 500 , CMPA = 101.25 ( .25 rejection) , real duty : 20.2% (101/500)
+ *
+ * Divisor = CLKDIV * HSPCLKDIV
+ * 1 TBPRD : 10 ns (default)
+ * 65535 TBPRD : 655350 ns
+ * 65535 TBPRD : 655350 * Divisor ns = X TBPRD : Cyclens
+ *
+ * accrooding to that , we must find a Divisor value , let X nearest 65535 .
+ * so , Divisor must Nearest Cyclens/655350
+ */
+int beagle_pwmss_setting(uint32_t pwm_id, float pwm_freq, float dutyA, float dutyB);
+
+/**
+ * @brief This API enables the particular PWM module.
+ *
+ * @param pwmid It is the instance number of EPWM of pwm sub system.
+ *
+ * @return true if successful
+ * @return false if fail
+ *
+ **/
+bool beagle_ehrpwm_enable(uint32_t pwmid);
+/**
+ * @brief This API disables the HR sub-module.
+ *
+ * @param pwmid It is the instance number of EPWM of pwm sub system.
+ *
+ * @return true if successful
+ * @return false if fail
+ *
+ **/
+bool beagle_ehrpwm_disable(uint32_t pwmid);
+
+/**
+ * @brief This function Enables pinmuxing for PWM module.
+ *
+ * @param pin_no It is individual pin at which freuqency need to be generated.
+ * It should be according to pwm sub system.
+ *
+ * @param pwm_id It is the instance number of EPWM of pwmsubsystem.
+ *
+ * @return true if successful
+ * @return false if fail
+ *
+ **/
+bool beagle_epwm_pinmux_setup(uint32_t pin_no, uint32_t pwm_id);
#ifdef __cplusplus
}
diff --git a/c/src/lib/libbsp/arm/beagle/pwm/pwm.c b/c/src/lib/libbsp/arm/beagle/pwm/pwm.c
index 7586a82..3b9716e 100644
--- a/c/src/lib/libbsp/arm/beagle/pwm/pwm.c
+++ b/c/src/lib/libbsp/arm/beagle/pwm/pwm.c
@@ -1,407 +1,419 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <sys/mman.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <errno.h>
-#include <time.h>
-#include "BBBiolib.h"
-/*-----------------------------------------------------------------------------------------------*/
-/*
- * PWMSS Registers
- *
- * @Source : AM335x Technical Reference Manual ,page 1991
- * Table 15-5. PWMSS REGISTERS
- *
-*/
-
-#define PWMSS0_MMAP_ADDR 0x48300000
-#define PWMSS1_MMAP_ADDR 0x48302000
-#define PWMSS2_MMAP_ADDR 0x48304000
-#define PWMSS_MMAP_LEN 0x1000
-
-#define PWMSS_IDVER 0x0
-#define PWMSS_SYSCONFIG 0x4
-#define PWMSS_CLKCONFIG 0x8
-#define PWMSS_CLKSTATUS 0xC
-
-/* EPWM Registers
+/**
+ * @file
*
- * @Source : AM335x Technical Reference Manual ,page 2084
- * Table 15-58. EPWM REGISTERS
+ * @ingroup arm_beagle
*
-*/
-#define EPWM_TBCTL 0x0
-#define EPWM_TBSTS 0x2
-#define EPWM_TBPHSHR 0x4
-#define EPWM_TBPHS 0x6
-#define EPWM_TBCNT 0x8
-#define EPWM_TBPRD 0xA
-#define EPWM_CMPCTL 0xE
-#define EPWM_CMPAHR 0x10
-#define EPWM_CMPA 0x12
-#define EPWM_CMPB 0x14
-#define EPWM_AQCTLA 0x16
-#define EPWM_AQCTLB 0x18
-#define EPWM_AQSFRC 0x1A
-#define EPWM_AQCSFRC 0x1C
-#define EPWM_DBCTL 0x1E
-#define EPWM_DBRED 0x20
-#define EPWM_DBFED 0x22
-/*-----------------------------------------------------------------------------------------------*/
-extern int memh;
-extern volatile unsigned int *CM_ptr; /*c ontrol module */
-volatile unsigned int *cm_per_addr;
-
-
-const unsigned int PWMSS_AddressOffset[]={PWMSS0_MMAP_ADDR,
- PWMSS1_MMAP_ADDR,
- PWMSS2_MMAP_ADDR};
-volatile unsigned int *pwmss_ptr[3] ={NULL, NULL, NULL} ;
-volatile unsigned int *epwm_ptr[3] ={NULL, NULL, NULL} ;
-volatile unsigned int *ecap_ptr[3] ={NULL, NULL, NULL} ;
-volatile unsigned int *eqep_ptr[3] ={NULL, NULL, NULL} ;
+ * @brief Support for PWM for the BeagleBone Black.
+ */
-#define TBCTL_CTRMODE_UP 0x0
-#define TBCTL_CTRMODE_DOWN 0x1
-#define TBCTL_CTRMODE_UPDOWN 0x2
-#define TBCTL_CTRMODE_FREEZE 0x3
-/* ----------------------------------------------------------------------------------------------- */
-/* PWMSS Timebase clock check
- * check the timenase clock enable or not
+/**
+ * Copyright (c) 2016 Punit Vara <punitvara at gmail.com>
*
- * @param PWMSS_ID : PWM sumsystem ID (BBBIO_PWMSS0 ,BBBIO_PWMSS1, BBBIO_PWMSS2)
- *
- * @return : 0 for disable timebase clock , 1 for enable for timebase clock
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
*/
-static int PWMSS_TB_clock_check(unsigned int PWMSS_ID)
-{
- volatile unsigned int* reg;
- unsigned int reg_value ;
- /* Control module check */
- reg =(void *)CM_ptr + BBBIO_PWMSS_CTRL;
- reg_value = *reg ;
-
- return (reg_value & (1 << PWMSS_ID)) ;
-}
+/** This file is based on
+ * https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.c
+ */
-/* ----------------------------------------------------------------------------------------------- */
-/* PWM subsystem system control
- * enable or disable module clock
- *
- * @param PWMSS_ID : PWM sumsystem ID (BBBIO_PWMSS0 ,BBBIO_PWMSS1, BBBIO_PWMSS2).
- * @param enable : 0 for disable , else for enable .
- *
- * @return : 1 for success , 0 for error
+#include <libcpu/am335x.h>
+#include <stdio.h>
+#include <bsp/gpio.h>
+#include <bsp/bbb-gpio.h>
+#include <bsp.h>
+#include <bsp/bbb-pwm.h>
+
+/* Currently these definitions are for BeagleBone Black board only
+ * Later on Beagle-xM board support can be added in this code.
+ * After support gets added if condition should be removed
*/
-static int PWMSS_module_ctrl(unsigned int PWMSS_ID, int enable)
-{
- volatile unsigned int *reg = NULL;
- unsigned int module_set[] = {BBBIO_PWMSS0, BBBIO_PWMSS1, BBBIO_PWMSS2};
- unsigned int module_clk_set[] = {BBBIO_CM_PER_EPWMSS0_CLKCTRL, BBBIO_CM_PER_EPWMSS1_CLKCTRL, BBBIO_CM_PER_EPWMSS2_CLKCTRL};
- int ret = 1;
+#if IS_AM335X
- reg = (void*)cm_per_addr + module_clk_set[PWMSS_ID];
- if(enable) {
- if(PWMSS_TB_clock_check(module_set[PWMSS_ID])) {
- /* Enable module clock */
- *reg = 0x2; /* Module enable and fully functional */
- return ret;
- }
-#ifdef BBBIO_LIB_DBG
- else {
- printf("PWMSS_module_ctrl : PWMSS-%d timebase clock disable in Control Module\n", PWMSS_ID);
- }
-#endif
- ret = 0 ;
+/*
+ * @brief This function select PWM module to be enabled
+ *
+ * @param pwm_id It is the instance number of EPWM of pwm sub system.
+ *
+ * @return Base Address of respective pwm instant.
+*/
+static uint32_t select_pwmss(uint32_t pwm_id)
+{
+uint32_t baseAddr=0;
+ if (pwm_id == BBB_PWMSS0)
+ {
+ baseAddr = AM335X_EPWM_0_REGS;
+ return baseAddr;
+ }
+ else if (pwm_id == BBB_PWMSS1)
+ {
+ baseAddr = AM335X_EPWM_1_REGS;
+ return baseAddr;
+ }
+ else if (pwm_id == BBB_PWMSS2)
+ {
+ baseAddr = AM335X_EPWM_2_REGS;
+ return baseAddr;
+ }
+ else
+ {
+ printf("Invalid PWM Id\n");
+ return 0;
}
- *reg = 0x3 << 16; /* Module is disabled and cannot be accessed */
- return ret;
}
-/* ----------------------------------------------------------------------------------------------- */
-/* PWM init
- * iolib_init will run this function automatically
- *
- * @return : 1 for success , 0 for failed
- */
-
-int BBBIO_PWM_Init()
+bool beagle_epwm_pinmux_setup(uint32_t pin_no, uint32_t pwm_id)
{
- int i = 0;
-
- if (memh == 0) {
-#ifdef BBBIO_LIB_DBG
- printf("BBBIO_PWM_Init: memory not mapped?\n");
-#endif
- return 0;
- }
-
- /* Create Memory map */
- for (i = 0 ; i < 3 ; i ++) {
- pwmss_ptr[i] = mmap(0, PWMSS_MMAP_LEN, PROT_READ | PROT_WRITE, MAP_SHARED, memh, PWMSS_AddressOffset[i]);
- if(pwmss_ptr[i] == MAP_FAILED) {
-#ifdef BBBIO_LIB_DBG
- printf("BBBIO_PWM_Init: PWMSS %d mmap failure!\n", i);
-#endif
- goto INIT_ERROR ;
- }
- ecap_ptr[i] = (void *)pwmss_ptr[i] + 0x100 ;
- eqep_ptr[i] = (void *)pwmss_ptr[i] + 0x180 ;
- epwm_ptr[i] = (void *)pwmss_ptr[i] + 0x200 ;
-
- if(!PWMSS_module_ctrl(i, 1)) {
-#ifdef BBBIO_LIB_DBG
- printf("BBBIO_PWM_Init: PWMSS %d clock failure!\n", i);
-#endif
- goto INIT_ERROR ;
+ switch(pwm_id) {
+ case BBB_PWMSS2:
+ switch(pin_no) {
+ case BBB_P8_13_2B:
+ REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(9)) = BBB_MUXMODE(BBB_MUX4);
+ break;
+ case BBB_P8_19_2A:
+ REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(8)) = BBB_MUXMODE(BBB_MUX4);
+ break;
+ case BBB_P8_45_2A:
+ REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(0)) = BBB_MUXMODE(BBB_MUX3);
+ break;
+ case BBB_P8_46_2B:
+ REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(1)) = BBB_MUXMODE(BBB_MUX3);
+ break;
+ default :
+ printf("Invalid pin for module 2\n");
+ return false;
}
+ break;
+ case BBB_PWMSS1:
+ switch(pin_no) {
+ case BBB_P8_34_1B:
+ REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(11)) = BBB_MUXMODE(BBB_MUX2);
+ break;
+ case BBB_P8_36_1A:
+ REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(10)) = BBB_MUXMODE(BBB_MUX2);
+ break;
+ case BBB_P9_14_1A:
+ REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(2)) = BBB_MUXMODE(BBB_MUX6);
+ break;
+ case BBB_P9_16_1B:
+ REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(3)) = BBB_MUXMODE(BBB_MUX6);
+ break;
+ default :
+ printf("Invalid pin for module 1\n");
+ return false;
+ }
+ break;
+ case BBB_PWMSS0:
+ switch(pin_no) {
+ case BBB_P9_21_0B:
+ REG(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_D0) = BBB_MUXMODE(BBB_MUX3);
+ break;
+ case BBB_P9_22_0A:
+ REG(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_SCLK) = BBB_MUXMODE(BBB_MUX3);
+ break;
+ case BBB_P9_29_0B:
+ REG(AM335X_PADCONF_BASE + AM335X_CONF_MCASP0_FSX) = BBB_MUXMODE(BBB_MUX1);
+ break;
+ case BBB_P9_31_0A:
+ REG(AM335X_PADCONF_BASE + AM335X_CONF_MCASP0_ACLKX) = BBB_MUXMODE(BBB_MUX1);
+ break;
+ default:
+ printf("Invalid pin for module 0\n");
+ return false;
}
- return 1;
-
-INIT_ERROR :
- BBBIO_PWM_Release();
- return 0;
+ break;
+
+ default:
+ printf("Invalid PWM sub system\n");
+ return false;
}
-
-/* ----------------------------------------------------------------------------------------------- */
-void BBBIO_PWM_Release()
-{
- int i = 0;
- for(i = 0 ; i < 3 ; i ++) {
- if(pwmss_ptr[i] != NULL) {
- munmap((void *)pwmss_ptr[i], PWMSS_MMAP_LEN);
- pwmss_ptr[i] = NULL;
- ecap_ptr[i] = NULL;
- eqep_ptr[i] = NULL;
- epwm_ptr[i] = NULL;
- }
- }
}
-/* ----------------------------------------------------------------------------------------------- */
-/* PWMSS status (no effect now)
- * set pluse rgument of epwm module
+/**
+ * @brief This function Enables TBCLK(Time Base Clock) for specific
+ * EPWM instance of pwmsubsystem.
*
- * @param PWMID : EPWMSS number , 0~3
+ * @param instance It is the instance number of EPWM of pwmsubsystem.
*
- * @return : 1 for success , 0 for failed
- */
-int BBBIO_PWMSS_Status(unsigned int PWMID)
+ * @return true if successful
+ **/
+static bool pwmss_tbclk_enable(unsigned int instance)
{
- int param_error = 1;
- volatile unsigned int* reg;
- unsigned int reg_value ;
-
- if (memh == 0)
- param_error = 0;
-
- if (PWMID > 2) /* if input is not EPWMSS 0~ WPEMSS 2 */
- param_error = 0;
-
- if (param_error == 0) {
-#ifdef BBBIO_LIB_DBG
- printf("BBBIO_PWM_Status: parameter error!\n");
-#endif
- return 0;
- }
-
- reg =(void *)CM_ptr + BBBIO_PWMSS_CTRL;
-
- reg_value = *reg >> PWMID & 0x01 ;
- if(reg_value == 0) {
- printf("PWMSS [%d] Timebase clock Disable , Control Module [pwmss_ctrl register]\n", PWMID);
- }
- else {
- reg=(void *)pwmss_ptr[PWMID] + PWMSS_CLKSTATUS;
- reg_value = *reg ;
-
- printf("PWMSS [%d] :\tCLKSTOP_ACK %d , CLK_EN_ACK %d , CLKSTOP_ACK %d , CLK_EN_ACK %d , CLKSTOP_ACK %d , CLK_EN_ACK %d\n",
- PWMID ,
- reg_value >>9 & 0x1 ,
- reg_value >>8 & 0x1 ,
- reg_value >>5 & 0x1 ,
- reg_value >>4 & 0x1 ,
- reg_value >>1 & 0x1 ,
- reg_value >>0 & 0x1 );
- }
- return 1 ;
-}
-/* ----------------------------------------------------------------------------------------------- */
-/* PWMSS setting
- * set pluse rgument of epwm module
+uint32_t enable_bit;
+bool is_valid = true;
+
+ if (instance == BBB_PWMSS0)
+ {
+ enable_bit = AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN;
+ }
+ else if (instance == BBB_PWMSS1)
+ {
+ enable_bit = AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN;
+ }
+ else if (instance == BBB_PWMSS2)
+ {
+ enable_bit = AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN;
+ }
+ else
+ {
+ is_valid = false;
+ }
+
+ if (is_valid)
+ {
+ REG(AM335X_PADCONF_BASE + AM335X_PWMSS_CTRL) |= enable_bit;
+ }
+
+ return is_valid;
+ }
+
+/**
+ * @brief This functions enables clock for EHRPWM module in PWMSS subsystem.
*
- * @param PWMID : EPWMSS number , 0~2
- * @param HZ : pluse HZ
- * @param dutyA : Duty Cycle in ePWM A
- * @param dutyB : Duty Cycle in ePWM B
+ * @param pwm_id It is the instance number of EPWM of pwm sub system.
*
- * @return : 1 for success , 0 for failed
+ * @return None.
*
- * @example : BBBIO_PWMSS_Setting(0 , 50.0f , 50.0f , 25.0f); // Generate 50HZ pwm in PWM0 ,
- * // duty cycle is 50% for ePWM0A , 25% for ePWM0B
- *
- * @Note :
- * find an number nearst 65535 for TBPRD , to improve duty precision,
+ **/
+static void epwm_clock_enable(uint32_t pwm_id)
+{
+ if((pwm_id <3) && (pwm_id >=0)) {
+ uint32_t baseAddr;
+ baseAddr = select_pwmss(pwm_id);
+ REG(baseAddr - AM335X_EPWM_REGS + AM335X_PWMSS_CLKCONFIG) |= AM335X_PWMSS_CLK_EN_ACK;
+ } else {
+ printf("Invalid pwm_id\n");
+ }
+}
+
+/**
+ * @brief This function configures the L3 and L4_PER system clocks.
+ * It also configures the system clocks for the specified ePWMSS
+ * instance.
*
- * Using big TBPRD can increase the range of CMPA and CMPB ,
- * and it means we can get better precision on duty cycle.
+ * @param pwmss_id The instance number of ePWMSS whose system clocks
+ * have to be configured.
*
- * EX : 20.25% duty cycle
- * on TBPRD = 62500 , CMPA = 12656.25 ( .25 rejection) , real duty : 20.2496% (12656 /62500)
- * on TBPRD = 6250 , CMPA = 1265.625 ( .625 rejection), real duty : 20.24% (1265 6250)
- * on TBPRD = 500 , CMPA = 101.25 ( .25 rejection) , real duty : 20.2% (101/500)
+ * 'pwmss_id' can take one of the following values:
+ * (0 <= pwmss_id <= 2)
*
- * Divisor = CLKDIV * HSPCLKDIV
- * 1 TBPRD : 10 ns (default)
- * 65535 TBPRD : 655350 ns
- * 65535 TBPRD : 655350 * Divisor ns = X TBPRD : Cyclens
+ * @return None.
*
- * accrooding to that , we must find a Divisor value , let X nearest 65535 .
- * so , Divisor must Nearest Cyclens/655350
-*/
-
-int BBBIO_PWMSS_Setting(unsigned int PWMID , float HZ ,float dutyA ,float dutyB)
+ */
+static void module_clk_config(uint32_t pwmss_id)
{
- int param_error = 1;
- volatile unsigned short* reg16 ;
- if (memh == 0)
- param_error = 0;
- if (PWMID > 2) // if input is not EPWMSS 0~ WPEMSS 2
- param_error = 0;
- if (HZ < 0 )
- param_error = 0;
- if(dutyA < 0.0f || dutyA > 100.0f || dutyB < 0.0f || dutyB > 100.0f)
- param_error = 0;
-
- if (param_error == 0) {
-#ifdef BBBIO_LIB_DBG
- printf("BBBIO_PWMSS_Setting: parameter error!\n");
-#endif
- return 0;
+ if(pwmss_id == 0)
+ {
+ REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS0_CLKCTRL) |=
+ AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE;
+
+ while(AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE !=
+ (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS0_CLKCTRL) &
+ AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE));
+
+ while((AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC <<
+ AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT) !=
+ (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS0_CLKCTRL) &
+ AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST));
}
+ else if(pwmss_id == 1)
+ {
+ REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS1_CLKCTRL) |=
+ AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE;
+ while(AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE !=
+ (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS1_CLKCTRL) &
+ AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE));
+
+ while((AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC <<
+ AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT) !=
+ (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS1_CLKCTRL) &
+ AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST));
+ }
+ else if(pwmss_id == 2)
+ {
+ REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS2_CLKCTRL) |=
+ AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE;
+ while(AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE !=
+ (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS2_CLKCTRL) &
+ AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE));
+
+ while((AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC <<
+ AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT) !=
+ (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS2_CLKCTRL) &
+ AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST));
+ }
+ else
+ {
+ printf("Please enter valid pwm Id \n");
+ }
+}
- dutyA /= 100.0f ;
- dutyB /= 100.0f ;
-
- /* compute neccessary TBPRD */
- float Cyclens =0.0f ;
- float Divisor =0;
- int i , j ;
- const float CLKDIV_div[] = {1.0 ,2.0 ,4.0 ,8.0 ,16.0 ,32.0 , 64.0 , 128.0};
- const float HSPCLKDIV_div[] ={1.0 ,2.0 ,4.0 ,6.0 ,8.0 ,10.0 , 12.0 , 14.0};
- int NearCLKDIV =7;
- int NearHSPCLKDIV =7;
- int NearTBPRD =0;
-
- Cyclens = 1000000000.0f / HZ ; /* 10^9 / HZ , comput time per cycle (ns) */
-
-
- Divisor = (Cyclens / 655350.0f) ; /* am335x provide (128*14) divider , and per TBPRD means 10 ns when divider /1 ,
- * and max TBPRD is 65535 , so , the max cycle is 128*14* 65535 *10ns
- */
-#ifdef BBBIO_LIB_DBG
- printf("Cyclens %f , Divisor %f\n", Cyclens, Divisor);
-#endif
+bool beagle_pwm_init(uint32_t pwmss_id)
+{
+ bool status = true;
+ if((pwmss_id <3) && (pwmss_id >=0))
+ {
+ module_clk_config(pwmss_id);
+ epwm_clock_enable(pwmss_id);
+ pwmss_tbclk_enable(pwmss_id);
+ return status;
+ }
+ else {
+ status =false;
+ return status;
+ }
+}
- if(Divisor > (128 * 14)) {
-#ifdef BBBIO_LIB_DBG
- printf("BBBIO_PWMSS_Setting : Can't generate %f HZ \n", HZ);
-#endif
- return 0;
- }
- else {
- /* using Exhaustive Attack metho */
- for(i = 0 ; i < 8 ; i ++) {
- for(j = 0 ; j < 8 ; j ++) {
- if((CLKDIV_div[i] * HSPCLKDIV_div[j]) < (CLKDIV_div[NearCLKDIV] * HSPCLKDIV_div[NearHSPCLKDIV]) &&
- ((CLKDIV_div[i] * HSPCLKDIV_div[j]) > Divisor)) {
- NearCLKDIV = i ;
- NearHSPCLKDIV = j ;
- }
+int beagle_pwmss_setting(uint32_t pwm_id, float pwm_freq, float dutyA, float dutyB)
+{
+ uint32_t baseAddr;
+ int status = 1;
+
+ if(pwm_freq <= 0.5) {
+ status =0;
+ return status;
+ }
+ if(dutyA < 0.0f || dutyA > 100.0f || dutyB < 0.0f || dutyB > 100.0f) {
+ status = 0;
+ return status;
+ }
+ dutyA /= 100.0f;
+ dutyB /= 100.0f;
+
+ /*Compute necessary TBPRD*/
+ float Cyclens = 0.0f;
+ float Divisor =0;
+ int i,j;
+ const float CLKDIV_div[] = {1.0,2.0,4.0,8.0,16.0,32.0,64.0,128.0};
+ const float HSPCLKDIV_div[] = {1.0, 2.0, 4.0, 6.0, 8.0, 10.0,12.0, 14.0};
+ int NearCLKDIV =7;
+ int NearHSPCLKDIV =7;
+ int NearTBPRD =0;
+
+ /** 10^9 /Hz compute time per cycle (ns) */
+ Cyclens = 1000000000.0f / pwm_freq;
+
+ /** am335x provide (128* 14) divider and per TBPRD means 10ns when divider
+ * and max TBPRD is 65535 so max cycle is 128 * 8 * 14 * 65535 * 10ns */
+ Divisor = (Cyclens / 655350.0f);
+
+ if(Divisor > (128 * 14)) {
+ printf("Can't generate %f HZ",pwm_freq);
+ return 0;
+ }
+ else {
+ for (i=0;i<8;i++) {
+ for(j=0 ; j<8; j++) {
+ if((CLKDIV_div[i] * HSPCLKDIV_div[j]) < (CLKDIV_div[NearCLKDIV]
+ * HSPCLKDIV_div[NearHSPCLKDIV]) && (CLKDIV_div[i] * HSPCLKDIV_div[j] > Divisor)) {
+ NearCLKDIV = i;
+ NearHSPCLKDIV = j;
}
}
-#ifdef BBBIO_LIB_DBG
- printf("nearest CLKDIV %f , HSPCLKDIV %f\n" ,CLKDIV_div[NearCLKDIV] ,HSPCLKDIV_div[NearHSPCLKDIV]);
-#endif
- NearTBPRD = (Cyclens / (10.0 *CLKDIV_div[NearCLKDIV] *HSPCLKDIV_div[NearHSPCLKDIV])) ;
-
-#ifdef BBBIO_LIB_DBG
- printf("nearest TBPRD %d, %f %f\n ",NearTBPRD,NearTBPRD * dutyA, NearTBPRD * dutyB);
-#endif
-
- /* setting clock diver and freeze time base */
- reg16=(void*)epwm_ptr[PWMID] +EPWM_TBCTL;
- *reg16 = TBCTL_CTRMODE_FREEZE | (NearCLKDIV << 10) | (NearHSPCLKDIV << 7);
-
- /* setting duty A and duty B */
- reg16=(void*)epwm_ptr[PWMID] +EPWM_CMPB;
- *reg16 =(unsigned short)((float)NearTBPRD * dutyB);
-
- reg16=(void*)epwm_ptr[PWMID] +EPWM_CMPA;
- *reg16 =(unsigned short)((float)NearTBPRD * dutyA);
-
- reg16=(void*)epwm_ptr[PWMID] +EPWM_TBPRD;
- *reg16 =(unsigned short)NearTBPRD;
-
- /* reset time base counter */
- reg16 = (void *)epwm_ptr[PWMID] + EPWM_TBCNT;
- *reg16 = 0;
}
- return 1;
+ baseAddr = select_pwmss(pwm_id);
+ REG16(baseAddr + AM335X_EPWM_TBCTL) &= ~(AM335X_TBCTL_CLKDIV_MASK | AM335X_TBCTL_HSPCLKDIV_MASK);
+
+ REG16(baseAddr + AM335X_EPWM_TBCTL) = (REG16(baseAddr + AM335X_EPWM_TBCTL) &
+ (~AM335X_EPWM_TBCTL_CLKDIV)) | ((NearCLKDIV
+ << AM335X_EPWM_TBCTL_CLKDIV_SHIFT) & AM335X_EPWM_TBCTL_CLKDIV);
+
+ REG16(baseAddr + AM335X_EPWM_TBCTL) = (REG16(baseAddr + AM335X_EPWM_TBCTL) &
+ (~AM335X_EPWM_TBCTL_HSPCLKDIV)) | ((NearHSPCLKDIV <<
+ AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT) & AM335X_EPWM_TBCTL_HSPCLKDIV);
+
+ NearTBPRD = (Cyclens / (10.0 * CLKDIV_div[NearCLKDIV] * HSPCLKDIV_div[NearHSPCLKDIV]));
+
+ REG16(baseAddr + AM335X_EPWM_TBCTL) = (REG16(baseAddr + AM335X_EPWM_TBCTL) &
+ (~AM335X_EPWM_PRD_LOAD_SHADOW_MASK)) | (((bool)AM335X_EPWM_SHADOW_WRITE_DISABLE <<
+ AM335X_EPWM_TBCTL_PRDLD_SHIFT) & AM335X_EPWM_PRD_LOAD_SHADOW_MASK);
+
+ REG16(baseAddr + AM335X_EPWM_TBCTL) = (REG16(baseAddr + AM335X_EPWM_TBCTL) &
+ (~AM335X_EPWM_COUNTER_MODE_MASK)) | (((unsigned int)AM335X_EPWM_COUNT_UP <<
+ AM335X_TBCTL_CTRMODE_SHIFT) & AM335X_EPWM_COUNTER_MODE_MASK);
+
+ /*setting clock divider and freeze time base*/
+ REG16(baseAddr + AM335X_EPWM_CMPB) = (unsigned short)((float)(NearTBPRD) * dutyB);
+ REG16(baseAddr + AM335X_EPWM_CMPA) = (unsigned short)((float)(NearTBPRD) * dutyA);
+ REG16(baseAddr + AM335X_EPWM_TBPRD) = (unsigned short)NearTBPRD;
+ REG16(baseAddr + AM335X_EPWM_TBCNT) = 0;
+ }
+ return status;
}
-/* ----------------------------------------------------------------------------------------------- */
-/* Enable/Disable ehrPWM module
- * @param PWMID : PWMSS number , 0~2
- *
- * @return : void
- *
- * @example : BBBIO_PWMSS_Enable(0) ;// Enable PWMSS 0
- */
-void BBBIO_ehrPWM_Enable(unsigned int PWMSS_ID)
+bool beagle_ehrpwm_enable(uint32_t pwmid)
{
- volatile unsigned short *reg16 ;
-
- reg16=(void*)epwm_ptr[PWMSS_ID] +EPWM_AQCTLA;
- *reg16 = 0x2 | ( 0x3 << 4) ;
-
- reg16=(void*)epwm_ptr[PWMSS_ID] +EPWM_AQCTLB;
- *reg16 = 0x2 | ( 0x3 << 8) ;
-
- reg16 = (void *)epwm_ptr[PWMSS_ID] + EPWM_TBCNT;
- *reg16 = 0;
-
- reg16=(void *)epwm_ptr[PWMSS_ID] + EPWM_TBCTL;
- *reg16 &= ~0x3;
+ bool status = true;
+ uint32_t baseAddr;
+ if((pwmid<3) && (pwmid >=0)) {
+ baseAddr = select_pwmss(pwmid);
+ REG16(baseAddr + AM335X_EPWM_AQCTLA) = AM335X_EPWM_AQCTLA_ZRO_XAHIGH | (AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE << AM335X_EPWM_AQCTLA_CAU_SHIFT);
+ REG16(baseAddr + AM335X_EPWM_AQCTLB) = AM335X_EPWM_AQCTLB_ZRO_XBHIGH | (AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE << AM335X_EPWM_AQCTLB_CBU_SHIFT);
+ REG16(baseAddr + AM335X_EPWM_TBCNT) = 0;
+ REG16(baseAddr + AM335X_EPWM_TBCTL) |= AM335X_TBCTL_FREERUN | AM335X_TBCTL_CTRMODE_UP;
+ return status;
+ }
+ else {
+ status =false;
+ return status;
+ }
}
-void BBBIO_ehrPWM_Disable(unsigned int PWMSS_ID)
+bool beagle_ehrpwm_disable(uint32_t pwmid)
{
- volatile unsigned short *reg16 ;
- reg16=(void *)epwm_ptr[PWMSS_ID] + EPWM_TBCTL;
- *reg16 |= 0x3;
-
- reg16=(void*)epwm_ptr[PWMSS_ID] +EPWM_AQCTLA;
- *reg16 = 0x1 | ( 0x3 << 4) ;
-
- reg16=(void*)epwm_ptr[PWMSS_ID] +EPWM_AQCTLB;
- *reg16 = 0x1 | ( 0x3 << 8) ;
-
- reg16 = (void *)epwm_ptr[PWMSS_ID] + EPWM_TBCNT;
- *reg16 = 0;
+ bool status = true;
+ uint32_t baseAddr;
+ if((pwmid<3) && (pwmid >=0)) {
+ baseAddr = select_pwmss(pwmid);
+ REG16(baseAddr + AM335X_EPWM_TBCTL) = AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE;
+ REG16(baseAddr + AM335X_EPWM_AQCTLA) = AM335X_EPWM_AQCTLA_ZRO_XALOW | (AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE << AM335X_EPWM_AQCTLA_CAU_SHIFT);
+ REG16(baseAddr + AM335X_EPWM_AQCTLB) = AM335X_EPWM_AQCTLA_ZRO_XBLOW | (AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE << AM335X_EPWM_AQCTLB_CBU_SHIFT);
+ REG16(baseAddr + AM335X_EPWM_TBCNT) = 0;
+ return status;
+ }
+ else {
+ status = false;
+ return status;
+ }
}
-//--------------------------------------------------------
-
-
-
-
-
-
-
-
+#endif
+/* For support of BeagleboardxM */
+#if IS_DM3730
+/* Currently this section is just to satisfy
+ * GPIO API and to make the build successful.
+ * Later on support can be added here.
+ */
+uint32_t select_pwmss(uint32_t pwm_id)
+{
+return -1;
+}
+bool pwmss_tbclk_enable(unsigned int instance)
+{
+return false;
+}
+bool beagle_pwm_init(uint32_t pwmss_id)
+{
+return false;
+}
+bool beagle_ehrpwm_disable(uint32_t pwmid)
+{
+return false;
+}
+bool beagle_ehrpwm_enable(uint32_t pwmid)
+{
+return false;
+}
+int beagle_pwmss_setting(uint32_t pwm_id, float pwm_freq, float dutyA, float dutyB)
+{
+return -1;
+}
+bool beagle_epwm_pinmux_setup(uint32_t pin_no, uint32_t pwm_id)
+{
+return false;
+}
+#endif
diff --git a/c/src/lib/libcpu/arm/shared/include/am335x.h b/c/src/lib/libcpu/arm/shared/include/am335x.h
index 2009cef..f59f896 100644
--- a/c/src/lib/libcpu/arm/shared/include/am335x.h
+++ b/c/src/lib/libcpu/arm/shared/include/am335x.h
@@ -467,4 +467,99 @@
#define AM335X_CONF_EXT_WAKEUP 0xA00
#define AM335X_CONF_RTC_KALDO_ENN 0xA04
#define AM335X_CONF_USB0_DRVVBUS 0xA1C
-#define AM335X_CONF_USB1_DRVVBUS 0xA34 \ No newline at end of file
+#define AM335X_CONF_USB1_DRVVBUS 0xA34
+
+/* Registers for PWM Subsystem */
+#define AM335X_PWMSS_CTRL (0x664)
+#define AM335X_CM_PER_EPWMSS0_CLKCTRL (0xD4)
+#define AM335X_CM_PER_EPWMSS1_CLKCTRL (0xCC)
+#define AM335X_CM_PER_EPWMSS2_CLKCTRL (0xD8)
+#define AM335X_CONTROL_MODULE (0x44e10000)
+#define AM335X_CM_PER_ADDR (0x44e00000)
+#define AM335X_PWMSS_CLKSTATUS (0xC)
+#define AM335X_PWMSS0_MMAP_ADDR 0x48300000
+#define AM335X_PWMSS1_MMAP_ADDR 0x48302000
+#define AM335X_PWMSS2_MMAP_ADDR 0x48304000
+#define AM335X_PWMSS_MMAP_LEN 0x1000
+#define AM335X_PWMSS_IDVER 0x0
+#define AM335X_PWMSS_SYSCONFIG 0x4
+#define AM335X_PWMSS_CLKCONFIG 0x8
+#define AM335X_PWMSS_CLK_EN_ACK 0x100
+#define AM335X_PWMSS_CLKSTATUS 0xC
+#define AM335X_EPWM_TBCTL 0x0
+#define AM335X_EPWM_TBSTS 0x2
+#define AM335X_EPWM_TBPHSHR 0x4
+#define AM335X_EPWM_TBPHS 0x6
+#define AM335X_EPWM_TBCNT 0x8
+#define AM335X_EPWM_TBPRD 0xA
+#define AM335X_EPWM_CMPCTL 0xE
+#define AM335X_EPWM_CMPAHR 0x10
+#define AM335X_EPWM_CMPA 0x12
+#define AM335X_EPWM_CMPB 0x14
+#define AM335X_EPWM_AQCTLA 0x16
+#define AM335X_EPWM_AQCTLB 0x18
+#define AM335X_EPWM_AQSFRC 0x1A
+#define AM335X_EPWM_AQCSFRC 0x1C
+#define AM335X_EPWM_DBCTL 0x1E
+#define AM335X_EPWM_DBRED 0x20
+#define AM335X_EPWM_DBFED 0x22
+#define AM335X_TBCTL_CTRMODE_UP 0x0
+#define AM335X_TBCTL_CTRMODE_DOWN 0x1
+#define AM335X_TBCTL_CTRMODE_UPDOWN 0x2
+#define AM335X_TBCTL_CTRMODE_FREEZE 0x3
+#define AM335X_EPWM_AQCTLA_ZRO_XALOW (0x0001u)
+#define AM335X_EPWM_AQCTLA_ZRO_XAHIGH (0x0002u)
+#define AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE (0x0003u)
+#define AM335X_EPWM_AQCTLA_CAU_SHIFT (0x0004u)
+#define AM335X_EPWM_AQCTLA_ZRO_XBLOW (0x0001u)
+#define AM335X_EPWM_AQCTLB_ZRO_XBHIGH (0x0002u)
+#define AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE (0x0003u)
+#define AM335X_EPWM_AQCTLB_CBU_SHIFT (0x0008u)
+#define AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE (0x0003u)
+#define AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN (0x00000001u)
+#define AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN (0x00000002u)
+#define AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN (0x00000004u)
+#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define AM335X_TBCTL_CLKDIV_MASK (3 << 10)
+#define AM335X_TBCTL_HSPCLKDIV_MASK (3 << 7)
+#define AM335X_EPWM_TBCTL_CLKDIV (0x1C00u)
+#define AM335X_EPWM_TBCTL_CLKDIV_SHIFT (0x000Au)
+#define AM335X_EPWM_TBCTL_HSPCLKDIV (0x0380u)
+#define AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT (0x0007u)
+#define AM335X_EPWM_TBCTL_PRDLD (0x0008u)
+#define AM335X_EPWM_PRD_LOAD_SHADOW_MASK AM335X_EPWM_TBCTL_PRDLD
+#define AM335X_EPWM_SHADOW_WRITE_ENABLE 0x0
+#define AM335X_EPWM_SHADOW_WRITE_DISABLE 0x1
+#define AM335X_EPWM_TBCTL_PRDLD_SHIFT (0x0003u)
+#define AM335X_EPWM_TBCTL_CTRMODE (0x0003u)
+#define AM335X_EPWM_COUNTER_MODE_MASK AM335X_EPWM_TBCTL_CTRMODE
+#define AM335X_TBCTL_FREERUN (2 << 14)
+#define AM335X_TBCTL_CTRMODE_UP (0x0000u)
+#define AM335X_TBCTL_CTRMODE_SHIFT (0x0000u)
+#define AM335X_EPWM_COUNT_UP (AM335X_TBCTL_CTRMODE_UP << \
+ AM335X_TBCTL_CTRMODE_SHIFT)
+
+#define AM335X_EPWM_REGS (0x00000200)
+#define AM335X_EPWM_0_REGS (AM335X_PWMSS0_MMAP_ADDR + AM335X_EPWM_REGS)
+#define AM335X_EPWM_1_REGS (AM335X_PWMSS1_MMAP_ADDR + AM335X_EPWM_REGS)
+#define AM335X_EPWM_2_REGS (AM335X_PWMSS2_MMAP_ADDR + AM335X_EPWM_REGS)
+
+#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE (0x00000003u)
+#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC (0x0u)
+#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST (0x00030000u)
+
+#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE (0x00000003u)
+#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST (0x00030000u)
+#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC (0x0u)
+#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+
+#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE (0x00000003u)
+#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC (0x0u)
+#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST (0x00030000u)
+
+
+