diff options
Diffstat (limited to 'c/src/lib/libbsp/powerpc')
183 files changed, 3391 insertions, 3391 deletions
diff --git a/c/src/lib/libbsp/powerpc/dmv177/clock/clock.c b/c/src/lib/libbsp/powerpc/dmv177/clock/clock.c index b3a1fc1c29..b768a20541 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/clock/clock.c +++ b/c/src/lib/libbsp/powerpc/dmv177/clock/clock.c @@ -48,11 +48,11 @@ rtems_isr_entry Old_ticker; void Clock_exit( void ); - + /* * These are set by clock driver during its init */ - + rtems_device_major_number rtems_clock_major = ~0; rtems_device_minor_number rtems_clock_minor; @@ -142,11 +142,11 @@ void Install_clock( void Clock_exit( void ) { - /* nothing to do */; + /* nothing to do */; /* do not restore old vector */ } - + /*PAGE * * Clock_initialize @@ -174,17 +174,17 @@ rtems_device_driver Clock_initialize( BSP_Configuration.microseconds_per_tick; Install_clock( (rtems_isr_entry) Clock_isr ); - + /* * make major/minor avail to others such as shared memory driver */ - + rtems_clock_major = major; rtems_clock_minor = minor; - + return RTEMS_SUCCESSFUL; } - + /* PAGE * * Clock_control @@ -210,15 +210,15 @@ rtems_device_driver Clock_control( { uint32_t isrlevel; rtems_libio_ioctl_args_t *args = pargp; - + if (args == 0) goto done; - + /* * This is hokey, but until we get a defined interface * to do this, it will just be this simple... */ - + if (args->command == rtems_build_name('I', 'S', 'R', ' ')) { Clock_isr( CLOCK_VECTOR, pargp ); @@ -229,7 +229,7 @@ rtems_device_driver Clock_control( (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); rtems_interrupt_enable( isrlevel ); } - + done: return RTEMS_SUCCESSFUL; } diff --git a/c/src/lib/libbsp/powerpc/dmv177/console/conscfg.c b/c/src/lib/libbsp/powerpc/dmv177/console/conscfg.c index 80f12e9954..106819a7aa 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/console/conscfg.c +++ b/c/src/lib/libbsp/powerpc/dmv177/console/conscfg.c @@ -32,7 +32,7 @@ * all others being given the name indicated. */ -mc68681_baud_t +mc68681_baud_t dmv177_mc68681_baud_table[4][RTEMS_TERMIOS_NUMBER_BAUD_RATES] = { { /* ACR[7] = 0, X = 0 */ MC68681_BAUD_NOT_VALID, /* B0 */ @@ -125,7 +125,7 @@ mc68681_baud_t }; #define MC68681_PORT_CONFIG \ - (MC68681_DATA_BAUD_RATE_SET_1|MC68681_XBRG_ENABLED) + (MC68681_DATA_BAUD_RATE_SET_1|MC68681_XBRG_ENABLED) /* * Based on BSP configuration information decide whether to do polling IO diff --git a/c/src/lib/libbsp/powerpc/dmv177/console/debugio.c b/c/src/lib/libbsp/powerpc/dmv177/console/debugio.c index bc4f97a69d..6b3234ef06 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/console/debugio.c +++ b/c/src/lib/libbsp/powerpc/dmv177/console/debugio.c @@ -38,7 +38,7 @@ extern console_data Console_Port_Data[]; extern rtems_device_minor_number Console_Port_Minor; - + /* PAGE * * DEBUG_puts @@ -95,7 +95,7 @@ void DEBUG_puth( unsigned long i,d; uint32_t Irql; void (*poll)(int minor, char cChar); - + poll = Console_Port_Tbl[Console_Port_Minor].pDeviceFns->deviceWritePolled; rtems_interrupt_disable(Irql); diff --git a/c/src/lib/libbsp/powerpc/dmv177/include/bsp.h b/c/src/lib/libbsp/powerpc/dmv177/include/bsp.h index cf003774c9..1c37e843b2 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/dmv177/include/bsp.h @@ -25,7 +25,7 @@ extern "C" { #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 4 #define CONFIGURE_INTERRUPT_STACK_MEMORY (12 * 1024) - + #ifdef ASM /* Definition of where to store registers in alignment handler */ #define ALIGN_REGS 0x0140 @@ -118,15 +118,15 @@ int rtems_dmv177_sonic_driver_attach(struct rtems_bsdnet_ifconfig *config); /* * Device Driver Table Entries */ - + /* * NOTE: Use the standard Console driver entry */ - + /* * NOTE: Use the standard Clock driver entry */ - + /* * Information placed in the linkcmds file. @@ -147,12 +147,12 @@ extern int end; /* last address in the program */ /* * How many libio files we want */ - + #define BSP_LIBIO_MAX_FDS 20 /* functions */ -/* +/* * genvec.c */ rtems_isr_entry set_EE_vector( diff --git a/c/src/lib/libbsp/powerpc/dmv177/include/dmv170.h b/c/src/lib/libbsp/powerpc/dmv177/include/dmv170.h index f22feb636d..4a54fd7573 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/include/dmv170.h +++ b/c/src/lib/libbsp/powerpc/dmv177/include/dmv170.h @@ -2,9 +2,9 @@ * * This include file contains information pertaining to the DMV170. * - * NOTE: Other than where absolutely required, this version currently - * supports only the peripherals and bits used by the basic board - * support package. This includes at least significant pieces of + * NOTE: Other than where absolutely required, this version currently + * supports only the peripherals and bits used by the basic board + * support package. This includes at least significant pieces of * the following items: * * + UART Channels A and B @@ -18,7 +18,7 @@ * * $Id$ */ - + #ifndef _INCLUDE_DMV170_h #define _INCLUDE_DMV170_h @@ -59,7 +59,7 @@ extern "C" { #define SONIC_BASE_ADDRESS DMV170_SONIC_ADDR #define SONIC_VECTOR DMV170_ETHERNET_IRQ -/* base address for the SCC (85C30) */ +/* base address for the SCC (85C30) */ #define Z85C30_ADDR 0xfb000010 #define Z85C30_CTRL_A 0xfb000010 #define Z85C30_DATA_A 0xfb000018 @@ -127,7 +127,7 @@ extern "C" { #define DMV170_LOWER_STATUS_LED_CONTROL_MASK 0x2000 #define DMV170_LOWER_STATUS_LED_IS_OFF 0x2000 #define DMV170_LOWER_STATUS_LED_IS_ON 0x0000 -#ifdef DMV176 +#ifdef DMV176 /* The following are not available for the DMV171 */ #define DMV170_RAM_TYPE_MASK 0x4000 #define DMV170_RAM_TYPE_IS_DRAM 0x4000 @@ -136,7 +136,7 @@ extern "C" { #define DMV170_IACK_VECTOR_AUTOVECTOR_IS_VECTOR 0x8000 #define DMV170_IACK_VECTOR_AUTOVECTOR_IS_NOT_VECTOR 0x0000 #endif - + /* * The following defines the bits in the Timer Control Register. */ @@ -220,7 +220,7 @@ extern "C" { * DUART Baud Rate Definitions. */ -#define DMV170_DUART_9621 MC68681_BAUD_RATE_MASK_600 /* close to 9600 */ +#define DMV170_DUART_9621 MC68681_BAUD_RATE_MASK_600 /* close to 9600 */ #define DMV170_RTC_FREQUENCY 0x0000 @@ -248,10 +248,10 @@ extern "C" { #define DMV170_ETHERNET_IRQ DMV170_LIRQ5 #define DMV170_SCSI_IRQ DMV170_LIRQ5 #define DMV170_SCC_IRQ DMV170_LIRQ5 -#define DMV170_MEZZANINE_IRQ_0 DMV170_LIRQ4 +#define DMV170_MEZZANINE_IRQ_0 DMV170_LIRQ4 #define DMV170_TICK_IRQ DMV170_LIRQ3 -#define DMV170_LOCATION_MON_IRQ DMV170_LIRQ2 -#define DMV170_SCV64_IRQ DMV170_LIRQ1 +#define DMV170_LOCATION_MON_IRQ DMV170_LIRQ2 +#define DMV170_SCV64_IRQ DMV170_LIRQ1 #define DMV170_RTC_IRQ DMV170_LIRQ0 #define DMV170_ACFAIL_IRQ DMV170_L7IACF @@ -283,6 +283,6 @@ uint32_t SCV64_Get_Interrupt_Enable(); #ifdef __cplusplus } #endif - + #endif /* !_INCLUDE_DMV170_h */ /* end of include file */ diff --git a/c/src/lib/libbsp/powerpc/dmv177/scv64/scv64.c b/c/src/lib/libbsp/powerpc/dmv177/scv64/scv64.c index 5e67698b3a..e7e357d0d2 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/scv64/scv64.c +++ b/c/src/lib/libbsp/powerpc/dmv177/scv64/scv64.c @@ -14,23 +14,23 @@ typedef struct { /* DARF Registers */ - volatile uint32_t DMALAR; /* 0x00 */ - volatile uint32_t DMAVAR; /* 0x04 */ - volatile uint32_t DMATC; /* 0x08 */ - volatile uint32_t DCSR; /* 0x0c */ - volatile uint32_t VMEBAR; /* 0x10 */ - volatile uint32_t RXDATA; /* 0x14 */ - volatile uint32_t RXADDR; /* 0x18 */ - volatile uint32_t RXCTL; /* 0x1c */ - volatile uint32_t BUSSEL; /* 0x20 */ - volatile uint32_t IVECT; /* 0x24 */ - volatile uint32_t APBR; /* 0x28 */ - volatile uint32_t TXDATA; /* 0x2c */ - volatile uint32_t TXADDR; /* 0x30 */ - volatile uint32_t TXCTL; /* 0x34 */ - volatile uint32_t LMFIFO; /* 0x38 */ - volatile uint32_t MODE; /* 0x3c */ - volatile uint32_t SA64BAR; /* 0x40 */ + volatile uint32_t DMALAR; /* 0x00 */ + volatile uint32_t DMAVAR; /* 0x04 */ + volatile uint32_t DMATC; /* 0x08 */ + volatile uint32_t DCSR; /* 0x0c */ + volatile uint32_t VMEBAR; /* 0x10 */ + volatile uint32_t RXDATA; /* 0x14 */ + volatile uint32_t RXADDR; /* 0x18 */ + volatile uint32_t RXCTL; /* 0x1c */ + volatile uint32_t BUSSEL; /* 0x20 */ + volatile uint32_t IVECT; /* 0x24 */ + volatile uint32_t APBR; /* 0x28 */ + volatile uint32_t TXDATA; /* 0x2c */ + volatile uint32_t TXADDR; /* 0x30 */ + volatile uint32_t TXCTL; /* 0x34 */ + volatile uint32_t LMFIFO; /* 0x38 */ + volatile uint32_t MODE; /* 0x3c */ + volatile uint32_t SA64BAR; /* 0x40 */ volatile uint32_t MA64BAR; /* 0x44 */ volatile uint32_t LAG; /* 0x48 */ volatile uint32_t DMAVTC; /* 0x4c */ @@ -39,38 +39,38 @@ typedef struct { volatile uint32_t reserved_50_7F[12]; /* ACC Registers */ - volatile uint8_t STAT0_pad[3]; /* 0x80 */ - volatile uint8_t STAT0; - volatile uint8_t STAT1_pad[3]; /* 0x84 */ - volatile uint8_t STAT1; - volatile uint8_t GENCTL_pad[3]; /* 0x88 */ - volatile uint8_t GENCTL; - volatile uint8_t VINT_pad[3]; /* 0x8c */ - volatile uint8_t VINT; - volatile uint8_t VREQ_pad[3]; /* 0x90 */ - volatile uint8_t VREQ; - volatile uint8_t VARB_pad[3]; /* 0x94 */ - volatile uint8_t VARB; - volatile uint8_t ID_pad[3]; /* 0x98 */ - volatile uint8_t ID; - volatile uint8_t NA_pad[3]; /* 0x9c */ - volatile uint8_t NA; - volatile uint8_t _7IS_pad[3]; /* 0xa0 */ - volatile uint8_t _7IS; - volatile uint8_t LIS_pad[3]; /* 0xa4 */ - volatile uint8_t LIS; - volatile uint8_t UIE_pad[3]; /* 0xa8 */ - volatile uint8_t UIE; - volatile uint8_t LIE_pad[3]; /* 0xac */ - volatile uint8_t LIE; - volatile uint8_t VIE_pad[3]; /* 0xb0 */ - volatile uint8_t VIE; - volatile uint8_t IC10_pad[3]; /* 0xb4 */ - volatile uint8_t IC10; - volatile uint8_t IC32_pad[3]; /* 0xb8 */ - volatile uint8_t IC32; - volatile uint8_t IC54_pad[3]; /* 0xbc */ - volatile uint8_t IC54; + volatile uint8_t STAT0_pad[3]; /* 0x80 */ + volatile uint8_t STAT0; + volatile uint8_t STAT1_pad[3]; /* 0x84 */ + volatile uint8_t STAT1; + volatile uint8_t GENCTL_pad[3]; /* 0x88 */ + volatile uint8_t GENCTL; + volatile uint8_t VINT_pad[3]; /* 0x8c */ + volatile uint8_t VINT; + volatile uint8_t VREQ_pad[3]; /* 0x90 */ + volatile uint8_t VREQ; + volatile uint8_t VARB_pad[3]; /* 0x94 */ + volatile uint8_t VARB; + volatile uint8_t ID_pad[3]; /* 0x98 */ + volatile uint8_t ID; + volatile uint8_t NA_pad[3]; /* 0x9c */ + volatile uint8_t NA; + volatile uint8_t _7IS_pad[3]; /* 0xa0 */ + volatile uint8_t _7IS; + volatile uint8_t LIS_pad[3]; /* 0xa4 */ + volatile uint8_t LIS; + volatile uint8_t UIE_pad[3]; /* 0xa8 */ + volatile uint8_t UIE; + volatile uint8_t LIE_pad[3]; /* 0xac */ + volatile uint8_t LIE; + volatile uint8_t VIE_pad[3]; /* 0xb0 */ + volatile uint8_t VIE; + volatile uint8_t IC10_pad[3]; /* 0xb4 */ + volatile uint8_t IC10; + volatile uint8_t IC32_pad[3]; /* 0xb8 */ + volatile uint8_t IC32; + volatile uint8_t IC54_pad[3]; /* 0xbc */ + volatile uint8_t IC54; /* Utility Registers */ volatile uint32_t MISC; volatile uint32_t delay_line[3]; @@ -90,7 +90,7 @@ typedef struct { #define LOCAL_INTERRUPT_ENABLE_4 0x10 #define LOCAL_INTERRUPT_ENABLE_5 0x20 -/* +/* * IC54 Register */ #define AUTOVECTOR_5 0x80 @@ -110,7 +110,7 @@ SCV64_Registers *SCV64 = (void *)DMV170_SCV64_BASE_ADDRESS; void SCV64_Initialize() { SCV64->LIE = 0; } - + /*PAGE * * SCV64_Generate_DUART_Interrupts @@ -121,7 +121,7 @@ void SCV64_Initialize() { void SCV64_Generate_DUART_Interrupts() { uint8_t data; - + /* * Set Local Interrupt 5 enable */ @@ -146,7 +146,7 @@ void SCV64_Generate_DUART_Interrupts() { uint32_t SCV64_Get_Interrupt() { uint8_t data; - + /* * Put the LIS data into the lower byte of the result */ diff --git a/c/src/lib/libbsp/powerpc/dmv177/sonic/dmvsonic.c b/c/src/lib/libbsp/powerpc/dmv177/sonic/dmvsonic.c index f769f4e635..faf189a627 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/sonic/dmvsonic.c +++ b/c/src/lib/libbsp/powerpc/dmv177/sonic/dmvsonic.c @@ -97,8 +97,8 @@ uint32_t dmv177_sonic_read_register( #endif sonic_configuration_t dmv177_sonic_configuration = { - SONIC_BASE_ADDRESS, /* base address */ - SONIC_VECTOR, /* vector number */ + SONIC_BASE_ADDRESS, /* base address */ + SONIC_VECTOR, /* vector number */ SONIC_DCR, /* DCR register value */ SONIC_DC2, /* DC2 register value */ TDA_COUNT, /* number of transmit descriptors */ @@ -110,5 +110,5 @@ sonic_configuration_t dmv177_sonic_configuration = { int rtems_dmv177_sonic_driver_attach(struct rtems_bsdnet_ifconfig *config) { return rtems_sonic_driver_attach( config, &dmv177_sonic_configuration ); - + } diff --git a/c/src/lib/libbsp/powerpc/dmv177/start/start.S b/c/src/lib/libbsp/powerpc/dmv177/start/start.S index e3e4bc3fb3..33d793ad98 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/start/start.S +++ b/c/src/lib/libbsp/powerpc/dmv177/start/start.S @@ -66,7 +66,7 @@ _start: */ bl .Laddr /* get current address */ - + .Laddr: mflr r4 /* real address of .Laddr */ lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ diff --git a/c/src/lib/libbsp/powerpc/dmv177/startup/bspstart.c b/c/src/lib/libbsp/powerpc/dmv177/startup/bspstart.c index 971a6bb4e4..0a1ef09de1 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/dmv177/startup/bspstart.c @@ -21,7 +21,7 @@ * The original table from the application and our copy of it with * some changes. */ - + extern rtems_configuration_table Configuration; rtems_configuration_table BSP_Configuration; rtems_cpu_table Cpu_table; @@ -67,7 +67,7 @@ void bsp_pretasking_hook(void) * bsp_predriver_hook * * Initialization before drivers are setup. - */ + */ void bsp_predriver_hook(void) { @@ -93,14 +93,14 @@ void bsp_start( void ) */ _CPU_MSR_SET( msr_value ); - + /* * Need to "allocate" the memory for the RTEMS Workspace and * tell the RTEMS configuration where it is. This memory is * not malloc'ed. It is just "pulled from the air". */ - work_space_start = + work_space_start = (unsigned char *)&RAM_END - BSP_Configuration.work_space_size; if ( work_space_start <= (unsigned char *)&end ) { diff --git a/c/src/lib/libbsp/powerpc/dmv177/startup/genpvec.c b/c/src/lib/libbsp/powerpc/dmv177/startup/genpvec.c index 4661a718bc..5b3d292c78 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/startup/genpvec.c +++ b/c/src/lib/libbsp/powerpc/dmv177/startup/genpvec.c @@ -7,7 +7,7 @@ * * The external exception vector numbers begin with DMV170_IRQ_FIRST. * DMV170_IRQ_FIRST is defined to be one greater than the last processor - * interrupt. + * interrupt. * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -26,8 +26,8 @@ #define NUM_LIRQ_HANDLERS 20 #define NUM_LIRQ ( MAX_BOARD_IRQS - PPC_IRQ_LAST ) -/* - * Structure to for one of possible multiple interrupt handlers for +/* + * Structure to for one of possible multiple interrupt handlers for * a given interrupt. */ typedef struct @@ -42,7 +42,7 @@ typedef struct * handlers at a later time. */ EE_ISR_Type ISR_Nodes [NUM_LIRQ_HANDLERS]; -uint16_t Nodes_Used; +uint16_t Nodes_Used; Chain_Control ISR_Array [NUM_LIRQ]; /*PAGE @@ -56,22 +56,22 @@ Chain_Control ISR_Array [NUM_LIRQ]; * * Output parameters: NONE * - * Return values: + * Return values: */ rtems_isr external_exception_ISR ( rtems_vector_number vector /* IN */ ) -{ +{ uint16_t index; rtems_boolean is_active=FALSE; uint32_t scv64_status; Chain_Node *node; EE_ISR_Type *ee_isr; - + /* - * Get all active interrupts. + * Get all active interrupts. */ scv64_status = SCV64_Get_Interrupt(); scv64_status &= SCV64_Get_Interrupt_Enable(); @@ -121,7 +121,7 @@ rtems_isr external_exception_ISR ( * initialize_external_exception_vector * * This routine initializes the external exception vector - * + * * Input parameters: NONE * * Output parameters: NONE @@ -134,24 +134,24 @@ void initialize_external_exception_vector () int i; rtems_isr_entry previous_isr; rtems_status_code status; - extern void SCV64_Initialize( void ); + extern void SCV64_Initialize( void ); Nodes_Used = 0; /* * Initialize the SCV64 chip */ - SCV64_Initialize(); + SCV64_Initialize(); for (i=0; i <NUM_LIRQ; i++) Chain_Initialize_empty( &ISR_Array[i] ); - /* - * Install external_exception_ISR () as the handler for + /* + * Install external_exception_ISR () as the handler for * the General Purpose Interrupt. */ - status = rtems_interrupt_catch( external_exception_ISR, + status = rtems_interrupt_catch( external_exception_ISR, PPC_IRQ_EXTERNAL , (rtems_isr_entry *) &previous_isr ); } @@ -160,7 +160,7 @@ void initialize_external_exception_vector () * * set_EE_vector * - * This routine installs one of multiple ISRs for the general purpose + * This routine installs one of multiple ISRs for the general purpose * inerrupt. * * Input parameters: @@ -179,12 +179,12 @@ rtems_isr_entry set_EE_vector( { uint16_t vec_idx = vector - DMV170_IRQ_FIRST; uint32_t index; - - /* + + /* * Verify that all of the nodes have not been used. */ assert (Nodes_Used < NUM_LIRQ_HANDLERS); - + /* * If we have already installed this handler for this vector, then * just reset it. @@ -200,8 +200,8 @@ rtems_isr_entry set_EE_vector( * Increment the number of nedes used and set the index for the node * array. */ - - Nodes_Used++; + + Nodes_Used++; index = Nodes_Used - 1; /* @@ -211,8 +211,8 @@ rtems_isr_entry set_EE_vector( ISR_Nodes[index].vector = vector; /* - * Connect this node to the chain at the location of the - * vector index. + * Connect this node to the chain at the location of the + * vector index. */ Chain_Append( &ISR_Array[vec_idx], &ISR_Nodes[index].Node ); diff --git a/c/src/lib/libbsp/powerpc/dmv177/startup/setvec.c b/c/src/lib/libbsp/powerpc/dmv177/startup/setvec.c index 16b94f5503..614a9b8205 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/startup/setvec.c +++ b/c/src/lib/libbsp/powerpc/dmv177/startup/setvec.c @@ -41,7 +41,7 @@ rtems_isr_entry set_vector( /* returns old vector */ rtems_isr_entry previous_isr; rtems_status_code status; - /* + /* * vectors greater than PPC603e_IRQ_LAST are handled by the General purpose * interupt handler. */ diff --git a/c/src/lib/libbsp/powerpc/dmv177/timer/timer.c b/c/src/lib/libbsp/powerpc/dmv177/timer/timer.c index e912c018da..c9a406f6bf 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/timer/timer.c +++ b/c/src/lib/libbsp/powerpc/dmv177/timer/timer.c @@ -21,8 +21,8 @@ rtems_boolean Timer_driver_Find_average_overhead; /*PAGE * * Timer_initialize - * - * This routine initializes the timer. + * + * This routine initializes the timer. * * Input parameters: NONE * @@ -40,7 +40,7 @@ void Timer_initialize() Timer_driver_Start_time = PPC_Get_timebase_register(); - + } @@ -97,7 +97,7 @@ int Read_timer() * * Input parameters: NONE * - * Output parameters: + * Output parameters: * status code of successful * * Return values: NONE @@ -115,7 +115,7 @@ rtems_status_code Empty_function( void ) * * This routine sets a global boolean to the value passed in. * - * Input parameters: + * Input parameters: * find_flag - flag to indicate to find the average overhead. * * Output parameters: NONE diff --git a/c/src/lib/libbsp/powerpc/eth_comm/canbus/canbus.c b/c/src/lib/libbsp/powerpc/eth_comm/canbus/canbus.c index 389836e389..e9cce22c8a 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/canbus/canbus.c +++ b/c/src/lib/libbsp/powerpc/eth_comm/canbus/canbus.c @@ -56,7 +56,7 @@ canInterruptHandler (rtems_vector_number v) } tmpTail = rxMsgBufTail[dev]; while (1) { - if ((tmpTail == rxMsgBufHead[dev]) && + if ((tmpTail == rxMsgBufHead[dev]) && (rxMsgBuf[dev][tmpTail].ctrl1 & I82527_MSG_CTRL_NEWDAT)) { break; /* Buf is full */ } @@ -69,7 +69,7 @@ canInterruptHandler (rtems_vector_number v) rxMsgBuf[dev][tmpTail].ctrl1 = candev[dev]->msg15.ctrl1; rxMsgBuf[dev][tmpTail].arb = candev[dev]->msg15.arb; rxMsgBuf[dev][tmpTail].cfg = candev[dev]->msg15.cfg; - + pkt_len = (rxMsgBuf[dev][tmpTail].cfg >> 4) & 0xf; for (i=0; i<pkt_len; i++) { rxMsgBuf[dev][tmpTail].data[i] = candev[dev]->msg15.data[i]; @@ -97,7 +97,7 @@ canInterruptHandler (rtems_vector_number v) candev[dev]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_SET | I82527_MSG_CTRL_INTPND_CLR); - candev[dev]->msg15.ctrl1 = 0xff & (I82527_MSG_CTRL_NEWDAT_CLR | + candev[dev]->msg15.ctrl1 = 0xff & (I82527_MSG_CTRL_NEWDAT_CLR | I82527_MSG_CTRL_RMTPND_CLR); candev[dev]->status = 0x0; } @@ -117,7 +117,7 @@ rtems_device_driver canbus_initialize( #endif rtems_status_code status; rtems_isr_entry old_handler; - + #if (NUM_CAN_DEVS > 0) candev[0]=&canbus0; rtems_interrupt_catch (canInterruptHandler, @@ -135,7 +135,7 @@ rtems_device_driver canbus_initialize( rtems_interrupt_catch (canInterruptHandler, PPC_IRQ_IRQ2, &old_handler); - + /* Right now, we only support 3 CAN interfaces */ #else #error NUM_CAN_DEVS is too big. Fix it, damnit! @@ -147,7 +147,7 @@ rtems_device_driver canbus_initialize( for (i=0; i < NUM_CAN_DEVS; i++) { - + /* clear rx buffers */ rxMsgBufHead[i] = 0; rxMsgBufTail[i] = 0; @@ -158,10 +158,10 @@ rtems_device_driver canbus_initialize( candev[i]->ctrl = I82527_CTRL_CCE | /* Enable cfg reg writes */ I82527_CTRL_INIT; /* Disable external xfers */ - + candev[i]->cir = I82527_CIR_DMC; /* Divide memory clock by 2 */ - + /* We want 250 kbps so assuming an input clock rate of 10 MHz: * DSC = 0 => SCLK = 10 MHz, tSCLK = 100ns * BRP = 1 => tq = 200ns @@ -181,7 +181,7 @@ rtems_device_driver canbus_initialize( candev[i]->gms = 0xffff; /* addresses must match exactly */ candev[i]->gml = 0xffffffff; /* addresses must match exactly */ - + candev[i]->mlm = 0x0; /* all addresses accepted */ candev[i]->p2conf = 0xff; /* make all outputs */ @@ -190,85 +190,85 @@ rtems_device_driver canbus_initialize( candev[i]->msg1.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg2.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ candev[i]->msg2.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg3.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ candev[i]->msg3.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg4.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ candev[i]->msg4.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR | /* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg5.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ candev[i]->msg5.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg6.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ candev[i]->msg6.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg7.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ candev[i]->msg7.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg8.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ candev[i]->msg8.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg9.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ candev[i]->msg9.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg10.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ candev[i]->msg10.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR | /* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg11.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ candev[i]->msg11.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg12.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ candev[i]->msg12.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg13.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ candev[i]->msg13.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg14.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ candev[i]->msg14.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ - I82527_MSG_CTRL_INTPND_CLR; + I82527_MSG_CTRL_INTPND_CLR; candev[i]->msg15.cfg = 0 ; /* dir is rcv */ candev[i]->msg15.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ @@ -306,7 +306,7 @@ rtems_device_driver canbus_open( /* msg is in use, rx interrupts are enabled */ candev[minor]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_SET | I82527_MSG_CTRL_RXIE_SET); - + candev[minor]->ctrl |= I82527_CTRL_IE; candev[minor]->ctrl &= ~(I82527_CTRL_CCE | I82527_CTRL_INIT); switch (minor) { @@ -329,10 +329,10 @@ rtems_device_driver canbus_close( candev[minor]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_CLR | I82527_MSG_CTRL_RXIE_CLR | I82527_MSG_CTRL_TXIE_CLR); - + /* Take transceiver off the bus, enable cfg. reg. writes */ candev[minor]->ctrl |= (I82527_CTRL_CCE | I82527_CTRL_INIT); - + return RTEMS_SUCCESSFUL; } @@ -351,7 +351,7 @@ rtems_device_driver canbus_read( tmpHead = rxMsgBufHead[minor]; while (1){ - if ((tmpHead == rxMsgBufTail[minor]) && + if ((tmpHead == rxMsgBufTail[minor]) && !(rxMsgBuf[minor][tmpHead].ctrl1 & I82527_MSG_CTRL_NEWDAT)) { break; } @@ -361,7 +361,7 @@ rtems_device_driver canbus_read( msg->ctrl1 = rxMsgBuf[minor][tmpHead].ctrl1; msg->arb = rxMsgBuf[minor][tmpHead].arb; msg->cfg = rxMsgBuf[minor][tmpHead].cfg; - + pkt_len = (msg->cfg >> 4) & 0xf; for (i=0; i<pkt_len; i++) { msg->data[i] = rxMsgBuf[minor][tmpHead].data[i]; @@ -390,7 +390,7 @@ rtems_device_driver canbus_read( return RTEMS_UNSATISFIED; } - + rtems_device_driver canbus_write( rtems_device_major_number major, rtems_device_minor_number minor, @@ -436,7 +436,7 @@ rtems_device_driver canbus_control( /* part of old canbus_read */ -#if 0 +#if 0 for (i=0; i < RX_CAN_BUF_SIZE) { if (rxMsgBuf[minor][i].ctrl1 & I82527_MSG_CTRL_NEWDAT) break; @@ -447,17 +447,17 @@ rtems_device_driver canbus_control( int j; msg.arb = rxMsgBuf[minor][i].arb; msg.cfg = rxMsgBuf[minor][i].cfg; - + pkt_len = (msg.cfg >> 4) & 0xf; - for (j=0; j < pkt_len; j++) + for (j=0; j < pkt_len; j++) msg.data[j] = rxMsgBuf[minor][i].data[j]; - - + + /* wait until there is a msg */ while (!(candev->msg15.ctrl1 & I82527_MSG_CTRL_NEWDAT)) continue; - + msg->ctrl1 = candev->msg15.ctrl1; msg->cfg = candev->msg15.cfg; msg->arb = candev->msg15.arb; @@ -468,7 +468,7 @@ rtems_device_driver canbus_control( candev->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_SET | I82527_MSG_CTRL_INTPND_CLR); - candev->msg15.ctrl1 = 0xff & (I82527_MSG_CTRL_NEWDAT_CLR | + candev->msg15.ctrl1 = 0xff & (I82527_MSG_CTRL_NEWDAT_CLR | I82527_MSG_CTRL_RMTPND_CLR); candev->status = 0x0; diff --git a/c/src/lib/libbsp/powerpc/eth_comm/clock/p_clock.c b/c/src/lib/libbsp/powerpc/eth_comm/clock/p_clock.c index 4a79f81864..b4bf7ca93e 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/clock/p_clock.c +++ b/c/src/lib/libbsp/powerpc/eth_comm/clock/p_clock.c @@ -28,7 +28,7 @@ static rtems_irq_connect_data clockIrqData = {BSP_PERIODIC_TIMER, (rtems_irq_enable)clockOn, (rtems_irq_disable)clockOff, (rtems_irq_is_enabled)clockIsOn}; - + int BSP_get_clock_irq_level() { /* @@ -65,6 +65,6 @@ int BSP_connect_clock_handler (rtems_irq_hdl hdl) clockIrqData.on = (rtems_irq_enable)clockOn; clockIrqData.off = (rtems_irq_enable)clockOff; clockIrqData.isOn = (rtems_irq_is_enabled)clockIsOn; - + return BSP_install_rtems_irq_handler (&clockIrqData); } diff --git a/c/src/lib/libbsp/powerpc/eth_comm/console/console.c b/c/src/lib/libbsp/powerpc/eth_comm/console/console.c index 411e279ef2..d9d98c5a91 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/console/console.c +++ b/c/src/lib/libbsp/powerpc/eth_comm/console/console.c @@ -1,10 +1,10 @@ -#define I_WANT_TERMIOS +#define I_WANT_TERMIOS /* * BSP specific Serial I/O Functions for the eth-comm BSP * - * This file contains the BSP specific functions for + * This file contains the BSP specific functions for * performing serial I/O. These are the functions - * RTEMS uses (the 6 listed in the device driver + * RTEMS uses (the 6 listed in the device driver * structure) * * The SCCs and SMCs are assigned as follows @@ -21,7 +21,7 @@ * appear to work correctly yet. On startup, with termios enabled, * the board hangs for a few seconds before running correctly * - * Author: Jay Monkman (jmonkman@frasca.com) + * Author: Jay Monkman (jmonkman@frasca.com) * Copyright (C) 1998 by Frasca International, Inc. * * $Id$ @@ -42,7 +42,7 @@ rtems_device_driver console_initialize(rtems_device_major_number major, void *arg) { rtems_status_code status; - + #ifdef I_WANT_TERMIOS /* * Set up TERMIOS (for /dev/console) @@ -59,11 +59,11 @@ rtems_device_driver console_initialize(rtems_device_major_number major, * Do device-specific initialization */ m8xx_uart_smc_initialize(SMC1_MINOR); /* /dev/tty0 */ - m8xx_uart_smc_initialize(SMC2_MINOR); /* /dev/tty1 */ + m8xx_uart_smc_initialize(SMC2_MINOR); /* /dev/tty1 */ m8xx_uart_scc_initialize(SCC2_MINOR); /* /dev/tty2 */ m8xx_uart_scc_initialize(SCC3_MINOR); /* /dev/tty3 */ m8xx_uart_scc_initialize(SCC4_MINOR); /* /dev/tty4 */ - + /* * Register the devices */ @@ -84,7 +84,7 @@ rtems_device_driver console_initialize(rtems_device_major_number major, rtems_fatal_error_occurred (status); return RTEMS_SUCCESSFUL; } - + rtems_device_driver console_open(rtems_device_major_number major, rtems_device_minor_number minor, void *arg) @@ -116,7 +116,7 @@ rtems_device_driver console_open(rtems_device_major_number major, case 2: sccregs = &m8xx.scc1; break; - case 3: + case 3: sccregs = &m8xx.scc2; break; case 4: @@ -136,7 +136,7 @@ rtems_device_driver console_open(rtems_device_major_number major, if (minor == SCC2_MINOR) { return rtems_termios_open (major, minor, arg, &sccPollCallbacks); } - else { + else { return RTEMS_SUCCESSFUL; } #else @@ -207,7 +207,7 @@ rtems_device_driver console_write(rtems_device_major_number major, rtems_device_driver console_control(rtems_device_major_number major, rtems_device_minor_number minor, void *arg) -{ +{ #ifdef I_WANT_TERMIOS if (minor == SCC2_MINOR) { return rtems_termios_ioctl (arg); diff --git a/c/src/lib/libbsp/powerpc/eth_comm/include/bsp.h b/c/src/lib/libbsp/powerpc/eth_comm/include/bsp.h index 1a8f6b76f4..8c7f2e07fd 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/eth_comm/include/bsp.h @@ -40,7 +40,7 @@ extern "C" { /* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */ #define CONFIGURE_INTERRUPT_STACK_MEMORY (4 * 1024) - + /* * Network driver configuration */ @@ -98,7 +98,7 @@ extern rtems_configuration_table BSP_Configuration; /* * NOTE: Use the standard Console driver entry */ - + /* * NOTE: Use the standard Clock driver entry */ diff --git a/c/src/lib/libbsp/powerpc/eth_comm/include/canbus.h b/c/src/lib/libbsp/powerpc/eth_comm/include/canbus.h index 6b07b823dd..e32d3c6338 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/include/canbus.h +++ b/c/src/lib/libbsp/powerpc/eth_comm/include/canbus.h @@ -11,7 +11,7 @@ * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * $Id: + * $Id: */ #ifndef __CANBUS_H_ @@ -102,8 +102,8 @@ typedef struct i82527_t_ { #define I82527_DCR0 (1) #define I82527_BTR1_SPL (1<<7) #define I82527_MSG_CTRL_MSGVAL (2<<6) -#define I82527_MSG_CTRL_MSGVAL_NC (3<<6) -#define I82527_MSG_CTRL_MSGVAL_SET (2<<6) +#define I82527_MSG_CTRL_MSGVAL_NC (3<<6) +#define I82527_MSG_CTRL_MSGVAL_SET (2<<6) #define I82527_MSG_CTRL_MSGVAL_CLR (1<<6) #define I82527_MSG_CTRL_TXIE (2<<4) #define I82527_MSG_CTRL_TXIE_NC (3<<4) @@ -145,23 +145,23 @@ extern i82527_t canbus1; extern i82527_t canbus2; -rtems_device_driver canbus_initialize(rtems_device_major_number, - rtems_device_minor_number, +rtems_device_driver canbus_initialize(rtems_device_major_number, + rtems_device_minor_number, void *); -rtems_device_driver canbus_open(rtems_device_major_number, - rtems_device_minor_number, +rtems_device_driver canbus_open(rtems_device_major_number, + rtems_device_minor_number, void *); -rtems_device_driver canbus_close(rtems_device_major_number, - rtems_device_minor_number, +rtems_device_driver canbus_close(rtems_device_major_number, + rtems_device_minor_number, void *); -rtems_device_driver canbus_read(rtems_device_major_number, - rtems_device_minor_number, +rtems_device_driver canbus_read(rtems_device_major_number, + rtems_device_minor_number, void *); -rtems_device_driver canbus_write(rtems_device_major_number, - rtems_device_minor_number, +rtems_device_driver canbus_write(rtems_device_major_number, + rtems_device_minor_number, void *); -rtems_device_driver canbus_control(rtems_device_major_number, - rtems_device_minor_number, +rtems_device_driver canbus_control(rtems_device_major_number, + rtems_device_minor_number, void *); diff --git a/c/src/lib/libbsp/powerpc/eth_comm/include/info.h b/c/src/lib/libbsp/powerpc/eth_comm/include/info.h index 305a1d1429..d205fed121 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/include/info.h +++ b/c/src/lib/libbsp/powerpc/eth_comm/include/info.h @@ -25,7 +25,7 @@ typedef struct BoardInfoBlock_ { uint8_t fpn[16]; /* Frasca part number in ASCII */ uint16_t rev; /* Board revision */ uint32_t ip_num; /* Board IP number */ - + } boardinfo_t; #define IFACE_ARINC429_TX0 0x00000001; diff --git a/c/src/lib/libbsp/powerpc/eth_comm/irq/irq.c b/c/src/lib/libbsp/powerpc/eth_comm/irq/irq.c index d5f7ff1655..fe4b7fa418 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/eth_comm/irq/irq.c @@ -10,7 +10,7 @@ * * $Id$ */ - + #include <rtems/system.h> #include <bsp.h> #include <bsp/irq.h> @@ -65,9 +65,9 @@ static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine) /* - * masks used to mask off the interrupts. For exmaple, for ILVL2, the - * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 - * and ILVL7. + * masks used to mask off the interrupts. For exmaple, for ILVL2, the + * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 + * and ILVL7. * */ const static unsigned int SIU_IvectMask[BSP_SIU_IRQ_NUMBER] = @@ -131,10 +131,10 @@ int BSP_irq_enable_at_cpm(const rtems_irq_symbolic_name irqLine) int BSP_irq_disable_at_cpm(const rtems_irq_symbolic_name irqLine) { int cpm_irq_index; - + if (!is_cpm_irq(irqLine)) return 1; - + cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << cpm_irq_index); @@ -144,10 +144,10 @@ int BSP_irq_disable_at_cpm(const rtems_irq_symbolic_name irqLine) int BSP_irq_enabled_at_cpm(const rtems_irq_symbolic_name irqLine) { int cpm_irq_index; - + if (!is_cpm_irq(irqLine)) return 0; - + cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); return (((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr & (1 << cpm_irq_index)); } @@ -155,7 +155,7 @@ int BSP_irq_enabled_at_cpm(const rtems_irq_symbolic_name irqLine) int BSP_irq_enable_at_siu(const rtems_irq_symbolic_name irqLine) { int siu_irq_index; - + if (!is_siu_irq(irqLine)) return 1; @@ -172,7 +172,7 @@ int BSP_irq_disable_at_siu(const rtems_irq_symbolic_name irqLine) if (!is_siu_irq(irqLine)) return 1; - + siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); ppc_cached_irq_mask &= ~(1 << (31-siu_irq_index)); ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; @@ -198,7 +198,7 @@ int BSP_irq_enabled_at_siu (const rtems_irq_symbolic_name irqLine) int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) { unsigned int level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -219,14 +219,14 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) * store the data provided by user */ rtems_hdl_tbl[irq->name] = *irq; - + if (is_cpm_irq(irq->name)) { /* * Enable interrupt at PIC level */ BSP_irq_enable_at_cpm (irq->name); } - + if (is_siu_irq(irq->name)) { /* * Enable interrupt at SIU level @@ -244,7 +244,7 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) * Enable interrupt on device */ irq->on(irq); - + _CPU_ISR_Enable(level); return 1; @@ -263,7 +263,7 @@ int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) { unsigned int level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -295,7 +295,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) /* * disable exception at processor level */ - } + } /* * Disable interrupt on device @@ -411,7 +411,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + rtems_hdl_tbl[BSP_DECREMENTER].hdl(); _CPU_MSR_SET(msr); @@ -422,12 +422,12 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) */ #ifdef DISPATCH_HANDLER_STAT loopCounter = 0; -#endif +#endif while (1) { if ((ppc_cached_irq_mask & ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend) == 0) { #ifdef DISPATCH_HANDLER_STAT if (loopCounter > maxLoop) maxLoop = loopCounter; -#endif +#endif break; } irq = (((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec >> 26); @@ -442,12 +442,12 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) * Acknowledge current interrupt. This has no effect on internal level interrupt. */ ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = (1 << (31 - irq)); - + if (cpmIntr) { /* * We will reenable the SIU CPM interrupt to allow nesting of CPM interrupt. * We must before acknowledege the current irq at CPM level to avoid trigerring - * the interrupt again. + * the interrupt again. */ /* * Acknowledge and get the vector. @@ -467,7 +467,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + rtems_hdl_tbl[irq].hdl(); _CPU_MSR_SET(msr); @@ -480,12 +480,12 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; #ifdef DISPATCH_HANDLER_STAT ++ loopCounter; -#endif +#endif } } - - + + void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) { /* diff --git a/c/src/lib/libbsp/powerpc/eth_comm/irq/irq.h b/c/src/lib/libbsp/powerpc/eth_comm/irq/irq.h index 6b30b759e9..635ee42fb8 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/irq/irq.h +++ b/c/src/lib/libbsp/powerpc/eth_comm/irq/irq.h @@ -69,7 +69,7 @@ typedef enum { * Some SIU IRQ symbolic name definition. Please note that * INT IRQ are defined but a single one will be used to * redirect all CPM interrupt. - */ + */ BSP_SIU_EXT_IRQ_0 = 0, BSP_SIU_INT_IRQ_0 = 1, @@ -78,19 +78,19 @@ typedef enum { BSP_SIU_EXT_IRQ_2 = 4, BSP_SIU_INT_IRQ_2 = 5, - + BSP_SIU_EXT_IRQ_3 = 6, BSP_SIU_INT_IRQ_3 = 7, - + BSP_SIU_EXT_IRQ_4 = 8, BSP_SIU_INT_IRQ_4 = 9, BSP_SIU_EXT_IRQ_5 = 10, BSP_SIU_INT_IRQ_5 = 11, - + BSP_SIU_EXT_IRQ_6 = 12, BSP_SIU_INT_IRQ_6 = 13, - + BSP_SIU_EXT_IRQ_7 = 14, BSP_SIU_INT_IRQ_7 = 15, /* @@ -110,18 +110,18 @@ typedef enum { BSP_CPM_IRQ_SPI = BSP_CPM_IRQ_LOWEST_OFFSET + 5, BSP_CPM_IRQ_PARALLEL_IO_PC6 = BSP_CPM_IRQ_LOWEST_OFFSET + 6, BSP_CPM_IRQ_TIMER_4 = BSP_CPM_IRQ_LOWEST_OFFSET + 7, - + BSP_CPM_IRQ_PARALLEL_IO_PC7 = BSP_CPM_IRQ_LOWEST_OFFSET + 9, BSP_CPM_IRQ_PARALLEL_IO_PC8 = BSP_CPM_IRQ_LOWEST_OFFSET + 10, BSP_CPM_IRQ_PARALLEL_IO_PC9 = BSP_CPM_IRQ_LOWEST_OFFSET + 11, BSP_CPM_IRQ_TIMER_3 = BSP_CPM_IRQ_LOWEST_OFFSET + 12, - + BSP_CPM_IRQ_PARALLEL_IO_PC10 = BSP_CPM_IRQ_LOWEST_OFFSET + 14, BSP_CPM_IRQ_PARALLEL_IO_PC11 = BSP_CPM_IRQ_LOWEST_OFFSET + 15, BSP_CPM_I2C = BSP_CPM_IRQ_LOWEST_OFFSET + 16, BSP_CPM_RISC_TIMER_TABLE = BSP_CPM_IRQ_LOWEST_OFFSET + 17, BSP_CPM_IRQ_TIMER_2 = BSP_CPM_IRQ_LOWEST_OFFSET + 18, - + BSP_CPM_IDMA2 = BSP_CPM_IRQ_LOWEST_OFFSET + 20, BSP_CPM_IDMA1 = BSP_CPM_IRQ_LOWEST_OFFSET + 21, BSP_CPM_SDMA_CHANNEL_BUS_ERR = BSP_CPM_IRQ_LOWEST_OFFSET + 22, @@ -138,10 +138,10 @@ typedef enum { * Some Processor exception handled as rtems IRQ symbolic name definition */ BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET - + }rtems_irq_symbolic_name; -#define CPM_INTERRUPT +#define CPM_INTERRUPT /* @@ -171,9 +171,9 @@ typedef struct __rtems_irq_connect_data__ { * It is usually called immediately AFTER connecting the interrupt handler. * RTEMS may well need such a function when restoring normal interrupt * processing after a debug session. - * + * */ - rtems_irq_enable on; + rtems_irq_enable on; /* * function for disabling interrupts at device level (ONLY!). * The code will disable it at SIU and CPM level. RATIONALE : anyway @@ -209,7 +209,7 @@ typedef struct { rtems_irq_symbolic_name irqBase; /* * software priorities associated with interrupts. - * if irqPrio [i] > intrPrio [j] it means that + * if irqPrio [i] > intrPrio [j] it means that * interrupt handler hdl connected for interrupt name i * will not be interrupted by the handler connected for interrupt j * The interrupt source will be physically masked at i8259 level. @@ -285,7 +285,7 @@ int BSP_irq_enabled_at_siu (const rtems_irq_symbolic_name irqLine); * 4) perform rescheduling when necessary, * 5) restore the C scratch registers... * 6) restore initial execution flow - * + * */ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); /* @@ -328,7 +328,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config); * (Re) get info on current RTEMS interrupt management. */ int BSP_rtems_irq_mngt_get(rtems_irq_global_settings**); - + extern void BSP_rtems_irq_mng_init(unsigned cpuId); #ifdef __cplusplus diff --git a/c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S b/c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S index 095e75aa51..38c7d2283d 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S +++ b/c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S @@ -1,5 +1,5 @@ /* - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * IRQ veneers for RTEMS. * * The license and distribution terms for this file may be @@ -15,22 +15,22 @@ * * $Id$ */ - + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include <bsp/vectors.h> #include <libcpu/raw_exception.h> - + #define SYNC \ sync; \ isync - + .text - .p2align 5 - + .p2align 5 + PUBLIC_VAR(decrementer_exception_vector_prolog_code) - + SYM (decrementer_exception_vector_prolog_code): /* * let room for exception frame @@ -41,11 +41,11 @@ SYM (decrementer_exception_vector_prolog_code): ba shared_raw_irq_code_entry PUBLIC_VAR (decrementer_exception_vector_prolog_code_size) - + decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code PUBLIC_VAR(external_exception_vector_prolog_code) - + SYM (external_exception_vector_prolog_code): /* * let room for exception frame @@ -56,12 +56,12 @@ SYM (external_exception_vector_prolog_code): ba shared_raw_irq_code_entry PUBLIC_VAR (external_exception_vector_prolog_code_size) - + external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code PUBLIC_VAR(shared_raw_irq_code_entry) PUBLIC_VAR(C_dispatch_irq_handler) - + .p2align 5 SYM (shared_raw_irq_code_entry): /* @@ -72,17 +72,17 @@ SYM (shared_raw_irq_code_entry): * R4 : vector number */ /* - * Save SRR0/SRR1 As soon As possible as it is the minimal needed + * Save SRR0/SRR1 As soon As possible as it is the minimal needed * to reenable exception processing */ stw r0, GPR0_OFFSET(r1) stw r2, GPR2_OFFSET(r1) stw r3, GPR3_OFFSET(r1) - + mfsrr0 r0 mfsrr1 r2 mfmsr r3 - + stw r0, SRR0_FRAME_OFFSET(r1) stw r2, SRR1_FRAME_OFFSET(r1) /* @@ -119,7 +119,7 @@ SYM (shared_raw_irq_code_entry): mfctr r6 mfxer r7 mflr r8 - + stw r5, EXC_CR_OFFSET(r1) stw r6, EXC_CTR_OFFSET(r1) stw r7, EXC_XER_OFFSET(r1) @@ -157,9 +157,9 @@ SYM (shared_raw_irq_code_entry): cmpwi r2,0 bne nested mfspr r1, SPRG1 - -nested: - /* + +nested: + /* * Start Incrementing nesting level in R2 */ addi r2,r2,1 @@ -176,7 +176,7 @@ nested: /* store new nesting level in _ISR_Nest_level */ stw r2, _ISR_Nest_level@l(r7) #endif - + addi r6, r6, 1 mfmsr r5 /* @@ -186,7 +186,7 @@ nested: /* * We are now running on the interrupt stack. External and decrementer * exceptions are still disabled. I see no purpose trying to optimize - * further assembler code. + * further assembler code. */ /* * Call C exception handler for decrementer Interrupt frame is passed just @@ -195,7 +195,7 @@ nested: addi r3, r14, 0x8 bl C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */ /* - * start decrementing nesting level. Note : do not test result against 0 + * start decrementing nesting level. Note : do not test result against 0 * value as an easy exit condition because if interrupt nesting level > 1 * then _Thread_Dispatch_disable_level > 1 */ @@ -219,7 +219,7 @@ nested: stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */ cmpwi r3, 0 /* - * switch back to original stack (done here just optimize registers + * switch back to original stack (done here just optimize registers * contention. Could have been done before...) */ addi r1, r14, 0 @@ -227,14 +227,14 @@ nested: /* * Here we are running again on the thread system stack. * We have interrupt nesting level = _Thread_Dispatch_disable_level = 0. - * Interrupt are still disabled. Time to check if scheduler request to + * Interrupt are still disabled. Time to check if scheduler request to * do something with the current thread... */ addis r4, 0, _Context_Switch_necessary@ha lwz r5, _Context_Switch_necessary@l(r4) cmpwi r5, 0 bne switch - + addis r6, 0, _ISR_Signals_to_thread_executing@ha lwz r7, _ISR_Signals_to_thread_executing@l(r6) cmpwi r7, 0 @@ -266,12 +266,12 @@ nested: lwz r30, EXC_XER_OFFSET(r1) lwz r29, EXC_CR_OFFSET(r1) lwz r28, EXC_LR_OFFSET(r1) - + mtctr r31 mtxer r30 mtcr r29 mtlr r28 - + lmw r4, GPR4_OFFSET(r1) lwz r2, GPR2_OFFSET(r1) lwz r0, GPR0_OFFSET(r1) @@ -286,21 +286,21 @@ nested: /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC rfi - + switch: bl SYM (_Thread_Dispatch) - -easy_exit: + +easy_exit: /* * start restoring interrupt frame */ @@ -308,7 +308,7 @@ easy_exit: lwz r4, EXC_XER_OFFSET(r1) lwz r5, EXC_CR_OFFSET(r1) lwz r6, EXC_LR_OFFSET(r1) - + mtctr r3 mtxer r4 mtcr r5 @@ -337,7 +337,7 @@ easy_exit: /* * Restore rfi related settings */ - + lwz r4, SRR1_FRAME_OFFSET(r1) lwz r2, SRR0_FRAME_OFFSET(r1) lwz r3, GPR3_OFFSET(r1) diff --git a/c/src/lib/libbsp/powerpc/eth_comm/irq/irq_init.c b/c/src/lib/libbsp/powerpc/eth_comm/irq/irq_init.c index 9ff513766e..53a8fb8975 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/irq/irq_init.c +++ b/c/src/lib/libbsp/powerpc/eth_comm/irq/irq_init.c @@ -79,7 +79,7 @@ void BSP_SIU_irq_init() ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel = ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel; } -/* +/* * Initialize CPM interrupt management */ void @@ -93,7 +93,7 @@ BSP_CPM_irq_init(void) (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | #else (CICR_SCB_SCC2 | CICR_SCA_SCC1) | -#endif +#endif ((BSP_CPM_INTERRUPT/2) << 13) | CICR_HP_MASK; ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr = 0; @@ -104,7 +104,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) { rtems_raw_except_connect_data vectorDesc; int i; - + BSP_SIU_irq_init(); BSP_CPM_irq_init(); /* @@ -132,7 +132,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) */ BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); } - + /* * We must connect the raw irq handler for the two * expected interrupt sources : decrementer and external interrupts. @@ -154,7 +154,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) if (!mpc8xx_set_exception (&vectorDesc)) { BSP_panic("Unable to initialize RTEMS external raw exception\n"); } -#ifdef TRACE_IRQ_INIT +#ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operationnal\n"); #endif } diff --git a/c/src/lib/libbsp/powerpc/eth_comm/network/network.c b/c/src/lib/libbsp/powerpc/eth_comm/network/network.c index 5a280e4eae..4ed7a0daa1 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/network/network.c +++ b/c/src/lib/libbsp/powerpc/eth_comm/network/network.c @@ -142,9 +142,9 @@ static void m860_scc1_interrupt_handler () */ if ((m8xx.scc1.sccm & 0x8) && (m8xx.scc1.scce & 0x8)) { m8xx.scc1.scce = 0x8; - /* I don't think the next line is needed. It was in + /* I don't think the next line is needed. It was in * the 68360 stuff, though. - * m8xx.scc1.sccm &= ~0x8; + * m8xx.scc1.sccm &= ~0x8; */ enet_driver[0].rxInterrupts++; rtems_event_send (enet_driver[0].rxDaemonTid, INTERRUPT_EVENT); @@ -155,9 +155,9 @@ static void m860_scc1_interrupt_handler () */ if ((m8xx.scc1.sccm & 0x12) && (m8xx.scc1.scce & 0x12)) { m8xx.scc1.scce = 0x12; - /* I don't think the next line is needed. It was in + /* I don't think the next line is needed. It was in * the 68360 stuff, though. - * m8xx.scc1.sccm &= ~0x12; + * m8xx.scc1.sccm &= ~0x12; */ enet_driver[0].txInterrupts++; rtems_event_send (enet_driver[0].txDaemonTid, INTERRUPT_EVENT); @@ -177,7 +177,7 @@ static void m860_fec_interrupt_handler () enet_driver[0].rxInterrupts++; rtems_event_send (enet_driver[0].rxDaemonTid, INTERRUPT_EVENT); } - + /* * Buffer transmitted or transmitter error? */ @@ -203,17 +203,17 @@ m860_scc_initialize_hardware (struct m860_enet_struct *sc) { int i; unsigned char *hwaddr; - + /* * Configure port A CLK1, CLK2, TXD1 and RXD1 pins */ m8xx.papar |= 0x303; m8xx.padir &= ~0x303; m8xx.paodr &= ~0x303; - + /* * Configure port C CTS1* and CD1* pins, and PC4-PC7 - * + * */ m8xx.pcpar &= ~0x30; m8xx.pcdir |= 0x0f00; @@ -221,28 +221,28 @@ m860_scc_initialize_hardware (struct m860_enet_struct *sc) m8xx.pcso |= 0x30; m8xx.pcdat &= ~0x0f00; /* Clear LOOP */ m8xx.pcdat |= 0x0700; /* Set FULDL, TPSQEL, TPAPCE */ - + /* * Connect CLK1 and CLK2 to SCC1 */ m8xx.sicr &= ~0xFF; m8xx.sicr |= (5 << 3) | 4; - + /* * Initialize SDMA configuration register */ m8xx.sdcr = 1; - + /* * Allocate mbuf pointers */ - sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, + sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT); - sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, + sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT); if (!sc->rxMbuf || !sc->txMbuf) rtems_panic ("No memory for mbuf pointers",0); - + /* * Set receiver and transmitter buffer descriptor bases */ @@ -250,46 +250,46 @@ m860_scc_initialize_hardware (struct m860_enet_struct *sc) sc->txBdBase = m8xx_bd_allocate(sc->txBdCount); m8xx.scc1p.rbase = (char *)sc->rxBdBase - (char *)&m8xx; m8xx.scc1p.tbase = (char *)sc->txBdBase - (char *)&m8xx; - + /* * Send "Init parameters" command */ m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC1); - + /* * Set receive and transmit function codes */ m8xx.scc1p.rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0); m8xx.scc1p.tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0); - + /* * Set maximum receive buffer length */ m8xx.scc1p.mrblr = RBUF_SIZE; - + /* * Set CRC parameters */ m8xx.scc1p.un.ethernet.c_pres = 0xFFFFFFFF; m8xx.scc1p.un.ethernet.c_mask = 0xDEBB20E3; - + /* * Clear diagnostic counters */ m8xx.scc1p.un.ethernet.crcec = 0; m8xx.scc1p.un.ethernet.alec = 0; m8xx.scc1p.un.ethernet.disfc = 0; - + /* * Set pad value */ m8xx.scc1p.un.ethernet.pads = 0x8888; - + /* * Set retry limit */ m8xx.scc1p.un.ethernet.ret_lim = 15; - + /* * Set maximum and minimum frame length */ @@ -297,7 +297,7 @@ m860_scc_initialize_hardware (struct m860_enet_struct *sc) m8xx.scc1p.un.ethernet.minflr = 64; m8xx.scc1p.un.ethernet.maxd1 = RBUF_SIZE; m8xx.scc1p.un.ethernet.maxd2 = RBUF_SIZE; - + /* * Clear group address hash table */ @@ -305,21 +305,21 @@ m860_scc_initialize_hardware (struct m860_enet_struct *sc) m8xx.scc1p.un.ethernet.gaddr2 = 0; m8xx.scc1p.un.ethernet.gaddr3 = 0; m8xx.scc1p.un.ethernet.gaddr4 = 0; - + /* * Set our physical address */ hwaddr = sc->arpcom.ac_enaddr; - + m8xx.scc1p.un.ethernet.paddr_h = (hwaddr[5] << 8) | hwaddr[4]; m8xx.scc1p.un.ethernet.paddr_m = (hwaddr[3] << 8) | hwaddr[2]; m8xx.scc1p.un.ethernet.paddr_l = (hwaddr[1] << 8) | hwaddr[0]; - + /* * Aggressive retry */ m8xx.scc1p.un.ethernet.p_per = 0; - + /* * Clear individual address hash table */ @@ -327,14 +327,14 @@ m860_scc_initialize_hardware (struct m860_enet_struct *sc) m8xx.scc1p.un.ethernet.iaddr2 = 0; m8xx.scc1p.un.ethernet.iaddr3 = 0; m8xx.scc1p.un.ethernet.iaddr4 = 0; - + /* * Clear temp address */ m8xx.scc1p.un.ethernet.taddr_l = 0; m8xx.scc1p.un.ethernet.taddr_m = 0; m8xx.scc1p.un.ethernet.taddr_h = 0; - + /* * Set up receive buffer descriptors */ @@ -351,12 +351,12 @@ m860_scc_initialize_hardware (struct m860_enet_struct *sc) } sc->txBdHead = sc->txBdTail = 0; sc->txBdActiveCount = 0; - + /* * Clear any outstanding events */ m8xx.scc1.scce = 0xFFFF; - + /* * Set up interrupts */ @@ -364,20 +364,20 @@ m860_scc_initialize_hardware (struct m860_enet_struct *sc) rtems_panic ("Can't attach M8xx SCC1 interrupt handler\n",0); } m8xx.scc1.sccm = 0; /* No interrupts unmasked till necessary */ - + /* * Set up General SCC Mode Register * Ethernet configuration */ m8xx.scc1.gsmr_h = 0x0; m8xx.scc1.gsmr_l = 0x1088000c; - + /* * Set up data synchronization register * Ethernet synchronization pattern */ m8xx.scc1.dsr = 0xd555; - + /* * Set up protocol-specific mode register * No Heartbeat check @@ -395,13 +395,13 @@ m860_scc_initialize_hardware (struct m860_enet_struct *sc) * Disable full-duplex operation */ m8xx.scc1.psmr = 0x080A | (sc->acceptBroadcast ? 0 : 0x100); - + /* * Enable the TENA (RTS1*) pin */ m8xx.pcpar |= 0x1; m8xx.pcdir &= ~0x1; - + /* * Enable receiver and transmitter */ @@ -433,7 +433,7 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) */ m8xx.fec.ecntrl=0x1; - /* + /* * Put ethernet transciever in reset */ m8xx.pgcra |= 0x80; @@ -452,10 +452,10 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) /* * Set SIU interrupt level to LVL2 - * + * */ m8xx.fec.ivec = ((((unsigned) BSP_FAST_ETHERNET_CTRL)/2) << 29); - + /* * Set the TX and RX fifo sizes. For now, we'll split it evenly */ @@ -468,7 +468,7 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) * Set our physical address */ hwaddr = sc->arpcom.ac_enaddr; - + m8xx.fec.addr_low = (hwaddr[0] << 24) | (hwaddr[1] << 16) | (hwaddr[2] << 8) | (hwaddr[3] << 0); m8xx.fec.addr_high = (hwaddr[4] << 24) | (hwaddr[5] << 16); @@ -487,13 +487,13 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) /* * Allocate mbuf pointers */ - sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, + sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT); - sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, + sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT); if (!sc->rxMbuf || !sc->txMbuf) rtems_panic ("No memory for mbuf pointers",0); - + /* * Set receiver and transmitter buffer descriptor bases */ @@ -501,7 +501,7 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) sc->txBdBase = m8xx_bd_allocate(sc->txBdCount); m8xx.fec.r_des_start = (int)sc->rxBdBase; m8xx.fec.x_des_start = (int)sc->txBdBase; - + /* * Set up Receive Control Register: * Not promiscuous mode @@ -535,17 +535,17 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) m8xx.sdcr = 1; /* - * Set MII speed to 2.5 MHz for 25 Mhz system clock + * Set MII speed to 2.5 MHz for 25 Mhz system clock */ m8xx.fec.mii_speed = 0x0a; m8xx.fec.mii_data = 0x58021000; - + /* * Set up receive buffer descriptors */ for (i = 0 ; i < sc->rxBdCount ; i++) (sc->rxBdBase + i)->status = 0; - + /* * Set up transmit buffer descriptors */ @@ -555,13 +555,13 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) } sc->txBdHead = sc->txBdTail = 0; sc->txBdActiveCount = 0; - - + + /* * Mask all FEC interrupts and clear events */ - m8xx.fec.imask = M8xx_FEC_IEVENT_TFINT | + m8xx.fec.imask = M8xx_FEC_IEVENT_TFINT | M8xx_FEC_IEVENT_RFINT; m8xx.fec.ievent = ~0; @@ -589,7 +589,7 @@ m860Enet_retire_tx_bd (struct m860_enet_struct *sc) int i; int nRetired; struct mbuf *m, *n; - + i = sc->txBdTail; nRetired = 0; while ((sc->txBdActiveCount != 0) @@ -615,7 +615,7 @@ m860Enet_retire_tx_bd (struct m860_enet_struct *sc) enet_driver[0].txRetryLimit++; if (status & M8xx_BD_UNDERRUN) enet_driver[0].txUnderrun++; - + /* * Restart the transmitter */ @@ -661,7 +661,7 @@ scc_rxDaemon (void *arg) uint16_t status; m8xxBufferDescriptor_t *rxBd; int rxBdIndex; - + /* * Allocate space for incoming packets and start reception */ @@ -678,14 +678,14 @@ scc_rxDaemon (void *arg) break; } } - + /* * Input packet handling loop */ rxBdIndex = 0; for (;;) { rxBd = sc->rxBdBase + rxBdIndex; - + /* * Wait for packet if there's not one ready */ @@ -694,7 +694,7 @@ scc_rxDaemon (void *arg) * Clear old events */ m8xx.scc1.scce = 0x8; - + /* * Wait for packet * Note that the buffer descriptor is checked @@ -704,19 +704,19 @@ scc_rxDaemon (void *arg) */ while ((status = rxBd->status) & M8xx_BD_EMPTY) { rtems_event_set events; - + /* * Unmask RXF (Full frame received) event */ m8xx.scc1.sccm |= 0x8; - + rtems_bsdnet_event_receive (INTERRUPT_EVENT, RTEMS_WAIT|RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &events); } } - + /* * Check that packet is valid */ @@ -735,7 +735,7 @@ scc_rxDaemon (void *arg) * FIXME: Packet filtering hook could be done here. */ struct ether_header *eh; - + m = sc->rxMbuf[rxBdIndex]; m->m_len = m->m_pkthdr.len = rxBd->length - sizeof(uint32_t) - @@ -743,7 +743,7 @@ scc_rxDaemon (void *arg) eh = mtod (m, struct ether_header *); m->m_data += sizeof(struct ether_header); ether_input (ifp, eh, m); - + /* * Allocate a new mbuf */ @@ -774,13 +774,13 @@ scc_rxDaemon (void *arg) if (status & M8xx_BD_COLLISION) sc->rxCollision++; } - + /* * Reenable the buffer descriptor */ rxBd->status = (status & (M8xx_BD_WRAP | M8xx_BD_INTERRUPT)) | M8xx_BD_EMPTY; - + /* * Move to next buffer descriptor */ @@ -798,7 +798,7 @@ fec_rxDaemon (void *arg) uint16_t status; m8xxBufferDescriptor_t *rxBd; int rxBdIndex; - + /* * Allocate space for incoming packets and start reception */ @@ -816,14 +816,14 @@ fec_rxDaemon (void *arg) break; } } - + /* * Input packet handling loop */ rxBdIndex = 0; for (;;) { rxBd = sc->rxBdBase + rxBdIndex; - + /* * Wait for packet if there's not one ready */ @@ -832,7 +832,7 @@ fec_rxDaemon (void *arg) * Clear old events */ m8xx.fec.ievent = M8xx_FEC_IEVENT_RFINT; - + /* * Wait for packet * Note that the buffer descriptor is checked @@ -842,19 +842,19 @@ fec_rxDaemon (void *arg) */ while ((status = rxBd->status) & M8xx_BD_EMPTY) { rtems_event_set events; - + /* * Unmask RXF (Full frame received) event */ m8xx.fec.ievent |= M8xx_FEC_IEVENT_RFINT; - + rtems_bsdnet_event_receive (INTERRUPT_EVENT, RTEMS_WAIT|RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &events); } } - + /* * Check that packet is valid */ @@ -864,7 +864,7 @@ fec_rxDaemon (void *arg) * FIXME: Packet filtering hook could be done here. */ struct ether_header *eh; - + m = sc->rxMbuf[rxBdIndex]; m->m_len = m->m_pkthdr.len = rxBd->length - sizeof(uint32_t) - @@ -872,7 +872,7 @@ fec_rxDaemon (void *arg) eh = mtod (m, struct ether_header *); m->m_data += sizeof(struct ether_header); ether_input (ifp, eh, m); - + /* * Allocate a new mbuf */ @@ -923,12 +923,12 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) struct mbuf *l = NULL; uint16_t status; int nAdded; - + /* * Free up buffer descriptors */ m860Enet_retire_tx_bd (sc); - + /* * Set up the transmit buffer descriptors. * No need to pad out short packets since the @@ -947,7 +947,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) * Clear old events */ m8xx.scc1.scce = 0x12; - + /* * Wait for buffer descriptor to become available. * Note that the buffer descriptors are checked @@ -963,7 +963,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) m860Enet_retire_tx_bd (sc); while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { rtems_event_set events; - + /* * Unmask TXB (buffer transmitted) and * TXE (transmitter error) events. @@ -976,13 +976,13 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) m860Enet_retire_tx_bd (sc); } } - + /* * Don't set the READY flag till the * whole packet has been readied. */ status = nAdded ? M8xx_BD_READY : 0; - + /* * FIXME: Why not deal with empty mbufs at at higher level? * The IP fragmentation routine in ip_output @@ -1016,7 +1016,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) if (l != NULL) l->m_next = m; } - + /* * Set the transmit buffer status. * Break out of the loop if this mbuf is the last in the frame. @@ -1043,12 +1043,12 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) /* struct mbuf *l = NULL; */ uint16_t status; int nAdded; - + /* * Free up buffer descriptors */ m860Enet_retire_tx_bd (sc); - + /* * Set up the transmit buffer descriptors. * No need to pad out short packets since the @@ -1067,7 +1067,7 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) * Clear old events */ m8xx.fec.ievent = M8xx_FEC_IEVENT_TFINT; - + /* * Wait for buffer descriptor to become available. * Note that the buffer descriptors are checked @@ -1083,7 +1083,7 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) m860Enet_retire_tx_bd (sc); while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { rtems_event_set events; - + /* * Unmask TXB (buffer transmitted) and * TXE (transmitter error) events. @@ -1096,13 +1096,13 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) m860Enet_retire_tx_bd (sc); } } - + /* * Don't set the READY flag till the * whole packet has been readied. */ status = nAdded ? M8xx_BD_READY : 0; - + /* * FIXME: Why not deal with empty mbufs at at higher level? * The IP fragmentation routine in ip_output @@ -1138,7 +1138,7 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) l->m_next = m; */ } - + /* * Set the transmit buffer status. * Break out of the loop if this mbuf is the last in the frame. @@ -1168,13 +1168,13 @@ scc_txDaemon (void *arg) struct ifnet *ifp = &sc->arpcom.ac_if; struct mbuf *m; rtems_event_set events; - + for (;;) { /* * Wait for packet */ rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, RTEMS_EVENT_ANY | RTEMS_WAIT, RTEMS_NO_TIMEOUT, &events); - + /* * Send packets till queue is empty */ @@ -1198,16 +1198,16 @@ fec_txDaemon (void *arg) struct ifnet *ifp = &sc->arpcom.ac_if; struct mbuf *m; rtems_event_set events; - + for (;;) { /* * Wait for packet */ - rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, - RTEMS_EVENT_ANY | RTEMS_WAIT, - RTEMS_NO_TIMEOUT, + rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, + RTEMS_EVENT_ANY | RTEMS_WAIT, + RTEMS_NO_TIMEOUT, &events); - + /* * Send packets till queue is empty */ @@ -1231,7 +1231,7 @@ static void m860_enet_start (struct ifnet *ifp) { struct m860_enet_struct *sc = ifp->if_softc; - + rtems_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT); ifp->if_flags |= IFF_OACTIVE; } @@ -1244,22 +1244,22 @@ scc_init (void *arg) { struct m860_enet_struct *sc = arg; struct ifnet *ifp = &sc->arpcom.ac_if; - + if (sc->txDaemonTid == 0) { - + /* * Set up SCC hardware */ m860_scc_initialize_hardware (sc); - + /* * Start driver tasks */ sc->txDaemonTid = rtems_bsdnet_newproc ("SCtx", 4096, scc_txDaemon, sc); sc->rxDaemonTid = rtems_bsdnet_newproc ("SCrx", 4096, scc_rxDaemon, sc); - + } - + /* * Set flags appropriately */ @@ -1267,12 +1267,12 @@ scc_init (void *arg) m8xx.scc1.psmr |= 0x200; else m8xx.scc1.psmr &= ~0x200; - + /* * Tell the world that we're running. */ ifp->if_flags |= IFF_RUNNING; - + /* * Enable receiver and transmitter */ @@ -1284,22 +1284,22 @@ fec_init (void *arg) { struct m860_enet_struct *sc = arg; struct ifnet *ifp = &sc->arpcom.ac_if; - + if (sc->txDaemonTid == 0) { - + /* * Set up SCC hardware */ m860_fec_initialize_hardware (sc); - + /* * Start driver tasks */ sc->txDaemonTid = rtems_bsdnet_newproc ("SCtx", 4096, fec_txDaemon, sc); sc->rxDaemonTid = rtems_bsdnet_newproc ("SCrx", 4096, fec_rxDaemon, sc); - + } - + /* * Set flags appropriately */ @@ -1308,12 +1308,12 @@ fec_init (void *arg) else m8xx.fec.r_cntrl &= ~0x8; - + /* * Tell the world that we're running. */ ifp->if_flags |= IFF_RUNNING; - + /* * Enable receiver and transmitter */ @@ -1328,9 +1328,9 @@ static void scc_stop (struct m860_enet_struct *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; - + ifp->if_flags &= ~IFF_RUNNING; - + /* * Shut down receiver and transmitter */ @@ -1341,9 +1341,9 @@ static void fec_stop (struct m860_enet_struct *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; - + ifp->if_flags &= ~IFF_RUNNING; - + /* * Shut down receiver and transmitter */ @@ -1366,7 +1366,7 @@ enet_stats (struct m860_enet_struct *sc) printf (" Overrun:%-8lu", sc->rxOverrun); printf (" Collision:%-8lu\n", sc->rxCollision); printf (" Discarded:%-8lu\n", (unsigned long)m8xx.scc1p.un.ethernet.disfc); - + printf (" Tx Interrupts:%-8lu", sc->txInterrupts); printf (" Deferred:%-8lu", sc->txDeferred); printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat); @@ -1385,37 +1385,37 @@ scc_ioctl (struct ifnet *ifp, int command, caddr_t data) { struct m860_enet_struct *sc = ifp->if_softc; int error = 0; - + switch (command) { case SIOCGIFADDR: case SIOCSIFADDR: ether_ioctl (ifp, command, data); break; - + case SIOCSIFFLAGS: switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { case IFF_RUNNING: scc_stop (sc); break; - + case IFF_UP: scc_init (sc); break; - + case IFF_UP | IFF_RUNNING: scc_stop (sc); scc_init (sc); break; - + default: break; } break; - + case SIO_RTEMS_SHOW_STATS: enet_stats (sc); break; - + /* * FIXME: All sorts of multicast commands need to be added here! */ @@ -1431,37 +1431,37 @@ fec_ioctl (struct ifnet *ifp, int command, caddr_t data) { struct m860_enet_struct *sc = ifp->if_softc; int error = 0; - + switch (command) { case SIOCGIFADDR: case SIOCSIFADDR: ether_ioctl (ifp, command, data); break; - + case SIOCSIFFLAGS: switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { case IFF_RUNNING: fec_stop (sc); break; - + case IFF_UP: fec_init (sc); break; - + case IFF_UP | IFF_RUNNING: fec_stop (sc); fec_init (sc); break; - + default: break; } break; - + case SIO_RTEMS_SHOW_STATS: enet_stats (sc); break; - + /* * FIXME: All sorts of multicast commands need to be added here! */ @@ -1482,7 +1482,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) struct ifnet *ifp; int mtu; int i; - + /* * Find a free driver */ @@ -1496,7 +1496,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) printf ("Too many SCC drivers.\n"); return 0; } - + /* * Process options */ @@ -1524,7 +1524,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) else sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF; sc->acceptBroadcast = !config->ignore_broadcast; - + /* * Set up network interface values */ @@ -1539,7 +1539,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; if (ifp->if_snd.ifq_maxlen == 0) ifp->if_snd.ifq_maxlen = ifqmaxlen; - + /* * Attach the interface */ @@ -1554,7 +1554,7 @@ rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) struct m860_enet_struct *sc; struct ifnet *ifp; int mtu; - + /* * Find a free driver */ @@ -1563,7 +1563,7 @@ rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) if (ifp->if_softc != NULL) return 0; - + /* * Process options */ @@ -1591,7 +1591,7 @@ rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) else sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF; sc->acceptBroadcast = !config->ignore_broadcast; - + /* * Set up network interface values */ @@ -1606,7 +1606,7 @@ rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; if (ifp->if_snd.ifq_maxlen == 0) ifp->if_snd.ifq_maxlen = ifqmaxlen; - + /* * Attach the interface */ diff --git a/c/src/lib/libbsp/powerpc/eth_comm/start/start.S b/c/src/lib/libbsp/powerpc/eth_comm/start/start.S index a281c11ad6..288b7f3cd9 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/start/start.S +++ b/c/src/lib/libbsp/powerpc/eth_comm/start/start.S @@ -39,7 +39,7 @@ * GDB likes to have debugging information for the entry veneer. * Here is some DWARF information. */ -/* +/* * There was some debugging info here, but I removed it because I * couldn't get it to work. It isn't really necessary as far as I * can tell. It should still be in the papyrus BSP. -Jay @@ -47,30 +47,30 @@ -/* +/* * On entry to download_entry, R3 will hold a pointer to a Board Info * Block (boardinfo_t). This should be copied as soon as possible * to the global M860_binfo. (The block should be copied, _NOT_ * the pointer) */ - .section ".entry" /* This might have to be the first thing in the + .section ".entry" /* This might have to be the first thing in the * text section. At one time, it had to be * first, but I don't believe it is true * andy more. */ PUBLIC_VAR (start) SYM(start): bl .startup -base_addr: +base_addr: /* * Parameters from linker */ -toc_pointer: +toc_pointer: .long s.got -bss_length: +bss_length: .long bss.size -bss_addr: +bss_addr: .long bss.start PUBLIC_VAR (text_addr) @@ -83,16 +83,16 @@ text_length: /* - * Initialization code + * Initialization code */ .startup: /* Get start address */ mflr r1 - + /* clear the bss section */ bl bssclr -/* +/* * Copy the Board Info Block */ .extern SYM(M860_binfo) diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c index da674ec747..3d830a9f6e 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c @@ -51,13 +51,13 @@ void bsp_libc_init( void *, uint32_t, int ); void BSP_panic(char *s) { printk("%s PANIC %s\n",_RTEMS_version, s); - __asm__ __volatile ("sc"); + __asm__ __volatile ("sc"); } void _BSP_Fatal_error(unsigned int v) { printk("%s PANIC ERROR %x\n",_RTEMS_version, v); - __asm__ __volatile ("sc"); + __asm__ __volatile ("sc"); } /* @@ -73,14 +73,14 @@ void _BSP_Fatal_error(unsigned int v) * not yet initialized. * */ - + void bsp_pretasking_hook(void) { extern int _end; uint32_t heap_start; - /* + /* * Let's check to see if the size of M860_binfo is what * it should be. It might not be if the info.h files * for RTEMS and the bootloader define boardinfo_t @@ -103,7 +103,7 @@ bsp_pretasking_hook(void) } /* set up a 256K heap */ bsp_libc_init((void *) heap_start, 256 * 1024, 0); - + #ifdef RTEMS_DEBUG rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); #endif @@ -121,7 +121,7 @@ void bsp_start(void) ppc_cpu_revision_t myCpuRevision; register unsigned char* intrStack; extern void cpu_init(void); - + /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... @@ -134,19 +134,19 @@ void bsp_start(void) /* * Initialize some SPRG registers related to irq handling */ - + intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE); _write_SPRG1((unsigned int)intrStack); /* Signal them that this BSP has fixed PR288 - eventually, this should go away */ _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); - + /* * Install our own set of exception vectors */ initialize_exceptions(); - + /* * Allocate the memory for the RTEMS Work Space. This can come from * a variety of places: hard coded address, malloc'ed from outside @@ -172,7 +172,7 @@ void bsp_start(void) } BSP_Configuration.work_space_start = (void *)ws_start; - BSP_Configuration.work_space_size = 512 * 1024; + BSP_Configuration.work_space_size = 512 * 1024; /* * initialize the CPU table for this BSP @@ -195,7 +195,7 @@ void bsp_start(void) /* * Since we are currently autodetecting whether to use SCC1 or * the FEC for ethernet, we set up a register in the ethernet - * transciever that is used for 10/100 Mbps ethernet now, so that + * transciever that is used for 10/100 Mbps ethernet now, so that * we can attempt to read it later in rtems_enet_driver_attach() */ m8xx.fec.mii_speed = 0x0a; @@ -212,6 +212,6 @@ void bsp_start(void) BSP_rtems_irq_mng_init(0); #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); -#endif +#endif } diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/cpuinit.c index 6049f37878..99355ea11e 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/startup/cpuinit.c +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/cpuinit.c @@ -1,8 +1,8 @@ -/* - * cpuinit.c - this file contains functions for initializing the CPU +/* + * cpuinit.c - this file contains functions for initializing the CPU * * Written by Jay Monkman (jmonkman@frasca.com) - * + * * $Id$ */ @@ -18,14 +18,14 @@ void cpu_init(void) { register unsigned long t1, t2; - /* Let's clear MSR[IR] and MSR[DR] */ + /* Let's clear MSR[IR] and MSR[DR] */ t2 = PPC_MSR_IR | PPC_MSR_DR; __asm__ volatile ( "mfmsr %0\n" "andc %0, %0, %1\n" "mtmsr %0\n" :"=r"(t1), "=r"(t2): "1"(t2)); - + t1 = M8xx_CACHE_CMD_UNLOCK; /* PUT_DC_CST(t1); */ PUT_IC_CST(t1); diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c index f226e56df9..adc3c0491d 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c @@ -1,7 +1,7 @@ -/* +/* * mmutlbtab.c - * - * This file defines the MMU_TLB_table for the eth_comm board. + * + * This file defines the MMU_TLB_table for the eth_comm board. * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -25,20 +25,20 @@ * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must * not have more than 32 lines in it! * - * We set up the virtual memory map so that virtual address of a + * We set up the virtual memory map so that virtual address of a * location is equal to its real address. */ MMU_TLB_table_t MMU_TLB_table[] = { /* - * DRAM: CS1, Start address 0x00000000, 8M, - * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * DRAM: CS1, Start address 0x00000000, 8M, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, * R/W,X for supervisor, no ASID comparison, not cache-inhibited. * EPN TWC RPN */ { 0x00000200, 0x0D, 0x000001FD } /* DRAM - PS=PS=8M */ }; -/* +/* * MMU_N_TLB_Table_Entries is defined here because the size of the * MMU_TLB_table is only known in this file. */ diff --git a/c/src/lib/libbsp/powerpc/eth_comm/vectors/vectors.S b/c/src/lib/libbsp/powerpc/eth_comm/vectors/vectors.S index 331c3e5f99..561f190225 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/vectors/vectors.S +++ b/c/src/lib/libbsp/powerpc/eth_comm/vectors/vectors.S @@ -2,26 +2,26 @@ * (c) 1999, Eric Valette valette@crf.canon.fr * * - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * exception veneers for RTEMS. * * $Id$ */ - + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include <bsp/vectors.h> - + #define SYNC \ sync; \ isync - + .text - .p2align 5 - + .p2align 5 + PUBLIC_VAR(default_exception_vector_code_prolog) SYM (default_exception_vector_code_prolog): /* @@ -34,7 +34,7 @@ SYM (default_exception_vector_code_prolog): stw r2, EXC_LR_OFFSET(r1) bl 0f 0: /* - * r3 = exception vector entry point + * r3 = exception vector entry point * (256 * vector number) + few instructions */ mflr r3 @@ -43,13 +43,13 @@ SYM (default_exception_vector_code_prolog): */ srwi r3,r3,8 ba push_normalized_frame - + PUBLIC_VAR (default_exception_vector_code_prolog_size) - + default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog - + .p2align 5 -PUBLIC_VAR (push_normalized_frame) +PUBLIC_VAR (push_normalized_frame) SYM (push_normalized_frame): stw r3, EXCEPTION_NUMBER_OFFSET(r1) stw r0, GPR0_OFFSET(r1) @@ -63,7 +63,7 @@ SYM (push_normalized_frame): * Saved a few line above : R0 * * Manual says that "stmw" instruction may be slower than - * series of individual "stw" but who cares about performance + * series of individual "stw" but who cares about performance * for the DEFAULT exception handler? */ stmw r4, GPR4_OFFSET(r1) /* save R4->R31 */ @@ -89,7 +89,7 @@ SYM (push_normalized_frame): ori r3,r3, MSR_RI | MSR_IR | MSR_DR mtmsr r3 SYNC - + /* * Call C exception handler */ @@ -130,12 +130,12 @@ SYM (push_normalized_frame): /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC diff --git a/c/src/lib/libbsp/powerpc/eth_comm/vectors/vectors.h b/c/src/lib/libbsp/powerpc/eth_comm/vectors/vectors.h index 8647d98ee4..3a366f5b83 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/vectors/vectors.h +++ b/c/src/lib/libbsp/powerpc/eth_comm/vectors/vectors.h @@ -1,4 +1,4 @@ -/* +/* * vectors.h Exception frame related contant and API. * * This include file describe the data structure and the functions implemented @@ -16,10 +16,10 @@ #define LIBBSP_POWERPC_ETH_COMM_VECTORS_H /* - * The callee (high level exception code written in C) + * The callee (high level exception code written in C) * will store the Link Registers (return address) at entry r1 + 4 !!!. * So let room for it!!!. - */ + */ #define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 #define SRR0_FRAME_OFFSET 8 #define SRR1_FRAME_OFFSET 12 @@ -81,7 +81,7 @@ extern int default_exception_vector_code_prolog_size; * zero, it performs more or less like memmove. No copy is performed if * source and destination addresses are equal. However the caches * are synchronized. Note that the size is always rounded up to the - * next mutiple of 4. + * next mutiple of 4. */ extern void * codemove(void *, const void *, unsigned int, unsigned long); extern void initialize_exceptions(); diff --git a/c/src/lib/libbsp/powerpc/eth_comm/vectors/vectors_init.c b/c/src/lib/libbsp/powerpc/eth_comm/vectors/vectors_init.c index 332da08eda..489f9d5054 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/vectors/vectors_init.c +++ b/c/src/lib/libbsp/powerpc/eth_comm/vectors/vectors_init.c @@ -1,4 +1,4 @@ -/* +/* * vectors_init.c Exception hanlding initialisation (and generic handler). * * This include file describe the data structure and the functions implemented @@ -26,7 +26,7 @@ exception_handler_t globalExceptHdl; void C_exception_handler(BSP_Exception_frame* excPtr) { int recoverable = 0; - + printk("exception handler called for exception %d\n", excPtr->_EXC_number); printk("\t Next PC or Address of fault = %x\n", excPtr->EXC_SRR0); printk("\t Saved MSR = %x\n", excPtr->EXC_SRR1); @@ -70,7 +70,7 @@ void C_exception_handler(BSP_Exception_frame* excPtr) if (excPtr->_EXC_number == ASM_DEC_VECTOR) recoverable = 1; if (excPtr->_EXC_number == ASM_SYS_VECTOR) -#ifdef TEST_RAW_EXCEPTION_CODE +#ifdef TEST_RAW_EXCEPTION_CODE recoverable = 1; #else recoverable = 0; diff --git a/c/src/lib/libbsp/powerpc/gen405/dlentry/dlentry.S b/c/src/lib/libbsp/powerpc/gen405/dlentry/dlentry.S index 97ca329573..bc9c28cdd0 100644 --- a/c/src/lib/libbsp/powerpc/gen405/dlentry/dlentry.S +++ b/c/src/lib/libbsp/powerpc/gen405/dlentry/dlentry.S @@ -7,9 +7,9 @@ * IMD Ingenieurbuero fuer Microcomputertechnik * * COPYRIGHT (c) 1998 by IMD - * + * * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP: + * This file has been derived from the papyrus BSP: * * This file contains the entry veneer for RTEMS programs * downloaded to Papyrus. @@ -31,8 +31,8 @@ * * $Id$ * - * derived from "helas403/dlentry.S": - * Id: dlentry.S,v 1.2 2000/08/02 16:30:57 joel Exp + * derived from "helas403/dlentry.S": + * Id: dlentry.S,v 1.2 2000/08/02 16:30:57 joel Exp */ #include <rtems/asm.h> @@ -52,7 +52,7 @@ * .text * .data * .bss - * see linker command file for section placement + * see linker command file for section placement * * The initial stack is set to stack.end * @@ -63,7 +63,7 @@ * GDB likes to have debugging information for the entry veneer. * Here was some DWARF information. IMD removed it, because we * could not check, whether it was still correct. Sorry. - + */ #if PPC_ASM == PPC_ASM_ELF @@ -75,20 +75,20 @@ PUBLIC_VAR (download_entry) SYM(download_entry): bl .startup -base_addr: +base_addr: /*--------------------------------------------------------------------------- * Parameters from linker *--------------------------------------------------------------------------*/ -toc_pointer: +toc_pointer: #if PPC_ASM == PPC_ASM_ELF .long s.got #else .long TOC[tc0] #endif -bss_length: +bss_length: .long bss.size -bss_addr: +bss_addr: .long bss.start stack_top: .long stack.end @@ -105,7 +105,7 @@ stack_top: .extern SYM(__vectors) lis r2,__vectors@h /* set EVPR exc. vector prefix */ - mtspr evpr,r2 + mtspr evpr,r2 /*------------------------------------------------------------------- * C_setup. diff --git a/c/src/lib/libbsp/powerpc/gen405/include/bsp.h b/c/src/lib/libbsp/powerpc/gen405/include/bsp.h index a50344ff63..a7eedd807e 100644 --- a/c/src/lib/libbsp/powerpc/gen405/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/gen405/include/bsp.h @@ -3,12 +3,12 @@ * This include file contains all GEN405 board IO definitions. * * derived from helas403/include/bsp.h: - * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp + * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp * Author: Thomas Doerfler <td@imd.m.isar.de> * IMD Ingenieurbuero fuer Microcomputertechnik * * COPYRIGHT (c) 1998 by IMD - * + * * Changes from IMD are covered by the original distributions terms. * This file has been derived from the papyrus BSP. * @@ -109,15 +109,15 @@ extern rtems_cpu_table Cpu_table; /* owned by BSP */ /* * Device Driver Table Entries */ - + /* * NOTE: Use the standard Console driver entry */ - + /* * NOTE: Use the standard Clock driver entry */ - + /* functions */ rtems_isr_entry set_vector( /* returns old vector */ diff --git a/c/src/lib/libbsp/powerpc/gen405/startup/bspstart.c b/c/src/lib/libbsp/powerpc/gen405/startup/bspstart.c index 82ac8f0ac1..97f70ec440 100644 --- a/c/src/lib/libbsp/powerpc/gen405/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/gen405/startup/bspstart.c @@ -13,9 +13,9 @@ * IMD Ingenieurbuero fuer Microcomputertechnik * * COPYRIGHT (c) 1998 by IMD - * + * * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP: + * This file has been derived from the papyrus BSP: * * Author: Andrew Bray <andy@i-cubed.co.uk> * @@ -45,7 +45,7 @@ * the above copyright notice and this notice appears in all * copies. IMD makes no representations about the suitability * of this software for any purpose. - * + * * Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/bspstart.c: * * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. @@ -63,7 +63,7 @@ #include <rtems/libio.h> #include <rtems/libcsupport.h> #include <ictrl.h> - + /* * The original table from the application and our copy of it with * some changes. @@ -81,7 +81,7 @@ void *bsp_ram_end = (void *)RAM_END; /* first addr behind avail. ram area */ /* Initialize whatever libc we are using * called from postdriver hook */ - + void bsp_postdriver_hook(void); void bsp_libc_init( void *, uint32_t, int ); @@ -90,7 +90,7 @@ void bsp_libc_init( void *, uint32_t, int ); * bsp_predriver_hook * * Before drivers are setup. - */ + */ void bsp_predriver_hook(void) { @@ -112,7 +112,7 @@ void bsp_predriver_hook(void) * not yet initialized. * */ - + void bsp_pretasking_hook(void) { extern int _end; @@ -133,13 +133,13 @@ void bsp_pretasking_hook(void) heap_size = heap_end - heap_start; bsp_libc_init((void *) heap_start, heap_size, 0); /* 64 * 1024 */ - + #ifdef RTEMS_DEBUG rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); #endif } - + /* * bsp_start @@ -162,11 +162,11 @@ void bsp_start( void ) * tell the RTEMS configuration where it is. This memory is * not malloc'ed. It is just "pulled from the air". */ - /* FIME: plan usage of RAM better: + /* FIME: plan usage of RAM better: - make top of ram dynamic, - take out some part for persistant log - - make rest of ram to heap... - -remove RAM_END from bsp.h, this cannot be valid... + - make rest of ram to heap... + -remove RAM_END from bsp.h, this cannot be valid... or must be a function call */ BSP_Configuration.work_space_start = (void *) @@ -181,7 +181,7 @@ void bsp_start( void ) Cpu_table.postdriver_hook = bsp_postdriver_hook; Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY; - Cpu_table.clicks_per_usec = 300; + Cpu_table.clicks_per_usec = 300; Cpu_table.serial_per_sec = 14625000; /* = (CPU Clock / UART Internal Clock Divisor) */ Cpu_table.serial_external_clock = 0; Cpu_table.timer_internal_clock = 1; diff --git a/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.S b/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.S index b2a3d16666..f0b8ee6738 100644 --- a/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.S +++ b/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.S @@ -7,9 +7,9 @@ * IMD Ingenieurbuero fuer Microcomputertechnik * * COPYRIGHT (c) 1998 by IMD - * + * * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP: + * This file has been derived from the papyrus BSP: * * This file contains the entry veneer for RTEMS programs * downloaded to Papyrus. @@ -49,7 +49,7 @@ * .text * .data * .bss - * see linker command file for section placement + * see linker command file for section placement * * The initial stack is set to stack.end * @@ -60,9 +60,9 @@ * GDB likes to have debugging information for the entry veneer. * Here was some DWARF information. IMD removed it, because we * could not check, whether it was still correct. Sorry. - + */ - + #if PPC_ASM == PPC_ASM_ELF .section .entry #else @@ -72,20 +72,20 @@ PUBLIC_VAR (download_entry) SYM(download_entry): bl .startup -base_addr: +base_addr: /*--------------------------------------------------------------------------- * Parameters from linker *--------------------------------------------------------------------------*/ -toc_pointer: +toc_pointer: #if PPC_ASM == PPC_ASM_ELF .long s.got #else .long TOC[tc0] #endif -bss_length: +bss_length: .long bss.size -bss_addr: +bss_addr: .long bss.start stack_top: .long stack.end @@ -103,7 +103,7 @@ stack_top: lis r2,__vectors@h /* set EVPR exc. vector prefix */ mtspr evpr,r2 - + /*------------------------------------------------------------------- * C_setup. *------------------------------------------------------------------*/ diff --git a/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S b/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S index d5db474d54..d11babaa93 100644 --- a/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S +++ b/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S @@ -1,15 +1,15 @@ /* flashentry.s * * This file contains the entry code for RTEMS programs starting - * directly from Flash. + * directly from Flash. * * Author: Thomas Doerfler <td@imd.m.isar.de> * IMD Ingenieurbuero fuer Microcomputertechnik * * COPYRIGHT (c) 1998 by IMD - * + * * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP: + * This file has been derived from the papyrus BSP: * * This file contains the entry veneer for RTEMS programs * stored in Papyrus' flash ROM. @@ -39,7 +39,7 @@ * Reset_entry. *---------------------------------------------------------------------------*/ #if PPC_ASM == PPC_ASM_ELF - .section .reset,"ax",@progbits + .section .reset,"ax",@progbits /* this section MUST be located at absolute address 0xFFFFFFFC or last word of EPROM */ #else @@ -49,7 +49,7 @@ ba flash_entry /* this is the first instruction after reset */ .previous - + /*---------------------------------------------------------------------------- * ROM Vector area. *---------------------------------------------------------------------------*/ @@ -71,23 +71,23 @@ toc_pointer: #else .long TOC[tc0] #endif -text_length: +text_length: .long text.size text_addr: .long text.start -copy_src: +copy_src: .long copy.src copy_length: .long copy.size -copy_dest: +copy_dest: .long copy.dest -bss_length: +bss_length: .long bss.size -bss_addr: +bss_addr: .long bss.start stack_top: .long stack.end - + /*---------------------------------------------------------------------------- * from Reset_entry. *---------------------------------------------------------------------------*/ @@ -99,12 +99,12 @@ stack_top: /* set up bank register BR0 for Flash-EPROM: * NOTE: bank size should stay 1MByte, this is standard size * after RESET - * base addr = Fffxxxxx -> 0b11111111........................ + * base addr = Fffxxxxx -> 0b11111111........................ * bank size = 1 MByte -> 0b........000..................... (std) * bank use = readonly -> 0b...........01................... - * seq. fill = targ frst-> 0b.............0.................. + * seq. fill = targ frst-> 0b.............0.................. * burst mode= enable -> 0b..............1................. - * bus width = 8 bit -> 0b...............00............... + * bus width = 8 bit -> 0b...............00............... * ready pin = disable -> 0b.................0.............. * first wait= 2 clocks -> 0b..................0010.......... * burst wait= 2 clocks -> 0b......................10........ @@ -130,12 +130,12 @@ stack_top: * test RAM config 16 MByte (1x4Mx32Bit) *------------------------------------------------------------------*/ /* set up bank register BR7 for DRAM: - * base addr = 000xxxxx -> 0b00000000........................ + * base addr = 000xxxxx -> 0b00000000........................ * bank size = 16MByte -> 0b........100..................... * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. + * seq. fill = targ.frst-> 0b.............0.................. * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... + * bus width = 32bit -> 0b...............10............... * adr mux = internal -> 0b.................0.............. * RAS to CAS= 2 clocks -> 0b..................1............. * Alt. Rfrsh= normal -> 0b...................0............ @@ -151,7 +151,7 @@ stack_top: */ lis r2,0x0099 ori r2,r2,0x2AB0 - mtdcr br7,r2 /* write to DCR BR7*/ + mtdcr br7,r2 /* write to DCR BR7*/ lis r2,0x0000 /* start address = 0x00000000 */ lis r3,0x0100 /* size 16 MB = 0x01000000 */ @@ -163,13 +163,13 @@ stack_top: * test RAM config 32 MByte (2x4Mx32Bit) *------------------------------------------------------------------*/ /* set up bank register BR7 like above - * set up bank register BR6 for DRAM: - * base addr = 010xxxxx -> 0b00010000........................ + * set up bank register BR6 for DRAM: + * base addr = 010xxxxx -> 0b00010000........................ * bank size = 16MByte -> 0b........100..................... (for now) * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. + * seq. fill = targ.frst-> 0b.............0.................. * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... + * bus width = 32bit -> 0b...............10............... * adr mux = internal -> 0b.................0.............. * RAS to CAS= 2 clocks -> 0b..................1............. * Alt. Rfrsh= normal -> 0b...................0............ @@ -185,29 +185,29 @@ stack_top: */ lis r2,0x1099 ori r2,r2,0x2AB0 - mtdcr br6,r2 /* write to DCR BR6*/ + mtdcr br6,r2 /* write to DCR BR6*/ lis r2,0x0100 /* start address = 0x01000000 */ lis r3,0x0100 /* size 16 MB = 0x01000000 */ bl ramacc /* test memory accessibility */ cmpi 0,0,r4,0 /* memory ok? else test smaller size */ beq ramcfgok /* ok, we found configuration... +/ - + lis r2,0x0000 /* disable BR6, config not ok */ - mtdcr br6,r2 /* write to DCR BR6*/ + mtdcr br6,r2 /* write to DCR BR6*/ b ramcfgok /* and finish configuration */ - -ramcfgt18: + +ramcfgt18: /*-------------------------------------------------------------------- * test RAM config 8 MByte (1x2Mx32Bit) *------------------------------------------------------------------*/ /* set up bank register BR7 for DRAM: - * base addr = 000xxxxx -> 0b00000000........................ + * base addr = 000xxxxx -> 0b00000000........................ * bank size = 8MByte -> 0b........011..................... * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. + * seq. fill = targ.frst-> 0b.............0.................. * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... + * bus width = 32bit -> 0b...............10............... * adr mux = internal -> 0b.................0.............. * RAS to CAS= 2 clocks -> 0b..................1............. * Alt. Rfrsh= normal -> 0b...................0............ @@ -223,7 +223,7 @@ ramcfgt18: */ lis r2,0x0079 ori r2,r2,0x2AB0 - mtdcr br7,r2 /* write to DCR BR7 */ + mtdcr br7,r2 /* write to DCR BR7 */ lis r2,0x0000 /* start address = 0x00000000 */ lis r3,0x0080 /* size 8 MB = 0x00800000 */ @@ -235,13 +235,13 @@ ramcfgt18: * test RAM config 16 MByte (2x2Mx32Bit) *------------------------------------------------------------------*/ /* set up bank register BR7 like above - * set up bank register BR6 for DRAM: - * base addr = 008xxxxx -> 0b00001000........................ + * set up bank register BR6 for DRAM: + * base addr = 008xxxxx -> 0b00001000........................ * bank size = 08MByte -> 0b........011..................... (for now) * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. + * seq. fill = targ.frst-> 0b.............0.................. * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... + * bus width = 32bit -> 0b...............10............... * adr mux = internal -> 0b.................0.............. * RAS to CAS= 2 clocks -> 0b..................1............. * Alt. Rfrsh= normal -> 0b...................0............ @@ -257,29 +257,29 @@ ramcfgt18: */ lis r2,0x0879 ori r2,r2,0x2AB0 - mtdcr br6,r2 /* write to DCR BR6*/ + mtdcr br6,r2 /* write to DCR BR6*/ lis r2,0x0080 /* start address = 0x00800000 */ lis r3,0x0080 /* size 8 MB = 0x00800000 */ bl ramacc /* test memory accessibility */ cmpi 0,0,r4,0 /* memory ok? else test smaller size */ beq ramcfgok /* ok, we found configuration... +/ - + lis r2,0x0000 /* disable BR6, config not ok */ - mtdcr br6,r2 /* write to DCR BR6*/ + mtdcr br6,r2 /* write to DCR BR6*/ b ramcfgok /* and finish configuration */ - -ramcfgt14: + +ramcfgt14: /*-------------------------------------------------------------------- * test RAM config 4 MByte (1x1Mx32Bit) *------------------------------------------------------------------*/ /* set up bank register BR7 for DRAM: - * base addr = 000xxxxx -> 0b00000000........................ + * base addr = 000xxxxx -> 0b00000000........................ * bank size = 4MByte -> 0b........010..................... * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. + * seq. fill = targ.frst-> 0b.............0.................. * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... + * bus width = 32bit -> 0b...............10............... * adr mux = internal -> 0b.................0.............. * RAS to CAS= 2 clocks -> 0b..................1............. * Alt. Rfrsh= normal -> 0b...................0............ @@ -299,19 +299,19 @@ ramcfgt14: */ lis r2,0x0059 ori r2,r2,0x2AB0 - mtdcr br7,r2 /* write to DCR BR7*/ + mtdcr br7,r2 /* write to DCR BR7*/ /*-------------------------------------------------------------------- * test RAM config 8 MByte (2x1Mx32Bit) *------------------------------------------------------------------*/ /* set up bank register BR7 like above - * set up bank register BR6 for DRAM: - * base addr = 004xxxxx -> 0b00000100........................ + * set up bank register BR6 for DRAM: + * base addr = 004xxxxx -> 0b00000100........................ * bank size = 4MByte -> 0b........010..................... (for now) * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. + * seq. fill = targ.frst-> 0b.............0.................. * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... + * bus width = 32bit -> 0b...............10............... * adr mux = internal -> 0b.................0.............. * RAS to CAS= 2 clocks -> 0b..................1............. * Alt. Rfrsh= normal -> 0b...................0............ @@ -327,19 +327,19 @@ ramcfgt14: */ lis r2,0x0459 ori r2,r2,0x2AB0 - mtdcr br6,r2 /* write to DCR BR6*/ + mtdcr br6,r2 /* write to DCR BR6*/ lis r2,0x0040 /* start address = 0x00400000 */ lis r3,0x0040 /* size 4 MB = 0x00400000 */ bl ramacc /* test memory accessibility */ cmpi 0,0,r4,0 /* memory ok? else test smaller size */ beq ramcfgok /* ok, we found configuration... +/ - + lis r2,0x0000 /* disable BR6, config not ok */ - mtdcr br6,r2 /* write to DCR BR6*/ + mtdcr br6,r2 /* write to DCR BR6*/ b ramcfgok /* and finish configuration */ -ramcfgok: +ramcfgok: /*-------------------------------------------------------------------- * init the DRAM where STACK+ DATA+ BBS will be placed. If this is OK * we will return here. @@ -350,24 +350,24 @@ ramcfgok: addi r2,0,PPC_I_CACHE/PPC_CACHE_ALIGNMENT mtctr r2 /* count the loops needed... */ xor r2,r2,r2 /* start at adr zero */ -icinvlp: +icinvlp: iccci 0,r2 addi r2,r2,PPC_CACHE_ALIGNMENT bdnz icinvlp - + addi r2,r0,PPC_D_CACHE/PPC_CACHE_ALIGNMENT mtctr r2 /* count the loops needed... */ xor r2,r2,r2 /* start at adr 0 */ -dcinvlp: +dcinvlp: dccci 0,r2 addi r2,r2,PPC_CACHE_ALIGNMENT bdnz dcinvlp /*-------------------------------------------------------------------- * Enable two 128MB cachable regions. * FEPROM is cachable at 0xFFF00000..0xFFFFFFFF - * DRAM is cachable at 0x00000000..0x00FFFFFF + * DRAM is cachable at 0x00000000..0x00FFFFFF * FEPROM is noncachable at 0x7FF00000..0x7FFFFFFF - * DRAM is noncachable at 0x80000000..0x80FFFFFF + * DRAM is noncachable at 0x80000000..0x80FFFFFF *-------------------------------------------------------------------*/ addis r2,r0,0x8000 addi r2,r2,0x0001 @@ -386,17 +386,17 @@ dcinvlp: lis r2,0x0000 /* do not allow critical IRQ */ ori r2,r2,0x0000 mtdcr exier, r2 /* disable all external IRQs */ - + addi r2,r0,-1 /* r2 = 0xffffffff */ mtdcr exisr, r2 /* clear all pendingdisable IRQs */ - + /*-------------------------------------------------------------------- * C_setup. *-------------------------------------------------------------------*/ lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */ - + addi r1,r1,-56 /* start stack at data_addr - 56 */ addi r3,r0,0x0 /* clear r3 */ stw r3, 0(r1) /* Clear stack chain */ @@ -452,7 +452,7 @@ ramacc: xor r4,r4,r4 /* r4 = 0 */ stw r4,0(r2) /* init ram at start address */ addi r4,r0,0x04 /* set start shift */ -ramaccf1: +ramaccf1: cmp 0,0,r4,r3 /* compare with length */ bge ramaccfx /* r4 >= r3? then finished */ add r5,r4,r2 /* get next address to fill */ @@ -463,7 +463,7 @@ ramaccf1: ramaccfx: lwz r4,0(r2) /* get memory at start adr */ blr - + #if PPC_ABI == PPC_ABI_POWEROPEN DESCRIPTOR (startup) diff --git a/c/src/lib/libbsp/powerpc/helas403/include/bsp.h b/c/src/lib/libbsp/powerpc/helas403/include/bsp.h index b55f35a041..56aff201e1 100644 --- a/c/src/lib/libbsp/powerpc/helas403/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/helas403/include/bsp.h @@ -6,7 +6,7 @@ * IMD Ingenieurbuero fuer Microcomputertechnik * * COPYRIGHT (c) 1998 by IMD - * + * * Changes from IMD are covered by the original distributions terms. * This file has been derived from the papyrus BSP. * @@ -106,15 +106,15 @@ extern rtems_cpu_table Cpu_table; /* owned by BSP */ /* * Device Driver Table Entries */ - + /* * NOTE: Use the standard Console driver entry */ - + /* * NOTE: Use the standard Clock driver entry */ - + /* functions */ rtems_isr_entry set_vector( /* returns old vector */ diff --git a/c/src/lib/libbsp/powerpc/helas403/startup/bspstart.c b/c/src/lib/libbsp/powerpc/helas403/startup/bspstart.c index e5f5d7bc94..a769b7c380 100644 --- a/c/src/lib/libbsp/powerpc/helas403/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/helas403/startup/bspstart.c @@ -13,9 +13,9 @@ * IMD Ingenieurbuero fuer Microcomputertechnik * * COPYRIGHT (c) 1998 by IMD - * + * * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP: + * This file has been derived from the papyrus BSP: * * Author: Andrew Bray <andy@i-cubed.co.uk> * @@ -45,7 +45,7 @@ * the above copyright notice and this notice appears in all * copies. IMD makes no representations about the suitability * of this software for any purpose. - * + * * Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/bspstart.c: * * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. @@ -61,7 +61,7 @@ #include <rtems/libio.h> #include <rtems/libcsupport.h> #include <ictrl.h> - + /* * The original table from the application and our copy of it with * some changes. @@ -79,7 +79,7 @@ void *bsp_ram_end = (void *)RAM_END; /* first addr behind avail. ram area */ /* Initialize whatever libc we are using * called from postdriver hook */ - + void bsp_postdriver_hook(void); void bsp_libc_init( void *, uint32_t, int ); @@ -88,7 +88,7 @@ void bsp_libc_init( void *, uint32_t, int ); * bsp_predriver_hook * * Before drivers are setup. - */ + */ void bsp_predriver_hook(void) { @@ -110,7 +110,7 @@ void bsp_predriver_hook(void) * not yet initialized. * */ - + void bsp_pretasking_hook(void) { extern int _end; @@ -121,12 +121,12 @@ void bsp_pretasking_hook(void) heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); bsp_libc_init((void *) heap_start, 64 * 1024, 0); - + #ifdef RTEMS_DEBUG rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); #endif } - + /* * bsp_start @@ -149,11 +149,11 @@ void bsp_start( void ) * tell the RTEMS configuration where it is. This memory is * not malloc'ed. It is just "pulled from the air". */ - /* FIME: plan usage of RAM better: + /* FIME: plan usage of RAM better: - make top of ram dynamic, - take out some part for persistant log - - make rest of ram to heap... - -remove RAM_END from bsp.h, this cannot be valid... + - make rest of ram to heap... + -remove RAM_END from bsp.h, this cannot be valid... or must be a function call */ BSP_Configuration.work_space_start = (void *) diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/clock/p_clock.c b/c/src/lib/libbsp/powerpc/mbx8xx/clock/p_clock.c index 4a79f81864..b4bf7ca93e 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/clock/p_clock.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/clock/p_clock.c @@ -28,7 +28,7 @@ static rtems_irq_connect_data clockIrqData = {BSP_PERIODIC_TIMER, (rtems_irq_enable)clockOn, (rtems_irq_disable)clockOff, (rtems_irq_is_enabled)clockIsOn}; - + int BSP_get_clock_irq_level() { /* @@ -65,6 +65,6 @@ int BSP_connect_clock_handler (rtems_irq_hdl hdl) clockIrqData.on = (rtems_irq_enable)clockOn; clockIrqData.off = (rtems_irq_enable)clockOff; clockIrqData.isOn = (rtems_irq_is_enabled)clockIsOn; - + return BSP_install_rtems_irq_handler (&clockIrqData); } diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c b/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c index 7716cf3a85..efb7c6853b 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c @@ -45,7 +45,7 @@ * Interrupt-driven I/O requires termios. * * TESTS: - * + * * TO RUN THE TESTS, USE POLLED I/O WITHOUT TERMIOS SUPPORT. Some tests * play with the interrupt masks and turn off I/O. Those tests will hang * when interrupt-driven I/O is used. Other tests, such as cdtest, do I/O @@ -55,16 +55,16 @@ * should all be fixed to work with interrupt-driven I/O and to * produce output in the expected sequence. Obviously, the termios test * requires termios support in the driver. - * + * * Set CONSOLE_MINOR to the appropriate device minor number in the * config file. This allows the RTEMS application console to be different * from the EPPBug debug console or the GDB port. - * + * * This driver handles all five available serial ports: it distinguishes * the sub-devices using minor device numbers. It is not possible to have * other protocols running on the other ports when this driver is used as * currently written. - * + * * Based on code (alloc860.c in eth_comm port) by * Jay Monkman (jmonkman@frasca.com), * Copyright (C) 1998 by Frasca International, Inc. @@ -118,7 +118,7 @@ static int _EPPCBug_pollRead( volatile int simask; /* We must read and write m8xx.simask */ int retval; ISR_Level level; - + struct { int clun; int dlun; @@ -126,7 +126,7 @@ static int _EPPCBug_pollRead( int nbytes_requested; int reserved; } volatile input_params; - + struct { int status; union { @@ -145,30 +145,30 @@ static int _EPPCBug_pollRead( retval = -1; input_params.clun = 0; - + switch( minor ) { - case SMC1_MINOR: + case SMC1_MINOR: input_params.dlun = 0; /* Should be 4, but doesn't work with EPPCBug 1.1 */ break; - case SMC2_MINOR: + case SMC2_MINOR: input_params.dlun = 5; break; - case SCC2_MINOR: + case SCC2_MINOR: input_params.dlun = 1; break; #ifdef mpc860 - case SCC3_MINOR: + case SCC3_MINOR: input_params.dlun = 2; break; - case SCC4_MINOR: + case SCC4_MINOR: input_params.dlun = 3; break; #endif - default: + default: input_params.dlun = 0; break; } - + _ISR_Disable( level ); simask = m8xx.simask; @@ -180,21 +180,21 @@ static int _EPPCBug_pollRead( :: "g" (&input_params), "g" (&output_params) : "3", "4", "10" ); if ( (output_params.status == 0) && output_params.u.stat.input_char_available) { - + /* Read the char and return it */ input_params.inbuf = &c; input_params.nbytes_requested = 1; - + asm volatile( "li 10,0x200 /* Code for .CIO_READ */\n\ mr 3, %0 /* Address of input_params */\n\ mr 4, %1 /* Address of output_params */\n\ - sc" /* Call EPPCBUG */ + sc" /* Call EPPCBUG */ :: "g" (&input_params), "g" (&output_params) : "3", "4", "10" ); if ( (output_params.status == 0) && output_params.u.read.nbytes_received) retval = (int)c; } - + m8xx.simask = simask; _ISR_Enable( level ); return retval; @@ -227,7 +227,7 @@ static int _EPPCBug_pollWrite( volatile int simask; int i, retval; ISR_Level level; - + struct { int clun; int dlun; @@ -235,7 +235,7 @@ static int _EPPCBug_pollWrite( int nbytes_to_output; int reserved; } volatile input_params; - + struct { int status; union { @@ -255,26 +255,26 @@ static int _EPPCBug_pollWrite( input_params.clun = 0; input_params.reserved = 0; - + switch( minor ) { - case SMC1_MINOR: + case SMC1_MINOR: input_params.dlun = 0; /* Should be 4, but doesn't work with EPPCBug 1.1 */ break; - case SMC2_MINOR: + case SMC2_MINOR: input_params.dlun = 5; break; - case SCC2_MINOR: + case SCC2_MINOR: input_params.dlun = 1; break; #ifdef mpc860 - case SCC3_MINOR: + case SCC3_MINOR: input_params.dlun = 2; break; - case SCC4_MINOR: + case SCC4_MINOR: input_params.dlun = 3; break; #endif - default: + default: input_params.dlun = 0; break; } @@ -291,7 +291,7 @@ static int _EPPCBug_pollWrite( asm volatile( "li 10,0x202 /* Code for .CIO_STAT */\n\ mr 3, %0 /* Address of input_params */\n\ mr 4, %1 /* Address of output_params */\n\ - sc" /* Call EPPCBUG */ + sc" /* Call EPPCBUG */ :: "g" (&input_params), "g" (&output_params) : "3", "4", "10" ); if (output_params.status) @@ -301,11 +301,11 @@ static int _EPPCBug_pollWrite( /* Output the characters until done */ input_params.outbuf = &buf[i]; input_params.nbytes_to_output = len - i; - + asm volatile( "li 10,0x201 /* Code for .CIO_WRITE */\n\ mr 3, %0 /* Address of input_params */\n\ mr 4, %1 /* Address of output_params */\n\ - sc" /* Call EPPCBUG */ + sc" /* Call EPPCBUG */ :: "g" (&input_params), "g" (&output_params) : "3", "4", "10" ); if (output_params.status) @@ -313,7 +313,7 @@ static int _EPPCBug_pollWrite( i += output_params.u.write.nbytes_sent; } - + /* Return something */ m8xx.simask = simask; _ISR_Enable( level ); @@ -361,7 +361,7 @@ static rtems_status_code do_poll_read( #if NVRAM_CONFIGURE == 1 int (*pollRead)( int minor ); - + if ( (nvram->console_mode & 0x06) == 0x04 ) pollRead = _EPPCBug_pollRead; else @@ -399,7 +399,7 @@ static rtems_status_code do_poll_read( * Output characters through polled I/O. Returns only once every character has * been sent. * - * CR is transmitted AFTER a LF on output. + * CR is transmitted AFTER a LF on output. * * Input parameters: * major - ignored. Should be the major number for this driver. @@ -427,7 +427,7 @@ static rtems_status_code do_poll_write( #if NVRAM_CONFIGURE == 1 int (*pollWrite)(int minor, const char *buf, int len); - + if ( (nvram->console_mode & 0x06) == 0x04 ) pollWrite = _EPPCBug_pollWrite; else @@ -468,8 +468,8 @@ static rtems_status_code do_poll_write( static void _BSP_output_char( char c ) { char cr = '\r'; - - /* + + /* * Can't rely on console_initialize having been called before this function * is used, so it may fail unless output is done through EPPC-Bug. */ @@ -489,8 +489,8 @@ static void _BSP_output_char( char c ) if( c == '\n' ) m8xx_uart_pollWrite( PRINTK_MINOR, &cr, 1 ); } - -#else + +#else #if PRINTK_IO_MODE == 2 #define PRINTK_WRITE _EPPCBug_pollWrite @@ -501,7 +501,7 @@ static void _BSP_output_char( char c ) PRINTK_WRITE( PRINTK_MINOR, &c, 1 ); if( c == '\n' ) PRINTK_WRITE( PRINTK_MINOR, &cr, 1 ); - + #endif } @@ -543,7 +543,7 @@ serial_init() bd_t *bd; bd = eppcbugInfo; - + cp = cpmp; sp = (smc_t*)&(cp->cp_smc[SMC_INDEX]); up = (smc_uart_t *)&cp->cp_dparam[PROFF_CONS]; @@ -723,14 +723,14 @@ rtems_device_driver console_initialize( { rtems_status_code status; rtems_device_minor_number console_minor; - + /* * Set up TERMIOS if needed */ #if NVRAM_CONFIGURE == 1 /* Use NVRAM info for configuration */ console_minor = nvram->console_printk_port & 0x07; - + if ( nvram->console_mode & 0x01 ) /* termios */ rtems_termios_initialize (); @@ -739,7 +739,7 @@ rtems_device_driver console_initialize( * Do common initialization. */ m8xx_uart_initialize(); - + /* * Do device-specific initialization */ @@ -750,12 +750,12 @@ rtems_device_driver console_initialize( if ( ((nvram->console_mode & 0x30) != 0x20) || (((nvram->console_printk_port & 0x30) >> 4) != SMC2_MINOR) ) - m8xx_uart_smc_initialize(SMC2_MINOR); /* /dev/tty1 */ + m8xx_uart_smc_initialize(SMC2_MINOR); /* /dev/tty1 */ if ( ((nvram->console_mode & 0x30) != 0x20) || (((nvram->console_printk_port & 0x30) >> 4) != SCC2_MINOR) ) m8xx_uart_scc_initialize(SCC2_MINOR); /* /dev/tty2 */ - + #ifdef mpc860 if ( ((nvram->console_mode & 0x30) != 0x20) || @@ -771,18 +771,18 @@ rtems_device_driver console_initialize( #else /* NVRAM_CONFIGURE != 1 */ console_minor = CONSOLE_MINOR; - + #if UARTS_USE_TERMIOS == 1 rtems_termios_initialize (); - + #endif /* UARTS_USE_TERMIOS */ - + /* * Do common initialization. */ m8xx_uart_initialize(); - + /* * Do device-specific initialization */ @@ -791,13 +791,13 @@ rtems_device_driver console_initialize( #endif #if PRINTK_IO_MODE != 2 || PRINTK_MINOR != SMC2_MINOR - m8xx_uart_smc_initialize(SMC2_MINOR); /* /dev/tty1 */ + m8xx_uart_smc_initialize(SMC2_MINOR); /* /dev/tty1 */ #endif #if PRINTK_IO_MODE != 2 || PRINTK_MINOR != SCC2_MINOR m8xx_uart_scc_initialize(SCC2_MINOR); /* /dev/tty2 */ #endif - + #ifdef mpc860 #if PRINTK_IO_MODE != 2 || PRINTK_MINOR != SCC3_MINOR @@ -818,31 +818,31 @@ rtems_device_driver console_initialize( status = rtems_io_register_name ("/dev/tty0", major, SMC1_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + status = rtems_io_register_name ("/dev/tty1", major, SMC2_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + status = rtems_io_register_name ("/dev/tty2", major, SCC2_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + #ifdef mpc860 status = rtems_io_register_name ("/dev/tty3", major, SCC3_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + status = rtems_io_register_name ("/dev/tty4", major, SCC4_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + #endif /* mpc860 */ - + /* Now register the RTEMS console */ status = rtems_io_register_name ("/dev/console", major, console_minor); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + return RTEMS_SUCCESSFUL; } @@ -881,12 +881,12 @@ rtems_device_driver console_open( 0 /* outputUsesInterrupts */ }; rtems_status_code sc; - - + + #if (NVRAM_CONFIGURE == 1) || \ ((NVRAM_CONFIGURE != 1) && (UARTS_USE_TERMIOS == 1) && \ (UARTS_IO_MODE == 1)) - + static const rtems_termios_callbacks intrCallbacks = { NULL, /* firstOpen */ NULL, /* lastClose */ @@ -898,13 +898,13 @@ rtems_device_driver console_open( 1 /* outputUsesInterrupts */ }; #endif - - if ( minor > NUM_PORTS-1 ) + + if ( minor > NUM_PORTS-1 ) return RTEMS_INVALID_NUMBER; #if NVRAM_CONFIGURE == 1 - /* Use NVRAM info for configuration */ + /* Use NVRAM info for configuration */ if ( nvram->console_mode & 0x01 ) { /* Use termios */ if ( (nvram->console_mode & 0x06) == 0x02 ) { @@ -923,7 +923,7 @@ rtems_device_driver console_open( else /* no termios -- default to polled I/O */ return RTEMS_SUCCESSFUL; - + #else /* NVRAM_CONFIGURE != 1 */ #if UARTS_USE_TERMIOS == 1 @@ -943,7 +943,7 @@ rtems_device_driver console_open( #endif /* UARTS_USE_TERMIOS != 1 */ return sc; - + #endif /* NVRAM_CONFIGURE != 1 */ } @@ -962,7 +962,7 @@ rtems_device_driver console_close( #if NVRAM_CONFIGURE == 1 - /* Use NVRAM info for configuration */ + /* Use NVRAM info for configuration */ if ( nvram->console_mode & 0x01 ) /* use termios */ return rtems_termios_close( arg ); @@ -996,7 +996,7 @@ rtems_device_driver console_read( #if NVRAM_CONFIGURE == 1 - /* Use NVRAM info for configuration */ + /* Use NVRAM info for configuration */ if ( nvram->console_mode & 0x01 ) /* use termios */ return rtems_termios_read( arg ); @@ -1030,7 +1030,7 @@ rtems_device_driver console_write( #if NVRAM_CONFIGURE == 1 - /* Use NVRAM info for configuration */ + /* Use NVRAM info for configuration */ if ( nvram->console_mode & 0x01 ) /* use termios */ return rtems_termios_write( arg ); @@ -1059,13 +1059,13 @@ rtems_device_driver console_control( rtems_device_minor_number minor, void *arg ) -{ +{ if ( minor > NUM_PORTS-1 ) return RTEMS_INVALID_NUMBER; #if NVRAM_CONFIGURE == 1 - /* Uuse NVRAM info for configuration */ + /* Uuse NVRAM info for configuration */ if ( nvram->console_mode & 0x01 ) /* termios */ return rtems_termios_ioctl( arg ); diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/ide/idecfg.c b/c/src/lib/libbsp/powerpc/mbx8xx/ide/idecfg.c index eb9f6c135b..6dee967b54 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/ide/idecfg.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/ide/idecfg.c @@ -45,5 +45,5 @@ ide_controller_bsp_table_t IDE_Controller_Table[] = { }; /* Number of rows in IDE_Controller_Table */ -unsigned long IDE_Controller_Count = +unsigned long IDE_Controller_Count = sizeof(IDE_Controller_Table)/sizeof(IDE_Controller_Table[0]); diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/ide/pcmcia_ide.c b/c/src/lib/libbsp/powerpc/mbx8xx/ide/pcmcia_ide.c index 6c6d2d368d..9e9d3069fc 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/ide/pcmcia_ide.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/ide/pcmcia_ide.c @@ -33,8 +33,8 @@ /* #define DATAREG_16BIT */ /* 16 bit mode not yet working */ /* #define DEBUG_OUT */ -/* - * support functions for PCMCIA IDE IF +/* + * support functions for PCMCIA IDE IF */ /*=========================================================================*\ | Function: | @@ -55,11 +55,11 @@ boolean mbx8xx_pcmciaide_probe \*=========================================================================*/ { boolean ide_card_plugged = TRUE; /* assume: we have a card plugged in */ - + /* * check, that the CD# pins are low -> a PCMCIA card is plugged in */ - if ((m8xx.pipr + if ((m8xx.pipr & (M8xx_PCMCIA_PIPR_CACD1 | M8xx_PCMCIA_PIPR_CACD2)) != 0x00) { ide_card_plugged = FALSE; } @@ -79,7 +79,7 @@ boolean mbx8xx_pcmciaide_probe int cis_pos = 0; boolean fixed_disk_tuple_found = FALSE; boolean ata_disk_tuple_found = FALSE; - + while ((cis_pos < 256) && (CIS_BYTE(cis_pos) != 0xff) && (!fixed_disk_tuple_found || !ata_disk_tuple_found)) { @@ -95,10 +95,10 @@ boolean mbx8xx_pcmciaide_probe (CIS_BYTE(cis_pos+3) == 0x01)) { ata_disk_tuple_found = TRUE; } - /* - * advance using the length field + /* + * advance using the length field */ - cis_pos += CIS_BYTE(cis_pos+1)+2; + cis_pos += CIS_BYTE(cis_pos+1)+2; } ide_card_plugged = fixed_disk_tuple_found && ata_disk_tuple_found; } @@ -127,7 +127,7 @@ void mbx8xx_pcmciaide_initialize * FIXME: enable interrupts, if needed */ /* - * FIXME: set programming voltage as requested + * FIXME: set programming voltage as requested */ } @@ -155,14 +155,14 @@ void mbx8xx_pcmciaide_read_reg if (reg == IDE_REGISTER_DATA_WORD) { #ifdef DATAREG_16BIT - *value = *(volatile uint16_t*)(port+reg); + *value = *(volatile uint16_t*)(port+reg); #else - *value = ((*(volatile uint8_t*)(port+reg) << 8) + - (*(volatile uint8_t*)(port+reg+1) )); + *value = ((*(volatile uint8_t*)(port+reg) << 8) + + (*(volatile uint8_t*)(port+reg+1) )); #endif } else { - *value = *(volatile uint8_t*)(port+reg); + *value = *(volatile uint8_t*)(port+reg); } #ifdef DEBUG_OUT printk("mbx8xx_pcmciaide_read_reg(0x%x)=0x%x\r\n",reg,*value & 0xff); @@ -196,14 +196,14 @@ void mbx8xx_pcmciaide_write_reg #endif if (reg == IDE_REGISTER_DATA_WORD) { #ifdef DATAREG_16BIT - *(volatile uint16_t*)(port+reg) = value; + *(volatile uint16_t*)(port+reg) = value; #else - *(volatile uint8_t*)(port+reg) = value >> 8; - *(volatile uint8_t*)(port+reg+1) = value; + *(volatile uint8_t*)(port+reg) = value >> 8; + *(volatile uint8_t*)(port+reg+1) = value; #endif } else { - *(volatile uint8_t*)(port+reg)= value; + *(volatile uint8_t*)(port+reg)= value; } } @@ -218,9 +218,9 @@ void mbx8xx_pcmciaide_read_block +---------------------------------------------------------------------------+ | Input Parameters: | \*-------------------------------------------------------------------------*/ - int minor, - uint16_t block_size, - blkdev_sg_buffer *bufs, + int minor, + uint16_t block_size, + blkdev_sg_buffer *bufs, uint32_t *cbuf, uint32_t *pos ) @@ -242,17 +242,17 @@ void mbx8xx_pcmciaide_read_block ((uint8_t*)(bufs[(*cbuf)].buffer) + (*pos)); #endif uint32_t llength = bufs[(*cbuf)].length; - - while (((*(volatile uint8_t*)(port+IDE_REGISTER_STATUS)) - & IDE_REGISTER_STATUS_DRQ) && + + while (((*(volatile uint8_t*)(port+IDE_REGISTER_STATUS)) + & IDE_REGISTER_STATUS_DRQ) && (cnt < block_size)) { #ifdef DATAREG_16BIT *lbuf++ = *(volatile uint16_t*)(port+8); /* 16 bit data port */ - cnt += 2; + cnt += 2; (*pos) += 2; #else *lbuf++ = *(volatile uint8_t*)(port+IDE_REGISTER_DATA); - cnt += 1; + cnt += 1; (*pos) += 1; #endif if ((*pos) == llength) { @@ -261,7 +261,7 @@ void mbx8xx_pcmciaide_read_block lbuf = bufs[(*cbuf)].buffer; llength = bufs[(*cbuf)].length; } - } + } } /*=========================================================================*\ @@ -275,9 +275,9 @@ void mbx8xx_pcmciaide_write_block +---------------------------------------------------------------------------+ | Input Parameters: | \*-------------------------------------------------------------------------*/ - int minor, - uint16_t block_size, - blkdev_sg_buffer *bufs, + int minor, + uint16_t block_size, + blkdev_sg_buffer *bufs, uint32_t *cbuf, uint32_t *pos ) @@ -300,17 +300,17 @@ void mbx8xx_pcmciaide_write_block ((uint8_t*)(bufs[(*cbuf)].buffer) + (*pos)); #endif uint32_t llength = bufs[(*cbuf)].length; - - while (((*(volatile uint8_t*)(port+IDE_REGISTER_STATUS)) - & IDE_REGISTER_STATUS_DRQ) && + + while (((*(volatile uint8_t*)(port+IDE_REGISTER_STATUS)) + & IDE_REGISTER_STATUS_DRQ) && (cnt < block_size)) { #ifdef DATAREG_16BIT *(volatile uint16_t*)(port+8) = *lbuf++; /* 16 bit data port */ - cnt += 2; + cnt += 2; (*pos) += 2; #else *(volatile uint8_t*)(port+IDE_REGISTER_DATA) = *lbuf++; - cnt += 1; + cnt += 1; (*pos) += 1; #endif if ((*pos) == llength) { @@ -319,7 +319,7 @@ void mbx8xx_pcmciaide_write_block lbuf = bufs[(*cbuf)].buffer; llength = bufs[(*cbuf)].length; } - } + } } /*=========================================================================*\ @@ -368,7 +368,7 @@ rtems_status_code mbx8xx_pcmciaide_config_io_speed } /* - * The following table configures the functions used for IDE drivers + * The following table configures the functions used for IDE drivers * in this BSP. */ diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h b/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h index b86bbd8e31..9beb406672 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h @@ -107,7 +107,7 @@ extern rtems_configuration_table BSP_Configuration; /* * NOTE: Use the standard Console driver entry */ - + /* * NOTE: Use the standard Clock driver entry */ diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c index 1b8f8c2da1..2a5afa4569 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c @@ -10,7 +10,7 @@ * * $Id$ */ - + #include <rtems/system.h> #include <bsp.h> #include <bsp/irq.h> @@ -66,9 +66,9 @@ static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine) /* - * masks used to mask off the interrupts. For exmaple, for ILVL2, the - * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 - * and ILVL7. + * masks used to mask off the interrupts. For exmaple, for ILVL2, the + * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 + * and ILVL7. * */ const static unsigned int SIU_IvectMask[BSP_SIU_IRQ_NUMBER] = @@ -132,10 +132,10 @@ int BSP_irq_enable_at_cpm(const rtems_irq_symbolic_name irqLine) int BSP_irq_disable_at_cpm(const rtems_irq_symbolic_name irqLine) { int cpm_irq_index; - + if (!is_cpm_irq(irqLine)) return 1; - + cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << cpm_irq_index); @@ -145,10 +145,10 @@ int BSP_irq_disable_at_cpm(const rtems_irq_symbolic_name irqLine) int BSP_irq_enabled_at_cpm(const rtems_irq_symbolic_name irqLine) { int cpm_irq_index; - + if (!is_cpm_irq(irqLine)) return 0; - + cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); return (((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr & (1 << cpm_irq_index)); } @@ -156,7 +156,7 @@ int BSP_irq_enabled_at_cpm(const rtems_irq_symbolic_name irqLine) int BSP_irq_enable_at_siu(const rtems_irq_symbolic_name irqLine) { int siu_irq_index; - + if (!is_siu_irq(irqLine)) return 1; @@ -173,7 +173,7 @@ int BSP_irq_disable_at_siu(const rtems_irq_symbolic_name irqLine) if (!is_siu_irq(irqLine)) return 1; - + siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); ppc_cached_irq_mask &= ~(1 << (31-siu_irq_index)); ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; @@ -199,7 +199,7 @@ int BSP_irq_enabled_at_siu (const rtems_irq_symbolic_name irqLine) int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) { unsigned int level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -220,14 +220,14 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) * store the data provided by user */ rtems_hdl_tbl[irq->name] = *irq; - + if (is_cpm_irq(irq->name)) { /* * Enable interrupt at PIC level */ BSP_irq_enable_at_cpm (irq->name); } - + if (is_siu_irq(irq->name)) { /* * Enable interrupt at SIU level @@ -245,7 +245,7 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) * Enable interrupt on device */ irq->on(irq); - + _CPU_ISR_Enable(level); return 1; @@ -264,7 +264,7 @@ int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) { unsigned int level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -296,7 +296,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) /* * disable exception at processor level */ - } + } /* * Disable interrupt on device @@ -412,7 +412,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + rtems_hdl_tbl[BSP_DECREMENTER].hdl(); _CPU_MSR_SET(msr); @@ -423,12 +423,12 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) */ #ifdef DISPATCH_HANDLER_STAT loopCounter = 0; -#endif +#endif while (1) { if ((ppc_cached_irq_mask & ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend) == 0) { #ifdef DISPATCH_HANDLER_STAT if (loopCounter > maxLoop) maxLoop = loopCounter; -#endif +#endif break; } irq = (((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec >> 26); @@ -443,12 +443,12 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) * Acknowledge current interrupt. This has no effect on internal level interrupt. */ ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = (1 << (31 - irq)); - + if (cpmIntr) { /* * We will reenable the SIU CPM interrupt to allow nesting of CPM interrupt. * We must before acknowledege the current irq at CPM level to avoid trigerring - * the interrupt again. + * the interrupt again. */ /* * Acknowledge and get the vector. @@ -468,7 +468,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + rtems_hdl_tbl[irq].hdl(); _CPU_MSR_SET(msr); @@ -481,12 +481,12 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; #ifdef DISPATCH_HANDLER_STAT ++ loopCounter; -#endif +#endif } } - - + + void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) { /* diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h index a3b2f71f0c..49e720a6b5 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h +++ b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h @@ -69,7 +69,7 @@ typedef enum { * Some SIU IRQ symbolic name definition. Please note that * INT IRQ are defined but a single one will be used to * redirect all CPM interrupt. - */ + */ BSP_SIU_EXT_IRQ_0 = 0, BSP_SIU_INT_IRQ_0 = 1, @@ -78,19 +78,19 @@ typedef enum { BSP_SIU_EXT_IRQ_2 = 4, BSP_SIU_INT_IRQ_2 = 5, - + BSP_SIU_EXT_IRQ_3 = 6, BSP_SIU_INT_IRQ_3 = 7, - + BSP_SIU_EXT_IRQ_4 = 8, BSP_SIU_INT_IRQ_4 = 9, BSP_SIU_EXT_IRQ_5 = 10, BSP_SIU_INT_IRQ_5 = 11, - + BSP_SIU_EXT_IRQ_6 = 12, BSP_SIU_INT_IRQ_6 = 13, - + BSP_SIU_EXT_IRQ_7 = 14, BSP_SIU_INT_IRQ_7 = 15, /* @@ -110,18 +110,18 @@ typedef enum { BSP_CPM_IRQ_SPI = BSP_CPM_IRQ_LOWEST_OFFSET + 5, BSP_CPM_IRQ_PARALLEL_IO_PC6 = BSP_CPM_IRQ_LOWEST_OFFSET + 6, BSP_CPM_IRQ_TIMER_4 = BSP_CPM_IRQ_LOWEST_OFFSET + 7, - + BSP_CPM_IRQ_PARALLEL_IO_PC7 = BSP_CPM_IRQ_LOWEST_OFFSET + 9, BSP_CPM_IRQ_PARALLEL_IO_PC8 = BSP_CPM_IRQ_LOWEST_OFFSET + 10, BSP_CPM_IRQ_PARALLEL_IO_PC9 = BSP_CPM_IRQ_LOWEST_OFFSET + 11, BSP_CPM_IRQ_TIMER_3 = BSP_CPM_IRQ_LOWEST_OFFSET + 12, - + BSP_CPM_IRQ_PARALLEL_IO_PC10 = BSP_CPM_IRQ_LOWEST_OFFSET + 14, BSP_CPM_IRQ_PARALLEL_IO_PC11 = BSP_CPM_IRQ_LOWEST_OFFSET + 15, BSP_CPM_I2C = BSP_CPM_IRQ_LOWEST_OFFSET + 16, BSP_CPM_RISC_TIMER_TABLE = BSP_CPM_IRQ_LOWEST_OFFSET + 17, BSP_CPM_IRQ_TIMER_2 = BSP_CPM_IRQ_LOWEST_OFFSET + 18, - + BSP_CPM_IDMA2 = BSP_CPM_IRQ_LOWEST_OFFSET + 20, BSP_CPM_IDMA1 = BSP_CPM_IRQ_LOWEST_OFFSET + 21, BSP_CPM_SDMA_CHANNEL_BUS_ERR = BSP_CPM_IRQ_LOWEST_OFFSET + 22, @@ -138,10 +138,10 @@ typedef enum { * Some Processor exception handled as rtems IRQ symbolic name definition */ BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET - + }rtems_irq_symbolic_name; -#define CPM_INTERRUPT +#define CPM_INTERRUPT /* @@ -171,9 +171,9 @@ typedef struct __rtems_irq_connect_data__ { * It is usually called immediately AFTER connecting the interrupt handler. * RTEMS may well need such a function when restoring normal interrupt * processing after a debug session. - * + * */ - rtems_irq_enable on; + rtems_irq_enable on; /* * function for disabling interrupts at device level (ONLY!). * The code will disable it at SIU and CPM level. RATIONALE : anyway @@ -209,7 +209,7 @@ typedef struct { rtems_irq_symbolic_name irqBase; /* * software priorities associated with interrupts. - * if irqPrio [i] > intrPrio [j] it means that + * if irqPrio [i] > intrPrio [j] it means that * interrupt handler hdl connected for interrupt name i * will not be interrupted by the handler connected for interrupt j * The interrupt source will be physically masked at i8259 level. @@ -285,7 +285,7 @@ int BSP_irq_enabled_at_siu (const rtems_irq_symbolic_name irqLine); * 4) perform rescheduling when necessary, * 5) restore the C scratch registers... * 6) restore initial execution flow - * + * */ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); /* @@ -328,7 +328,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config); * (Re) get info on current RTEMS interrupt management. */ int BSP_rtems_irq_mngt_get(rtems_irq_global_settings**); - + extern void BSP_rtems_irq_mng_init(unsigned cpuId); #ifdef __cplusplus diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S index 1d3e1d2fcf..fa877aafaf 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S +++ b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S @@ -1,5 +1,5 @@ /* - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * IRQ veneers for RTEMS. * * The license and distribution terms for this file may be @@ -15,22 +15,22 @@ * * $Id$ */ - + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include <bsp/vectors.h> #include <libcpu/raw_exception.h> - + #define SYNC \ sync; \ isync - + .text - .p2align 5 - + .p2align 5 + PUBLIC_VAR(decrementer_exception_vector_prolog_code) - + SYM (decrementer_exception_vector_prolog_code): /* * let room for exception frame @@ -38,32 +38,32 @@ SYM (decrementer_exception_vector_prolog_code): stwu r1, - (EXCEPTION_FRAME_END)(r1) stw r4, GPR4_OFFSET(r1) #ifdef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE - /* + /* * save link register */ mflr r4 stw r4, EXC_LR_OFFSET(r1) - /* + /* * make link register contain shared_raw_irq_code_entry * address */ lis r4,shared_raw_irq_code_entry@h ori r4,r4,shared_raw_irq_code_entry@l mtlr r4 - + li r4, ASM_DEC_VECTOR blr #else li r4, ASM_DEC_VECTOR ba shared_raw_irq_code_entry -#endif +#endif PUBLIC_VAR (decrementer_exception_vector_prolog_code_size) - + decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code PUBLIC_VAR(external_exception_vector_prolog_code) - + SYM (external_exception_vector_prolog_code): /* * let room for exception frame @@ -71,12 +71,12 @@ SYM (external_exception_vector_prolog_code): stwu r1, - (EXCEPTION_FRAME_END)(r1) stw r4, GPR4_OFFSET(r1) #ifdef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE - /* + /* * save link register */ mflr r4 stw r4, EXC_LR_OFFSET(r1) - /* + /* * make link register contain shared_raw_irq_code_entry * address */ @@ -90,14 +90,14 @@ SYM (external_exception_vector_prolog_code): li r4, ASM_EXT_VECTOR ba shared_raw_irq_code_entry #endif - + PUBLIC_VAR (external_exception_vector_prolog_code_size) - + external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code PUBLIC_VAR(shared_raw_irq_code_entry) PUBLIC_VAR(C_dispatch_irq_handler) - + .p2align 5 SYM (shared_raw_irq_code_entry): /* @@ -108,17 +108,17 @@ SYM (shared_raw_irq_code_entry): * R4 : vector number */ /* - * Save SRR0/SRR1 As soon As possible as it is the minimal needed + * Save SRR0/SRR1 As soon As possible as it is the minimal needed * to reenable exception processing */ stw r0, GPR0_OFFSET(r1) stw r2, GPR2_OFFSET(r1) stw r3, GPR3_OFFSET(r1) - + mfsrr0 r0 mfsrr1 r2 mfmsr r3 - + stw r0, SRR0_FRAME_OFFSET(r1) stw r2, SRR1_FRAME_OFFSET(r1) /* @@ -157,14 +157,14 @@ SYM (shared_raw_irq_code_entry): #ifndef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE mflr r8 #endif - + stw r5, EXC_CR_OFFSET(r1) stw r6, EXC_CTR_OFFSET(r1) stw r7, EXC_XER_OFFSET(r1) -#ifndef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE +#ifndef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE stw r8, EXC_LR_OFFSET(r1) #endif - + /* * Add some non volatile registers to store information * that will be used when returning from C handler @@ -197,9 +197,9 @@ SYM (shared_raw_irq_code_entry): cmpwi r2,0 bne nested mfspr r1, SPRG1 - -nested: - /* + +nested: + /* * Start Incrementing nesting level in R2 */ addi r2,r2,1 @@ -216,7 +216,7 @@ nested: /* store new nesting level in _ISR_Nest_level */ stw r2, _ISR_Nest_level@l(r7) #endif - + addi r6, r6, 1 mfmsr r5 /* @@ -226,7 +226,7 @@ nested: /* * We are now running on the interrupt stack. External and decrementer * exceptions are still disabled. I see no purpose trying to optimize - * further assembler code. + * further assembler code. */ /* * Call C exception handler for decrementer Interrupt frame is passed just @@ -235,7 +235,7 @@ nested: addi r3, r14, 0x8 bl C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */ /* - * start decrementing nesting level. Note : do not test result against 0 + * start decrementing nesting level. Note : do not test result against 0 * value as an easy exit condition because if interrupt nesting level > 1 * then _Thread_Dispatch_disable_level > 1 */ @@ -259,7 +259,7 @@ nested: stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */ cmpwi r3, 0 /* - * switch back to original stack (done here just optimize registers + * switch back to original stack (done here just optimize registers * contention. Could have been done before...) */ addi r1, r14, 0 @@ -267,14 +267,14 @@ nested: /* * Here we are running again on the thread system stack. * We have interrupt nesting level = _Thread_Dispatch_disable_level = 0. - * Interrupt are still disabled. Time to check if scheduler request to + * Interrupt are still disabled. Time to check if scheduler request to * do something with the current thread... */ addis r4, 0, _Context_Switch_necessary@ha lwz r5, _Context_Switch_necessary@l(r4) cmpwi r5, 0 bne switch - + addis r6, 0, _ISR_Signals_to_thread_executing@ha lwz r7, _ISR_Signals_to_thread_executing@l(r6) cmpwi r7, 0 @@ -306,12 +306,12 @@ nested: lwz r30, EXC_XER_OFFSET(r1) lwz r29, EXC_CR_OFFSET(r1) lwz r28, EXC_LR_OFFSET(r1) - + mtctr r31 mtxer r30 mtcr r29 mtlr r28 - + lmw r4, GPR4_OFFSET(r1) lwz r2, GPR2_OFFSET(r1) lwz r0, GPR0_OFFSET(r1) @@ -326,21 +326,21 @@ nested: /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC rfi - + switch: bl SYM (_Thread_Dispatch) - -easy_exit: + +easy_exit: /* * start restoring interrupt frame */ @@ -348,7 +348,7 @@ easy_exit: lwz r4, EXC_XER_OFFSET(r1) lwz r5, EXC_CR_OFFSET(r1) lwz r6, EXC_LR_OFFSET(r1) - + mtctr r3 mtxer r4 mtcr r5 @@ -377,7 +377,7 @@ easy_exit: /* * Restore rfi related settings */ - + lwz r4, SRR1_FRAME_OFFSET(r1) lwz r2, SRR0_FRAME_OFFSET(r1) lwz r3, GPR3_OFFSET(r1) diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_init.c b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_init.c index 01d2d14cd4..98406a91b5 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_init.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_init.c @@ -80,7 +80,7 @@ void BSP_SIU_irq_init() ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel = ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel; } -/* +/* * Initialize CPM interrupt management */ void @@ -94,7 +94,7 @@ BSP_CPM_irq_init(void) (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | #else (CICR_SCB_SCC2 | CICR_SCA_SCC1) | -#endif +#endif ((BSP_CPM_INTERRUPT/2) << 13) | CICR_HP_MASK; ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr = 0; @@ -105,7 +105,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) { rtems_raw_except_connect_data vectorDesc; int i; - + BSP_SIU_irq_init(); BSP_CPM_irq_init(); /* @@ -133,7 +133,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) */ BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); } - + /* * We must connect the raw irq handler for the two * expected interrupt sources : decrementer and external interrupts. @@ -155,7 +155,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) if (!mpc8xx_set_exception (&vectorDesc)) { BSP_panic("Unable to initialize RTEMS external raw exception\n"); } -#ifdef TRACE_IRQ_INIT +#ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operationnal\n"); #endif } diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c b/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c index 1c2d20ec70..32c08798f5 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c @@ -7,7 +7,7 @@ * Right now, we only do 10 Mbps, even with the FEC. The function * rtems_enet_driver_attach determines which one to use. Currently, * only one may be used at a time. - * + * * Based on the MC68360 network driver by * W. Eric Norum * Saskatchewan Accelerator Laboratory @@ -180,7 +180,7 @@ static void m860_fec_interrupt_handler () enet_driver[0].rxInterrupts++; rtems_event_send (enet_driver[0].rxDaemonTid, INTERRUPT_EVENT); } - + /* * Buffer transmitted or transmitter error? */ @@ -208,7 +208,7 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) { int i; unsigned char *hwaddr; - + /* * Configure port A * PA15 is enet RxD. Set PAPAR(15) to 1, PADIR(15) to 0. @@ -219,7 +219,7 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) m8xx.papar |= 0x303; m8xx.padir &= ~0x303; m8xx.paodr &= ~0x2; - + /* * Configure port C * PC11 is CTS1*. Set PCPAR(11) to 0, PCDIR(11) to 0, and PCSO(11) to 1. @@ -228,7 +228,7 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) m8xx.pcpar &= ~0x30; m8xx.pcdir &= ~0x30; m8xx.pcso |= 0x30; - + /* * Connect CLK1 and CLK2 to SCC1 in the SICR. * CLK1 is TxClk, CLK2 is RxClk. No grant mechanism, SCC1 is directly @@ -237,22 +237,22 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) * T1CS = 0b100 (CLK1) */ m8xx.sicr |= 0x2C; - + /* * Initialize SDMA configuration register */ m8xx.sdcr = 1; - + /* * Allocate mbuf pointers */ - sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, + sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT); - sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, + sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT); if (!sc->rxMbuf || !sc->txMbuf) rtems_panic ("No memory for mbuf pointers"); - + /* * Set receiver and transmitter buffer descriptor bases */ @@ -260,46 +260,46 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) sc->txBdBase = m8xx_bd_allocate(sc->txBdCount); m8xx.scc1p.rbase = (char *)sc->rxBdBase - (char *)&m8xx; m8xx.scc1p.tbase = (char *)sc->txBdBase - (char *)&m8xx; - + /* * Send "Init parameters" command */ m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC1); - + /* * Set receive and transmit function codes */ m8xx.scc1p.rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0); m8xx.scc1p.tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0); - + /* * Set maximum receive buffer length */ m8xx.scc1p.mrblr = RBUF_SIZE; - + /* * Set CRC parameters */ m8xx.scc1p.un.ethernet.c_pres = 0xFFFFFFFF; m8xx.scc1p.un.ethernet.c_mask = 0xDEBB20E3; - + /* * Clear diagnostic counters */ m8xx.scc1p.un.ethernet.crcec = 0; m8xx.scc1p.un.ethernet.alec = 0; m8xx.scc1p.un.ethernet.disfc = 0; - + /* * Set pad value */ m8xx.scc1p.un.ethernet.pads = 0x8888; - + /* * Set retry limit */ m8xx.scc1p.un.ethernet.ret_lim = 15; - + /* * Set maximum and minimum frame length */ @@ -307,7 +307,7 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) m8xx.scc1p.un.ethernet.minflr = 64; m8xx.scc1p.un.ethernet.maxd1 = MAX_MTU_SIZE; m8xx.scc1p.un.ethernet.maxd2 = MAX_MTU_SIZE; - + /* * Clear group address hash table */ @@ -315,21 +315,21 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) m8xx.scc1p.un.ethernet.gaddr2 = 0; m8xx.scc1p.un.ethernet.gaddr3 = 0; m8xx.scc1p.un.ethernet.gaddr4 = 0; - + /* * Set our physical address */ hwaddr = sc->arpcom.ac_enaddr; - + m8xx.scc1p.un.ethernet.paddr_h = (hwaddr[5] << 8) | hwaddr[4]; m8xx.scc1p.un.ethernet.paddr_m = (hwaddr[3] << 8) | hwaddr[2]; m8xx.scc1p.un.ethernet.paddr_l = (hwaddr[1] << 8) | hwaddr[0]; - + /* * Aggressive retry */ m8xx.scc1p.un.ethernet.p_per = 0; - + /* * Clear individual address hash table */ @@ -337,14 +337,14 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) m8xx.scc1p.un.ethernet.iaddr2 = 0; m8xx.scc1p.un.ethernet.iaddr3 = 0; m8xx.scc1p.un.ethernet.iaddr4 = 0; - + /* * Clear temp address */ m8xx.scc1p.un.ethernet.taddr_l = 0; m8xx.scc1p.un.ethernet.taddr_m = 0; m8xx.scc1p.un.ethernet.taddr_h = 0; - + /* * Set up receive buffer descriptors */ @@ -361,12 +361,12 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) } sc->txBdHead = sc->txBdTail = 0; sc->txBdActiveCount = 0; - + /* * Clear any outstanding events */ m8xx.scc1.scce = 0xFFFF; - + /* * Set up interrupts */ @@ -374,20 +374,20 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) rtems_panic ("Can't attach M8xx SCC1 interrupt handler\n"); } m8xx.scc1.sccm = 0; /* No interrupts unmasked till necessary */ - + /* * Set up General SCC Mode Register * Ethernet configuration */ m8xx.scc1.gsmr_h = 0x0; m8xx.scc1.gsmr_l = 0x1088000c; - + /* * Set up data synchronization register * Ethernet synchronization pattern */ m8xx.scc1.dsr = 0xd555; - + /* * Set up protocol-specific mode register * No Heartbeat check @@ -405,13 +405,13 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) * Disable full-duplex operation */ m8xx.scc1.psmr = 0x080A | (sc->acceptBroadcast ? 0 : 0x100); - + /* * Enable the TENA (RTS1*) pin */ m8xx.pcpar |= 0x1; m8xx.pcdir &= ~0x1; - + /* * Enable receiver and transmitter */ @@ -452,7 +452,7 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) */ m8xx.fec.ecntrl=0x1; - /* + /* * Put ethernet transciever in reset */ m8xx.pgcra |= 0x80; @@ -471,10 +471,10 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) /* * Set SIU interrupt level to LVL2 - * + * */ m8xx.fec.ivec = ((((unsigned) BSP_FAST_ETHERNET_CTRL)/2) << 29); - + /* * Set the TX and RX fifo sizes. For now, we'll split it evenly */ @@ -487,7 +487,7 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) * Set our physical address */ hwaddr = sc->arpcom.ac_enaddr; - + m8xx.fec.addr_low = (hwaddr[0] << 24) | (hwaddr[1] << 16) | (hwaddr[2] << 8) | (hwaddr[3] << 0); m8xx.fec.addr_high = (hwaddr[4] << 24) | (hwaddr[5] << 16); @@ -506,13 +506,13 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) /* * Allocate mbuf pointers */ - sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, + sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT); - sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, + sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT); if (!sc->rxMbuf || !sc->txMbuf) rtems_panic ("No memory for mbuf pointers"); - + /* * Set receiver and transmitter buffer descriptor bases */ @@ -520,7 +520,7 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) sc->txBdBase = m8xx_bd_allocate(sc->txBdCount); m8xx.fec.r_des_start = (int)sc->rxBdBase; m8xx.fec.x_des_start = (int)sc->txBdBase; - + /* * Set up Receive Control Register: * Not promiscuous mode @@ -554,17 +554,17 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) m8xx.sdcr = 1; /* - * Set MII speed to 2.5 MHz for 25 Mhz system clock + * Set MII speed to 2.5 MHz for 25 Mhz system clock */ m8xx.fec.mii_speed = 0x0a; m8xx.fec.mii_data = 0x58021000; - + /* * Set up receive buffer descriptors */ for (i = 0 ; i < sc->rxBdCount ; i++) (sc->rxBdBase + i)->status = 0; - + /* * Set up transmit buffer descriptors */ @@ -574,13 +574,13 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) } sc->txBdHead = sc->txBdTail = 0; sc->txBdActiveCount = 0; - - + + /* * Mask all FEC interrupts and clear events */ - m8xx.fec.imask = M8xx_FEC_IEVENT_TFINT | + m8xx.fec.imask = M8xx_FEC_IEVENT_TFINT | M8xx_FEC_IEVENT_RFINT; m8xx.fec.ievent = ~0; @@ -610,7 +610,7 @@ m8xx_Enet_retire_tx_bd (struct m8xx_enet_struct *sc) int i; int nRetired; struct mbuf *m, *n; - + i = sc->txBdTail; nRetired = 0; while ((sc->txBdActiveCount != 0) @@ -636,7 +636,7 @@ m8xx_Enet_retire_tx_bd (struct m8xx_enet_struct *sc) enet_driver[0].txRetryLimit++; if (status & M8xx_BD_UNDERRUN) enet_driver[0].txUnderrun++; - + /* * Restart the transmitter */ @@ -682,7 +682,7 @@ scc_rxDaemon (void *arg) uint16_t status; m8xxBufferDescriptor_t *rxBd; int rxBdIndex; - + /* * Allocate space for incoming packets and start reception */ @@ -699,14 +699,14 @@ scc_rxDaemon (void *arg) break; } } - + /* * Input packet handling loop */ rxBdIndex = 0; for (;;) { rxBd = sc->rxBdBase + rxBdIndex; - + /* * Wait for packet if there's not one ready */ @@ -715,7 +715,7 @@ scc_rxDaemon (void *arg) * Clear old events */ m8xx.scc1.scce = 0x8; - + /* * Wait for packet * Note that the buffer descriptor is checked @@ -725,19 +725,19 @@ scc_rxDaemon (void *arg) */ while ((status = rxBd->status) & M8xx_BD_EMPTY) { rtems_event_set events; - + /* * Unmask RXF (Full frame received) event */ m8xx.scc1.sccm |= 0x8; - + rtems_bsdnet_event_receive (INTERRUPT_EVENT, RTEMS_WAIT|RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &events); } } - + /* * Check that packet is valid */ @@ -756,12 +756,12 @@ scc_rxDaemon (void *arg) * FIXME: Packet filtering hook could be done here. */ struct ether_header *eh; - + /* * Invalidate the buffer for this descriptor */ rtems_cache_invalidate_multiple_data_lines((const void *)rxBd->buffer, rxBd->length); - + m = sc->rxMbuf[rxBdIndex]; m->m_len = m->m_pkthdr.len = rxBd->length - sizeof(uint32_t) - @@ -769,7 +769,7 @@ scc_rxDaemon (void *arg) eh = mtod (m, struct ether_header *); m->m_data += sizeof(struct ether_header); ether_input (ifp, eh, m); - + /* * Allocate a new mbuf */ @@ -800,13 +800,13 @@ scc_rxDaemon (void *arg) if (status & M8xx_BD_COLLISION) sc->rxCollision++; } - + /* * Reenable the buffer descriptor */ rxBd->status = (status & (M8xx_BD_WRAP | M8xx_BD_INTERRUPT)) | M8xx_BD_EMPTY; - + /* * Move to next buffer descriptor */ @@ -826,7 +826,7 @@ fec_rxDaemon (void *arg) uint16_t status; m8xxBufferDescriptor_t *rxBd; int rxBdIndex; - + /* * Allocate space for incoming packets and start reception */ @@ -844,14 +844,14 @@ fec_rxDaemon (void *arg) break; } } - + /* * Input packet handling loop */ rxBdIndex = 0; for (;;) { rxBd = sc->rxBdBase + rxBdIndex; - + /* * Wait for packet if there's not one ready */ @@ -860,7 +860,7 @@ fec_rxDaemon (void *arg) * Clear old events */ m8xx.fec.ievent = M8xx_FEC_IEVENT_RFINT; - + /* * Wait for packet * Note that the buffer descriptor is checked @@ -870,19 +870,19 @@ fec_rxDaemon (void *arg) */ while ((status = rxBd->status) & M8xx_BD_EMPTY) { rtems_event_set events; - + /* * Unmask RXF (Full frame received) event */ m8xx.fec.ievent |= M8xx_FEC_IEVENT_RFINT; - + rtems_bsdnet_event_receive (INTERRUPT_EVENT, RTEMS_WAIT|RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &events); } } - + /* * Check that packet is valid */ @@ -892,12 +892,12 @@ fec_rxDaemon (void *arg) * FIXME: Packet filtering hook could be done here. */ struct ether_header *eh; - + /* * Invalidate the buffer for this descriptor */ rtems_cache_invalidate_multiple_data_lines((const void *)rxBd->buffer, rxBd->length); - + m = sc->rxMbuf[rxBdIndex]; m->m_len = m->m_pkthdr.len = rxBd->length - sizeof(uint32_t) - @@ -905,7 +905,7 @@ fec_rxDaemon (void *arg) eh = mtod (m, struct ether_header *); m->m_data += sizeof(struct ether_header); ether_input (ifp, eh, m); - + /* * Allocate a new mbuf */ @@ -958,12 +958,12 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) struct mbuf *l = NULL; uint16_t status; int nAdded; - + /* * Free up buffer descriptors */ m8xx_Enet_retire_tx_bd (sc); - + /* * Set up the transmit buffer descriptors. * No need to pad out short packets since the @@ -982,7 +982,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) * Clear old events */ m8xx.scc1.scce = 0x12; - + /* * Wait for buffer descriptor to become available. * Note that the buffer descriptors are checked @@ -998,7 +998,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) m8xx_Enet_retire_tx_bd (sc); while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { rtems_event_set events; - + /* * Unmask TXB (buffer transmitted) and * TXE (transmitter error) events. @@ -1011,13 +1011,13 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) m8xx_Enet_retire_tx_bd (sc); } } - + /* * Don't set the READY flag till the * whole packet has been readied. */ status = nAdded ? M8xx_BD_READY : 0; - + /* * FIXME: Why not deal with empty mbufs at at higher level? * The IP fragmentation routine in ip_output @@ -1037,7 +1037,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) * Flush the buffer for this descriptor */ rtems_cache_flush_multiple_data_lines((const void *)txBd->buffer, txBd->length); - + sc->txMbuf[sc->txBdHead] = m; nAdded++; if (++sc->txBdHead == sc->txBdCount) { @@ -1057,7 +1057,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) if (l != NULL) l->m_next = m; } - + /* * Set the transmit buffer status. * Break out of the loop if this mbuf is the last in the frame. @@ -1086,12 +1086,12 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) /* struct mbuf *l = NULL; */ uint16_t status; int nAdded; - + /* * Free up buffer descriptors */ m8xx_Enet_retire_tx_bd (sc); - + /* * Set up the transmit buffer descriptors. * No need to pad out short packets since the @@ -1110,7 +1110,7 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) * Clear old events */ m8xx.fec.ievent = M8xx_FEC_IEVENT_TFINT; - + /* * Wait for buffer descriptor to become available. * Note that the buffer descriptors are checked @@ -1126,7 +1126,7 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) m8xx_Enet_retire_tx_bd (sc); while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { rtems_event_set events; - + /* * Unmask TXB (buffer transmitted) and * TXE (transmitter error) events. @@ -1139,13 +1139,13 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) m8xx_Enet_retire_tx_bd (sc); } } - + /* * Don't set the READY flag till the * whole packet has been readied. */ status = nAdded ? M8xx_BD_READY : 0; - + /* * FIXME: Why not deal with empty mbufs at at higher level? * The IP fragmentation routine in ip_output @@ -1160,12 +1160,12 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) */ txBd->buffer = mtod (m, void *); txBd->length = m->m_len; - + /* * Flush the buffer for this descriptor */ rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length); - + sc->txMbuf[sc->txBdHead] = m; nAdded++; if (++sc->txBdHead == sc->txBdCount) { @@ -1187,7 +1187,7 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) l->m_next = m; */ } - + /* * Set the transmit buffer status. * Break out of the loop if this mbuf is the last in the frame. @@ -1219,13 +1219,13 @@ scc_txDaemon (void *arg) struct ifnet *ifp = &sc->arpcom.ac_if; struct mbuf *m; rtems_event_set events; - + for (;;) { /* * Wait for packet */ rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, RTEMS_EVENT_ANY | RTEMS_WAIT, RTEMS_NO_TIMEOUT, &events); - + /* * Send packets till queue is empty */ @@ -1251,16 +1251,16 @@ fec_txDaemon (void *arg) struct ifnet *ifp = &sc->arpcom.ac_if; struct mbuf *m; rtems_event_set events; - + for (;;) { /* * Wait for packet */ - rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, - RTEMS_EVENT_ANY | RTEMS_WAIT, - RTEMS_NO_TIMEOUT, + rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, + RTEMS_EVENT_ANY | RTEMS_WAIT, + RTEMS_NO_TIMEOUT, &events); - + /* * Send packets till queue is empty */ @@ -1286,7 +1286,7 @@ static void m8xx_enet_start (struct ifnet *ifp) { struct m8xx_enet_struct *sc = ifp->if_softc; - + rtems_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT); ifp->if_flags |= IFF_OACTIVE; } @@ -1300,22 +1300,22 @@ scc_init (void *arg) { struct m8xx_enet_struct *sc = arg; struct ifnet *ifp = &sc->arpcom.ac_if; - + if (sc->txDaemonTid == 0) { - + /* * Set up SCC hardware */ m8xx_enet_initialize (sc); - + /* * Start driver tasks */ sc->txDaemonTid = rtems_bsdnet_newproc ("SCtx", 4096, scc_txDaemon, sc); sc->rxDaemonTid = rtems_bsdnet_newproc ("SCrx", 4096, scc_rxDaemon, sc); - + } - + /* * Set flags appropriately */ @@ -1323,12 +1323,12 @@ scc_init (void *arg) m8xx.scc1.psmr |= 0x200; else m8xx.scc1.psmr &= ~0x200; - + /* * Tell the world that we're running. */ ifp->if_flags |= IFF_RUNNING; - + /* * Enable receiver and transmitter */ @@ -1342,22 +1342,22 @@ fec_init (void *arg) { struct m8xx_enet_struct *sc = arg; struct ifnet *ifp = &sc->arpcom.ac_if; - + if (sc->txDaemonTid == 0) { - + /* * Set up SCC hardware */ m8xx_fec_initialize_hardware (sc); - + /* * Start driver tasks */ sc->txDaemonTid = rtems_bsdnet_newproc ("SCtx", 4096, fec_txDaemon, sc); sc->rxDaemonTid = rtems_bsdnet_newproc ("SCrx", 4096, fec_rxDaemon, sc); - + } - + /* * Set flags appropriately */ @@ -1366,12 +1366,12 @@ fec_init (void *arg) else m8xx.fec.r_cntrl &= ~0x8; - + /* * Tell the world that we're running. */ ifp->if_flags |= IFF_RUNNING; - + /* * Enable receiver and transmitter */ @@ -1387,9 +1387,9 @@ static void scc_stop (struct m8xx_enet_struct *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; - + ifp->if_flags &= ~IFF_RUNNING; - + /* * Shut down receiver and transmitter */ @@ -1402,9 +1402,9 @@ static void fec_stop (struct m8xx_enet_struct *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; - + ifp->if_flags &= ~IFF_RUNNING; - + /* * Shut down receiver and transmitter */ @@ -1429,7 +1429,7 @@ enet_stats (struct m8xx_enet_struct *sc) printf (" Overrun:%-8lu", sc->rxOverrun); printf (" Collision:%-8lu\n", sc->rxCollision); printf (" Discarded:%-8lu\n", (unsigned long)m8xx.scc1p.un.ethernet.disfc); - + printf (" Tx Interrupts:%-8lu", sc->txInterrupts); printf (" Deferred:%-8lu", sc->txDeferred); printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat); @@ -1449,37 +1449,37 @@ scc_ioctl (struct ifnet *ifp, int command, caddr_t data) { struct m8xx_enet_struct *sc = ifp->if_softc; int error = 0; - + switch (command) { case SIOCGIFADDR: case SIOCSIFADDR: ether_ioctl (ifp, command, data); break; - + case SIOCSIFFLAGS: switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { case IFF_RUNNING: scc_stop (sc); break; - + case IFF_UP: scc_init (sc); break; - + case IFF_UP | IFF_RUNNING: scc_stop (sc); scc_init (sc); break; - + default: break; } break; - + case SIO_RTEMS_SHOW_STATS: enet_stats (sc); break; - + /* * FIXME: All sorts of multicast commands need to be added here! */ @@ -1497,37 +1497,37 @@ fec_ioctl (struct ifnet *ifp, int command, caddr_t data) { struct m8xx_enet_struct *sc = ifp->if_softc; int error = 0; - + switch (command) { case SIOCGIFADDR: case SIOCSIFADDR: ether_ioctl (ifp, command, data); break; - + case SIOCSIFFLAGS: switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { case IFF_RUNNING: fec_stop (sc); break; - + case IFF_UP: fec_init (sc); break; - + case IFF_UP | IFF_RUNNING: fec_stop (sc); fec_init (sc); break; - + default: break; } break; - + case SIO_RTEMS_SHOW_STATS: enet_stats (sc); break; - + /* * FIXME: All sorts of multicast commands need to be added here! */ @@ -1575,12 +1575,12 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) printf ("Driver already in use.\n"); return 0; } - + /* * Process options */ #if NVRAM_CONFIGURE == 1 - + /* Configure from NVRAM */ if ( (addr = nvram->ipaddr) ) { /* We have a non-zero entry, copy the value */ @@ -1589,7 +1589,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) else rtems_panic("Can't allocate ip_address buffer!\n"); } - + if ( (addr = nvram->netmask) ) { /* We have a non-zero entry, copy the value */ if ( (pAddr = malloc ( INET_ADDR_MAX_BUF_SIZE, 0, M_NOWAIT )) ) @@ -1601,7 +1601,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) /* Ethernet address requires special handling -- it must be copied into * the arpcom struct. The following if construct serves only to give the * User Area NVRAM parameter the highest priority. - * + * * If the ethernet address is specified in NVRAM, go ahead and copy it. * (ETHER_ADDR_LEN = 6 bytes). */ @@ -1619,9 +1619,9 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) */ rtems_panic("No Ethernet address specified!\n"); } - + #else /* NVRAM_CONFIGURE != 1 */ - + if (config->hardware_address) { memcpy (sc->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN); } @@ -1631,7 +1631,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) */ rtems_panic("No Ethernet address specified!\n"); } - + #endif /* NVRAM_CONFIGURE != 1 */ if (config->mtu) @@ -1647,7 +1647,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) else sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF; sc->acceptBroadcast = !config->ignore_broadcast; - + /* * Set up network interface values */ @@ -1662,7 +1662,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; if (ifp->if_snd.ifq_maxlen == 0) ifp->if_snd.ifq_maxlen = ifqmaxlen; - + /* * Attach the interface */ @@ -1701,7 +1701,7 @@ rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) printf ("Driver already in use.\n"); return 0; } - + /* * Process options */ @@ -1724,7 +1724,7 @@ rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) else sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF; sc->acceptBroadcast = !config->ignore_broadcast; - + /* * Set up network interface values */ @@ -1739,7 +1739,7 @@ rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; if (ifp->if_snd.ifq_maxlen == 0) ifp->if_snd.ifq_maxlen = ifqmaxlen; - + /* * Attach the interface */ @@ -1753,7 +1753,7 @@ rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) int rtems_enet_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching) { - + #ifdef MPC860T if ((m8xx.fec.mii_data & 0xffff) == 0x2000) { /* rtems_scc1_driver_attach(config);*/ diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c index 0c853fabaf..2fc1a2f194 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c @@ -57,13 +57,13 @@ void bsp_libc_init( void *, uint32_t, int ); void BSP_panic(char *s) { printk("%s PANIC %s\n",_RTEMS_version, s); - __asm__ __volatile ("sc"); + __asm__ __volatile ("sc"); } void _BSP_Fatal_error(unsigned int v) { printk("%s PANIC ERROR %x\n",_RTEMS_version, v); - __asm__ __volatile ("sc"); + __asm__ __volatile ("sc"); } /* @@ -75,7 +75,7 @@ void _BSP_Fatal_error(unsigned int v) * Must not use libc (to do io) from here, since drivers are not yet * initialized. * - * Installed in the rtems_cpu_table defined in + * Installed in the rtems_cpu_table defined in * rtems/c/src/exec/score/cpu/m68k/cpu.h in main() below. Called from * rtems_initialize_executive() defined in rtems/c/src/exec/sapi/src/init.c * @@ -87,7 +87,7 @@ void _BSP_Fatal_error(unsigned int v) */ void bsp_pretasking_hook(void) { - /* + /* * These are assigned addresses in the linkcmds file for the BSP. This * approach is better than having these defined as manifest constants and * compiled into the kernel, but it is still not ideal when dealing with @@ -101,7 +101,7 @@ void bsp_pretasking_hook(void) extern unsigned char _HeapEnd; bsp_libc_init( &_HeapStart, &_HeapEnd - &_HeapStart, 0 ); - + #ifdef RTEMS_DEBUG rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); #endif @@ -135,11 +135,11 @@ void bsp_pretasking_hook(void) void bsp_start(void) { extern void *_WorkspaceBase; - + ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; register unsigned char* intrStack; - + /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... @@ -148,7 +148,7 @@ void bsp_start(void) myCpuRevision = get_ppc_cpu_revision(); mmu_init(); - + /* * Enable instruction and data caches. Do not force writethrough mode. */ @@ -168,7 +168,7 @@ void bsp_start(void) /* * Initialize some SPRG registers related to irq handling */ - + intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE); _write_SPRG1((unsigned int)intrStack); /* signal them that we have fixed PR288 - eventually, this should go away */ @@ -217,7 +217,7 @@ void bsp_start(void) Cpu_table.timer_least_valid = 3; #endif - /* + /* * Call this in case we use TERMIOS for console I/O */ m8xx_uart_reserve_resources( &BSP_Configuration ); @@ -232,6 +232,6 @@ void bsp_start(void) BSP_rtems_irq_mng_init(0); #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); -#endif +#endif } diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c index 676d473051..19d8c59b77 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c @@ -18,7 +18,7 @@ * in the SIU when it takes control, but does not restore it before * returning control to the program. We thus keep a copy of the * register, and restore it from gdb using the hook facilities. - * + * * We arrange for simask_copy to be initialized to zero so that * it resides in the .data section. This avoids having gdb set * the mask to crud before we get to initialize explicitly. Of @@ -35,11 +35,11 @@ uint32_t simask_copy = 0; * number MBXA/PG1. We are assuming that the values in MBXA/PG1 * are for the older MBX boards whose part number does not have * the "B" suffix, but we have discovered that the values from - * MBXA/PG2 work better, even for the older boards. - * + * MBXA/PG2 work better, even for the older boards. + * * THESE VALUES HAVE ONLY BEEN VERIFIED FOR THE MBX821-001 and * MBX860-002. USE WITH CARE! - * + * * NOTE: The MBXA/PG2 manual lists the clock speed of the MBX821_001B * as being 50 MHz, while the MBXA/IH2.1 manual lists it as 40 MHz. * We think the MBX821_001B is an entry level board and thus is 50 MHz, @@ -58,7 +58,7 @@ static uint32_t upmaTable[64] = { * initialized by EPPCBug 1.1. In particular, the original * burst-write values do not work! Also, the following values * facilitate higher performance. - */ + */ /* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */ 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04, 0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005, @@ -83,7 +83,7 @@ static uint32_t upmaTable[64] = { 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, 0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - + /* Exception. (offset 0x3c in UPM RAM) */ 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007 @@ -109,14 +109,14 @@ static uint32_t upmaTable[64] = { /* 40 MHz MBX */ /* - * Note: For the older MBX models (i.e. without the "b" + * Note: For the older MBX models (i.e. without the "b" * suffix, e.g. mbx860_001), the following values (from the * MBXA/PG2 manual) work better than, but are different * from those published in the original MBXA/PG1 manual and * initialized by EPPCBug 1.1. In particular, the following * burst-read and burst-write values facilitate higher * performance. - */ + */ /* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */ 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00, 0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, @@ -141,7 +141,7 @@ static uint32_t upmaTable[64] = { 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, 0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - + /* Exception. (offset 0x3c in UPM RAM) */ 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007 #else @@ -157,14 +157,14 @@ void _InitMBX8xx (void) register uint32_t r1, i; extern uint32_t simask_copy; - /* + /* * Initialize the Debug Enable Register (DER) to an appropriate - * value for EPPCBug debugging. + * value for EPPCBug debugging. * (This value should also work for BDM debugging.) */ r1 = 0x70C67C07; /* All except EXTIE, ALIE, DECIE */ _mtspr( M8xx_DER, r1 ); - + /* * Initialize the Instruction Support Control Register (ICTRL) to a * an appropriate value for normal operation. A different value, @@ -172,7 +172,7 @@ void _InitMBX8xx (void) */ r1 = 0x00000007; _mtspr( M8xx_ICTRL, r1 ); - + /* * Disable and invalidate the instruction and data caches. */ @@ -185,7 +185,7 @@ void _InitMBX8xx (void) r1 = M8xx_CACHE_CMD_INVALIDATE; /* invalidate all */ _mtspr( M8xx_IC_CST, r1 ); _isync; - + r1 = M8xx_CACHE_CMD_DISABLE; _mtspr( M8xx_DC_CST, r1 ); _isync; @@ -214,14 +214,14 @@ void _InitMBX8xx (void) * imd: accessing m8xx.* should not occure before setting up the immr ! */ simask_copy = m8xx.simask; - - /* - * Initialize the SIU Module Configuration Register (SIUMCR) + + /* + * Initialize the SIU Module Configuration Register (SIUMCR) * m8xx.siumcr = 0x00602900, the default MBX and firmware value. */ - m8xx.siumcr = M8xx_SIUMCR_EARP0 | M8xx_SIUMCR_DBGC3 | M8xx_SIUMCR_DBPC0 | + m8xx.siumcr = M8xx_SIUMCR_EARP0 | M8xx_SIUMCR_DBGC3 | M8xx_SIUMCR_DBPC0 | M8xx_SIUMCR_DPC | M8xx_SIUMCR_MLRC2 | M8xx_SIUMCR_SEME; - + /* * Initialize the System Protection Control Register (SYPCR). * The SYPCR can only be written once after Reset. @@ -229,39 +229,39 @@ void _InitMBX8xx (void) * - Disable software watchdog timer * m8xx.sypcr = 0xFFFFFF88, the default MBX and firmware value. */ - m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) | M8xx_SYPCR_BMT(0xFF) | + m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) | M8xx_SYPCR_BMT(0xFF) | M8xx_SYPCR_BME | M8xx_SYPCR_SWF; /* Initialize the SIU Interrupt Edge Level Mask Register (SIEL) */ m8xx.siel = 0xAAAA0000; /* Default MBX and firmware value. */ - + /* Initialize the Transfer Error Status Register (TESR) */ m8xx.tesr = 0xFFFFFFFF; /* Default firmware value. */ - + /* Initialize the SDMA Configuration Register (SDCR) */ m8xx.sdcr = 0x00000001; /* Default firmware value. */ - + /* * Initialize the Timebase Status and Control Register (TBSCR) * m8xx.tbscr = 0x00C3, default MBX and firmware value. */ m8xx.tbscrk = M8xx_UNLOCK_KEY; /* unlock TBSCR */ - m8xx.tbscr = M8xx_TBSCR_REFA | M8xx_TBSCR_REFB | + m8xx.tbscr = M8xx_TBSCR_REFA | M8xx_TBSCR_REFB | M8xx_TBSCR_TBF | M8xx_TBSCR_TBE; - + /* Initialize the Real-Time Clock Status and Control Register (RTCSC) */ m8xx.rtcsk = M8xx_UNLOCK_KEY; /* unlock RTCSC */ m8xx.rtcsc = 0x00C3; /* Default MBX and firmware value. */ - + /* Unlock other Real-Time Clock registers */ m8xx.rtck = M8xx_UNLOCK_KEY; /* unlock RTC */ m8xx.rtseck = M8xx_UNLOCK_KEY; /* unlock RTSEC */ m8xx.rtcalk = M8xx_UNLOCK_KEY; /* unlock RTCAL */ - + /* Initialize the Periodic Interrupt Status and Control Register (PISCR) */ m8xx.piscrk = M8xx_UNLOCK_KEY; /* unlock PISCR */ m8xx.piscr = 0x0083; /* Default MBX and firmware value. */ - + /* Initialize the System Clock and Reset Control Register (SCCR) * Set the clock sources and division factors: * Timebase Source is GCLK2 / 16 @@ -299,18 +299,18 @@ void _InitMBX8xx (void) defined(mbx821_005)) m8xx.plprcr = 0x4C400000; #else -#error "MBX board not defined" +#error "MBX board not defined" #endif /* Unlock the timebase and decrementer registers. */ m8xx.tbk = M8xx_UNLOCK_KEY; - /* + /* * Initialize decrementer register to a large value to * guarantee that a decrementer interrupt will not be * generated before the kernel is fully initialized. */ r1 = 0x7FFFFFFF; _mtspr( M8xx_DEC, r1 ); - + /* Initialize the timebase register (TB is 64 bits) */ r1 = 0x00000000; _mtspr( M8xx_TBU_WR, r1 ); @@ -322,24 +322,24 @@ void _InitMBX8xx (void) /* * User Programmable Machine A (UPMA) Initialization - * + * * If this initialization code is running from DRAM, it is very * dangerous to change the value of any UPMA Ram array word from * what the firmware (EPPCBug) initialized it to. Thus we don't * initialize UPMA if EPPCBUG_VECTORS is defined; we assume EPPCBug * has done the appropriate initialization. - * + * * An exception to our rule, is that, for the older MBX boards * (those without the "B" suffix, e.g. MBX821-001 and MBX860-002), * we do re-initialize the burst-read and burst-write values with * values that are more efficient. Also, in the MBX821 case, - * the burst-write original values set by EPPCBug do not work! + * the burst-write original values set by EPPCBug do not work! * This change can be done safely because the caches have not yet * been activated. * * The RAM array of UPMA is initialized by writing to each of * its 64 32-bit RAM locations. - * Note: UPM register initialization should occur before + * Note: UPM register initialization should occur before * initialization of the corresponding BRx and ORx registers. */ #if ( !defined(EPPCBUG_VECTORS) ) @@ -373,27 +373,27 @@ void _InitMBX8xx (void) #if ( !defined(EPPCBUG_VECTORS) ) /* * Initialize the memory periodic timer. - * Memory Periodic Timer Prescaler Register (MPTPR: 16-bit register) + * Memory Periodic Timer Prescaler Register (MPTPR: 16-bit register) * m8xx.mptpr = 0x0200; */ m8xx.mptpr = M8xx_MPTPR_PTP(0x2); - + /* * Initialize the Machine A Mode Register (MAMR) - * + * * ASSUMES THAT DIMMs ARE NOT INSTALLED! - * + * * Without DIMMs: * m8xx.mamr = 0x13821000 (40 MHz) or 0x18821000 (50 MHz). - * + * * With DIMMs: * m8xx.mamr = 0x06821000 (40 MHz) or 0x08821000 (50 MHz). */ #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) - m8xx.mamr = M8xx_MEMC_MMR_PTP(0x18) | M8xx_MEMC_MMR_PTE | + m8xx.mamr = M8xx_MEMC_MMR_PTP(0x18) | M8xx_MEMC_MMR_PTE | M8xx_MEMC_MMR_DSP(0x1) | M8xx_MEMC_MMR_G0CL(0) | M8xx_MEMC_MMR_UPWAIT; #else - m8xx.mamr = M8xx_MEMC_MMR_PTP(0x13) | M8xx_MEMC_MMR_PTE | + m8xx.mamr = M8xx_MEMC_MMR_PTP(0x13) | M8xx_MEMC_MMR_PTE | M8xx_MEMC_MMR_DSP(0x1) | M8xx_MEMC_MMR_G0CL(0) | M8xx_MEMC_MMR_UPWAIT; #endif #endif /* ! defined(EPPCBUG_VECTORS) */ @@ -416,31 +416,31 @@ void _InitMBX8xx (void) * FC000000 FC7FFFFF 7 8 N N GPCM Y Y Socketed FLASH Memory * * z = 3 for 4MB installed on the motherboard, z = F for 16M - * + * * NOTE: The devices selected by CS0 and CS7 can be selected with jumper J4. * This table assumes that the 32-bit soldered flash device is the boot ROM. */ /* * CS0 : Soldered (32-bit) Flash Memory at 0xFE000000 - * + * * CHANGE THIS CODE IF YOU CHANGE JUMPER J4 FROM ITS FACTORY DEFAULT SETTING! * (or better yet, don't reprogram BR0 and OR0; just program BR7 and OR7 to * access whatever flash device is not selected during hard reset.) - * + * * MBXA/PG2 appears to lie in note 14 for table 2-4. The manual states that * "EPPCBUG configures the reset flash device at the lower address, and the * nonreset flash device at the higher address." If we take reset flash device * to mean the boot flash memory, then the statement must mean that BR0 must * point to the device at the lower address, i.e. 0xFC000000, while BR7 must * point to the device at the highest address, i.e. 0xFE000000. - * + * * THIS IS NOT THE CASE! - * + * * The boot flash is always configured to start at 0xFE000000, and the other * one to start at 0xFC000000. Changing jumper J4 only changes the width of * the memory ports into these two region. - * + * * BR0 = 0xFE000001 * Base addr [0-16] 0b11111110000000000 = 0xFE000000 * Address type [17-19] 0b000 @@ -464,7 +464,7 @@ void _InitMBX8xx (void) * * m8xx.memc[0]._or = 0xFF800930 (40 MHz) * m8xx.memc[0]._or = 0xFF800940 (50 MHz) - * m8xx.memc[0]._br = 0xFE000001 + * m8xx.memc[0]._br = 0xFE000001 */ #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) m8xx.memc[0]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | @@ -476,13 +476,13 @@ void _InitMBX8xx (void) m8xx.memc[0]._br = M8xx_BR_BA(0xFE000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; - /* + /* * CS1 : Local DRAM Memory at 0x00000000 * m8xx.memc[1]._or = 0xFFC00400; * m8xx.memc[1]._br = 0x00000081; */ #if ( defined(mbx860_001b) ) - m8xx.memc[1]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | + m8xx.memc[1]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); #elif ( defined(mbx860_002b) || \ defined(mbx860_003b) || \ @@ -495,7 +495,7 @@ void _InitMBX8xx (void) defined(mbx821_001) || \ defined(mbx821_002) || \ defined(mbx821_003) ) - m8xx.memc[1]._or = M8xx_MEMC_OR_4M | M8xx_MEMC_OR_ATM(0) | + m8xx.memc[1]._or = M8xx_MEMC_OR_4M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); #elif ( defined(mbx860_004) || \ defined(mbx860_005) || \ @@ -507,7 +507,7 @@ void _InitMBX8xx (void) defined(mbx821_004b) || \ defined(mbx821_005b) || \ defined(mbx821_006b) ) - m8xx.memc[1]._or = M8xx_MEMC_OR_16M | M8xx_MEMC_OR_ATM(0) | + m8xx.memc[1]._or = M8xx_MEMC_OR_16M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); #else #error "MBX board not defined" @@ -515,28 +515,28 @@ void _InitMBX8xx (void) m8xx.memc[1]._br = M8xx_BR_BA(0x00000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | M8xx_BR_MS_UPMA | M8xx_MEMC_BR_V; - /* - * CS2 : DIMM Memory - Bank #0, not present + /* + * CS2 : DIMM Memory - Bank #0, not present * m8xx.memc[2]._or = 0x00000400; * m8xx.memc[2]._br = 0x00000080; */ - m8xx.memc[2]._or = M8xx_MEMC_OR_ATM(0) | + m8xx.memc[2]._or = M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); m8xx.memc[2]._br = M8xx_BR_AT(0) | M8xx_BR_PS32 | M8xx_BR_MS_UPMA; /* ! M8xx_MEMC_BR_V */ - /* - * CS3 : DIMM Memory - Bank #1, not present + /* + * CS3 : DIMM Memory - Bank #1, not present * m8xx.memc[3]._or = 0x00000400; * m8xx.memc[3]._br = 0x00000080; */ - m8xx.memc[3]._or = M8xx_MEMC_OR_ATM(0) | + m8xx.memc[3]._or = M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); m8xx.memc[3]._br = M8xx_BR_AT(0) | M8xx_BR_PS32 | M8xx_BR_MS_UPMA; /* ! M8xx_MEMC_BR_V */ /* - * CS4 : Battery-Backed SRAM at 0xFA000000 + * CS4 : Battery-Backed SRAM at 0xFA000000 * m8xx.memc[4]._or = 0xFFE00920@ 40 MHz, 0xFFE00930 @ 50 MHz * m8xx.memc[4]._br = 0xFA000401; */ @@ -551,7 +551,7 @@ void _InitMBX8xx (void) M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; /* - * CS5 : PCI I/O and Memory at 0x80000000 + * CS5 : PCI I/O and Memory at 0x80000000 * m8xx.memc[5]._or = 0xA0000108; * m8xx.memc[5]._br = 0x80000001; */ @@ -560,8 +560,8 @@ void _InitMBX8xx (void) m8xx.memc[5]._br = M8xx_BR_BA(0x80000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; - /* - * CS6 : QSPAN Registers at 0xFA210000 + /* + * CS6 : QSPAN Registers at 0xFA210000 * m8xx.memc[6]._or = 0xFFFF0108; * m8xx.memc[6]._br = 0xFA210001; */ @@ -570,8 +570,8 @@ void _InitMBX8xx (void) m8xx.memc[6]._br = M8xx_BR_BA(0xFA210000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; - /* - * CS7 : Socketed (8-bit) Flash at 0xFC000000 + /* + * CS7 : Socketed (8-bit) Flash at 0xFC000000 * m8xx.memc[7]._or = 0xFF800930 @ 40 MHz, 0xFF800940 @ 50 MHz * m8xx.memc[7]._br = 0xFC000401; */ @@ -591,36 +591,36 @@ void _InitMBX8xx (void) * PCMCIA region 0: common memory */ m8xx.pbr0 = PCMCIA_MEM_ADDR; - m8xx.por0 = (M8xx_PCMCIA_POR_BSIZE_64MB - | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) - | M8xx_PCMCIA_POR_PSL(32) - | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_MEM + m8xx.por0 = (M8xx_PCMCIA_POR_BSIZE_64MB + | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) + | M8xx_PCMCIA_POR_PSL(32) + | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_MEM |M8xx_PCMCIA_POR_PSLOT_A | M8xx_PCMCIA_POR_VALID); /* * PCMCIA region 1: dma memory */ m8xx.pbr1 = PCMCIA_DMA_ADDR; - m8xx.por1 = (M8xx_PCMCIA_POR_BSIZE_64MB - | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) - | M8xx_PCMCIA_POR_PSL(32) - | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_DMA + m8xx.por1 = (M8xx_PCMCIA_POR_BSIZE_64MB + | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) + | M8xx_PCMCIA_POR_PSL(32) + | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_DMA |M8xx_PCMCIA_POR_PSLOT_A | M8xx_PCMCIA_POR_VALID); /* * PCMCIA region 2: attribute memory */ m8xx.pbr2 = PCMCIA_ATTRB_ADDR; - m8xx.por2 = (M8xx_PCMCIA_POR_BSIZE_64MB - | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) - | M8xx_PCMCIA_POR_PSL(32) + m8xx.por2 = (M8xx_PCMCIA_POR_BSIZE_64MB + | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) + | M8xx_PCMCIA_POR_PSL(32) | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_ATT |M8xx_PCMCIA_POR_PSLOT_A | M8xx_PCMCIA_POR_VALID); /* * PCMCIA region 3: I/O access */ m8xx.pbr3 = PCMCIA_IO_ADDR; - m8xx.por3 = (M8xx_PCMCIA_POR_BSIZE_64MB - | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) - | M8xx_PCMCIA_POR_PSL(32) + m8xx.por3 = (M8xx_PCMCIA_POR_BSIZE_64MB + | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) + | M8xx_PCMCIA_POR_PSL(32) | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_IO |M8xx_PCMCIA_POR_PSLOT_A | M8xx_PCMCIA_POR_VALID); diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c index a252f7d1ac..47b34f3e12 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c @@ -1,7 +1,7 @@ -/* +/* * mmutlbtab.c - * - * This file defines the MMU_TLB_table for the MBX8xx. + * + * This file defines the MMU_TLB_table for the MBX8xx. * * Copyright (c) 1999, National Research Council of Canada * @@ -27,14 +27,14 @@ * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must * not have more than 32 lines in it! * - * We set up the virtual memory map so that virtual address of a + * We set up the virtual memory map so that virtual address of a * location is equal to its real address. */ MMU_TLB_table_t MMU_TLB_table[] = { #if ( defined(mbx860_001b) ) /* - * DRAM: CS1, Start address 0x00000000, 2M, - * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * DRAM: CS1, Start address 0x00000000, 2M, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, * R/W,X for all, no ASID comparison, not cache-inhibited. * Last 512K block is cache-inhibited, but not guarded for use by EPPCBug. * EPN TWC RPN @@ -55,8 +55,8 @@ MMU_TLB_table_t MMU_TLB_table[] = { defined(mbx821_002) || \ defined(mbx821_003) ) /* - * DRAM: CS1, Start address 0x00000000, 4M, - * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * DRAM: CS1, Start address 0x00000000, 4M, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, * R/W,X for all, no ASID comparison, not cache-inhibited. * Last 512K block is cache-inhibited, but not guarded for use by EPPCBug. * EPN TWC RPN @@ -78,10 +78,10 @@ MMU_TLB_table_t MMU_TLB_table[] = { defined(mbx821_005) || \ defined(mbx821_004b) || \ defined(mbx821_005b) || \ - defined(mbx821_006b) ) + defined(mbx821_006b) ) /* - * DRAM: CS1, Start address 0x00000000, 16M, - * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * DRAM: CS1, Start address 0x00000000, 16M, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, * R/W,X for all, no ASID comparison, not cache-inhibited. * EPN TWC RPN */ @@ -93,9 +93,9 @@ MMU_TLB_table_t MMU_TLB_table[] = { /* * * NVRAM: CS4, Start address 0xFA000000, 32K, - * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, * R/W,X for all, no ASID comparison, cache-inhibited. - * + * * EPN TWC RPN */ { 0xFA000200, 0x01, 0xFA0009FF }, /* NVRAM - PS=16K */ @@ -103,7 +103,7 @@ MMU_TLB_table_t MMU_TLB_table[] = { /* * * Board Control/Status Register #1/#2: CS4, Start address 0xFA100000, (4 x 8 bits?) - * ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, + * ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, * R/W,X for all, no ASID comparison, cache-inhibited. * EPN TWC RPN */ @@ -111,10 +111,10 @@ MMU_TLB_table_t MMU_TLB_table[] = { /* * * (IMMR-SPRs) Dual Port RAM: Start address 0xFA200000, 16K, - * ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, + * ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, * R/W,X for all, no ASID comparison, cache-inhibited. - * - * Note: We use the value in MBXA/PG2, which is also the value that + * + * Note: We use the value in MBXA/PG2, which is also the value that * EPPC-Bug programmed into our boards. The alternative is the value * in MBXA/PG1: 0xFFA00000. This value might well depend on the revision * of the firmware. @@ -124,7 +124,7 @@ MMU_TLB_table_t MMU_TLB_table[] = { /* * * Flash: CS0, Start address 0xFE000000, 4M, (BootROM-EPPCBug) - * ASID=0x0, APG=0x0, not guarded memory, + * ASID=0x0, APG=0x0, not guarded memory, * R/O,X for all, no ASID comparison, not cache-inhibited. * EPN TWC RPN */ @@ -138,7 +138,7 @@ MMU_TLB_table_t MMU_TLB_table[] = { { 0xFE380200, 0x05, 0xFE380CFD }, /* Flash - PS=512K */ /* * BootROM: CS7, Start address 0xFC000000, 4M?, (socketed FLASH) - * ASID=0x0, APG=0x0, not guarded memory, + * ASID=0x0, APG=0x0, not guarded memory, * R/O,X for all, no ASID comparison, not cache-inhibited. * EPN TWC RPN */ @@ -173,23 +173,23 @@ MMU_TLB_table_t MMU_TLB_table[] = { * For each space (MEM/DMA/ATTRIB/IO) only the first 8MB are mapped * ASID=0x0, APG=0x0, guarded memory, * R/W,X for all, no ASID comparison, cache-inhibited. - * EPN TWC + * EPN TWC * RPN */ - { (PCMCIA_MEM_ADDR & 0xfffff000) | 0x200, 0x1D, + { (PCMCIA_MEM_ADDR & 0xfffff000) | 0x200, 0x1D, (PCMCIA_MEM_ADDR & 0xfffff000) | 0x9F7 },/* PCMCIA Memory - PS=8M */ - { (PCMCIA_DMA_ADDR & 0xfffff000) | 0x200, 0x1D, + { (PCMCIA_DMA_ADDR & 0xfffff000) | 0x200, 0x1D, (PCMCIA_DMA_ADDR & 0xfffff000) | 0x9F7 },/* PCMCIA DMA - PS=8M */ - { (PCMCIA_ATTRB_ADDR & 0xfffff000) | 0x200, 0x1D, + { (PCMCIA_ATTRB_ADDR & 0xfffff000) | 0x200, 0x1D, (PCMCIA_ATTRB_ADDR & 0xfffff000) | 0x9F7 },/* PCMCIA ATTRIB-PS=8M*/ - { (PCMCIA_IO_ADDR & 0xfffff000) | 0x200, 0x1D, + { (PCMCIA_IO_ADDR & 0xfffff000) | 0x200, 0x1D, (PCMCIA_IO_ADDR & 0xfffff000) | 0x9F7 } /* PCMCIA I/O - PS=8M */ }; -/* +/* * MMU_N_TLB_Table_Entries is defined here because the size of the * MMU_TLB_table is only known in this file. */ diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S b/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S index ebd60be5ab..ed44cfd41c 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S @@ -6,28 +6,28 @@ * all remaining initialization. * * This file is based on several others: - * - * (1) start360.s from the gen68360 BSP by + * + * (1) start360.s from the gen68360 BSP by * W. Eric Norum (eric@skatter.usask.ca) * with the following copyright and license: * * COPYRIGHT (c) 1989-1998. * On-Line Applications Research Corporation (OAR). - * + * * The license and distribution terms for this file may in * the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * * (2) start.s for the eth_comm port by * Jay Monkman (jmonkman@fracsa.com), - * which itself is based on the - * + * which itself is based on the + * * (3) dlentry.s for the Papyrus BSP, written by: * Andrew Bray <andy@i-cubed.co.uk> * with the following copyright and license: * * COPYRIGHT (c) 1995 by i-cubed ltd. - * + * * (4) start860.S for the MBX821/MBX860, written by: * Darlene A. Stewart <darlene.stewart@iit.nrc.ca> * Copyright (c) 1999, National Research Council of Canada @@ -179,7 +179,7 @@ .L_D4_e: .L_D2: .previous - + /* * Tell C's eabi-ctor's that we have an atexit function, * and that it is to register __do_global_dtors. @@ -188,7 +188,7 @@ PUBLIC_VAR(__atexit) .section ".sdata","aw" .align 2 -SYM(__atexit): +SYM(__atexit): EXT_PROC_REF(atexit)@fixup .previous @@ -198,7 +198,7 @@ SYM(__atexit): .previous /* That should do it */ - + /* * Put the entry point in its own section. That way, we can guarantee * to put it first in the .text section in the linker script. @@ -208,16 +208,16 @@ SYM(__atexit): PUBLIC_VAR (start) SYM(start): bl .startup /* or bl .spin */ -base_addr: +base_addr: /* * Parameters from linker */ -toc_pointer: +toc_pointer: .long __GOT_START__ -bss_length: +bss_length: .long bss.size -bss_addr: +bss_addr: .long bss.start PUBLIC_VAR (text_addr) @@ -230,7 +230,7 @@ text_length: /* * Spin, if necessary, to acquire control from debugger (CodeWarrior). - */ + */ spin: .long 0x0001 .spin: @@ -238,22 +238,22 @@ spin: lwz r3, spin@l(r3) cmpwi r3, 0x1 beq .spin -/* +/* * #define LOADED_BY_EPPCBUG */ #define LOADED_BY_EPPCBUG -#define EARLY_CONSOLE +#define EARLY_CONSOLE /* - * Initialization code + * Initialization code */ -.startup: +.startup: /* Get the start address. */ mflr r1 -#ifdef LOADED_BY_EPPCBUG +#ifdef LOADED_BY_EPPCBUG /* Save pointer to residual/board data */ lis r9,eppcbugInfo@ha stw r3,eppcbugInfo@l(r9) -#endif +#endif /* Initialize essential registers. */ bl initregs nop @@ -272,24 +272,24 @@ spin: EXTERN_PROC (_InitMBX8xx) bl PROC (_InitMBX8xx) nop - + /* Clear the bss section. */ bl bssclr nop #if defined(EARLY_CONSOLE) && defined(LOADED_BY_EPPCBUG) EXTERN_PROC (serial_init) bl PROC (serial_init) -#endif +#endif lis r5,environ@ha la r5,environ@l(r5) /* environp */ /* clear argc and argv */ xor r3, r3, r3 xor r4, r4, r4 - + EXTERN_PROC (boot_card) bl PROC (boot_card) /* call the first C routine */ nop - + /* we should never return from boot_card, but in case we do ... */ /* The next instructions are dependent on your runtime environment */ @@ -297,14 +297,14 @@ spin: lis r10, 0x0400 /* Data cache disable */ mtspr 568, r10 isync - + mtspr 560, r10 /* Instruction cache disable */ isync - + stop_here: li r10, 0x0F00 /* .RETURN */ sc - + b stop_here nop @@ -320,13 +320,13 @@ bssclr: rlwinm. r5,r5,30,0x3FFFFFFF /* form length/4 */ beqlr /* no bss - return */ mtctr r5 /* set ctr reg */ - + li r5,0x0000 /* r5 = 0 */ clear_bss: stw r5,0(r4) /* store r6 */ addi r4,r4,0x4 /* update r4 */ bdnz clear_bss /* dec counter and loop */ - + blr /* return */ /* @@ -337,24 +337,24 @@ clear_bss: * r0 - scratch */ initregs: - /* + /* * Disable address translation. We should already be running in real space, * so this should be a no-op, i.e. no need to switch instruction stream * addresses from virtual space to real space. Other bits set the processor * for big-endian mode, exceptions vectored to 0x000n_nnnn (vectors are * already in low memory!), no execution tracing, machine check exceptions - * enabled, floating-point not available (MPC8xx has none), supervisor + * enabled, floating-point not available (MPC8xx has none), supervisor * priviledge level, external interrupts disabled, power management * disabled (normal operation mode). */ li r0, 0x1000 /* MSR_ME */ mtmsr r0 /* Context-synchronizing */ isync - + /* * Clear the exception handling registers. * Note SPRG3 is reserved for use by EPPCBug on the MBX8xx. - */ + */ li r0, 0x0000 mtdar r0 mtspr sprg0, r0 @@ -362,13 +362,13 @@ initregs: mtspr sprg2, r0 mtspr srr0, r0 mtspr srr1, r0 - + mr r6, r0 mr r7, r0 mr r8, r0 mr r9, r0 mr r10, r0 - mr r11, r0 + mr r11, r0 mr r12, r0 mr r13, r0 mr r14, r0 @@ -389,9 +389,9 @@ initregs: mr r29, r0 mr r30, r0 mr r31, r0 - + blr /* return */ - + .L_text_e: .comm environ,4,4 diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.S b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.S index d634cc8b88..14720aee38 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.S +++ b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.S @@ -2,26 +2,26 @@ * (c) 1999, Eric Valette valette@crf.canon.fr * * - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * exception veneers for RTEMS. * * $Id$ */ - + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include <bsp/vectors.h> - + #define SYNC \ sync; \ isync - + .text - .p2align 5 - + .p2align 5 + PUBLIC_VAR(default_exception_vector_code_prolog) SYM (default_exception_vector_code_prolog): /* @@ -34,7 +34,7 @@ SYM (default_exception_vector_code_prolog): stw r2, EXC_LR_OFFSET(r1) bl 0f 0: /* - * r3 = exception vector entry point + * r3 = exception vector entry point * (256 * vector number) + few instructions */ mflr r3 @@ -42,21 +42,21 @@ SYM (default_exception_vector_code_prolog): * r3 = r3 >> 8 = vector */ srwi r3,r3,8 -#ifdef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE +#ifdef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE lis r2,push_normalized_frame@h ori r2,r2,push_normalized_frame@l mtlr r2 blr #else ba push_normalized_frame -#endif - +#endif + PUBLIC_VAR (default_exception_vector_code_prolog_size) - + default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog - + .p2align 5 -PUBLIC_VAR (push_normalized_frame) +PUBLIC_VAR (push_normalized_frame) SYM (push_normalized_frame): stw r3, EXCEPTION_NUMBER_OFFSET(r1) stw r0, GPR0_OFFSET(r1) @@ -70,7 +70,7 @@ SYM (push_normalized_frame): * Saved a few line above : R0 * * Manual says that "stmw" instruction may be slower than - * series of individual "stw" but who cares about performance + * series of individual "stw" but who cares about performance * for the DEFAULT exception handler? */ stmw r4, GPR4_OFFSET(r1) /* save R4->R31 */ @@ -96,7 +96,7 @@ SYM (push_normalized_frame): ori r3,r3, MSR_RI | MSR_IR | MSR_DR mtmsr r3 SYNC - + /* * Call C exception handler */ @@ -137,12 +137,12 @@ SYM (push_normalized_frame): /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.h b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.h index fc841f0fa2..43fb7ecedf 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.h +++ b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.h @@ -1,4 +1,4 @@ -/* +/* * vectors.h Exception frame related contant and API. * * This include file describe the data structure and the functions implemented @@ -16,10 +16,10 @@ #define LIBBSP_POWERPC_MBX8XX_VECTORS_H /* - * The callee (high level exception code written in C) + * The callee (high level exception code written in C) * will store the Link Registers (return address) at entry r1 + 4 !!!. * So let room for it!!!. - */ + */ #define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 #define SRR0_FRAME_OFFSET 8 #define SRR1_FRAME_OFFSET 12 @@ -81,7 +81,7 @@ extern int default_exception_vector_code_prolog_size; * zero, it performs more or less like memmove. No copy is performed if * source and destination addresses are equal. However the caches * are synchronized. Note that the size is always rounded up to the - * next mutiple of 4. + * next mutiple of 4. */ extern void * codemove(void *, const void *, unsigned int, unsigned long); extern void initialize_exceptions(); diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors_init.c b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors_init.c index 1aaae35f5e..5c97bb892e 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors_init.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors_init.c @@ -1,4 +1,4 @@ -/* +/* * vectors_init.c Exception hanlding initialisation (and generic handler). * * This include file describe the data structure and the functions implemented @@ -25,7 +25,7 @@ exception_handler_t globalExceptHdl; void C_exception_handler(BSP_Exception_frame* excPtr) { int recoverable = 0; - + printk("exception handler called for exception %d\n", excPtr->_EXC_number); printk("\t Next PC or Address of fault = %x\n", excPtr->EXC_SRR0); printk("\t Saved MSR = %x\n", excPtr->EXC_SRR1); @@ -69,7 +69,7 @@ void C_exception_handler(BSP_Exception_frame* excPtr) if (excPtr->_EXC_number == ASM_DEC_VECTOR) recoverable = 1; if (excPtr->_EXC_number == ASM_SYS_VECTOR) -#ifdef TEST_RAW_EXCEPTION_CODE +#ifdef TEST_RAW_EXCEPTION_CODE recoverable = 1; #else recoverable = 0; diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h b/c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h index 85488eb076..fb79919160 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h @@ -48,7 +48,7 @@ #define BSP_CONSOLE_PORT BSP_UART_COM1 #define BSP_UART_BAUD_BASE 115200 - + #include <bsp/openpic.h> #define BSP_PIC_DO_EOI openpic_eoi(0) diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/clock/p_clock.c b/c/src/lib/libbsp/powerpc/mpc8260ads/clock/p_clock.c index 7416a21231..4e92c97e5b 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/clock/p_clock.c +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/clock/p_clock.c @@ -28,7 +28,7 @@ static rtems_irq_connect_data clockIrqData = {BSP_PERIODIC_TIMER, (rtems_irq_enable)clockOn, (rtems_irq_disable)clockOff, (rtems_irq_is_enabled)clockIsOn}; - + int BSP_get_clock_irq_level() { /* diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/console/console.c b/c/src/lib/libbsp/powerpc/mpc8260ads/console/console.c index 0f64818fbd..29243f4783 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/console/console.c +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/console/console.c @@ -45,7 +45,7 @@ * Interrupt-driven I/O requires termios. * * TESTS: - * + * * TO RUN THE TESTS, USE POLLED I/O WITHOUT TERMIOS SUPPORT. Some tests * play with the interrupt masks and turn off I/O. Those tests will hang * when interrupt-driven I/O is used. Other tests, such as cdtest, do I/O @@ -55,16 +55,16 @@ * should all be fixed to work with interrupt-driven I/O and to * produce output in the expected sequence. Obviously, the termios test * requires termios support in the driver. - * + * * Set CONSOLE_MINOR to the appropriate device minor number in the * config file. This allows the RTEMS application console to be different * from the EPPBug debug console or the GDB port. - * + * * This driver handles all five available serial ports: it distinguishes * the sub-devices using minor device numbers. It is not possible to have * other protocols running on the other ports when this driver is used as * currently written. - * + * * Based on code (alloc860.c in eth_comm port) by * Jay Monkman (jmonkman@frasca.com), * Copyright (C) 1998 by Frasca International, Inc. @@ -153,7 +153,7 @@ static rtems_status_code do_poll_read( * Output characters through polled I/O. Returns only once every character has * been sent. * - * CR is transmitted AFTER a LF on output. + * CR is transmitted AFTER a LF on output. * * Input parameters: * major - ignored. Should be the major number for this driver. @@ -198,8 +198,8 @@ static rtems_status_code do_poll_write( static void _BSP_output_char( char c ) { char cr = '\r'; - - /* + + /* * Can't rely on console_initialize having been called before this function * is used, so it may fail unless output is done through EPPC-Bug. */ @@ -208,7 +208,7 @@ static void _BSP_output_char( char c ) PRINTK_WRITE( PRINTK_MINOR, &c, 1 ); if( c == '\n' ) PRINTK_WRITE( PRINTK_MINOR, &cr, 1 ); - + } @@ -231,7 +231,7 @@ rtems_device_driver console_initialize( { rtems_status_code status; rtems_device_minor_number console_minor; - + /* * Set up TERMIOS if needed */ @@ -244,12 +244,12 @@ rtems_device_driver console_initialize( #else rtems_termios_initialize (); #endif /* UARTS_USE_TERMIOS */ - + /* * Do common initialization. */ m8xx_uart_initialize(); - + /* * Do device-specific initialization */ @@ -290,7 +290,7 @@ rtems_device_driver console_initialize( status = rtems_io_register_name ("/dev/tty2", major, SCC3_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + status = rtems_io_register_name ("/dev/tty3", major, SCC4_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); @@ -309,7 +309,7 @@ rtems_device_driver console_initialize( rtems_fatal_error_occurred (status); chmod("/dev/console",0666); chown("/dev/console",2,0); - + return RTEMS_SUCCESSFUL; } @@ -351,12 +351,12 @@ rtems_device_driver console_open( 0 /* outputUsesInterrupts */ }; #endif - + #endif - + rtems_status_code sc; - - if ( minor > NUM_PORTS-1 ) + + if ( minor > NUM_PORTS-1 ) return RTEMS_INVALID_NUMBER; @@ -375,7 +375,7 @@ rtems_device_driver console_open( #endif /* UARTS_USE_TERMIOS != 1 */ return sc; - + } @@ -453,7 +453,7 @@ rtems_device_driver console_control( rtems_device_minor_number minor, void *arg ) -{ +{ if ( minor > NUM_PORTS-1 ) return RTEMS_INVALID_NUMBER; diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/include/bsp.h b/c/src/lib/libbsp/powerpc/mpc8260ads/include/bsp.h index 0ee4d6de38..0ddbb8eb33 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/include/bsp.h @@ -123,7 +123,7 @@ extern rtems_configuration_table BSP_Configuration; /* * NOTE: Use the standard Console driver entry */ - + /* * NOTE: Use the standard Clock driver entry */ diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c index 17fddf21a1..7de64a8884 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c @@ -16,7 +16,7 @@ * * $Id$ */ - + #include <bsp.h> #include <bsp/irq.h> #include <rtems.h> @@ -146,7 +146,7 @@ static m82xxIrqMasks_t SIU_MaskBit[BSP_CPM_IRQ_NUMBER] = void dump_irq_masks(void ) { int i; - for( i=0; i<BSP_CPM_IRQ_NUMBER;i++ ) + for( i=0; i<BSP_CPM_IRQ_NUMBER;i++ ) { printk( "%04d: %08X %08X\n", i, @@ -172,9 +172,9 @@ static void compute_SIU_IvectMask_from_prio () * correspond to the priorities defined * for the SIU in irq_init.c. */ - + int i,j; - + for( i=0; i<BSP_CPM_IRQ_NUMBER; i++ ) { for( j=0;j<BSP_CPM_IRQ_NUMBER; j++ ) @@ -182,9 +182,9 @@ static void compute_SIU_IvectMask_from_prio () { SIU_MaskBit[i].priority_h |= SIU_MaskBit[j].mask_h; SIU_MaskBit[i].priority_l |= SIU_MaskBit[j].mask_l; - } + } } - + } /* @@ -217,10 +217,10 @@ int BSP_irq_enable_at_cpm(const rtems_irq_symbolic_name irqLine) int BSP_irq_disable_at_cpm(const rtems_irq_symbolic_name irqLine) { int cpm_irq_index; - + if (!is_cpm_irq(irqLine)) return 1; - + cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); m8260.simr_h &= ~(SIU_MaskBit[cpm_irq_index].mask_h); @@ -233,10 +233,10 @@ int BSP_irq_disable_at_cpm(const rtems_irq_symbolic_name irqLine) int BSP_irq_enabled_at_cpm(const rtems_irq_symbolic_name irqLine) { int cpm_irq_index; - + if (!is_cpm_irq(irqLine)) return 0; - + cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); return ((m8260.simr_h & SIU_MaskBit[cpm_irq_index].mask_h) || @@ -274,7 +274,7 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) * store the data provided by user */ rtems_hdl_tbl[irq->name] = *irq; - + if (is_cpm_irq(irq->name)) { /* * Enable interrupt at PIC level @@ -317,7 +317,7 @@ int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) { unsigned int level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -332,32 +332,32 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) return 0; } _CPU_ISR_Disable(level); - + if (is_cpm_irq(irq->name)) { /* * disable interrupt at PIC level */ BSP_irq_disable_at_cpm (irq->name); } - + if (is_processor_irq(irq->name)) { /* * disable exception at processor level */ - } - + } + /* * Disable interrupt on device */ irq->off(irq); - + /* * restore the default irq value */ rtems_hdl_tbl[irq->name] = default_rtems_entry; - + _CPU_ISR_Enable(level); - + return 1; } @@ -378,7 +378,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) /* Fill in priority masks */ compute_SIU_IvectMask_from_prio(); - + _CPU_ISR_Disable(level); /* * start with CPM IRQ @@ -458,14 +458,14 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) */ #ifdef DISPATCH_HANDLER_STAT loopCounter = 0; -#endif +#endif while (1) { if( ((m8260.sipnr_h & m8260.simr_h) | (m8260.sipnr_l & m8260.simr_l)) == 0 ) { #ifdef DISPATCH_HANDLER_STAT if (loopCounter > maxLoop) maxLoop = loopCounter; -#endif +#endif break; } @@ -495,11 +495,11 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) /* disable exceptions again */ _CPU_MSR_SET(msr); - + /* restore interrupt masks */ m8260.simr_h = old_simr_h; m8260.simr_l = old_simr_l; - + } #ifdef DISPATCH_HANDLER_STAT ++ loopCounter; @@ -507,8 +507,8 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) } } - - + + void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) { /* diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.h b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.h index 451d4e0894..d01dcc1e47 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.h +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.h @@ -83,7 +83,7 @@ typedef enum { * * The MPC8260 User Manual seems shot through with inconsistencies * about this whole area. - */ + */ /* * Some CPM IRQ symbolic name definition @@ -153,7 +153,7 @@ typedef enum { }rtems_irq_symbolic_name; -#define CPM_INTERRUPT +#define CPM_INTERRUPT /* @@ -183,9 +183,9 @@ typedef struct __rtems_irq_connect_data__ { * It is usually called immediately AFTER connecting the interrupt handler. * RTEMS may well need such a function when restoring normal interrupt * processing after a debug session. - * + * */ - rtems_irq_enable on; + rtems_irq_enable on; /* * function for disabling interrupts at device level (ONLY!). * The code will disable it at SIU and CPM level. RATIONALE : anyway @@ -221,7 +221,7 @@ typedef struct { rtems_irq_symbolic_name irqBase; /* * software priorities associated with interrupts. - * if irqPrio [i] > intrPrio [j] it means that + * if irqPrio [i] > intrPrio [j] it means that * interrupt handler hdl connected for interrupt name i * will not be interrupted by the handler connected for interrupt j * The interrupt source will be physically masked at i8259 level. @@ -300,7 +300,7 @@ int BSP_irq_enabled_at_cpm (const rtems_irq_symbolic_name irqLine); * 4) perform rescheduling when necessary, * 5) restore the C scratch registers... * 6) restore initial execution flow - * + * */ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); /* @@ -344,7 +344,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config); * (Re) get info on current RTEMS interrupt management. */ int BSP_rtems_irq_mngt_get(rtems_irq_global_settings**); - + extern void BSP_rtems_irq_mng_init(unsigned cpuId); #ifdef __cplusplus diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_asm.S b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_asm.S index a0d7d02510..64f0176109 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_asm.S +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_asm.S @@ -1,5 +1,5 @@ /* - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * IRQ veneers for RTEMS. * * The license and distribution terms for this file may be @@ -14,7 +14,7 @@ * * $Id$ */ - + #include <bsp/vectors.h> #include <rtems/score/cpuopts.h> /* for PPC_HAS_FPU */ #include <rtems/score/cpu.h> @@ -24,13 +24,13 @@ #define SYNC \ sync; \ isync - + .text - .p2align 5 - - + .p2align 5 + + PUBLIC_VAR(decrementer_exception_vector_prolog_code) - + SYM (decrementer_exception_vector_prolog_code): /* @@ -42,11 +42,11 @@ SYM (decrementer_exception_vector_prolog_code): ba shared_raw_irq_code_entry PUBLIC_VAR (decrementer_exception_vector_prolog_code_size) - + decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code PUBLIC_VAR(external_exception_vector_prolog_code) - + SYM (external_exception_vector_prolog_code): /* * let room for exception frame @@ -57,12 +57,12 @@ SYM (external_exception_vector_prolog_code): ba shared_raw_irq_code_entry PUBLIC_VAR (external_exception_vector_prolog_code_size) - + external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code PUBLIC_VAR(shared_raw_irq_code_entry) PUBLIC_VAR(C_dispatch_irq_handler) - + .p2align 5 SYM (shared_raw_irq_code_entry): /* @@ -73,7 +73,7 @@ SYM (shared_raw_irq_code_entry): * R4 : vector number */ /* - * Save SRR0/SRR1 As soon As possible as it is the minimal needed + * Save SRR0/SRR1 As soon As possible as it is the minimal needed * to reenable exception processing */ stw r0, GPR0_OFFSET(r1) @@ -100,7 +100,7 @@ SYM (shared_raw_irq_code_entry): #endif mtmsr r3 SYNC - + /* * Push C scratch registers on the current stack. It may * actually be the thread stack or the interrupt stack. @@ -122,7 +122,7 @@ SYM (shared_raw_irq_code_entry): mfctr r6 mfxer r7 mflr r8 - + stw r5, EXC_CR_OFFSET(r1) stw r6, EXC_CTR_OFFSET(r1) stw r7, EXC_XER_OFFSET(r1) @@ -148,23 +148,23 @@ SYM (shared_raw_irq_code_entry): /* mfspr r2, SPRG0 */ addis r6, 0, _ISR_Nest_level@ha lwz r2, _ISR_Nest_level@l( r6 ) - + /* * Check if stack switch is necessary */ cmpwi r2,0 bne nested mfspr r1, SPRG1 - -nested: - /* + +nested: + /* * Start Incrementing nesting level in R2 */ addi r2,r2,1 - + addis r6, 0, _ISR_Nest_level@ha stw r2, _ISR_Nest_level@l( r6 ) - + /* * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level */ @@ -173,7 +173,7 @@ nested: * store new nesting level in SPRG0 */ /* mtspr SPRG0, r2 */ - + addi r6, r6, 1 mfmsr r5 /* @@ -183,40 +183,40 @@ nested: /* * We are now running on the interrupt stack. External and decrementer * exceptions are still disabled. I see no purpose trying to optimize - * further assembler code. + * further assembler code. */ /* * Call C exception handler for decrementer Interrupt frame is passed just * in case... */ - + addi r3, r14, 0x8 bl C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */ /* - * start decrementing nesting level. Note : do not test result against 0 + * start decrementing nesting level. Note : do not test result against 0 * value as an easy exit condition because if interrupt nesting level > 1 * then _Thread_Dispatch_disable_level > 1 */ /* mfspr r2, SPRG0 */ - + addis r6, 0, _ISR_Nest_level@ha lwz r2, _ISR_Nest_level@l( r6 ) - + /* * start decrementing _Thread_Dispatch_disable_level */ lwz r3,_Thread_Dispatch_disable_level@l(r15) addi r2, r2, -1 /* Continue decrementing nesting level */ addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */ - - stw r2, _ISR_Nest_level@l( r6 ) + + stw r2, _ISR_Nest_level@l( r6 ) /* mtspr SPRG0, r2 */ /* End decrementing nesting level */ - + stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */ cmpwi r3, 0 /* - * switch back to original stack (done here just optimize registers + * switch back to original stack (done here just optimize registers * contention. Could have been done before...) */ addi r1, r14, 0 @@ -224,14 +224,14 @@ nested: /* * Here we are running again on the thread system stack. * We have interrupt nesting level = _Thread_Dispatch_disable_level = 0. - * Interrupt are still disabled. Time to check if scheduler request to + * Interrupt are still disabled. Time to check if scheduler request to * do something with the current thread... */ addis r4, 0, _Context_Switch_necessary@ha lwz r5, _Context_Switch_necessary@l(r4) cmpwi r5, 0 bne switch - + addis r6, 0, _ISR_Signals_to_thread_executing@ha lwz r7, _ISR_Signals_to_thread_executing@l(r6) cmpwi r7, 0 @@ -244,7 +244,7 @@ nested: */ stmw r16, GPR16_OFFSET(r1) addi r3, r1, 0x8 - + /* * compute SP at exception entry */ @@ -257,7 +257,7 @@ nested: * Call High Level signal handling code */ bl _ThreadProcessSignalsFromIrq - + /* * start restoring exception like frame @@ -266,16 +266,16 @@ nested: lwz r30, EXC_XER_OFFSET(r1) lwz r29, EXC_CR_OFFSET(r1) lwz r28, EXC_LR_OFFSET(r1) - + mtctr r31 mtxer r30 mtcr r29 mtlr r28 - - + + lmw r4, GPR4_OFFSET(r1) - + lwz r2, GPR2_OFFSET(r1) lwz r0, GPR0_OFFSET(r1) @@ -289,21 +289,21 @@ nested: /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC rfi - + switch: bl SYM (_Thread_Dispatch) - -easy_exit: + +easy_exit: /* * start restoring interrupt frame */ @@ -311,7 +311,7 @@ easy_exit: lwz r4, EXC_XER_OFFSET(r1) lwz r5, EXC_CR_OFFSET(r1) lwz r6, EXC_LR_OFFSET(r1) - + mtctr r3 mtxer r4 mtcr r5 @@ -337,11 +337,11 @@ easy_exit: xori r3, r3, MSR_RI /*| MSR_IR | MSR_DR*/ mtmsr r3 SYNC - + /* * Restore rfi related settings */ - + lwz r4, SRR1_FRAME_OFFSET(r1) lwz r2, SRR0_FRAME_OFFSET(r1) lwz r3, GPR3_OFFSET(r1) diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_init.c b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_init.c index d2ca9b2005..b0f8324ae7 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_init.c +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_init.c @@ -74,7 +74,7 @@ static rtems_irq_prio irqPrioTable[BSP_CPM_IRQ_NUMBER]={ }; -/* +/* * Initialize CPM interrupt management */ void @@ -99,7 +99,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) { rtems_raw_except_connect_data vectorDesc; int i; - + BSP_CPM_irq_init(); /* * Initialize Rtems management interrupt table @@ -126,7 +126,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) */ BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); } - + /* * We must connect the raw irq handler for the two * expected interrupt sources : decrementer and external interrupts. @@ -148,7 +148,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) if (!mpc8xx_set_exception (&vectorDesc)) { BSP_panic("Unable to initialize RTEMS external raw exception\n"); } -#ifdef TRACE_IRQ_INIT +#ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operationnal\n"); #endif } diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/network/if_hdlcsubr.c b/c/src/lib/libbsp/powerpc/mpc8260ads/network/if_hdlcsubr.c index 424bb5b5bc..64a4ee3d7d 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/network/if_hdlcsubr.c +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/network/if_hdlcsubr.c @@ -104,7 +104,7 @@ hdlc_output(ifp, m0, dst, rt0) struct mbuf *mcopy = (struct mbuf *)0; /* register struct ether_header *eh; */ int off, len = m->m_pkthdr.len; - + /* printk( "hdlc output" ); */ /* struct arpcom *ac = (struct arpcom *)ifp; */ @@ -175,8 +175,8 @@ hdlc_output(ifp, m0, dst, rt0) if (m == 0) senderr(ENOBUFS); - -#if 0 + +#if 0 eh = mtod(m, struct ether_header *); (void)memcpy(&eh->ether_type, &type, sizeof(eh->ether_type)); @@ -199,7 +199,7 @@ hdlc_output(ifp, m0, dst, rt0) if ((ifp->if_flags & IFF_OACTIVE) == 0) (*ifp->if_start)(ifp); splx(s); - + ifp->if_obytes += len /*+ sizeof (struct ether_header)*/; if (m->m_flags & M_MCAST) ifp->if_omcasts++; @@ -223,21 +223,21 @@ hdlc_input(ifp, m) { register struct ifqueue *inq; int s; - + struct ether_header eh; - + if ((ifp->if_flags & IFF_UP) == 0) { m_freem(m); return; } ifp->if_ibytes += m->m_pkthdr.len; -/* +/* if (memcmp((caddr_t)etherbroadcastaddr, (caddr_t)eh->ether_dhost, sizeof(etherbroadcastaddr)) == 0) m->m_flags |= M_BCAST; else if (eh->ether_dhost[0] & 1) m->m_flags |= M_MCAST; -*/ +*/ if (m->m_flags & (M_BCAST|M_MCAST)) ifp->if_imcasts++; @@ -285,11 +285,11 @@ hdlc_ifattach(ifp) sdl->sdl_family == AF_LINK) { sdl->sdl_type = IFT_ETHER; sdl->sdl_alen = ifp->if_addrlen; -/* +/* memcpy(LLADDR(sdl), (caddr_t)((struct arpcom *)ifp)->ac_enaddr, ifp->if_addrlen); -*/ +*/ break; } } @@ -309,7 +309,7 @@ hdlc_ioctl(struct ifnet *ifp, int command, caddr_t data) ifp->if_flags |= IFF_UP; switch (ifa->ifa_addr->sa_family) { -#if 0 +#if 0 #ifdef INET case AF_INET: ifp->if_init(ifp->if_softc); /* before arpwhohas */ @@ -329,11 +329,11 @@ hdlc_ioctl(struct ifnet *ifp, int command, caddr_t data) struct sockaddr *sa; sa = (struct sockaddr *) & ifr->ifr_data; -/* +/* memcpy((caddr_t) sa->sa_data, ((struct arpcom *)ifp->if_softc)->ac_enaddr, ETHER_ADDR_LEN); -*/ +*/ } break; diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/network/network.c b/c/src/lib/libbsp/powerpc/mpc8260ads/network/network.c index ce8e51564e..9de8b0ff26 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/network/network.c +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/network/network.c @@ -250,13 +250,13 @@ m8260_scc_initialize_hardware (struct m8260_hdlc_struct *sc) /* * Allocate mbuf pointers */ - sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, + sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT); - sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, + sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT); if (!sc->rxMbuf || !sc->txMbuf) rtems_panic ("No memory for mbuf pointers"); - + /* * Set receiver and transmitter buffer descriptor bases */ @@ -265,7 +265,7 @@ m8260_scc_initialize_hardware (struct m8260_hdlc_struct *sc) m8260.scc3p.rbase = (char *)sc->rxBdBase - (char *)&m8260; m8260.scc3p.tbase = (char *)sc->txBdBase - (char *)&m8260; - + /* * Send "Init parameters" command */ @@ -277,7 +277,7 @@ m8260_scc_initialize_hardware (struct m8260_hdlc_struct *sc) */ m8260.scc3p.rfcr = M8260_RFCR_MOT | M8260_RFCR_60X_BUS; m8260.scc3p.tfcr = M8260_TFCR_MOT | M8260_TFCR_60X_BUS; - + /* * Set maximum receive buffer length */ @@ -394,7 +394,7 @@ m8260Enet_retire_tx_bd (struct m8260_hdlc_struct *sc) int i; int nRetired; struct mbuf *m, *n; - + i = sc->txBdTail; nRetired = 0; while ((sc->txBdActiveCount != 0) @@ -409,7 +409,7 @@ m8260Enet_retire_tx_bd (struct m8260_hdlc_struct *sc) */ if( status & M8260_BD_UNDERRUN ) { hdlc_driver[0].txUnderrun++; - + /* * Restart the transmitter */ @@ -451,7 +451,7 @@ scc_rxDaemon (void *arg) uint16_t status; m8260BufferDescriptor_t *rxBd; int rxBdIndex; - + /* * Allocate space for incoming packets and start reception */ @@ -479,7 +479,7 @@ scc_rxDaemon (void *arg) rxBdIndex = 0; for (;;) { rxBd = sc->rxBdBase + rxBdIndex; - + /* * Wait for packet if there's not one ready */ @@ -506,7 +506,7 @@ scc_rxDaemon (void *arg) m8260.scc3.sccm |= M8260_SCCE_RXF; /* printk( "Rxdwait "); */ - + rtems_bsdnet_event_receive (INTERRUPT_EVENT, RTEMS_WAIT|RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, @@ -515,7 +515,7 @@ scc_rxDaemon (void *arg) /* printk( "Rxd " ); */ } } - + /* * Check that packet is valid */ @@ -577,13 +577,13 @@ scc_rxDaemon (void *arg) if (status & M8260_BD_CARRIER_LOST) sc->rxLostCarrier++; } - + /* * Reenable the buffer descriptor */ rxBd->status = (status & (M8260_BD_WRAP | M8260_BD_INTERRUPT)) | M8260_BD_EMPTY; - + /* * Move to next buffer descriptor */ @@ -601,12 +601,12 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) struct mbuf *l = NULL; uint16_t status; int nAdded; - + /* * Free up buffer descriptors */ m8260Enet_retire_tx_bd (sc); - + /* * Set up the transmit buffer descriptors. * No need to pad out short packets since the @@ -630,7 +630,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) * Clear old events */ m8260.scc3.scce = M8260_SCCE_TX | M8260_SCCE_TXE; - + /* * Wait for buffer descriptor to become available. * Note that the buffer descriptors are checked @@ -646,7 +646,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) m8260Enet_retire_tx_bd (sc); while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { rtems_event_set events; - + /* * Unmask TX (buffer transmitted) event */ @@ -659,13 +659,13 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) m8260Enet_retire_tx_bd (sc); } } - + /* * Don't set the READY flag till the * whole packet has been readied. */ status = nAdded ? M8260_BD_READY : 0; - + /* * FIXME: Why not deal with empty mbufs at at higher level? * The IP fragmentation routine in ip_output @@ -715,7 +715,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) if (l != NULL) l->m_next = m; } - + /* * Set the transmit buffer status. * Break out of the loop if this mbuf is the last in the frame. @@ -745,13 +745,13 @@ scc_txDaemon (void *arg) struct ifnet *ifp = &sc->ac_if; struct mbuf *m; rtems_event_set events; - + for (;;) { /* * Wait for packet */ rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, RTEMS_EVENT_ANY | RTEMS_WAIT, RTEMS_NO_TIMEOUT, &events); - + /* * Send packets till queue is empty */ @@ -780,7 +780,7 @@ static void m8260_hdlc_start (struct ifnet *ifp) { struct m8260_hdlc_struct *sc = ifp->if_softc; - + rtems_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT); ifp->if_flags |= IFF_OACTIVE; } @@ -793,22 +793,22 @@ scc_init (void *arg) { struct m8260_hdlc_struct *sc = arg; struct ifnet *ifp = &sc->ac_if; - + if (sc->txDaemonTid == 0) { - + /* * Set up SCC hardware */ m8260_scc_initialize_hardware (sc); - + /* * Start driver tasks */ sc->txDaemonTid = rtems_bsdnet_newproc ("SCtx", 4096, scc_txDaemon, sc); sc->rxDaemonTid = rtems_bsdnet_newproc ("SCrx", 4096, scc_rxDaemon, sc); - + } - + #if 0 /* * Set flags appropriately @@ -823,7 +823,7 @@ scc_init (void *arg) * Tell the world that we're running. */ ifp->if_flags |= IFF_RUNNING; - + /* * Enable receiver and transmitter */ @@ -839,9 +839,9 @@ static void scc_stop (struct m8260_hdlc_struct *sc) { struct ifnet *ifp = &sc->ac_if; - + ifp->if_flags &= ~IFF_RUNNING; - + /* * Shut down receiver and transmitter */ @@ -862,7 +862,7 @@ hdlc_stats (struct m8260_hdlc_struct *sc) printf (" Overrun:%-8lu", sc->rxOverrun); printf (" No Carrier:%-8lu\n", sc->rxLostCarrier); printf (" Discarded:%-8lu\n", (unsigned long)m8260.scc3p.un.hdlc.disfc); - + printf (" Tx Interrupts:%-8lu", sc->txInterrupts); printf (" No Carrier:%-8lu", sc->txLostCarrier); printf (" Underrun:%-8lu\n", sc->txUnderrun); @@ -877,37 +877,37 @@ scc_ioctl (struct ifnet *ifp, int command, caddr_t data) { struct m8260_hdlc_struct *sc = ifp->if_softc; int error = 0; - + switch (command) { case SIOCGIFADDR: case SIOCSIFADDR: hdlc_ioctl (ifp, command, data); break; - + case SIOCSIFFLAGS: switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { case IFF_RUNNING: scc_stop (sc); break; - + case IFF_UP: scc_init (sc); break; - + case IFF_UP | IFF_RUNNING: scc_stop (sc); scc_init (sc); break; - + default: break; } break; - + case SIO_RTEMS_SHOW_STATS: hdlc_stats (sc); break; - + /* * FIXME: All sorts of multicast commands need to be added here! */ @@ -930,7 +930,7 @@ rtems_scc3_driver_attach (struct rtems_bsdnet_ifconfig *config) struct ifnet *ifp; int mtu; int i; - + /* * Find a free driver */ @@ -976,7 +976,7 @@ rtems_scc3_driver_attach (struct rtems_bsdnet_ifconfig *config) else sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF; sc->acceptBroadcast = !config->ignore_broadcast; - + /* * Set up network interface values */ @@ -991,7 +991,7 @@ rtems_scc3_driver_attach (struct rtems_bsdnet_ifconfig *config) ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | /*IFF_PROMISC |*/ IFF_NOARP; if (ifp->if_snd.ifq_maxlen == 0) ifp->if_snd.ifq_maxlen = ifqmaxlen; - + /* * Attach the interface */ diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/start/start.S b/c/src/lib/libbsp/powerpc/mpc8260ads/start/start.S index 021454fa0b..241e60212a 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/start/start.S +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/start/start.S @@ -42,23 +42,23 @@ */ - .section ".entry" /* This might have to be the first thing in the + .section ".entry" /* This might have to be the first thing in the * text section. At one time, it had to be * first, but I don't believe it is true * any more. */ PUBLIC_VAR (start) SYM(start): bl .startup -base_addr: +base_addr: /* * Parameters from linker */ -toc_pointer: +toc_pointer: .long s.got -bss_length: +bss_length: .long bss.size -bss_addr: +bss_addr: .long bss.start PUBLIC_VAR (data_length ) @@ -80,7 +80,7 @@ text_length: /* - * Initialization code + * Initialization code */ .startup: /* Get start address */ @@ -104,15 +104,15 @@ text_length: -#ifdef ENABLE_CACHE +#ifdef ENABLE_CACHE /* Enable caches */ mfspr r5, 1008 ori r5, r5, 0x8000 isync mtspr 1008, r5 - + /* Leave D-cache disabled for now */ -#if 0 +#if 0 ori r5, r5, 0x4000 sync mtspr 1008, r5 @@ -128,7 +128,7 @@ text_length: *-------------------------------------------------- */ lis r13, 0x0050 /* set nap mode and DPM */ - or r5, r5, r13 + or r5, r5, r13 mtspr 1008, r5 /*-------------------------------------------------- @@ -155,11 +155,11 @@ text_length: /* clear argc and argv */ xor r3, r3, r3 xor r4, r4, r4 - + .extern SYM (boot_card) bl SYM (boot_card) /* call the first C routine */ - + /* we don't expect to return from boot_card but if we do */ /* wait here for watchdog to kick us into hard reset */ diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c b/c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c index 9f35b9eaca..1aba24a0fd 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c @@ -180,11 +180,11 @@ extern void m8260_console_reserve_resources(rtems_configuration_table *); * not yet initialized. * */ - + void bsp_pretasking_hook(void) { - /* + /* * These are assigned addresses in the linkcmds file for the BSP. This * approach is better than having these defined as manifest constants and * compiled into the kernel, but it is still not ideal when dealing with @@ -200,16 +200,16 @@ bsp_pretasking_hook(void) bsp_libc_init( &_HeapStart, &_HeapEnd - &_HeapStart, 0 ); - + #ifdef STACK_CHECKER_ON /* * Initialize the stack bounds checker * We can either turn it on here or from the app. */ - + Stack_check_Initialize(); #endif - + #ifdef RTEMS_DEBUG rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); #endif @@ -266,7 +266,7 @@ void bsp_start(void) /* mmu_init(); */ - + /* * Enable instruction and data caches. Do not force writethrough mode. */ diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/mpc8260ads/startup/cpuinit.c index 8c5ff89d4b..28d7790fc6 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/startup/cpuinit.c +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/startup/cpuinit.c @@ -1,8 +1,8 @@ -/* - * cpuinit.c - this file contains functions for initializing the CPU +/* + * cpuinit.c - this file contains functions for initializing the CPU * * Written by Jay Monkman (jmonkman@frasca.com) - * + * * $Id$ */ @@ -24,14 +24,14 @@ void cpu_init(void) #if 0 register unsigned long t1, t2; - /* Let's clear MSR[IR] and MSR[DR] */ + /* Let's clear MSR[IR] and MSR[DR] */ t2 = PPC_MSR_IR | PPC_MSR_DR; __asm__ volatile ( "mfmsr %0\n" "andc %0, %0, %1\n" "mtmsr %0\n" :"=r"(t1), "=r"(t2): "1"(t2)); - + t1 = M8xx_CACHE_CMD_UNLOCK; /* PUT_DC_CST(t1); */ PUT_IC_CST(t1); diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/vectors/vectors.S b/c/src/lib/libbsp/powerpc/mpc8260ads/vectors/vectors.S index b60307ad3c..e22b8c247c 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/vectors/vectors.S +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/vectors/vectors.S @@ -2,26 +2,26 @@ * (c) 1999, Eric Valette valette@crf.canon.fr * * - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * exception veneers for RTEMS. * * $Id$ */ - + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include <bsp/vectors.h> - + #define SYNC \ sync; \ isync - + .text - .p2align 5 - + .p2align 5 + PUBLIC_VAR(default_exception_vector_code_prolog) SYM (default_exception_vector_code_prolog): /* @@ -34,7 +34,7 @@ SYM (default_exception_vector_code_prolog): stw r2, EXC_LR_OFFSET(r1) bl 0f 0: /* - * r3 = exception vector entry point + * r3 = exception vector entry point * (256 * vector number) + few instructions */ mflr r3 @@ -43,13 +43,13 @@ SYM (default_exception_vector_code_prolog): */ srwi r3,r3,8 ba push_normalized_frame - + PUBLIC_VAR (default_exception_vector_code_prolog_size) - + default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog - + .p2align 5 -PUBLIC_VAR (push_normalized_frame) +PUBLIC_VAR (push_normalized_frame) SYM (push_normalized_frame): stw r3, EXCEPTION_NUMBER_OFFSET(r1) stw r0, GPR0_OFFSET(r1) @@ -63,7 +63,7 @@ SYM (push_normalized_frame): * Saved a few line above : R0 * * Manual says that "stmw" instruction may be slower than - * series of individual "stw" but who cares about performance + * series of individual "stw" but who cares about performance * for the DEFAULT exception handler? */ stmw r4, GPR4_OFFSET(r1) /* save R4->R31 */ @@ -90,7 +90,7 @@ SYM (push_normalized_frame): ori r3,r3, MSR_RI /*| MSR_IR | MSR_DR*/ mtmsr r3 SYNC - + /* * Call C exception handler */ @@ -128,16 +128,16 @@ SYM (push_normalized_frame): xori r3, r3, MSR_RI /*| MSR_IR | MSR_DR*/ mtmsr r3 SYNC - + /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/vectors/vectors.h b/c/src/lib/libbsp/powerpc/mpc8260ads/vectors/vectors.h index fc841f0fa2..43fb7ecedf 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/vectors/vectors.h +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/vectors/vectors.h @@ -1,4 +1,4 @@ -/* +/* * vectors.h Exception frame related contant and API. * * This include file describe the data structure and the functions implemented @@ -16,10 +16,10 @@ #define LIBBSP_POWERPC_MBX8XX_VECTORS_H /* - * The callee (high level exception code written in C) + * The callee (high level exception code written in C) * will store the Link Registers (return address) at entry r1 + 4 !!!. * So let room for it!!!. - */ + */ #define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 #define SRR0_FRAME_OFFSET 8 #define SRR1_FRAME_OFFSET 12 @@ -81,7 +81,7 @@ extern int default_exception_vector_code_prolog_size; * zero, it performs more or less like memmove. No copy is performed if * source and destination addresses are equal. However the caches * are synchronized. Note that the size is always rounded up to the - * next mutiple of 4. + * next mutiple of 4. */ extern void * codemove(void *, const void *, unsigned int, unsigned long); extern void initialize_exceptions(); diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/vectors/vectors_init.c b/c/src/lib/libbsp/powerpc/mpc8260ads/vectors/vectors_init.c index 21863706a5..f77648c63a 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/vectors/vectors_init.c +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/vectors/vectors_init.c @@ -1,4 +1,4 @@ -/* +/* * vectors_init.c Exception hanlding initialisation (and generic handler). * * This include file describe the data structure and the functions implemented @@ -69,7 +69,7 @@ void C_exception_handler(BSP_Exception_frame* excPtr) if (excPtr->_EXC_number == ASM_DEC_VECTOR) recoverable = 1; if (excPtr->_EXC_number == ASM_SYS_VECTOR) -#ifdef TEST_RAW_EXCEPTION_CODE +#ifdef TEST_RAW_EXCEPTION_CODE recoverable = 1; #else recoverable = 0; diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/clock/clock.c b/c/src/lib/libbsp/powerpc/ppcn_60x/clock/clock.c index e08be577a8..5015453a00 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/clock/clock.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/clock/clock.c @@ -43,11 +43,11 @@ uint32_t Clock_Decrementer_value; rtems_isr_entry Old_ticker; void Clock_exit( void ); - + /* * These are set by clock driver during its init */ - + rtems_device_major_number rtems_clock_major = ~0; rtems_device_minor_number rtems_clock_minor; @@ -139,11 +139,11 @@ void Install_clock( void Clock_exit( void ) { - /* nothing to do */; + /* nothing to do */; /* do not restore old vector */ } - + /* * Clock_initialize * @@ -170,17 +170,17 @@ rtems_device_driver Clock_initialize( (BSP_Configuration.microseconds_per_tick/1000); Install_clock((rtems_isr_entry)Clock_isr); - + /* * make major/minor avail to others such as shared memory driver */ - + rtems_clock_major = major; rtems_clock_minor = minor; - + return RTEMS_SUCCESSFUL; } - + /* * Clock_control * @@ -205,15 +205,15 @@ rtems_device_driver Clock_control( { uint32_t isrlevel; rtems_libio_ioctl_args_t *args = pargp; - + if (args == 0) goto done; - + /* * This is hokey, but until we get a defined interface * to do this, it will just be this simple... */ - + if (args->command == rtems_build_name('I', 'S', 'R', ' ')) { Clock_isr( CLOCK_VECTOR, pargp ); @@ -224,7 +224,7 @@ rtems_device_driver Clock_control( (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); rtems_interrupt_enable( isrlevel ); } - + done: return RTEMS_SUCCESSFUL; } diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/console/config.c b/c/src/lib/libbsp/powerpc/ppcn_60x/console/config.c index 0e755266e5..1aace346a9 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/console/config.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/console/config.c @@ -429,7 +429,7 @@ static boolean config_PMX1553_probe(int minor) * Disable special register set and lock Enhanced Feature Register */ outport_byte(&pNS16550Write->LineControl, 0); - + /* * The PMX1553 currently uses a 16 MHz clock rather than the * 7.3728 MHz clock described in the ST16C654 data sheet. When diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/console/console.c b/c/src/lib/libbsp/powerpc/ppcn_60x/console/console.c index bfa9b7b4ea..54b167efc5 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/console/console.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/console/console.c @@ -44,7 +44,7 @@ console_data Console_Port_Data[NUM_CONSOLE_PORTS]; unsigned long Console_Port_Count; rtems_device_minor_number Console_Port_Minor; - + /* PAGE * * console_open @@ -82,9 +82,9 @@ rtems_device_driver console_open( Callbacks.pollRead = c->deviceRead; Callbacks.write = c->deviceWrite; Callbacks.setAttributes = c->deviceSetAttributes; - Callbacks.stopRemoteTx = + Callbacks.stopRemoteTx = Console_Port_Tbl[minor].pDeviceFlow->deviceStopRemoteTx; - Callbacks.startRemoteTx = + Callbacks.startRemoteTx = Console_Port_Tbl[minor].pDeviceFlow->deviceStartRemoteTx; Callbacks.outputUsesInterrupts = c->deviceOutputUsesInterrupts; status = rtems_termios_open ( major, minor, arg, &Callbacks); @@ -94,7 +94,7 @@ rtems_device_driver console_open( * Patch in flow control routines */ /* XXX */ -#if 0 +#if 0 if((status==RTEMS_SUCCESSFUL) && (Console_Port_Tbl[minor].pDeviceFlow)) { @@ -132,7 +132,7 @@ rtems_device_driver console_open( return status; } - + rtems_device_driver console_close( rtems_device_major_number major, rtems_device_minor_number minor, @@ -150,7 +150,7 @@ rtems_device_driver console_close( return rtems_termios_close (arg); } - + rtems_device_driver console_read( rtems_device_major_number major, rtems_device_minor_number minor, @@ -159,7 +159,7 @@ rtems_device_driver console_read( { return rtems_termios_read (arg); } - + rtems_device_driver console_write( rtems_device_major_number major, rtems_device_minor_number minor, @@ -168,7 +168,7 @@ rtems_device_driver console_write( { return rtems_termios_write (arg); } - + rtems_device_driver console_control( rtems_device_major_number major, rtems_device_minor_number minor, @@ -224,7 +224,7 @@ rtems_device_driver console_initialize( */ rtems_fatal_error_occurred(RTEMS_IO_ERROR); } - + Console_Port_Minor=minor; /* @@ -296,7 +296,7 @@ void DEBUG_puts( rtems_interrupt_disable(Irql); - for ( s = string ; *s ; s++ ) + for ( s = string ; *s ; s++ ) { Console_Port_Tbl[Console_Port_Minor].pDeviceFns-> deviceWritePolled(Console_Port_Minor, *s); @@ -329,7 +329,7 @@ DEBUG_puth( uint32_t Irql; rtems_interrupt_disable(Irql); - + Console_Port_Tbl[Console_Port_Minor].pDeviceFns-> deviceWritePolled(Console_Port_Minor, '0'); Console_Port_Tbl[Console_Port_Minor].pDeviceFns-> diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/console/debugio.c b/c/src/lib/libbsp/powerpc/ppcn_60x/console/debugio.c index bc4f97a69d..6b3234ef06 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/console/debugio.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/console/debugio.c @@ -38,7 +38,7 @@ extern console_data Console_Port_Data[]; extern rtems_device_minor_number Console_Port_Minor; - + /* PAGE * * DEBUG_puts @@ -95,7 +95,7 @@ void DEBUG_puth( unsigned long i,d; uint32_t Irql; void (*poll)(int minor, char cChar); - + poll = Console_Port_Tbl[Console_Port_Minor].pDeviceFns->deviceWritePolled; rtems_interrupt_disable(Irql); diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/console/i8042.c b/c/src/lib/libbsp/powerpc/ppcn_60x/console/i8042.c index 93ca26aced..b148c0f389 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/console/i8042.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/console/i8042.c @@ -94,7 +94,7 @@ static volatile Ring_buffer_t KbdInputBuffer; * to polled mode as required for command processing */ void i8042_polled_on( - int minor + int minor ) { #if CONSOLE_USE_INTERRUPTS @@ -103,7 +103,7 @@ void i8042_polled_on( } void i8042_polled_off( - int minor + int minor ) { #if CONSOLE_USE_INTERRUPTS @@ -856,7 +856,7 @@ static void i8042_scan_code( } } - /* + /* * If we got a character then queue it */ if(cChar) @@ -944,13 +944,13 @@ void i8042_init(int minor) /* PAGE * - * i8042_inbyte_nonblocking_polled + * i8042_inbyte_nonblocking_polled * * Console Termios polling input entry point. */ -int i8042_inbyte_nonblocking_polled( - int minor +int i8042_inbyte_nonblocking_polled( + int minor ) { uint8_t ucScan; diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/console/i8042_p.h b/c/src/lib/libbsp/powerpc/ppcn_60x/console/i8042_p.h index 57273fbe7f..544b4ef944 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/console/i8042_p.h +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/console/i8042_p.h @@ -73,7 +73,7 @@ extern "C" { #define KBD_CMD_ENABLE 0xf4 /* Clears Buffer and Starts Scanning. */ #define KBD_CMD_DISABLE 0xf5 /* reset to power up */ -#define KBD_CMD_SET_DEFAULT 0xf6 +#define KBD_CMD_SET_DEFAULT 0xf6 #define KBD_CMD_SET_ALL_TLMTIC 0xf7 /* Set all keys telematic */ #define KBD_CMD_SET_ALL_MKBR 0xf8 /* Set all keys Make /Break */ #define KBD_CMD_SET_ALL_MAKE 0xf9 /* Set all keys Make only */ diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/console/vga.c b/c/src/lib/libbsp/powerpc/ppcn_60x/console/vga.c index 9e67cc6541..ca93acb48d 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/console/vga.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/console/vga.c @@ -75,10 +75,10 @@ static uint8_t cursCol = 0; /* Current cursor column. */ /*-------------------------------------------------------------------------+ | Function: setHardwareCursorPos -| Description: Set hardware video cursor at given offset into video RAM. +| Description: Set hardware video cursor at given offset into video RAM. | Global Variables: None. | Arguments: videoCursor - Offset into video memory. -| Returns: Nothing. +| Returns: Nothing. +--------------------------------------------------------------------------*/ static inline void setHardwareCursorPos(uint16_t videoCursor) @@ -91,10 +91,10 @@ setHardwareCursorPos(uint16_t videoCursor) /*-------------------------------------------------------------------------+ | Function: updateVideoRamPtr | Description: Updates value of global variable "videoRamPtr" based on -| current window's cursor position. +| current window's cursor position. | Global Variables: videoRamPtr, cursRow, cursCol. | Arguments: None. -| Returns: Nothing. +| Returns: Nothing. +--------------------------------------------------------------------------*/ static inline void updateVideoRamPtr(void) @@ -108,7 +108,7 @@ updateVideoRamPtr(void) | Description: Scrolls display up n lines. | Global Variables: None. | Arguments: lines - number of lines to scroll. -| Returns: Nothing. +| Returns: Nothing. +--------------------------------------------------------------------------*/ static void scrollUp(uint8_t lines) @@ -130,7 +130,7 @@ scrollUp(uint8_t lines) blankCount = lines * videoCols; nonBlankCount = DISPLAY_CELL_COUNT - blankCount; ptrSrc = videoRam + blankCount; - ptrDst = videoRam; + ptrDst = videoRam; while(nonBlankCount--) { @@ -139,7 +139,7 @@ scrollUp(uint8_t lines) } else { - /* + /* * Clear the whole display. */ blankCount = DISPLAY_CELL_COUNT; @@ -159,7 +159,7 @@ scrollUp(uint8_t lines) | Description: Print printable character to display. | Global Variables: videoRamPtr, cursRow, cursCol. | Arguments: c - character to write to display. -| Returns: Nothing. +| Returns: Nothing. +--------------------------------------------------------------------------*/ static void printCHAR(char c) @@ -184,7 +184,7 @@ printCHAR(char c) | Description: Print BS (BackSpace - '\b') character to display. | Global Variables: videoRamPtr, cursRow, cursCol. | Arguments: None. -| Returns: Nothing. +| Returns: Nothing. +--------------------------------------------------------------------------*/ static inline void printBS(void) @@ -214,7 +214,7 @@ printBS(void) | Description: Print HT (Horizontal Tab - '\t') character to display. | Global Variables: cursCol. | Arguments: None. -| Returns: Nothing. +| Returns: Nothing. +--------------------------------------------------------------------------*/ static inline void printHT(void) @@ -232,7 +232,7 @@ printHT(void) | Description: Print LF (Line Feed - '\n') character to display. | Global Variables: cursRow. | Arguments: None. -| Returns: Nothing. +| Returns: Nothing. +--------------------------------------------------------------------------*/ static inline void printLF(void) @@ -252,7 +252,7 @@ printLF(void) | Description: Print CR (Carriage Return - '\r') to display. | Global Variables: cursCol. | Arguments: None. -| Returns: Nothing. +| Returns: Nothing. +--------------------------------------------------------------------------*/ static inline void printCR(void) @@ -266,7 +266,7 @@ printCR(void) */ void vga_write( - int minor, + int minor, char cChar) { switch (cChar) @@ -291,15 +291,15 @@ vga_write( setHardwareCursorPos(videoRamPtr - videoRam); } /* vga_write */ -/* +/* * vga_write_support * * Console Termios output entry point. * */ int vga_write_support( - int minor, - const char *buf, + int minor, + const char *buf, int len ) { diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/console/vga_p.h b/c/src/lib/libbsp/powerpc/ppcn_60x/console/vga_p.h index 3ab6cbc2ba..8541951bd0 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/console/vga_p.h +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/console/vga_p.h @@ -53,13 +53,13 @@ extern boolean vga_probe(int minor); extern void vga_init(int minor); extern void vga_write( - int minor, + int minor, char cChar ); extern int vga_write_support( - int minor, - const char *buf, + int minor, + const char *buf, int len ); diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/console/z85c30cfg.c b/c/src/lib/libbsp/powerpc/ppcn_60x/console/z85c30cfg.c index 4aeafe3939..5072a91b29 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/console/z85c30cfg.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/console/z85c30cfg.c @@ -28,7 +28,7 @@ #include <rtems.h> #include <bsp.h> -/* +/* * Read_85c30_register * * Read a Z85c30 register @@ -64,7 +64,7 @@ void Write_85c30_register( outport_byte(ulCtrlPort, ucData); } -/* +/* * Read_85c30_data * * Read a Z85c30 data register diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/include/bsp.h b/c/src/lib/libbsp/powerpc/ppcn_60x/include/bsp.h index f423e8dea7..412d76ace0 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/include/bsp.h @@ -42,7 +42,7 @@ extern "C" { #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 #define CONFIGURE_INTERRUPT_STACK_MEMORY (32 * 1024) - + /* Define processor identification. */ #define MPC601 1 @@ -157,8 +157,8 @@ extern "C" { /* * 8259 IRQ definations. */ -#define PPCN_60X_IRQ_SYS_TIMER (PPCN_60X_8259_IRQ_BASE + 0) -#define PPCN_60X_IRQ_KBD (PPCN_60X_8259_IRQ_BASE + 1) +#define PPCN_60X_IRQ_SYS_TIMER (PPCN_60X_8259_IRQ_BASE + 0) +#define PPCN_60X_IRQ_KBD (PPCN_60X_8259_IRQ_BASE + 1) #define PPCN_60X_IRQ_COM2 (PPCN_60X_8259_IRQ_BASE + 3) #define PPCN_60X_IRQ_COM1 (PPCN_60X_8259_IRQ_BASE + 4) #define PPCN_60X_IRQ_CIO (PPCN_60X_8259_IRQ_BASE + 5) @@ -343,7 +343,7 @@ void InitializeNvRAM(void); #define BSP_TIMER_LEAST_VALID 1 /* Don't trust a value lower than this */ /* - * Convert decrement value to tenths of microsecnds (used by + * Convert decrement value to tenths of microsecnds (used by * shared timer driver). * * + There are 4 bus cycles per click @@ -404,19 +404,19 @@ void InitializeNvRAM(void); /* * Device Driver Table Entries */ - + /* * NOTE: Use the standard Console driver entry */ - + /* * NOTE: Use the standard Clock driver entry */ - + /* * How many libio files we want */ - + #define BSP_LIBIO_MAX_FDS 20 /* functions */ @@ -436,13 +436,13 @@ rtems_isr_entry set_vector( /* returns old vector */ */ rtems_isr bsp_stub_handler( rtems_vector_number trap -); +); rtems_isr bsp_spurious_handler( rtems_vector_number trap ); void bsp_spurious_initialize(); -/* +/* * genvec.c */ void set_EE_vector( diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/include/extisrdrv.h b/c/src/lib/libbsp/powerpc/ppcn_60x/include/extisrdrv.h index 32d0e7562c..3ed86b3564 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/include/extisrdrv.h +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/include/extisrdrv.h @@ -20,7 +20,7 @@ extern rtems_device_minor_number rtems_externalISR_minor; #define EXTISR_DRIVER_TABLE_ENTRY \ { ExternalISR_initialize, NULL, NULL, NULL, NULL, ExternalISR_control } - + rtems_device_driver ExternalISR_initialize( rtems_device_major_number, rtems_device_minor_number, diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/network/amd79c970.c b/c/src/lib/libbsp/powerpc/ppcn_60x/network/amd79c970.c index 2ad0b8e02a..c09bf2a1d5 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/network/amd79c970.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/network/amd79c970.c @@ -39,7 +39,7 @@ * The number of transmit buffer descriptors has to be quite large * since a single frame often uses four or more buffer descriptors. * - * Set the number of Tx and Rx buffers, using Log_2(# buffers). + * Set the number of Tx and Rx buffers, using Log_2(# buffers). */ #define LANCE_LOG2_TX_BUFFERS 4 #define LANCE_LOG2_RX_BUFFERS 4 @@ -76,11 +76,11 @@ #define RD_CSR32(dp, index, value) \ PCNET_IO_WR32(dp, rap, index); \ PCNET_IO_RD32(dp, rdp, value) - + #define WR_CSR32(dp, index, value) \ PCNET_IO_WR32(dp, rap, index); \ PCNET_IO_WR32(dp, rdp, value) - + #define RD_BCR32(dp, index, value) \ PCNET_IO_WR32(dp, rap, index); \ PCNET_IO_RD32(dp, bdp, value) @@ -363,21 +363,21 @@ amd79c970_initialize_hardware (int instance, int broadcastFlag) } /* - * Set the receive descriptor ring length + * Set the receive descriptor ring length */ dp->initBlk.ib_rlen=RX_RING_LEN_BITS; /* - * Set the receive descriptor ring address + * Set the receive descriptor ring address */ dp->initBlk.ib_rdra=Swap32((uint32_t)&dp->rxBdBase[0]+ PCI_SYS_MEM_BASE); /* - * Set the transmit descriptor ring length + * Set the transmit descriptor ring length */ dp->initBlk.ib_tlen=TX_RING_LEN_BITS; /* - * Set the tranmit descriptor ring address + * Set the tranmit descriptor ring address */ dp->initBlk.ib_tdra=Swap32((uint32_t)&dp->txBdBase[0]+ PCI_SYS_MEM_BASE); @@ -386,7 +386,7 @@ amd79c970_initialize_hardware (int instance, int broadcastFlag) { dp->initBlk.ib_padr[i]=dp->iface->hwaddr[i]; } - + /* * Ensure that we are in DWIO mode */ @@ -405,13 +405,13 @@ amd79c970_initialize_hardware (int instance, int broadcastFlag) ulInitClkPCIAddr=(uint32_t)&dp->initBlk+PCI_SYS_MEM_BASE; /* - * CSR2 must contain the high order 16 bits of the first word in - * the initialization block + * CSR2 must contain the high order 16 bits of the first word in + * the initialization block */ WR_CSR32(dp, CSR2, (ulInitClkPCIAddr >> 16) & 0xffff); /* - * CSR1 must contain the low order 16 bits of the first word in - * the initialization block + * CSR1 must contain the low order 16 bits of the first word in + * the initialization block */ WR_CSR32(dp, CSR1, (ulInitClkPCIAddr & 0xffff)); @@ -752,7 +752,7 @@ amd79c970_rx (int dev, void *p1, void *p2) /* * Give the network code a chance to digest the - * packet. This guards against a flurry of + * packet. This guards against a flurry of * incoming packets (usually an ARP storm) from * using up all the available memory. */ @@ -876,7 +876,7 @@ amd79c970_show (struct iface *iface) * Following arguments are optional, but if present, must appear in * the following order: * Following arguments are optional, but if Ethernet address is - * specified, Internet address must also be specified. + * specified, Internet address must also be specified. * ###.###.###.### -- IP address * ##:##:##:##:##:## -- Ethernet address */ @@ -946,7 +946,7 @@ rtems_ka9q_driver_attach (int argc, char *argv[], void *p) * Set receive buffer descriptor count */ dp->rxBdCount=RX_RING_SIZE; - + /* * Set transmit buffer descriptor count */ diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/network/amd79c970.h b/c/src/lib/libbsp/powerpc/ppcn_60x/network/amd79c970.h index f600611418..8f81ebf568 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/network/amd79c970.h +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/network/amd79c970.h @@ -17,7 +17,7 @@ #define _PCNET_H /* - * IO space structure for the AMD79C970 device + * IO space structure for the AMD79C970 device */ typedef volatile struct pc_net @@ -69,10 +69,10 @@ typedef struct pc_net_eeprom { } pc_net_eeprom_t; /* - * PCnet-PCI Single Chip Ethernet Controller for PCI Local Bus + * PCnet-PCI Single Chip Ethernet Controller for PCI Local Bus */ /* - * Register and bit definitions + * Register and bit definitions */ #define CSR0 0 @@ -104,7 +104,7 @@ typedef struct pc_net_eeprom { #define APROM2 0x08 /* - * CSR0: Bit definitions + * CSR0: Bit definitions */ #define CSR0_ERR 0x8000 /* error summary */ #define CSR0_BABL 0x4000 /* babble error */ @@ -181,10 +181,10 @@ typedef struct pc_net_eeprom { #define CSR80_XMTFW16 (0<<8) /* fifo level to stop dma */ #define CSR80_XMTFW32 (1<<8) #define CSR80_XMTFW64 (2<<8) -/* must also clear csr4 CSR4_DMAPLUS: */ +/* must also clear csr4 CSR4_DMAPLUS: */ #define CSR80_DMATC(x) ((x)&0xff) /* max transfers per burst. deflt 16 */ /* - * must also set csr4 CSR4_TIMER: + * must also set csr4 CSR4_TIMER: */ #define CSR82_DMABAT(x) ((x)&0xffff) /* max burst time nanosecs*100 */ @@ -198,12 +198,12 @@ typedef struct pc_net_eeprom { #define BCR19_PVALID 0x8000 /* aprom (eeprom) read checksum ok */ /* - * initial setting of csr0 + * initial setting of csr0 */ #define CSR0_IVALUE (CSR0_IDON | CSR0_IENA | CSR0_STRT | CSR0_INIT) /* - * our setting of csr3 + * our setting of csr3 */ #define CSR3_VALUE (CSR3_ACON | CSR3_BSWP) @@ -226,7 +226,7 @@ typedef volatile struct initblk { * The bytes must be swapped within the word, so that, for example, * the address 8:0:20:1:25:5a is written in the order * 0 8 1 20 5a 25 - * For PCI970 that is long word swapped: so no swapping needed, since + * For PCI970 that is long word swapped: so no swapping needed, since * the bus will swap. */ uint8_t ib_padr[8]; /* physical address */ @@ -237,11 +237,11 @@ typedef volatile struct initblk { /* - * bits in mode register: allows alteration of the chips operating parameters + * bits in mode register: allows alteration of the chips operating parameters */ #define IBM_PROM 0x8000 /* promiscuous mode */ /* - * mode is also in cr15 + * mode is also in cr15 */ #define MODE_DRCVBC 0x4000 /* disable receive broadcast */ #define MODE_DRCVPA 0x2000 /* disable receive physical address */ @@ -259,15 +259,15 @@ typedef volatile struct initblk { #define IBM_DTX 0x0002 /* disable transmitter */ #define IBM_DRX 0x0001 /* disable receiver */ -/* +/* * Buffer Management is accomplished through message descriptors organized * in ring structures in main memory. There are two rings allocated for the - * device: a receive ring and a transmit ring. The following defines the + * device: a receive ring and a transmit ring. The following defines the * structure of the descriptor rings. */ /* - * Receive List type definition + * Receive List type definition * * This essentially consists of 4, 32 bit LE words. In the following the * fields are ordered so that they map correctly in BE mode, however each @@ -277,7 +277,7 @@ typedef volatile struct initblk { typedef volatile struct rmde { uint32_t rmde_addr; /* buf addr */ - uint16_t rmde_bcnt; + uint16_t rmde_bcnt; uint16_t rmde_flags; uint16_t rmde_mcnt; @@ -288,7 +288,7 @@ typedef volatile struct rmde { /* - * bits in the flags field + * bits in the flags field */ #define RFLG_OWN 0x8000 /* ownership bit, 1==LANCE */ #define RFLG_ERR 0x4000 /* error summary */ @@ -300,19 +300,19 @@ typedef volatile struct rmde { #define RFLG_ENP 0x0100 /* end of packet */ /* - * bits in the buffer byte count field + * bits in the buffer byte count field */ #define RBCNT_ONES 0xf000 /* must be ones */ #define RBCNT_BCNT 0x0fff /* buf byte count, in 2's compl */ /* - * bits in the message byte count field + * bits in the message byte count field */ #define RMCNT_RES 0xf000 /* reserved, read as zeros */ #define RMCNT_BCNT 0x0fff /* message byte count */ /* - * Transmit List type definition + * Transmit List type definition * * This essentially consists of 4, 32 bit LE words. In the following the * fields are ordered so that they map correctly in BE mode, however each @@ -321,7 +321,7 @@ typedef volatile struct rmde { typedef volatile struct tmde { uint32_t tmde_addr; /* buf addr */ - uint16_t tmde_bcnt; + uint16_t tmde_bcnt; uint16_t tmde_status; /* misc error and status bits */ uint32_t tmde_error; @@ -330,7 +330,7 @@ typedef volatile struct tmde { } tmde_t; /* - * bits in the status field + * bits in the status field */ #define TST_OWN 0x8000 /* ownership bit, 1==LANCE */ #define TST_ERR 0x4000 /* error summary */ @@ -342,18 +342,18 @@ typedef volatile struct tmde { #define TST_ENP 0x0100 /* end of packet */ /* - * setting of status field when packet is to be transmitted + * setting of status field when packet is to be transmitted */ #define TST_XMIT (TST_STP | TST_ENP | TST_OWN) /* - * bits in the buffer byte count field + * bits in the buffer byte count field */ #define TBCNT_ONES 0xf000 /* must be ones */ #define TBCNT_BCNT 0x0fff /* buf byte count, in 2's compl */ /* - * bits in the error field + * bits in the error field */ #define TERR_BUFF 0x8000 /* buffer error */ #define TERR_UFLO 0x4000 /* underflow error */ @@ -368,7 +368,7 @@ typedef volatile struct tmde { */ /* - * receive errors + * receive errors */ #define ERR_FRAM 0 /* framing error */ #define ERR_OFLO 1 /* overflow error */ @@ -376,7 +376,7 @@ typedef volatile struct tmde { #define ERR_RBUFF 3 /* receive buffer error */ /* - * transmit errors + * transmit errors */ #define ERR_MORE 4 /* more than one retry */ #define ERR_ONE 5 /* one retry */ @@ -388,7 +388,7 @@ typedef volatile struct tmde { #define ERR_RTRY 11 /* retry error, >16 retries */ /* - * errors reported in csr0 + * errors reported in csr0 */ #define ERR_BABL 12 /* transmitter timeout error */ #define ERR_MISS 13 /* missed packet */ @@ -400,7 +400,7 @@ typedef volatile struct tmde { #define NHARD_ERRORS 18 /* error types used in diagnostic */ /* - * other statistics + * other statistics */ #define ERR_TTOUT 18 /* transmit timeouts */ #define ERR_ITOUT 19 /* init timeouts */ @@ -412,7 +412,7 @@ typedef volatile struct tmde { #define NUM_ERRORS 24 /* number of errors types */ /* - * Bit definitions for BCR19 + * Bit definitions for BCR19 */ #define prom_EDI (uint16_t)0x0001 #define prom_EDO (uint16_t)0x0001 diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/mk48t18.h b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/mk48t18.h index 958fd5a557..10bfb872a5 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/mk48t18.h +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/mk48t18.h @@ -31,7 +31,7 @@ * The CRC's are computed with x**16+x**12+x**5 + 1 polynomial * The clock is kept in 24 hour BCD mode and should be set to UT(GMT) */ - + typedef struct _MK48T18_CMOS_MAP { uint8_t SystemDependentArea2[8]; uint8_t FeatureByte0[1]; diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/nvram.c b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/nvram.c index 790542f155..146ae4567c 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/nvram.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/nvram.c @@ -33,7 +33,7 @@ void ); typedef -uint8_t +uint8_t (*PNVRAMREAD) ( uint32_t ulOffset diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/prepnvr.h b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/prepnvr.h index cf55a4525d..058cf7b45a 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/prepnvr.h +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/nvram/prepnvr.h @@ -1,29 +1,29 @@ /* Structure map for NVRAM on PowerPC Reference Platform */ - + /* Revision 1 changes (8/25/94): - Power Management (RESTART_BLOCK struct) - Normal added to PM_MODE - OSIRQMask (HEADER struct) */ - + /* All fields are either character/byte strings which are valid either endian or they are big-endian numbers. - + There are a number of Date and Time fields which are in RTC format, big-endian. These are stored in UT (GMT). - + For enum's: if given in hex then they are bit significant, i.e. only one bit is on for each enum. */ - + #ifndef _NVRAM_ #define _NVRAM_ #define VERSION 1 #define REVISION 0 - + #define OSAREASIZE 1024 /* size of OSArea space */ #define CONFSIZE 512 /* guess at size of Configuration space */ - + typedef struct _SECURITY { unsigned long BootErrCnt; /* Count of boot password errors */ unsigned long ConfigErrCnt; /* Count of config password errors */ @@ -35,7 +35,7 @@ typedef struct _SECURITY { unsigned long ConfigSetDT[2]; /* Date&Time from RTC of last set of pw */ unsigned char Serial[16]; /* Box serial number */ } SECURITY; - + typedef enum _OS_ID { Unknown = 0, Firmware = 1, @@ -50,41 +50,41 @@ typedef enum _OS_ID { Low_End_Client = 10, SCO = 11 } OS_ID; - + typedef struct _ERROR_LOG { unsigned char ErrorLogEntry[40]; /* To be architected */ } ERROR_LOG; - + /*---Revision 1: Change the following struct:---*/ typedef struct _RESUME_BLOCK { /* Hibernation Resume Device will be an environment variable */ unsigned long CheckSum; /* Checksum of RESUME_BLOCK */ volatile unsigned long BootStatus; - + void * ResumeAddr; /* For Suspend Resume */ void * SaveAreaAddr; /* For Suspend Resume */ unsigned long SaveAreaLength; /* For Suspend Resume */ - + unsigned long HibResumeImageRBA; /* RBA (512B blocks) of compressed OS memory image to be loaded by FW on Resume from hibernation */ unsigned long HibResumeImageRBACount; /* Size of image in 512B blocks*/ unsigned long Reserved; } RESUME_BLOCK; - + typedef enum _OSAREA_USAGE { Empty = 0, Used = 1 } OSAREA_USAGE; - + typedef enum _PM_MODE { Suspend = 0x80, /* Part of state is in memory */ Hibernate = 0x40, /* Nothing in memory - state saved elsewhere */ /* Revision 1: Normal added (actually was already here) */ Normal = 0x00 /* No power management in effect */ } PMMode; - + typedef struct _HEADER { unsigned short Size; /* NVRAM size in K(1024) */ unsigned char Version; /* Structure map different */ @@ -100,28 +100,28 @@ typedef struct _HEADER { RESUME_BLOCK ResumeBlock; SECURITY Security; ERROR_LOG ErrorLog[2]; - + /* Global Environment information */ void * GEAddress; unsigned long GELength; /* Date&Time from RTC of last change to Global Environment */ unsigned long GELastWriteDT[2]; - + /* Configuration information */ void * ConfigAddress; unsigned long ConfigLength; /* Date&Time from RTC of last change to Configuration */ unsigned long ConfigLastWriteDT[2]; unsigned long ConfigCount; /* Count of entries in Configuration */ - + /* OS dependent temp area */ void * OSAreaAddress; unsigned long OSAreaLength; /* Date&Time from RTC of last change to OSAreaArea */ unsigned long OSAreaLastWriteDT[2]; - + /* Revision 1: add this mask - function tbd */ /*unsigned short OSIRQMask; OS to FW IRQ Mask - "I've used this one" */ } HEADER, *PHEADER; - + #endif /* ndef _NVRAM_ */ diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/start/start.S b/c/src/lib/libbsp/powerpc/ppcn_60x/start/start.S index 8761450bd6..05d463c2ee 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/start/start.S +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/start/start.S @@ -75,7 +75,7 @@ _start: ori r3,r3 ,H0_60X_ICE #endif mtspr HID0,r3 - + /* clear bss */ lis r6,__bss_start@h ori r6,r6,__bss_start@l diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/startup/bspstart.c b/c/src/lib/libbsp/powerpc/ppcn_60x/startup/bspstart.c index 5e34429c09..ca313e001b 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/startup/bspstart.c @@ -27,7 +27,7 @@ * the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * $Id: + * $Id: */ #include <string.h> @@ -61,7 +61,7 @@ static unsigned long ulBusSpeed[] = { * The original table from the application and our copy of it with * some changes. */ - + extern rtems_configuration_table Configuration; rtems_configuration_table BSP_Configuration; @@ -142,13 +142,13 @@ void bsp_std_close( void ) close(stdout_fd); close(stderr_fd); } - + /* * bsp_predriver_hook * * Before drivers are setup. - */ + */ void bsp_predriver_hook(void) { /* bsp_spurious_initialize; ??*/ @@ -266,7 +266,7 @@ void bsp_start( void ) * of work space from the last physical address on the CPU board. */ - work_space_start = + work_space_start = (unsigned char *)ulMemorySize - BSP_Configuration.work_space_size; if ( work_space_start <= (unsigned char *)&end ) { @@ -282,7 +282,7 @@ void bsp_start( void ) Cpu_table.exceptions_in_RAM = TRUE; Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ - Cpu_table.predriver_hook = bsp_predriver_hook; + Cpu_table.predriver_hook = bsp_predriver_hook; Cpu_table.postdriver_hook = bsp_postdriver_hook; Cpu_table.do_zero_of_workspace = TRUE; Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY; diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/startup/genpvec.c b/c/src/lib/libbsp/powerpc/ppcn_60x/startup/genpvec.c index a7a6f3dacc..98348b1020 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/startup/genpvec.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/startup/genpvec.c @@ -32,8 +32,8 @@ #include <rtems/chain.h> #include <assert.h> -/* - * Proto types for this file +/* + * Proto types for this file */ rtems_isr external_exception_ISR ( @@ -49,8 +49,8 @@ rtems_isr external_exception_ISR ( uint8_t ucMaster8259Mask; uint8_t ucSlave8259Mask; -/* - * Structure to for one of possible multiple interrupt handlers for +/* + * Structure to for one of possible multiple interrupt handlers for * a given interrupt. */ typedef struct @@ -65,7 +65,7 @@ typedef struct * handlers at a later time. */ EE_ISR_Type ISR_Nodes [NUM_LIRQ_HANDLERS]; - uint16_t Nodes_Used; + uint16_t Nodes_Used; Chain_Control ISR_Array [NUM_LIRQ]; void initialize_external_exception_vector() @@ -139,7 +139,7 @@ void initialize_external_exception_vector() ELCRM_INT5_LVL); break; } - + case SYS_TYPE_PPC2: case SYS_TYPE_PPC2a: case SYS_TYPE_PPC4: @@ -158,18 +158,18 @@ void initialize_external_exception_vector() } } - /* - * Install external_exception_ISR () as the handler for + /* + * Install external_exception_ISR () as the handler for * the General Purpose Interrupt. */ - status = rtems_interrupt_catch( external_exception_ISR, + status = rtems_interrupt_catch( external_exception_ISR, PPC_IRQ_EXTERNAL, (rtems_isr_entry *) &previous_isr ); } /* - * This routine installs one of multiple ISRs for the general purpose + * This routine installs one of multiple ISRs for the general purpose * inerrupt. */ void set_EE_vector( @@ -200,7 +200,7 @@ void set_EE_vector( * Doing things in this order makes them more atomic */ - Nodes_Used++; + Nodes_Used++; index = Nodes_Used - 1; @@ -215,13 +215,13 @@ void set_EE_vector( En_Ext_Interrupt(vector); } -/* +/* * This interrupt service routine is called for an External Exception. */ rtems_isr external_exception_ISR ( rtems_vector_number vector /* IN */ ) -{ +{ uint16_t index; uint8_t ucISr; EE_ISR_Type *node; diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/startup/setvec.c b/c/src/lib/libbsp/powerpc/ppcn_60x/startup/setvec.c index 240d4577c0..435da9dc02 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/startup/setvec.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/startup/setvec.c @@ -19,7 +19,7 @@ * the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * $Id: + * $Id: */ #include <rtems.h> @@ -27,8 +27,8 @@ /* - * This routine installs vector number vector. - * + * This routine installs vector number vector. + * */ rtems_isr_entry set_vector( /* returns old vector */ rtems_isr_entry handler, /* isr routine */ @@ -39,7 +39,7 @@ rtems_isr_entry set_vector( /* returns old vector */ rtems_isr_entry previous_isr; rtems_status_code status; - /* + /* * vectors greater than PPC_IRQ_LAST are handled by the General purpose * interupt handler. (8259) */ diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/startup/spurious.c b/c/src/lib/libbsp/powerpc/ppcn_60x/startup/spurious.c index 3ead7a7892..6a1a427a0f 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/startup/spurious.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/startup/spurious.c @@ -1,12 +1,12 @@ /* * PPCn_60x Spurious Trap Handler * - * This is just enough of a trap handler to let us know what + * This is just enough of a trap handler to let us know what * the likely source of the trap was. * * Based upon the SPARC ERC32 version which was developed as - * part of the port of RTEMS to the ERC32 implementation - * of the SPARC by On-Line Applications Research Corporation (OAR) + * part of the port of RTEMS to the ERC32 implementation + * of the SPARC by On-Line Applications Research Corporation (OAR) * under contract to the European Space Agency (ESA). * * COPYRIGHT (c) 1995. European Space Agency. @@ -41,7 +41,7 @@ rtems_isr bsp_spurious_handler( DEBUG_puts( "Spurious Trap" ); - + switch ( trap ) { case PPC_IRQ_SYSTEM_RESET: DEBUG_puts( "System reset" ); @@ -88,7 +88,7 @@ rtems_isr bsp_spurious_handler( #if defined(ppc403) || defined(ppc405) case PPC_IRQ_CRIT : - DEBUG_puts( "Critical Error "); + DEBUG_puts( "Critical Error "); break; case PPC_IRQ_PIT: DEBUG_puts( "Prog. Interval Timer " ); @@ -104,13 +104,13 @@ rtems_isr bsp_spurious_handler( break; #elif defined(ppc601) -#error "Please fill in names. " +#error "Please fill in names. " case PPC_IRQ_TRACE : DEBUG_puts( "0x02000" ); break; #elif defined(ppc603) -#error "Please fill in names. " +#error "Please fill in names. " case PPC_IRQ_TRANS_MISS : DEBUG_puts( "0x1000" ); break; @@ -145,7 +145,7 @@ rtems_isr bsp_spurious_handler( break; #elif defined(mpc604) -#error "Please fill in names. " +#error "Please fill in names. " case PPC_IRQ_ADDR_BRK: DEBUG_puts( "0x1300" ); break; @@ -184,7 +184,7 @@ void bsp_spurious_initialize() * trap 0 which we will use as a shutdown. */ - set_vector( bsp_spurious_handler, trap, 1 ); + set_vector( bsp_spurious_handler, trap, 1 ); } set_vector( bsp_stub_handler, PPC_IRQ_DECREMENTER, 1 ); diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/startup/swap.c b/c/src/lib/libbsp/powerpc/ppcn_60x/startup/swap.c index 5ea1c39b0c..68072fe502 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/startup/swap.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/startup/swap.c @@ -37,7 +37,7 @@ inline unsigned int Swap32( "rlwimi %0,%1,24,16,23;" "rlwimi %0,%1,8,8,15;" "rlwimi %0,%1,24,0,7;" : - + "=&r" ((ulSwapped)) : "r" ((ulValue)) ); diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/timer/timer.c b/c/src/lib/libbsp/powerpc/ppcn_60x/timer/timer.c index 9d82edb0da..8b38bf11b6 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/timer/timer.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/timer/timer.c @@ -26,7 +26,7 @@ uint64_t Timer_driver_Start_time; rtems_boolean Timer_driver_Find_average_overhead; /* - * Timer_initialize + * Timer_initialize */ void Timer_initialize() { diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/tod/cmos.h b/c/src/lib/libbsp/powerpc/ppcn_60x/tod/cmos.h index 6df03f6cbd..1d544133bc 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/tod/cmos.h +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/tod/cmos.h @@ -17,7 +17,7 @@ /* CMOS is the 64 bytes of RAM in the DS1385 chip */ /* The CRC's are computed with x**16+x**12+x**5 + 1 polynomial */ /* The clock is kept in 24 hour BCD mode and should be set to UT(GMT) */ - + #ifndef _CMOS_ #define _CMOS_ @@ -65,7 +65,7 @@ /* Define Control Register D structure. */ #define DS1385_REGD_VALID 0x80 - + typedef struct _CMOS_MAP { volatile uint8_t DateAndTime[14]; @@ -91,5 +91,5 @@ typedef struct _CMOS_MAP { attribute = lock */ uint8_t ConfigCrc[2]; /* CRC on ConfigPW */ } CMOS_MAP, *PCMOS_MAP; - + #endif /* _CMOS_ */ diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/tod/tod.c b/c/src/lib/libbsp/powerpc/ppcn_60x/tod/tod.c index 7872747a6a..2b2c03392f 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/tod/tod.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/tod/tod.c @@ -88,7 +88,7 @@ static rtems_id semRTC; /* * This only works for the Gregorian calendar - i.e. after 1752 (in the UK) */ -uint8_t +uint8_t GregorianDay(rtems_time_of_day *pTOD) { boolean isLeap; @@ -164,7 +164,7 @@ Return Value: return; } -uint8_t +uint8_t DsReadRawClockRegister ( uint8_t Register ) @@ -233,7 +233,7 @@ Return Value: return; } -uint8_t +uint8_t DsReadClockRegister ( uint8_t Register ) diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/universe/universe.c b/c/src/lib/libbsp/powerpc/ppcn_60x/universe/universe.c index 19a53ce56a..ca0d048450 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/universe/universe.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/universe/universe.c @@ -100,9 +100,9 @@ typedef struct { uint32_t V6_STATID; /* Offset 0x0338 */ uint32_t V7_STATID; /* Offset 0x033C */ uint32_t Buf_Offset_0x0340[ 0x30 ]; /* Offset 0x0340 */ - uint32_t MAST_CTL; /* Offset 0x0400 */ - uint32_t MISC_CTL; /* Offset 0x0404 */ - uint32_t MISC_STAT; /* Offset 0x0408 */ + uint32_t MAST_CTL; /* Offset 0x0400 */ + uint32_t MISC_CTL; /* Offset 0x0404 */ + uint32_t MISC_STAT; /* Offset 0x0408 */ uint32_t USER_AM; /* Offset 0x040C */ uint32_t Buf_Offset_0x0410[ 0x2bc ];/* Offset 0x0410 */ uint32_t VSI0_CTL; /* Offset 0x0F00 */ @@ -146,7 +146,7 @@ volatile Universe_Memory *UNIVERSE; void PCI_bus_write( volatile uint32_t * _addr, /* IN */ uint32_t _data /* IN */ -) +) { outport_32(_addr, _data); } @@ -156,7 +156,7 @@ uint32_t PCI_bus_read( ) { uint32_t data; - + inport_32(_addr, data); return data; } @@ -179,14 +179,14 @@ void InitializeUniverse() { uint32_t pci_id; uint32_t universe_temp_value; - + /* - * Verify the UNIVERSE CHIP ID + * Verify the UNIVERSE CHIP ID */ (void)PCIConfigRead32(0,4,0,PCI_CONFIG_VENDOR_LOW, &pci_id); - /* - * compare to known ID + /* + * compare to known ID */ if (pci_id != 0x000010e3 ){ DEBUG_puts ("Invalid PPCN_60X_UNIVERSE_CHIP_ID: "); @@ -205,16 +205,16 @@ void InitializeUniverse() PCI_ENABLE_MEMORY_SPACE | PCI_ENABLE_BUS_MASTER); - /* + /* * Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register */ - PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 ); + PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 ); #if 0 /* * Set VMEbus Slave Image 0 Base Address to 0x04000000 on VSI0_BS register. */ - PCI_bus_write( &UNIVERSE->VSI0_BS, 0x04000000 ); + PCI_bus_write( &UNIVERSE->VSI0_BS, 0x04000000 ); /* * Set VMEbus Slave Image 0 Bound Address to 0x05000000 on VSI0_BD register. @@ -222,7 +222,7 @@ void InitializeUniverse() PCI_bus_write( &UNIVERSE->VSI0_BD, 0x05000000 ); /* - * VMEbus Slave Image 0 Translation Offset to 0x7C000000 on VSI0_TO + * VMEbus Slave Image 0 Translation Offset to 0x7C000000 on VSI0_TO * register. Map the VME base address 0x4000000 to local memory address 0x0 */ PCI_bus_write( &UNIVERSE->VSI0_TO, 0x7C000000 ); @@ -231,12 +231,12 @@ void InitializeUniverse() * Set the VMEbus Slave Image 0 Control register with write posted, * read prefetch and AM code set for program, data, supervisor and user mode */ - PCI_bus_write( &UNIVERSE->VSI0_CTL, 0xE0F20000 ); + PCI_bus_write( &UNIVERSE->VSI0_CTL, 0xE0F20000 ); #endif /* * Set the VMEbus Master Control register with retry forever, 256 bytes - * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes + * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes * aligned burst size and PCI bus number to be zero */ PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 ); @@ -245,9 +245,9 @@ void InitializeUniverse() * VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data * width, A32 VMEbus Address Space, AM code to be data, none-privilleged, * single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable - PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 ); + PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 ); */ - + PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 ); PCI_bus_write( &UNIVERSE->LSI0_BS, 0x04000000 ); PCI_bus_write( &UNIVERSE->LSI0_BD, 0x05000000 ); @@ -257,44 +257,44 @@ void InitializeUniverse() #if 0 /* * Set the PCI Slave Image 0 Control register with posted write enable, - * 32 bit data width, A32 VMEbus address base, AM code to be data, - * none-privilleged, single and BLT cycles on VME bus with PCI + * 32 bit data width, A32 VMEbus address base, AM code to be data, + * none-privilleged, single and BLT cycles on VME bus with PCI * bus memory space. - PCI_bus_write( &UNIVERSE->LSI0_CTL, 0xC0820100 ); + PCI_bus_write( &UNIVERSE->LSI0_CTL, 0xC0820100 ); */ - PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 ); + PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 ); /* - * Set the PCI Slave Image 0 Base Address to be + * Set the PCI Slave Image 0 Base Address to be * 0x0 on LSI0_BS register. */ PCI_bus_write( &UNIVERSE->LSI0_BS, 0x00FF0000 ); /* - * Set the PCI Slave Image 0 Bound Address to be + * Set the PCI Slave Image 0 Bound Address to be * 0xFFFFF000 on VSI0_BD register. */ - PCI_bus_write( &UNIVERSE->LSI0_BD, 0x00FFF000 ); + PCI_bus_write( &UNIVERSE->LSI0_BD, 0x00FFF000 ); /* - * Set the PCI Slave Image 0 Translation Offset to be + * Set the PCI Slave Image 0 Translation Offset to be * 0x0 on VSI0_TO register. - * Note: If the actual VME address is bigger than 0x40000000, we need + * Note: If the actual VME address is bigger than 0x40000000, we need * to set the PCI Slave Image 0 Translation Offset = 0x40000000 - * register. - * i.e. if actual VME ADRR = 0x50000000, then we - * need to subtract it by 0x40000000 and set + * register. + * i.e. if actual VME ADRR = 0x50000000, then we + * need to subtract it by 0x40000000 and set * the LSI0_T0 register to be 0x40000000 and then * perform a PCI data access by adding 0xC0000000 to * 0x10000000 -- which is came form the result of - * (0x50000000 - 0x40000000). + * (0x50000000 - 0x40000000). */ - PCI_bus_write( &UNIVERSE->LSI0_TO, 0x0 ); + PCI_bus_write( &UNIVERSE->LSI0_TO, 0x0 ); #endif - /* + /* * Remove the Universe from VMEbus BI-Mode (bus-isolation). Once out of - * BI-Mode VMEbus accesses can be made. + * BI-Mode VMEbus accesses can be made. */ universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL ); @@ -309,22 +309,22 @@ void InitializeUniverse() * Slave Image 0 registers. */ void set_vme_base_address ( - uint32_t base_address + uint32_t base_address ) -{ +{ volatile uint32_t temp; /* * Calculate the current size of the Slave VME image 0 */ - temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) - + temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) - ( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000); /* - * Set the VMEbus Slave Image 0 Base Address to be + * Set the VMEbus Slave Image 0 Base Address to be * the specifed base address on VSI0_BS register. */ - PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) ); + PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) ); /* * Update the VMEbus Slave Image 0 Bound Address. @@ -342,7 +342,7 @@ void set_vme_base_address ( * Gets the VME base address */ uint32_t get_vme_base_address () -{ +{ volatile uint32_t temp; temp = PCI_bus_read( &UNIVERSE->VSI0_BS ); @@ -364,15 +364,15 @@ uint32_t get_vme_slave_size() * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF) */ void set_vme_slave_size (uint32_t size) -{ +{ volatile uint32_t temp; - if (size<0) + if (size<0) size = 0; - - if (size > 0x17FFFFF) + + if (size > 0x17FFFFF) size = 0x17FFFFF; - + /* * Read the VME slave image base address */ @@ -424,20 +424,20 @@ void put_vme( uint16_t *vme_ptr, uint16_t value ) -{ +{ if (vme_ptr > (uint16_t*)0x3EFFFFFF) { - /* + /* * LSI0_TO register to 0x3EFFF000 if it had not been updated already */ if (( PCI_bus_read( &UNIVERSE->LSI0_TO) & 0xFFFFF000) != 0x3EFFF000) PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 ); - - *(uint16_t*) (((uint32_t)vme_ptr - 0x3EFFF000) + + + *(uint16_t*) (((uint32_t)vme_ptr - 0x3EFFF000) + PPCN_60X_PCI_MEM_BASE) = value; } else - *(uint16_t*)((uint32_t)vme_ptr + + *(uint16_t*)((uint32_t)vme_ptr + PPCN_60X_PCI_MEM_BASE) = value; } #endif diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/vectors/vectors.S b/c/src/lib/libbsp/powerpc/ppcn_60x/vectors/vectors.S index cd7b737314..2f30978143 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/vectors/vectors.S +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/vectors/vectors.S @@ -17,7 +17,7 @@ */ /* vectors.s 1.1 - 95/12/04 * - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * interrupt veneers for RTEMS. * */ @@ -116,58 +116,58 @@ PUBLIC_VAR (__vectors) SYM (__vectors): - + #if PPCN_60X_USE_DINK - .org reset_vector - file_base + .org reset_vector - file_base /* This is where the DINK soft reset handler is located */ - ba 0xfff00180 - - .org mach_vector - file_base + ba 0xfff00180 + + .org mach_vector - file_base ba 0xfff00200 - - .org prot_vector - file_base + + .org prot_vector - file_base ba 0xfff00300 - - .org isi_vector - file_base + + .org isi_vector - file_base ba 0xfff00400 - - .org ext_vector - file_base + + .org ext_vector - file_base rfi - - .org align_vector - file_base - ba 0xfff00600 - - .org prog_vector - file_base - ba 0xfff00700 - - .org float_vector - file_base + + .org align_vector - file_base + ba 0xfff00600 + + .org prog_vector - file_base + ba 0xfff00700 + + .org float_vector - file_base ba 0xfff00800 - .org dec_vector - file_base + .org dec_vector - file_base rfi - - .org sys_vector - file_base - ba 0xfff00C00 - - .org trace_vector - file_base - ba 0xfff00d00 - - .org itm_vector - file_base - ba 0xfff01000 - - .org dltm_vector - file_base - ba 0xfff01100 - - .org dstm_vector - file_base - ba 0xfff01200 - - .org addr_vector - file_base - ba 0xfff01300 - - .org sysmgmt_vector - file_base - ba 0xfff01400 + + .org sys_vector - file_base + ba 0xfff00C00 + + .org trace_vector - file_base + ba 0xfff00d00 + + .org itm_vector - file_base + ba 0xfff01000 + + .org dltm_vector - file_base + ba 0xfff01100 + + .org dstm_vector - file_base + ba 0xfff01200 + + .org addr_vector - file_base + ba 0xfff01300 + + .org sysmgmt_vector - file_base + ba 0xfff01400 #else - .org reset_vector - file_base + .org reset_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) li r4,1 @@ -198,8 +198,8 @@ waitfortx: lwz r3,IP_3(r1) addi r1,r1,IP_END rfi - - .org mach_vector - file_base + + .org mach_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) stw r3,IP_3(r1) @@ -215,80 +215,80 @@ waitfortx: dcbst 0,r4 li r4,0x02 b display_exc - - .org prot_vector - file_base + + .org prot_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) li r4,0x03 b display_exc - - .org isi_vector - file_base + + .org isi_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) li r4,0x04 b display_exc - - .org ext_vector - file_base + + .org ext_vector - file_base rfi - - .org align_vector - file_base + + .org align_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) li r4,0x06 b display_exc - - .org prog_vector - file_base + + .org prog_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) li r4,0x07 b display_exc - .org float_vector - file_base + .org float_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) li r4,0x08 b display_exc - .org dec_vector - file_base + .org dec_vector - file_base rfi - - .org sys_vector - file_base + + .org sys_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) li r4,0x0a b display_exc - - .org trace_vector - file_base + + .org trace_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) li r4,0x0b b display_exc - - .org itm_vector - file_base + + .org itm_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) li r4,0x0c b display_exc - - .org dltm_vector - file_base + + .org dltm_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) li r4,0x0d b display_exc - - .org dstm_vector - file_base + + .org dstm_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) li r4,0x0e b display_exc - - .org addr_vector - file_base + + .org addr_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) li r4,0x0f b display_exc - - .org sysmgmt_vector - file_base + + .org sysmgmt_vector - file_base stwu r1, -(IP_END)(r1) stw r4,IP_4(r1) li r4,0x00 diff --git a/c/src/lib/libbsp/powerpc/psim/console/console-io.c b/c/src/lib/libbsp/powerpc/psim/console/console-io.c index 99339461f6..0aaffd07ea 100644 --- a/c/src/lib/libbsp/powerpc/psim/console/console-io.c +++ b/c/src/lib/libbsp/powerpc/psim/console/console-io.c @@ -48,7 +48,7 @@ void console_outbyte_polled( } /* - * console_inbyte_nonblocking + * console_inbyte_nonblocking * * This routine polls for a character. */ diff --git a/c/src/lib/libbsp/powerpc/psim/include/bsp.h b/c/src/lib/libbsp/powerpc/psim/include/bsp.h index d0652bfa9a..887317328e 100644 --- a/c/src/lib/libbsp/powerpc/psim/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/psim/include/bsp.h @@ -46,7 +46,7 @@ extern "C" { /* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */ #define CONFIGURE_INTERRUPT_STACK_MEMORY (12 * 1024) - + #ifdef ASM /* Definition of where to store registers in alignment handler */ #define ALIGN_REGS 0x0140 @@ -106,15 +106,15 @@ extern "C" { /* * Device Driver Table Entries */ - + /* * NOTE: Use the standard Console driver entry */ - + /* * NOTE: Use the standard Clock driver entry */ - + /* * Information placed in the linkcmds file. diff --git a/c/src/lib/libbsp/powerpc/psim/shmsupp/mpisr.c b/c/src/lib/libbsp/powerpc/psim/shmsupp/mpisr.c index 37448098d7..7bdd192648 100644 --- a/c/src/lib/libbsp/powerpc/psim/shmsupp/mpisr.c +++ b/c/src/lib/libbsp/powerpc/psim/shmsupp/mpisr.c @@ -1,4 +1,4 @@ -/* +/* * NOTE: This routine is not used when in polling mode. Either * this routine OR Shm_clockisr is used in a particular system. * diff --git a/c/src/lib/libbsp/powerpc/psim/startup/bspstart.c b/c/src/lib/libbsp/powerpc/psim/startup/bspstart.c index 6709f43403..87403907e4 100644 --- a/c/src/lib/libbsp/powerpc/psim/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/psim/startup/bspstart.c @@ -26,7 +26,7 @@ * The original table from the application and our copy of it with * some changes. */ - + extern rtems_configuration_table Configuration; rtems_configuration_table BSP_Configuration; @@ -44,7 +44,7 @@ extern uint32_t rdb_start; /* * Use the shared implementations of the following routines */ - + void bsp_postdriver_hook(void); void bsp_libc_init( void *, uint32_t, int ); @@ -87,7 +87,7 @@ void bsp_start( void ) unsigned char *work_space_start; #if 0 - /* + /* * Set MSR to show vectors at 0 XXX */ _CPU_MSR_Value( msr_value ); @@ -126,7 +126,7 @@ void bsp_start( void ) BSP_Configuration.work_space_size += 1024; - work_space_start = + work_space_start = (unsigned char *)&RAM_END - BSP_Configuration.work_space_size; if ( work_space_start <= (unsigned char *)&end ) { diff --git a/c/src/lib/libbsp/powerpc/psim/timer/timer.c b/c/src/lib/libbsp/powerpc/psim/timer/timer.c index 3052f0402c..a1412b2d0b 100644 --- a/c/src/lib/libbsp/powerpc/psim/timer/timer.c +++ b/c/src/lib/libbsp/powerpc/psim/timer/timer.c @@ -1,4 +1,4 @@ -/* +/* * This file implements a benchmark timer using the PPC decrement register. * * COPYRIGHT (c) 1989-2000. diff --git a/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S b/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S index 6ed7ddf15c..0d58bd38e4 100644 --- a/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S +++ b/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S @@ -1,6 +1,6 @@ /* vectors.s 1.1 - 95/12/04 * - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * interrupt vectors for RTEMS. * * COPYRIGHT (c) 1989-1999. @@ -55,29 +55,29 @@ .set IP_4, (IP_3 + 4) .set IP_5, (IP_4 + 4) .set IP_6, (IP_5 + 4) - + .set IP_7, (IP_6 + 4) .set IP_8, (IP_7 + 4) .set IP_9, (IP_8 + 4) .set IP_10, (IP_9 + 4) - + .set IP_11, (IP_10 + 4) .set IP_12, (IP_11 + 4) .set IP_13, (IP_12 + 4) .set IP_28, (IP_13 + 4) - + .set IP_29, (IP_28 + 4) .set IP_30, (IP_29 + 4) .set IP_31, (IP_30 + 4) .set IP_CR, (IP_31 + 4) - + .set IP_CTR, (IP_CR + 4) .set IP_XER, (IP_CTR + 4) .set IP_LR, (IP_XER + 4) .set IP_PC, (IP_LR + 4) - + .set IP_MSR, (IP_PC + 4) - + .set IP_END, (IP_MSR + 16) /* Vector offsets */ @@ -104,7 +104,7 @@ PUBLIC_VAR (__vectors) SYM (__vectors): - + /* Decrementer interrupt */ .org dec_vector - file_base #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c index 9a3f6b79d4..feb01efb96 100644 --- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c +++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c @@ -37,7 +37,7 @@ void PCI_bus_delay () void PCI_bus_write( volatile uint32_t * _addr, /* IN */ uint32_t _data /* IN */ -) +) { _data = Convert_Endian_32( _data ); *_addr = _data; @@ -48,7 +48,7 @@ uint32_t PCI_bus_read( ) { uint32_t data; - + data = *_addr; data = Convert_Endian_32( data ); return data; @@ -68,7 +68,7 @@ uint32_t Read_pci_device_register( * Write the PCI configuration address */ PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address ); - + /* * Delay needed when running out of DRAM */ @@ -78,20 +78,20 @@ uint32_t Read_pci_device_register( * read data */ data = PCI_bus_read( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_DATA ); - + return data; } void Write_pci_device_register( uint32_t address, - uint32_t data + uint32_t data ) { /* * Write the PCI configuration address */ PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address ); - + /* * Delay needed when running out of DRAM */ diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h index 16d2bbfc6f..78f0e71973 100644 --- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h +++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h @@ -10,7 +10,7 @@ * the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * $Id: + * $Id: */ #ifndef __PCI_h #define __PCI_h @@ -20,12 +20,12 @@ */ void PCI_bus_write( - volatile uint32_t * _addr, - uint32_t _data -); + volatile uint32_t * _addr, + uint32_t _data +); uint32_t PCI_bus_read( - volatile uint32_t * _addr + volatile uint32_t * _addr ); uint32_t Read_pci_device_register( @@ -34,7 +34,7 @@ uint32_t Read_pci_device_register( void Write_pci_device_register( uint32_t address, - uint32_t data + uint32_t data ); #endif diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c index 8b1cfa0958..c04c288c69 100644 --- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c +++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c @@ -22,7 +22,7 @@ unsigned int SCORE603e_FLASH_Disable( ) { uint8_t value; - + value = *SCORE603E_BOARD_CTRL_REG; value = value | (~SCORE603E_BRD_FLASH_DISABLE_MASK); *SCORE603E_BOARD_CTRL_REG = value; @@ -32,7 +32,7 @@ unsigned int SCORE603e_FLASH_Disable( unsigned int SCORE603e_FLASH_verify_enable() { - volatile uint8_t *Ctrl_Status_Register = + volatile uint8_t *Ctrl_Status_Register = (void *)SCORE603E_BOARD_CTRL_REG; uint8_t ctrl_value; uint32_t pci_value; diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c index eccf81476b..fda1760b0e 100644 --- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c +++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c @@ -97,9 +97,9 @@ typedef struct { uint32_t V6_STATID; /* 0x80030338 */ uint32_t V7_STATID; /* 0x8003033C */ uint32_t Buf_0x80030340[ 0x30 ]; /* 0x80030340 */ - uint32_t MAST_CTL; /* 0x80030400 */ - uint32_t MISC_CTL; /* 0x80030404 */ - uint32_t MISC_STAT; /* 0x80030408 */ + uint32_t MAST_CTL; /* 0x80030400 */ + uint32_t MISC_CTL; /* 0x80030404 */ + uint32_t MISC_STAT; /* 0x80030408 */ uint32_t USER_AM; /* 0x8003040C */ uint32_t Buf_0x80030410[ 0x2bc ];/* 0x80030410 */ uint32_t VSI0_CTL; /* 0x80030F00 */ @@ -135,7 +135,7 @@ typedef struct { uint32_t VCSR_BS; /* 0x80030FFC */ } Universe_Memory; -volatile Universe_Memory *UNIVERSE = +volatile Universe_Memory *UNIVERSE = (volatile Universe_Memory *)SCORE603E_UNIVERSE_BASE; @@ -160,21 +160,21 @@ void initialize_universe() #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE) volatile uint32_t universe_temp_value; #endif - + /* * Read the VME jumper location to determine the VME base address */ - jumper_selection = PCI_bus_read( + jumper_selection = PCI_bus_read( (volatile uint32_t*)SCORE603E_VME_JUMPER_ADDR ); jumper_selection = (jumper_selection >> 3) & 0x1f; /* - * Verify the UNIVERSE CHIP ID + * Verify the UNIVERSE CHIP ID */ pci_id = Read_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE ); - /* - * compare to known ID + /* + * compare to known ID */ if (pci_id != SCORE603E_UNIVERSE_CHIP_ID ){ DEBUG_puts ("Invalid SCORE603E_UNIVERSE_CHIP_ID: "); @@ -197,14 +197,14 @@ void initialize_universe() */ Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x4, 0x2800007 ); - /* + /* * Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register */ - PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 ); + PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 ); /* * Set the VMEbus Master Control register with retry forever, 256 bytes - * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes + * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes * aligned burst size and PCI bus number to be zero */ PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 ); @@ -213,17 +213,17 @@ void initialize_universe() * VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data * width, A32 VMEbus Address Space, AM code to be data, none-privilleged, * single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable - PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 ); + PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 ); */ - + PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 ); PCI_bus_write( &UNIVERSE->LSI0_BS, 0x04000000 ); PCI_bus_write( &UNIVERSE->LSI0_BD, 0x05000000 ); PCI_bus_write( &UNIVERSE->LSI0_TO, 0x7C000000 ); - /* + /* * Remove the Universe from VMEbus BI-Mode (bus-isolation). Once out of - * BI-Mode VMEbus accesses can be made. + * BI-Mode VMEbus accesses can be made. */ universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL ); @@ -232,7 +232,7 @@ void initialize_universe() PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value | ~0xFF0FFFFF)); #elif (SCORE603E_USE_DINK) - /* + /* * Do not modify the DINK setup of the universe chip. */ @@ -249,22 +249,22 @@ void initialize_universe() * Slave Image 0 registers. */ void set_vme_base_address ( - uint32_t base_address + uint32_t base_address ) -{ +{ volatile uint32_t temp; /* * Calculate the current size of the Slave VME image 0 */ - temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) - + temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) - ( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000); /* - * Set the VMEbus Slave Image 0 Base Address to be + * Set the VMEbus Slave Image 0 Base Address to be * the specifed base address on VSI0_BS register. */ - PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) ); + PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) ); /* * Update the VMEbus Slave Image 0 Bound Address. @@ -282,7 +282,7 @@ void set_vme_base_address ( * Gets the VME base address */ uint32_t get_vme_base_address () -{ +{ volatile uint32_t temp; temp = PCI_bus_read( &UNIVERSE->VSI0_BS ); @@ -304,15 +304,15 @@ uint32_t get_vme_slave_size() * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF) */ void set_vme_slave_size (uint32_t size) -{ +{ volatile uint32_t temp; - if (size<0) + if (size<0) size = 0; - - if (size > 0x17FFFFF) + + if (size > 0x17FFFFF) size = 0x17FFFFF; - + /* * Read the VME slave image base address */ diff --git a/c/src/lib/libbsp/powerpc/score603e/clock/clock.c b/c/src/lib/libbsp/powerpc/score603e/clock/clock.c index ce299f3ba1..7d768acea7 100644 --- a/c/src/lib/libbsp/powerpc/score603e/clock/clock.c +++ b/c/src/lib/libbsp/powerpc/score603e/clock/clock.c @@ -43,11 +43,11 @@ uint32_t Clock_Decrementer_value; rtems_isr_entry Old_ticker; void Clock_exit( void ); - + /* * These are set by clock driver during its init */ - + rtems_device_major_number rtems_clock_major = ~0; rtems_device_minor_number rtems_clock_minor; @@ -139,11 +139,11 @@ void Install_clock( void Clock_exit( void ) { - /* nothing to do */; + /* nothing to do */; /* do not restore old vector */ } - + /* * Clock_initialize * @@ -170,17 +170,17 @@ rtems_device_driver Clock_initialize( (BSP_Configuration.microseconds_per_tick / 1000); Install_clock( (rtems_isr_entry) Clock_isr ); - + /* * make major/minor avail to others such as shared memory driver */ - + rtems_clock_major = major; rtems_clock_minor = minor; - + return RTEMS_SUCCESSFUL; } - + /* * Clock_control * @@ -205,15 +205,15 @@ rtems_device_driver Clock_control( { uint32_t isrlevel; rtems_libio_ioctl_args_t *args = pargp; - + if (args == 0) goto done; - + /* * This is hokey, but until we get a defined interface * to do this, it will just be this simple... */ - + if (args->command == rtems_build_name('I', 'S', 'R', ' ')) { Clock_isr( CLOCK_VECTOR, pargp ); @@ -224,7 +224,7 @@ rtems_device_driver Clock_control( (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); rtems_interrupt_enable( isrlevel ); } - + done: return RTEMS_SUCCESSFUL; } diff --git a/c/src/lib/libbsp/powerpc/score603e/console/85c30.c b/c/src/lib/libbsp/powerpc/score603e/console/85c30.c index ed5592e6b1..0bad370f35 100644 --- a/c/src/lib/libbsp/powerpc/score603e/console/85c30.c +++ b/c/src/lib/libbsp/powerpc/score603e/console/85c30.c @@ -1,5 +1,5 @@ /* - * This file contains the console driver chip level routines for the + * This file contains the console driver chip level routines for the * z85c30 chip. * * Currently only polled mode is supported. @@ -11,7 +11,7 @@ * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * $Id: + * $Id: */ #include <rtems.h> @@ -42,19 +42,19 @@ typedef struct { } char_size_info; static const char_size_info Char_size_85c30[] = { - { Z8530_READ_CHARACTER_BITS_8, Z8530_WRITE_CHARACTER_BITS_8, 0xFF }, - { Z8530_READ_CHARACTER_BITS_7, Z8530_WRITE_CHARACTER_BITS_7, 0x7F }, - { Z8530_READ_CHARACTER_BITS_6, Z8530_WRITE_CHARACTER_BITS_6, 0x3F }, + { Z8530_READ_CHARACTER_BITS_8, Z8530_WRITE_CHARACTER_BITS_8, 0xFF }, + { Z8530_READ_CHARACTER_BITS_7, Z8530_WRITE_CHARACTER_BITS_7, 0x7F }, + { Z8530_READ_CHARACTER_BITS_6, Z8530_WRITE_CHARACTER_BITS_6, 0x3F }, { Z8530_READ_CHARACTER_BITS_5, Z8530_WRITE_CHARACTER_BITS_5, 0x1F } }; -static const unsigned char Clock_speed_85c30[] = { +static const unsigned char Clock_speed_85c30[] = { Z8530_x1_CLOCK, Z8530_x16_CLOCK, Z8530_x32_CLOCK, Z8530_x64_CLOCK }; -static const unsigned char Stop_bit_85c30[] = { +static const unsigned char Stop_bit_85c30[] = { Z8530_STOP_BITS_1, Z8530_STOP_BITS_1_AND_A_HALF, Z8530_STOP_BITS_2 }; -static const unsigned char Parity_85c30[] = { +static const unsigned char Parity_85c30[] = { Z8530_PARITY_NONE, Z8530_PARITY_ODD, Z8530_PARITY_EVEN }; @@ -64,19 +64,19 @@ static const unsigned char Parity_85c30[] = { * * Read a Z85c30 register */ -static unsigned char Read_85c30_register( +static unsigned char Read_85c30_register( volatile unsigned char *csr, /* IN */ unsigned char register_number /* IN */ ) { unsigned char Data; - - *csr = register_number; + + *csr = register_number; rtems_bsp_delay_in_bus_cycles( 40 ); Data = *csr; - + rtems_bsp_delay_in_bus_cycles( 40 ); return Data; @@ -118,7 +118,7 @@ void Reset_85c30_chip( Write_85c30_register( ctrl_0, 0x09, 0x80 ); Write_85c30_register( ctrl_1, 0x09, 0x40 ); } - + /* PAGE * @@ -138,7 +138,7 @@ void initialize_85c30_port( Setup = Port->Protocol; ctrl = Port->ctrl; - baud_constant = _Score603e_Z8530_Baud( Port->Chip->clock_frequency, + baud_constant = _Score603e_Z8530_Baud( Port->Chip->clock_frequency, Port->Chip->clock_x, Setup->baud_rate ); /* @@ -244,13 +244,13 @@ void initialize_85c30_port( value = 0x8a; value = value | Char_size_85c30[ Setup->write_char_bits ].write_setup; Write_85c30_register( ctrl, 0x05, value ); - + /* * Reset Tx UNDERRUN/EOM LATCH and ERROR - * via register 0 + * via register 0 */ Write_85c30_register( ctrl, 0x00, 0xf0 ); - + #if CONSOLE_USE_INTERRUPTS /* * Set Write Register 1 to interrupt on Rx characters or special condition. @@ -311,7 +311,7 @@ void outbyte_polled_85c30( { unsigned char z8530_status; uint32_t isrlevel; - + rtems_interrupt_disable( isrlevel ); /* @@ -324,7 +324,7 @@ void outbyte_polled_85c30( /* * Write the character. */ - Write_85c30_register( csr, DATA_REGISTER, (unsigned char) ch ); + Write_85c30_register( csr, DATA_REGISTER, (unsigned char) ch ); rtems_interrupt_enable( isrlevel ); } @@ -336,7 +336,7 @@ void outbyte_polled_85c30( * This routine polls for a character. */ -int inbyte_nonblocking_85c30( +int inbyte_nonblocking_85c30( const Port_85C30_info *Port ) { @@ -352,7 +352,7 @@ int inbyte_nonblocking_85c30( z8530_status = Read_85c30_register( csr, STATUS_REGISTER ); if ( !Z8530_Status_Is_RX_character_available( z8530_status ) ) return -1; - + /* * Return the character read. */ @@ -396,7 +396,7 @@ rtems_isr ISR_85c30_Async( if ( Z8530_Status_Is_RX_character_available( status ) ) { data = Read_85c30_register( Port->ctrl, DATA_REGISTER ); data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value; - + rtems_termios_enqueue_raw_characters( Port->Protocol->console_termios_data, &data, 1 ); did_something = TRUE; diff --git a/c/src/lib/libbsp/powerpc/score603e/console/85c30.h b/c/src/lib/libbsp/powerpc/score603e/console/85c30.h index 4a1e482a06..121d641994 100644 --- a/c/src/lib/libbsp/powerpc/score603e/console/85c30.h +++ b/c/src/lib/libbsp/powerpc/score603e/console/85c30.h @@ -1,6 +1,6 @@ /* 85c30.h * - * This include file contains z85c30 chip information. + * This include file contains z85c30 chip information. * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -9,7 +9,7 @@ * the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * $Id: + * $Id: */ #ifndef __85c30_H @@ -18,7 +18,7 @@ /* * Clock Speed Definations */ - + #define Z8530_x1_CLOCK 0x00 #define Z8530_x16_CLOCK 0x40 #define Z8530_x32_CLOCK 0x80 diff --git a/c/src/lib/libbsp/powerpc/score603e/console/console.c b/c/src/lib/libbsp/powerpc/score603e/console/console.c index 5391eeca47..78cf33c9e0 100644 --- a/c/src/lib/libbsp/powerpc/score603e/console/console.c +++ b/c/src/lib/libbsp/powerpc/score603e/console/console.c @@ -24,8 +24,8 @@ #if (1) /* - * The Port Used for the Console interface is based upon which - * debugger is being used. The SDS debugger uses a binary + * The Port Used for the Console interface is based upon which + * debugger is being used. The SDS debugger uses a binary * interface on port 0 as part of the debugger. Thus port 0 can * not be used as the console port for the SDS debugger. */ @@ -58,7 +58,7 @@ int USE_FOR_CONSOLE = USE_FOR_CONSOLE_DEF; * * Console Device Driver Entry Points */ - + /* PAGE * * DEBUG_puts @@ -89,7 +89,7 @@ void DEBUG_puts( /* should disable interrupts here */ - for ( s = string ; *s ; s++ ) + for ( s = string ; *s ; s++ ) outbyte_polled_85c30( csr, *s ); outbyte_polled_85c30( csr, '\r' ); @@ -100,28 +100,28 @@ void DEBUG_puts( /* PAGE * - * console_inbyte_nonblocking + * console_inbyte_nonblocking * * Console Termios polling input entry point. */ -int console_inbyte_nonblocking( - int minor +int console_inbyte_nonblocking( + int minor ) { int port = minor; - /* - * verify port Number + /* + * verify port Number */ assert ( port < NUM_Z85C30_PORTS ); - + /* * return a character from the 85c30 port. */ return inbyte_nonblocking_85c30( &Ports_85C30[ port ] ); } - + rtems_device_driver console_close( rtems_device_major_number major, rtems_device_minor_number minor, @@ -130,7 +130,7 @@ rtems_device_driver console_close( { return rtems_termios_close (arg); } - + rtems_device_driver console_read( rtems_device_major_number major, rtems_device_minor_number minor, @@ -139,7 +139,7 @@ rtems_device_driver console_read( { return rtems_termios_read (arg); } - + rtems_device_driver console_write( rtems_device_major_number major, rtems_device_minor_number minor, @@ -148,7 +148,7 @@ rtems_device_driver console_write( { return rtems_termios_write (arg); } - + rtems_device_driver console_control( rtems_device_major_number major, rtems_device_minor_number minor, @@ -171,7 +171,7 @@ rtems_isr console_isr( ) { int i; - + for (i=0; i < NUM_Z85C30_PORTS; i++){ ISR_85c30_Async( &Ports_85C30[i] ); @@ -180,7 +180,7 @@ rtems_isr console_isr( ISR_85c30_Async( &Ports_85C30[i] ); } #endif - } + } } void console_exit() @@ -190,12 +190,12 @@ void console_exit() uint32_t ch; for ( i=0 ; i < NUM_Z85C30_PORTS ; i++ ) { - + buffer = &( Ports_85C30[i].Protocol->TX_Buffer); while ( !Ring_buffer_Is_empty( buffer ) ) { Ring_buffer_Remove_character( buffer, ch ); - outbyte_polled_85c30( Ports_85C30[i].ctrl, ch ); + outbyte_polled_85c30( Ports_85C30[i].ctrl, ch ); } } } @@ -205,7 +205,7 @@ void console_initialize_interrupts( void ) volatile Ring_buffer_t *buffer; Console_Protocol *protocol; int i; - + for ( i=0 ; i < NUM_Z85C30_PORTS ; i++ ) { protocol = Ports_85C30[i].Protocol; @@ -217,15 +217,15 @@ void console_initialize_interrupts( void ) protocol->Is_TX_active = FALSE; } - /* + /* * Connect each vector to the interupt service routine. */ for (i=0; i < NUM_Z85C30_CHIPS; i++) set_vector( console_isr, Chips_85C30[i].vector, 1 ); - + atexit( console_exit ); - + } void console_outbyte_interrupts( const Port_85C30_info *Port, @@ -282,7 +282,7 @@ rtems_device_driver console_initialize( * Force to perform a hardware reset w/o * Master interrupt enable via register 9 */ - + for (port=0; port<NUM_Z85C30_PORTS; port++){ p0 = port; port++; @@ -290,7 +290,7 @@ rtems_device_driver console_initialize( Reset_85c30_chip( Ports_85C30[p0].ctrl, Ports_85C30[p1].ctrl ); } #else - /* TEMP - To see if this makes a diff with the new ports. + /* TEMP - To see if this makes a diff with the new ports. * Never reset chip 1 when using the chip as a monitor */ for (port=2; port<NUM_Z85C30_PORTS; port++){ @@ -301,7 +301,7 @@ rtems_device_driver console_initialize( } #endif - /* + /* * Initialize each port. * Note: the ports are numbered such that 0,1 are on the first chip * 2,3 are on the second .... @@ -327,16 +327,16 @@ rtems_device_driver console_initialize( * */ int console_write_support( - int minor, - const char *buf, + int minor, + const char *buf, int len) { int nwrite = 0; volatile uint8_t *csr; int port = minor; - /* - * verify port Number + /* + * verify port Number */ assert ( port < NUM_Z85C30_PORTS ); @@ -453,7 +453,7 @@ void console_outbyte_interrupts( uint32_t isrlevel; protocol = Port->Protocol; - + /* * If this is the first character then we need to prime the pump */ @@ -469,7 +469,7 @@ void console_outbyte_interrupts( } while ( Ring_buffer_Is_full( &protocol->TX_Buffer ) ); - + Ring_buffer_Add_character( &protocol->TX_Buffer, ch ); } diff --git a/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h b/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h index 65a7100676..7e20003b41 100644 --- a/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h +++ b/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h @@ -9,7 +9,7 @@ * the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * $Id: + * $Id: */ #ifndef __CONSOLEBSP_H @@ -25,12 +25,12 @@ extern "C" { /* * - * Note: The Ports are numbered 0..NUM_Z85C30_CHIPS with port 0 and 1 - * being on the first chip, and ports 2 and 3 being on the + * Note: The Ports are numbered 0..NUM_Z85C30_CHIPS with port 0 and 1 + * being on the first chip, and ports 2 and 3 being on the * second chip... */ - + /* * Z85c30 configuration informaiton. */ @@ -60,7 +60,7 @@ typedef enum { typedef enum { CONSOLE_PARITY_NONE, CONSOLE_PARITY_ODD, - CONSOLE_PARITY_EVEN, + CONSOLE_PARITY_EVEN, } CONSOLE_Parity; typedef enum { @@ -72,7 +72,7 @@ typedef enum { typedef struct { uint32_t baud_rate; /* baud rate value */ - CONSOLE_Stop_bits stop_bits; + CONSOLE_Stop_bits stop_bits; CONSOLE_Parity parity; CONSOLE_Character_bits read_char_bits; CONSOLE_Character_bits write_char_bits; @@ -83,7 +83,7 @@ typedef struct { void *console_termios_data; #endif -} Console_Protocol; +} Console_Protocol; /* @@ -112,7 +112,7 @@ typedef struct { } Port_85C30_info; /* - * Console port chip configuration tables. + * Console port chip configuration tables. */ extern Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ]; extern const Port_85C30_info Ports_85C30 [ NUM_Z85C30_PORTS ]; @@ -130,7 +130,7 @@ void outbyte_polled_85c30( char ch ); -int inbyte_nonblocking_85c30( +int inbyte_nonblocking_85c30( const Port_85C30_info *Port ); diff --git a/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c b/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c index a7b5e8dfea..2212260e0c 100644 --- a/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c +++ b/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c @@ -1,5 +1,5 @@ /* - * This file contains the table for the z85c30 port + * This file contains the table for the z85c30 port * used by the console driver. * * COPYRIGHT (c) 1989-1997. @@ -9,7 +9,7 @@ * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * $Id: + * $Id: */ #include "consolebsp.h" @@ -17,9 +17,9 @@ #define CONSOLE_DEFAULT_BAUD_RATE 9600 #define CONSOLE_DEFAULT_BAUD_CONSTANT Score603e_Z8530_Chip0_Baud(9600) - -#define CONSOLE_DEFAULT_STOP_BITS CONSOLE_STOP_BITS_1 -#define CONSOLE_DEFAULT_PARITY CONSOLE_PARITY_NONE + +#define CONSOLE_DEFAULT_STOP_BITS CONSOLE_STOP_BITS_1 +#define CONSOLE_DEFAULT_PARITY CONSOLE_PARITY_NONE #define CONSOLE_DEFAULT_READ_CHARACTER_BITS CONSOLE_CHARACTER_BITS_8 #define CONSOLE_DEFAULT_WRITE_CHARACTER_BITS CONSOLE_CHARACTER_BITS_8 #define CONSOLE_DEFAULT_CONSOLE_CLOCK CONSOLE_x16_CLOCK @@ -34,7 +34,7 @@ /* * Tables of information necessary to use the console 85c30 routines. */ -Console_Protocol Protocols_85c30 [ NUM_Z85C30_PORTS ] = +Console_Protocol Protocols_85c30 [ NUM_Z85C30_PORTS ] = { DEFAULT_PROTOCOL, DEFAULT_PROTOCOL, @@ -64,8 +64,8 @@ Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ] = SCORE603E_85C30_0_CLOCK, SCORE603E_85C30_0_CLOCK_X, CONSOLE_DEFAULT_CONSOLE_CLOCK - }, - { + }, + { SCORE603E_85C30_1_IRQ, SCORE603E_85C30_1_CLOCK, SCORE603E_85C30_1_CLOCK_X, @@ -73,25 +73,25 @@ Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ] = }, #if (HAS_PMC_PSC8) - { + { SCORE603E_85C30_2_IRQ, SCORE603E_85C30_2_CLOCK, SCORE603E_85C30_2_CLOCK_X, CONSOLE_DEFAULT_CONSOLE_CLOCK }, - { + { SCORE603E_85C30_3_IRQ, SCORE603E_85C30_3_CLOCK, SCORE603E_85C30_3_CLOCK_X, CONSOLE_DEFAULT_CONSOLE_CLOCK }, - { + { SCORE603E_85C30_4_IRQ, SCORE603E_85C30_4_CLOCK, SCORE603E_85C30_4_CLOCK_X, CONSOLE_DEFAULT_CONSOLE_CLOCK }, - { + { SCORE603E_85C30_5_IRQ, SCORE603E_85C30_5_CLOCK, SCORE603E_85C30_5_CLOCK_X, @@ -106,91 +106,91 @@ Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ] = * See consolebsp.h for the Port_85C30_info structure defination. */ const Port_85C30_info Ports_85C30 [ NUM_Z85C30_PORTS ] = { - { - (volatile unsigned char *) SCORE603E_85C30_CTRL_0, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_0, (volatile unsigned char *) SCORE603E_85C30_DATA_0, 0x00, &Protocols_85c30[0], - &Chips_85C30[0], + &Chips_85C30[0], }, - { - (volatile unsigned char *) SCORE603E_85C30_CTRL_1, - (volatile unsigned char *) SCORE603E_85C30_DATA_1, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_1, + (volatile unsigned char *) SCORE603E_85C30_DATA_1, 0x01, &Protocols_85c30[1], - &Chips_85C30[0], + &Chips_85C30[0], }, - { - (volatile unsigned char *) SCORE603E_85C30_CTRL_2, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_2, (volatile unsigned char *) SCORE603E_85C30_DATA_2, 0x02, &Protocols_85c30[2], - &Chips_85C30[1], + &Chips_85C30[1], }, - { - (volatile unsigned char *) SCORE603E_85C30_CTRL_3, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_3, (volatile unsigned char *) SCORE603E_85C30_DATA_3, 0x03, &Protocols_85c30[3], - &Chips_85C30[1], + &Chips_85C30[1], }, #if (HAS_PMC_PSC8) - { - (volatile unsigned char *) SCORE603E_85C30_CTRL_4, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_4, (volatile unsigned char *) SCORE603E_85C30_DATA_4, 0x04, &Protocols_85c30[4], - &Chips_85C30[2], + &Chips_85C30[2], }, - { - (volatile unsigned char *) SCORE603E_85C30_CTRL_5, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_5, (volatile unsigned char *) SCORE603E_85C30_DATA_5, 0x05, &Protocols_85c30[5], - &Chips_85C30[2], + &Chips_85C30[2], }, - { - (volatile unsigned char *) SCORE603E_85C30_CTRL_6, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_6, (volatile unsigned char *) SCORE603E_85C30_DATA_6, 0x06, &Protocols_85c30[6], - &Chips_85C30[3], + &Chips_85C30[3], }, - { - (volatile unsigned char *) SCORE603E_85C30_CTRL_7, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_7, (volatile unsigned char *) SCORE603E_85C30_DATA_7, 0x07, &Protocols_85c30[7], - &Chips_85C30[3], + &Chips_85C30[3], }, - { - (volatile unsigned char *) SCORE603E_85C30_CTRL_8, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_8, (volatile unsigned char *) SCORE603E_85C30_DATA_8, 0x08, &Protocols_85c30[8], - &Chips_85C30[4], + &Chips_85C30[4], }, - { - (volatile unsigned char *) SCORE603E_85C30_CTRL_9, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_9, (volatile unsigned char *) SCORE603E_85C30_DATA_9, 0x09, &Protocols_85c30[9], - &Chips_85C30[4], + &Chips_85C30[4], }, - { - (volatile unsigned char *) SCORE603E_85C30_CTRL_10, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_10, (volatile unsigned char *) SCORE603E_85C30_DATA_10, 0x0a, &Protocols_85c30[10], - &Chips_85C30[5], + &Chips_85C30[5], }, - { - (volatile unsigned char *) SCORE603E_85C30_CTRL_11, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_11, (volatile unsigned char *) SCORE603E_85C30_DATA_11, 0x0b, &Protocols_85c30[11], - &Chips_85C30[5], + &Chips_85C30[5], }, #endif }; diff --git a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h index 51930235db..12ba21e3c7 100644 --- a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h @@ -33,7 +33,7 @@ extern "C" { #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4) #endif #define CONFIGURE_INTERRUPT_STACK_MEMORY (12 * 1024) - + #ifdef ASM /* Definition of where to store registers in alignment handler */ #define ALIGN_REGS 0x0140 @@ -61,11 +61,11 @@ extern "C" { #define Score603e_Z8530_Chip1_Baud( _value ) \ _Score603e_Z8530_Baud( SCORE603E_85C30_1_CLOCK, \ - SCORE603E_85C30_1_CLOCK_X, _value ) + SCORE603E_85C30_1_CLOCK_X, _value ) #define Score603e_Z8530_Chip0_Baud( _value ) \ _Score603e_Z8530_Baud( SCORE603E_85C30_0_CLOCK, \ - SCORE603E_85C30_0_CLOCK_X, _value ) + SCORE603E_85C30_0_CLOCK_X, _value ) #define Initialize_Board_ctrl_register() \ *SCORE603E_BOARD_CTRL_REG = (*SCORE603E_BOARD_CTRL_REG | \ @@ -119,15 +119,15 @@ extern "C" { /* * Device Driver Table Entries */ - + /* * NOTE: Use the standard Console driver entry */ - + /* * NOTE: Use the standard Clock driver entry */ - + /* * Information placed in the linkcmds file. @@ -149,7 +149,7 @@ extern int end; /* last address in the program */ /* * How many libio files we want */ - + #define BSP_LIBIO_MAX_FDS 20 /* functions */ @@ -169,13 +169,13 @@ rtems_isr_entry set_vector( /* returns old vector */ */ rtems_isr bsp_stub_handler( rtems_vector_number trap -); +); rtems_isr bsp_spurious_handler( rtems_vector_number trap ); void bsp_spurious_initialize(); -/* +/* * genvec.c */ rtems_isr_entry set_EE_vector( @@ -217,7 +217,7 @@ void set_irq_mask( uint16_t get_irq_mask(); -void unmask_irq( +void unmask_irq( uint16_t irq_idx ); diff --git a/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h b/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h index 17d70815dc..90a1847ce4 100644 --- a/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h +++ b/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h @@ -82,8 +82,8 @@ extern "C" { #define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 #define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 #define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 #define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 #define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 #define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 @@ -109,8 +109,8 @@ extern "C" { #define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 #define CALLING_OVERHEAD_PORT_CREATE 0 #define CALLING_OVERHEAD_PORT_IDENT 0 -#define CALLING_OVERHEAD_PORT_DELETE 0 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 +#define CALLING_OVERHEAD_PORT_DELETE 0 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 #define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 #define CALLING_OVERHEAD_IO_INITIALIZE 0 diff --git a/c/src/lib/libbsp/powerpc/score603e/include/gen2.h b/c/src/lib/libbsp/powerpc/score603e/include/gen2.h index 2be08e07e4..64d9c10ba5 100644 --- a/c/src/lib/libbsp/powerpc/score603e/include/gen2.h +++ b/c/src/lib/libbsp/powerpc/score603e/include/gen2.h @@ -9,7 +9,7 @@ * the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * $Id: + * $Id: */ #ifndef __SCORE_GENERATION_2_h @@ -24,11 +24,11 @@ extern "C" { /* * ISA/PCI I/O space. */ -#define SCORE603E_VME_JUMPER_ADDR 0x00e20000 +#define SCORE603E_VME_JUMPER_ADDR 0x00e20000 #define SCORE603E_FLASH_BASE_ADDR 0x04000000 #define SCORE603E_ISA_PCI_IO_BASE 0x80000000 -#define SCORE603E_TIMER_PORT_C 0xfd000000 -#define SCORE603E_TIMER_INT_ACK 0xfd000000 +#define SCORE603E_TIMER_PORT_C 0xfd000000 +#define SCORE603E_TIMER_INT_ACK 0xfd000000 #define SCORE603E_TIMER_PORT_B 0xfd000008 #define SCORE603E_TIMER_PORT_A 0xfd000004 @@ -45,7 +45,7 @@ extern "C" { #define SCORE603E_85C30_DATA_3 ((volatile uint8_t*)0xfe20000c) /* - * PSC8 - PMC Card + * PSC8 - PMC Card */ #define SCORE603E_PCI_CONFIGURATION_BASE 0x80800000 #define SCORE603E_PMC_BASE SCORE603E_PCI_CONFIGURATION_BASE @@ -55,7 +55,7 @@ extern "C" { #define SCORE603E_PCI_DEVICE_ADDRESS( _offset) \ ((volatile uint32_t*)( SCORE603E_PCI_PMC_DEVICE_BASE + _offset )) - + #define SCORE603E_PMC_SERIAL_ADDRESS( _offset ) \ ((volatile uint8_t*)(SCORE603E_PCI_REGISTER_BASE + _offset)) @@ -63,29 +63,29 @@ extern "C" { /* * PMC serial channels - (4-7: 232 and 8-11: 422) */ -#define SCORE603E_85C30_CTRL_4 SCORE603E_PMC_SERIAL_ADDRESS(0x200020) -#define SCORE603E_85C30_DATA_4 SCORE603E_PMC_SERIAL_ADDRESS(0x200024) -#define SCORE603E_85C30_CTRL_5 SCORE603E_PMC_SERIAL_ADDRESS(0x200028) -#define SCORE603E_85C30_DATA_5 SCORE603E_PMC_SERIAL_ADDRESS(0x20002c) -#define SCORE603E_85C30_CTRL_6 SCORE603E_PMC_SERIAL_ADDRESS(0x200030) -#define SCORE603E_85C30_DATA_6 SCORE603E_PMC_SERIAL_ADDRESS(0x200034) -#define SCORE603E_85C30_CTRL_7 SCORE603E_PMC_SERIAL_ADDRESS(0x200038) -#define SCORE603E_85C30_DATA_7 SCORE603E_PMC_SERIAL_ADDRESS(0x20003c) -#define SCORE603E_85C30_CTRL_8 SCORE603E_PMC_SERIAL_ADDRESS(0x200000) -#define SCORE603E_85C30_DATA_8 SCORE603E_PMC_SERIAL_ADDRESS(0x200004) -#define SCORE603E_85C30_CTRL_9 SCORE603E_PMC_SERIAL_ADDRESS(0x200008) -#define SCORE603E_85C30_DATA_9 SCORE603E_PMC_SERIAL_ADDRESS(0x20000c) -#define SCORE603E_85C30_CTRL_10 SCORE603E_PMC_SERIAL_ADDRESS(0x200010) -#define SCORE603E_85C30_DATA_10 SCORE603E_PMC_SERIAL_ADDRESS(0x200014) -#define SCORE603E_85C30_CTRL_11 SCORE603E_PMC_SERIAL_ADDRESS(0x200018) -#define SCORE603E_85C30_DATA_11 SCORE603E_PMC_SERIAL_ADDRESS(0x20001c) +#define SCORE603E_85C30_CTRL_4 SCORE603E_PMC_SERIAL_ADDRESS(0x200020) +#define SCORE603E_85C30_DATA_4 SCORE603E_PMC_SERIAL_ADDRESS(0x200024) +#define SCORE603E_85C30_CTRL_5 SCORE603E_PMC_SERIAL_ADDRESS(0x200028) +#define SCORE603E_85C30_DATA_5 SCORE603E_PMC_SERIAL_ADDRESS(0x20002c) +#define SCORE603E_85C30_CTRL_6 SCORE603E_PMC_SERIAL_ADDRESS(0x200030) +#define SCORE603E_85C30_DATA_6 SCORE603E_PMC_SERIAL_ADDRESS(0x200034) +#define SCORE603E_85C30_CTRL_7 SCORE603E_PMC_SERIAL_ADDRESS(0x200038) +#define SCORE603E_85C30_DATA_7 SCORE603E_PMC_SERIAL_ADDRESS(0x20003c) +#define SCORE603E_85C30_CTRL_8 SCORE603E_PMC_SERIAL_ADDRESS(0x200000) +#define SCORE603E_85C30_DATA_8 SCORE603E_PMC_SERIAL_ADDRESS(0x200004) +#define SCORE603E_85C30_CTRL_9 SCORE603E_PMC_SERIAL_ADDRESS(0x200008) +#define SCORE603E_85C30_DATA_9 SCORE603E_PMC_SERIAL_ADDRESS(0x20000c) +#define SCORE603E_85C30_CTRL_10 SCORE603E_PMC_SERIAL_ADDRESS(0x200010) +#define SCORE603E_85C30_DATA_10 SCORE603E_PMC_SERIAL_ADDRESS(0x200014) +#define SCORE603E_85C30_CTRL_11 SCORE603E_PMC_SERIAL_ADDRESS(0x200018) +#define SCORE603E_85C30_DATA_11 SCORE603E_PMC_SERIAL_ADDRESS(0x20001c) #define SCORE603E_PCI_IO_CFG_ADDR 0x80000cf8 #define SCORE603E_PCI_IO_CFG_DATA 0x80000cfc #define SCORE603E_UNIVERSE_BASE 0x80030000 #define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000 -#define SCORE603E_PCI_MEM_BASE 0xc0000000 +#define SCORE603E_PCI_MEM_BASE 0xc0000000 #define SCORE603E_NVRAM_BASE 0xfd100000 #define SCORE603E_RTC_ADDRESS ((volatile unsigned char *)0xfd180000) #define SCORE603E_JP1_JP2_PROM_BASE 0xfff00000 @@ -106,7 +106,7 @@ extern "C" { /* * Definations for the ICM 1770 RTC chip - */ + */ /* * These values are programed into a register and must not be changed. */ @@ -115,25 +115,25 @@ extern "C" { #define ICM1770_CRYSTAL_FREQ_2M 0x02 #define ICM1770_CRYSTAL_FREQ_4M 0x03 -#define SCORE_RTC_FREQUENCY ICM1770_CRYSTAL_FREQ_32K +#define SCORE_RTC_FREQUENCY ICM1770_CRYSTAL_FREQ_32K /* * Z85C30 Definations for the 423 interface. */ #define SCORE603E_85C30_0_CLOCK 14745600 /* 10,000,000 ?10->14.5 */ -#define SCORE603E_85C30_0_CLOCK_X 16 +#define SCORE603E_85C30_0_CLOCK_X 16 /* * Z85C30 Definations for the 422 interface. */ #define SCORE603E_85C30_1_CLOCK 16000000 /* 10,000,000 ?10->14.5 */ -#define SCORE603E_85C30_1_CLOCK_X 16 +#define SCORE603E_85C30_1_CLOCK_X 16 /* * Z85C30 Definations for the PMC serial chips */ #define SCORE603E_85C30_PMC_CLOCK 16000000 /* 10,000,000 ?10->14.5 */ -#define SCORE603E_85C30_PMC_CLOCK_X 16 +#define SCORE603E_85C30_PMC_CLOCK_X 16 #define SCORE603E_85C30_2_CLOCK SCORE603E_85C30_PMC_CLOCK #define SCORE603E_85C30_3_CLOCK SCORE603E_85C30_PMC_CLOCK @@ -156,7 +156,7 @@ extern "C" { #define SCORE603E_FPGA_IRQ_INPUT ((volatile uint16_t*)0xfd00004c) /* - * The PMC status word is at the PMC base address + * The PMC status word is at the PMC base address */ #define SCORE603E_PMC_STATUS_ADDRESS (SCORE603E_PMC_SERIAL_ADDRESS (0)) #define Is_PMC_85C30_4_IRQ( _status ) (_status & 0x80) /* SCC 422-1 */ @@ -167,17 +167,17 @@ extern "C" { #define SCORE603E_PMC_CONTROL_ADDRESS SCORE603E_PMC_SERIAL_ADDRESS(0x100000) #define SCORE603E_PMC_SCC_232_LOOPBACK (_word) (_word|0x20) -#define PMC_SET_232_LOOPBACK(_word) (_word | 0x02) -#define PMC_CLEAR_232_LOOPBACK(_word) (_word & 0xfd) -#define PMC_SET_422_LOOPBACK(_word) (_word | 0x01) -#define PMC_CLEAR_422_LOOPBACK(_word) (_word & 0xfe) - +#define PMC_SET_232_LOOPBACK(_word) (_word | 0x02) +#define PMC_CLEAR_232_LOOPBACK(_word) (_word & 0xfd) +#define PMC_SET_422_LOOPBACK(_word) (_word | 0x01) +#define PMC_CLEAR_422_LOOPBACK(_word) (_word & 0xfe) + /* * Score603e Interupt Definations. */ -/* +/* * First Score Unique IRQ */ #define Score_IRQ_First ( PPC_IRQ_LAST + 1 ) @@ -202,25 +202,25 @@ extern "C" { #define SCORE603E_IRQ14 ( Score_IRQ_First + 14 ) #define SCORE603E_IRQ15 ( Score_IRQ_First + 15 ) -#define SCORE603E_TIMER1_IRQ SCORE603E_IRQ00 -#define SCORE603E_TIMER2_IRQ SCORE603E_IRQ01 -#define SCORE603E_TIMER3_IRQ SCORE603E_IRQ02 -#define SCORE603E_85C30_1_IRQ SCORE603E_IRQ03 -#define SCORE603E_85C30_0_IRQ SCORE603E_IRQ04 -#define SCORE603E_RTC_IRQ SCORE603E_IRQ05 -#define SCORE603E_PCI_IRQ_0 SCORE603E_IRQ06 -#define SCORE603E_PCI_IRQ_1 SCORE603E_IRQ07 -#define SCORE603E_PCI_IRQ_2 SCORE603E_IRQ08 -#define SCORE603E_PCI_IRQ_3 SCORE603E_IRQ09 -#define SCORE603E_UNIVERSE_IRQ SCORE603E_IRQ10 -#define SCORE603E_1553_IRQ SCORE603E_IRQ11 -#define SCORE603E_MAIL_BOX_IRQ_0 SCORE603E_IRQ12 -#define SCORE603E_MAIL_BOX_IRQ_1 SCORE603E_IRQ13 -#define SCORE603E_MAIL_BOX_IRQ_2 SCORE603E_IRQ14 -#define SCORE603E_MAIL_BOX_IRQ_3 SCORE603E_IRQ15 - -/* - * The Score FPGA maps all interrupts comming from the PMC card to +#define SCORE603E_TIMER1_IRQ SCORE603E_IRQ00 +#define SCORE603E_TIMER2_IRQ SCORE603E_IRQ01 +#define SCORE603E_TIMER3_IRQ SCORE603E_IRQ02 +#define SCORE603E_85C30_1_IRQ SCORE603E_IRQ03 +#define SCORE603E_85C30_0_IRQ SCORE603E_IRQ04 +#define SCORE603E_RTC_IRQ SCORE603E_IRQ05 +#define SCORE603E_PCI_IRQ_0 SCORE603E_IRQ06 +#define SCORE603E_PCI_IRQ_1 SCORE603E_IRQ07 +#define SCORE603E_PCI_IRQ_2 SCORE603E_IRQ08 +#define SCORE603E_PCI_IRQ_3 SCORE603E_IRQ09 +#define SCORE603E_UNIVERSE_IRQ SCORE603E_IRQ10 +#define SCORE603E_1553_IRQ SCORE603E_IRQ11 +#define SCORE603E_MAIL_BOX_IRQ_0 SCORE603E_IRQ12 +#define SCORE603E_MAIL_BOX_IRQ_1 SCORE603E_IRQ13 +#define SCORE603E_MAIL_BOX_IRQ_2 SCORE603E_IRQ14 +#define SCORE603E_MAIL_BOX_IRQ_3 SCORE603E_IRQ15 + +/* + * The Score FPGA maps all interrupts comming from the PMC card to * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be * read to indicate which interrupt was chained to the FPGA. */ @@ -239,7 +239,7 @@ extern "C" { #define MAX_BOARD_IRQS SCORE603E_IRQ19 - + /* * BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer * driver. @@ -250,7 +250,7 @@ extern "C" { #define BSP_TIMER_LEAST_VALID 1 /* Don't trust a value lower than this */ /* - * Convert decrement value to tenths of microsecnds (used by + * Convert decrement value to tenths of microsecnds (used by * shared timer driver). * * + CPU has a 66.67 Mhz bus, diff --git a/c/src/lib/libbsp/powerpc/score603e/start/start.S b/c/src/lib/libbsp/powerpc/score603e/start/start.S index 24b511282f..ae5fac1808 100644 --- a/c/src/lib/libbsp/powerpc/score603e/start/start.S +++ b/c/src/lib/libbsp/powerpc/score603e/start/start.S @@ -66,7 +66,7 @@ past_constants: mr r4,r5 ori r4,r4,0x0000 /* 0x2030 */ mtmsr r4 - + /* The first generation board needed initialization here but the */ /* second does not. */ diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c b/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c index 59d7168b42..e1b0091355 100644 --- a/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c +++ b/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c @@ -7,7 +7,7 @@ * the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * $Id: + * $Id: */ #include <bsp.h> @@ -63,7 +63,7 @@ uint16_t get_irq_mask() return value; } -void unmask_irq( +void unmask_irq( uint16_t irq_idx ) { @@ -85,7 +85,7 @@ void unmask_irq( } #endif - value &= (~(0x1 << mask_idx)); + value &= (~(0x1 << mask_idx)); set_irq_mask( value ); } @@ -111,7 +111,7 @@ void init_irq_data_register() uint16_t read_and_clear_PMC_irq( uint16_t irq -) +) { uint16_t status_word = irq; @@ -155,7 +155,7 @@ uint16_t read_and_clear_irq() irq = (*SCORE603E_FPGA_VECT_DATA); if ((irq & 0xffff0) != 0x10) { - DEBUG_puts( "ERROR:: no irq data\n"); + DEBUG_puts( "ERROR:: no irq data\n"); return (irq | 0x80); } diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c b/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c index e5d1fcce1b..3f016c3612 100644 --- a/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c +++ b/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c @@ -1,6 +1,6 @@ /* Hwr_init.c * - * $Id: + * $Id: */ #include <bsp.h> @@ -75,22 +75,22 @@ typedef struct { void init_RTC() { volatile Harris_RTC *the_RTC; - + the_RTC = (volatile Harris_RTC *)SCORE603E_RTC_ADDRESS; the_RTC->command_register = 0x0; } void init_PCI() -{ +{ #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE) uint32_t value; /* - * NOTE: Accessing any memory location not mapped by the BAT - * registers will cause a TLB miss exception. - * Set the DBAT1 to be configured for 256M of PCI MEM - * at 0xC0000000 with Write-through and Guarded Attributed and + * NOTE: Accessing any memory location not mapped by the BAT + * registers will cause a TLB miss exception. + * Set the DBAT1 to be configured for 256M of PCI MEM + * at 0xC0000000 with Write-through and Guarded Attributed and * read/write access allowed */ @@ -118,10 +118,10 @@ void init_PCI() #if (0) /* - * NOTE: Accessing any memory location not mapped by the BAT - * registers will cause a TLB miss exception. - * Set the DBAT3 to be configured for 256M of PCI MEM - * at 0xC0000000 with Write-through and Guarded Attributed and + * NOTE: Accessing any memory location not mapped by the BAT + * registers will cause a TLB miss exception. + * Set the DBAT3 to be configured for 256M of PCI MEM + * at 0xC0000000 with Write-through and Guarded Attributed and * read/write access allowed */ @@ -192,7 +192,7 @@ void data_cache_enable () uint32_t value; /* - * enable data cache + * enable data cache */ PPC_Get_HID0( value ); diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c b/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c index 11603b0c95..b3b2c22607 100644 --- a/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c @@ -12,7 +12,7 @@ * the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * $Id: + * $Id: */ #include <string.h> @@ -25,7 +25,7 @@ * The original table from the application and our copy of it with * some changes. */ - + extern rtems_configuration_table Configuration; rtems_configuration_table BSP_Configuration; rtems_cpu_table Cpu_table; @@ -71,7 +71,7 @@ void bsp_pretasking_hook(void) * bsp_predriver_hook * * Before drivers are setup initialize interupt vectors. - */ + */ void init_RTC(); void initialize_PMC(); @@ -88,13 +88,13 @@ void bsp_predriver_hook(void) initialize_PMC(); #endif - /* + /* * Initialize Bsp General purpose vector table. */ initialize_external_exception_vector(); #if (0) - /* + /* * XXX - Modify this to write a 48000000 (loop to self) command * to each interrupt location. This is better for debug. */ @@ -167,7 +167,7 @@ void initialize_PMC() { * * Standard post driver hook plus some BSP specific stuff. */ - + void SCORE603e_bsp_postdriver_hook(void) { extern void Init_EE_mask_init(void); @@ -205,27 +205,27 @@ void bsp_start( void ) ); /* - * There are multiple ROM monitors available for this board. + * There are multiple ROM monitors available for this board. */ #if (SCORE603E_USE_SDS) - /* + /* * Write instruction for Unconditional Branch to ROM vector. */ - - Code = 0x4bf00002; - for (Address = 0x100; Address <= 0xe00; Address += 0x100) { + + Code = 0x4bf00002; + for (Address = 0x100; Address <= 0xe00; Address += 0x100) { A_Vector = (uint32_t*)Address; Code = 0x4bf00002 + Address; *A_Vector = Code; } - - for (Address = 0x1000; Address <= 0x1400; Address += 0x100) { + + for (Address = 0x1000; Address <= 0x1400; Address += 0x100) { A_Vector = (uint32_t*)Address; Code = 0x4bf00002 + Address; *A_Vector = Code; } - + Cpu_table.exceptions_in_RAM = TRUE; msr_value = 0x2030; @@ -263,7 +263,7 @@ void bsp_start( void ) * not malloc'ed. It is just "pulled from the air". */ - work_space_start = + work_space_start = (unsigned char *)&RAM_END - BSP_Configuration.work_space_size; if ( work_space_start <= (unsigned char *)&end ) { @@ -287,7 +287,7 @@ void bsp_start( void ) Cpu_table.idle_task_stack_size = (3 * STACK_MINIMUM_SIZE); #if ( PPC_USE_DATA_CACHE ) - instruction_cache_enable (); + instruction_cache_enable (); data_cache_enable (); #endif } diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c b/c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c index a97444c865..b1e59ed579 100644 --- a/c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c +++ b/c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c @@ -20,8 +20,8 @@ #include <stdio.h> /* for sprintf */ -/* - * Proto types for this file +/* + * Proto types for this file */ rtems_isr external_exception_ISR ( @@ -31,8 +31,8 @@ rtems_isr external_exception_ISR ( #define NUM_LIRQ_HANDLERS 20 #define NUM_LIRQ ( MAX_BOARD_IRQS - PPC_IRQ_LAST ) -/* - * Structure to for one of possible multiple interrupt handlers for +/* + * Structure to for one of possible multiple interrupt handlers for * a given interrupt. */ typedef struct @@ -47,7 +47,7 @@ typedef struct * handlers at a later time. */ EE_ISR_Type ISR_Nodes [NUM_LIRQ_HANDLERS]; - uint16_t Nodes_Used; + uint16_t Nodes_Used; Chain_Control ISR_Array [NUM_LIRQ]; /* XXX */ @@ -67,14 +67,14 @@ void initialize_external_exception_vector () for (i=0; i <NUM_LIRQ; i++) Chain_Initialize_empty( &ISR_Array[i] ); - + init_irq_data_register(); - - /* - * Install external_exception_ISR () as the handler for + + /* + * Install external_exception_ISR () as the handler for * the General Purpose Interrupt. */ - status = rtems_interrupt_catch( external_exception_ISR, + status = rtems_interrupt_catch( external_exception_ISR, PPC_IRQ_EXTERNAL, (rtems_isr_entry *) &previous_isr ); } @@ -83,7 +83,7 @@ void Init_EE_mask_init() { } /* - * This routine installs one of multiple ISRs for the general purpose + * This routine installs one of multiple ISRs for the general purpose * inerrupt. */ rtems_isr_entry set_EE_vector( @@ -93,9 +93,9 @@ rtems_isr_entry set_EE_vector( { uint16_t vec_idx = vector - Score_IRQ_First; uint32_t index; - + assert (Nodes_Used < NUM_LIRQ_HANDLERS); - + /* * If we have already installed this handler for this vector, then * just reset it. @@ -110,15 +110,15 @@ rtems_isr_entry set_EE_vector( /* * Doing things in this order makes them more atomic */ - - Nodes_Used++; + + Nodes_Used++; index = Nodes_Used - 1; ISR_Nodes[index].handler = handler; ISR_Nodes[index].vector = vector; - /* printf( "Vector Index: %04x, Vector: %d (%x)\n", + /* printf( "Vector Index: %04x, Vector: %d (%x)\n", vec_idx, vector, vector); */ Chain_Append( &ISR_Array[vec_idx], &ISR_Nodes[index].Node ); @@ -131,13 +131,13 @@ rtems_isr_entry set_EE_vector( return NULL; } -/* +/* * This interrupt service routine is called for an External Exception. */ rtems_isr external_exception_ISR ( rtems_vector_number vector /* IN */ ) -{ +{ uint16_t index; EE_ISR_Type *node; uint16_t value; @@ -167,7 +167,7 @@ rtems_isr external_exception_ISR ( node = (EE_ISR_Type *)(ISR_Array[ index ].first); if ( _Chain_Is_tail( &ISR_Array[ index ], (void *)node ) ) { - sprintf(err_msg,"ERROR:: check %d interrupt %02d has no isr\n", + sprintf(err_msg,"ERROR:: check %d interrupt %02d has no isr\n", check_irq, index); DEBUG_puts( err_msg); value = get_irq_mask(); @@ -183,7 +183,7 @@ rtems_isr external_exception_ISR ( } else #endif - { + { node = (EE_ISR_Type *)(ISR_Array[ index ].first); if ( _Chain_Is_tail( &ISR_Array[ index ], (void *)node ) ) { sprintf(err_msg,"ERROR:: interrupt %02x has no isr\n", index); diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/setvec.c b/c/src/lib/libbsp/powerpc/score603e/startup/setvec.c index 24bb18922e..b10521f05e 100644 --- a/c/src/lib/libbsp/powerpc/score603e/startup/setvec.c +++ b/c/src/lib/libbsp/powerpc/score603e/startup/setvec.c @@ -36,7 +36,7 @@ * the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * $Id: + * $Id: */ #include <rtems.h> @@ -44,8 +44,8 @@ /* - * This routine installs vector number vector. - * + * This routine installs vector number vector. + * */ rtems_isr_entry set_vector( /* returns old vector */ rtems_isr_entry handler, /* isr routine */ @@ -57,7 +57,7 @@ rtems_isr_entry set_vector( /* returns old vector */ rtems_status_code status; - /* + /* * vectors greater than PPC603e_IRQ_LAST are handled by the General purpose * interupt handler. */ diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/spurious.c b/c/src/lib/libbsp/powerpc/score603e/startup/spurious.c index a3b87f600b..59d5ba2949 100644 --- a/c/src/lib/libbsp/powerpc/score603e/startup/spurious.c +++ b/c/src/lib/libbsp/powerpc/score603e/startup/spurious.c @@ -1,11 +1,11 @@ /* * Score603e Spurious Trap Handler * - * This is just enough of a trap handler to let us know what + * This is just enough of a trap handler to let us know what * the likely source of the trap was. * - * Developed as part of the port of RTEMS to the ERC32 implementation - * of the SPARC by On-Line Applications Research Corporation (OAR) + * Developed as part of the port of RTEMS to the ERC32 implementation + * of the SPARC by On-Line Applications Research Corporation (OAR) * under contract to the European Space Agency (ESA). * * COPYRIGHT (c) 1995. European Space Agency. @@ -82,9 +82,9 @@ rtems_isr bsp_spurious_handler( break; #if defined(ppc403) -#error "Please fill in names. " +#error "Please fill in names. " case PPC_IRQ_CRIT : - DEBUG_puts( "\nTrap: Critical Error "); + DEBUG_puts( "\nTrap: Critical Error "); break; case PPC_IRQ_PIT: DEBUG_puts( "\nTrap: 0x01000" ); @@ -100,13 +100,13 @@ rtems_isr bsp_spurious_handler( break; #elif defined(ppc601) -#error "Please fill in names. " +#error "Please fill in names. " case PPC_IRQ_TRACE : DEBUG_puts( "\nTrap: 0x02000" ); break; #elif defined(ppc603) -#error "Please fill in names. " +#error "Please fill in names. " case PPC_IRQ_TRANS_MISS : DEBUG_puts( "\nTrap: 0x1000" ); break; @@ -141,7 +141,7 @@ rtems_isr bsp_spurious_handler( break; #elif defined(mpc604) -#error "Please fill in names. " +#error "Please fill in names. " case PPC_IRQ_ADDR_BRK: DEBUG_puts( "0x1300" ); break; @@ -179,7 +179,7 @@ void bsp_spurious_initialize() ; /* set_vector( bsp_stub_handler, trap, 1 ); */ else - set_vector( bsp_spurious_handler, trap, 1 ); + set_vector( bsp_spurious_handler, trap, 1 ); } } diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c b/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c index 441c98a224..8e2f334881 100644 --- a/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c +++ b/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c @@ -9,7 +9,7 @@ * the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * $Id: + * $Id: */ #include <rtems.h> diff --git a/c/src/lib/libbsp/powerpc/score603e/timer/timer.c b/c/src/lib/libbsp/powerpc/score603e/timer/timer.c index 6e7548d909..81a6b18de7 100644 --- a/c/src/lib/libbsp/powerpc/score603e/timer/timer.c +++ b/c/src/lib/libbsp/powerpc/score603e/timer/timer.c @@ -26,7 +26,7 @@ uint64_t Timer_driver_Start_time; rtems_boolean Timer_driver_Find_average_overhead; /* - * Timer_initialize + * Timer_initialize */ void Timer_initialize() diff --git a/c/src/lib/libbsp/powerpc/score603e/tod/tod.c b/c/src/lib/libbsp/powerpc/score603e/tod/tod.c index 234d46243b..a21140105d 100644 --- a/c/src/lib/libbsp/powerpc/score603e/tod/tod.c +++ b/c/src/lib/libbsp/powerpc/score603e/tod/tod.c @@ -1,14 +1,14 @@ /* - * Real Time Clock (Harris ICM7170) for RTEMS + * Real Time Clock (Harris ICM7170) for RTEMS * - * This part is found on the second generation of this board. + * This part is found on the second generation of this board. * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * * $Id$ - */ + */ #include <rtems.h> #include <tod.h> @@ -74,7 +74,7 @@ int checkRealTime() } /* - * These routines are ICM7170 should be in + * These routines are ICM7170 should be in * a separate support library. * XXX Make static */ @@ -113,13 +113,13 @@ void ICM7170_GetTOD( if (init ) { ICM7170_SetField( imc1770_regs, 0x11, (0x0c | icm1770_freq) ); init = FALSE; - } + } /* Latch times */ /* rtc_tod->ticks = */ - + usec = ICM7170_GetField( imc1770_regs, 0x00 ); - + year = ICM7170_GetField( imc1770_regs, 0x06 ); if ( year >= 88 ) year += 1900; @@ -151,7 +151,7 @@ void ICM7170_SetTOD( year -= 2000; else year -= 1900; - + ICM7170_SetField( imc1770_regs, 0x11, (0x04 |icm1770_freq ) ); ICM7170_SetField( imc1770_regs, 0x06, year ); @@ -162,8 +162,8 @@ void ICM7170_SetTOD( ICM7170_SetField( imc1770_regs, 0x03, rtc_tod->second ); /* - * I don't know which day of week is - * + * I don't know which day of week is + * */ ICM7170_SetField( imc1770_regs, 0x07, 1 ); diff --git a/c/src/lib/libbsp/powerpc/score603e/vectors/vectors.S b/c/src/lib/libbsp/powerpc/score603e/vectors/vectors.S index 14ed3c50fe..fc6a0f1e37 100644 --- a/c/src/lib/libbsp/powerpc/score603e/vectors/vectors.S +++ b/c/src/lib/libbsp/powerpc/score603e/vectors/vectors.S @@ -1,6 +1,6 @@ /* vectors.s 1.1 - 95/12/04 * - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * interrupt veneers for RTEMS. * */ @@ -64,101 +64,101 @@ PUBLIC_VAR (__vectors) SYM (__vectors): - + /* Decrementer interrupt */ - .org reset_vector - file_base - ba 0x00100 - ba 0xfff00100 - ba 0xfff00100 + .org reset_vector - file_base + ba 0x00100 + ba 0xfff00100 + ba 0xfff00100 ba 0xfff00100 - - .org mach_vector - file_base + + .org mach_vector - file_base ba 0x00200 ba 0xfff00200 ba 0xfff00200 ba 0xfff00200 - - .org prot_vector - file_base + + .org prot_vector - file_base ba 0x00300 ba 0xfff00300 ba 0xfff00300 ba 0xfff00300 - - .org isi_vector - file_base + + .org isi_vector - file_base ba 0x00400 ba 0xfff00400 ba 0xfff00400 ba 0xfff00400 - - .org ext_vector - file_base - ba 0x0500 - ba 0xfff00500 - ba 0xfff00500 - ba 0xfff00500 - - .org align_vector - file_base - ba 0x00600 - ba 0xfff00600 - ba 0xfff00600 - ba 0xfff00600 - - .org prog_vector - file_base - ba 0x00700 - ba 0xfff00700 - ba 0xfff00700 - ba 0xfff00700 - - .org float_vector - file_base + + .org ext_vector - file_base + ba 0x0500 + ba 0xfff00500 + ba 0xfff00500 + ba 0xfff00500 + + .org align_vector - file_base + ba 0x00600 + ba 0xfff00600 + ba 0xfff00600 + ba 0xfff00600 + + .org prog_vector - file_base + ba 0x00700 + ba 0xfff00700 + ba 0xfff00700 + ba 0xfff00700 + + .org float_vector - file_base ba 0x00800 ba 0xfff00800 ba 0xfff00800 ba 0xfff00800 - .org dec_vector - file_base + .org dec_vector - file_base rfi ba 0xfff00900 ba 0xfff00900 ba 0xfff00900 - - .org sys_vector - file_base - ba 0x0c00 - ba 0xfff00C00 - ba 0xfff00C00 - ba 0xfff00C00 - - .org trace_vector - file_base - ba 0x0d00 - ba 0xfff00d00 - ba 0xfff00d00 - ba 0xfff00d00 - - .org itm_vector - file_base - ba 0x01000 - ba 0xfff01000 - ba 0xfff01000 - ba 0xfff01000 - - .org dltm_vector - file_base - ba 0x01100 - ba 0xfff01100 - ba 0xfff01100 - ba 0xfff01100 - - .org dstm_vector - file_base - ba 0x1200 - ba 0xfff01200 - ba 0xfff01200 - ba 0xfff01200 - - .org addr_vector - file_base - ba 0x1300 - ba 0xfff01300 - ba 0xfff01300 - ba 0xfff01300 - - .org sysmgmt_vector - file_base - ba 0x1400 - ba 0xfff01400 - ba 0xfff01400 - ba 0xfff01400 + + .org sys_vector - file_base + ba 0x0c00 + ba 0xfff00C00 + ba 0xfff00C00 + ba 0xfff00C00 + + .org trace_vector - file_base + ba 0x0d00 + ba 0xfff00d00 + ba 0xfff00d00 + ba 0xfff00d00 + + .org itm_vector - file_base + ba 0x01000 + ba 0xfff01000 + ba 0xfff01000 + ba 0xfff01000 + + .org dltm_vector - file_base + ba 0x01100 + ba 0xfff01100 + ba 0xfff01100 + ba 0xfff01100 + + .org dstm_vector - file_base + ba 0x1200 + ba 0xfff01200 + ba 0xfff01200 + ba 0xfff01200 + + .org addr_vector - file_base + ba 0x1300 + ba 0xfff01300 + ba 0xfff01300 + ba 0xfff01300 + + .org sysmgmt_vector - file_base + ba 0x1400 + ba 0xfff01400 + ba 0xfff01400 + ba 0xfff01400 #endif diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/bootldr.h b/c/src/lib/libbsp/powerpc/shared/bootloader/bootldr.h index 4cb72fc3c1..594737efea 100644 --- a/c/src/lib/libbsp/powerpc/shared/bootloader/bootldr.h +++ b/c/src/lib/libbsp/powerpc/shared/bootloader/bootldr.h @@ -51,16 +51,16 @@ typedef struct _ctxt { /* The main structure which is pointed to permanently by r13. Things * are not separated very well between parts because it would cause * too much code bloat for such a simple program like the bootloader. - * The code is designed to be compiled with the -m relocatable option and - * tries to minimize the number of relocations/fixups and the number of - * functions who have to access the .got2 sections (this increases the + * The code is designed to be compiled with the -m relocatable option and + * tries to minimize the number of relocations/fixups and the number of + * functions who have to access the .got2 sections (this increases the * size of the prologue in every function). */ typedef struct _boot_data { RESIDUAL *residual; void *load_address; void *of_entry; - void *r6, *r7, *r8, *r9, *r10; + void *r6, *r7, *r8, *r9, *r10; u_long cache_lsize; void *image; /* Where to copy ourselves */ void *stack; @@ -77,80 +77,80 @@ typedef struct _boot_data { register boot_data *bd __asm__("r13"); extern inline int -pcibios_read_config_byte(u_char bus, u_char dev_fn, +pcibios_read_config_byte(u_char bus, u_char dev_fn, u_char where, u_char * val) { return bd->pci_functions->read_config_byte(bus, dev_fn, where, val); } extern inline int -pcibios_read_config_word(u_char bus, u_char dev_fn, +pcibios_read_config_word(u_char bus, u_char dev_fn, u_char where, u_short * val) { return bd->pci_functions->read_config_word(bus, dev_fn, where, val); } extern inline int -pcibios_read_config_dword(u_char bus, u_char dev_fn, +pcibios_read_config_dword(u_char bus, u_char dev_fn, u_char where, u_int * val) { return bd->pci_functions->read_config_dword(bus, dev_fn, where, val); } extern inline int -pcibios_write_config_byte(u_char bus, u_char dev_fn, +pcibios_write_config_byte(u_char bus, u_char dev_fn, u_char where, u_char val) { return bd->pci_functions->write_config_byte(bus, dev_fn, where, val); } extern inline int -pcibios_write_config_word(u_char bus, u_char dev_fn, +pcibios_write_config_word(u_char bus, u_char dev_fn, u_char where, u_short val) { return bd->pci_functions->write_config_word(bus, dev_fn, where, val); } extern inline int -pcibios_write_config_dword(u_char bus, u_char dev_fn, +pcibios_write_config_dword(u_char bus, u_char dev_fn, u_char where, u_int val) { return bd->pci_functions->write_config_dword(bus, dev_fn, where, val); } extern inline int pci_read_config_byte(struct pci_dev *dev, u_char where, u_char * val) { - return bd->pci_functions->read_config_byte(dev->bus->number, - dev->devfn, + return bd->pci_functions->read_config_byte(dev->bus->number, + dev->devfn, where, val); } extern inline int pci_read_config_word(struct pci_dev *dev, u_char where, u_short * val) { - return bd->pci_functions->read_config_word(dev->bus->number, - dev->devfn, + return bd->pci_functions->read_config_word(dev->bus->number, + dev->devfn, where, val); } extern inline int pci_read_config_dword(struct pci_dev *dev, u_char where, u_int * val) { - return bd->pci_functions->read_config_dword(dev->bus->number, - dev->devfn, + return bd->pci_functions->read_config_dword(dev->bus->number, + dev->devfn, where, val); } extern inline int pci_write_config_byte(struct pci_dev *dev, u_char where, u_char val) { - return bd->pci_functions->write_config_byte(dev->bus->number, - dev->devfn, + return bd->pci_functions->write_config_byte(dev->bus->number, + dev->devfn, where, val); } extern inline int pci_write_config_word(struct pci_dev *dev, u_char where, u_short val) { - return bd->pci_functions->write_config_word(dev->bus->number, - dev->devfn, + return bd->pci_functions->write_config_word(dev->bus->number, + dev->devfn, where, val); } extern inline int pci_write_config_dword(struct pci_dev *dev, u_char where, u_int val) { - return bd->pci_functions->write_config_dword(dev->bus->number, - dev->devfn, + return bd->pci_functions->write_config_dword(dev->bus->number, + dev->devfn, where, val); } @@ -159,12 +159,12 @@ pci_write_config_dword(struct pci_dev *dev, u_char where, u_int val) { * zero, it performs more or less like memmove. No copy is performed if * source and destination addresses are equal. However the caches * are synchronized. Note that the size is always rounded up to the - * next mutiple of 4. + * next mutiple of 4. */ extern void * codemove(void *, const void *, size_t, unsigned long); /* The physical memory allocator allows to align memory by - * powers of 2 given by the lower order bits of flags. + * powers of 2 given by the lower order bits of flags. * By default it allocates from higher addresses towrds lower ones, * setting PA_LOW reverses this behaviour. */ @@ -212,11 +212,11 @@ int find_max_mem(struct pci_dev *); #ifdef ASM /* These definitions simplify the ugly declarations necessary for - * GOT definitions. + * GOT definitions. */ #define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME -#define GOT(NAME) .L_ ## NAME (r30) +#define GOT(NAME) .L_ ## NAME (r30) #define START_GOT \ .section ".got2","aw"; \ diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/em86.c b/c/src/lib/libbsp/powerpc/shared/bootloader/em86.c index be444b2279..1ca667a82f 100644 --- a/c/src/lib/libbsp/powerpc/shared/bootloader/em86.c +++ b/c/src/lib/libbsp/powerpc/shared/bootloader/em86.c @@ -16,7 +16,7 @@ */ /***************************************************************************** -* +* * Code to interpret Video BIOS ROM routines. * * @@ -33,7 +33,7 @@ #endif -/* Code options, put them on the compiler command line */ +/* Code options, put them on the compiler command line */ /* #define EIP_STATS */ /* EIP based profiling */ /* #undef EIP_STATS */ @@ -61,10 +61,10 @@ typedef struct _x86 { *esbase, *csbase, *ssbase, *dsbase, *fsbase, *gsbase; volatile unsigned char *iobase; unsigned char *ioperm; - unsigned + unsigned reason, nexteip, parm1, parm2, opcode, base; unsigned *optable, opreg; /* no more used! */ - unsigned char* vbase; + unsigned char* vbase; unsigned instructions; #ifdef __BOOT__ u_char * ram; @@ -80,7 +80,7 @@ x86 v86_private __attribute__((aligned(32))); /* Emulator is in another source file */ -extern +extern void em86_enter(x86 * p); #define EAX (p->_eax.e) @@ -116,19 +116,19 @@ void em86_enter(x86 * p); static void dump86(x86 * p){ unsigned char *s = p->csbase + p->eip; printf("cs:eip=%04x:%08x, eax=%08x, ecx=%08x, edx=%08x, ebx=%08x\n", - p->cs, p->eip, ld_le32(&EAX), + p->cs, p->eip, ld_le32(&EAX), ld_le32(&ECX), ld_le32(&EDX), ld_le32(&EBX)); printf("ss:esp=%04x:%08x, ebp=%08x, esi=%08x, edi=%08x, efl=%08x\n", - p->ss, ld_le32(&ESP), ld_le32(&EBP), + p->ss, ld_le32(&ESP), ld_le32(&EBP), ld_le32(&ESI), ld_le32(&EDI), p->eflags); printf("nip=%08x, ds=%04x, es=%04x, fs=%04x, gs=%04x, total=%d\n", p->nexteip, p->ds, p->es, p->fs, p->gs, p->instructions); - printf("code: %02x %02x %02x %02x %02x %02x " + printf("code: %02x %02x %02x %02x %02x %02x " "%02x %02x %02x %02x %02x %02x\n", - s[0], s[1], s[2], s[3], s[4], s[5], + s[0], s[1], s[2], s[3], s[4], s[5], s[6], s[7], s[8], s[9], s[10], s[11]); #ifndef __BOOT__ - printf("op1=%08x, op2=%08x, result=%08x, flags=%08x\n", + printf("op1=%08x, op2=%08x, result=%08x, flags=%08x\n", p->filler[11], p->filler[12], p->filler[13], p->filler[14]); #endif } @@ -139,10 +139,10 @@ static void dump86(x86 * p){ int bios86pci(x86 * p) { unsigned reg=ld_le16(&DI); reg_type2 tmp; - + if (AL>=8 && AL<=13 && reg>0xff) { AH = PCIBIOS_BAD_REGISTER_NUMBER; - } else { + } else { switch(AL) { case 2: /* find_device */ /* Should be improved for BIOS able to handle @@ -222,13 +222,13 @@ int int10h(x86 * p) { /* Process BIOS video interrupt */ #else p->eflags = (p->eflags&0xfcff)|0x100; /* Set TF for debugging */ #endif - /* p->eflags|=0x100; uncomment to force a trap */ + /* p->eflags|=0x100; uncomment to force a trap */ return(0); } else { switch(AH) { case 0x12: switch(BL){ - case 0x32: + case 0x32: p->eip=p->nexteip; return(0); break; @@ -238,7 +238,7 @@ int int10h(x86 * p) { /* Process BIOS video interrupt */ default: break; } - printf("unhandled soft interrupt 0x10: vector=%x\n", vector); + printf("unhandled soft interrupt 0x10: vector=%x\n", vector); return(1); } } @@ -261,11 +261,11 @@ int process_softint(x86 * p) { } dump86(p); printf("Unhandled soft interrupt number 0x%04x, AX=0x%04x\n", - p->parm1, ld_le16(&AX)); + p->parm1, ld_le16(&AX)); return(1); } -/* The only function called back by the emulator is em86_trap, all +/* The only function called back by the emulator is em86_trap, all instructions may that change the code segment are trapped here. p->reason is one of the following codes. */ #define code_zerdiv 0 @@ -275,7 +275,7 @@ int process_softint(x86 * p) { #define code_bound 5 #define code_ud 6 #define code_dna 7 - + #define code_iretw 256 #define code_iretl 257 #define code_lcallw 258 @@ -290,8 +290,8 @@ int process_softint(x86 * p) { - The three LSB define the port size (1, 2 or 4) - bit of weight 512 means out if set, in if clear - bit of weight 256 means ins/outs if set, in/out if clear - - bit of weight 128 means use esi/edi if set, si/di if clear - (only used for ins/outs instructions, always clear for in/out) + - bit of weight 128 means use esi/edi if set, si/di if clear + (only used for ins/outs instructions, always clear for in/out) */ #define code_inb 1024+1 #define code_inw 1024+2 @@ -327,7 +327,7 @@ int em86_trap(x86 *p) { switch(p->reason) { case code_int3: #ifndef __BOOT__ - if(p->csbase+p->eip == bptaddr) { + if(p->csbase+p->eip == bptaddr) { *bptaddr=bptopc; bptaddr=NULL; } @@ -352,8 +352,8 @@ int em86_trap(x86 *p) { if(bptaddr) *bptaddr=bptopc; t=strtok(0," \n"); i=sscanf(t,"%x",&tmp); - if(i==1) { - bptaddr=p->vbase + tmp; + if(i==1) { + bptaddr=p->vbase + tmp; bptopc=*bptaddr; *bptaddr=0xcc; } else bptaddr=NULL; @@ -362,13 +362,13 @@ int em86_trap(x86 *p) { case 'Q': return 1; break; - + case 'g': case 'G': p->eflags &= ~0x100; return 0; break; - + case 's': case 'S': /* Print the 8 stack top words */ fp = (unsigned short *)(p->ssbase+ld_le16(&SP)); @@ -390,7 +390,7 @@ int em86_trap(x86 *p) { break; case code_ud: printf("Attempt to execute an unimplemented" - "or undefined opcode!\n"); + "or undefined opcode!\n"); dump86(p); return(1); /* exit interpreter */ break; @@ -433,7 +433,7 @@ int em86_trap(x86 *p) { for(i=p->parm1; i<p->parm1+(p->reason&7); i++) { p->ioperm[i/8] &= ~(1<<i%8); } - printf("Access to ports %04x-%04x enabled.\n", + printf("Access to ports %04x-%04x enabled.\n", p->parm1, p->parm1+(p->reason&7)-1); return(0); #endif @@ -451,7 +451,7 @@ int em86_trap(x86 *p) { void cleanup_v86_mess(void) { x86 *p = (x86 *) bd->v86_private; - + /* This automatically removes the mappings ! */ vfree(p->vbase); p->vbase = 0; @@ -460,11 +460,11 @@ void cleanup_v86_mess(void) { sfree(p->ioperm); p->ioperm=0; } - + int init_v86(void) { x86 *p = (x86 *) bd->v86_private; - + /* p->vbase is non null when the v86 is properly set-up */ if (p->vbase) return 0; @@ -485,7 +485,7 @@ int init_v86(void) { /* These calls should never fail. */ vmap(p->vbase, (u_long)p->ram|PTE_RAM, 0xa0000); vmap(p->vbase+0x100000, (u_long)p->ram|PTE_RAM, 0x10000); - vmap(p->vbase+0xa0000, + vmap(p->vbase+0xa0000, ((u_long)ptr_mem_map->isa_mem_base+0xa0000)|PTE_IO, 0x20000); return 0; } @@ -502,7 +502,7 @@ void em86_main(struct pci_dev *dev){ #define IOMASK 0 #endif - + #ifndef __BOOT__ int i; /* Allow or disable access to all ports */ @@ -523,21 +523,21 @@ void em86_main(struct pci_dev *dev){ AH=dev->bus->number; AL=dev->devfn; - /* All other registers are irrelevant except ES:DI which + /* All other registers are irrelevant except ES:DI which * should point to a PnP installation check block. This * is not yet implemented due to lack of references. */ /* Store a return address of 0xffff:0xffff as eyecatcher */ *(u_int *)(p->ssbase+ld_le16(&SP)) = UINT_MAX; - + /* Interrupt for BIOS EGA services is 0xf000:0xf065 (int 0x10) */ st_le32((u_int *)p->vbase + 0x10, 0xf000f065); - + /* Enable the ROM, read it and disable it immediately */ pci_read_config_dword(dev, PCI_ROM_ADDRESS, &saved_rom); pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0x000c0001); - /* Check that there is an Intel ROM. Should we also check that + /* Check that there is an Intel ROM. Should we also check that * the first instruction is a jump (0xe9 or 0xeb) ? */ signature = *(u_short *)(ptr_mem_map->isa_mem_base+0xc0000); @@ -551,26 +551,26 @@ void em86_main(struct pci_dev *dev){ if (!p->rom) return; - for(dst=(u_int *) p->rom, + for(dst=(u_int *) p->rom, src=(volatile u_int *)(ptr_mem_map->isa_mem_base+0xc0000), - left = length*512/sizeof(u_int); - left--; + left = length*512/sizeof(u_int); + left--; *dst++=*src++); - - /* Disable the ROM and map the copy in virtual address space, note + + /* Disable the ROM and map the copy in virtual address space, note * that the ROM has to be mapped as RAM since some BIOSes (at least * Cirrus) perform write accesses to their own ROM. The reason seems * to be that they check that they must execute from shadow RAM - * because accessing the ROM prevents accessing the video RAM + * because accessing the ROM prevents accessing the video RAM * according to comments in linux/arch/alpha/kernel/bios32.c. */ - + pci_write_config_dword(dev, PCI_ROM_ADDRESS, saved_rom); vmap(p->vbase+0xc0000, (u_long)p->rom|PTE_RAM, length*512); /* Now actually emulate the ROM init routine */ em86_enter(p); - + /* Free the acquired resources */ vunmap(p->vbase+0xc0000); pfree(p->rom); diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/em86real.S b/c/src/lib/libbsp/powerpc/shared/bootloader/em86real.S index 120b5c09ee..ad38fb24fb 100644 --- a/c/src/lib/libbsp/powerpc/shared/bootloader/em86real.S +++ b/c/src/lib/libbsp/powerpc/shared/bootloader/em86real.S @@ -16,7 +16,7 @@ */ /* If the symbol __BOOT__ is defined, a slightly different version is - * generated to be compiled with the -m relocatable option + * generated to be compiled with the -m relocatable option */ #ifdef __BOOT__ @@ -24,23 +24,23 @@ /* It is impossible to gather statistics in the boot version */ #undef EIP_STATS #endif - + /* * * Given the size of this code, it deserves a few comments on how it works, - * and why it was implemented the way it is. - * + * and why it was implemented the way it is. + * * The goal is to have a real mode i486SX emulator to initialize hardware, * mostly graphics boards, by interpreting ROM BIOSes. The choice of a 486SX * is logical since this is the lowest processor that PCI ROM BIOSes must run * on. - * + * * The goal of this emulator is not performance, but a small enough memory * footprint to include it in a bootloader. * * It is actually likely to be comparable to a 25MHz 386DX on a 200MHz 603e ! - * This is not as serious as it seems since most of the BIOS code performs - * a lot of accesses to I/O and non-cacheable memory spaces. For such + * This is not as serious as it seems since most of the BIOS code performs + * a lot of accesses to I/O and non-cacheable memory spaces. For such * instructions, the execution time is often dominated by bus accesses. * Statistics of the code also shows that it spends a large function of * the time in loops waiting for vertical retrace or programs one of the @@ -61,41 +61,41 @@ * (debug registers are impossible to implement at a reasonable cost) */ -/* Code options, put them on the compiler command line */ +/* Code options, put them on the compiler command line */ /* #define EIP_STATS */ /* EIP based profiling */ /* #undef EIP_STATS */ /* * Implementation notes: * - * A) flags emulation. - * + * A) flags emulation. + * * The most important decisions when it comes to obtain a reasonable speed * are related to how the EFLAGS register is emulated. * * Note: the code to set up flags is complex, but it is only seldom - * executed since cmp and test instructions use much faster flag evaluation - * paths. For example the overflow flag is almost only needed for pushf and + * executed since cmp and test instructions use much faster flag evaluation + * paths. For example the overflow flag is almost only needed for pushf and * int. Comparison results only involve (SF^OF) or (SF^OF)+ZF and the - * implementation is fast in this case. + * implementation is fast in this case. * * Rarely used flags: AC, NT and IOPL are kept in a memory EFLAGS image. * All other flags are either kept explicitly in PPC cr (DF, IF, and TF) or * lazily evaluated from the state of 4 registers called flags, result, op1, - * op2, and sometimes the cr itself. The emulation has been designed for - * minimal overhead for the common case where the flags are never used. With - * few exceptions, all instructions that set flags leave the result of the - * computation in a register called result, and operands are taken from op1 - * and op2 registers. However a few instructions like cmp, test and bit tests + * op2, and sometimes the cr itself. The emulation has been designed for + * minimal overhead for the common case where the flags are never used. With + * few exceptions, all instructions that set flags leave the result of the + * computation in a register called result, and operands are taken from op1 + * and op2 registers. However a few instructions like cmp, test and bit tests * (bt/btc/btr/bts/bsf/bsr) explicitly set cr bits to short circuit * condition code evaluation of conditional instructions. * * As a very brief summary: - * - * - the result of the last flag setting operation is often either in the - * result register or in op2 after increment or decrement instructions + * + * - the result of the last flag setting operation is often either in the + * result register or in op2 after increment or decrement instructions * because result and op1 may be needed to compute the carry. - * + * * - compare instruction leave the result of the unsigned comparison * in cr4 and of signed comparison in cr6. This means that: * - cr4[0]=CF (short circuit for jc/jnc) @@ -103,7 +103,7 @@ * - cr6[0]=(OF^SF) (short circuit for jl/jnl) * - cr6[1]=~((SF^OF)+ZF) (short circuit for jg/jng) * - cr6[2]=ZF (short circuit for jz/jnz) - * + * * - test instruction set flags in cr6 and clear overflow. This means that: * - cr6[0]=SF=(SF^OF) (short circuit for jl/jnl/js/jns) * - cr6[1]=~((SF^OF)+ZF) (short circuit for jg/jng) @@ -111,16 +111,16 @@ * * All flags may be lazily evaluated from several values kept in registers: * - * Flag: Depends upon: + * Flag: Depends upon: * OF result, op1, op2, flags[INCDEC_FIELD,SUBTRACTING,OF_STATE_MASK] * SF result, op2, flags[INCDEC_FIELD,RES_SIZE] * ZF result, op2, cr6[2], flags[INCDEC_FIELD,RES_SIZE,ZF_PROTECT] * AF op1, op2, flags[INCDEC_FIELD,SUBTRACTING,CF_IN] * PF result, op2, flags[INCDEC_FIELD] * CF result, op1, flags[CF_STATE_MASK, CF_IN] - * - * The order of the fields in the flags register has been chosen so that a - * single rlwimi is necessary for common instruction that do not affect all + * + * The order of the fields in the flags register has been chosen so that a + * single rlwimi is necessary for common instruction that do not affect all * flags. (See the code for inc/dec emulation). * * @@ -129,8 +129,8 @@ * The register called opcode holds in its low order 8 bits the opcode * (second byte if the first byte is 0x0f). More precisely it holds the * last byte fetched before the modrm byte or the immediate operand(s) - * of the instruction, if any. High order 24 bits are zero unless the - * instruction has prefixes. These higher order bits have the following + * of the instruction, if any. High order 24 bits are zero unless the + * instruction has prefixes. These higher order bits have the following * meaning: * 0x80000000 segment override prefix * 0x00001000 repnz prefix (0xf2) @@ -139,8 +139,8 @@ * 0x00000200 operand size prefix (0x66) * (bit 0x1000 and 0x800 cannot be set simultaneously) * - * Therefore if there is a segment override the value will be between very - * negative (between 0x80000000 and 0x800016ff), if there is no segment + * Therefore if there is a segment override the value will be between very + * negative (between 0x80000000 and 0x800016ff), if there is no segment * override, the value will be between 0 and 0x16ff. The reason for * this choice will be understood in the next part. * @@ -149,7 +149,7 @@ * the encoding of the modrm bytes (especially in 16 bit mode) is quite * complex. Hence a table, indexed by the five useful bits of the modrm * byte is used to simplify decoding. Here is a description: - * + * * bit mask meaning * 0x80000000 use ss as default segment register * 0x00004000 means that this addressing mode needs a base register @@ -164,8 +164,8 @@ * 10: 32 bit addressing mode * 60: 16 bit addressing mode with %si as index * 70: 16 bit addressing mode with %di as index - * - * This convention leads to the following special values used to check for + * + * This convention leads to the following special values used to check for * sib present and displacement-only, which happen to the three lowest * values in the table (unsigned): * 0x00003090 sib follows (implies it is a 32 bit mode) @@ -186,11 +186,11 @@ * instruction has no override prefix. * * D) BUGS - * + * * This software is obviously bug-free :-). Nevertheless, if you encounter * an interesting feature. Mail me a note, if possible with a detailed * instruction example showing where and how it fails. - * + * */ @@ -205,7 +205,7 @@ is actually never checked (real mode is CPL 0 anyway). */ /* Actually NT and IOPL are kept in memory */ #define NT86 17 #define IOPL86 18 /* Actually 18 and 19 */ -#define OF86 20 +#define OF86 20 #define DF86 21 #define IF86 22 #define TF86 23 @@ -222,11 +222,11 @@ is actually never checked (real mode is CPL 0 anyway). */ #define TF 23 /* Single step flag: cr5[3] */ /* Now the flags which are frequently used */ -/* +/* * CF_IN is a copy of the input carry with PPC polarity, * it is cleared for add, set for sub and cmp, - * equal to the x86 carry for adc and to its complement for sbb. - * it is used to evaluate AF and CF. + * equal to the x86 carry for adc and to its complement for sbb. + * it is used to evaluate AF and CF. */ #define CF_IN 0x80000000 @@ -237,10 +237,10 @@ is actually never checked (real mode is CPL 0 anyway). */ #define EVAL_CF andis. r3,flags,(CF_IN_CR)>>16; beql- _eval_cf -/* - * CF_STATE tells how to compute the carry bit. - * NOTRESULT16 and NOTRESULT8 are never set explicitly, - * but they may happen after a cmc instruction. +/* + * CF_STATE tells how to compute the carry bit. + * NOTRESULT16 and NOTRESULT8 are never set explicitly, + * but they may happen after a cmc instruction. */ #define CF 16 /* cr4[0] */ #define CF_LOCATION 0x30000000 @@ -256,7 +256,7 @@ is actually never checked (real mode is CPL 0 anyway). */ #define CF_NOTRES16 0x28000000 #define CF_RES8 0x30000000 #define CF_NOTRES8 0x38000000 - + #define CF_ADDL CF_RES32 #define CF_SUBL CF_NOTRES32 #define CF_ADDW CF_RES16 @@ -269,11 +269,11 @@ is actually never checked (real mode is CPL 0 anyway). */ #define CF_POL_INSERT(dst,pos) \ rlwimi dst,flags,(36-pos)%32,pos,pos #define RES2CF(dst) rlwinm dst,result,8,7,15 - -/* + +/* * OF_STATE tells how to compute the overflow bit. When the low order bit * is set (OF_EXPLICIT), it means that OF is the exclusive or of the - * two other bits. For the reason of this choice, see rotate instructions. + * two other bits. For the reason of this choice, see rotate instructions. */ #define OF 1 /* Only after EVAL_OF */ #define OF_STATE_MASK 0x07000000 @@ -289,11 +289,11 @@ is actually never checked (real mode is CPL 0 anyway). */ #define OF_ARITHB 0x04000000 #define EVAL_OF rlwinm. r3,flags,6,0,1; bngl+ _eval_of; andis. r3,flags,OF_VALUE>>16 - + /* See _eval_of to see how this can be used */ #define OF_ROTCNT(dst) rlwinm dst,flags,10,0x1c - -/* + +/* * SIGNED_IN_CR means that cr6 is set as after a signed compare: * - cr6[0] is SF^OF for jl/jnl/setl/setnl... * - cr6[1] is ~((SF^OF)+ZF) for jg/jng/setg/setng... @@ -305,7 +305,7 @@ is actually never checked (real mode is CPL 0 anyway). */ #define EVAL_SIGNED andis. r3,flags,SIGNED_IN_CR>>16; beql- _eval_signed -/* +/* * Above in CR means that cr4 is set as after an unsigned compare: * - cr4[0] is CF (CF_IN_CR is also set) * - cr4[1] is ~(CF+ZF) (ZF_IN_CR is also set) @@ -320,28 +320,28 @@ is actually never checked (real mode is CPL 0 anyway). */ #define SF_IN_CR 0x00200000 #define EVAL_SF andis. r3,flags,SF_IN_CR>>16; beql- _eval_sf_zf - + /* ZF_IN_CR means cr6[2] is a copy of ZF. */ -#define ZF 26 +#define ZF 26 #define ZF_IN_CR 0x00100000 - + #define EVAL_ZF andis. r3,flags,ZF_IN_CR>>16; beql- _eval_sf_zf #define ZF2ZF86(s,d) rlwimi d,s,ZF-ZF86,ZF86,ZF86 #define ZF862ZF(reg) rlwimi reg,reg,32+ZF86-ZF,ZF,ZF - -/* + +/* * ZF_PROTECT means cr6[2] is the only valid value for ZF. This is necessary - * because some infrequent instructions may leave SF and ZF in an apparently + * because some infrequent instructions may leave SF and ZF in an apparently * inconsistent state (both set): sahf, popf and the few (not implemented) * instructions that only affect ZF. */ #define ZF_PROTECT 0x00080000 - + /* The parity is always evaluated when it is needed */ #define PF 0 /* Only after EVAL_PF */ #define EVAL_PF bl _eval_pf -/* This field gives the shift amount to use to evaluate SF +/* This field gives the shift amount to use to evaluate SF and ZF when ZF_PROTECT is not set */ #define RES_SIZE_MASK 0x00060000 #define RESL 0x00000000 @@ -355,12 +355,12 @@ is actually never checked (real mode is CPL 0 anyway). */ #define SUBTRACTING 0x00010000 #define GET_ADDSUB(dst) rlwinm dst,flags,16,0x01 - + /* rotate (rcl/rcr/rol/ror) affect CF and OF but not other flags */ #define ROTATE_MASK (CF_IN_CR|CF_STATE_MASK|ABOVE_IN_CR|OF_STATE_MASK|SIGNED_IN_CR) #define ROTATE_FLAGS rlwimi flags,one,24,ROTATE_MASK -/* +/* * INCDEC_FIELD has at most one bit set when the last flag setting instruction * was either inc or dec (which do not affect the carry). When one of these * bits is set, it affects the way OF, SF, ZF, AF, and PF are evaluated. @@ -380,7 +380,7 @@ is actually never checked (real mode is CPL 0 anyway). */ /* Operations to perform to tell where the flags are after inc or dec */ #define INC_FLAGS(BWL) rlwimi flags,one,INC##BWL##_SHIFT,INCDEC_MASK #define DEC_FLAGS(BWL) rlwimi flags,one,DEC##BWL##_SHIFT,INCDEC_MASK - + /* How the flags are set after arithmetic operations */ #define FLAGS_ADD(BWL) (CF_ADD##BWL|OF_ARITH##BWL|RES##BWL) #define FLAGS_SBB(BWL) (CF_SUB##BWL|OF_ARITH##BWL|RES##BWL|SUBTRACTING) @@ -405,7 +405,7 @@ is actually never checked (real mode is CPL 0 anyway). */ /* How the flags are set after multiplies */ #define FLAGS_MUL (CF_EXPLICIT|OF_EXPLICIT) - + #define SET_FLAGS(fl) lis flags,(fl)>>16 #define ADD_FLAGS(fl) addis flags,flags,(fl)>>16 @@ -413,14 +413,14 @@ is actually never checked (real mode is CPL 0 anyway). */ * We are always off by one when compared with Intel's eip, this shortens * code by allowing to load next byte with lbzu x,1(eip). The register * called eip actually contains csbase+eip, and thus should be called lip - * for linear ip. + * for linear ip. */ - -/* - * Reason codes passed to the C part of the emulator, this includes all - * instructions which may change the current code segment. These definitions + +/* + * Reason codes passed to the C part of the emulator, this includes all + * instructions which may change the current code segment. These definitions * will soon go into a separate include file. Codes 0 to 255 correspond - * directly to the interrupt/trap that has to be generated. + * directly to the interrupt/trap that has to be generated. */ #define code_divide_err 0 @@ -430,7 +430,7 @@ is actually never checked (real mode is CPL 0 anyway). */ #define code_bound 5 #define code_ud 6 #define code_dna 7 /* FPU not available */ - + #define code_iretw 256 /* Interrupt returns */ #define code_iretl 257 #define code_lcallw 258 /* Far calls and jumps */ @@ -446,7 +446,7 @@ is actually never checked (real mode is CPL 0 anyway). */ - bit of weight 512 means out if set, in if clear - bit of weight 256 means ins/outs if set, in/out if clear - bit of weight 128 means use 32 bit addresses if set, 16 bit if clear - (only used for ins/outs instructions, always clear for in/out) + (only used for ins/outs instructions, always clear for in/out) */ #define code_inb 1024+1 #define code_inw 1024+2 @@ -468,13 +468,13 @@ is actually never checked (real mode is CPL 0 anyway). */ #define code_outsl_a32 1024+512+256+128+4 #define state 31 -/* r31 (state) is a pointer to a structure describing the emulated x86 +/* r31 (state) is a pointer to a structure describing the emulated x86 processor, its layout is the following: first the general purpose registers, they are in little endian byte order offset name - + 0 eax/ax/al 1 ah 4 ecx/cx/cl @@ -509,10 +509,10 @@ offset name #define DI 28 #define EDI 28 -/* +/* than the rest of the machine state, big endian ! -offset name +offset name 32 essel segment register selectors (values) 36 cssel @@ -541,7 +541,7 @@ offset name 128 vbase where the 1Mb memory is mapped 132 cntimg instruction counter - 136 scratch + 136 scratch 192 eipstat array of 32k unsigned long pairs for eip stats */ @@ -575,18 +575,18 @@ offset name #endif /* Global registers */ -/* Some segment register bases are permanently kept in registers since they +/* Some segment register bases are permanently kept in registers since they are often used: these are csb, esb and ssb because they are required for jumps, string instructions, and pushes/pops/calls/rets. dsbase is not kept in a register but loaded from memory to allow somewhat -more parallelism in the main emulation loop. +more parallelism in the main emulation loop. */ #define one 30 /* Constant one, so pervasive */ #define ssb 29 #define csb 28 #define esb 27 -#define eip 26 /* That one is indeed csbase+(e)ip-1 */ +#define eip 26 /* That one is indeed csbase+(e)ip-1 */ #define result 25 /* For the use of result, op1, op2 */ #define op1 24 /* see the section on flag emulation */ #define op2 23 @@ -605,11 +605,11 @@ specified by the modrm byte */ #define adbase 16 /* addressing mode table */ /* Following registers are used only as dedicated temporaries during decoding, they are free for use during emulation */ -/* - * ceip (current eip) is only in use when we call the external emulator for - * instructions that fault. Note that it is forbidden to change flags before - * the check for the fault happens (divide by zero...) ! ceip is also used - * when measuring timing. +/* + * ceip (current eip) is only in use when we call the external emulator for + * instructions that fault. Note that it is forbidden to change flags before + * the check for the fault happens (divide by zero...) ! ceip is also used + * when measuring timing. */ #define ceip 15 @@ -641,7 +641,7 @@ they are free for use during emulation */ GOT_ENTRY(jtab_www) GOT_ENTRY(adtable) END_GOT -#else +#else .text #endif .align 2 @@ -717,7 +717,7 @@ exit: lwz r0,100(r1) mtcr r4 addi r1,r1,96 blr - + trap: crmove 0,RF crclr RF bt- 0,resume @@ -745,23 +745,23 @@ complex: addi eip,eip,1 cmpwi r3,0 bne exit b restart - + /* Main loop */ -/* +/* * The two LSB of each entry in the main table mean the following: - * 00: indirect opcode: modrm follows and the three middle bits are an + * 00: indirect opcode: modrm follows and the three middle bits are an * opcode extension. The entry points to another jump table. * 01: direct instruction, branch directly to the routine. * 10: modrm specifies byte size memory and register operands. * 11: modrm specifies word/long memory and register operands. - * + * * The modrm byte, if present, is always loaded in r7. * * Note: most "mr x,y" instructions have been replaced by "addi x,y,0" since - * the latter can be executed in the second integer unit on 603e. + * the latter can be executed in the second integer unit on 603e. */ -/* +/* * This code is very good example of absolutely unmaintainable code. * It was actually much easier to write than it is to understand ! * If my computations are right, the maximum path length from fetching @@ -769,7 +769,7 @@ complex: addi eip,eip,1 * 46 instructions (for non-prefixed, single byte opcode instructions). * */ - .align 5 + .align 5 #ifdef EIP_STATS nop: NEXTBYTE(opcode) gotopcode: slwi r3,opcode,2 @@ -838,9 +838,9 @@ _ds: NEXTBYTE(r7) /* Lock (unimplemented) and repeat prefixes */ _lock: li r3,code_lock; b complex -_repnz: NEXTBYTE(r7); rlwimi opcode,one,12,0x1800; b 2f +_repnz: NEXTBYTE(r7); rlwimi opcode,one,12,0x1800; b 2f _repz: NEXTBYTE(r7); rlwimi opcode,one,11,0x1800; b 2f - + /* Operand and address size prefixes */ .align 4 _opsize: NEXTBYTE(r7); ori opcode,opcode,0x200 @@ -859,7 +859,7 @@ _twobytes: NEXTBYTE(r7); addi r3,r3,0x400 NEXTBYTE(r7) # modrm byte cmpwi cr1,r7,192 rlwinm opreg,r7,31,0x1c - beq- 6f + beq- 6f /* modrm with middle 3 bits specifying a register (prefixed) */ rlwinm r0,r4,3,0x8 li r4,0x1c0d @@ -874,7 +874,7 @@ _twobytes: NEXTBYTE(r7); addi r3,r3,0x400 rlwimi r3,r7,31,0x60 lwzx r4,r3,adbase cmpwi cr1,r4,0x3090 - bnl+ cr1,10f + bnl+ cr1,10f /* displacement only addressing modes */ 4: cmpwi r4,0x2000 bne 5f @@ -882,7 +882,7 @@ _twobytes: NEXTBYTE(r7); addi r3,r3,0x400 bctr 5: NEXTDWORD(offset) bctr -/* modrm with opcode extension (prefixed) */ +/* modrm with opcode extension (prefixed) */ 6: lwzx r4,r4,opreg mtctr r4 blt cr1,3b @@ -914,7 +914,7 @@ _twobytes: NEXTBYTE(r7); addi r3,r3,0x400 rlwinm r3,r4,30,0x1c # 16bit/32bit/%si index/%di index cmpwi cr1,r3,8 # set cr1 as early as possible rlwinm r6,r4,26,0x1c # base register - lwbrx offset,state,r6 # load the base register + lwbrx offset,state,r6 # load the base register beq cr0,14f # no displacement cmpw cr2,r4,opcode # check for ss as default base bgt cr0,12f # byte offset @@ -933,7 +933,7 @@ _twobytes: NEXTBYTE(r7); addi r3,r3,0x400 bgtctr cr2 addi base,ssb,0 bctr -/* 8 bit displacement */ +/* 8 bit displacement */ 12: NEXTBYTE(r5) extsb r5,r5 bgt cr1,13f @@ -953,7 +953,7 @@ _twobytes: NEXTBYTE(r7); addi r3,r3,0x400 bgtctr cr2 addi base,ssb,0 bctr -/* no displacement: only indexed modes may use ss as default base */ +/* no displacement: only indexed modes may use ss as default base */ 14: beqctr cr1 # 32 bit register indirect clrlwi offset,offset,16 bltctr cr1 # 16 bit register indirect @@ -970,7 +970,7 @@ _twobytes: NEXTBYTE(r7); addi r3,r3,0x400 rlwinm r3,r7,31,0x1c # index rlwinm offset,r7,2,0x1c # base cmpwi cr1,r3,ESP # has index ? - bne cr0,18f # base+d8/d32 + bne cr0,18f # base+d8/d32 cmpwi offset,EBP beq 17f # d32(,index,scale) xori r4,one,0xcc01 # build 0x0000cc00 @@ -1026,25 +1026,25 @@ _twobytes: NEXTBYTE(r7); addi r3,r3,0x400 /* * Flag evaluation subroutines: they have not been written for performance - * since they are not often used in practice. The rule of the game was to + * since they are not often used in practice. The rule of the game was to * write them with as few branches as possible. * The first routines eveluate either one or 2 (ZF and SF simultaneously) * flags and do not use r0 and r7. * The more complex routines (_eval_above, _eval_signed and _eval_flags) * call the former ones, using r0 as a return address save register and - * r7 as a safe temporary. + * r7 as a safe temporary. */ -/* +/* * _eval_sf_zf evaluates simultaneously SF and ZF unless ZF is already valid * and protected because it is possible, although it is exceptional, to have - * SF and ZF set at the same time after a few instructions which may leave the - * flags in this apparently inconsistent state: sahf, popf, iret and the few - * (for now unimplemented) instructions which only affect ZF (lar, lsl, arpl, - * cmpxchg8b). This also solves the obscure case of ZF set and PF clear. + * SF and ZF set at the same time after a few instructions which may leave the + * flags in this apparently inconsistent state: sahf, popf, iret and the few + * (for now unimplemented) instructions which only affect ZF (lar, lsl, arpl, + * cmpxchg8b). This also solves the obscure case of ZF set and PF clear. * On return: SF=cr6[0], ZF=cr6[2]. */ - + _eval_sf_zf: andis. r5,flags,ZF_PROTECT>>16 rlwinm r3,flags,0,INCDEC_FIELD RES_SHIFT(r4) @@ -1066,7 +1066,7 @@ _eval_sf_zf: andis. r5,flags,ZF_PROTECT>>16 crmove SF,0 blr -/* +/* * _eval_cf may be called at any time, no other flag is affected. * On return: CF=cr4[0], r3= CF ? 0x100:0 = CF<<8. */ @@ -1083,11 +1083,11 @@ _eval_cf: addc r3,flags,flags # CF_IN to xer[ca] cmplw cr4,one,r3 # sets cr4[0] blr -/* +/* * eval_of returns the overflow flag in OF_STATE field, which will be * either 001 (OF clear) or 101 (OF set), is is only called when the two - * low order bits of OF_STATE are not 01 (otherwise it will work but - * it is an elaborate variant of a nop with a few registers destroyed) + * low order bits of OF_STATE are not 01 (otherwise it will work but + * it is an elaborate variant of a nop with a few registers destroyed) * The code multiplexes several sources in a branchless way, was fun to write. */ _eval_of: GET_ADDSUB(r4) # 0(add)/1(sub) @@ -1113,7 +1113,7 @@ _eval_of: GET_ADDSUB(r4) # 0(add)/1(sub) rlwimi flags,r3,3,OF_VALUE # insert OF blr -/* +/* * _eval_pf will always be called when needed (complex but infrequent), * there are a few quirks for a branchless solution. * On return: PF=cr0[0], PF=MSB(r3) @@ -1135,12 +1135,12 @@ _eval_pf: rlwinm r3,flags,0,INCDEC_FIELD add. r3,r4,r5 # and test to simplify blr # returns in r3 and cr0 set. -/* +/* * _eval_af will always be called when needed (complex but infrequent): * - if after inc, af is set when 4 low order bits of op1 are 0 * - if after dec, af is set when 4 low order bits of op1 are 1 * (or 0 after adding 1 as implemented here) - * - if after add/sub/adc/sbb/cmp af is set from sum of 4 LSB of op1 + * - if after add/sub/adc/sbb/cmp af is set from sum of 4 LSB of op1 * and 4 LSB of op2 (eventually complemented) plus carry in. * - other instructions leave AF undefined so the returned value is irrelevant. * Returned value must be masked with 0x10, since all other bits are undefined. @@ -1164,7 +1164,7 @@ _eval_af: rlwinm r3,flags,0,INCDEC_FIELD or r3,r4,r5 blr -/* +/* * _eval_above will only be called if ABOVE_IN_CR is not set. * On return: ZF=cr6[2], CF=cr4[0], ABOVE=cr4[1] */ @@ -1218,7 +1218,7 @@ _eval_flags: mflr r0 /* Quite simple for real mode, input in r4, returns in r3. */ _segment_load: lwz r5,vbase(state) - rlwinm r3,r4,4,0xffff0 # segment selector * 16 + rlwinm r3,r4,4,0xffff0 # segment selector * 16 add r3,r3,r5 blr @@ -1234,10 +1234,10 @@ _check_port: lwz r5,ioperm(state) and. r0,r0,r5 bne- complex blr -/* +/* * Instructions are in approximate functional order: - * 1) move, exchange, lea, push/pop, pusha/popa - * 2) cbw/cwde/cwd/cdq, zero/sign extending moves, in/out + * 1) move, exchange, lea, push/pop, pusha/popa + * 2) cbw/cwde/cwd/cdq, zero/sign extending moves, in/out * 3) arithmetic: add/sub/adc/sbb/cmp/inc/dec/neg * 4) logical: and/or/xor/test/not/bt/btc/btr/bts/bsf/bsr * 5) jump, call, ret @@ -1256,20 +1256,20 @@ _check_port: lwz r5,ioperm(state) movb_imm_reg: rlwinm opreg,opcode,2,28,29; lbz r3,1(eip) rlwimi opreg,opcode,30,31,31; lbzu opcode,2(eip) stbx r3,REG; GOTNEXT - -movw_imm_reg: lhz r3,1(eip); clrlslwi opreg,opcode,29,2; lbzu opcode,3(eip) - sthx r3,REG; GOTNEXT - -movl_imm_reg: lwz r3,1(eip); clrlslwi opreg,opcode,29,2; lbzu opcode,5(eip) - stwx r3,REG; GOTNEXT - + +movw_imm_reg: lhz r3,1(eip); clrlslwi opreg,opcode,29,2; lbzu opcode,3(eip) + sthx r3,REG; GOTNEXT + +movl_imm_reg: lwz r3,1(eip); clrlslwi opreg,opcode,29,2; lbzu opcode,5(eip) + stwx r3,REG; GOTNEXT + movb_imm_mem: lbz r0,1(eip); cmpwi opreg,0 lbzu opcode,2(eip); bne- ud stbx r0,MEM; GOTNEXT movw_imm_mem: lhz r0,1(eip); cmpwi opreg,0 lbzu opcode,3(eip); bne- ud - sthx r0,MEM; GOTNEXT + sthx r0,MEM; GOTNEXT movl_imm_mem: lwz r0,1(eip); cmpwi opreg,0 lbzu opcode,5(eip); bne- ud @@ -1277,7 +1277,7 @@ movl_imm_mem: lwz r0,1(eip); cmpwi opreg,0 /* The special short form moves between memory and al/ax/eax */ movb_al_a32: lwbrx offset,eip,one; lbz r0,AL(state); lbzu opcode,5(eip) - stbx r0,MEM; GOTNEXT + stbx r0,MEM; GOTNEXT movb_al_a16: lhbrx offset,eip,one; lbz r0,AL(state); lbzu opcode,3(eip) stbx r0,MEM; GOTNEXT @@ -1298,13 +1298,13 @@ movb_a32_al: lwbrx offset,eip,one; lbzu opcode,5(eip); lbzx r0,MEM stb r0,AL(state); GOTNEXT movb_a16_al: lhbrx offset,eip,one; lbzu opcode,3(eip); lbzx r0,MEM - stb r0,AL(state); GOTNEXT + stb r0,AL(state); GOTNEXT movw_a32_ax: lwbrx offset,eip,one; lbzu opcode,5(eip); lhzx r0,MEM sth r0,AX(state); GOTNEXT movw_a16_ax: lhbrx offset,eip,one; lbzu opcode,3(eip); lhzx r0,MEM - sth r0,AX(state); GOTNEXT + sth r0,AX(state); GOTNEXT movl_a32_eax: lwbrx offset,eip,one; lbzu opcode,5(eip); lwzx r0,MEM stw r0,EAX(state); GOTNEXT @@ -1384,12 +1384,12 @@ leaw: cmpw base,state beq- ud sthbrx offset,REG NEXT - + leal: cmpw base,state beq- ud stwbrx offset,REG NEXT - + /* Short form pushes and pops */ pushw_sp_reg: li r3,SP lhbrx r4,state,r3 @@ -1400,7 +1400,7 @@ pushw_sp_reg: li r3,SP clrlwi r4,r4,16 sthx r0,ssb,r4 NEXT - + pushl_sp_reg: li r3,SP lhbrx r4,state,r3 clrlslwi opreg,opcode,29,2 @@ -1410,7 +1410,7 @@ pushl_sp_reg: li r3,SP clrlwi r4,r4,16 stwx r0,ssb,r4 NEXT - + popw_sp_reg: li r3,SP lhbrx r4,state,r3 clrlslwi opreg,opcode,29,2 @@ -1419,7 +1419,7 @@ popw_sp_reg: li r3,SP sthbrx r4,state,r3 sthx r0,REG NEXT - + popl_sp_reg: li r3,SP lhbrx r4,state,r3 clrlslwi opreg,opcode,29,2 @@ -1437,9 +1437,9 @@ pushw_sp_imm: li r3,SP sthbrx r4,state,r3 clrlwi r4,r4,16 lbzu opcode,3(eip) - sthx r0,ssb,r4 + sthx r0,ssb,r4 GOTNEXT - + pushl_sp_imm: li r3,SP lhbrx r4,state,r3 lwz r0,1(eip) @@ -1447,7 +1447,7 @@ pushl_sp_imm: li r3,SP sthbrx r4,state,r3 clrlwi r4,r4,16 lbzu opcode,5(eip) - stwx r0,ssb,r4 + stwx r0,ssb,r4 GOTNEXT pushw_sp_imm8: li r3,SP @@ -1458,9 +1458,9 @@ pushw_sp_imm8: li r3,SP clrlwi r4,r4,16 lbzu opcode,2(eip) extsb r0,r0 - sthx r0,ssb,r4 + sthx r0,ssb,r4 GOTNEXT - + pushl_sp_imm8: li r3,SP lhbrx r4,state,r3 lhz r0,1(eip) @@ -1469,9 +1469,9 @@ pushl_sp_imm8: li r3,SP clrlwi r4,r4,16 lbzu opcode,2(eip) extsb r0,r0 - stwx r0,ssb,r4 + stwx r0,ssb,r4 GOTNEXT - + /* General push/pop */ pushw_sp: lhbrx r0,MEM li r3,SP @@ -1481,7 +1481,7 @@ pushw_sp: lhbrx r0,MEM clrlwi r4,r4,16 sthbrx r0,r4,ssb NEXT - + pushl_sp: lwbrx r0,MEM li r3,SP lhbrx r4,state,r3 @@ -1490,11 +1490,11 @@ pushl_sp: lwbrx r0,MEM clrlwi r4,r4,16 stwbrx r0,r4,ssb NEXT - + /* pop is an exception with 32 bit addressing modes, it is possible to calculate wrongly the address when esp is used as base. But 16 bit addressing modes are safe */ - + popw_sp_a16: cmpw cr1,opreg,0 # first check the opcode li r3,SP lhbrx r4,state,r3 @@ -1504,7 +1504,7 @@ popw_sp_a16: cmpw cr1,opreg,0 # first check the opcode sthx r0,MEM sthbrx r4,state,r3 NEXT - + popl_sp_a16: cmpw cr1,opreg,0 li r3,SP lhbrx r4,state,r3 @@ -1558,7 +1558,7 @@ popaw_sp: li r3,SP bdnz 1b sthbrx r4,r3,state # updated sp NEXT - + popal_sp: li r3,SP lis r0,0xef00 # mask to skip esp lhbrx r4,state,r3 @@ -1577,12 +1577,12 @@ popal_sp: li r3,SP 2: sthbrx r4,state,r3 # updated sp NEXT -/* Moves with zero or sign extension: first the special cases */ +/* Moves with zero or sign extension: first the special cases */ cbw: lbz r3,AL(state) extsb r3,r3 sthbrx r3,AX,state NEXT - + cwde: lhbrx r3,AX,state extsh r3,r3 stwbrx r3,EAX,state @@ -1618,12 +1618,12 @@ movsbl: lbzx r3,MEM NEXT .equ movsww, movw_mem_reg - + movswl: lhbrx r3,MEM extsh r3,r3 stwbrx r3,REG NEXT - + movzbw: lbzx r3,MEM rlwimi opreg,opreg,4,0x10 rlwinm opreg,opreg,0,0x1c @@ -1635,19 +1635,19 @@ movzbl: lbzx r3,MEM rlwinm opreg,opreg,0,0x1c stwbrx r3,REG NEXT - + .equ movzww, movw_mem_reg movzwl: lhbrx r3,MEM stwbrx r3,REG NEXT -/* Byte swapping */ +/* Byte swapping */ bswap: clrlslwi opreg,opcode,29,2 # extract reg from opcode lwbrx r0,REG stwx r0,REG NEXT - + /* Input/output */ inb_port_al: NEXTBYTE(r4) b 1f @@ -1659,8 +1659,8 @@ inb_dx_al: li r4,DX lbzx r5,r4,r3 eieio stb r5,AL(state) - NEXT - + NEXT + inw_port_ax: NEXTBYTE(r4) b 1f inw_dx_ax: li r4,DX @@ -1671,8 +1671,8 @@ inw_dx_ax: li r4,DX lhzx r5,r4,r3 eieio sth r5,AX(state) - NEXT - + NEXT + inl_port_eax: NEXTBYTE(r4) b 1f inl_dx_eax: li r4,DX @@ -1684,7 +1684,7 @@ inl_dx_eax: li r4,DX eieio stw r5,EAX(state) NEXT - + outb_al_port: NEXTBYTE(r4) b 1f outb_al_dx: li r4,DX @@ -1695,8 +1695,8 @@ outb_al_dx: li r4,DX lbz r5,AL(state) stbx r5,r4,r3 eieio - NEXT - + NEXT + outw_ax_port: NEXTBYTE(r4) b 1f outw_ax_dx: li r4,DX @@ -1707,8 +1707,8 @@ outw_ax_dx: li r4,DX lhz r5,AX(state) sthx r5,r4,r3 eieio - NEXT - + NEXT + outl_eax_port: NEXTBYTE(r4) b 1f outl_eax_dx: li r4,DX @@ -1825,13 +1825,13 @@ carryforadc: addc r3,flags,flags # CF_IN to xer[ca] blr ARITH_WITH_CARRY(adc, FLAGS_ADD) - + /* for sbb the input carry must be the complement of the x86 carry */ carryforsbb: addc r3,flags,flags # CF_IN to xer[ca] RES2CF(r4) # 8/16 bit carry from result subfe r3,result,op1 CF_ROTCNT(r5) - addze r3,r4 + addze r3,r4 CF_POL(r4,23) rlwnm r3,r3,r5,0x100 eqv flags,r4,r3 # CF86 ? 0xfffffeff:0xffffffff @@ -1934,7 +1934,7 @@ cmpw_imm8: lbz op2,1(eip) sub result,op1,op2 cmplw cr4,op1,op2 GOTNEXT - + cmpl_imm_eax: addi base,state,0 li offset,EAX cmpl_imm: lwbrx op1,MEM @@ -2082,7 +2082,7 @@ op##l_imm8: lbz op2,1(eip); SET_FLAGS(FLAGS_LOG(L)); lwbrx op1,MEM; \ extsb op2,op2; lbzu opcode,2(eip); \ op result,op1,op2; \ stwbrx result,MEM; GOTNEXT - + LOGICAL(or) LOGICAL(and) @@ -2149,17 +2149,17 @@ notb: lbzx r3,MEM xori r3,r3,255 stbx r3,MEM NEXT - + notw: lhzx r3,MEM xori r3,r3,65535 sthx r3,MEM NEXT - + notl: lwzx r3,MEM not r3,r3 stwx r3,MEM NEXT - + boundw: lhbrx r4,REG li r3,code_bound lhbrx r5,MEM @@ -2173,7 +2173,7 @@ boundw: lhbrx r4,REG cmpw r4,r6 ble+ nop b complex - + boundl: lwbrx r4,REG li r3,code_bound lwbrx r5,MEM @@ -2186,10 +2186,10 @@ boundl: lwbrx r4,REG b complex /* Bit test and modify instructions */ - -/* Common routine: bit index in op2, returns memory value in r3, mask in op2, -and of mask and value in op1. CF flag is set as with 32 bit add when bit is -non zero since result (which is cleared) will be less than op1, and in cr4, + +/* Common routine: bit index in op2, returns memory value in r3, mask in op2, +and of mask and value in op1. CF flag is set as with 32 bit add when bit is +non zero since result (which is cleared) will be less than op1, and in cr4, all other flags are undefined from Intel doc. Here OF and SF are cleared and ZF is set as a side effect of result being cleared. */ _setup_bitw: cmpw base,state @@ -2205,7 +2205,7 @@ _setup_bitw: cmpw base,state and op1,r3,op2 # if result<op1 cmplw cr4,result,op1 # sets CF in cr4 blr - + _setup_bitl: cmpw base,state SET_FLAGS(FLAGS_BTEST) beq- 1f @@ -2217,14 +2217,14 @@ _setup_bitl: cmpw base,state and op1,r3,op2 cmplw cr4,result,op1 blr - + /* Immediate forms bit tests are not frequent since logical are often faster */ btw_imm: NEXTBYTE(op2) b 1f btw_reg_mem: lhbrx op2,REG 1: bl _setup_bitw NEXT - + btl_imm: NEXTBYTE(op2) b 1f btl_reg_mem: lhbrx op2,REG @@ -2238,7 +2238,7 @@ btcw_reg_mem: lhbrx op2,REG xor r3,r3,op2 sthbrx r3,MEM NEXT - + btcl_imm: NEXTBYTE(op2) b 1f btcl_reg_mem: lhbrx op2,REG @@ -2246,7 +2246,7 @@ btcl_reg_mem: lhbrx op2,REG xor r3,r3,op2 stwbrx result,MEM NEXT - + btrw_imm: NEXTBYTE(op2) b 1f btrw_reg_mem: lhbrx op2,REG @@ -2254,7 +2254,7 @@ btrw_reg_mem: lhbrx op2,REG andc r3,r3,op2 sthbrx r3,MEM NEXT - + btrl_imm: NEXTBYTE(op2) b 1f btrl_reg_mem: lhbrx op2,REG @@ -2262,7 +2262,7 @@ btrl_reg_mem: lhbrx op2,REG andc r3,r3,op2 stwbrx r3,MEM NEXT - + btsw_imm: NEXTBYTE(op2) b 1f btsw_reg_mem: lhbrx op2,REG @@ -2270,7 +2270,7 @@ btsw_reg_mem: lhbrx op2,REG or r3,r3,op2 sthbrx r3,MEM NEXT - + btsl_imm: NEXTBYTE(op2) b 1f btsl_reg_mem: lhbrx op2,REG @@ -2352,11 +2352,11 @@ sjmp_l: lbz r3,1(eip) jmp_l: lwbrx r3,eip,one # Simple addi eip,eip,5 lbzux opcode,eip,r3 - GOTNEXT + GOTNEXT -/* The conditional jumps: although it should not happen, +/* The conditional jumps: although it should not happen, byte relative jumps (sjmp) may wrap around in 16 bit mode */ - + #define NOTTAKEN_S lbzu opcode,2(eip); GOTNEXT #define NOTTAKEN_W lbzu opcode,3(eip); GOTNEXT #define NOTTAKEN_L lbzu opcode,5(eip); GOTNEXT @@ -2388,35 +2388,35 @@ jecxz_l: lwz r3,ECX(state); cmpwi r3,0; beq- sjmp_l; NOTTAKEN_S /* Note that loop is somewhat strange, the data size attribute gives the size of eip, and the address size whether the counter is cx or ecx. This is the same for jcxz/jecxz. */ - + loopw_w: li opreg,CX lhbrx r0,REG sub. r0,r0,one sthbrx r0,REG bne+ sjmp_w NOTTAKEN_S - + loopl_w: li opreg,ECX lwbrx r0,REG sub. r0,r0,one stwbrx r0,REG bne+ sjmp_w NOTTAKEN_S - + loopw_l: li opreg,CX lhbrx r0,REG sub. r0,r0,one sthbrx r0,REG bne+ sjmp_l NOTTAKEN_S - + loopl_l: li opreg,ECX lwbrx r0,REG sub. r0,r0,one stwbrx r0,REG bne+ sjmp_l NOTTAKEN_S - + loopzw_w: li opreg,CX lhbrx r0,REG EVAL_ZF @@ -2425,7 +2425,7 @@ loopzw_w: li opreg,CX bf ZF,1f bne+ sjmp_w 1: NOTTAKEN_S - + loopzl_w: li opreg,ECX lwbrx r0,REG EVAL_ZF @@ -2434,7 +2434,7 @@ loopzl_w: li opreg,ECX bf ZF,1f bne+ sjmp_w 1: NOTTAKEN_S - + loopzw_l: li opreg,CX lhbrx r0,REG EVAL_ZF @@ -2443,7 +2443,7 @@ loopzw_l: li opreg,CX bf ZF,1f bne+ sjmp_l 1: NOTTAKEN_S - + loopzl_l: li opreg,ECX lwbrx r0,REG EVAL_ZF @@ -2452,7 +2452,7 @@ loopzl_l: li opreg,ECX bf ZF,1f bne+ sjmp_l 1: NOTTAKEN_S - + loopnzw_w: li opreg,CX lhbrx r0,REG EVAL_ZF @@ -2461,7 +2461,7 @@ loopnzw_w: li opreg,CX bt ZF,1f bne+ sjmp_w 1: NOTTAKEN_S - + loopnzl_w: li opreg,ECX lwbrx r0,REG EVAL_ZF @@ -2470,7 +2470,7 @@ loopnzl_w: li opreg,ECX bt ZF,1f bne+ sjmp_w 1: NOTTAKEN_S - + loopnzw_l: li opreg,CX lhbrx r0,REG EVAL_ZF @@ -2479,7 +2479,7 @@ loopnzw_l: li opreg,CX bt ZF,1f bne+ sjmp_l 1: NOTTAKEN_S - + loopnzl_l: li opreg,ECX lwbrx r0,REG EVAL_ZF @@ -2489,7 +2489,7 @@ loopnzl_l: li opreg,ECX bne+ sjmp_l 1: NOTTAKEN_S -/* Memory indirect calls are rare enough to limit code duplication */ +/* Memory indirect calls are rare enough to limit code duplication */ callw_sp_mem: lhbrx r3,MEM sub r4,eip,csb addi r4,r4,1 # r4 is now return address @@ -2522,7 +2522,7 @@ retw_sp_imm: li opreg,SP GOTNEXT .equ retl_sp_imm, unimpl - + retw_sp: li opreg,SP lhbrx r4,REG addi r5,r4,2 @@ -2535,8 +2535,8 @@ retw_sp: li opreg,SP /* Enter is a mess, and the description in Intel documents is actually wrong * in most revisions (all PPro/PII I have but the old Pentium is Ok) ! - */ - + */ + enterw_sp: lhbrx r0,eip,one # Stack space to allocate li opreg,SP lhbrx r3,REG # SP @@ -2557,12 +2557,12 @@ enterw_sp: lhbrx r0,eip,one # Stack space to allocate addi r3,r3,-2 clrlwi r3,r3,16 sthx r4,ssb,r3 -2: bdnz 1b +2: bdnz 1b addi r3,r3,-2 # save current frame pointer clrlwi r3,r3,16 sthbrx r6,ssb,r3 3: sthbrx r6,state,r7 # New BP - sub r3,r3,r0 + sub r3,r3,r0 sthbrx r3,REG # Save new stack pointer NEXT @@ -2570,13 +2570,13 @@ enterw_sp: lhbrx r0,eip,one # Stack space to allocate leavew_sp: li opreg,BP lhbrx r3,REG # Stack = BP - addi r4,r3,2 # + addi r4,r3,2 # lhzx r3,ssb,r3 li opreg,SP sthbrx r4,REG # New Stack sth r3,BP(state) # Popped BP NEXT - + .equ leavel_sp, unimpl /* String instructions: first a generic setup routine, which exits early @@ -2596,11 +2596,11 @@ _setup_stringw: li offset,SI # cmpwi r3,0 beq nop # early exit here ! 1: mtctr r3 # ctr=CX or 1 - li r7,1 # stride + li r7,1 # stride bflr+ DF li r7,-1 # change stride sign blr - + /* Ending routine to update all changed registers (goes directly to NEXT) */ _finish_strw: li r4,SI sthbrx offset,state,r4 # update si @@ -2620,7 +2620,7 @@ lodsb_a16: bl _setup_stringw bdnz 1b stb r0,AL(state) b _finish_strw - + lodsw_a16: bl _setup_stringw slwi r7,r7,1 1: lhzx r0,STRINGSRC # [rep] lodsw @@ -2629,7 +2629,7 @@ lodsw_a16: bl _setup_stringw bdnz 1b sth r0,AX(state) b _finish_strw - + lodsl_a16: bl _setup_stringw slwi r7,r7,2 1: lwzx r0,STRINGSRC # [rep] lodsl @@ -2638,7 +2638,7 @@ lodsl_a16: bl _setup_stringw bdnz 1b stw r0,EAX(state) b _finish_strw - + stosb_a16: bl _setup_stringw lbz r0,AL(state) 1: stbx r0,STRINGDST # [rep] stosb @@ -2646,7 +2646,7 @@ stosb_a16: bl _setup_stringw clrlwi opreg,opreg,16 bdnz 1b b _finish_strw - + stosw_a16: bl _setup_stringw lhz r0,AX(state) slwi r7,r7,1 @@ -2655,7 +2655,7 @@ stosw_a16: bl _setup_stringw clrlwi opreg,opreg,16 bdnz 1b b _finish_strw - + stosl_a16: bl _setup_stringw lwz r0,EAX(state) slwi r7,r7,2 @@ -2664,7 +2664,7 @@ stosl_a16: bl _setup_stringw clrlwi opreg,opreg,16 bdnz 1b b _finish_strw - + movsb_a16: bl _setup_stringw 1: lbzx r0,STRINGSRC # [rep] movsb add offset,offset,r7 @@ -2674,7 +2674,7 @@ movsb_a16: bl _setup_stringw clrlwi opreg,opreg,16 bdnz 1b b _finish_strw - + movsw_a16: bl _setup_stringw slwi r7,r7,1 1: lhzx r0,STRINGSRC # [rep] movsw @@ -2685,7 +2685,7 @@ movsw_a16: bl _setup_stringw clrlwi opreg,opreg,16 bdnz 1b b _finish_strw - + movsl_a16: bl _setup_stringw slwi r7,r7,2 1: lwzx r0,STRINGSRC # [rep] movsl @@ -2696,14 +2696,14 @@ movsl_a16: bl _setup_stringw clrlwi opreg,opreg,16 bdnz 1b b _finish_strw - + /* At least on a Pentium, repeated string I/O instructions check for access port permission even if count is 0 ! So the order of the check is not important. */ insb_a16: li r4,DX li r3,code_insb_a16 lhbrx r4,state,r4 - bl _check_port + bl _check_port bl _setup_stringw lwz base,iobase(state) 1: lbzx r0,base,r4 # [rep] insb @@ -2713,11 +2713,11 @@ insb_a16: li r4,DX clrlwi opreg,opreg,16 bdnz 1b b _finish_strw - + insw_a16: li r4,DX li r3,code_insw_a16 lhbrx r4,state,r4 - bl _check_port + bl _check_port bl _setup_stringw lwz base,iobase(state) slwi r7,r7,1 @@ -2728,11 +2728,11 @@ insw_a16: li r4,DX clrlwi opreg,opreg,16 bdnz 1b b _finish_strw - + insl_a16: li r4,DX li r3,code_insl_a16 lhbrx r4,state,r4 - bl _check_port + bl _check_port bl _setup_stringw lwz base,iobase(state) slwi r7,r7,2 @@ -2743,17 +2743,17 @@ insl_a16: li r4,DX clrlwi opreg,opreg,16 bdnz 1b b _finish_strw - + outsb_a16: li r4,DX li r3,code_outsb_a16 lhbrx r4,state,r4 - bl _check_port + bl _check_port bl _setup_stringw lwz r6,iobase(state) 1: lbzx r0,STRINGSRC # [rep] outsb add offset,offset,r7 stbx r0,r6,r4 - clrlwi offset,offset,16 + clrlwi offset,offset,16 eieio bdnz 1b b _finish_strw @@ -2761,7 +2761,7 @@ outsb_a16: li r4,DX outsw_a16: li r4,DX li r3,code_outsw_a16 lhbrx r4,state,r4 - bl _check_port + bl _check_port bl _setup_stringw li r5,DX lwz r6,iobase(state) @@ -2769,7 +2769,7 @@ outsw_a16: li r4,DX 1: lhzx r0,STRINGSRC # [rep] outsw add offset,offset,r7 sthx r0,r6,r4 - clrlwi offset,offset,16 + clrlwi offset,offset,16 eieio bdnz 1b b _finish_strw @@ -2777,14 +2777,14 @@ outsw_a16: li r4,DX outsl_a16: li r4,DX li r3,code_outsl_a16 lhbrx r4,state,r4 - bl _check_port + bl _check_port bl _setup_stringw lwz r6,iobase(state) slwi r7,r7,2 1: lwzx r0,STRINGSRC # [rep] outsl add offset,offset,r7 stwx r0,r6,r4 - clrlwi offset,offset,16 + clrlwi offset,offset,16 eieio bdnz 1b b _finish_strw @@ -2869,7 +2869,7 @@ cmpsl_a16: bl _setup_stringw clrlwi opreg,opreg,16 bdnzf CF+2,3b b 2b - + scasb_a16: bl _setup_stringw lbzx op1,AL,state # AL SET_FLAGS(FLAGS_CMP(B)) @@ -2939,7 +2939,7 @@ scasl_a16: bl _setup_stringw .equ lodsb_a32, unimpl .equ lodsw_a32, unimpl .equ lodsl_a32, unimpl - .equ stosb_a32, unimpl + .equ stosb_a32, unimpl .equ stosw_a32, unimpl .equ stosl_a32, unimpl .equ movsb_a32, unimpl @@ -2964,22 +2964,22 @@ xlatb_a16: li offset,BX add r3,r3,base lbzx r3,r3,offset stb r3,AL(state) - NEXT + NEXT .equ xlatb_a32, unimpl -/* +/* * Shift and rotates: note the oddity that rotates do not affect SF/ZF/AF/PF * but shifts do. Also testing has indicated that rotates with a count of zero - * do not affect any flag. The documentation specifies this for shifts but - * is more obscure for rotates. The overflow flag setting is only specified + * do not affect any flag. The documentation specifies this for shifts but + * is more obscure for rotates. The overflow flag setting is only specified * when count is 1, otherwise OF is undefined which simplifies emulation. */ -/* +/* * The rotates through carry are among the most difficult instructions, * they are implemented as a shift of 2*n+some bits depending on case. - * First the left rotates through carry. + * First the left rotates through carry. */ /* Byte rcl is performed on 18 bits (17 actually used) in a single register */ @@ -3008,7 +3008,7 @@ rclb_1: li r3,1 rlwnm r0,r0,r3,0x000001ff # (23)0:NewCF:Result8 rlwimi flags,r0,19,CF_VALUE stbx r0,MEM - rlwimi flags,r0,18,OF_XOR + rlwimi flags,r0,18,OF_XOR NEXT /* Word rcl is performed on 33 bits (CF:data16:CF:(15 MSB of data16) */ @@ -3040,7 +3040,7 @@ rclw_1: li r3,1 add r0,r0,r4 # result rlwimi flags,r0,11,CF_VALUE sthbrx r0,MEM - rlwimi flags,r0,10,OF_XOR + rlwimi flags,r0,10,OF_XOR NEXT /* Longword rcl only needs 64 bits because the maximum rotate count is 31 ! */ @@ -3106,7 +3106,7 @@ rcrb_1: li r3,1 /* Word rcr is a 33 bit right shift with a quirk, because the 33rd bit is only needed when the rotate count is 16 and rotating left or right -by 16 a 32 bit quantity is the same ! */ +by 16 a 32 bit quantity is the same ! */ rcrw_imm: NEXTBYTE(r3) b 1f rcrw_cl: lbz r3,CL(state) @@ -3179,7 +3179,7 @@ rolb_1: li r3,1 rlwimi r0,r0,24,0xff000000 # replicate for shift in beq- nop # no flags changed if count 0 ROTATE_FLAGS - rotlw r0,r0,r3 + rotlw r0,r0,r3 rlwimi flags,r0,27,CF_VALUE # New CF stbx r0,MEM rlwimi flags,r0,26,OF_XOR # New OF (CF xor MSB) @@ -3660,7 +3660,7 @@ divl: li opreg,EDX # Not yet fully implemented stwbrx r5,EAX,state stwbrx r4,REG NEXT -/* +/* * Divide r4:r5 by r3, quotient in r5, remainder in r4. * The algorithm is stupid because it won't be used very often. */ @@ -3805,7 +3805,7 @@ movw_sr_mem: cmpwi opreg,20 # SREG 0 to 5 only 1: sthbrx r0,MEM NEXT -/* Now the instructions that modify the segment registers, note that +/* Now the instructions that modify the segment registers, note that move/pop to ss disable interrupts and traps for one instruction ! */ popl_sp_sr: li r6,4 b 1f @@ -3826,7 +3826,7 @@ popw_sp_sr: li r6,2 lwz ssb,ssbase(state) # pop ss crmove RF,TF # prevent traps NEXT - + movw_mem_sr: cmpwi opreg,20 addi r7,state,SELBASES bgt- ud @@ -3841,11 +3841,11 @@ movw_mem_sr: cmpwi opreg,20 bne+ nop lwz ssb,ssbase(state) crmove RF,TF # prevent traps - NEXT - + NEXT + .equ movl_mem_sr, movw_mem_sr -/* The encoding of les/lss/lds/lfs/lgs is strange, opcode is c4/b2/c5/b4/b5 +/* The encoding of les/lss/lds/lfs/lgs is strange, opcode is c4/b2/c5/b4/b5 for es/ss/ds/fs/gs which are sreg 0/2/3/4/5. And obviously there is no lcs instruction, it's called a far jump. */ @@ -3859,7 +3859,7 @@ ldlptrw: lhzux r7,MEM bl 1f sthx r7,REG NEXT - + 1: cmpw base,state lis r3,0xc011 # es/ss/ds/fs/gs rlwinm r5,opcode,2,0x0c # 00/08/04/00/04 @@ -3879,7 +3879,7 @@ ldlptrw: lhzux r7,MEM blr -/* Intructions that may modify the current code segment: the next optimization +/* Intructions that may modify the current code segment: the next optimization * might be to avoid calling C code when the code segment does not change. But * it's probably not worth the effort. */ @@ -3972,13 +3972,13 @@ stc: oris flags,flags,\ (CF_IN_CR|CF_LOCATION|CF_COMPLEMENT|ABOVE_IN_CR)>>16 xoris flags,flags,(CF_IN_CR|CF_LOCATION|ABOVE_IN_CR)>>16 NEXT - + cld: crclr DF NEXT std: crset DF NEXT - + cli: crclr IF NEXT @@ -4029,7 +4029,7 @@ popfl_sp: li r4,SP stw r3,eflags(state) sthbrx r5,r4,state b 1f - + popfw_sp: li r4,SP lhbrx r5,r4,state lhbrx r3,ssb,r5 @@ -4066,7 +4066,7 @@ setnz: EVAL_ZF #define SETCC(cond, eval, flag) \ set##cond: EVAL_##eval; bt flag,1b; b 0b; \ setn##cond: EVAL_##eval; bt flag,0b; b 1b - + SETCC(c, CF, CF) SETCC(a, ABOVE, ABOVE) SETCC(s, SF, SF) @@ -4134,7 +4134,7 @@ daa: lbz r0,AL(state) stb result,AL(state) rlwimi result,r3,2,0x100 # set CF if added NEXT - + das: lbz r0,AL(state) bl _eval_af rlwinm r7,r3,0,0x10 @@ -4153,7 +4153,7 @@ das: lbz r0,AL(state) stb result,AL(state) rlwimi result,r3,2,0x100 # set CF NEXT - + /* 486 specific instructions */ /* For cmpxchg, only the zero flag is important */ @@ -4226,7 +4226,7 @@ esc: li r3,code_dna # DNA interrupt .equ invd, unimpl -/* Undefined in real address mode */ +/* Undefined in real address mode */ .equ lar, ud .equ lgdt, unimpl @@ -4250,7 +4250,7 @@ esc: li r3,code_dna # DNA interrupt .equ smsw, unimpl .equ str, ud - + ud: li r3,code_ud li r4,0 b complex @@ -4272,7 +4272,7 @@ em86_end: .section .rodata #define ENTRY(x,t) .long x+t #endif - + #define BOP(x) ENTRY(x,2) /* Byte operation with mod/rm byte */ #define WLOP(x) ENTRY(x,3) /* 16 or 32 bit operation with mod/rm byte */ #define EXTOP(x) ENTRY(x,0) /* Opcode with extension in mod/rm byte */ @@ -4488,7 +4488,7 @@ _jtables: jtable(w, a16, sp, ax, www) /* data16, addr16 */ jtable(l, a32, sp, eax, llw) /* data32, addr32 */ /* The other possible combinations are only required by protected mode code using a big stack segment */ -/* Here are the auxiliary tables for opcode extensions, note that +/* Here are the auxiliary tables for opcode extensions, note that all entries get 2 or 3 added. */ #define grp1table(bwl,t,s8) \ grp1##bwl##_imm##s8:; \ @@ -4543,7 +4543,7 @@ grp5##wl##_##spesp: \ WLOP(inc##wl); WLOP(dec##wl); \ WLOP(call##wl##_##spesp##_mem); WLOP(lcall##wl##); \ WLOP(jmp##wl); WLOP(ljmp##wl); \ - WLOP(push##wl##_##spesp); OP(ud) + WLOP(push##wl##_##spesp); OP(ud) grp5table(w,sp) grp5table(l,sp) @@ -4551,7 +4551,7 @@ grp5##wl##_##spesp: \ #define grp8table(wl) \ grp8##wl: OP(ud); OP(ud); OP(ud); OP(ud); \ WLOP(bt##wl##_imm); WLOP(bts##wl##_imm); \ - WLOP(btr##wl##_imm); WLOP(btc##wl##_imm) + WLOP(btr##wl##_imm); WLOP(btc##wl##_imm) grp8table(w) grp8table(l) diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/exception.S b/c/src/lib/libbsp/powerpc/shared/bootloader/exception.S index 059c62cd32..46f719c443 100644 --- a/c/src/lib/libbsp/powerpc/shared/bootloader/exception.S +++ b/c/src/lib/libbsp/powerpc/shared/bootloader/exception.S @@ -16,80 +16,80 @@ */ /* This is an improved version of the TLB interrupt handling code from - * the 603e users manual (603eUM.pdf) downloaded from the WWW. All the - * visible bugs have been removed. Note that many have survived in the errata - * to the 603 user manual (603UMer.pdf). - * + * the 603e users manual (603eUM.pdf) downloaded from the WWW. All the + * visible bugs have been removed. Note that many have survived in the errata + * to the 603 user manual (603UMer.pdf). + * * This code also pays particular attention to optimization, takes into * account the differences between 603 and 603e, single/multiple processor * systems and tries to order instructions for dual dispatch in many places. - * + * * The optimization has been performed along two lines: * 1) to minimize the number of instruction cache lines needed for the most * common execution paths (the ones that do not result in an exception). - * 2) then to order the code to maximize the number of dual issue and - * completion opportunities without increasing the number of cache lines + * 2) then to order the code to maximize the number of dual issue and + * completion opportunities without increasing the number of cache lines * used in the same cases. - * + * * The last goal of this code is to fit inside the address range * assigned to the interrupt vectors: 192 instructions with fixed * entry points every 64 instructions. - * + * * Some typos have also been corrected and the Power l (lowercase L) * instructions replaced by lwz without comment. - * + * * I have attempted to describe the reasons of the order and of the choice * of the instructions but the comments may be hard to understand without * the processor manual. - * + * * Note that the fact that the TLB are reloaded by software in theory - * allows tremendous flexibility, for example we could avoid setting the + * allows tremendous flexibility, for example we could avoid setting the * reference bit of the PTE which will could actually not be accessed because - * of protection violation by changing a few lines of code. However, + * of protection violation by changing a few lines of code. However, * this would significantly slow down most TLB reload operations, and * this is the reason for which we try never to make checks which would be * redundant with hardware and usually indicate a bug in a program. - * + * * There are some inconsistencies in the documentation concerning the - * settings of SRR1 bit 15. All recent documentations say now that it is set + * settings of SRR1 bit 15. All recent documentations say now that it is set * for stores and cleared for loads. Anyway this handler never uses this bit. - * + * * A final remark, the rfi instruction seems to implicitly clear the * MSR<14> (tgpr)bit. The documentation claims that this bit is restored * from SRR1 by rfi, but the corresponding bit in SRR1 is the LRU way bit. * Anyway, the only exception which can occur while TGPR is set is a machine * check which would indicate an unrecoverable problem. Recent documentation - * now says in some place that rfi clears MSR<14>. - * - * TLB software load for 602/603/603e/603ev: - * Specific Instructions: - * tlbld - write the dtlb with the pte in rpa reg - * tlbli - write the itlb with the pte in rpa reg - * Specific SPRs: - * dmiss - address of dstream miss + * now says in some place that rfi clears MSR<14>. + * + * TLB software load for 602/603/603e/603ev: + * Specific Instructions: + * tlbld - write the dtlb with the pte in rpa reg + * tlbli - write the itlb with the pte in rpa reg + * Specific SPRs: + * dmiss - address of dstream miss * imiss - address of istream miss - * hash1 - address primary hash PTEG address - * hash2 - returns secondary hash PTEG address - * iCmp - returns the primary istream compare value - * dCmp - returns the primary dstream compare value + * hash1 - address primary hash PTEG address + * hash2 - returns secondary hash PTEG address + * iCmp - returns the primary istream compare value + * dCmp - returns the primary dstream compare value * rpa - the second word of pte used by tlblx - * Other specific resources: + * Other specific resources: * cr0 saved in 4 high order bits of SRR1, - * SRR1 bit 14 [WAY] selects TLB set to load from LRU algorithm - * gprs r0..r3 shadowed by the setting of MSR bit 14 [TGPR] + * SRR1 bit 14 [WAY] selects TLB set to load from LRU algorithm + * gprs r0..r3 shadowed by the setting of MSR bit 14 [TGPR] * other bits in SRR1 (unused by this handler but see earlier comments) - * + * * There are three basic flows corresponding to three vectors: - * 0x1000: Instruction TLB miss, + * 0x1000: Instruction TLB miss, * 0x1100: Data TLB miss on load, - * 0x1200: Data TLB miss on store or not dirty page + * 0x1200: Data TLB miss on store or not dirty page */ - + /* define the following if code does not have to run on basic 603 */ /* #define USE_KEY_BIT */ - + /* define the following for safe multiprocessing */ -/* #define MULTIPROCESSING */ +/* #define MULTIPROCESSING */ /* define the following for mixed endian */ /* #define CHECK_MIXED_ENDIAN */ @@ -100,53 +100,53 @@ /* Some OS kernels may want to keep a single copy of the dirty bit in a per * page table. In this case writable pages are always write-protected as long * as they are clean, and the dirty bit set actually means that the page - * is writable. + * is writable. */ -#define DIRTY_MEANS_WRITABLE - +#define DIRTY_MEANS_WRITABLE + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include "bootldr.h" -/* - * Instruction TLB miss flow - * Entry at 0x1000 with the following: - * srr0 -> address of instruction that missed - * srr1 -> 0:3=cr0, 13=1 (instruction), 14=lru way, 16:31=saved MSR - * msr<tgpr> -> 1 - * iMiss -> ea that missed - * iCmp -> the compare value for the va that missed +/* + * Instruction TLB miss flow + * Entry at 0x1000 with the following: + * srr0 -> address of instruction that missed + * srr1 -> 0:3=cr0, 13=1 (instruction), 14=lru way, 16:31=saved MSR + * msr<tgpr> -> 1 + * iMiss -> ea that missed + * iCmp -> the compare value for the va that missed * hash1 -> pointer to first hash pteg - * hash2 -> pointer to second hash pteg + * hash2 -> pointer to second hash pteg * - * Register usage: - * r0 is limit address during search / scratch after + * Register usage: + * r0 is limit address during search / scratch after * r1 is pte data / error code for ISI exception when search fails - * r2 is pointer to pte + * r2 is pointer to pte * r3 is compare value during search / scratch after */ /* Binutils or assembler bug ? Declaring the section executable and writable * generates an error message on the @fixup entries. */ - .section .exception,"aw" + .section .exception,"aw" # .org 0x1000 # instruction TLB miss entry point .globl tlb_handlers tlb_handlers: .type tlb_handlers,@function #define ISIVec tlb_handlers-0x1000+0x400 #define DSIVec tlb_handlers-0x1000+0x300 - mfspr r2,HASH1 + mfspr r2,HASH1 lwz r1,0(r2) # Start memory access as soon as possible - mfspr r3,ICMP # to load the cache. + mfspr r3,ICMP # to load the cache. 0: la r0,48(r2) # Use explicit loop to avoid using ctr 1: cmpw r1,r3 # In theory the loop is somewhat slower beq- 2f # than documentation example - cmpw r0,r2 # but we gain from starting cache load - lwzu r1,8(r2) # earlier and using slots between load - bne+ 1b # and comparison for other purposes. + cmpw r0,r2 # but we gain from starting cache load + lwzu r1,8(r2) # earlier and using slots between load + bne+ 1b # and comparison for other purposes. cmpw r1,r3 bne- 4f # Secondary hash check -2: lwz r1,4(r2) # Found: load second word of PTE +2: lwz r1,4(r2) # Found: load second word of PTE mfspr r0,IMISS # get miss address during load delay #ifdef ASSUME_REF_SET andi. r3,r1,8 # check for guarded memory @@ -159,12 +159,12 @@ tlb_handlers: # andi. r3,r1,8 # check for guarded memory # bne- 5f # andi. r3,r1,0x100 # check R bit ahead to help folding -/* However there is a better solution: these last three instructions can be -replaced by the following which should cause less pipeline stalls because +/* However there is a better solution: these last three instructions can be +replaced by the following which should cause less pipeline stalls because both tests are combined and there is a single CR rename buffer */ extlwi r3,r1,6,23 # Keep only RCWIMG in 6 most significant bits. - rlwinm. r3,r3,5,0,27 # Keep only G (in sign) and R and test. - blt- 5f # Negative means guarded, zero R not set. + rlwinm. r3,r3,5,0,27 # Keep only G (in sign) and R and test. + blt- 5f # Negative means guarded, zero R not set. mfsrr1 r3 # get saved cr0 bits now to dual issue ori r1,r1,0x100 mtspr RPA,r1 @@ -174,7 +174,7 @@ writeback at a later time, and avoid even more bus traffic in multiprocessing systems, when several processors access the same PTEGs. We also hope that the reference bit will be already set. */ bne+ 3f -#ifdef MULTIPROCESSING +#ifdef MULTIPROCESSING srwi r1,r1,8 # get byte 7 of pte stb r1,+6(r2) # update page table #else @@ -183,7 +183,7 @@ We also hope that the reference bit will be already set. */ #endif 3: mtcrf 0x80,r3 # restore CR0 rfi # return to executing program - + /* The preceding code is 20 to 25 instructions long, which occupies 3 or 4 cache lines. */ 4: andi. r0,r3,0x0040 # see if we have done second hash @@ -194,9 +194,9 @@ We also hope that the reference bit will be already set. */ lwz r1,0(r2) # load first entry b 0b # and go back to main loop /* We are now at 27 to 32 instructions, using 3 or 4 cache lines for all -cases in which the TLB is successfully loaded. */ +cases in which the TLB is successfully loaded. */ -/* Guarded memory protection violation: synthesize an ISI exception. */ +/* Guarded memory protection violation: synthesize an ISI exception. */ 5: lis r1,0x1000 # set srr1<3>=1 to flag guard violation /* Entry Not Found branches here with r1 correctly set. */ 6: mfsrr1 r3 @@ -209,41 +209,41 @@ a field of contiguous bits in a register by setting mask_begin>mask_end. */ mtcrf 0x80, r3 # restore CR0 mtmsr r0 # flip back to the native gprs isync # Required from 602 doc! - b ISIVec # go to instruction access exception -/* Up to now there are 37 to 42 instructions so at least 20 could be -inserted for complex cases or for statistics recording. */ + b ISIVec # go to instruction access exception +/* Up to now there are 37 to 42 instructions so at least 20 could be +inserted for complex cases or for statistics recording. */ -/* - Data TLB miss on load flow - Entry at 0x1100 with the following: - srr0 -> address of instruction that caused the miss - srr1 -> 0:3=cr0, 13=0 (data), 14=lru way, 15=0, 16:31=saved MSR - msr<tgpr> -> 1 - dMiss -> ea that missed - dCmp -> the compare value for the va that missed +/* + Data TLB miss on load flow + Entry at 0x1100 with the following: + srr0 -> address of instruction that caused the miss + srr1 -> 0:3=cr0, 13=0 (data), 14=lru way, 15=0, 16:31=saved MSR + msr<tgpr> -> 1 + dMiss -> ea that missed + dCmp -> the compare value for the va that missed hash1 -> pointer to first hash pteg - hash2 -> pointer to second hash pteg - - Register usage: - r0 is limit address during search / scratch after + hash2 -> pointer to second hash pteg + + Register usage: + r0 is limit address during search / scratch after r1 is pte data / error code for DSI exception when search fails - r2 is pointer to pte + r2 is pointer to pte r3 is compare value during search / scratch after */ - .org tlb_handlers+0x100 - mfspr r2,HASH1 + .org tlb_handlers+0x100 + mfspr r2,HASH1 lwz r1,0(r2) # Start memory access as soon as possible mfspr r3,DCMP # to load the cache. 0: la r0,48(r2) # Use explicit loop to avoid using ctr 1: cmpw r1,r3 # In theory the loop is somewhat slower beq- 2f # than documentation example - cmpw r0,r2 # but we gain from starting cache load - lwzu r1,8(r2) # earlier and using slots between load - bne+ 1b # and comparison for other purposes. + cmpw r0,r2 # but we gain from starting cache load + lwzu r1,8(r2) # earlier and using slots between load + bne+ 1b # and comparison for other purposes. cmpw r1,r3 bne- 4f # Secondary hash check -2: lwz r1,4(r2) # Found: load second word of PTE +2: lwz r1,4(r2) # Found: load second word of PTE mfspr r0,DMISS # get miss address during load delay #ifdef ASSUME_REF_SET mtspr RPA,r1 @@ -260,7 +260,7 @@ writeback at a later time, and avoid even more bus traffic in multiprocessing systems, when several processors access the same PTEGs. We also hope that the reference bit will be already set. */ bne+ 3f -#ifdef MULTIPROCESSING +#ifdef MULTIPROCESSING srwi r1,r1,8 # get byte 7 of pte stb r1,+6(r2) # update page table #else @@ -269,7 +269,7 @@ We also hope that the reference bit will be already set. */ #endif 3: mtcrf 0x80,r3 # restore CR0 rfi # return to executing program - + /* The preceding code is 18 to 23 instructions long, which occupies 3 cache lines. */ 4: andi. r0,r3,0x0040 # see if we have done second hash @@ -280,55 +280,55 @@ We also hope that the reference bit will be already set. */ lwz r1,0(r2) # load first entry asap b 0b # and go back to main loop /* We are now at 25 to 30 instructions, using 3 or 4 cache lines for all -cases in which the TLB is successfully loaded. */ +cases in which the TLB is successfully loaded. */ -/* - Data TLB miss on store or not dirty page flow - Entry at 0x1200 with the following: - srr0 -> address of instruction that caused the miss - srr1 -> 0:3=cr0, 13=0 (data), 14=lru way, 15=1, 16:31=saved MSR - msr<tgpr> -> 1 - dMiss -> ea that missed - dCmp -> the compare value for the va that missed +/* + Data TLB miss on store or not dirty page flow + Entry at 0x1200 with the following: + srr0 -> address of instruction that caused the miss + srr1 -> 0:3=cr0, 13=0 (data), 14=lru way, 15=1, 16:31=saved MSR + msr<tgpr> -> 1 + dMiss -> ea that missed + dCmp -> the compare value for the va that missed hash1 -> pointer to first hash pteg - hash2 -> pointer to second hash pteg - - Register usage: - r0 is limit address during search / scratch after + hash2 -> pointer to second hash pteg + + Register usage: + r0 is limit address during search / scratch after r1 is pte data / error code for DSI exception when search fails - r2 is pointer to pte + r2 is pointer to pte r3 is compare value during search / scratch after -*/ +*/ .org tlb_handlers+0x200 - mfspr r2,HASH1 + mfspr r2,HASH1 lwz r1,0(r2) # Start memory access as soon as possible - mfspr r3,DCMP # to load the cache. + mfspr r3,DCMP # to load the cache. 0: la r0,48(r2) # Use explicit loop to avoid using ctr 1: cmpw r1,r3 # In theory the loop is somewhat slower beq- 2f # than documentation example - cmpw r0,r2 # but we gain from starting cache load - lwzu r1,8(r2) # earlier and using slots between load - bne+ 1b # and comparison for other purposes. + cmpw r0,r2 # but we gain from starting cache load + lwzu r1,8(r2) # earlier and using slots between load + bne+ 1b # and comparison for other purposes. cmpw r1,r3 bne- 4f # Secondary hash check -2: lwz r1,4(r2) # Found: load second word of PTE +2: lwz r1,4(r2) # Found: load second word of PTE mfspr r0,DMISS # get miss address during load delay -/* We could simply set the C bit and then rely on hardware to flag protection -violations. This raises the problem that a page which actually has not been -modified may be marked as dirty and violates the OEA model for guaranteed -bit settings (table 5-8 of 603eUM.pdf). This can have harmful consequences -on operating system memory management routines, and play havoc with copy on +/* We could simply set the C bit and then rely on hardware to flag protection +violations. This raises the problem that a page which actually has not been +modified may be marked as dirty and violates the OEA model for guaranteed +bit settings (table 5-8 of 603eUM.pdf). This can have harmful consequences +on operating system memory management routines, and play havoc with copy on write schemes. So the protection check is ABSOLUTELY necessary. */ andi. r3,r1,0x80 # check C bit - beq- 5f # if (C==0) go to check protection -3: mfsrr1 r3 # get the saved cr0 bits + beq- 5f # if (C==0) go to check protection +3: mfsrr1 r3 # get the saved cr0 bits mtspr RPA,r1 # set the pte - tlbld r0 # load the dtlb - mtcrf 0x80,r3 # restore CR0 - rfi # return to executing program + tlbld r0 # load the dtlb + mtcrf 0x80,r3 # restore CR0 + rfi # return to executing program /* The preceding code is 20 instructions long, which occupy -3 cache lines. */ +3 cache lines. */ 4: andi. r0,r3,0x0040 # see if we have done second hash lis r1,0x4200 # set up error code in case next branch taken bne- 9f # speculatively issue the following @@ -342,21 +342,21 @@ cases in which the TLB C bit is already set. */ #ifdef DIRTY_MEANS_WRITABLE 5: lis r1,0x0A00 # protection violation on store #else -/* - Entry found and C==0: check protection before setting C: - Register usage: +/* + Entry found and C==0: check protection before setting C: + Register usage: r0 is dMiss register - r1 is PTE entry (to be copied to RPA if success) - r2 is pointer to pte - r3 is trashed + r1 is PTE entry (to be copied to RPA if success) + r2 is pointer to pte + r3 is trashed For the 603e, the key bit in SRR1 helps to decide whether there is a protection violation. However the way the check is done in the manual is not very efficient. The code shown here works as well for 603 and 603e and is much more efficient for the 603 and comparable to the manual example - for 603e. This code however has quite a bad structure due to the fact it - has been reordered to speed up the most common cases. -*/ + for 603e. This code however has quite a bad structure due to the fact it + has been reordered to speed up the most common cases. +*/ /* The first of the following two instructions could be replaced by andi. r3,r1,3 but it would compete with cmplwi for cr0 resource. */ 5: clrlwi r3,r1,30 # Extract two low order bits @@ -368,59 +368,59 @@ andi. r3,r1,3 but it would compete with cmplwi for cr0 resource. */ /* We are now at 33 instructions, using 5 cache lines. */ 7: bgt- 8f # if PP=11 then DSI protection exception /* This code only works if key bit is present (602/603e/603ev) */ -#ifdef USE_KEY_BIT +#ifdef USE_KEY_BIT mfsrr1 r3 # get the KEY bit and test it andis. r3,r3,0x0008 beq 6b # default prediction taken, truly better ? -#else +#else /* This code is for all 602 and 603 family models: */ mfsrr1 r3 # Here the trick is to use the MSR PR bit as a mfsrin r0,r0 # shift count for an rlwnm. instruction which extrwi r3,r3,1,17 # extracts and tests the correct key bit from rlwnm. r3,r0,r3,1,1 # the segment register. RISC they said... - mfspr r0,DMISS # Restore fault address to r0 + mfspr r0,DMISS # Restore fault address to r0 beq 6b # if 0 load tlb else protection fault #endif /* We are now at 40 instructions, (37 if using key bit), using 5 cache lines in all cases in which the C bit is successfully set */ 8: lis r1,0x0A00 # protection violation on store #endif /* DIRTY_IS_WRITABLE */ -/* PTE entry not found branch here with DSISR code in r1 */ +/* PTE entry not found branch here with DSISR code in r1 */ 9: mfsrr1 r3 mtdsisr r1 - clrlwi r2,r3,16 # set up srr1 for DSI exception + clrlwi r2,r3,16 # set up srr1 for DSI exception mfmsr r0 /* I have some doubts about the usefulness of the xori instruction in mixed or pure little-endian environment. The address is in the same doubleword, hence in the same protection domain and performing an exclusive or with 7 is only valid for byte accesses. */ -#ifdef CHECK_MIXED_ENDIAN +#ifdef CHECK_MIXED_ENDIAN andi. r1,r2,1 # test LE bit ahead to help folding #endif mtsrr1 r2 - rlwinm r0,r0,0,15,13 # clear the msr<tgpr> bit + rlwinm r0,r0,0,15,13 # clear the msr<tgpr> bit mfspr r1,DMISS # get miss address #ifdef CHECK_MIXED_ENDIAN - beq 1f # if little endian then: - xori r1,r1,0x07 # de-mung the data address + beq 1f # if little endian then: + xori r1,r1,0x07 # de-mung the data address 1: -#endif - mtdar r1 # put in dar - mtcrf 0x80,r3 # restore CR0 +#endif + mtdar r1 # put in dar + mtcrf 0x80,r3 # restore CR0 mtmsr r0 # flip back to the native gprs - isync # required from 602 manual + isync # required from 602 manual b DSIVec # branch to DSI exception /* We are now between 50 and 56 instructions. Close to the limit but should be sufficient in case bugs are found. */ -/* Altogether the three handlers occupy 128 instructions in the worst +/* Altogether the three handlers occupy 128 instructions in the worst case, 64 instructions could still be added (non contiguously). */ .org tlb_handlers+0x300 .globl _handler_glue _handler_glue: /* Entry code for exceptions: DSI (0x300), ISI(0x400), alignment(0x600) and * traps(0x700). In theory it is not necessary to save and restore r13 and all - * higher numbered registers, but it is done because it allowed to call the - * firmware (PPCBug) for debugging in the very first stages when writing the + * higher numbered registers, but it is done because it allowed to call the + * firmware (PPCBug) for debugging in the very first stages when writing the * bootloader. */ stwu r1,-160(r1) diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/head.S b/c/src/lib/libbsp/powerpc/shared/bootloader/head.S index b0eeb0e550..cb6d9134fc 100644 --- a/c/src/lib/libbsp/powerpc/shared/bootloader/head.S +++ b/c/src/lib/libbsp/powerpc/shared/bootloader/head.S @@ -19,16 +19,16 @@ #include <rtems/score/cpu.h> #include "bootldr.h" -#define TEST_PPCBUG_CALLS +#define TEST_PPCBUG_CALLS #undef TEST_PPCBUG_CALLS - + #define FRAME_SIZE 32 #define LOCK_CACHES (HID0_DLOCK | HID0_ILOCK) #define INVL_CACHES (HID0_DCI | HID0_ICFI) #define ENBL_CACHES (HID0_DCE | HID0_ICE) #define USE_PPCBUG - + #define PRINT_CHAR(c) \ addi r20,r3,0 ; \ li r3,c ; \ @@ -37,10 +37,10 @@ addi r3,r20,0 ; \ li r10,0x26 ; \ sc - - - - + + + + #define MONITOR_ENTER \ mfmsr r10 ; \ ori r10,r10,MSR_IP ; \ @@ -48,8 +48,8 @@ li r10,0x63 ; \ sc - - + + START_GOT GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_) @@ -61,21 +61,21 @@ GOT_ENTRY(_binary_rtems_gz_start) GOT_ENTRY(_binary_initrd_gz_start) GOT_ENTRY(_binary_initrd_gz_end) -#ifdef TEST_PPCBUG_CALLS +#ifdef TEST_PPCBUG_CALLS GOT_ENTRY(banner_start) GOT_ENTRY(banner_end) -#endif +#endif #ifdef USE_PPCBUG GOT_ENTRY(nioc_reset_packet) #endif END_GOT .globl start .type start,@function - + /* Point the stack into the PreP partition header in the x86 reserved - * code area, so that simple C routines can be called. + * code area, so that simple C routines can be called. */ -start: +start: #if defined(USE_PPCBUG) && defined(DEBUG) && defined(REENTER_MONITOR) MONITOR_ENTER #endif @@ -89,9 +89,9 @@ start: ori r0,r28,MSR_EE xori r0,r0,MSR_EE mtmsr r0 - + /* Enable the caches, from now on cr2.eq set means processor is 601 */ - + mfpvr r0 mfspr r29,HID0 srwi r0,r0,16 @@ -103,7 +103,7 @@ start: * commented out, 11/7/2002, gregm. This instruction sequence seems to * be pathological on the 603e. * - + #ifndef USE_PPCBUG ori r0,r29,ENBL_CACHES|INVL_CACHES|LOCK_CACHES xori r0,r0,INVL_CACHES|LOCK_CACHES @@ -112,10 +112,10 @@ start: mtspr HID0,r0 #endif */ - - + + 2: bl reloc - + /* save all the parameters and the orginal msr/hid0/r31 */ lwz bd,GOT(__bd) stw r3,0(bd) @@ -135,21 +135,21 @@ start: * corrupted by the IF DMAing data into its old buffers or * by writing descriptors... */ - lwz r3,GOT(nioc_reset_packet) + lwz r3,GOT(nioc_reset_packet) li r10, 0x1d /* .NETCTRL */ sc #endif -/* Call the routine to fill boot_data structure from residual data. - * And to find where the code has to be moved. +/* Call the routine to fill boot_data structure from residual data. + * And to find where the code has to be moved. */ lis r3,__size@sectoff@ha addi r3,r3,__size@sectoff@l bl early_setup -/* Now we need to relocate ourselves, where we are told to. First put a +/* Now we need to relocate ourselves, where we are told to. First put a * copy of the codemove routine to some place in memory. - * (which may be where the 0x41 partition was loaded, so size is critical). + * (which may be where the 0x41 partition was loaded, so size is critical). */ lwz r4,GOT(codemove) li r5,_size_codemove @@ -175,14 +175,14 @@ start: mtlr r8 # for the return address bctr # returns to the moved instruction - + /* Establish the new top stack frame. */ moved: lwz r1,stack(bd) li r0,0 stwu r0,-16(r1) /* relocate again */ - bl reloc + bl reloc /* Clear all of BSS */ lwz r10,GOT(.bss) li r0,__bss_words@sectoff@l @@ -213,7 +213,7 @@ moved: lwz r1,stack(bd) /* Some firmware versions leave stale values in the BATs, it's time * to invalidate them to avoid interferences with our own mappings. * But the 601 valid bit is in the BATL (IBAT only) and others are in - * the [ID]BATU. Bloat, bloat.. fortunately thrown away later. + * the [ID]BATU. Bloat, bloat.. fortunately thrown away later. */ #if defined(USE_PPCBUG) && defined(DEBUG) PRINT_CHAR('T') @@ -239,22 +239,22 @@ moved: lwz r1,stack(bd) PRINT_CHAR('i') #endif bl mm_init - + #if defined(USE_PPCBUG) && defined(DEBUG) PRINT_CHAR('M') #endif bl MMUon - + /* Now we are mapped and can perform I/O if we want */ -#ifdef TEST_PPCBUG_CALLS +#ifdef TEST_PPCBUG_CALLS /* Experience seems to show that PPCBug can only be called with the * data cache disabled and with MMU disabled. Bummer. - */ + */ li r10,0x22 # .OUTLN lwz r3,GOT(banner_start) lwz r4,GOT(banner_end) sc -#endif +#endif #if defined(USE_PPCBUG) && defined(DEBUG) PRINT_CHAR('H') #endif @@ -294,9 +294,9 @@ moved: lwz r1,stack(bd) li r30,0 */ dcbst 0,r30 /* Make sure it's in memory ! */ - -/* We just flash invalidate and disable the dcache, unless it's a 601, - * critical areas have been flushed and we don't care about the stack + +/* We just flash invalidate and disable the dcache, unless it's a 601, + * critical areas have been flushed and we don't care about the stack * and other scratch areas. */ beq cr2,1f @@ -306,20 +306,20 @@ moved: lwz r1,stack(bd) mtspr HID0,r0 xori r0,r0,HID0_DCI|HID0_DCE mtspr HID0,r0 - + /* Provisional return to FW, works for PPCBug */ #if 0 && defined(REENTER_MONITOR) MONITOR_ENTER #else 1: bctr #endif - - + + /* relocation function, r30 must point to got2+0x8000 */ -reloc: +reloc: /* Adjust got2 pointers, no need to check for 0, this code already puts - * a few entries in the table. + * a few entries in the table. */ li r0,__got2_entries@sectoff@l la r12,GOT(_GOT2_TABLE_) @@ -331,10 +331,10 @@ reloc: add r0,r0,r11 stw r0,0(r12) bdnz 1b - + /* Now adjust the fixups and the pointers to the fixups in case we need - * to move ourselves again. - */ + * to move ourselves again. + */ 2: li r0,__fixup_entries@sectoff@l lwz r12,GOT(_FIXUP_TABLE_) cmpwi r0,0 @@ -347,18 +347,18 @@ reloc: stw r10,0(r12) stw r0,0(r10) bdnz 3b - blr + blr /* Set the MMU on and off: code is always mapped 1:1 and does not need MMU, * but it does not cost so much to map it also and it catches calls through - * NULL function pointers. + * NULL function pointers. */ .globl MMUon .type MMUon,@function MMUon: blr nop -/* +/* mfmsr r0 ori r0,r0,MSR_IR|MSR_DR|MSR_IP mflr r11 @@ -371,7 +371,7 @@ MMUon: blr .type MMUoff,@function MMUoff: blr nop - + /* mfmsr r0 ori r0,r0,MSR_IR|MSR_DR|MSR_IP @@ -383,9 +383,9 @@ MMUoff: blr */ /* Due to the PPC architecture (and according to the specifications), a - * series of tlbie which goes through a whole 256 MB segment always flushes - * the whole TLB. This is obviously overkill and slow, but who cares ? - * It takes about 1 ms on a 200 MHz 603e and works even if residual data + * series of tlbie which goes through a whole 256 MB segment always flushes + * the whole TLB. This is obviously overkill and slow, but who cares ? + * It takes about 1 ms on a 200 MHz 603e and works even if residual data * get the number of TLB entries wrong. */ flush_tlb: @@ -396,8 +396,8 @@ flush_tlb: /* tlbsync is not implemented on 601, so use sync which seems to be a superset * of tlbsync in all cases and do not bother with CPU dependant code */ - sync - blr + sync + blr .globl codemove codemove: @@ -410,11 +410,11 @@ codemove: beq 7f /* Protect against 0 count */ mtctr r0 bge cr1,2f - + la r8,-4(r4) la r7,-4(r3) 1: lwzu r0,4(r8) - stwu r0,4(r7) + stwu r0,4(r7) bdnz 1b b 4f @@ -424,23 +424,23 @@ codemove: 3: lwzu r0,-4(r8) stwu r0,-4(r7) bdnz 3b - + /* Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. + * address. Otherwise we might miss one cache line. */ 4: cmpwi r6,0 add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ + beq 7f /* Always flush prefetch queue in any case */ subi r0,r6,1 andc r3,r3,r0 mr r4,r3 -5: cmplw r4,r5 +5: cmplw r4,r5 dcbst 0,r4 add r4,r4,r6 blt 5b sync /* Wait for all dcbst to complete on bus */ mr r4,r3 -6: cmplw r4,r5 +6: cmplw r4,r5 icbi 0,r4 add r4,r4,r6 blt 6b @@ -467,8 +467,8 @@ nioc_reset_packet: .long 0 /* Number of bytes */ .long 0 /* Status/Control Flags (unused for reset) */ #endif -#ifdef TEST_PPCBUG_CALLS -banner_start: +#ifdef TEST_PPCBUG_CALLS +banner_start: .ascii "This message was printed by PPCBug with MMU enabled" -banner_end: +banner_end: #endif diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/lib.c b/c/src/lib/libbsp/powerpc/shared/bootloader/lib.c index b988d968b4..ae6cf1fafc 100644 --- a/c/src/lib/libbsp/powerpc/shared/bootloader/lib.c +++ b/c/src/lib/libbsp/powerpc/shared/bootloader/lib.c @@ -27,11 +27,11 @@ void* memcpy(void *dst, const void * src, unsigned int n) { unsigned char *d=dst; const unsigned char *s=src; - + while(n-- > 0) *d++=*s++; return dst; } - + char* strcat(char * dest, const char * src) { char *tmp = dest; diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/misc.c b/c/src/lib/libbsp/powerpc/shared/bootloader/misc.c index 1ae0cf7a10..6b4718e7ea 100644 --- a/c/src/lib/libbsp/powerpc/shared/bootloader/misc.c +++ b/c/src/lib/libbsp/powerpc/shared/bootloader/misc.c @@ -57,13 +57,13 @@ extern struct console_io vacuum_console_functions; extern opaque log_console_setup, serial_console_setup, vga_console_setup; boot_data __bd = {0, 0, 0, 0, 0, 0, 0, 0, - 32, 0, 0, 0, 0, 0, 0, + 32, 0, 0, 0, 0, 0, 0, &mm_private, NULL, &pci_private, NULL, &v86_private, - "root=/dev/hdc1" + "root=/dev/hdc1" }; static void exit(void) __attribute__((noreturn)); @@ -80,7 +80,7 @@ void hang(const char *s, u_long x, ctxt *p) { #ifdef DEBUG print_all_maps("\nMemory mappings at exception time:\n"); #endif - printk("%s %lx NIP: %p LR: %p\n" + printk("%s %lx NIP: %p LR: %p\n" "Callback trace (stack:return address)\n", s, x, (void *) p->nip, (void *) p->lr); asm volatile("lwz %0,0(1); lwz %0,0(%0); lwz %0,0(%0)": "=b" (r1)); @@ -142,7 +142,7 @@ void gunzip(void *dst, int dstlen, unsigned char *src, int *lenp) printk("gunzip: ran out of data in header\n"); exit(); } - + s.zalloc = zalloc; s.zfree = zfree; r = inflateInit2(&s, -MAX_WBITS); @@ -163,9 +163,9 @@ void gunzip(void *dst, int dstlen, unsigned char *src, int *lenp) inflateEnd(&s); } -void decompress_kernel(int kernel_size, void * zimage_start, int len, +void decompress_kernel(int kernel_size, void * zimage_start, int len, void * initrd_start, int initrd_len ) { - u_char *parea; + u_char *parea; RESIDUAL* rescopy; int zimage_size= len; @@ -181,12 +181,12 @@ void decompress_kernel(int kernel_size, void * zimage_start, int len, exit(); } /* Note that this clears the bss as a side effect, so some code - * with ugly special case for SMP could be removed from the kernel! + * with ugly special case for SMP could be removed from the kernel! */ memset(parea, 0, kernel_size); printk("\nUncompressing the kernel...\n"); rescopy=salloc(sizeof(RESIDUAL)); - /* Let us hope that residual data is aligned on word boundary */ + /* Let us hope that residual data is aligned on word boundary */ *rescopy = *bd->residual; bd->residual = (void *)PAGE_ALIGN(kernel_size); @@ -203,7 +203,7 @@ void decompress_kernel(int kernel_size, void * zimage_start, int len, * DMA from the last pages of memory is slower because * prefetching from PCI has to be disabled to avoid accessing * non existing memory. So it is the ideal place to put the - * hash table. + * hash table. */ unsigned tmp = rescopy->TotalMemory; /* It's equivalent to tmp & (-tmp), but using the negation @@ -227,7 +227,7 @@ void decompress_kernel(int kernel_size, void * zimage_start, int len, printk("done\nNow booting...\n"); MMUoff(); /* We need to access address 0 ! */ codemove(0, parea, kernel_size, bd->cache_lsize); - codemove(bd->residual, rescopy, sizeof(RESIDUAL), bd->cache_lsize); + codemove(bd->residual, rescopy, sizeof(RESIDUAL), bd->cache_lsize); codemove(bd->r6, bd->cmd_line, sizeof(bd->cmd_line), bd->cache_lsize); /* codemove checks for 0 length */ codemove(bd->load_address, initrd_start, initrd_len, bd->cache_lsize); @@ -248,7 +248,7 @@ boot_udelay(uint32_t _microseconds) } while (now - start < ticks); } -void +void setup_hw(void) { char *cp, ch; @@ -258,9 +258,9 @@ setup_hw(void) int timer, err; u_short default_vga_cmd; static unsigned int indic; - + indic = 0; - + res=bd->residual; default_vga=NULL; default_vga_cmd = 0; @@ -274,10 +274,10 @@ setup_hw(void) ticks_per_ms = 16500; /* assume 66 MHz on bus */ } } - + select_console(CONSOLE_LOG); - /* We check that the keyboard is present and immediately + /* We check that the keyboard is present and immediately * select the serial console if not. */ err = kbdreset(); @@ -294,11 +294,11 @@ setup_hw(void) (vpd.TimeBaseDivisor ? vpd.TimeBaseDivisor : 4000), res->TotalMemory); printk("Original MSR: %lx\nOriginal HID0: %lx\nOriginal R31: %lx\n", - bd->o_msr, bd->o_hid0, bd->o_r31); + bd->o_msr, bd->o_hid0, bd->o_r31); /* This reconfigures all the PCI subsystem */ pci_init(); - + /* The Motorola NT firmware does not set the correct mem size */ if ( vpd.FirmwareSupplier == 0x10000 ) { int memsize; @@ -311,7 +311,7 @@ setup_hw(void) } } #define ENABLE_VGA_USAGE -#undef ENABLE_VGA_USAGE +#undef ENABLE_VGA_USAGE #ifdef ENABLE_VGA_USAGE /* Find the primary VGA device, chosing the first one found * if none is enabled. The basic loop structure has been copied @@ -338,7 +338,7 @@ setup_hw(void) /* Disable the enabled VGA device, if any. */ if (default_vga) - pci_write_config_word(default_vga, PCI_COMMAND, + pci_write_config_word(default_vga, PCI_COMMAND, default_vga_cmd& ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)); init_v86(); @@ -349,23 +349,23 @@ setup_hw(void) ((p->class) >> 16 != PCI_BASE_CLASS_DISPLAY)) continue; if (p->bus->number != 0) continue; - pci_read_config_word(p, PCI_COMMAND, &cmd); - pci_write_config_word(p, PCI_COMMAND, + pci_read_config_word(p, PCI_COMMAND, &cmd); + pci_write_config_word(p, PCI_COMMAND, cmd|PCI_COMMAND_IO|PCI_COMMAND_MEMORY); printk("Calling the emulator.\n"); em86_main(p); pci_write_config_word(p, PCI_COMMAND, cmd); - } + } cleanup_v86_mess(); -#endif +#endif /* Reenable the primary VGA device */ if (default_vga) { - pci_write_config_word(default_vga, PCI_COMMAND, + pci_write_config_word(default_vga, PCI_COMMAND, default_vga_cmd| (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)); - if (err) { - printk("Keyboard error %d, using serial console!\n", + if (err) { + printk("Keyboard error %d, using serial console!\n", err); } else { select_console(CONSOLE_VGA); @@ -386,14 +386,14 @@ setup_hw(void) /* In the future we may use the NVRAM to store default * kernel parameters. */ - nvram=residual_find_device(~0UL, NULL, SystemPeripheral, NVRAM, + nvram=residual_find_device(~0UL, NULL, SystemPeripheral, NVRAM, ~0UL, 0); if (nvram) { PnP_TAG_PACKET * pkt; - switch (nvram->DevId.Interface) { + switch (nvram->DevId.Interface) { case IndirectNVRAM: pkt=PnP_find_packet(res->DevicePnpHeap - +nvram->AllocatedOffset, + +nvram->AllocatedOffset, ) } } @@ -426,7 +426,7 @@ setup_hw(void) /* Functions to deal with the residual data */ static int same_DevID(unsigned short vendor, unsigned short Number, - char * str) + char * str) { static unsigned const char hexdigit[]="0123456789ABCDEF"; if (strlen(str)!=7) return 0; @@ -473,11 +473,11 @@ PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, if (tag_type(packet_tag)) mask=0xff; else mask=0xF8; masked_tag = packet_tag&mask; for(; *p != END_TAG; p+=size) { - if ((*p & mask) == masked_tag && !(n--)) + if ((*p & mask) == masked_tag && !(n--)) return (PnP_TAG_PACKET *) p; if (tag_type(*p)) size=ld_le16((unsigned short *)(p+1))+3; - else + else size=tag_small_count(*p)+1; } return 0; /* not found */ @@ -490,7 +490,7 @@ PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p, int next=0; while (p) { p = (unsigned char *) PnP_find_packet(p, 0x70, next); - if (p && p[1]==packet_type && !(n--)) + if (p && p[1]==packet_type && !(n--)) return (PnP_TAG_PACKET *) p; next = 1; }; @@ -504,7 +504,7 @@ PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, int next=0; while (p) { p = (unsigned char *) PnP_find_packet(p, 0x84, next); - if (p && p[3]==packet_type && !(n--)) + if (p && p[3]==packet_type && !(n--)) return (PnP_TAG_PACKET *) p; next = 1; }; @@ -526,12 +526,12 @@ find_max_mem( struct pci_dev *dev ) (dev->device == PCI_DEVICE_ID_MOTOROLA_MPC105)) || ((dev->vendor == PCI_VENDOR_ID_IBM) && (dev->device == 0x0037/*IBM 660 Bridge*/)) ) { - pci_read_config_byte(dev, 0xa0, &banks); + pci_read_config_byte(dev, 0xa0, &banks); for (i = 0; i < 8; i++) { if ( banks & (1<<i) ) { - pci_read_config_byte(dev, 0x90+i, &tmp); + pci_read_config_byte(dev, 0x90+i, &tmp); top = tmp; - pci_read_config_byte(dev, 0x98+i, &tmp); + pci_read_config_byte(dev, 0x98+i, &tmp); top |= (tmp&3)<<8; if ( top > max ) max = top; } diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/mm.c b/c/src/lib/libbsp/powerpc/shared/bootloader/mm.c index 38739fbb92..4371ae6a0d 100644 --- a/c/src/lib/libbsp/powerpc/shared/bootloader/mm.c +++ b/c/src/lib/libbsp/powerpc/shared/bootloader/mm.c @@ -25,16 +25,16 @@ * residual data. The holes between these areas can be virtually * remapped to any of these, since for some functions it is very handy * to have virtually contiguous but physically discontiguous memory. - * + * * Physical memory allocation is also very crude, since it's only * designed to manage a small number of large chunks. For valloc/vfree * and palloc/pfree, the unit of allocation is the 4kB page. - * + * * The salloc/sfree has been added after tracing gunzip and seeing * how it performed a very large number of small allocations. * For these the unit of allocation is 8 bytes (the s stands for - * small or subpage). This memory is cleared when allocated. - * + * small or subpage). This memory is cleared when allocated. + * */ #include <rtems/bspIo.h> @@ -50,7 +50,7 @@ * we want to avoid potential clashes with kernel includes. * Here a map maps contiguous areas from base to end, * the firstpte entry corresponds to physical address and has the low - * order bits set for caching and permission. + * order bits set for caching and permission. */ typedef struct _map { @@ -82,7 +82,7 @@ typedef struct _map { #define MAP_FREE_SUBS 6 #define MAP_USED_SUBS 7 -#define MAP_FREE 4 +#define MAP_FREE 4 #define MAP_FREE_PHYS 12 #define MAP_USED_PHYS 13 #define MAP_FREE_VIRT 20 @@ -114,7 +114,7 @@ struct _mm_private { map *sallocused; /* Used maps for salloc */ map *sallocphys; /* Physical areas used by salloc */ u_int hashcnt; /* Used to cycle in PTEG when they overflow */ -} mm_private = {hashmask: 0xffc0, +} mm_private = {hashmask: 0xffc0, freemaps: free_maps+0}; /* A simplified hash table entry declaration */ @@ -125,7 +125,7 @@ typedef struct _hash_entry { void print_maps(map *, const char *); -/* The handler used for all exceptions although for now it is only +/* The handler used for all exceptions although for now it is only * designed to properly handle MMU interrupts to fill the hash table. */ @@ -149,7 +149,7 @@ void _handler(int vec, ctxt *p) { printk("\nPanic: vector=%x, cause=%lx\n", vec, cause); hang("Memory protection violation at ", vaddr, p); } - + for(area=mm->mappings; area; area=area->next) { if(area->base<=vaddr && vaddr<=area->end) break; } @@ -158,13 +158,13 @@ void _handler(int vec, ctxt *p) { u_long hash, vsid, rpn; hash_entry volatile *hte, *_hte1; u_int i, alt=0, flushva; - + vsid = _read_SR((void *)vaddr); rpn = (vaddr&PAGE_MASK)-area->base+area->firstpte; hash = vsid<<6; hash ^= (vaddr>>(PAGE_SHIFT-6))&0x3fffc0; hash &= mm->hashmask; - /* Find an empty entry in the PTEG, else + /* Find an empty entry in the PTEG, else * replace a random one. */ hte = (hash_entry *) ((u_long)(mm->sdr1)+hash); @@ -174,14 +174,14 @@ void _handler(int vec, ctxt *p) { hash ^= mm->hashmask; alt = 0x40; _hte1 = hte; hte = (hash_entry *) ((u_long)(mm->sdr1)+hash); - + for (i=0; i<8; i++) { if (hte[i].key>=0) goto found; } alt = 0; hte = _hte1; /* Chose a victim entry and replace it. There might be - * better policies to choose the victim, but in a boot + * better policies to choose the victim, but in a boot * loader we want simplicity as long as it works. * * We would not need to invalidate the TLB entry since @@ -211,7 +211,7 @@ void _handler(int vec, ctxt *p) { } } else { MMUon(); - printk("\nPanic: vector=%x, dsisr=%lx, faultaddr =%lx, msr=%lx opcode=%lx\n", vec, + printk("\nPanic: vector=%x, dsisr=%lx, faultaddr =%lx, msr=%lx opcode=%lx\n", vec, cause, p->nip, p->msr, * ((unsigned int*) p->nip) ); if (vec == 7) { unsigned int* ptr = ((unsigned int*) p->nip) - 4 * 10; @@ -308,13 +308,13 @@ map * alloc_map_page(void) { if (!from) return NULL; from->end -= PAGE_SIZE; - + mm->freemaps = (map *) (from->end+1); - + for(p=mm->freemaps; p<mm->freemaps+PAGE_SIZE/sizeof(map)-1; p++) { p->next = p+1; p->firstpte = MAP_FREE; - } + } (p-1)->next=0; /* Take the last one as pointer to self and insert @@ -324,12 +324,12 @@ map * alloc_map_page(void) { p->firstpte = MAP_PERM_PHYS; p->base=(u_long) mm->freemaps; p->end = p->base+PAGE_SIZE-1; - + insert_map(&mm->physperm, p); - - if (from->end+1 == from->base) + + if (from->end+1 == from->base) free_map(remove_map(&mm->physavail, from)); - + return mm->freemaps; } @@ -364,13 +364,13 @@ void coalesce_maps(map *p) { /* These routines are used to find the free memory zones to avoid * overlapping destructive copies when initializing. - * They work from the top because of the way we want to boot. + * They work from the top because of the way we want to boot. * In the following the term zone refers to the memory described * by one or several contiguous so called segments in the * residual data. */ #define STACK_PAGES 2 -static inline u_long +static inline u_long find_next_zone(RESIDUAL *res, u_long lowpage, u_long flags) { u_long i, newmin=0, size=0; for(i=0; i<res->ActualNumMemSegs; i++) { @@ -384,14 +384,14 @@ find_next_zone(RESIDUAL *res, u_long lowpage, u_long flags) { return newmin+size; } -static inline u_long +static inline u_long find_zone_start(RESIDUAL *res, u_long highpage, u_long flags) { u_long i; int progress; do { progress=0; for (i=0; i<res->ActualNumMemSegs; i++) { - if ( (res->Segs[i].BasePage+res->Segs[i].PageCount + if ( (res->Segs[i].BasePage+res->Segs[i].PageCount == highpage) && res->Segs[i].Usage & flags) { highpage=res->Segs[i].BasePage; @@ -441,8 +441,8 @@ fix_residual( RESIDUAL *res ) res->Segs[i].BasePage = seg_fix[i].BasePage; res->Segs[i].PageCount = seg_fix[i].PageCount; } - /* The following should be fixed in the current version of the - * kernel and of the bootloader. + /* The following should be fixed in the current version of the + * kernel and of the bootloader. */ #if 0 /* PPCBug has this zero */ @@ -468,10 +468,10 @@ fix_residual( RESIDUAL *res ) /* This routine is the first C code called with very little stack space! * Its goal is to find where the boot image can be moved. This will - * be the highest address with enough room. + * be the highest address with enough room. */ int early_setup(u_long image_size) { - register RESIDUAL *res = bd->residual; + register RESIDUAL *res = bd->residual; u_long minpages = PAGE_ALIGN(image_size)>>PAGE_SHIFT; /* Fix residual if we are loaded by Motorola NT firmware */ @@ -481,19 +481,19 @@ int early_setup(u_long image_size) { /* FIXME: if OF we should do something different */ if( !bd->of_entry && res && res->ResidualLength <= sizeof(RESIDUAL) && res->Version == 0 ) { - u_long lowpage=ULONG_MAX, highpage; + u_long lowpage=ULONG_MAX, highpage; u_long imghigh=0, stkhigh=0; - /* Find the highest and large enough contiguous zone + /* Find the highest and large enough contiguous zone consisting of free and BootImage sections. */ - /* Find 3 free areas of memory, one for the main image, one - * for the stack (STACK_PAGES), and page one to put the map - * structures. They are allocated from the top of memory. + /* Find 3 free areas of memory, one for the main image, one + * for the stack (STACK_PAGES), and page one to put the map + * structures. They are allocated from the top of memory. * In most cases the stack will be put just below the image. */ - while((highpage = + while((highpage = find_next_zone(res, lowpage, BootImage|Free))) { lowpage=find_zone_start(res, highpage, BootImage|Free); - if ((highpage-lowpage)>minpages && + if ((highpage-lowpage)>minpages && highpage>imghigh) { imghigh=highpage; highpage -=minpages; @@ -510,14 +510,14 @@ int early_setup(u_long image_size) { /* The code mover is put at the lowest possible place * of free memory. If this corresponds to the loaded boot - * partition image it does not matter because it overrides - * the unused part of it (x86 code). + * partition image it does not matter because it overrides + * the unused part of it (x86 code). */ bd->mover=(void *) (lowpage<<PAGE_SHIFT); - /* Let us flush the caches in all cases. After all it should - * not harm even on 601 and we don't care about performance. - * Right now it's easy since all processors have a line size + /* Let us flush the caches in all cases. After all it should + * not harm even on 601 and we don't care about performance. + * Right now it's easy since all processors have a line size * of 32 bytes. Once again residual data has proved unreliable. */ bd->cache_lsize = 32; @@ -548,14 +548,14 @@ void * valloc(u_long size) { return (void *)q->base; } -static +static void vflush(map *virtmap) { struct _mm_private * mm = (struct _mm_private *) bd->mm_private; u_long i, limit=(mm->hashmask>>3)+8; hash_entry volatile *p=(hash_entry *) mm->sdr1; /* PTE handling is simple since the processor never update - * the entries. Writable pages always have the C bit set and + * the entries. Writable pages always have the C bit set and * all valid entries have the R bit set. From the processor * point of view the hash table is read only. */ @@ -578,7 +578,7 @@ void vflush(map *virtmap) { void vfree(void *vaddr) { map *physmap, *virtmap; /* Actual mappings pertaining to this vm */ struct _mm_private * mm = (struct _mm_private *) bd->mm_private; - + /* Flush memory queues */ asm volatile("sync": : : "memory"); @@ -588,7 +588,7 @@ void vfree(void *vaddr) { /* Remove mappings corresponding to virtmap */ for (physmap=mm->mappings; physmap; ) { map *nextmap=physmap->next; - if (physmap->base>=virtmap->base + if (physmap->base>=virtmap->base && physmap->base<virtmap->end) { free_map(remove_map(&mm->mappings, physmap)); } @@ -598,22 +598,22 @@ void vfree(void *vaddr) { vflush(virtmap); virtmap->firstpte= MAP_FREE_VIRT; - insert_map(&mm->virtavail, virtmap); + insert_map(&mm->virtavail, virtmap); coalesce_maps(mm->virtavail); } void vunmap(void *vaddr) { map *physmap, *virtmap; /* Actual mappings pertaining to this vm */ struct _mm_private *mm = (struct _mm_private *) bd->mm_private; - + /* Flush memory queues */ asm volatile("sync": : : "memory"); /* vaddr must be within one of the vm areas in use and - * then must correspond to one of the physical areas + * then must correspond to one of the physical areas */ for (virtmap=mm->virtused; virtmap; virtmap=virtmap->next) { - if (virtmap->base<=(u_long)vaddr && + if (virtmap->base<=(u_long)vaddr && virtmap->end>=(u_long)vaddr) break; } if (!virtmap) return; @@ -632,7 +632,7 @@ int vmap(void *vaddr, u_long p, u_long size) { if(!size) return 1; /* Check that the requested area fits in one vm image */ for (q=mm->virtused; q; q=q->next) { - if ((q->base <= (u_long)vaddr) && + if ((q->base <= (u_long)vaddr) && (q->end>=(u_long)vaddr+size -1)) break; } if (!q) return 1; @@ -673,7 +673,7 @@ void add_free_map(u_long base, u_long end) { q->base=base; q->end=end-1; q->firstpte=MAP_FREE_VIRT; - insert_map(&mm->virtavail, q); + insert_map(&mm->virtavail, q); } static inline @@ -691,10 +691,10 @@ void create_free_vm(void) { } /* Memory management initialization. - * Set up the mapping lists. + * Set up the mapping lists. */ -static inline +static inline void add_perm_map(u_long start, u_long size) { struct _mm_private *mm = (struct _mm_private *) bd->mm_private; map *p=alloc_map(); @@ -704,7 +704,7 @@ void add_perm_map(u_long start, u_long size) { insert_map(& mm->physperm , p); } -void mm_init(u_long image_size) +void mm_init(u_long image_size) { u_long lowpage=ULONG_MAX, highpage; struct _mm_private *mm = (struct _mm_private *) bd->mm_private; @@ -716,7 +716,7 @@ void mm_init(u_long image_size) /* The checks are simplified by the fact that the image * and stack area are always allocated at the upper end - * of a free block. + * of a free block. */ while((highpage = find_next_zone(res, lowpage, BootImage|Free))) { lowpage=find_zone_start(res, highpage, BootImage|Free); @@ -727,7 +727,7 @@ void mm_init(u_long image_size) } if ( (( u_long)bd->stack>>PAGE_SHIFT) == highpage) { highpage -= STACK_PAGES; - add_perm_map(highpage<<PAGE_SHIFT, + add_perm_map(highpage<<PAGE_SHIFT, STACK_PAGES*PAGE_SIZE); } /* Protect the interrupt handlers that we need ! */ @@ -751,8 +751,8 @@ void mm_init(u_long image_size) /* Setup the segment registers as we want them */ for (i=0; i<16; i++) _write_SR(i, (void *)(i<<28)); /* Create the maps for the physical memory, firwmarecode does not - * seem to be necessary. ROM is mapped read-only to reduce the risk - * of reprogramming it because it's often Flash and some are + * seem to be necessary. ROM is mapped read-only to reduce the risk + * of reprogramming it because it's often Flash and some are * amazingly easy to overwrite. */ create_identity_mappings(BootImage|Free|FirmwareCode|FirmwareHeap| @@ -762,14 +762,14 @@ void mm_init(u_long image_size) PCIAddr|PCIConfig|ISAAddr, PTE_IO); create_free_vm(); - + /* Install our own MMU and trap handlers. */ - codemove((void *) 0x300, _handler_glue, 0x100, bd->cache_lsize); - codemove((void *) 0x400, _handler_glue, 0x100, bd->cache_lsize); - codemove((void *) 0x600, _handler_glue, 0x100, bd->cache_lsize); - codemove((void *) 0x700, _handler_glue, 0x100, bd->cache_lsize); + codemove((void *) 0x300, _handler_glue, 0x100, bd->cache_lsize); + codemove((void *) 0x400, _handler_glue, 0x100, bd->cache_lsize); + codemove((void *) 0x600, _handler_glue, 0x100, bd->cache_lsize); + codemove((void *) 0x700, _handler_glue, 0x100, bd->cache_lsize); } - + void * salloc(u_long size) { map *p, *q; struct _mm_private *mm = (struct _mm_private *) bd->mm_private; @@ -816,17 +816,17 @@ void sfree(void *p) { } /* first/last area fit, flags is a power of 2 indicating the required - * alignment. The algorithms are stupid because we expect very little + * alignment. The algorithms are stupid because we expect very little * fragmentation of the areas, if any. The unit of allocation is the page. * The allocation is by default performed from higher addresses down, - * unless flags&PA_LOW is true. + * unless flags&PA_LOW is true. */ -void * __palloc(u_long size, int flags) +void * __palloc(u_long size, int flags) { u_long mask = ((1<<(flags&PA_ALIGN_MASK))-1); map *newmap, *frommap, *p, *splitmap=0; - map **queue; + map **queue; u_long qflags; struct _mm_private *mm = (struct _mm_private *) bd->mm_private; @@ -849,7 +849,7 @@ void * __palloc(u_long size, int flags) } /* We need to allocate that one now so no two allocations may attempt * to take the same memory simultaneously. Alloc_map_page does - * not call back here to avoid infinite recursion in alloc_map. + * not call back here to avoid infinite recursion in alloc_map. */ if (mask&PAGE_MASK) { @@ -868,11 +868,11 @@ void * __palloc(u_long size, int flags) if (!frommap) { if (splitmap) free_map(splitmap); - return NULL; + return NULL; } - + newmap=alloc_map(); - + if (flags&PA_LOW) { newmap->base = (frommap->base+mask)&~mask; } else { @@ -883,7 +883,7 @@ void * __palloc(u_long size, int flags) newmap->firstpte = qflags; /* Add a fragment if we don't allocate until the end. */ - + if (splitmap) { splitmap->base=newmap->base+size; splitmap->end=frommap->end; @@ -904,13 +904,13 @@ void * __palloc(u_long size, int flags) if (splitmap->base == splitmap->end+1) { free_map(remove_map(&mm->physavail, splitmap)); } else { - insert_map(&mm->physavail, splitmap); + insert_map(&mm->physavail, splitmap); } } insert_map(queue, newmap); return (void *) newmap->base; - + } void pfree(void * p) { @@ -923,13 +923,13 @@ void pfree(void * p) { coalesce_maps(mm->physavail); } -#ifdef DEBUG +#ifdef DEBUG /* Debugging functions */ void print_maps(map *chain, const char *s) { map *p; printk("%s",s); for(p=chain; p; p=p->next) { - printk(" %08lx-%08lx: %08lx\n", + printk(" %08lx-%08lx: %08lx\n", p->base, p->end, p->firstpte); } } diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/pci.c b/c/src/lib/libbsp/powerpc/shared/bootloader/pci.c index 6bd25a86c9..8f17d06b46 100644 --- a/c/src/lib/libbsp/powerpc/shared/bootloader/pci.c +++ b/c/src/lib/libbsp/powerpc/shared/bootloader/pci.c @@ -45,7 +45,7 @@ typedef unsigned int u32; typedef struct _pci_resource { struct _pci_resource *next; - struct pci_dev *dev; + struct pci_dev *dev; u_long base; /* will be 64 bits on 64 bits machines */ u_long size; u_char type; /* 1 is I/O else low order 4 bits of the memory type */ @@ -80,9 +80,9 @@ struct _pci_private { pci_area_head io, mem; } pci_private = { - config_addr: NULL, - config_data: (volatile u_char *) 0x80800000, - last_dev_p: NULL, + config_addr: NULL, + config_data: (volatile u_char *) 0x80800000, + last_dev_p: NULL, resources: NULL, io: {NULL, 0xfff, 0}, mem: {NULL, 0xfffff, 0} @@ -100,33 +100,33 @@ struct _pci_private { #endif #if defined(PCI_DEBUG) -static void +static void print_pci_resources(const char *s) { pci_resource *p; printk("%s", s); for (p=pci->resources; p; p=p->next) { /* - printk(" %p:%p %06x %08lx %08lx %d\n", + printk(" %p:%p %06x %08lx %08lx %d\n", p, p->next, (p->dev->devfn<<8)+(p->dev->bus->number<<16) +0x10+p->reg*4, p->base, p->size, - p->type); + p->type); */ - printk(" %p:%p %d:%02x (%04x:%04x) %08lx %08lx %d\n", + printk(" %p:%p %d:%02x (%04x:%04x) %08lx %08lx %d\n", p, p->next, - p->dev->bus->number, PCI_SLOT(p->dev->devfn), + p->dev->bus->number, PCI_SLOT(p->dev->devfn), p->dev->vendor, p->dev->device, p->base, p->size, - p->type); + p->type); } } -static void +static void print_pci_area(pci_area *p) { for (; p; p=p->next) { printk(" %p:%p %p %08lx %08lx\n", @@ -134,7 +134,7 @@ print_pci_area(pci_area *p) { } } -static void +static void print_pci_areas(const char *s) { printk("%s PCI I/O areas:\n",s); print_pci_area(pci->io.head); @@ -142,7 +142,7 @@ print_pci_areas(const char *s) { print_pci_area(pci->mem.head); } #else -#define print_pci_areas(x) +#define print_pci_areas(x) #define print_pci_resources(x) #endif @@ -159,7 +159,7 @@ struct blacklist_entry { }; #define BLACKLIST(vid, did, breg, actual_size) \ - {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##vid##_##did, breg, actual_size} + {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##vid##_##did, breg, actual_size} static struct blacklist_entry blacklist[] = { BLACKLIST(S3, TRIO, 0, 0x04000000), @@ -168,7 +168,7 @@ static struct blacklist_entry blacklist[] = { /* This function filters resources and then inserts them into a list of - * configurable pci resources. + * configurable pci resources. */ @@ -180,7 +180,7 @@ static struct blacklist_entry blacklist[] = { static int insert_before(pci_resource *e, pci_resource *t) { - if (e->dev->bus->number != t->dev->bus->number) + if (e->dev->bus->number != t->dev->bus->number) return e->dev->bus->number > t->dev->bus->number; if (AREA(e) != AREA(t)) return AREA(e)<AREA(t); return (e->size > t->size); @@ -195,8 +195,8 @@ static void insert_resource(pci_resource *r) { pci_resource *p; if (!r) return; - /* First fixup in case we have a blacklist entry. Note that this - * may temporarily leave a resource in an inconsistent state: with + /* First fixup in case we have a blacklist entry. Note that this + * may temporarily leave a resource in an inconsistent state: with * (base & (size-1)) !=0. This is harmless. */ for (b=blacklist; b->vendor!=0xffff; b++) { @@ -207,13 +207,13 @@ static void insert_resource(pci_resource *r) { break; } } - + /* Motorola NT firmware does not configure pci devices which are not * required for booting, others do. For now: * - allocated devices in the ISA range (64kB I/O, 16Mb memory) * but non zero base registers are left as is. - * - all other registers, whether already allocated or not, are - * reallocated unless they require an inordinate amount of + * - all other registers, whether already allocated or not, are + * reallocated unless they require an inordinate amount of * resources (>256 Mb for memory >64kB for I/O). These * devices with too large mapping requirements are simply ignored * and their bases are set to 0. This should disable the @@ -233,37 +233,37 @@ static void insert_resource(pci_resource *r) { ** the hardware, we are stuck with the kludge below. Note that ** everything is remapped on the CPCI backplane and any downstream ** hardware, its just the builtin stuff we're tiptoeing around. - ** + ** ** Gregm, 7/16/2003 */ if( r->dev->bus->number <= 1 ) { - if ((r->type==PCI_BASE_ADDRESS_SPACE_IO) + if ((r->type==PCI_BASE_ADDRESS_SPACE_IO) ? (r->base && r->base <0x10000) : (r->base && r->base <0x1000000)) { #ifdef PCI_DEBUG - printk("freeing region; %p:%p %d:%02x (%04x:%04x) %08lx %08lx %d\n", + printk("freeing region; %p:%p %d:%02x (%04x:%04x) %08lx %08lx %d\n", r, r->next, - r->dev->bus->number, PCI_SLOT(r->dev->devfn), + r->dev->bus->number, PCI_SLOT(r->dev->devfn), r->dev->vendor, r->dev->device, r->base, r->size, - r->type); + r->type); #endif sfree(r); return; } } - if ((r->type==PCI_BASE_ADDRESS_SPACE_IO) + if ((r->type==PCI_BASE_ADDRESS_SPACE_IO) ? (r->size >= 0x10000) : (r->size >= 0x10000000)) { r->size = 0; r->base = 0; } - /* Now insert into the list sorting by + /* Now insert into the list sorting by * 1) decreasing bus number * 2) space: prefetchable memory, non-prefetchable and finally I/O * 3) decreasing size @@ -284,21 +284,21 @@ static void insert_resource(pci_resource *r) { -/* This version only works for bus 0. I don't have any P2P bridges to test +/* This version only works for bus 0. I don't have any P2P bridges to test * a more sophisticated version which has therefore not been implemented. * Prefetchable memory is not yet handled correctly either. * And several levels of PCI bridges much less even since there must be - * allocated together to be able to setup correctly the top bridge. + * allocated together to be able to setup correctly the top bridge. */ -static u_long find_range(u_char bus, u_char type, +static u_long find_range(u_char bus, u_char type, pci_resource **first, pci_resource **past, u_int *flags) { pci_resource *p; u_long total=0; u_int fl=0; - for (p=pci->resources; p; p=p->next) + for (p=pci->resources; p; p=p->next) { if ((p->dev->bus->number == bus) && AREA(p)==type) break; @@ -306,12 +306,12 @@ static u_long find_range(u_char bus, u_char type, *first = p; - for (; p; p=p->next) + for (; p; p=p->next) { if ((p->dev->bus->number != bus) || AREA(p)!=type || p->size == 0) break; total = total+p->size; - fl |= 1<<p->type; + fl |= 1<<p->type; } *past = p; @@ -328,7 +328,7 @@ static u_long find_range(u_char bus, u_char type, -static inline void init_free_area(pci_area_head *h, u_long start, +static inline void init_free_area(pci_area_head *h, u_long start, u_long end, u_int mask, int high) { pci_area *p; p = salloc(sizeof(pci_area)); @@ -376,12 +376,12 @@ static void insert_area(pci_area_head *h, pci_area *p) { static -void remove_area(pci_area_head *h, pci_area *p) +void remove_area(pci_area_head *h, pci_area *p) { pci_area *q = h->head; if (!p || !q) return; - if (q==p) + if (q==p) { h->head = q->next; return; @@ -401,7 +401,7 @@ static pci_area * alloc_area(pci_area_head *h, struct pci_bus *bus, pci_area *from, *split, *new; required = (required+h->mask) & ~h->mask; - for (p=h->head, from=NULL; p; p=p->next) + for (p=h->head, from=NULL; p; p=p->next) { u_long l1 = ((p->start+required+mask)&~mask)-1; u_long l2 = ((p->start+mask)&~mask)+required-1; @@ -417,41 +417,41 @@ static pci_area * alloc_area(pci_area_head *h, struct pci_bus *bus, /* If allocation of new succeeds then allocation of split has * also been successful (given the current mm algorithms) ! */ - if (!new) { - sfree(split); - return NULL; + if (!new) { + sfree(split); + return NULL; } new->bus = bus; new->flags = flags; /* Now allocate pci_space taking alignment into account ! */ - if (h->high) + if (h->high) { u_long l1 = ((from->end+1)&~mask)-required; - u_long l2 = (from->end+1-required)&~mask; + u_long l2 = (from->end+1-required)&~mask; new->start = (l1>l2) ? l1 : l2; split->end = from->end; from->end = new->start-1; split->start = new->start+required; new->end = new->start+required-1; - } - else + } + else { u_long l1 = ((from->start+mask)&~mask)+required-1; - u_long l2 = ((from->start+required+mask)&~mask)-1; + u_long l2 = ((from->start+required+mask)&~mask)-1; new->end = (l1<l2) ? l1 : l2; split->start = from->start; from->start = new->end+1; new->start = new->end+1-required; split->end = new->start-1; } - + if (from->end+1 == from->start) remove_area(h, from); - if (split->end+1 != split->start) + if (split->end+1 != split->start) { split->bus = NULL; insert_area(h, split); - } - else + } + else { sfree(split); } @@ -465,7 +465,7 @@ static pci_area * alloc_area(pci_area_head *h, struct pci_bus *bus, static inline -void alloc_space(pci_area *p, pci_resource *r) +void alloc_space(pci_area *p, pci_resource *r) { if (p->start & (r->size-1)) { r->base = p->end+1-r->size; @@ -480,7 +480,7 @@ void alloc_space(pci_area *p, pci_resource *r) -static void reconfigure_bus_space(u_char bus, u_char type, pci_area_head *h) +static void reconfigure_bus_space(u_char bus, u_char type, pci_area_head *h) { pci_resource *first, *past, *r; pci_area *area, tmp; @@ -494,7 +494,7 @@ static void reconfigure_bus_space(u_char bus, u_char type, pci_area_head *h) if (!area) return; tmp = *area; - for (r=first; r!=past; r=r->next) + for (r=first; r!=past; r=r->next) { alloc_space(&tmp, r); } @@ -537,8 +537,8 @@ static void reconfigure_pci(void) { /* First reconfigure the I/O space, this will be more - * complex when there is more than 1 bus. And 64 bits - * devices are another kind of problems. + * complex when there is more than 1 bus. And 64 bits + * devices are another kind of problems. */ reconfigure_bus_space(0, PCI_AREA_IO, &pci->io); reconfigure_bus_space(0, PCI_AREA_MEMORY, &pci->mem); @@ -546,7 +546,7 @@ static void reconfigure_pci(void) { /* Now we have to touch the configuration space of all * the devices to remap them better than they are right now. - * This is done in 3 steps: + * This is done in 3 steps: * 1) first disable I/O and memory response of all devices * 2) modify the base registers * 3) restore the original PCI_COMMAND register. @@ -562,12 +562,12 @@ static void reconfigure_pci(void) { } for (r=pci->resources; r; r= r->next) { - pci_write_config_dword(r->dev, + pci_write_config_dword(r->dev, PCI_BASE_ADDRESS_0+(r->reg<<2), r->base); if ((r->type& (PCI_BASE_ADDRESS_SPACE| - PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == + PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == (PCI_BASE_ADDRESS_SPACE_MEMORY| PCI_BASE_ADDRESS_MEM_TYPE_64)) { pci_write_config_dword(r->dev, @@ -592,60 +592,60 @@ static void reconfigure_pci(void) { static int -indirect_pci_read_config_byte(unsigned char bus, unsigned char dev_fn, +indirect_pci_read_config_byte(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned char *val) { - out_be32(pci->config_addr, + out_be32(pci->config_addr, 0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24)); *val=in_8(pci->config_data + (offset&3)); return PCIBIOS_SUCCESSFUL; } static int -indirect_pci_read_config_word(unsigned char bus, unsigned char dev_fn, +indirect_pci_read_config_word(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned short *val) { - *val = 0xffff; + *val = 0xffff; if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; - out_be32(pci->config_addr, + out_be32(pci->config_addr, 0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24)); *val=in_le16((volatile u_short *)(pci->config_data + (offset&3))); return PCIBIOS_SUCCESSFUL; } static int -indirect_pci_read_config_dword(unsigned char bus, unsigned char dev_fn, +indirect_pci_read_config_dword(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned int *val) { - *val = 0xffffffff; + *val = 0xffffffff; if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; - out_be32(pci->config_addr, + out_be32(pci->config_addr, 0x80|(bus<<8)|(dev_fn<<16)|(offset<<24)); *val=in_le32((volatile u_int *)pci->config_data); return PCIBIOS_SUCCESSFUL; } static int -indirect_pci_write_config_byte(unsigned char bus, unsigned char dev_fn, +indirect_pci_write_config_byte(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned char val) { - out_be32(pci->config_addr, + out_be32(pci->config_addr, 0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24)); out_8(pci->config_data + (offset&3), val); return PCIBIOS_SUCCESSFUL; } static int -indirect_pci_write_config_word(unsigned char bus, unsigned char dev_fn, +indirect_pci_write_config_word(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned short val) { if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; - out_be32(pci->config_addr, + out_be32(pci->config_addr, 0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24)); out_le16((volatile u_short *)(pci->config_data + (offset&3)), val); return PCIBIOS_SUCCESSFUL; } static int -indirect_pci_write_config_dword(unsigned char bus, unsigned char dev_fn, +indirect_pci_write_config_dword(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned int val) { if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; - out_be32(pci->config_addr, + out_be32(pci->config_addr, 0x80|(bus<<8)|(dev_fn<<16)|(offset<<24)); out_le32((volatile u_int *)pci->config_data, val); return PCIBIOS_SUCCESSFUL; @@ -662,21 +662,21 @@ static const struct pci_config_access_functions indirect_functions = { static int -direct_pci_read_config_byte(unsigned char bus, unsigned char dev_fn, +direct_pci_read_config_byte(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned char *val) { if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) { *val=0xff; return PCIBIOS_DEVICE_NOT_FOUND; } - *val=in_8(pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1) + *val=in_8(pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1) + (PCI_FUNC(dev_fn)<<8) + offset); return PCIBIOS_SUCCESSFUL; } static int -direct_pci_read_config_word(unsigned char bus, unsigned char dev_fn, +direct_pci_read_config_word(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned short *val) { - *val = 0xffff; + *val = 0xffff; if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) { return PCIBIOS_DEVICE_NOT_FOUND; @@ -688,9 +688,9 @@ direct_pci_read_config_word(unsigned char bus, unsigned char dev_fn, } static int -direct_pci_read_config_dword(unsigned char bus, unsigned char dev_fn, +direct_pci_read_config_dword(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned int *val) { - *val = 0xffffffff; + *val = 0xffffffff; if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) { return PCIBIOS_DEVICE_NOT_FOUND; @@ -702,19 +702,19 @@ direct_pci_read_config_dword(unsigned char bus, unsigned char dev_fn, } static int -direct_pci_write_config_byte(unsigned char bus, unsigned char dev_fn, +direct_pci_write_config_byte(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned char val) { if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) { return PCIBIOS_DEVICE_NOT_FOUND; } - out_8(pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1) - + (PCI_FUNC(dev_fn)<<8) + offset, + out_8(pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1) + + (PCI_FUNC(dev_fn)<<8) + offset, val); return PCIBIOS_SUCCESSFUL; } static int -direct_pci_write_config_word(unsigned char bus, unsigned char dev_fn, +direct_pci_write_config_word(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned short val) { if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) { @@ -728,7 +728,7 @@ direct_pci_write_config_word(unsigned char bus, unsigned char dev_fn, } static int -direct_pci_write_config_dword(unsigned char bus, unsigned char dev_fn, +direct_pci_write_config_dword(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned int val) { if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) { @@ -765,35 +765,35 @@ void pci_read_bases(struct pci_dev *dev, unsigned int howmany) u32 l, ml; pci_read_config_word(dev, PCI_COMMAND, &cmd); - for(reg=0; reg<howmany; reg=nextreg) + for(reg=0; reg<howmany; reg=nextreg) { pci_resource *r; nextreg=reg+1; pci_read_config_dword(dev, REG, &l); #if 0 - if (l == 0xffffffff /*AJF || !l*/) continue; + if (l == 0xffffffff /*AJF || !l*/) continue; #endif - /* Note that disabling the memory response of a host bridge - * would lose data if a DMA transfer were in progress. In a - * bootloader we don't care however. Also we can't print any + /* Note that disabling the memory response of a host bridge + * would lose data if a DMA transfer were in progress. In a + * bootloader we don't care however. Also we can't print any * message for a while since we might just disable the console. */ - pci_write_config_word(dev, PCI_COMMAND, cmd & + pci_write_config_word(dev, PCI_COMMAND, cmd & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)); pci_write_config_dword(dev, REG, ~0); pci_read_config_dword(dev, REG, &ml); pci_write_config_dword(dev, REG, l); - /* Reenable the device now that we've played with - * base registers. + /* Reenable the device now that we've played with + * base registers. */ pci_write_config_word(dev, PCI_COMMAND, cmd); /* seems to be an unused entry skip it */ if ( ml == 0 || ml == 0xffffffff ) continue; - if ((l & + if ((l & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == (PCI_BASE_ADDRESS_MEM_TYPE_64 |PCI_BASE_ADDRESS_SPACE_MEMORY)) { @@ -864,7 +864,7 @@ u_int pci_scan_bus(struct pci_bus *bus) dev->vendor = l & 0xffff; dev->device = (l >> 16) & 0xffff; - pcibios_read_config_dword(bus->number, devfn, + pcibios_read_config_dword(bus->number, devfn, PCI_CLASS_REVISION, &class); class >>= 8; /* upper 3 bytes */ dev->class = class; @@ -1030,14 +1030,14 @@ u_int pci_scan_bus(struct pci_bus *bus) #if 0 void -pci_fixup(void) +pci_fixup(void) { struct pci_dev *p; struct pci_bus *bus; - for (bus = &pci_root; bus; bus=bus->next) + for (bus = &pci_root; bus; bus=bus->next) { - for (p=bus->devices; p; p=p->sibling) + for (p=bus->devices; p; p=p->sibling) { } } @@ -1059,7 +1059,7 @@ static void print_pci_info() for(pb= &pci_root; pb; pb=pb->children ) { printk(" number %d, primary %d, secondary %d, subordinate %d\n", - pb->number, + pb->number, pb->primary, pb->secondary, pb->subordinate ); @@ -1076,7 +1076,7 @@ static void print_pci_info() pd->vendor, pd->device, pd->irq ); - + } printk("\n"); } @@ -1088,7 +1088,7 @@ static void print_pci_info() for (r=pci->resources; r; r= r->next) { printk(" bus %d, vendor %04x, device %04x, base %08x, size %08x, type %d\n", - r->dev->bus->number, + r->dev->bus->number, r->dev->vendor, r->dev->device, r->base, @@ -1198,9 +1198,9 @@ static void recursive_bus_reconfigure( struct pci_bus *pbus ) childbus->subordinate ); #endif - - /* + + /* **use the current values & the saved ones to figure out ** the address spaces for the bridge */ @@ -1269,7 +1269,7 @@ static void recursive_bus_reconfigure( struct pci_bus *pbus ) printk("pci: pf memory %04x, limit %04x\n", base16, limit16); #endif #ifdef WRITE_BRIDGE_PF - pcibios_write_config_dword(pdev->bus->number, pdev->devfn, PCI_PREF_BASE_UPPER32, 0); + pcibios_write_config_dword(pdev->bus->number, pdev->devfn, PCI_PREF_BASE_UPPER32, 0); pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_PREF_MEMORY_BASE, base16 ); pcibios_write_config_dword(pdev->bus->number, pdev->devfn, PCI_PREF_LIMIT_UPPER32, 0); pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_PREF_MEMORY_LIMIT, limit16 ); @@ -1280,7 +1280,7 @@ static void recursive_bus_reconfigure( struct pci_bus *pbus ) pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_BRIDGE_CONTROL, (uint16_t)( PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR )); - pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_COMMAND, (uint16_t)( PCI_COMMAND_IO | + pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_COMMAND, (uint16_t)( PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | @@ -1351,7 +1351,7 @@ static void recursive_bus_reconfigure( struct pci_bus *pbus ) else { /* memory space */ - + /* shift base pointer up to an integer multiple of the size of the desired region */ if( astart.start_pcimem % r->size ) astart.start_pcimem = (((astart.start_pcimem / r->size) + 1) * r->size); @@ -1379,7 +1379,7 @@ static void recursive_bus_reconfigure( struct pci_bus *pbus ) -void pci_init(void) +void pci_init(void) { PPC_DEVICE *hostbridge; @@ -1388,18 +1388,18 @@ void pci_init(void) return; } pci->last_dev_p = &(bd->pci_devices); - hostbridge=residual_find_device(PROCESSORDEVICE, NULL, + hostbridge=residual_find_device(PROCESSORDEVICE, NULL, BridgeController, PCIBridge, -1, 0); if (hostbridge) { if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) { bd->pci_functions=&indirect_functions; - /* Should be extracted from residual data, + /* Should be extracted from residual data, * indeed MPC106 in CHRP mode is different, * but we should not use residual data in - * this case anyway. + * this case anyway. */ - pci->config_addr = ((volatile u_int *) + pci->config_addr = ((volatile u_int *) (ptr_mem_map->io_base+0xcf8)); pci->config_data = ptr_mem_map->io_base+0xcfc; } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) { @@ -1412,7 +1412,7 @@ void pci_init(void) u_int id0; bd->pci_functions = &direct_functions; /* On all direct bridges I know the host bridge itself - * appears as device 0 function 0. + * appears as device 0 function 0. */ pcibios_read_config_dword(0, 0, PCI_VENDOR_ID, &id0); if (id0==~0U) { diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/pci.h b/c/src/lib/libbsp/powerpc/shared/bootloader/pci.h index caf0c3e12f..3884760c8b 100644 --- a/c/src/lib/libbsp/powerpc/shared/bootloader/pci.h +++ b/c/src/lib/libbsp/powerpc/shared/bootloader/pci.h @@ -42,7 +42,7 @@ #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ -#define PCI_STATUS_DEVSEL_FAST 0x000 +#define PCI_STATUS_DEVSEL_FAST 0x000 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 #define PCI_STATUS_DEVSEL_SLOW 0x400 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ @@ -71,8 +71,8 @@ /* * Base addresses specify locations in memory or I/O space. - * Decoded size can be determined by writing a value of - * 0xffffffff to the register, and reading it back. Only + * Decoded size can be determined by writing a value of + * 0xffffffff to the register, and reading it back. Only * 1 bits are decoded. */ #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ @@ -96,7 +96,7 @@ /* Header type 0 (normal devices) */ #define PCI_CARDBUS_CIS 0x28 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c -#define PCI_SUBSYSTEM_ID 0x2e +#define PCI_SUBSYSTEM_ID 0x2e #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ #define PCI_ROM_ADDRESS_ENABLE 0x01 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) @@ -455,8 +455,8 @@ #define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010 #define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 -#define PCI_VENDOR_ID_DPT 0x1044 -#define PCI_DEVICE_ID_DPT 0xa400 +#define PCI_VENDOR_ID_DPT 0x1044 +#define PCI_DEVICE_ID_DPT 0xa400 #define PCI_VENDOR_ID_OPTI 0x1045 #define PCI_DEVICE_ID_OPTI_92C178 0xc178 @@ -1072,17 +1072,17 @@ /* Functions used to access pci configuration space */ struct pci_config_access_functions { - int (*read_config_byte)(unsigned char, unsigned char, + int (*read_config_byte)(unsigned char, unsigned char, unsigned char, unsigned char *); - int (*read_config_word)(unsigned char, unsigned char, + int (*read_config_word)(unsigned char, unsigned char, unsigned char, unsigned short *); - int (*read_config_dword)(unsigned char, unsigned char, + int (*read_config_dword)(unsigned char, unsigned char, unsigned char, unsigned int *); - int (*write_config_byte)(unsigned char, unsigned char, + int (*write_config_byte)(unsigned char, unsigned char, unsigned char, unsigned char); - int (*write_config_word)(unsigned char, unsigned char, + int (*write_config_word)(unsigned char, unsigned char, unsigned char, unsigned short); - int (*write_config_dword)(unsigned char, unsigned char, + int (*write_config_dword)(unsigned char, unsigned char, unsigned char, unsigned int); }; diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/zlib.c b/c/src/lib/libbsp/powerpc/shared/bootloader/zlib.c index 78ba7867fc..70e97abb6e 100644 --- a/c/src/lib/libbsp/powerpc/shared/bootloader/zlib.c +++ b/c/src/lib/libbsp/powerpc/shared/bootloader/zlib.c @@ -119,7 +119,7 @@ typedef uLong (*check_func) OF((uLong check, Bytef *buf, uInt len)); /* deflate.h -- internal compression state * Copyright (C) 1995 Jean-loup Gailly - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* WARNING: this file should *not* be used by applications. It is @@ -130,7 +130,7 @@ typedef uLong (*check_func) OF((uLong check, Bytef *buf, uInt len)); /*+++++*/ /* infblock.h -- header to use infblock.c * Copyright (C) 1995 Mark Adler - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* WARNING: this file should *not* be used by applications. It is @@ -171,7 +171,7 @@ local int inflate_packet_flush OF(( /*+++++*/ /* inftrees.h -- header to use inftrees.c * Copyright (C) 1995 Mark Adler - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* WARNING: this file should *not* be used by applications. It is @@ -233,7 +233,7 @@ local int inflate_trees_free OF(( /*+++++*/ /* infcodes.h -- header to use infcodes.c * Copyright (C) 1995 Mark Adler - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* WARNING: this file should *not* be used by applications. It is @@ -262,7 +262,7 @@ local void inflate_codes_free OF(( /*+++++*/ /* inflate.c -- zlib interface to inflate modules * Copyright (C) 1995 Mark Adler - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* inflate private state */ @@ -294,7 +294,7 @@ struct internal_state { /* mode independent information */ int nowrap; /* flag for no wrapper */ uInt wbits; /* log2(window size) (8..15, defaults to 15) */ - inflate_blocks_statef + inflate_blocks_statef *blocks; /* current inflate_blocks state */ }; @@ -569,7 +569,7 @@ z_stream *z; /*+++++*/ /* infutil.h -- types and macros common to blocks and codes * Copyright (C) 1995 Mark Adler - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* WARNING: this file should *not* be used by applications. It is @@ -607,7 +607,7 @@ struct inflate_blocks_state { } trees; /* if DTREE, decoding info for trees */ struct { inflate_huft *tl, *td; /* trees to free */ - inflate_codes_statef + inflate_codes_statef *codes; } decode; /* if CODES, current state */ } sub; /* submode */ @@ -665,7 +665,7 @@ local int inflate_flush OF(( /*+++++*/ /* inffast.h -- header to use inffast.c * Copyright (C) 1995 Mark Adler - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* WARNING: this file should *not* be used by applications. It is @@ -685,7 +685,7 @@ local int inflate_fast OF(( /*+++++*/ /* infblock.c -- interpret and process block types to last block * Copyright (C) 1995 Mark Adler - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* Table for deflate from PKZIP's appnote.txt. */ @@ -1133,7 +1133,7 @@ local int inflate_packet_flush(s) /*+++++*/ /* inftrees.c -- generate Huffman trees for efficient decoding * Copyright (C) 1995 Mark Adler - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* simplify the use of the inflate_huft type with some defines */ @@ -1226,7 +1226,7 @@ uIntf *b; /* code lengths in bits (all assumed <= BMAX) */ uInt n; /* number of codes (assumed <= N_MAX) */ uInt s; /* number of simple-valued codes (0..s-1) */ uIntf *d; /* list of base values for non-simple codes */ -uIntf *e; /* list of extra bits for non-simple codes */ +uIntf *e; /* list of extra bits for non-simple codes */ inflate_huft * FAR *t; /* result: starting table */ uIntf *m; /* maximum lookup bits, returns actual */ z_stream *zs; /* for zalloc function */ @@ -1596,14 +1596,14 @@ z_stream *z; /* for zfree function */ q = (--p)->next; ZFREE(z, p, p->word.Nalloc * sizeof(inflate_huft)); p = q; - } + } return Z_OK; } /*+++++*/ /* infcodes.c -- process literals and length/distance pairs * Copyright (C) 1995 Mark Adler - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* simplify the use of the inflate_huft type with some defines */ @@ -1844,7 +1844,7 @@ z_stream *z; /*+++++*/ /* inflate_util.c -- data and routines common to blocks and codes * Copyright (C) 1995 Mark Adler - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* copy as much as possible from the sliding window to the output area */ @@ -1917,7 +1917,7 @@ int r; /*+++++*/ /* inffast.c -- process literals and length/distance pairs fast * Copyright (C) 1995 Mark Adler - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* simplify the use of the inflate_huft type with some defines */ @@ -2078,7 +2078,7 @@ z_stream *z; /*+++++*/ /* zutil.c -- target dependent utility functions for the compression library * Copyright (C) 1995 Jean-loup Gailly. - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* From: zutil.c,v 1.8 1995/05/03 17:27:12 jloup Exp */ @@ -2099,7 +2099,7 @@ char *z_errmsg[] = { /*+++++*/ /* adler32.c -- compute the Adler-32 checksum of a data stream * Copyright (C) 1995 Mark Adler - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* From: adler32.c,v 1.6 1995/05/03 17:27:08 jloup Exp */ diff --git a/c/src/lib/libbsp/powerpc/shared/bootloader/zlib.h b/c/src/lib/libbsp/powerpc/shared/bootloader/zlib.h index 31485f4632..11b040595c 100644 --- a/c/src/lib/libbsp/powerpc/shared/bootloader/zlib.h +++ b/c/src/lib/libbsp/powerpc/shared/bootloader/zlib.h @@ -52,7 +52,7 @@ /* zconf.h -- configuration of the zlib compression library * Copyright (C) 1995 Jean-loup Gailly. - * For conditions of distribution and use, see copyright notice in zlib.h + * For conditions of distribution and use, see copyright notice in zlib.h */ /* From: zconf.h,v 1.12 1995/05/03 17:27:12 jloup Exp */ @@ -145,7 +145,7 @@ typedef uLong FAR uLongf; #define ZLIB_VERSION "0.95P" -/* +/* The 'zlib' compression library provides in-memory compression and decompression functions, including integrity checks of the uncompressed data. This version of the library supports only one compression method @@ -262,7 +262,7 @@ extern char *zlib_version; /* basic functions */ extern int inflateInit OF((z_stream *strm)); -/* +/* Initializes the internal stream state for decompression. The fields zalloc and zfree must be initialized before by the caller. If zalloc and zfree are set to Z_NULL, inflateInit updates them to use default allocation @@ -341,7 +341,7 @@ extern int inflateEnd OF((z_stream *strm)); extern int inflateInit2 OF((z_stream *strm, int windowBits)); -/* +/* This is another version of inflateInit with more compression options. The fields next_out, zalloc and zfree must be initialized before by the caller. @@ -373,7 +373,7 @@ extern int inflateInit2 OF((z_stream *strm, */ extern int inflateSync OF((z_stream *strm)); -/* +/* Skips invalid compressed data until the special marker (see deflate() above) can be found, or until all available input is skipped. No output is provided. diff --git a/c/src/lib/libbsp/powerpc/shared/clock/p_clock.c b/c/src/lib/libbsp/powerpc/shared/clock/p_clock.c index 2cb8ab20b9..fe90a3d01e 100644 --- a/c/src/lib/libbsp/powerpc/shared/clock/p_clock.c +++ b/c/src/lib/libbsp/powerpc/shared/clock/p_clock.c @@ -23,7 +23,7 @@ static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, (rtems_irq_enable)clockOn, (rtems_irq_disable)clockOff, (rtems_irq_is_enabled) clockIsOn}; - + int BSP_disconnect_clock_handler (void) { diff --git a/c/src/lib/libbsp/powerpc/shared/console/console.c b/c/src/lib/libbsp/powerpc/shared/console/console.c index c16084562c..2a3a1d6c60 100644 --- a/c/src/lib/libbsp/powerpc/shared/console/console.c +++ b/c/src/lib/libbsp/powerpc/shared/console/console.c @@ -21,7 +21,7 @@ * * $Id$ */ - + #include <stdlib.h> #include <assert.h> #include <stdlib.h> @@ -97,7 +97,7 @@ console_initialize(rtems_device_major_number major, * Set up TERMIOS */ rtems_termios_initialize (); - + /* * Do device-specific initialization */ @@ -105,7 +105,7 @@ console_initialize(rtems_device_major_number major, /* RTEMS calls this routine once with 'minor'==0; loop through * all known instances... */ - + for (minor=0; minor < sizeof(ttyS)/sizeof(ttyS[0]); minor++) { char *nm; /* @@ -173,7 +173,7 @@ console_open(rtems_device_major_number major, void *arg) { rtems_status_code status; - static rtems_termios_callbacks cb = + static rtems_termios_callbacks cb = { console_first_open, /* firstOpen */ console_last_close, /* lastClose */ @@ -196,7 +196,7 @@ console_open(rtems_device_major_number major, /* * Pass data area info down to driver */ - BSP_uart_termios_set(minor, + BSP_uart_termios_set(minor, ((rtems_libio_open_close_args_t *)arg)->iop->data1); /* Enable interrupts on channel */ BSP_uart_intr_ctrl(minor, BSP_UART_INTR_CTRL_TERMIOS); @@ -215,11 +215,11 @@ console_close(rtems_device_major_number major, rtems_device_driver res = RTEMS_SUCCESSFUL; res = rtems_termios_close (arg); - + return res; } /* console_close */ - + /*-------------------------------------------------------------------------+ | Console device driver READ entry point. +--------------------------------------------------------------------------+ @@ -233,7 +233,7 @@ console_read(rtems_device_major_number major, return rtems_termios_read (arg); } /* console_read */ - + /*-------------------------------------------------------------------------+ | Console device driver WRITE entry point. @@ -247,20 +247,20 @@ console_write(rtems_device_major_number major, { return rtems_termios_write (arg); - + } /* console_write */ - + /* * Handle ioctl request. */ -rtems_device_driver +rtems_device_driver console_control(rtems_device_major_number major, rtems_device_minor_number minor, void *arg ) -{ +{ /* does the BSP support break callbacks ? */ #if defined(BIOCSETBREAKCB) && defined(BIOCGETBREAKCB) rtems_libio_ioctl_args_t *ioa=arg; @@ -269,7 +269,7 @@ rtems_libio_ioctl_args_t *ioa=arg; return BSP_uart_set_break_cb(minor, ioa); case BIOCGETBREAKCB: return BSP_uart_get_break_cb(minor, ioa); - + default: break; } @@ -282,45 +282,45 @@ conSetAttr(int minor, const struct termios *t) { int baud; - switch (t->c_cflag & CBAUD) + switch (t->c_cflag & CBAUD) { - case B50: + case B50: baud = 50; break; - case B75: - baud = 75; + case B75: + baud = 75; break; - case B110: - baud = 110; + case B110: + baud = 110; break; - case B134: - baud = 134; + case B134: + baud = 134; break; - case B150: - baud = 150; + case B150: + baud = 150; break; case B200: - baud = 200; + baud = 200; break; - case B300: + case B300: baud = 300; break; - case B600: - baud = 600; + case B600: + baud = 600; break; - case B1200: + case B1200: baud = 1200; break; - case B1800: - baud = 1800; + case B1800: + baud = 1800; break; - case B2400: + case B2400: baud = 2400; break; - case B4800: + case B4800: baud = 4800; break; - case B9600: + case B9600: baud = 9600; break; case B19200: @@ -329,7 +329,7 @@ conSetAttr(int minor, const struct termios *t) case B38400: baud = 38400; break; - case B57600: + case B57600: baud = 57600; break; case B115200: diff --git a/c/src/lib/libbsp/powerpc/shared/console/inch.c b/c/src/lib/libbsp/powerpc/shared/console/inch.c index f92ed2e21e..4b30a22978 100644 --- a/c/src/lib/libbsp/powerpc/shared/console/inch.c +++ b/c/src/lib/libbsp/powerpc/shared/console/inch.c @@ -56,7 +56,7 @@ static char shift_map[] = '*',0x80,' ',0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80, 0x80,0x80,0x80,0x80,'7','8','9',0x80,'4','5','6',0x80, '1','2','3','0',177 -}; /* Keyboard scancode -> character map with SHIFT key modifier. */ +}; /* Keyboard scancode -> character map with SHIFT key modifier. */ static char kbd_buffer[KBD_BUF_SIZE]; static uint16_t kbd_first = 0; @@ -152,7 +152,7 @@ _IBMPC_scankey(char *outChar) break; case 0x53: - if (ctrl_pressed && alt_pressed) + if (ctrl_pressed && alt_pressed) rtemsReboot(); /* ctrl+alt+del -> reboot */ break; @@ -251,11 +251,11 @@ _IBMPC_inch(void) return c; } /* _IBMPC_inch */ - + /* * Routine that can be used before interrupt management is initialized. */ - + char BSP_wait_polled_input(void) { @@ -268,7 +268,7 @@ BSP_wait_polled_input(void) /*-------------------------------------------------------------------------+ | Function: _IBMPC_inch_sleep -| Description: If charcter is ready return it, otherwise sleep until +| Description: If charcter is ready return it, otherwise sleep until | it is ready | Global Variables: None. | Arguments: None. @@ -288,14 +288,14 @@ _IBMPC_inch_sleep(void) { return c; } - + if(ticks_per_second == 0) { - rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND, + rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND, &ticks_per_second); } rtems_task_wake_after((ticks_per_second+24)/25); } - + return c; } /* _IBMPC_inch */ diff --git a/c/src/lib/libbsp/powerpc/shared/console/polled_io.c b/c/src/lib/libbsp/powerpc/shared/console/polled_io.c index b2958098b7..7172e8d222 100644 --- a/c/src/lib/libbsp/powerpc/shared/console/polled_io.c +++ b/c/src/lib/libbsp/powerpc/shared/console/polled_io.c @@ -205,34 +205,34 @@ unsigned int keymap_count = 7; */ char func_buf[] = { - '\033', '[', '[', 'A', 0, - '\033', '[', '[', 'B', 0, - '\033', '[', '[', 'C', 0, - '\033', '[', '[', 'D', 0, - '\033', '[', '[', 'E', 0, - '\033', '[', '1', '7', '~', 0, - '\033', '[', '1', '8', '~', 0, - '\033', '[', '1', '9', '~', 0, - '\033', '[', '2', '0', '~', 0, - '\033', '[', '2', '1', '~', 0, - '\033', '[', '2', '3', '~', 0, - '\033', '[', '2', '4', '~', 0, - '\033', '[', '2', '5', '~', 0, - '\033', '[', '2', '6', '~', 0, - '\033', '[', '2', '8', '~', 0, - '\033', '[', '2', '9', '~', 0, - '\033', '[', '3', '1', '~', 0, - '\033', '[', '3', '2', '~', 0, - '\033', '[', '3', '3', '~', 0, - '\033', '[', '3', '4', '~', 0, - '\033', '[', '1', '~', 0, - '\033', '[', '2', '~', 0, - '\033', '[', '3', '~', 0, - '\033', '[', '4', '~', 0, - '\033', '[', '5', '~', 0, - '\033', '[', '6', '~', 0, - '\033', '[', 'M', 0, - '\033', '[', 'P', 0, + '\033', '[', '[', 'A', 0, + '\033', '[', '[', 'B', 0, + '\033', '[', '[', 'C', 0, + '\033', '[', '[', 'D', 0, + '\033', '[', '[', 'E', 0, + '\033', '[', '1', '7', '~', 0, + '\033', '[', '1', '8', '~', 0, + '\033', '[', '1', '9', '~', 0, + '\033', '[', '2', '0', '~', 0, + '\033', '[', '2', '1', '~', 0, + '\033', '[', '2', '3', '~', 0, + '\033', '[', '2', '4', '~', 0, + '\033', '[', '2', '5', '~', 0, + '\033', '[', '2', '6', '~', 0, + '\033', '[', '2', '8', '~', 0, + '\033', '[', '2', '9', '~', 0, + '\033', '[', '3', '1', '~', 0, + '\033', '[', '3', '2', '~', 0, + '\033', '[', '3', '3', '~', 0, + '\033', '[', '3', '4', '~', 0, + '\033', '[', '1', '~', 0, + '\033', '[', '2', '~', 0, + '\033', '[', '3', '~', 0, + '\033', '[', '4', '~', 0, + '\033', '[', '5', '~', 0, + '\033', '[', '6', '~', 0, + '\033', '[', 'M', 0, + '\033', '[', 'P', 0, }; char *funcbufptr = func_buf; @@ -320,7 +320,7 @@ unsigned int accent_table_size = 68; /* These #defines have been copied from drivers/char/pc_keyb.h, by - * Martin Mares (mj@ucw.cz). + * Martin Mares (mj@ucw.cz). * converted to offsets by Till Straumann <strauman@slac.stanford.edu> */ #define KBD_STATUS_REG 0x4 /* Status register (R) */ @@ -385,7 +385,7 @@ SPR_RO(PVR) #endif /* USE_KBD_SUPPORT */ -/* Early messages after mm init but before console init are kept in log +/* Early messages after mm init but before console init are kept in log * buffers. */ #define PAGE_LOG_CHARS (PAGE_SIZE-sizeof(int)-sizeof(u_long)-1) @@ -509,7 +509,7 @@ static void pfree(void* p) --global_index; } #endif - + void log_putc(const u_char c) { console_log *l; @@ -519,11 +519,11 @@ void log_putc(const u_char c) { if (!l) { l=__palloc(sizeof(console_log)); memset(l, 0, sizeof(console_log)); - if (!console_global_data.log) + if (!console_global_data.log) console_global_data.log = l; else { console_log *p; - for (p=console_global_data.log; + for (p=console_global_data.log; p->next; p=p->next); p->next = l; } @@ -534,7 +534,7 @@ void log_putc(const u_char c) { /* This puts is non standard since it does not automatically add a newline * at the end. So it is made private to avoid confusion in other files. */ -static +static void puts(const u_char *s) { char c; @@ -549,10 +549,10 @@ static void flush_log(void) { console_log *p, *next; if (console_global_data.vacuum_sent) { -#ifdef TRACE_FLUSH_LOG - printk("%d characters sent into oblivion before MM init!\n", +#ifdef TRACE_FLUSH_LOG + printk("%d characters sent into oblivion before MM init!\n", console_global_data.vacuum_sent); -#endif +#endif } for(p=console_global_data.log; p; p=next) { puts(p->data); @@ -570,7 +570,7 @@ void serial_putc(const u_char c) while ((INL_CONSOLE_INB(lsr) & LSR_THRE) == 0) ; INL_CONSOLE_OUTB(thr, c); } - + int serial_getc(void) { while ((INL_CONSOLE_INB(lsr) & LSR_DR) == 0) ; @@ -587,16 +587,16 @@ static void scroll(void) { int i; - memcpy ( (u_char *)vidmem, (u_char *)vidmem + console_global_data.cols * 2, + memcpy ( (u_char *)vidmem, (u_char *)vidmem + console_global_data.cols * 2, ( console_global_data.lines - 1 ) * console_global_data.cols * 2 ); - for ( i = ( console_global_data.lines - 1 ) * console_global_data.cols * 2; - i < console_global_data.lines * console_global_data.cols * 2; + for ( i = ( console_global_data.lines - 1 ) * console_global_data.cols * 2; + i < console_global_data.lines * console_global_data.cols * 2; i += 2 ) vidmem[i] = ' '; } /* - * cursor() sets an offset (0-1999) into the 80x25 text area + * cursor() sets an offset (0-1999) into the 80x25 text area */ static void cursor(int x, int y) @@ -608,7 +608,7 @@ cursor(int x, int y) vga_outb(0x15, pos); } -void +void vga_putc(const u_char c) { int x,y; @@ -628,7 +628,7 @@ vga_putc(const u_char c) } else if (c == '\r') { x = 0; } else { - vidmem [ ( x + console_global_data.cols * y ) * 2 ] = c; + vidmem [ ( x + console_global_data.cols * y ) * 2 ] = c; if ( ++x >= console_global_data.cols ) { x = 0; if ( ++y >= console_global_data.lines ) { @@ -765,7 +765,7 @@ static int kbd_get(int ms) { else return data; } - if (--ms < 0) return -1; + if (--ms < 0) return -1; #ifdef __BOOT__ boot_udelay(1000); #else @@ -776,7 +776,7 @@ static int kbd_get(int ms) { static void kbd_put(u_char c, int ms, int port) { while (kbd_inb(KBD_STATUS_REG) & KBD_STAT_IBF) { - if (--ms < 0) return; + if (--ms < 0) return; #ifdef __BOOT__ boot_udelay(1000); #else @@ -800,14 +800,14 @@ int kbdreset(void) /* Enable then reset the KB */ kbd_put(KBD_CCMD_KBD_ENABLE, 10, KBD_CNTL_REG); - + while (1) { kbd_put(KBD_CMD_RESET, 10, KBD_DATA_REG); c = kbd_get(1000); if (c == KBD_REPLY_ACK) break; if (c != KBD_REPLY_RESEND) return 2; } - + if (kbd_get(1000) != KBD_REPLY_POR) return 3; /* Disable the keyboard while setting up the controller */ @@ -816,7 +816,7 @@ int kbdreset(void) /* Enable interrupts and keyboard controller */ kbd_put(KBD_CCMD_WRITE_MODE, 10, KBD_CNTL_REG); - kbd_put(KBD_MODE_KBD_INT | KBD_MODE_SYS | + kbd_put(KBD_MODE_KBD_INT | KBD_MODE_SYS | KBD_MODE_DISABLE_MOUSE | KBD_MODE_KCC, 10, KBD_DATA_REG); @@ -833,30 +833,30 @@ int kbd_tstc(void) } #endif /* USE_KBD_SUPPORT */ -const struct console_io +const struct console_io vacuum_console_functions = { - vacuum_putc, - vacuum_getc, + vacuum_putc, + vacuum_getc, vacuum_tstc }; static const struct console_io log_console_functions = { - log_putc, - vacuum_getc, + log_putc, + vacuum_getc, vacuum_tstc } , serial_console_functions = { - serial_putc, - serial_getc, + serial_putc, + serial_getc, serial_tstc } #if defined(USE_KBD_SUPPORT) && defined(USE_VGA_SUPPORT) , vga_console_functions = { - vga_putc, - kbd_getc, + vga_putc, + kbd_getc, kbd_tstc } #endif @@ -866,7 +866,7 @@ console_io* curIo = (console_io*) &vacuum_console_functions; int select_console(ioType t) { static ioType curType = CONSOLE_VACUUM; - + switch (t) { case CONSOLE_VACUUM : curIo = (console_io*)&vacuum_console_functions; break; case CONSOLE_LOG : curIo = (console_io*)&log_console_functions; break; @@ -909,7 +909,7 @@ int printk(const char *fmt, ...) { int i; /* Should not be a problem with 8kB of stack */ char buf[1024]; - + va_start(args, fmt); i = k_vsprintf(buf, fmt, args); va_end(args); @@ -947,7 +947,7 @@ do { u32 t1, t2, t3; \ "=r" (num), "=&r" (t1), "=&r" (t2), "=&r"(t3), "=&b" (rmd) : \ "0" (num)); \ \ -} while(0); +} while(0); #define SIGN 1 /* unsigned/signed long */ #define LARGE 2 /* use 'ABCDEF' instead of 'abcdef' */ @@ -974,7 +974,7 @@ static char * number(char * str, int size, int type, u64 num) sign = '-'; num = -num; size--; - } + } } i = 0; @@ -988,7 +988,7 @@ static char * number(char * str, int size, int type, u64 num) } tmp[i++] = digits[rem]; } while (num != 0); - + size -= i; if (!(type&(ZEROPAD))) while(size-->0) @@ -1022,14 +1022,14 @@ int k_vsprintf(char *buf, const char *fmt, va_list args) *str++ = *fmt; continue; } - + /* process flags, only 0 padding needed */ flags = 0; if (*++fmt == '0' ) { flags |= ZEROPAD; fmt++; } - + /* get field width */ field_width = -1; if (is_digit(*fmt)) @@ -1092,14 +1092,14 @@ int k_vsprintf(char *buf, const char *fmt, va_list args) --fmt; continue; } - /* This ugly code tries to minimize the number of va_arg() - * since they expand to a lot of code on PPC under the SYSV - * calling conventions (but not with -mcall-aix which has + /* This ugly code tries to minimize the number of va_arg() + * since they expand to a lot of code on PPC under the SYSV + * calling conventions (but not with -mcall-aix which has * other problems). Arguments have at least the size of a * long allocated, and we use this fact to minimize bloat. * (and pointers are assimilated to unsigned long too). */ - if (sizeof(long long) > sizeof(long) && flags & LLONG) + if (sizeof(long long) > sizeof(long) && flags & LLONG) num = va_arg(args, unsigned long long); else { u_long n = va_arg(args, unsigned long); @@ -1109,10 +1109,10 @@ int k_vsprintf(char *buf, const char *fmt, va_list args) else n = (unsigned short) n; } else if (! flags & LONG) { - /* Here the compiler correctly removes this + /* Here the compiler correctly removes this * do nothing code on 32 bit PPC. */ - if (flags & SIGN) + if (flags & SIGN) n = (int) n; else n = (unsigned) n; diff --git a/c/src/lib/libbsp/powerpc/shared/console/uart.c b/c/src/lib/libbsp/powerpc/shared/console/uart.c index 5bdf8e110b..7fb5597873 100644 --- a/c/src/lib/libbsp/powerpc/shared/console/uart.c +++ b/c/src/lib/libbsp/powerpc/shared/console/uart.c @@ -57,10 +57,10 @@ static struct uart_data uart_data[2] = { #define MAX_UARTS (sizeof(uart_data)/sizeof(uart_data[0])) #define SANITY_CHECK(uart) \ assert( MAX_UARTS > (unsigned)(uart) && uart_data[(uart)].ioBase != UART_UNSUPP ) -/* +/* * Macros to read/wirte register of uart, if configuration is * different just rewrite these macros - */ + */ static inline unsigned char uread(int uart, unsigned int reg) @@ -70,7 +70,7 @@ uread(int uart, unsigned int reg) } -static inline void +static inline void uwrite(int uart, int reg, unsigned int val) { out_8((unsigned char*)(uart_data[uart].ioBase + reg), val); @@ -111,7 +111,7 @@ inline void uartError(int uart, void *termiosPrivate) { unsigned char uartStatus,dummy; BSP_UartBreakCbProc h; - + uartStatus = uread(uart, LSR); dummy = uread(uart, RBR); if ((uartStatus & BI) && (h=uart_data[uart].breakCallback.handler)) @@ -122,7 +122,7 @@ inline void uartError(int uart, void *termiosPrivate) } #endif -/* +/* * Uart initialization, it is hardcoded to 8 bit, no parity, * one stop bit, FIFO, things to be changed * are baud rate and nad hw flow control, @@ -132,10 +132,10 @@ void BSP_uart_init(int uart, int baud, int hwFlow) { unsigned char tmp; - + /* Sanity check */ SANITY_CHECK(uart); - + switch(baud) { case 50: @@ -156,23 +156,23 @@ BSP_uart_init(int uart, int baud, int hwFlow) assert(0); return; } - + /* Set DLAB bit to 1 */ uwrite(uart, LCR, DLAB); - + /* Set baud rate */ - uwrite(uart, DLL, (BSPBaseBaud/baud) & 0xff); - uwrite(uart, DLM, ((BSPBaseBaud/baud) >> 8) & 0xff); + uwrite(uart, DLL, (BSPBaseBaud/baud) & 0xff); + uwrite(uart, DLM, ((BSPBaseBaud/baud) >> 8) & 0xff); /* 8-bit, no parity , 1 stop */ uwrite(uart, LCR, CHR_8_BITS); - + /* Set DTR, RTS and OUT2 high */ uwrite(uart, MCR, DTR | RTS | OUT_2); /* Enable FIFO */ - uwrite(uart, FCR, FIFO_EN | XMIT_RESET | RCV_RESET | RECEIVE_FIFO_TRIGGER12); + uwrite(uart, FCR, FIFO_EN | XMIT_RESET | RCV_RESET | RECEIVE_FIFO_TRIGGER12); /* Disable Interrupts */ uwrite(uart, IER, 0); @@ -188,7 +188,7 @@ BSP_uart_init(int uart, int baud, int hwFlow) return; } -/* +/* * Set baud */ void @@ -198,10 +198,10 @@ BSP_uart_set_baud(int uart, int baud) /* Sanity check */ SANITY_CHECK(uart); - - /* + + /* * This function may be called whenever TERMIOS parameters - * are changed, so we have to make sire that baud change is + * are changed, so we have to make sire that baud change is * indeed required */ @@ -217,14 +217,14 @@ BSP_uart_set_baud(int uart, int baud) uwrite(uart, MCR, mcr); uwrite(uart, IER, ier); - + return; } /* - * Enable/disable interrupts + * Enable/disable interrupts */ -void +void BSP_uart_intr_ctrl(int uart, int cmd) { @@ -282,7 +282,7 @@ BSP_uart_intr_ctrl(int uart, int cmd) assert(0); break; } - + return; } @@ -290,7 +290,7 @@ void BSP_uart_throttle(int uart) { unsigned int mcr; - + SANITY_CHECK(uart); if(!uart_data[uart].hwFlow) @@ -332,12 +332,12 @@ BSP_uart_unthrottle(int uart) * Status function, -1 if error * detected, 0 if no received chars available, * 1 if received char available, 2 if break - * is detected, it will eat break and error - * chars. It ignores overruns - we cannot do + * is detected, it will eat break and error + * chars. It ignores overruns - we cannot do * anything about - it execpt count statistics * and we are not counting it. */ -int +int BSP_uart_polled_status(int uart) { unsigned char val; @@ -355,7 +355,7 @@ BSP_uart_polled_status(int uart) if((val & (DR | OE | FE)) == 1) { - /* No error, character present */ + /* No error, character present */ return BSP_UART_STATUS_CHAR; } @@ -365,12 +365,12 @@ BSP_uart_polled_status(int uart) return BSP_UART_STATUS_NOCHAR; } - /* + /* * Framing or parity error * eat character */ uread(uart, RBR); - + return BSP_UART_STATUS_ERROR; } @@ -378,14 +378,14 @@ BSP_uart_polled_status(int uart) /* * Polled mode write function */ -void +void BSP_uart_polled_write(int uart, int val) { unsigned char val1; - + /* Sanity check */ SANITY_CHECK(uart); - + for(;;) { if((val1=uread(uart, LSR)) & THRE) @@ -406,7 +406,7 @@ BSP_uart_polled_write(int uart, int val) } uwrite(uart, THR, val & 0xff); - + return; } @@ -417,16 +417,16 @@ BSP_output_char_via_serial(const char val) if (val == '\n') BSP_uart_polled_write(BSPConsolePort,'\r'); } -/* +/* * Polled mode read function */ -int +int BSP_uart_polled_read(int uart) { unsigned char val; SANITY_CHECK(uart); - + for(;;) { if(uread(uart, LSR) & DR) @@ -434,13 +434,13 @@ BSP_uart_polled_read(int uart) break; } } - + val = uread(uart, RBR); return (int)(val & 0xff); } -unsigned +unsigned BSP_poll_char_via_serial() { return BSP_uart_polled_read(BSPConsolePort); @@ -453,7 +453,7 @@ uart_noop(const rtems_irq_connect_data *unused) } /* note that the IRQ names contain _ISA_ for legacy - * reasons. They can be any interrupt, depending + * reasons. They can be any interrupt, depending * on the particular BSP... */ @@ -469,7 +469,7 @@ static int doit(int uart, rtems_irq_hdl handler, int (*p)(const rtems_irq_connect_data*)) { rtems_irq_connect_data d={0}; - d.name = (uart == BSP_UART_COM1) ? + d.name = (uart == BSP_UART_COM1) ? BSP_ISA_UART_COM1_IRQ : BSP_ISA_UART_COM2_IRQ; d.off = d.on = uart_noop; d.isOn = uart_isr_is_on; @@ -482,7 +482,7 @@ BSP_uart_install_isr(int uart, rtems_irq_hdl handler) { return doit(uart, handler, BSP_install_rtems_irq_handler); } - + int BSP_uart_remove_isr(int uart, rtems_irq_hdl handler) { @@ -499,14 +499,14 @@ static char termios_tx_hold_com[2] = {0,0}; static volatile char termios_tx_hold_valid_com[2] = {0,0}; /* - * Set channel parameters + * Set channel parameters */ void BSP_uart_termios_set(int uart, void *ttyp) { unsigned char val; SANITY_CHECK(uart); - + if(uart_data[uart].hwFlow) { val = uread(uart, MSR); @@ -519,7 +519,7 @@ BSP_uart_termios_set(int uart, void *ttyp) } termios_tx_active_com[uart] = 0; termios_ttyp_com[uart] = ttyp; - termios_tx_hold_com[uart] = 0; + termios_tx_hold_com[uart] = 0; termios_tx_hold_valid_com[uart] = 0; return; @@ -538,7 +538,7 @@ BSP_uart_termios_write_com(int minor, const char *buf, int len) /* If there TX buffer is busy - something is royally screwed up */ /* assert((uread(BSP_UART_COM1, LSR) & THRE) != 0); */ - + if(termios_stopped_com[uart]) { @@ -566,7 +566,7 @@ BSP_uart_termios_write_com(int minor, const char *buf, int len) else if(!termios_tx_active_com[uart]) { termios_tx_active_com[uart] = 1; - uwrite(uart, IER, + uwrite(uart, IER, (RECEIVE_ENABLE | TRANSMIT_ENABLE | RECEIVER_LINE_ST_ENABLE @@ -589,7 +589,7 @@ BSP_uart_termios_isr_com(int uart) for(;;) { vect = uread(uart, IIR) & 0xf; - + switch(vect) { case MODEM_STATUS : @@ -625,9 +625,9 @@ BSP_uart_termios_isr_com(int uart) } return; case TRANSMITTER_HODING_REGISTER_EMPTY : - /* - * TX holding empty: we have to disable these interrupts - * if there is nothing more to send. + /* + * TX holding empty: we have to disable these interrupts + * if there is nothing more to send. */ ret = rtems_termios_dequeue_characters(termios_ttyp_com[uart], 1); @@ -670,7 +670,7 @@ BSP_uart_termios_isr_com(int uart) } } } - + void BSP_uart_termios_isr_com1(void) { diff --git a/c/src/lib/libbsp/powerpc/shared/console/uart.h b/c/src/lib/libbsp/powerpc/shared/console/uart.h index 087d151462..8396603d47 100644 --- a/c/src/lib/libbsp/powerpc/shared/console/uart.h +++ b/c/src/lib/libbsp/powerpc/shared/console/uart.h @@ -59,7 +59,7 @@ typedef struct BSP_UartBreakCbRec_ { /* * Command values for BSP_uart_intr_ctrl(), - * values are strange in order to catch errors + * values are strange in order to catch errors * with assert */ #define BSP_UART_INTR_CTRL_DISABLE (0) diff --git a/c/src/lib/libbsp/powerpc/shared/include/bsp.h b/c/src/lib/libbsp/powerpc/shared/include/bsp.h index 85488eb076..fb79919160 100644 --- a/c/src/lib/libbsp/powerpc/shared/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/shared/include/bsp.h @@ -48,7 +48,7 @@ #define BSP_CONSOLE_PORT BSP_UART_COM1 #define BSP_UART_BAUD_BASE 115200 - + #include <bsp/openpic.h> #define BSP_PIC_DO_EOI openpic_eoi(0) diff --git a/c/src/lib/libbsp/powerpc/shared/include/nvram.h b/c/src/lib/libbsp/powerpc/shared/include/nvram.h index 49edc54d3d..3f6f77988a 100644 --- a/c/src/lib/libbsp/powerpc/shared/include/nvram.h +++ b/c/src/lib/libbsp/powerpc/shared/include/nvram.h @@ -166,5 +166,5 @@ char *prep_nvram_first_var(void); char *prep_nvram_next_var(char *name); #endif /* ASM */ - + #endif /* _PPC_NVRAM_H */ diff --git a/c/src/lib/libbsp/powerpc/shared/irq/i8259.c b/c/src/lib/libbsp/powerpc/shared/irq/i8259.c index 0261d892f3..806a7eb19b 100644 --- a/c/src/lib/libbsp/powerpc/shared/irq/i8259.c +++ b/c/src/lib/libbsp/powerpc/shared/irq/i8259.c @@ -11,7 +11,7 @@ * * $Id$ */ - + #include <bsp.h> #include <bsp/irq.h> @@ -29,7 +29,7 @@ volatile rtems_i8259_masks i8259s_cache = 0xfffb; | Description: Mask IRQ line in appropriate PIC chip. | Global Variables: i8259s_cache | Arguments: vector_offset - number of IRQ line to mask. -| Returns: Nothing. +| Returns: Nothing. +--------------------------------------------------------------------------*/ int BSP_irq_disable_at_i8259s (const rtems_irq_symbolic_name irqLine) { @@ -40,12 +40,12 @@ int BSP_irq_disable_at_i8259s (const rtems_irq_symbolic_name irqLine) ((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET) ) return 1; - + _CPU_ISR_Disable(level); - + mask = 1 << irqLine; i8259s_cache |= mask; - + if (irqLine < 8) { outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); @@ -57,14 +57,14 @@ int BSP_irq_disable_at_i8259s (const rtems_irq_symbolic_name irqLine) _CPU_ISR_Enable (level); return 0; -} +} /*-------------------------------------------------------------------------+ | Function: BSP_irq_enable_at_i8259s | Description: Unmask IRQ line in appropriate PIC chip. | Global Variables: i8259s_cache | Arguments: irqLine - number of IRQ line to mask. -| Returns: Nothing. +| Returns: Nothing. +--------------------------------------------------------------------------*/ int BSP_irq_enable_at_i8259s (const rtems_irq_symbolic_name irqLine) { @@ -77,10 +77,10 @@ int BSP_irq_enable_at_i8259s (const rtems_irq_symbolic_name irqLine) return 1; _CPU_ISR_Disable(level); - + mask = ~(1 << irqLine); i8259s_cache &= mask; - + if (irqLine < 8) { outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); @@ -106,14 +106,14 @@ int BSP_irq_enabled_at_i8259s (const rtems_irq_symbolic_name irqLine) mask = (1 << irqLine); return (~(i8259s_cache & mask)); } - + /*-------------------------------------------------------------------------+ | Function: BSP_irq_ack_at_i8259s | Description: Signal generic End Of Interrupt (EOI) to appropriate PIC. | Global Variables: None. | Arguments: irqLine - number of IRQ line to acknowledge. -| Returns: Nothing. +| Returns: Nothing. +--------------------------------------------------------------------------*/ int BSP_irq_ack_at_i8259s (const rtems_irq_symbolic_name irqLine) { @@ -147,5 +147,5 @@ void BSP_i8259s_init(void) outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x02);/* edge triggered, Cascade (slave) on IRQ2 */ outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x01); /* Select 8086 mode */ outport_byte(PIC_SLAVE_IMR_IO_PORT, 0xFF); /* Mask all */ - + } diff --git a/c/src/lib/libbsp/powerpc/shared/irq/irq.c b/c/src/lib/libbsp/powerpc/shared/irq/irq.c index 0f7d50fa9b..356c7921f9 100644 --- a/c/src/lib/libbsp/powerpc/shared/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/shared/irq/irq.c @@ -12,7 +12,7 @@ */ #include <stdlib.h> - + #include <bsp.h> #include <bsp/irq.h> #include <bsp/VME.h> @@ -80,7 +80,7 @@ static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine) /* * ------------------------ RTEMS Irq helper functions ---------------- */ - + /* * Caution : this function assumes the variable "internal_config" * is already set and that the tables it contains are still valid @@ -126,7 +126,7 @@ int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq) { unsigned int level; rtems_irq_connect_data* vchain; - + if (!isValidInterrupt(irq->name)) { printk("Invalid interrupt vector %d\n",irq->name); return 0; @@ -144,7 +144,7 @@ int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq) /* save off topmost handler */ vchain[0]= rtems_hdl_tbl[irq->name]; - + /* * store the data provided by user */ @@ -153,14 +153,14 @@ int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq) /* link chain to new topmost handler */ rtems_hdl_tbl[irq->name].next_handler = (void *)vchain; - + if (is_isa_irq(irq->name)) { /* * Enable interrupt at PIC level */ BSP_irq_enable_at_i8259s (irq->name); } - + if (is_pci_irq(irq->name)) { /* * Enable interrupt at OPENPIC level @@ -177,7 +177,7 @@ int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq) * Enable interrupt on device */ irq->on(irq); - + _CPU_ISR_Enable(level); return 1; @@ -191,7 +191,7 @@ int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq) int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) { unsigned int level; - + if (!isValidInterrupt(irq->name)) { printk("Invalid interrupt vector %d\n",irq->name); return 0; @@ -215,14 +215,14 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) */ rtems_hdl_tbl[irq->name] = *irq; rtems_hdl_tbl[irq->name].next_handler = (void *)-1; - + if (is_isa_irq(irq->name)) { /* * Enable interrupt at PIC level */ BSP_irq_enable_at_i8259s (irq->name); } - + if (is_pci_irq(irq->name)) { /* * Enable interrupt at OPENPIC level @@ -239,7 +239,7 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) * Enable interrupt on device */ irq->on(irq); - + _CPU_ISR_Enable(level); return 1; @@ -263,7 +263,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_irq_connect_data *pchain= NULL, *vchain = NULL; unsigned int level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -302,7 +302,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) } else { - if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) + if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { _CPU_ISR_Enable(level); return 0; @@ -325,7 +325,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) /* * disable exception at processor level */ - } + } /* * Disable interrupt on device @@ -394,7 +394,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) { rtems_irq_connect_data* vchain; for( vchain = &rtems_hdl_tbl[i]; - ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); + ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { vchain->on(vchain); @@ -406,7 +406,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) { rtems_irq_connect_data* vchain; for( vchain = &rtems_hdl_tbl[i]; - ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); + ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { vchain->off(vchain); @@ -434,7 +434,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) { rtems_irq_connect_data* vchain; for( vchain = &rtems_hdl_tbl[i]; - ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); + ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { vchain->on(vchain); @@ -447,13 +447,13 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) { rtems_irq_connect_data* vchain; for( vchain = &rtems_hdl_tbl[i]; - ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); + ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { vchain->off(vchain); } } - + openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET); } } @@ -470,7 +470,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) { rtems_irq_connect_data* vchain; for( vchain = &rtems_hdl_tbl[i]; - ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); + ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { vchain->on(vchain); @@ -483,7 +483,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) { rtems_irq_connect_data* vchain; for( vchain = &rtems_hdl_tbl[i]; - ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); + ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { vchain->off(vchain); @@ -500,10 +500,10 @@ int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) { *config = internal_config; return 0; -} +} int _BSP_vme_bridge_irq = -1; - + unsigned BSP_spuriousIntr = 0; /* * High level IRQ handler called from shared_raw_irq_code_entry @@ -522,12 +522,12 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + rtems_hdl_tbl[BSP_DECREMENTER].hdl(); _CPU_MSR_SET(msr); return; - + } irq = openpic_irq(0); if (irq == OPENPIC_VEC_SPURIOUS) { @@ -554,7 +554,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + /* rtems_hdl_tbl[irq].hdl(); */ { rtems_irq_connect_data* vchain; @@ -585,9 +585,9 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) openpic_eoi(0); } } - - - + + + void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) { /* diff --git a/c/src/lib/libbsp/powerpc/shared/irq/irq.h b/c/src/lib/libbsp/powerpc/shared/irq/irq.h index 9d1fab5102..f2457d36e5 100644 --- a/c/src/lib/libbsp/powerpc/shared/irq/irq.h +++ b/c/src/lib/libbsp/powerpc/shared/irq/irq.h @@ -104,7 +104,7 @@ typedef enum { BSP_MAX_OFFSET = BSP_MISC_IRQ_MAX_OFFSET, /* * Some ISA IRQ symbolic name definition - */ + */ BSP_ISA_PERIODIC_TIMER = 0, BSP_ISA_KEYBOARD = 1, @@ -114,7 +114,7 @@ typedef enum { BSP_ISA_UART_COM1_IRQ = 4, BSP_ISA_RT_TIMER1 = 8, - + BSP_ISA_RT_TIMER3 = 10, /* * Some PCI IRQ symbolic name definition @@ -125,10 +125,10 @@ typedef enum { * Some Processor execption handled as rtems IRQ symbolic name definition */ BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET - + }rtems_irq_symbolic_name; - + /* @@ -162,9 +162,9 @@ typedef struct __rtems_irq_connect_data__ { * It is usually called immediately AFTER connecting the interrupt handler. * RTEMS may well need such a function when restoring normal interrupt * processing after a debug session. - * + * */ - rtems_irq_enable on; + rtems_irq_enable on; /* * function for disabling interrupts at device level (ONLY!). * The code will disable it at i8259s level. RATIONALE : anyway @@ -205,7 +205,7 @@ typedef struct { rtems_irq_symbolic_name irqBase; /* * software priorities associated with interrupts. - * if irqPrio [i] > intrPrio [j] it means that + * if irqPrio [i] > intrPrio [j] it means that * interrupt handler hdl connected for interrupt name i * will not be interrupted by the handler connected for interrupt j * The interrupt source will be physically masked at i8259 level. @@ -282,7 +282,7 @@ int BSP_irq_enabled_at_i8259s (const rtems_irq_symbolic_name irqLine); * 4) perform rescheduling when necessary, * 5) restore the C scratch registers... * 6) restore initial execution flow - * + * */ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data*); @@ -329,7 +329,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config); * (Re) get info on current RTEMS interrupt management. */ int BSP_rtems_irq_mngt_get(rtems_irq_global_settings**); - + extern void BSP_rtems_irq_mng_init(unsigned cpuId); extern void BSP_i8259s_init(void); diff --git a/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S b/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S index 6faaf9f587..7eb018d606 100644 --- a/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S +++ b/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S @@ -1,5 +1,5 @@ /* - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * IRQ veneers for RTEMS. * * The license and distribution terms for this file may be @@ -15,22 +15,22 @@ * * $Id$ */ - + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include <bsp/vectors.h> #include <libcpu/raw_exception.h> - + #define SYNC \ sync; \ isync - + .text - .p2align 5 - + .p2align 5 + PUBLIC_VAR(decrementer_exception_vector_prolog_code) - + SYM (decrementer_exception_vector_prolog_code): /* * let room for exception frame @@ -41,11 +41,11 @@ SYM (decrementer_exception_vector_prolog_code): ba shared_raw_irq_code_entry PUBLIC_VAR (decrementer_exception_vector_prolog_code_size) - + decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code PUBLIC_VAR(external_exception_vector_prolog_code) - + SYM (external_exception_vector_prolog_code): /* * let room for exception frame @@ -56,12 +56,12 @@ SYM (external_exception_vector_prolog_code): ba shared_raw_irq_code_entry PUBLIC_VAR (external_exception_vector_prolog_code_size) - + external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code PUBLIC_VAR(shared_raw_irq_code_entry) PUBLIC_VAR(C_dispatch_irq_handler) - + .p2align 5 SYM (shared_raw_irq_code_entry): /* @@ -72,7 +72,7 @@ SYM (shared_raw_irq_code_entry): * R4 : vector number */ /* - * Save SRR0/SRR1 As soon As possible as it is the minimal needed + * Save SRR0/SRR1 As soon As possible as it is the minimal needed * to reenable exception processing */ stw r0, GPR0_OFFSET(r1) @@ -81,10 +81,10 @@ SYM (shared_raw_irq_code_entry): */ stw r2, GPR2_OFFSET(r1) stw r3, GPR3_OFFSET(r1) - + mfsrr0 r0 mfsrr1 r3 - + stw r0, SRR0_FRAME_OFFSET(r1) stw r3, SRR1_FRAME_OFFSET(r1) @@ -123,7 +123,7 @@ SYM (shared_raw_irq_code_entry): mfctr r6 mfxer r7 mflr r8 - + stw r5, EXC_CR_OFFSET(r1) stw r6, EXC_CTR_OFFSET(r1) stw r7, EXC_XER_OFFSET(r1) @@ -161,9 +161,9 @@ SYM (shared_raw_irq_code_entry): cmpwi r3,0 bne nested mfspr r1, SPRG1 - -nested: - /* + +nested: + /* * Start Incrementing nesting level in R3 */ addi r3,r3,1 @@ -180,7 +180,7 @@ nested: /* store new nesting level in _ISR_Nest_level */ stw r3, _ISR_Nest_level@l(r7) #endif - + addi r6, r6, 1 mfmsr r5 /* @@ -190,7 +190,7 @@ nested: /* * We are now running on the interrupt stack. External and decrementer * exceptions are still disabled. I see no purpose trying to optimize - * further assembler code. + * further assembler code. */ /* * Call C exception handler for decrementer Interrupt frame is passed just @@ -199,7 +199,7 @@ nested: addi r3, r14, 0x8 bl C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */ /* - * start decrementing nesting level. Note : do not test result against 0 + * start decrementing nesting level. Note : do not test result against 0 * value as an easy exit condition because if interrupt nesting level > 1 * then _Thread_Dispatch_disable_level > 1 */ @@ -223,7 +223,7 @@ nested: stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */ cmpwi r3, 0 /* - * switch back to original stack (done here just optimize registers + * switch back to original stack (done here just optimize registers * contention. Could have been done before...) */ addi r1, r14, 0 @@ -231,14 +231,14 @@ nested: /* * Here we are running again on the thread system stack. * We have interrupt nesting level = _Thread_Dispatch_disable_level = 0. - * Interrupt are still disabled. Time to check if scheduler request to + * Interrupt are still disabled. Time to check if scheduler request to * do something with the current thread... */ addis r4, 0, _Context_Switch_necessary@ha lwz r5, _Context_Switch_necessary@l(r4) cmpwi r5, 0 bne switch - + addis r6, 0, _ISR_Signals_to_thread_executing@ha lwz r7, _ISR_Signals_to_thread_executing@l(r6) cmpwi r7, 0 @@ -270,12 +270,12 @@ nested: lwz r30, EXC_XER_OFFSET(r1) lwz r29, EXC_CR_OFFSET(r1) lwz r28, EXC_LR_OFFSET(r1) - + mtctr r31 mtxer r30 mtcr r29 mtlr r28 - + lmw r4, GPR4_OFFSET(r1) lwz r2, GPR2_OFFSET(r1) lwz r0, GPR0_OFFSET(r1) @@ -290,21 +290,21 @@ nested: /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC rfi - + switch: bl SYM (_Thread_Dispatch) - -easy_exit: + +easy_exit: /* * start restoring interrupt frame */ @@ -312,7 +312,7 @@ easy_exit: lwz r4, EXC_XER_OFFSET(r1) lwz r5, EXC_CR_OFFSET(r1) lwz r6, EXC_LR_OFFSET(r1) - + mtctr r3 mtxer r4 mtcr r5 @@ -341,7 +341,7 @@ easy_exit: /* * Restore rfi related settings */ - + lwz r4, SRR1_FRAME_OFFSET(r1) lwz r3, SRR0_FRAME_OFFSET(r1) lwz r2, GPR2_OFFSET(r1) diff --git a/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c b/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c index 5d14948608..c8de84c5e9 100644 --- a/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c +++ b/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c @@ -125,25 +125,25 @@ void VIA_isa_bridge_interrupts_setup(void) maxBus = BusCountPCI(); pci_dev.function = 0; /* Assumes the bidge is the first function */ - + for (pci_dev.bus = 0; pci_dev.bus < maxBus; pci_dev.bus++) { -#ifdef SCAN_PCI_PRINT +#ifdef SCAN_PCI_PRINT printk("isa_bridge_interrupts_setup: Scanning bus %d\n", pci_dev.bus); -#endif +#endif for (pci_dev.device = 0; pci_dev.device < PCI_MAX_DEVICES; pci_dev.device++) { -#ifdef SCAN_PCI_PRINT +#ifdef SCAN_PCI_PRINT printk("isa_bridge_interrupts_setup: Scanning device %d\n", pci_dev.device); -#endif +#endif pci_read_config_dword(pci_dev.bus, pci_dev.device, pci_dev.function, PCI_VENDOR_ID, &temp); -#ifdef SCAN_PCI_PRINT +#ifdef SCAN_PCI_PRINT printk("Vendor/device = %x\n", temp); #endif if ((temp == (((unsigned short) PCI_VENDOR_ID_VIA) | (PCI_DEVICE_ID_VIA_82C586_0 << 16))) ) { bridge = pci_dev; via_82c586 = &bridge; -#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS +#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS /* * Should print : bus = 0, device = 11, function = 0 on a MCP750. */ @@ -151,27 +151,27 @@ void VIA_isa_bridge_interrupts_setup(void) via_82c586->bus, via_82c586->device, via_82c586->function); -#endif +#endif found = 1; goto loop_exit; - + } } } loop_exit: if (!found) BSP_panic("VIA_82C586 PCI/ISA bridge not found!n"); - + tmp = inb(0x810); if ( !(tmp & 0x2)) { -#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS +#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS printk("This is a second generation MCP750 board\n"); printk("We must reprogram the PCI/ISA bridge...\n"); -#endif +#endif pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, 0x47, &tmp); -#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS +#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp); -#endif +#endif /* * Enable 4D0/4D1 ISA interrupt level/edge config registers */ @@ -190,31 +190,31 @@ loop_exit: */ pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, 0x54, &tmp); -#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS +#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp); -#endif +#endif tmp = 0; pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, 0x54, tmp); } else { -#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS +#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS printk("This is a first generation MCP750 board\n"); printk("We just show the actual value used by PCI/ISA bridge\n"); -#endif +#endif pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, 0x47, &tmp); -#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS +#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp); -#endif +#endif /* * Show the Interrupt inputs inverting/non-inverting level status */ pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, 0x54, &tmp); -#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS +#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp); -#endif +#endif } } @@ -229,15 +229,15 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) rtems_raw_except_connect_data vectorDesc; int known_cpi_isa_bridge = 0; int i; - + /* * First initialize the Interrupt management hardware */ -#ifdef TRACE_IRQ_INIT +#ifdef TRACE_IRQ_INIT printk("Going to initialize raven interrupt controller (openpic compliant)\n"); -#endif +#endif openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses); -#ifdef TRACE_IRQ_INIT +#ifdef TRACE_IRQ_INIT printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n"); #endif if ( currentBoard == MESQUITE ) { @@ -258,9 +258,9 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) printk("If your card works correctly please add a test and set known_cpi_isa_bridge to true\n"); printk("currentBoard = %i\n", currentBoard); } -#ifdef TRACE_IRQ_INIT +#ifdef TRACE_IRQ_INIT printk("Going to initialize the ISA PC legacy IRQ management hardware\n"); -#endif +#endif BSP_i8259s_init(); /* * Initialize Rtems management interrupt table @@ -287,7 +287,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) */ BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); } - + /* * We must connect the raw irq handler for the two * expected interrupt sources : decrementer and external interrupts. @@ -309,7 +309,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) if (!mpc60x_set_exception (&vectorDesc)) { BSP_panic("Unable to initialize RTEMS external raw exception\n"); } -#ifdef TRACE_IRQ_INIT +#ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operationnal\n"); #endif } diff --git a/c/src/lib/libbsp/powerpc/shared/motorola/motorola.c b/c/src/lib/libbsp/powerpc/shared/motorola/motorola.c index 262bd5e265..f30cfc5d2d 100644 --- a/c/src/lib/libbsp/powerpc/shared/motorola/motorola.c +++ b/c/src/lib/libbsp/powerpc/shared/motorola/motorola.c @@ -61,7 +61,7 @@ ** multiple interrupt lines over the interrupt pin supplied by the ** record. If more than one entry is present, the most preferable ** should supplied first. -** +** */ #define NULL_PINMAP {-1,{-1,-1,-1,-1}} @@ -69,7 +69,7 @@ -static struct _int_map mcp750_intmap[] = { +static struct _int_map mcp750_intmap[] = { { 0, 16, 0, {{1, {5, 19,-1,-1}}, /* pmc slot */ NULL_PINMAP}}, @@ -226,12 +226,12 @@ motorolaBoard getMotorolaBoard() for (entry = 0; mot_boards[entry].cpu_type != 0; entry++) { if ((mot_boards[entry].cpu_type & 0xff) != cpu_type) continue; - + if (mot_boards[entry].base_type == 0) { mot_entry = entry; break; } - + if (mot_boards[entry].base_type != base_mod) continue; else{ diff --git a/c/src/lib/libbsp/powerpc/shared/motorola/motorola.h b/c/src/lib/libbsp/powerpc/shared/motorola/motorola.h index f5b3a908cb..11d3fff4c4 100644 --- a/c/src/lib/libbsp/powerpc/shared/motorola/motorola.h +++ b/c/src/lib/libbsp/powerpc/shared/motorola/motorola.h @@ -60,9 +60,9 @@ typedef enum { HOST_BRIDGE_HAWK = 1, HOST_BRIDGE_UNKNOWN = 255 }motorolaHostBridge; - + #define MOTOROLA_CPUTYPE_REG 0x800 -#define MOTOROLA_BASETYPE_REG 0x803 +#define MOTOROLA_BASETYPE_REG 0x803 extern prep_t checkPrepBoardType(RESIDUAL *res); extern prep_t currentPrepType; diff --git a/c/src/lib/libbsp/powerpc/shared/openpic/openpic.c b/c/src/lib/libbsp/powerpc/shared/openpic/openpic.c index ad927a4e72..0a619ba1c2 100644 --- a/c/src/lib/libbsp/powerpc/shared/openpic/openpic.c +++ b/c/src/lib/libbsp/powerpc/shared/openpic/openpic.c @@ -243,13 +243,13 @@ void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses /* No processor */ openpic_maptimer(i, 0); } - + /* Initialize IPI interrupts */ for (i = 0; i < OPENPIC_NUM_IPI; i++) { /* Disabled, Priority 0 */ openpic_initipi(i, 0, OPENPIC_VEC_IPI+i); } - + /* Initialize external interrupts */ for (i = 0; i < NumSources; i++) { /* Enabled, Priority 8 */ @@ -259,14 +259,14 @@ void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses /* Processor 0 */ openpic_mapirq(i, 1<<0); } - + /* Initialize the spurious interrupt */ openpic_set_spurious(OPENPIC_VEC_SPURIOUS); -#if 0 +#if 0 if (request_irq(IRQ_8259_CASCADE, no_action, SA_INTERRUPT, "82c59 cascade", NULL)) printk("Unable to get OpenPIC IRQ 0 for cascade\n"); -#endif +#endif openpic_set_priority(0, 0); openpic_disable_8259_pass_through(); } diff --git a/c/src/lib/libbsp/powerpc/shared/pci/detect_raven_bridge.c b/c/src/lib/libbsp/powerpc/shared/pci/detect_raven_bridge.c index f68f7be2aa..7748e3c307 100644 --- a/c/src/lib/libbsp/powerpc/shared/pci/detect_raven_bridge.c +++ b/c/src/lib/libbsp/powerpc/shared/pci/detect_raven_bridge.c @@ -57,25 +57,25 @@ void detect_host_bridge() PPC_DEVICE *hostbridge; unsigned int id0; unsigned int tmp; - + /* * This code assumes that the host bridge is located at * bus 0, dev 0, func 0 AND that the old pre PCI 2.1 * standart devices detection mecahnism that was used on PC * (still used in BSD source code) works. */ - hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL, + hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL, BridgeController, PCIBridge, -1, 0); if (hostbridge) { if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) { pci.pci_functions=&pci_indirect_functions; - /* Should be extracted from residual data, + /* Should be extracted from residual data, * indeed MPC106 in CHRP mode is different, * but we should not use residual data in - * this case anyway. + * this case anyway. */ - pci.pci_config_addr = ((volatile unsigned char *) + pci.pci_config_addr = ((volatile unsigned char *) (ptr_mem_map->io_base+0xcf8)); pci.pci_config_data = ptr_mem_map->io_base+0xcfc; } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) { @@ -87,7 +87,7 @@ void detect_host_bridge() /* Let us try by experimentation at our own risk! */ pci.pci_functions = &pci_direct_functions; /* On all direct bridges I know the host bridge itself - * appears as device 0 function 0. + * appears as device 0 function 0. */ pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0); if (id0==~0U) { @@ -108,27 +108,27 @@ void detect_host_bridge() * We have a Raven bridge. We will get information about its settings */ pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); -#ifdef SHOW_RAVEN_SETTING +#ifdef SHOW_RAVEN_SETTING printk("RAVEN PCI command register = %x\n",id0); -#endif +#endif id0 |= RAVEN_CLEAR_EVENTS_MASK; pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0); pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); -#ifdef SHOW_RAVEN_SETTING +#ifdef SHOW_RAVEN_SETTING printk("After error clearing RAVEN PCI command register = %x\n",id0); -#endif - +#endif + if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) { pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp); -#ifdef SHOW_RAVEN_SETTING +#ifdef SHOW_RAVEN_SETTING printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1)); -#endif +#endif } if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) { pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp); -#ifdef SHOW_RAVEN_SETTING +#ifdef SHOW_RAVEN_SETTING printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp); -#endif +#endif OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE); printk("OpenPIC found at %x.\n", OpenPIC); diff --git a/c/src/lib/libbsp/powerpc/shared/pci/pci.c b/c/src/lib/libbsp/powerpc/shared/pci/pci.c index 506221c8e2..ba5a97d44d 100644 --- a/c/src/lib/libbsp/powerpc/shared/pci/pci.c +++ b/c/src/lib/libbsp/powerpc/shared/pci/pci.c @@ -44,9 +44,9 @@ unsigned char ucMaxPCIBus; static int indirect_pci_read_config_byte(unsigned char bus, unsigned char slot, - unsigned char function, + unsigned char function, unsigned char offset, unsigned char *val) { - out_be32((unsigned int*) pci.pci_config_addr, + out_be32((unsigned int*) pci.pci_config_addr, 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); *val = in_8(pci.pci_config_data + (offset&3)); return PCIBIOS_SUCCESSFUL; @@ -54,11 +54,11 @@ indirect_pci_read_config_byte(unsigned char bus, unsigned char slot, static int indirect_pci_read_config_word(unsigned char bus, unsigned char slot, - unsigned char function, + unsigned char function, unsigned char offset, unsigned short *val) { - *val = 0xffff; + *val = 0xffff; if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; - out_be32((unsigned int*) pci.pci_config_addr, + out_be32((unsigned int*) pci.pci_config_addr, 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); *val = in_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3))); return PCIBIOS_SUCCESSFUL; @@ -66,11 +66,11 @@ indirect_pci_read_config_word(unsigned char bus, unsigned char slot, static int indirect_pci_read_config_dword(unsigned char bus, unsigned char slot, - unsigned char function, + unsigned char function, unsigned char offset, unsigned int *val) { - *val = 0xffffffff; + *val = 0xffffffff; if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; - out_be32((unsigned int*) pci.pci_config_addr, + out_be32((unsigned int*) pci.pci_config_addr, 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24)); *val = in_le32((volatile unsigned int *)pci.pci_config_data); return PCIBIOS_SUCCESSFUL; @@ -78,9 +78,9 @@ indirect_pci_read_config_dword(unsigned char bus, unsigned char slot, static int indirect_pci_write_config_byte(unsigned char bus, unsigned char slot, - unsigned char function, + unsigned char function, unsigned char offset, unsigned char val) { - out_be32((unsigned int*) pci.pci_config_addr, + out_be32((unsigned int*) pci.pci_config_addr, 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); out_8(pci.pci_config_data + (offset&3), val); return PCIBIOS_SUCCESSFUL; @@ -88,10 +88,10 @@ indirect_pci_write_config_byte(unsigned char bus, unsigned char slot, static int indirect_pci_write_config_word(unsigned char bus, unsigned char slot, - unsigned char function, + unsigned char function, unsigned char offset, unsigned short val) { if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; - out_be32((unsigned int*) pci.pci_config_addr, + out_be32((unsigned int*) pci.pci_config_addr, 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); out_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)), val); return PCIBIOS_SUCCESSFUL; @@ -99,10 +99,10 @@ indirect_pci_write_config_word(unsigned char bus, unsigned char slot, static int indirect_pci_write_config_dword(unsigned char bus, unsigned char slot, - unsigned char function, + unsigned char function, unsigned char offset, unsigned int val) { if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; - out_be32((unsigned int*) pci.pci_config_addr, + out_be32((unsigned int*) pci.pci_config_addr, 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24)); out_le32((volatile unsigned int *)pci.pci_config_data, val); return PCIBIOS_SUCCESSFUL; @@ -123,22 +123,22 @@ pci_config BSP_pci_configuration = {(volatile unsigned char*)PCI_CONFIG_ADDR, static int direct_pci_read_config_byte(unsigned char bus, unsigned char slot, - unsigned char function, + unsigned char function, unsigned char offset, unsigned char *val) { if (bus != 0 || (1<<slot & 0xff8007fe)) { *val=0xff; return PCIBIOS_DEVICE_NOT_FOUND; } - *val=in_8(pci.pci_config_data + ((1<<slot)&~1) + *val=in_8(pci.pci_config_data + ((1<<slot)&~1) + (function<<8) + offset); return PCIBIOS_SUCCESSFUL; } static int direct_pci_read_config_word(unsigned char bus, unsigned char slot, - unsigned char function, + unsigned char function, unsigned char offset, unsigned short *val) { - *val = 0xffff; + *val = 0xffff; if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; if (bus != 0 || (1<<slot & 0xff8007fe)) { return PCIBIOS_DEVICE_NOT_FOUND; @@ -151,9 +151,9 @@ direct_pci_read_config_word(unsigned char bus, unsigned char slot, static int direct_pci_read_config_dword(unsigned char bus, unsigned char slot, - unsigned char function, + unsigned char function, unsigned char offset, unsigned int *val) { - *val = 0xffffffff; + *val = 0xffffffff; if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; if (bus != 0 || (1<<slot & 0xff8007fe)) { return PCIBIOS_DEVICE_NOT_FOUND; @@ -166,20 +166,20 @@ direct_pci_read_config_dword(unsigned char bus, unsigned char slot, static int direct_pci_write_config_byte(unsigned char bus, unsigned char slot, - unsigned char function, + unsigned char function, unsigned char offset, unsigned char val) { if (bus != 0 || (1<<slot & 0xff8007fe)) { return PCIBIOS_DEVICE_NOT_FOUND; } - out_8(pci.pci_config_data + ((1<<slot)&~1) - + (function<<8) + offset, + out_8(pci.pci_config_data + ((1<<slot)&~1) + + (function<<8) + offset, val); return PCIBIOS_SUCCESSFUL; } static int direct_pci_write_config_word(unsigned char bus, unsigned char slot, - unsigned char function, + unsigned char function, unsigned char offset, unsigned short val) { if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; if (bus != 0 || (1<<slot & 0xff8007fe)) { @@ -194,7 +194,7 @@ direct_pci_write_config_word(unsigned char bus, unsigned char slot, static int direct_pci_write_config_dword(unsigned char bus, unsigned char slot, - unsigned char function, + unsigned char function, unsigned char offset, unsigned int val) { if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; if (bus != 0 || (1<<slot & 0xff8007fe)) { @@ -232,7 +232,7 @@ const pci_config_access_functions pci_direct_functions = { printk("pci : Device %d:%02x routed to interrupt_line %d\n", pbus, pslot, int_name ) -/* +/* ** Validate a test interrupt name and print a warning if its not one of ** the names defined in the routing record. */ @@ -244,19 +244,19 @@ static int test_intname( for(j=0; row->pin_route[j].pin > -1; j++) { - if( row->pin_route[j].pin == int_pin ) + if( row->pin_route[j].pin == int_pin ) { _nopin = 0; - + for(k=0; k<4 && row->pin_route[j].int_name[k] > -1; k++ ) { - if( row->pin_route[j].int_name[k] == int_name ){ _noname=0; break; } + if( row->pin_route[j].int_name[k] == int_name ){ _noname=0; break; } } break; } } - if( _nopin ) + if( _nopin ) { printk("pci : Device %d:%02x supplied a bogus interrupt_pin %d\n", pbus, pslot, int_pin ); return -1; @@ -288,7 +288,7 @@ static int FindPCIbridge( int mybus, struct pcibridge *pb ) for(pbus=0; pbus< BusCountPCI(); pbus++) { for(pslot=0; pslot< PCI_MAX_DEVICES; pslot++) - { + { pci_read_config_word(pbus, pslot, 0, PCI_DEVICE_ID, &devid); if( devid == 0xffff ) continue; @@ -297,7 +297,7 @@ static int FindPCIbridge( int mybus, struct pcibridge *pb ) pci_read_config_word(pbus, pslot, 0, PCI_CLASS_DEVICE, &dclass); - if( dclass == PCI_CLASS_BRIDGE_PCI ) + if( dclass == PCI_CLASS_BRIDGE_PCI ) { pci_read_config_byte(pbus, pslot, 0, PCI_PRIMARY_BUS, &buspri); pci_read_config_byte(pbus, pslot, 0, PCI_SECONDARY_BUS, &bussec); @@ -349,7 +349,7 @@ void FixupPCI( const struct _int_map *bspmap, int (*swizzler)(int,int) ) for(pbus=0; pbus< BusCountPCI(); pbus++) { for(pslot=0; pslot< PCI_MAX_DEVICES; pslot++) - { + { pci_read_config_word(pbus, pslot, 0, PCI_DEVICE_ID, &devid); if( devid == 0xffff ) continue; @@ -406,13 +406,13 @@ void FixupPCI( const struct _int_map *bspmap, int (*swizzler)(int,int) ) } } - + if( !ismatch ) { - /* + /* ** no match, which means we're on a bus someplace. Work ** backwards from it to one of our defined busses, - ** swizzling thru each bridge on the way. + ** swizzling thru each bridge on the way. */ /* keep pbus, pslot pointed to the device being @@ -481,7 +481,7 @@ void FixupPCI( const struct _int_map *bspmap, int (*swizzler)(int,int) ) { struct pcibridge pb; - /* + /* ** Haven't found our bus in the int map, so work ** upwards thru the bridges till we find it. */ @@ -504,7 +504,7 @@ void FixupPCI( const struct _int_map *bspmap, int (*swizzler)(int,int) ) printk("pci : No bridge from bus %d towards root found\n", tbus ); goto donesearch; } - + } } diff --git a/c/src/lib/libbsp/powerpc/shared/pci/pci.h b/c/src/lib/libbsp/powerpc/shared/pci/pci.h index 0971a0ec48..4ce74f7307 100644 --- a/c/src/lib/libbsp/powerpc/shared/pci/pci.h +++ b/c/src/lib/libbsp/powerpc/shared/pci/pci.h @@ -43,7 +43,7 @@ #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ -#define PCI_STATUS_DEVSEL_FAST 0x000 +#define PCI_STATUS_DEVSEL_FAST 0x000 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 #define PCI_STATUS_DEVSEL_SLOW 0x400 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ @@ -72,8 +72,8 @@ /* * Base addresses specify locations in memory or I/O space. - * Decoded size can be determined by writing a value of - * 0xffffffff to the register, and reading it back. Only + * Decoded size can be determined by writing a value of + * 0xffffffff to the register, and reading it back. Only * 1 bits are decoded. */ #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ @@ -97,7 +97,7 @@ /* Header type 0 (normal devices) */ #define PCI_CARDBUS_CIS 0x28 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c -#define PCI_SUBSYSTEM_ID 0x2e +#define PCI_SUBSYSTEM_ID 0x2e #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ #define PCI_ROM_ADDRESS_ENABLE 0x01 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) @@ -456,8 +456,8 @@ #define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010 #define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 -#define PCI_VENDOR_ID_DPT 0x1044 -#define PCI_DEVICE_ID_DPT 0xa400 +#define PCI_VENDOR_ID_DPT 0x1044 +#define PCI_DEVICE_ID_DPT 0xa400 #define PCI_VENDOR_ID_OPTI 0x1045 #define PCI_DEVICE_ID_OPTI_92C178 0xc178 @@ -1112,37 +1112,37 @@ typedef struct { extern pci_config BSP_pci_configuration; extern inline int -pci_read_config_byte(unsigned char bus, unsigned char slot, unsigned char function, +pci_read_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char where, unsigned char * val) { return BSP_pci_configuration.pci_functions->read_config_byte(bus, slot, function, where, val); } extern inline int -pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char function, +pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char where, unsigned short * val) { return BSP_pci_configuration.pci_functions->read_config_word(bus, slot, function, where, val); } extern inline int -pci_read_config_dword(unsigned char bus, unsigned char slot, unsigned char function, +pci_read_config_dword(unsigned char bus, unsigned char slot, unsigned char function, unsigned char where, unsigned int * val) { return BSP_pci_configuration.pci_functions->read_config_dword(bus, slot, function, where, val); } extern inline int -pci_write_config_byte(unsigned char bus, unsigned char slot, unsigned char function, +pci_write_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char where, unsigned char val) { return BSP_pci_configuration.pci_functions->write_config_byte(bus, slot, function, where, val); } extern inline int -pci_write_config_word(unsigned char bus, unsigned char slot, unsigned char function, +pci_write_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char where, unsigned short val) { return BSP_pci_configuration.pci_functions->write_config_word(bus, slot, function, where, val); } extern inline int -pci_write_config_dword(unsigned char bus, unsigned char slot, unsigned char function, +pci_write_config_dword(unsigned char bus, unsigned char slot, unsigned char function, unsigned char where, unsigned int val) { return BSP_pci_configuration.pci_functions->write_config_dword(bus, slot, function, where, val); } diff --git a/c/src/lib/libbsp/powerpc/shared/pci/pcifinddevice.c b/c/src/lib/libbsp/powerpc/shared/pci/pcifinddevice.c index 6ba8d9cc05..3371eefe6f 100644 --- a/c/src/lib/libbsp/powerpc/shared/pci/pcifinddevice.c +++ b/c/src/lib/libbsp/powerpc/shared/pci/pcifinddevice.c @@ -28,7 +28,7 @@ BSP_pciFindDevice( unsigned short vendorid, unsigned short deviceid, hd = (hd & PCI_MULTI_FUNCTION ? PCI_MAX_FUNCTIONS : 1); for (fun=0; fun<hd; fun++) { - /* + /* * The last devfn id/slot is special; must skip it */ if (PCI_MAX_DEVICES-1==dev && PCI_MAX_FUNCTIONS-1 == fun) diff --git a/c/src/lib/libbsp/powerpc/shared/residual/residual.c b/c/src/lib/libbsp/powerpc/shared/residual/residual.c index 4327382c67..7d5b1a4aa8 100644 --- a/c/src/lib/libbsp/powerpc/shared/residual/residual.c +++ b/c/src/lib/libbsp/powerpc/shared/residual/residual.c @@ -22,7 +22,7 @@ static int same_DevID(unsigned short vendor, unsigned short Number, - char * str) + char * str) { static unsigned const char hexdigit[]="0123456789ABCDEF"; if (strlen(str)!=7) return 0; @@ -68,11 +68,11 @@ PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, if (tag_type(packet_tag)) mask=0xff; else mask=0xF8; masked_tag = packet_tag&mask; for(; *p != END_TAG; p+=size) { - if ((*p & mask) == masked_tag && !(n--)) + if ((*p & mask) == masked_tag && !(n--)) return (PnP_TAG_PACKET *) p; if (tag_type(*p)) size=ld_le16((unsigned short *)(p+1))+3; - else + else size=tag_small_count(*p)+1; } return 0; /* not found */ @@ -85,7 +85,7 @@ PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p, int next=0; while (p) { p = (unsigned char *) PnP_find_packet(p, 0x70, next); - if (p && p[1]==packet_type && !(n--)) + if (p && p[1]==packet_type && !(n--)) return (PnP_TAG_PACKET *) p; next = 1; }; @@ -99,7 +99,7 @@ PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, int next=0; while (p) { p = (unsigned char *) PnP_find_packet(p, 0x84, next); - if (p && p[3]==packet_type && !(n--)) + if (p && p[3]==packet_type && !(n--)) return (PnP_TAG_PACKET *) p; next = 1; }; diff --git a/c/src/lib/libbsp/powerpc/shared/start/rtems_crti.S b/c/src/lib/libbsp/powerpc/shared/start/rtems_crti.S index 3d63d1261b..81ec2ae557 100644 --- a/c/src/lib/libbsp/powerpc/shared/start/rtems_crti.S +++ b/c/src/lib/libbsp/powerpc/shared/start/rtems_crti.S @@ -4,11 +4,11 @@ #include <libcpu/io.h> /* terminate the __init() function and create - * a new head '_init' for use by RTEMS to + * a new head '_init' for use by RTEMS to * invoke C++ global constructors * NOTE: it is essential that this snippet * is hooked between ecrti and crtbegin - * + * * ecrti has the following .init section: * __init: * stwu r1,-16(r1) diff --git a/c/src/lib/libbsp/powerpc/shared/start/start.S b/c/src/lib/libbsp/powerpc/shared/start/start.S index c986564cb7..8c90a442f0 100644 --- a/c/src/lib/libbsp/powerpc/shared/start/start.S +++ b/c/src/lib/libbsp/powerpc/shared/start/start.S @@ -28,20 +28,20 @@ li r10,0x63 ; \ sc - + .text .globl __rtems_entry_point .type __rtems_entry_point,@function __rtems_entry_point: #ifdef DEBUG_EARLY_START MONITOR_ENTER -#endif - -/* +#endif + +/* * PREP * This is jumped to on prep systems right after the kernel is relocated * to its proper place in memory by the boot loader. The expected layout - * of the regs is: + * of the regs is: * r3: ptr to residual data * r4: initrd_start or if no initrd then 0 * r5: initrd_end - unused if r4 is 0 @@ -51,7 +51,7 @@ __rtems_entry_point: * The Prep boot loader insure that the MMU is currently off... * */ - + mr r31,r3 /* save parameters */ mr r30,r4 mr r29,r5 @@ -64,7 +64,7 @@ __rtems_entry_point: bl flush_tlbs /* * Use the first pair of BAT registers to map the 1st 256MB - * of RAM to KERNELBASE. + * of RAM to KERNELBASE. */ lis r11,KERNELBASE@h ori r11,r11,0x1ffe /* set up BAT registers for 604 */ @@ -77,14 +77,14 @@ __rtems_entry_point: isync /* - * we now have the 1st 256M of ram mapped with the bats. We are still - * running on the bootloader stack and cannot switch to an RTEMS allocated + * we now have the 1st 256M of ram mapped with the bats. We are still + * running on the bootloader stack and cannot switch to an RTEMS allocated * init stack before copying the residual data that may have been set just after * rtems_end address. This bug has been experienced on MVME2304. Thank to - * Till Straumann <strauman@SLAC.Stanford.EDU> for hunting it and suggesting + * Till Straumann <strauman@SLAC.Stanford.EDU> for hunting it and suggesting * the appropriate code. */ - + enter_C_code: bl MMUon bl __eabi /* setup EABI and SYSV environment */ @@ -96,7 +96,7 @@ enter_C_code: mr r4,r30 mr r5,r29 mr r6,r28 - mr r7,r27 + mr r7,r27 bl save_boot_params /* * stack = &__rtems_end + 4096 @@ -113,10 +113,10 @@ enter_C_code: li r3, 0 /* argc */ bl boot_card bl _return_to_ppcbug - + .globl MMUon .type MMUon,@function -MMUon: +MMUon: mfmsr r0 #if (PPC_HAS_FPU == 0) ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP @@ -130,10 +130,10 @@ MMUon: mtsrr1 r0 SYNC rfi - + .globl MMUoff .type MMUoff,@function -MMUoff: +MMUoff: mfmsr r0 ori r0,r0,MSR_IR| MSR_DR | MSR_IP mflr r11 @@ -146,22 +146,22 @@ MMUoff: .globl _return_to_ppcbug .type _return_to_ppcbug,@function - + _return_to_ppcbug: mflr r30 bl MMUoff MONITOR_ENTER bl MMUon mtctr r30 - bctr + bctr -/* +/* * An undocumented "feature" of 604e requires that the v bit * be cleared before changing BAT values. * * Also, newer IBM firmware does not clear bat3 and 4 so * this makes sure it's done. - * -- Cort + * -- Cort */ clear_bats: li r20,0 @@ -171,14 +171,14 @@ clear_bats: SYNC beq 1f mtspr DBAT0U,r20 - mtspr DBAT0L,r20 + mtspr DBAT0L,r20 mtspr DBAT1U,r20 mtspr DBAT1L,r20 mtspr DBAT2U,r20 - mtspr DBAT2L,r20 + mtspr DBAT2L,r20 mtspr DBAT3U,r20 mtspr DBAT3L,r20 -1: +1: mtspr IBAT0U,r20 mtspr IBAT0L,r20 mtspr IBAT1U,r20 @@ -187,7 +187,7 @@ clear_bats: mtspr IBAT2L,r20 mtspr IBAT3U,r20 mtspr IBAT3L,r20 - SYNC + SYNC blr flush_tlbs: @@ -197,6 +197,6 @@ flush_tlbs: bgt 1b sync blr - + .comm environ,4,4 diff --git a/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c b/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c index 2565b9a251..82ade603ef 100644 --- a/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c @@ -51,7 +51,7 @@ SPR_RW(SPRG1) /* * Copy of residuals passed by firmware */ -RESIDUAL residualCopy; +RESIDUAL residualCopy; /* * Copy Additional boot param passed by boot loader */ @@ -85,15 +85,15 @@ unsigned int BSP_time_base_divisor; void BSP_panic(char *s) { printk("%s PANIC %s\n",_RTEMS_version, s); - __asm__ __volatile ("sc"); + __asm__ __volatile ("sc"); } void _BSP_Fatal_error(unsigned int v) { printk("%s PANIC ERROR %x\n",_RTEMS_version, v); - __asm__ __volatile ("sc"); + __asm__ __volatile ("sc"); } - + /* * The original table from the application and our copy of it with * some changes. @@ -110,7 +110,7 @@ char *rtems_progname; /* * Use the shared implementations of the following routines */ - + void bsp_postdriver_hook(void); void bsp_libc_init( void *, uint32_t, int ); @@ -127,10 +127,10 @@ void bsp_libc_init( void *, uint32_t, int ); * not yet initialized. * */ - + void bsp_pretasking_hook(void) { - uint32_t heap_start; + uint32_t heap_start; uint32_t heap_size; uint32_t heap_sbrk_spared; extern uint32_t _bsp_sbrk_init(uint32_t, uint32_t*); @@ -145,7 +145,7 @@ void bsp_pretasking_hook(void) #ifdef SHOW_MORE_INIT_SETTINGS printk(" HEAP start %x size %x (%x bytes spared for sbrk)\n", heap_start, heap_size, heap_sbrk_spared); -#endif +#endif bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared); @@ -167,7 +167,7 @@ void zero_bss() void save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_options) { - + residualCopy = *r3; strncpy(loaderParam, additional_boot_options, MAX_LOADER_ADD_PARM); loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0'; @@ -209,7 +209,7 @@ void bsp_start( void ) l2cr = get_L2CR(); #ifdef SHOW_LCR2_REGISTER printk("Initial L2CR value = %x\n", l2cr); -#endif +#endif if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1)) set_L2CR(0xb9A14000); /* @@ -262,15 +262,15 @@ void bsp_start( void ) /* T. Straumann: give more PCI address space */ setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x10000000, IO_PAGE); /* - * Must have acces to open pic PCI ACK registers + * Must have acces to open pic PCI ACK registers * provided by the RAVEN - * + * */ setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE); select_console(CONSOLE_LOG); - /* We check that the keyboard is present and immediately + /* We check that the keyboard is present and immediately * select the serial console if not. */ err = kbdreset(); @@ -282,11 +282,11 @@ void bsp_start( void ) while (1); } myBoard = getMotorolaBoard(); - + printk("-----------------------------------------\n"); printk("Welcome to %s on %s\n", _RTEMS_version, motorolaBoardToString(myBoard)); printk("-----------------------------------------\n"); -#ifdef SHOW_MORE_INIT_SETTINGS +#ifdef SHOW_MORE_INIT_SETTINGS printk("Residuals are located at %x\n", (unsigned) &residualCopy); printk("Additionnal boot options are %s\n", loaderParam); printk("Initial system stack at %x\n",stack); @@ -294,7 +294,7 @@ void bsp_start( void ) printk("-----------------------------------------\n"); #endif -#ifdef TEST_RETURN_TO_PPCBUG +#ifdef TEST_RETURN_TO_PPCBUG printk("Hit <Enter> to return to PPCBUG monitor\n"); printk("When Finished hit GO. It should print <Back from monitor>\n"); debug_getc(); @@ -305,7 +305,7 @@ void bsp_start( void ) #ifdef SHOW_MORE_INIT_SETTINGS printk("Going to start PCI buses scanning and initialization\n"); -#endif +#endif InitializePCI(); { @@ -323,7 +323,7 @@ void bsp_start( void ) #ifdef SHOW_MORE_INIT_SETTINGS printk("Number of PCI buses found is : %d\n", BusCountPCI()); #endif -#ifdef TEST_RAW_EXCEPTION_CODE +#ifdef TEST_RAW_EXCEPTION_CODE printk("Testing exception handling Part 1\n"); /* * Cause a software exception @@ -334,7 +334,7 @@ void bsp_start( void ) */ printk("Testing exception handling Part 2\n"); __asm__ __volatile ("sc"); -#endif +#endif BSP_mem_size = residualCopy.TotalMemory; @@ -369,7 +369,7 @@ void bsp_start( void ) )) { printk("WARNING: unable to setup page tables VME bridge must share PCI space\n"); } - + /* * Set up our hooks * Make sure libc_init is done before drivers initialized so that @@ -385,8 +385,8 @@ void bsp_start( void ) #ifdef SHOW_MORE_INIT_SETTINGS printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size); -#endif - work_space_start = +#endif + work_space_start = (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size; if ( work_space_start <= ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) { @@ -401,18 +401,18 @@ void bsp_start( void ) */ BSP_rtems_irq_mng_init(0); - + /* Activate the page table mappings only after * initializing interrupts because the irq_mng_init() * routine needs to modify the text - */ + */ if (pt) { #ifdef SHOW_MORE_INIT_SETTINGS printk("Page table setup finished; will activate it NOW...\n"); #endif BSP_pgtbl_activate(pt); /* finally, switch off DBAT3 */ - setdbat(3, 0, 0, 0, 0); + setdbat(3, 0, 0, 0, 0); } /* @@ -430,5 +430,5 @@ void bsp_start( void ) #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); -#endif +#endif } diff --git a/c/src/lib/libbsp/powerpc/shared/startup/pgtbl_setup.c b/c/src/lib/libbsp/powerpc/shared/startup/pgtbl_setup.c index 5cd462a65d..7f957bfc48 100644 --- a/c/src/lib/libbsp/powerpc/shared/startup/pgtbl_setup.c +++ b/c/src/lib/libbsp/powerpc/shared/startup/pgtbl_setup.c @@ -61,7 +61,7 @@ unsigned ldPtSize,tmp; 0, /* WIMG */ TRIV121_PP_RO_PAGE); if (TRIV121_MAP_SUCCESS != tmp) { - printk("Unable to map page index %i; reverting to BAT0\n", + printk("Unable to map page index %i; reverting to BAT0\n", tmp); pt = 0; } else { @@ -74,7 +74,7 @@ unsigned ldPtSize,tmp; 0, /* WIMG */ TRIV121_PP_RW_PAGE); if (TRIV121_MAP_SUCCESS != tmp) { - printk("Unable to map page index %i; reverting to BAT0\n", + printk("Unable to map page index %i; reverting to BAT0\n", tmp); pt = 0; } diff --git a/c/src/lib/libbsp/powerpc/shared/startup/sbrk.c b/c/src/lib/libbsp/powerpc/shared/startup/sbrk.c index 3a8b5664f8..8cd9e05cd9 100644 --- a/c/src/lib/libbsp/powerpc/shared/startup/sbrk.c +++ b/c/src/lib/libbsp/powerpc/shared/startup/sbrk.c @@ -32,7 +32,7 @@ static uint32_t remaining_size=0; #define LIMIT_32M 0x02000000 -uint32_t +uint32_t _bsp_sbrk_init(uint32_t heap_start, uint32_t *heap_size_p) { uint32_t rval=0; diff --git a/c/src/lib/libbsp/powerpc/shared/vectors/vectors.S b/c/src/lib/libbsp/powerpc/shared/vectors/vectors.S index 17c4ffecd6..55f990ec33 100644 --- a/c/src/lib/libbsp/powerpc/shared/vectors/vectors.S +++ b/c/src/lib/libbsp/powerpc/shared/vectors/vectors.S @@ -2,37 +2,37 @@ * (c) 1999, Eric Valette valette@crf.canon.fr * * - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * exception veneers for RTEMS. * * $Id$ */ - + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include <bsp/vectors.h> - + #define SYNC \ sync; \ isync - + PUBLIC_VAR (__rtems_start) .section .entry_point_section,"awx",@progbits /* * Entry point information used by bootloader code */ -SYM (__rtems_start): +SYM (__rtems_start): .long __rtems_entry_point /* * end of special Entry point section - */ + */ .text - .p2align 5 - + .p2align 5 + PUBLIC_VAR(default_exception_vector_code_prolog) SYM (default_exception_vector_code_prolog): /* @@ -48,7 +48,7 @@ SYM (default_exception_vector_code_prolog): stw r3, EXC_LR_OFFSET(r1) bl 0f 0: /* - * r3 = exception vector entry point + * r3 = exception vector entry point * (256 * vector number) + few instructions */ mflr r3 @@ -57,13 +57,13 @@ SYM (default_exception_vector_code_prolog): */ srwi r3,r3,8 ba push_normalized_frame - + PUBLIC_VAR (default_exception_vector_code_prolog_size) - + default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog - + .p2align 5 -PUBLIC_VAR (push_normalized_frame) +PUBLIC_VAR (push_normalized_frame) SYM (push_normalized_frame): stw r3, EXCEPTION_NUMBER_OFFSET(r1) stw r0, GPR0_OFFSET(r1) @@ -77,7 +77,7 @@ SYM (push_normalized_frame): * Saved a few line above : R0 * * Manual says that "stmw" instruction may be slower than - * series of individual "stw" but who cares about performance + * series of individual "stw" but who cares about performance * for the DEFAULT exception handler? */ stmw r4, GPR4_OFFSET(r1) /* save R4->R31 */ @@ -107,7 +107,7 @@ SYM (push_normalized_frame): ori r3,r3, MSR_RI | MSR_IR | MSR_DR mtmsr r3 SYNC - + /* * Call C exception handler */ @@ -148,12 +148,12 @@ SYM (push_normalized_frame): /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC diff --git a/c/src/lib/libbsp/powerpc/shared/vectors/vectors.h b/c/src/lib/libbsp/powerpc/shared/vectors/vectors.h index f995b16303..976af3d7f4 100644 --- a/c/src/lib/libbsp/powerpc/shared/vectors/vectors.h +++ b/c/src/lib/libbsp/powerpc/shared/vectors/vectors.h @@ -1,4 +1,4 @@ -/* +/* * vectors.h Exception frame related contant and API. * * This include file describe the data structure and the functions implemented @@ -16,10 +16,10 @@ #define LIBBSP_POWERPC_MCP750_VECTORS_H /* - * The callee (high level exception code written in C) + * The callee (high level exception code written in C) * will store the Link Registers (return address) at entry r1 + 4 !!!. * So let room for it!!!. - */ + */ #define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 #define SRR0_FRAME_OFFSET 8 #define SRR1_FRAME_OFFSET 12 @@ -86,7 +86,7 @@ extern int default_exception_vector_code_prolog_size[]; * zero, it performs more or less like memmove. No copy is performed if * source and destination addresses are equal. However the caches * are synchronized. Note that the size is always rounded up to the - * next mutiple of 4. + * next mutiple of 4. */ extern void * codemove(void *, const void *, unsigned int, unsigned long); extern void initialize_exceptions(); diff --git a/c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c b/c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c index 0a8577b92d..c897d89159 100644 --- a/c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c +++ b/c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c @@ -1,4 +1,4 @@ -/* +/* * vectors_init.c Exception hanlding initialisation (and generic handler). * * This include file describe the data structure and the functions implemented @@ -72,7 +72,7 @@ void *lr; void C_exception_handler(BSP_Exception_frame* excPtr) { int recoverable = 0; - + printk("exception handler called for exception %d\n", excPtr->_EXC_number); printk("\t Next PC or Address of fault = %x\n", excPtr->EXC_SRR0); printk("\t Saved MSR = %x\n", excPtr->EXC_SRR1); @@ -119,7 +119,7 @@ void C_exception_handler(BSP_Exception_frame* excPtr) if (excPtr->_EXC_number == ASM_DEC_VECTOR) recoverable = 1; if (excPtr->_EXC_number == ASM_SYS_VECTOR) -#ifdef TEST_RAW_EXCEPTION_CODE +#ifdef TEST_RAW_EXCEPTION_CODE recoverable = 1; #else recoverable = 0; diff --git a/c/src/lib/libbsp/powerpc/shared/vme/VMEConfig.h b/c/src/lib/libbsp/powerpc/shared/vme/VMEConfig.h index 04347d270a..482e0bfc39 100644 --- a/c/src/lib/libbsp/powerpc/shared/vme/VMEConfig.h +++ b/c/src/lib/libbsp/powerpc/shared/vme/VMEConfig.h @@ -4,7 +4,7 @@ /* BSP specific address space configuration parameters */ -/* +/* * The BSP maps VME address ranges into * one BAT. * NOTE: the BSP (startup/bspstart.c) uses diff --git a/c/src/lib/libbsp/powerpc/ss555/clock/p_clock.c b/c/src/lib/libbsp/powerpc/ss555/clock/p_clock.c index 0a3b92c4c3..0cbda2f24a 100644 --- a/c/src/lib/libbsp/powerpc/ss555/clock/p_clock.c +++ b/c/src/lib/libbsp/powerpc/ss555/clock/p_clock.c @@ -63,6 +63,6 @@ int BSP_connect_clock_handler (rtems_irq_hdl hdl) clockIrqData.on = (rtems_irq_enable)clockOn; clockIrqData.off = (rtems_irq_enable)clockOff; clockIrqData.isOn = (rtems_irq_is_enabled)clockIsOn; - + return BSP_install_rtems_irq_handler (&clockIrqData); } diff --git a/c/src/lib/libbsp/powerpc/ss555/console/console.c b/c/src/lib/libbsp/powerpc/ss555/console/console.c index 810cf69bda..fdfbf88a73 100644 --- a/c/src/lib/libbsp/powerpc/ss555/console/console.c +++ b/c/src/lib/libbsp/powerpc/ss555/console/console.c @@ -18,7 +18,7 @@ * (although that would be easy to change). * * I/O may be interrupt-driven (recommended for real-time applications) or - * polled. + * polled. * * LIMITATIONS: * @@ -34,7 +34,7 @@ * Interrupt-driven I/O requires termios. * * TESTS: - * + * * TO RUN THE TESTS, USE POLLED I/O WITHOUT TERMIOS SUPPORT. Some tests * play with the interrupt masks and turn off I/O. Those tests will hang * when interrupt-driven I/O is used. Other tests, such as cdtest, do I/O @@ -44,17 +44,17 @@ * should all be fixed to work with interrupt-driven I/O and to * produce output in the expected sequence. Obviously, the termios test * requires termios support in the driver. - * + * * Set CONSOLE_MINOR to the appropriate device minor number in the * config file. This allows the RTEMS application console to be different * from the GDB port. - * + * * This driver handles both available serial ports: it distinguishes * the sub-devices using minor device numbers. It is not possible to have * other protocols running on the other ports when this driver is used as * currently written. * - * + * * SS555 port sponsored by Defence Research and Development Canada - Suffield * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) * @@ -133,7 +133,7 @@ static rtems_status_code do_poll_read( * Output characters through polled I/O. Returns only once every character has * been sent. * - * CR is transmitted AFTER a LF on output. + * CR is transmitted AFTER a LF on output. * * Input parameters: * major - ignored. Should be the major number for this driver. @@ -176,8 +176,8 @@ static rtems_status_code do_poll_write( static void _BSP_output_char( char c ) { char cr = '\r'; - - /* + + /* * Can't rely on console_initialize having been called before this * function is used, so it may fail. */ @@ -206,14 +206,14 @@ rtems_device_driver console_initialize( ) { rtems_status_code status; - + /* * Set up TERMIOS if needed */ #if UARTS_USE_TERMIOS == 1 rtems_termios_initialize (); #endif /* UARTS_USE_TERMIOS */ - + /* * Do device-specific initialization */ @@ -223,17 +223,17 @@ rtems_device_driver console_initialize( status = rtems_io_register_name ("/dev/tty0", major, SCI1_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + m5xx_uart_initialize(SCI2_MINOR); status = rtems_io_register_name ("/dev/tty1", major, SCI2_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + /* Now register the RTEMS console */ status = rtems_io_register_name ("/dev/console", major, CONSOLE_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + return RTEMS_SUCCESSFUL; } @@ -249,10 +249,10 @@ rtems_device_driver console_open( { rtems_status_code sc; - if ( minor > NUM_PORTS - 1 ) + if ( minor > NUM_PORTS - 1 ) return RTEMS_INVALID_NUMBER; - #if (UARTS_USE_TERMIOS == 1) + #if (UARTS_USE_TERMIOS == 1) { #if (UARTS_IO_MODE == 1) /* RTEMS interrupt-driven I/O with termios */ @@ -283,7 +283,7 @@ rtems_device_driver console_open( sc = rtems_termios_open( major, minor, arg, &callbacks ); #endif - + return sc; } @@ -365,7 +365,7 @@ rtems_device_driver console_control( rtems_device_minor_number minor, void *arg ) -{ +{ if ( minor > NUM_PORTS-1 ) return RTEMS_INVALID_NUMBER; diff --git a/c/src/lib/libbsp/powerpc/ss555/include/bsp.h b/c/src/lib/libbsp/powerpc/ss555/include/bsp.h index 03eb954350..fcc22c8b43 100644 --- a/c/src/lib/libbsp/powerpc/ss555/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/ss555/include/bsp.h @@ -40,7 +40,7 @@ extern "C" { /* * Clock definitions */ - + #define BSP_CRYSTAL_HZ 4000000 /* crystal frequency, Hz */ #define BSP_CLOCK_HZ 40000000 /* CPU clock frequency, Hz @@ -72,9 +72,9 @@ typedef struct cpld_ { rtems_unsigned8 nflash_writess; /* Enable/disable NAND-flash writes */ rtems_unsigned8 padA[0xC00000 - 0xA00002]; } cpld_t; - + extern volatile cpld_t cpld; /* defined in linkcmds */ - + /* * Define the time limits for RTEMS Test Suite test durations. * Long test and short test duration limits are provided. These @@ -154,7 +154,7 @@ extern rtems_configuration_table BSP_Configuration; /* * NOTE: Use the standard Console driver entry */ - + /* * NOTE: Use the standard Clock driver entry */ diff --git a/c/src/lib/libbsp/powerpc/ss555/irq/irq.h b/c/src/lib/libbsp/powerpc/ss555/irq/irq.h index 8265b84b70..34f7401380 100644 --- a/c/src/lib/libbsp/powerpc/ss555/irq/irq.h +++ b/c/src/lib/libbsp/powerpc/ss555/irq/irq.h @@ -38,8 +38,8 @@ extern "C" { /* * The SS555 has no external interrupt controller chip, so use the standard * routines from the CPU-dependent code. - */ -#define BSP_install_rtems_irq_handler(ptr) CPU_install_rtems_irq_handler(ptr) + */ +#define BSP_install_rtems_irq_handler(ptr) CPU_install_rtems_irq_handler(ptr) #define BSP_get_current_rtems_irq_handler(ptr) CPU_get_current_rtems_irq_handler(ptr) #define BSP_remove_rtems_irq_handler(ptr) CPU_remove_rtems_irq_handler(ptr) #define BSP_rtems_irq_mngt_set(config) CPU_rtems_irq_mngt_set(config) diff --git a/c/src/lib/libbsp/powerpc/ss555/startup/bspstart.c b/c/src/lib/libbsp/powerpc/ss555/startup/bspstart.c index 9e990f354a..626b510732 100644 --- a/c/src/lib/libbsp/powerpc/ss555/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/ss555/startup/bspstart.c @@ -64,13 +64,13 @@ void bsp_libc_init( void *, unsigned32, int ); void BSP_panic(char *s) { printk("%s PANIC %s\n",_RTEMS_version, s); - __asm__ __volatile ("sc"); + __asm__ __volatile ("sc"); } void _BSP_Fatal_error(unsigned int v) { printk("%s PANIC ERROR %x\n",_RTEMS_version, v); - __asm__ __volatile ("sc"); + __asm__ __volatile ("sc"); } /* @@ -95,7 +95,7 @@ void _BSP_Fatal_error(unsigned int v) */ void bsp_pretasking_hook(void) { - /* + /* * These are assigned addresses in the linkcmds file for the BSP. This * approach is better than having these defined as manifest constants and * compiled into the kernel, but it is still not ideal when dealing with @@ -105,13 +105,13 @@ void bsp_pretasking_hook(void) * the kernel and the application can be linked and burned into ROM * independently of each other. */ - unsigned char *_HeapStart = - (char*)BSP_Configuration.work_space_start + unsigned char *_HeapStart = + (char*)BSP_Configuration.work_space_start + BSP_Configuration.work_space_size; extern unsigned char _HeapEnd[]; bsp_libc_init( _HeapStart, _HeapEnd - _HeapStart, 0 ); - + #ifdef RTEMS_DEBUG rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); #endif @@ -141,11 +141,11 @@ void bsp_pretasking_hook(void) void bsp_start(void) { extern char _WorkspaceBase[]; - + ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; register unsigned char* intrStack; - + /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function stores the result in global variables so that it can be used @@ -190,7 +190,7 @@ void bsp_start(void) Cpu_table.clicks_per_usec = BSP_CRYSTAL_HZ / 4 / 1000000; Cpu_table.clock_speed = BSP_CLOCK_HZ; /* for SCI baud rate generator */ - /* + /* * Call this in case we use TERMIOS for console I/O */ m5xx_uart_reserve_resources( &BSP_Configuration ); diff --git a/c/src/lib/libbsp/powerpc/ss555/startup/iss555.c b/c/src/lib/libbsp/powerpc/ss555/startup/iss555.c index 34731848d2..133fad3b2d 100644 --- a/c/src/lib/libbsp/powerpc/ss555/startup/iss555.c +++ b/c/src/lib/libbsp/powerpc/ss555/startup/iss555.c @@ -38,7 +38,7 @@ void _InitSS555 (void) * Initialize the System Protection Control Register (SYPCR). * The SYPCR can only be written once after Reset. */ - usiu.sypcr = + usiu.sypcr = USIU_SYPCR_SWTC(WATCHDOG_TIMEOUT) /* set watchdog timeout */ | USIU_SYPCR_BMT(0xFF) /* set bus monitor timeout */ | USIU_SYPCR_BME /* enable bus monitor */ @@ -50,12 +50,12 @@ void _InitSS555 (void) | USIU_SYPCR_SWP; /* prescale watchdog by 2048 */ TICKLE_WATCHDOG(); /* restart watchdog timer */ - - /* + + /* * Re-tune the PLL to the desired system clock frequency. */ usiu.plprck = USIU_UNLOCK_KEY; /* unlock PLPRCR */ - usiu.plprcr = + usiu.plprcr = USIU_PLPRCR_TEXPS /* assert TEXP always */ | USIU_PLPRCR_MF(BSP_CLOCK_HZ / BSP_CRYSTAL_HZ); /* PLL multiplication factor */ @@ -63,11 +63,11 @@ void _InitSS555 (void) while (((plprcr = usiu.plprcr) & USIU_PLPRCR_SPLS) == 0) ; /* wait for PLL to re-lock */ - - /* + + /* * Enable the timebase and decrementer, then initialize decrementer * register to a large value to guarantee that a decrementer interrupt - * will not be generated before the kernel is fully initialized. + * will not be generated before the kernel is fully initialized. * Initialize the timebase register to zero. */ usiu.tbscrk = USIU_UNLOCK_KEY; @@ -84,7 +84,7 @@ void _InitSS555 (void) * Run the Inter-Module Bus at full speed. */ imb.uimb.umcr &= ~UIMB_UMCR_HSPEED; - + /* * Initialize Memory Controller for External RAM * @@ -96,19 +96,19 @@ void _InitSS555 (void) * zero but set it up appropriately. */ extern char int_ram_top[]; /* top of internal ram */ - + usiu.memc[0]._or = USIU_MEMC_OR_512K /* bank size */ | USIU_MEMC_OR_SCY(0) /* wait states in first beat of burst */ | USIU_MEMC_OR_BSCY(0); /* wait states in subsequent beats */ - + usiu.memc[0]._br = - USIU_MEMC_BR_BA(_read_IMMR() & IMMR_FLEN + USIU_MEMC_BR_BA(_read_IMMR() & IMMR_FLEN ? (rtems_unsigned32)int_ram_top : 0) /* base address */ | USIU_MEMC_BR_PS32 /* 32-bit data bus */ | USIU_MEMC_BR_TBDIP /* toggle bdip */ | USIU_MEMC_BR_V; /* base register valid */ - + /* * Initialize Memory Controller for External CPLD * @@ -120,21 +120,21 @@ void _InitSS555 (void) | USIU_MEMC_OR_CSNT /* negate CS/WE early */ | USIU_MEMC_OR_ACS_HALF /* assert CS half cycle after address */ | USIU_MEMC_OR_SCY(15) /* wait states in first beat of burst */ - | USIU_MEMC_OR_TRLX; /* relaxed timing */ + | USIU_MEMC_OR_TRLX; /* relaxed timing */ usiu.memc[3]._br = USIU_MEMC_BR_BA(&cpld) /* base address */ | USIU_MEMC_BR_PS16 /* 16-bit data bus */ | USIU_MEMC_BR_BI /* inhibit bursting */ | USIU_MEMC_BR_V; /* base register valid */ - + /* * Disable show cycles and serialization so that burst accesses will work * properly. A different value, such as 0x0, may be more appropriate for * debugging, but can be set with the debugger, if needed. */ _write_ICTRL(0x00000007); - + /* * Set up Burst Buffer Controller (BBC) */ @@ -144,6 +144,6 @@ void _InitSS555 (void) _isync; _CPU_MSR_GET(msr); - msr |= MSR_IP; /* set prefix for exception relocation */ + msr |= MSR_IP; /* set prefix for exception relocation */ _CPU_MSR_SET(msr); } diff --git a/c/src/lib/libbsp/powerpc/ss555/startup/start.S b/c/src/lib/libbsp/powerpc/ss555/startup/start.S index ec759f1fa6..73a4606a8d 100644 --- a/c/src/lib/libbsp/powerpc/ss555/startup/start.S +++ b/c/src/lib/libbsp/powerpc/ss555/startup/start.S @@ -5,28 +5,28 @@ * all remaining initialization. * * This file is based on several others: - * - * (1) start360.s from the gen68360 BSP by + * + * (1) start360.s from the gen68360 BSP by * W. Eric Norum (eric@skatter.usask.ca) * with the following copyright and license: * * COPYRIGHT (c) 1989-1998. * On-Line Applications Research Corporation (OAR). - * + * * The license and distribution terms for this file may in * the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * * (2) start.s for the eth_comm port by * Jay Monkman (jmonkman@fracsa.com), - * which itself is based on the - * + * which itself is based on the + * * (3) dlentry.s for the Papyrus BSP, written by: * Andrew Bray <andy@i-cubed.co.uk> * with the following copyright and license: * * COPYRIGHT (c) 1995 by i-cubed ltd. - * + * * (4) start860.S for the MBX821/MBX860, written by: * Darlene A. Stewart <darlene.stewart@iit.nrc.ca> * Copyright (c) 1999, National Research Council of Canada @@ -182,7 +182,7 @@ .L_D4_e: .L_D2: .previous - + /* * Tell C's eabi-ctor's that we have an atexit function, * and that it is to register __do_global_dtors. @@ -191,7 +191,7 @@ PUBLIC_VAR(__atexit) .section ".sdata","aw" .align 2 -SYM(__atexit): +SYM(__atexit): EXT_PROC_REF(atexit)@fixup .previous @@ -201,7 +201,7 @@ SYM(__atexit): .previous /* That should do it */ - + /* * Put the entry point in its own section. That way, we can guarantee * to put it first in the .text section in the linker script. @@ -211,7 +211,7 @@ SYM(__atexit): PUBLIC_VAR (start) SYM(start): bl .startup /* or bl .spin */ -base_addr: +base_addr: /* * Parameters from linker @@ -219,19 +219,19 @@ base_addr: stack_top: .long initStackPtr -toc_pointer: +toc_pointer: .long __GOT_START__ -bss_length: +bss_length: .long bss.size -bss_addr: +bss_addr: .long bss.start -data_length: +data_length: .long data.size -data_addr: +data_addr: .long data.start -contents_addr: +contents_addr: .long data.contents.start PUBLIC_VAR (text_addr) @@ -244,7 +244,7 @@ text_length: /* * Spin, if necessary, to acquire control from debugger (CodeWarrior). - */ + */ spin: .long 0x0001 .spin: @@ -254,9 +254,9 @@ spin: beq .spin /* - * Initialization code + * Initialization code */ -.startup: +.startup: /* Capture address of linker parameters. */ mflr r3 @@ -273,7 +273,7 @@ spin: /* Initialize the memory mapped MPC555 registers (done in C). */ EXTERN_PROC (_InitSS555) bl PROC (_InitSS555) - + /* Clear the .bss section. */ bl bssclr @@ -295,7 +295,7 @@ spin: li r3, 0 /* argc */ EXTERN_PROC (boot_card) bl PROC (boot_card) /* call the first C routine */ - + /* We should never return from boot_card, but in case we do ... */ /* The next instructions are dependent on your runtime environment. */ @@ -323,7 +323,7 @@ dc1: addi r4, r4, 0x4 /* next source */ addi r5, r5, 0x4 /* next target */ bdnz dc1 /* dec counter and loop */ - + blr /* return */ /* @@ -345,7 +345,7 @@ clear_bss: stw r5, 0(r4) /* store r6 */ addi r4, r4, 0x4 /* update r4 */ bdnz clear_bss /* dec counter and loop */ - + blr /* return */ /* @@ -356,7 +356,7 @@ clear_bss: * r0 - scratch */ initregs: - /* + /* * Set the processor for big-endian mode, exceptions vectored to * 0x000n_nnnn, no execution tracing, machine check exceptions * enabled, floating-point not available, supervisor priviledge @@ -366,10 +366,10 @@ initregs: li r0, 0x1000 /* MSR_ME */ mtmsr r0 /* Context-synchronizing */ isync - + /* * Clear the exception handling registers. - */ + */ li r0, 0x0000 mtdar r0 mtspr sprg0, r0 @@ -378,13 +378,13 @@ initregs: mtspr sprg3, r0 mtspr srr0, r0 mtspr srr1, r0 - + mr r6, r0 mr r7, r0 mr r8, r0 mr r9, r0 mr r10, r0 - mr r11, r0 + mr r11, r0 mr r12, r0 mr r13, r0 mr r14, r0 @@ -405,9 +405,9 @@ initregs: mr r29, r0 mr r30, r0 mr r31, r0 - + blr /* return */ - + .L_text_e: .comm environ,4,4 diff --git a/c/src/lib/libbsp/powerpc/ss555/wrapup/Makefile.am b/c/src/lib/libbsp/powerpc/ss555/wrapup/Makefile.am index f50a893094..e4652a6b5d 100644 --- a/c/src/lib/libbsp/powerpc/ss555/wrapup/Makefile.am +++ b/c/src/lib/libbsp/powerpc/ss555/wrapup/Makefile.am @@ -9,7 +9,7 @@ CLEANFILES = ../libbsp.a ___libbsp_a_SOURCES = ___libbsp_a_LIBADD = ../pclock$(LIB_VARIANT).rel \ - ../console$(LIB_VARIANT).rel ../startup$(LIB_VARIANT).rel + ../console$(LIB_VARIANT).rel ../startup$(LIB_VARIANT).rel ___libbsp_a_LIBADD += \ ../../../../libcpu/powerpc/shared/cpuIdent$(LIB_VARIANT).rel \ diff --git a/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c b/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c index f31add1feb..660747d5b8 100644 --- a/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c +++ b/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c @@ -83,7 +83,7 @@ void _CPU_Context_Initialize( *((uint32_t*)sp) = 0; the_context->gpr1 = sp; - + _CPU_MSR_GET( msr_value ); if (!(new_level & CPU_MODES_INTERRUPT_MASK)) { @@ -97,7 +97,7 @@ void _CPU_Context_Initialize( /* * The FP bit of the MSR should only be enabled if this is a floating - * point task. Unfortunately, the vfprintf_r routine in newlib + * point task. Unfortunately, the vfprintf_r routine in newlib * ends up pushing a floating point register regardless of whether or * not a floating point number is being printed. Serious restructuring * of vfprintf.c will be required to avoid this behavior. At this @@ -124,14 +124,14 @@ void _CPU_Context_Initialize( #if (PPC_ABI == PPC_ABI_SVR4) { unsigned r13 = 0; asm volatile ("mr %0, 13" : "=r" ((r13))); - + the_context->gpr13 = r13; } #elif (PPC_ABI == PPC_ABI_EABI) { uint32_t r2 = 0; unsigned r13 = 0; asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); - + the_context->gpr2 = r2; the_context->gpr13 = r13; } diff --git a/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu_asm.S b/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu_asm.S index 847091f6c9..74845982b2 100644 --- a/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu_asm.S +++ b/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu_asm.S @@ -109,7 +109,7 @@ .set FP_30, (FP_29 + FP_SIZE) .set FP_31, (FP_30 + FP_SIZE) .set FP_FPSCR, (FP_31 + FP_SIZE) - + .set IP_LINK, 0 .set IP_0, (IP_LINK + 8) .set IP_2, (IP_0 + 4) @@ -118,12 +118,12 @@ .set IP_4, (IP_3 + 4) .set IP_5, (IP_4 + 4) .set IP_6, (IP_5 + 4) - + .set IP_7, (IP_6 + 4) .set IP_8, (IP_7 + 4) .set IP_9, (IP_8 + 4) .set IP_10, (IP_9 + 4) - + .set IP_11, (IP_10 + 4) .set IP_12, (IP_11 + 4) .set IP_13, (IP_12 + 4) @@ -133,15 +133,15 @@ .set IP_30, (IP_29 + 4) .set IP_31, (IP_30 + 4) .set IP_CR, (IP_31 + 4) - + .set IP_CTR, (IP_CR + 4) .set IP_XER, (IP_CTR + 4) .set IP_LR, (IP_XER + 4) .set IP_PC, (IP_LR + 4) - + .set IP_MSR, (IP_PC + 4) .set IP_END, (IP_MSR + 16) - + BEGIN_CODE /* * _CPU_Context_save_fp_context diff --git a/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c b/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c index 77f10642a8..11ddae9bf6 100644 --- a/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c +++ b/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c @@ -93,7 +93,7 @@ void _CPU_Initialize( * Store Msr Value in the IRQ info structure. */ _CPU_MSR_Value(_CPU_IRQ_info.msr_initial); - + #if (PPC_USE_SPRG) i = _CPU_IRQ_info.msr_initial; asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */ @@ -111,7 +111,7 @@ void _CPU_Initialize( * * Complete initialization since the table is now allocated. */ - + void _CPU_Initialize_vectors(void) { int i; @@ -126,7 +126,7 @@ void _CPU_Initialize_vectors(void) _ISR_Vector_table[i] = handler; } - + /*PAGE * * _CPU_ISR_Calculate_level @@ -137,7 +137,7 @@ void _CPU_Initialize_vectors(void) * is why it was necessary to adopt a scheme which allowed the user * to specify specifically which interrupt sources were enabled. */ - + uint32_t _CPU_ISR_Calculate_level( uint32_t new_level ) @@ -189,7 +189,7 @@ void _CPU_ISR_Set_level( * * _CPU_ISR_Get_level * - * This routine gets the current interrupt level from the MSR and + * This routine gets the current interrupt level from the MSR and * converts it to an RTEMS interrupt level. */ @@ -197,9 +197,9 @@ uint32_t _CPU_ISR_Get_level( void ) { uint32_t level = 0; uint32_t msr; - + asm volatile("mfmsr %0" : "=r" ((msr))); - + msr &= PPC_MSR_DISABLE_MASK; /* @@ -246,12 +246,12 @@ void _CPU_Context_Initialize( sp = (uint32_t)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE; *((uint32_t*)sp) = 0; the_context->gpr1 = sp; - + the_context->msr = _CPU_ISR_Calculate_level( new_level ); /* * The FP bit of the MSR should only be enabled if this is a floating - * point task. Unfortunately, the vfprintf_r routine in newlib + * point task. Unfortunately, the vfprintf_r routine in newlib * ends up pushing a floating point register regardless of whether or * not a floating point number is being printed. Serious restructuring * of vfprintf.c will be required to avoid this behavior. At this @@ -266,7 +266,7 @@ void _CPU_Context_Initialize( * * + Set the exception prefix bit to point to the exception table * + Force the RI bit - * + Use the DR and IR bits + * + Use the DR and IR bits */ _CPU_MSR_Value( msr_value ); the_context->msr |= (msr_value & PPC_MSR_EP); @@ -284,7 +284,7 @@ void _CPU_Context_Initialize( #if (PPC_ABI == PPC_ABI_SVR4) { unsigned r13 = 0; asm volatile ("mr %0, 13" : "=r" ((r13))); - + the_context->pc = (uint32_t)entry_point; the_context->gpr13 = r13; } @@ -294,7 +294,7 @@ void _CPU_Context_Initialize( { uint32_t r2 = 0; unsigned r13 = 0; asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); - + the_context->pc = (uint32_t)entry_point; the_context->gpr2 = r2; the_context->gpr13 = r13; @@ -335,7 +335,7 @@ void _CPU_ISR_install_vector( /* * Install the wrapper so this ISR can be invoked properly. */ - if (_CPU_Table.exceptions_in_RAM) + if (_CPU_Table.exceptions_in_RAM) _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); /* @@ -344,7 +344,7 @@ void _CPU_ISR_install_vector( */ _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler : - _CPU_Table.spurious_handler ? + _CPU_Table.spurious_handler ? (ISR_Handler_entry)_CPU_Table.spurious_handler : (ISR_Handler_entry)ppc_spurious; } @@ -440,7 +440,7 @@ const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = { }; #endif /* mpc860 */ -uint32_t ppc_exception_vector_addr( +uint32_t ppc_exception_vector_addr( uint32_t vector ); @@ -453,24 +453,24 @@ uint32_t ppc_exception_vector_addr( * supported trap handler (a.k.a. interrupt service routine). * * Input Parameters: - * vector - trap table entry number plus synchronous + * vector - trap table entry number plus synchronous * vs. asynchronous information * new_handler - address of the handler to be installed * old_handler - pointer to an address of the handler previously installed * * Output Parameters: NONE * *new_handler - address of the handler previously installed - * - * NOTE: + * + * NOTE: * * This routine is based on the SPARC routine _CPU_ISR_install_raw_handler. - * Install a software trap handler as an executive interrupt handler + * Install a software trap handler as an executive interrupt handler * (which is desirable since RTEMS takes care of window and register issues), - * then the executive needs to know that the return address is to the trap + * then the executive needs to know that the return address is to the trap * rather than the instruction following the trap. * */ - + void _CPU_ISR_install_raw_handler( uint32_t vector, proc_ptr new_handler, @@ -506,8 +506,8 @@ void _CPU_ISR_install_raw_handler( #define LOW_BITS_MASK 0x000003FF if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) { - /* - * Set u32_handler = to target address + /* + * Set u32_handler = to target address */ u32_handler = slot->b_Handler & 0x03fffffc; @@ -518,15 +518,15 @@ void _CPU_ISR_install_raw_handler( *old_handler = (proc_ptr) u32_handler; } else -/* There are two kinds of handlers for the MPC860. One is the 'standard' +/* There are two kinds of handlers for the MPC860. One is the 'standard' * one like above. The other is for the cascaded interrupts from the SIU * and CPM. Therefore we must check for the alternate one if the standard * one is not present */ #if defined(mpc860) || defined(mpc821) if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) { - /* - * Set u32_handler = to target address + /* + * Set u32_handler = to target address */ u32_handler = slot->b_Handler & 0x03fffffc; *old_handler = (proc_ptr) u32_handler; @@ -547,9 +547,9 @@ void _CPU_ISR_install_raw_handler( u32_handler = (uint32_t) new_handler; - /* - * IMD FIX: insert address fragment only (bits 6..29) - * therefore check for proper address range + /* + * IMD FIX: insert address fragment only (bits 6..29) + * therefore check for proper address range * and remove unwanted bits */ if ((u32_handler & 0xfc000000) == 0xfc000000) { @@ -568,7 +568,7 @@ void _CPU_ISR_install_raw_handler( _CPU_Data_Cache_Block_Flush( slot ); } -uint32_t ppc_exception_vector_addr( +uint32_t ppc_exception_vector_addr( uint32_t vector ) { @@ -632,7 +632,7 @@ uint32_t ppc_exception_vector_addr( break; #if defined(ppc403) || defined(ppc405) - + /* PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET case PPC_IRQ_CRIT: Offset = 0x00100; diff --git a/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu_asm.S b/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu_asm.S index 1aed87b6ac..cd35eb02af 100644 --- a/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu_asm.S +++ b/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu_asm.S @@ -38,7 +38,7 @@ #include <rtems/asm.h> #include <rtems/score/ppc_offs.h> - + BEGIN_CODE /* * _CPU_Context_save_fp_context @@ -365,7 +365,7 @@ PROC (_CPU_Context_switch): stw r7, GP_PC-GP_26(r3) mfmsr r8 stw r8, GP_MSR-GP_26(r3) - + #if ( PPC_USE_DATA_CACHE ) dcbt r5, r4 #endif diff --git a/c/src/lib/libbsp/powerpc/support/old_exception_processing/irq_stub.S b/c/src/lib/libbsp/powerpc/support/old_exception_processing/irq_stub.S index 71c6332a41..6a0dd00342 100644 --- a/c/src/lib/libbsp/powerpc/support/old_exception_processing/irq_stub.S +++ b/c/src/lib/libbsp/powerpc/support/old_exception_processing/irq_stub.S @@ -74,7 +74,7 @@ slwi r4,r0,2 lwz r28, Nest_level(r11) add r4, r4, r30 - + lwz r30, 0(r28) mr r3, r0 lwz r31, Stack(r11) @@ -86,14 +86,14 @@ */ /* Switch stacks, here we must prevent ALL interrupts */ #if (PPC_USE_SPRG) - mfmsr r5 - mfspr r6, sprg2 -#else + mfmsr r5 + mfspr r6, sprg2 +#else lwz r6,msr_initial(r11) lis r5,~PPC_MSR_DISABLE_MASK@ha ori r5,r5,~PPC_MSR_DISABLE_MASK@l and r6,r6,r5 - mfmsr r5 + mfmsr r5 #endif mtmsr r6 cmpwi r30, 0 @@ -154,10 +154,10 @@ LABEL (nested): /* We must re-disable the interrupts */ #if (PPC_USE_SPRG) mfspr r11, sprg3 - mfspr r0, sprg2 + mfspr r0, sprg2 #else lis r11,_CPU_IRQ_info@ha - addi r11,r11,_CPU_IRQ_info@l + addi r11,r11,_CPU_IRQ_info@l lwz r0,msr_initial(r11) lis r30,~PPC_MSR_DISABLE_MASK@ha ori r30,r30,~PPC_MSR_DISABLE_MASK@l @@ -190,8 +190,8 @@ LABEL (nested): bne LABEL (easy_exit) lwz r30, 0(r30) lwz r31, Signal(r11) - - /* + + /* * if ( _Context_Switch_necessary ) * goto switch */ @@ -199,7 +199,7 @@ LABEL (nested): lwz r28, 0(r31) li r6,0 bne LABEL (switch) - /* + /* * if ( !_ISR_Signals_to_thread_executing ) * goto easy_exit * _ISR_Signals_to_thread_executing = 0; @@ -232,14 +232,14 @@ LABEL (switch): mfspr r0, sprg2 #else lis r11,_CPU_IRQ_info@ha - addi r11,r11,_CPU_IRQ_info@l + addi r11,r11,_CPU_IRQ_info@l lwz r0,msr_initial(r11) lis r5,~PPC_MSR_DISABLE_MASK@ha ori r5,r5,~PPC_MSR_DISABLE_MASK@l and r0,r0,r5 #endif mtmsr r0 - + /* * easy_exit: * prepare to get out of interrupt diff --git a/c/src/lib/libbsp/powerpc/support/old_exception_processing/rtems/score/ppc_offs.h b/c/src/lib/libbsp/powerpc/support/old_exception_processing/rtems/score/ppc_offs.h index d319107aaa..05a4fddb8f 100644 --- a/c/src/lib/libbsp/powerpc/support/old_exception_processing/rtems/score/ppc_offs.h +++ b/c/src/lib/libbsp/powerpc/support/old_exception_processing/rtems/score/ppc_offs.h @@ -104,7 +104,7 @@ .set FP_31, (FP_30 + 4) .set FP_FPSCR, (FP_31 + 4) #endif - + .set IP_LINK, 0 #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) .set IP_0, (IP_LINK + 56) @@ -117,12 +117,12 @@ .set IP_4, (IP_3 + 4) .set IP_5, (IP_4 + 4) .set IP_6, (IP_5 + 4) - + .set IP_7, (IP_6 + 4) .set IP_8, (IP_7 + 4) .set IP_9, (IP_8 + 4) .set IP_10, (IP_9 + 4) - + .set IP_11, (IP_10 + 4) .set IP_12, (IP_11 + 4) .set IP_13, (IP_12 + 4) @@ -132,15 +132,15 @@ .set IP_30, (IP_29 + 4) .set IP_31, (IP_30 + 4) .set IP_CR, (IP_31 + 4) - + .set IP_CTR, (IP_CR + 4) .set IP_XER, (IP_CTR + 4) .set IP_LR, (IP_XER + 4) .set IP_PC, (IP_LR + 4) - + .set IP_MSR, (IP_PC + 4) .set IP_END, (IP_MSR + 16) - + /* _CPU_IRQ_info offsets */ /* These must be in this order */ @@ -162,5 +162,5 @@ #endif .set Signal, Switch_necessary + 4 .set msr_initial, Signal + 4 - + #endif /* __PPC_OFFS_H */ |