diff options
Diffstat (limited to 'c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c index f226e56df9..adc3c0491d 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c @@ -1,7 +1,7 @@ -/* +/* * mmutlbtab.c - * - * This file defines the MMU_TLB_table for the eth_comm board. + * + * This file defines the MMU_TLB_table for the eth_comm board. * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -25,20 +25,20 @@ * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must * not have more than 32 lines in it! * - * We set up the virtual memory map so that virtual address of a + * We set up the virtual memory map so that virtual address of a * location is equal to its real address. */ MMU_TLB_table_t MMU_TLB_table[] = { /* - * DRAM: CS1, Start address 0x00000000, 8M, - * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * DRAM: CS1, Start address 0x00000000, 8M, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, * R/W,X for supervisor, no ASID comparison, not cache-inhibited. * EPN TWC RPN */ { 0x00000200, 0x0D, 0x000001FD } /* DRAM - PS=PS=8M */ }; -/* +/* * MMU_N_TLB_Table_Entries is defined here because the size of the * MMU_TLB_table is only known in this file. */ |