diff options
Diffstat (limited to 'bsps/include')
178 files changed, 29184 insertions, 637 deletions
diff --git a/bsps/include/bsp/bootcard.h b/bsps/include/bsp/bootcard.h index 6e28e6508f..5f339d65f8 100644 --- a/bsps/include/bsp/bootcard.h +++ b/bsps/include/bsp/bootcard.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -5,11 +7,28 @@ */ /* - * Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved. + * Copyright (C) 2008, 2014 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_SHARED_BOOTCARD_H diff --git a/bsps/include/bsp/console-termios.h b/bsps/include/bsp/console-termios.h index 58e58c5cd5..f82c7eee4e 100644 --- a/bsps/include/bsp/console-termios.h +++ b/bsps/include/bsp/console-termios.h @@ -1,9 +1,28 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* - * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2014 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef BSP_CONSOLE_TERMIOS_H diff --git a/bsps/include/bsp/default-initial-extension.h b/bsps/include/bsp/default-initial-extension.h index 5192d18394..a29d5415ea 100644 --- a/bsps/include/bsp/default-initial-extension.h +++ b/bsps/include/bsp/default-initial-extension.h @@ -10,7 +10,7 @@ */ /* - * Copyright (C) 2012 embedded brains GmbH + * Copyright (C) 2012 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h index 4df5f26455..87fc481ead 100644 --- a/bsps/include/bsp/fatal.h +++ b/bsps/include/bsp/fatal.h @@ -9,7 +9,7 @@ */ /* - * Copyright (C) 2012, 2022 embedded brains GmbH + * Copyright (C) 2012, 2022 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -72,6 +72,8 @@ typedef enum { BSP_FATAL_CONSOLE_INSTALL_0, BSP_FATAL_CONSOLE_INSTALL_1, BSP_FATAL_CONSOLE_REGISTER_DEV_2, + BSP_FATAL_MMU_ADDRESS_INVALID, + BSP_FATAL_HEAP_EXTEND_ERROR, /* ARM fatal codes */ BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(1), @@ -89,7 +91,6 @@ typedef enum { LEON3_FATAL_CLOCK_INITIALIZATION, LEON3_FATAL_INVALID_CACHE_CONFIG_BOOT_PROCESSOR, LEON3_FATAL_INVALID_CACHE_CONFIG_SECONDARY_PROCESSOR, - LEON3_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT, /* LPC24XX fatal codes */ LPC24XX_FATAL_PL111_SET_UP = BSP_FATAL_CODE_BLOCK(3), @@ -157,6 +158,8 @@ typedef enum { QORIQ_FATAL_RESTART_FAILED, QORIQ_FATAL_RESTART_INSTALL_INTERRUPT, QORIQ_FATAL_RESTART_INTERRUPT_FAILED, + QORIQ_FATAL_CLOCK_INTERRUPT_INSTALL, + QORIQ_FATAL_CLOCK_INTERRUPT_SET_PRIORITY, /* ATSAM fatal codes */ ATSAM_FATAL_XDMA_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(11), @@ -183,10 +186,13 @@ typedef enum { RISCV_FATAL_NO_PLIC_REG_IN_DEVICE_TREE, RISCV_FATAL_INVALID_PLIC_NDEV_IN_DEVICE_TREE, RISCV_FATAL_TOO_LARGE_PLIC_NDEV_IN_DEVICE_TREE, - RISCV_FATAL_INVALID_INTERRUPT_AFFINITY, + RISCV_FATAL_UNUSED_0, RISCV_FATAL_NO_NS16550_INTERRUPTS_IN_DEVICE_TREE, RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE, RISCV_FATAL_CLOCK_SMP_INIT, + RISCV_FATAL_NO_APBUART_REG_IN_DEVICE_TREE, + RISCV_FATAL_NO_APBUART_INTERRUPTS_IN_DEVICE_TREE, + RISCV_FATAL_NO_APBUART_CLOCK_FREQUENCY_IN_DEVICE_TREE, /* GRLIB fatal codes */ GRLIB_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT = BSP_FATAL_CODE_BLOCK(14), @@ -208,6 +214,9 @@ typedef enum { /* MicroBlaze fatal codes */ MICROBLAZE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(16), + + /* Xilinx fatal codes */ + XIL_FATAL_TTC_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(17), } bsp_fatal_code; RTEMS_NO_RETURN static inline void diff --git a/bsps/include/bsp/fdt.h b/bsps/include/bsp/fdt.h index 670b5284b3..a8d6764c72 100644 --- a/bsps/include/bsp/fdt.h +++ b/bsps/include/bsp/fdt.h @@ -1,9 +1,28 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* - * Copyright (c) 2015, 2017 embedded brains GmbH. All rights reserved. + * Copyright (C) 2015, 2017 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_SHARED_FDT_H diff --git a/bsps/include/bsp/irq-default.h b/bsps/include/bsp/irq-default.h index 8aacb4fec3..fff68c3db2 100644 --- a/bsps/include/bsp/irq-default.h +++ b/bsps/include/bsp/irq-default.h @@ -7,7 +7,7 @@ */ /* - * Copyright (C) 2019 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2019 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/include/bsp/irq-generic.h b/bsps/include/bsp/irq-generic.h index fa1343a990..3aef0be855 100644 --- a/bsps/include/bsp/irq-generic.h +++ b/bsps/include/bsp/irq-generic.h @@ -3,16 +3,16 @@ /** * @file * - * @ingroup bsp_interrupt + * @ingroup RTEMSImplClassicIntr * - * @brief This header file provides interfaces of the generic interrupt - * controller support. + * @brief This header file provides interfaces of the Interrupt Manager + * implementation. */ /* * Copyright (C) 2016 Chris Johns <chrisj@rtems.org> * - * Copyright (C) 2008, 2021 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2008, 2024 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -47,6 +47,7 @@ #include <rtems/irq-extension.h> #include <rtems/score/assert.h> +#include <rtems/score/processormask.h> #ifdef RTEMS_SMP #include <rtems/score/atomic.h> @@ -62,12 +63,12 @@ extern "C" { #error "BSP_INTERRUPT_VECTOR_COUNT shall be defined" #endif -#if defined(BSP_INTERRUPT_USE_INDEX_TABLE) && !defined(BSP_INTERRUPT_HANDLER_TABLE_SIZE) - #error "if you define BSP_INTERRUPT_USE_INDEX_TABLE, you have to define BSP_INTERRUPT_HANDLER_TABLE_SIZE etc. as well" +#if defined(BSP_INTERRUPT_USE_INDEX_TABLE) && !defined(BSP_INTERRUPT_DISPATCH_TABLE_SIZE) + #error "if you define BSP_INTERRUPT_USE_INDEX_TABLE, you have to define BSP_INTERRUPT_DISPATCH_TABLE_SIZE etc. as well" #endif -#ifndef BSP_INTERRUPT_HANDLER_TABLE_SIZE - #define BSP_INTERRUPT_HANDLER_TABLE_SIZE BSP_INTERRUPT_VECTOR_COUNT +#ifndef BSP_INTERRUPT_DISPATCH_TABLE_SIZE + #define BSP_INTERRUPT_DISPATCH_TABLE_SIZE BSP_INTERRUPT_VECTOR_COUNT #endif #define bsp_interrupt_assert(e) _Assert(e) @@ -76,56 +77,54 @@ extern "C" { * @brief Each member of this table references the first installed entry at the * corresponding interrupt vector or is NULL. */ -extern rtems_interrupt_entry *bsp_interrupt_handler_table[]; +extern rtems_interrupt_entry *bsp_interrupt_dispatch_table[]; #ifdef BSP_INTERRUPT_USE_INDEX_TABLE - #if BSP_INTERRUPT_HANDLER_TABLE_SIZE < 0x100 - typedef uint8_t bsp_interrupt_handler_index_type; - #elif BSP_INTERRUPT_HANDLER_TABLE_SIZE < 0x10000 - typedef uint16_t bsp_interrupt_handler_index_type; + #if BSP_INTERRUPT_DISPATCH_TABLE_SIZE < 0x100 + typedef uint8_t bsp_interrupt_dispatch_index_type; + #elif BSP_INTERRUPT_DISPATCH_TABLE_SIZE < 0x10000 + typedef uint16_t bsp_interrupt_dispatch_index_type; #else - typedef uint32_t bsp_interrupt_handler_index_type; + typedef uint32_t bsp_interrupt_dispatch_index_type; #endif - extern bsp_interrupt_handler_index_type bsp_interrupt_handler_index_table []; + extern bsp_interrupt_dispatch_index_type bsp_interrupt_dispatch_index_table []; #endif -static inline rtems_vector_number bsp_interrupt_handler_index( +static inline rtems_vector_number bsp_interrupt_dispatch_index( rtems_vector_number vector ) { #ifdef BSP_INTERRUPT_USE_INDEX_TABLE - return bsp_interrupt_handler_index_table [vector]; + return bsp_interrupt_dispatch_index_table [vector]; #else return vector; #endif } /** - * @defgroup bsp_interrupt BSP Interrupt Support + * @defgroup RTEMSImplClassicIntr Interrupt Manager * - * @ingroup RTEMSBSPsShared + * @ingroup RTEMSImplClassic * - * @brief Generic BSP Interrupt Support + * @brief This group contains the Interrupt Manager implementation. * - * The BSP interrupt support manages a sequence of interrupt vector numbers - * greater than or equal to zero and less than @ref BSP_INTERRUPT_VECTOR_COUNT - * It provides methods to - * @ref bsp_interrupt_handler_install() "install", - * @ref bsp_interrupt_handler_remove() "remove" and - * @ref bsp_interrupt_handler_dispatch() "dispatch" interrupt handlers for each - * vector number. It implements parts of the RTEMS interrupt manager. + * The Interrupt Manager implementation manages a sequence of interrupt vector + * numbers greater than or equal to zero and less than + * ``BSP_INTERRUPT_VECTOR_COUNT``. It provides methods to install, remove, and + * dispatch interrupt entries for each vector number, see + * bsp_interrupt_dispatch_entries(). * - * The entry points to a list of interrupt handlers are stored in a table - * (= handler table). + * The entry points to a list of interrupt entries are stored in a table + * (= dispatch table). * - * You have to configure the BSP interrupt support in the <bsp/irq.h> file + * You have to configure the Interrupt Manager implementation in the <bsp/irq.h> file * for each BSP. For a minimum configuration you have to provide - * @ref BSP_INTERRUPT_VECTOR_COUNT. + * ``BSP_INTERRUPT_VECTOR_COUNT``. * * For boards with small memory requirements you can define - * @ref BSP_INTERRUPT_USE_INDEX_TABLE. With an enabled index table the handler - * table will be accessed via a small index table. You can define the size of - * the handler table with @ref BSP_INTERRUPT_HANDLER_TABLE_SIZE. + * ``BSP_INTERRUPT_USE_INDEX_TABLE``. With an enabled index table the + * dispatch table will be accessed via a small index table. You can define the + * size of the dispatch table with ``BSP_INTERRUPT_DISPATCH_TABLE_SIZE``. * * You have to provide some special routines in your BSP (follow the links for * the details): @@ -177,10 +176,10 @@ static inline rtems_vector_number bsp_interrupt_handler_index( void bsp_interrupt_handler_default(rtems_vector_number vector); /** - * @brief Initialize BSP interrupt support. + * @brief Initialize Interrupt Manager implementation. * * You must call this function before you can install, remove and dispatch - * interrupt handlers. There is no protection against concurrent + * interrupt entries. There is no protection against concurrent * initialization. This function must be called at most once. The BSP * specific bsp_interrupt_facility_initialize() function will be called after * all internals are initialized. If the BSP specific initialization fails, @@ -249,8 +248,8 @@ rtems_status_code bsp_interrupt_vector_is_enabled( * @brief Enables the interrupt vector. * * This function shall enable the vector at the corresponding facility (in most - * cases the interrupt controller). It will be called then the first handler - * is installed for the vector in bsp_interrupt_handler_install() for example. + * cases the interrupt controller). It will be called then the first entry + * is installed for the vector in rtems_interrupt_entry_install() for example. * * @note The implementation should use * bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ) to validate @@ -261,7 +260,10 @@ rtems_status_code bsp_interrupt_vector_is_enabled( * @retval ::RTEMS_SUCCESSFUL The requested operation was successful. * * @retval ::RTEMS_UNSATISFIED The request to enable the interrupt vector has - * not been satisfied. + * not been satisfied. The presence of this error condition is + * implementation-defined. The interrupt vector attributes obtained by + * rtems_interrupt_get_attributes() should indicate if it is possible to + * enable a particular interrupt vector. */ rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector ); @@ -270,7 +272,7 @@ rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector ); * * This function shall disable the vector at the corresponding facility (in * most cases the interrupt controller). It will be called then the last - * handler is removed for the vector in bsp_interrupt_handler_remove() for + * entry is removed for the vector in rtems_interrupt_entry_remove() for * example. * * @note The implementation should use @@ -282,7 +284,10 @@ rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector ); * @retval ::RTEMS_SUCCESSFUL The requested operation was successful. * * @retval ::RTEMS_UNSATISFIED The request to disable the interrupt vector has - * not been satisfied. + * not been satisfied. The presence of this error condition is + * implementation-defined. The interrupt vector attributes obtained by + * rtems_interrupt_get_attributes() should indicate if it is possible to + * disable a particular interrupt vector. */ rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number vector ); @@ -320,8 +325,11 @@ rtems_status_code bsp_interrupt_is_pending( * * @retval ::RTEMS_SUCCESSFUL The requested operation was successful. * - * @retval ::RTEMS_UNSATISFIED The request to cause the interrupt vector has - * not been satisfied. + * @retval ::RTEMS_UNSATISFIED The request to raise the interrupt vector has + * not been satisfied. The presence of this error condition is + * implementation-defined. The interrupt vector attributes obtained by + * rtems_interrupt_get_attributes() should indicate if it is possible to + * raise a particular interrupt vector. */ rtems_status_code bsp_interrupt_raise( rtems_vector_number vector ); @@ -338,7 +346,10 @@ rtems_status_code bsp_interrupt_raise( rtems_vector_number vector ); * @retval ::RTEMS_SUCCESSFUL The requested operation was successful. * * @retval ::RTEMS_UNSATISFIED The request to cause the interrupt vector has - * not been satisfied. + * not been satisfied. The presence of this error condition is + * implementation-defined. The interrupt vector attributes obtained by + * rtems_interrupt_get_attributes() should indicate if it is possible to + * raise a particular interrupt vector on a specific processor. */ rtems_status_code bsp_interrupt_raise_on( rtems_vector_number vector, @@ -355,10 +366,62 @@ rtems_status_code bsp_interrupt_raise_on( * @retval ::RTEMS_SUCCESSFUL The requested operation was successful. * * @retval ::RTEMS_UNSATISFIED The request to cause the interrupt vector has - * not been satisfied. + * not been satisfied. The presence of this error condition is + * implementation-defined. The interrupt vector attributes obtained by + * rtems_interrupt_get_attributes() should indicate if it is possible to + * clear a particular interrupt vector. */ rtems_status_code bsp_interrupt_clear( rtems_vector_number vector ); +/** + * @brief Gets the processor affinity set of the interrupt vector. + * + * The function may have no implementation in uniprocessor configurations. + * + * @param vector is the interrupt vector number. + * + * @param[out] affinity is the pointer to a Processor_mask object. When the + * directive call is successful, the processor affinity set of the interrupt + * vector will be stored in this object. A set bit in the processor set + * means that the corresponding processor is in the processor affinity set of + * the interrupt vector, otherwise the bit is cleared. + * + * @retval ::RTEMS_SUCCESSFUL The requested operation was successful. + * + * @retval ::RTEMS_UNSATISFIED The request to get the processor affinity of the + * interrupt vector has not been satisfied. + */ +rtems_status_code bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +); + +/** + * @brief Sets the processor affinity set of the interrupt vector. + * + * The function may have no implementation in uniprocessor configurations. + * + * @param vector is the interrupt vector number. It shall be valid. + * + * @param affinity is the pointer to a Processor_mask object. The processor set + * defines the new processor affinity set of the interrupt vector. A set bit + * in the processor set means that the corresponding processor shall be in + * the processor affinity set of the interrupt vector, otherwise the bit + * shall be cleared. + * + * @retval ::RTEMS_SUCCESSFUL The requested operation was successful. + * + * @retval ::RTEMS_INVALID_NUMBER The referenced processor set was not a valid + * new processor affinity set for the interrupt vector. + * + * @retval ::RTEMS_UNSATISFIED The request to set the processor affinity of the + * interrupt vector has not been satisfied. + */ +rtems_status_code bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +); + #if defined(RTEMS_SMP) /** * @brief Handles a spurious interrupt. @@ -404,7 +467,7 @@ static inline void bsp_interrupt_entry_store_release( #if defined(RTEMS_SMP) _Atomic_Store_uintptr( (Atomic_Uintptr *) ptr, - (Atomic_Uintptr) value, + (uintptr_t) value, ATOMIC_ORDER_RELEASE ); #else @@ -429,10 +492,10 @@ static inline rtems_interrupt_entry *bsp_interrupt_entry_load_first( { rtems_vector_number index; - index = bsp_interrupt_handler_index( vector ); + index = bsp_interrupt_dispatch_index( vector ); return bsp_interrupt_entry_load_acquire( - &bsp_interrupt_handler_table[ index ] + &bsp_interrupt_dispatch_table[ index ] ); } @@ -463,6 +526,35 @@ static inline void bsp_interrupt_dispatch_entries( * This function does not validate the vector number. If the vector number is * out of range, then the behaviour is undefined. * + * The function assumes that no interrupt entries are installed at the vector. + * In this case, no operation is performed. + * + * In uniprocessor configurations, you can call this function within every + * context which can be disabled via rtems_interrupt_local_disable(). + * + * In SMP configurations, you can call this function in every context. + * + * @param vector is the vector number. + */ +static inline void bsp_interrupt_handler_dispatch_unlikely( + rtems_vector_number vector +) +{ + const rtems_interrupt_entry *entry; + + entry = bsp_interrupt_entry_load_first( vector ); + + if ( RTEMS_PREDICT_FALSE( entry != NULL ) ) { + bsp_interrupt_dispatch_entries( entry ); + } +} + +/** + * @brief Sequentially calls all interrupt handlers installed at the vector. + * + * This function does not validate the vector number. If the vector number is + * out of range, then the behaviour is undefined. + * * In uniprocessor configurations, you can call this function within every * context which can be disabled via rtems_interrupt_local_disable(). * @@ -492,9 +584,9 @@ static inline void bsp_interrupt_handler_dispatch_unchecked( /** * @brief Sequentially calls all interrupt handlers installed at the vector. * - * If the vector number is out of range or the handler list is empty - * bsp_interrupt_handler_default() will be called with the vector number as - * argument. + * If the vector number is out of range or the interrupt entry list is empty, + * then bsp_interrupt_handler_default() will be called with the vector number + * as argument. * * In uniprocessor configurations, you can call this function within every * context which can be disabled via rtems_interrupt_local_disable(). @@ -575,7 +667,7 @@ void bsp_interrupt_entry_remove( * * If the bit associated with a vector is set, then the entry is unique, * otherwise it may be shared. If the bit with index - * #BSP_INTERRUPT_HANDLER_TABLE_SIZE is set, then the interrupt support is + * #BSP_INTERRUPT_DISPATCH_TABLE_SIZE is set, then the interrupt support is * initialized, otherwise it is not initialized. */ extern uint8_t bsp_interrupt_handler_unique_table[]; @@ -633,9 +725,20 @@ static inline void bsp_interrupt_set_handler_unique( */ static inline bool bsp_interrupt_is_initialized( void ) { - return bsp_interrupt_is_handler_unique( BSP_INTERRUPT_HANDLER_TABLE_SIZE ); + return bsp_interrupt_is_handler_unique( BSP_INTERRUPT_DISPATCH_TABLE_SIZE ); } +/** + * @brief Gets a reference to the interrupt handler table slot associated with + * the index. + * + * @return Returns a reference to the interrupt handler table slot associated + * with the index. + */ +rtems_interrupt_entry **bsp_interrupt_get_dispatch_table_slot( + rtems_vector_number index +); + #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/bsps/include/bsp/irq-info.h b/bsps/include/bsp/irq-info.h index 25f05a9f69..e687a01dfd 100644 --- a/bsps/include/bsp/irq-info.h +++ b/bsps/include/bsp/irq-info.h @@ -3,14 +3,14 @@ /** * @file * - * @ingroup bsp_interrupt + * @ingroup RTEMSImplClassicIntr * * @brief This header file provides interfaces of the generic interrupt * controller support for the RTEMS Shell. */ /* - * Copyright (C) 2008, 2009 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2008, 2009 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/include/bsp/stackalloc.h b/bsps/include/bsp/stackalloc.h index e2541a9019..17ac5b74b1 100644 --- a/bsps/include/bsp/stackalloc.h +++ b/bsps/include/bsp/stackalloc.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -7,11 +9,28 @@ */ /* - * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved. + * Copyright (C) 2009, 2012 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_SHARED_STACK_ALLOC_H diff --git a/bsps/include/bsp/u-boot.h b/bsps/include/bsp/u-boot.h index 5b170e71ab..eb49d1f8ca 100644 --- a/bsps/include/bsp/u-boot.h +++ b/bsps/include/bsp/u-boot.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -7,11 +9,28 @@ */ /* - * Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved. + * Copyright (C) 2010, 2014 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_SHARED_U_BOOT_H diff --git a/bsps/include/bsp/uart-output-char.h b/bsps/include/bsp/uart-output-char.h index fa183e4984..065f29fa75 100644 --- a/bsps/include/bsp/uart-output-char.h +++ b/bsps/include/bsp/uart-output-char.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -7,11 +9,28 @@ */ /* - * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * Copyright (c) 2010 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_SHARED_UART_OUTPUT_CHAR_H diff --git a/bsps/include/bsp/utility.h b/bsps/include/bsp/utility.h index 38157ee27f..4466a8c9b7 100644 --- a/bsps/include/bsp/utility.h +++ b/bsps/include/bsp/utility.h @@ -1,17 +1,36 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * - * @ingroup bsp_kit + * @ingroup RTEMSBSPsShared * - * @brief Utility macros. + * @brief This header file provides utility macros for BSPs. */ /* - * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. + * Copyright (C) 2008, 2011 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBCPU_SHARED_UTILITY_H diff --git a/bsps/include/dev/clock/VERSION b/bsps/include/dev/clock/VERSION new file mode 100644 index 0000000000..1ccbe7c216 --- /dev/null +++ b/bsps/include/dev/clock/VERSION @@ -0,0 +1,24 @@ +The information in this file describes the source of +bsps/include/dev/clock/xttcps_hw.h. + +Import from: + +https://github.com/Xilinx/embeddedsw.git + +commit 5330a64c8efd14f0eef09befdbb8d3d738c33ec2 +Refs: <xilinx_v2022.2> +Author: Nicole Baze <nicole.baze@xilinx.com> +AuthorDate: Mon Oct 3 13:27:19 2022 -0700 +Commit: Siva Addepalli <sivaprasad.addepalli@xilinx.com> +CommitDate: Fri Oct 7 10:26:16 2022 +0530 + + xilpm: versal: server: Fix bug in AIE2 zeroization + + There is a bug in AIE2 zeriozation function when polling for memory + zeroization complete. Currently the entire memory register is being + checked against zero but instead we need to check the bits specific + to the memory tiles. This patch updates the zeroization check by + adding a mask so that only the desired bits are checked for zero. + + Signed-off-by: Nicole Baze <nicole.baze@xilinx.com> + Acked-by: Jesus De Haro <jesus.de-haro@xilinx.com> diff --git a/bsps/include/dev/clock/xttcps_hw.h b/bsps/include/dev/clock/xttcps_hw.h new file mode 100644 index 0000000000..4d40ab445b --- /dev/null +++ b/bsps/include/dev/clock/xttcps_hw.h @@ -0,0 +1,210 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xttcps_hw.h +* @addtogroup ttcps_v3_15 +* @{ +* +* This file defines the hardware interface to one of the three timer counters +* in the Ps block. +* +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- ------------------------------------------------- +* 1.00a drg/jz 01/21/10 First release +* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.5 srm 10/06/17 Updated XTTCPS_COUNT_VALUE_MASK, +* XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to +* mask 16 bit values for zynq and 32 bit values for +* zynq ultrascale+mpsoc " +* </pre> +* +******************************************************************************/ + +#ifndef XTTCPS_HW_H /* prevent circular inclusions */ +#define XTTCPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#ifdef __rtems__ +#include <xil_system.h> +#endif + +/************************** Constant Definitions *****************************/ +/* + * Flag for a9 processor + */ + #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) + #define ARMA9 + #endif + +/** @name Register Map + * + * Register offsets from the base address of the device. + * + * @{ + */ +#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */ +#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/ +#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */ +#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */ +#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */ +#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */ +#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */ +#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */ +#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */ +/* @} */ + +/** @name Clock Control Register + * Clock Control Register definitions + * @{ + */ +#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */ +#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */ +#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */ +#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */ +#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */ +#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */ +/* @} */ + +/** @name Counter Control Register + * Counter Control Register definitions + * @{ + */ +#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */ +#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */ +#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */ +#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */ +#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */ +#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */ +#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */ +#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */ +/* @} */ + +/** @name Current Counter Value Register + * Current Counter Value Register definitions + * @{ + */ +#if defined(ARMA9) +#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */ +#else +#define XTTCPS_COUNT_VALUE_MASK 0xFFFFFFFFU /**< 32-bit counter value */ +#endif +/* @} */ + +/** @name Interval Value Register + * Interval Value Register is the maximum value the counter will count up or + * down to. + * @{ + */ +#if defined(ARMA9) +#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/ +#else +#define XTTCPS_INTERVAL_VAL_MASK 0xFFFFFFFFU /**< 32-bit Interval value*/ +#endif +/* @} */ + +/** @name Match Registers + * Definitions for Match registers, each timer counter has three match + * registers. + * @{ + */ +#if defined(ARMA9) +#define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */ +#else +#define XTTCPS_MATCH_MASK 0xFFFFFFFFU /**< 32-bit Match value */ +#endif +#define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */ +/* @} */ + +/** @name Interrupt Registers + * Following register bit mask is for all interrupt registers. + * + * @{ + */ +#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */ +#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */ +#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */ +#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */ +#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */ +#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */ +/* @} */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given Timer Counter register. +* +* @param BaseAddress is the base address of the timer counter device. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XTtcPs_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (u32)(RegOffset))) + +/****************************************************************************/ +/** +* +* Write the given Timer Counter register. +* +* @param BaseAddress is the base address of the timer counter device. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset, +* u32 Data) +* +*****************************************************************************/ +#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))) + +/****************************************************************************/ +/** +* +* Calculate a match register offset using the Match Register index. +* +* @param MatchIndex is the 0-2 value of the match register +* +* @return MATCH_N_OFFSET. +* +* @note C-style signature: +* u32 XTtcPs_Match_N_Offset(u8 MatchIndex) +* +*****************************************************************************/ +#define XTtcPs_Match_N_Offset(MatchIndex) \ + ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex))) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif +#endif /* end of protection macro */ +/** @} */ diff --git a/bsps/include/dev/i2c/cadence-i2c-regs.h b/bsps/include/dev/i2c/cadence-i2c-regs.h index 7d7c3b284a..0318b9850a 100644 --- a/bsps/include/dev/i2c/cadence-i2c-regs.h +++ b/bsps/include/dev/i2c/cadence-i2c-regs.h @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (C) 2014 embedded brains GmbH + * Copyright (C) 2014 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/include/dev/i2c/cadence-i2c.h b/bsps/include/dev/i2c/cadence-i2c.h index aff97237a4..1aba2b7ad0 100644 --- a/bsps/include/dev/i2c/cadence-i2c.h +++ b/bsps/include/dev/i2c/cadence-i2c.h @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (C) 2014 embedded brains GmbH + * Copyright (C) 2014 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/include/dev/irq/arm-gic-irq.h b/bsps/include/dev/irq/arm-gic-irq.h index e0a96c781a..c3615a12a0 100644 --- a/bsps/include/dev/irq/arm-gic-irq.h +++ b/bsps/include/dev/irq/arm-gic-irq.h @@ -1,17 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file + * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief ARM GIC IRQ + * @brief This header file provides interfaces of the ARM Generic Interrupt + * Controller (GIC) support. */ /* - * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H @@ -19,12 +39,17 @@ #include <bsp.h> #include <dev/irq/arm-gic.h> -#include <rtems/score/processormask.h> #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ +/** + * @addtogroup DevIRQGIC + * + * @{ + */ + #define ARM_GIC_IRQ_SGI_0 0 #define ARM_GIC_IRQ_SGI_1 1 #define ARM_GIC_IRQ_SGI_2 2 @@ -66,16 +91,6 @@ rtems_status_code arm_gic_irq_get_group( gic_group *group ); -rtems_status_code bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -); - -rtems_status_code bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -); - void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets); static inline rtems_status_code arm_gic_irq_generate_software_irq( @@ -94,9 +109,13 @@ static inline rtems_status_code arm_gic_irq_generate_software_irq( return sc; } +#ifdef RTEMS_SMP uint32_t arm_gic_irq_processor_count(void); void arm_gic_irq_initialize_secondary_cpu(void); +#endif + +/** @} */ #ifdef __cplusplus } diff --git a/bsps/include/dev/irq/arm-gic-regs.h b/bsps/include/dev/irq/arm-gic-regs.h index 5827411c3b..c03a7a7a07 100644 --- a/bsps/include/dev/irq/arm-gic-regs.h +++ b/bsps/include/dev/irq/arm-gic-regs.h @@ -1,17 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file + * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief ARM GIC Register definitions + * @brief This header file provides interfaces of the ARM Generic Interrupt + * Controller (GIC) memory-mapped registers. */ /* - * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H @@ -19,6 +39,12 @@ #include <bsp/utility.h> +/** + * @addtogroup DevIRQGIC + * + * @{ + */ + typedef struct { uint32_t iccicr; #define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4) @@ -206,4 +232,6 @@ typedef struct { uint32_t icspigrpmodr[64]; } gic_sgi_ppi; +/** @} */ + #endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */ diff --git a/bsps/include/dev/irq/arm-gic-tm27.h b/bsps/include/dev/irq/arm-gic-tm27.h index d7aeefb529..70e76c7603 100644 --- a/bsps/include/dev/irq/arm-gic-tm27.h +++ b/bsps/include/dev/irq/arm-gic-tm27.h @@ -1,17 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file + * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief ARM GIC TM27 Support + * @brief This header file provides the TM27 support for the ARM Generic + * Interrupt Controller (GIC). */ /* - * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RTEMS_TMTEST27 @@ -21,11 +41,11 @@ #ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H #define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H -#include <assert.h> - #include <bsp.h> #include <bsp/irq.h> +#include <rtems/score/assert.h> + #define MUST_WAIT_FOR_INTERRUPT 1 #ifndef ARM_GIC_TM27_IRQ_LOW @@ -36,50 +56,66 @@ #define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13 #endif +#define TM27_INTERRUPT_VECTOR_DEFAULT ARM_GIC_TM27_IRQ_LOW + #define ARM_GIC_TM27_PRIO_LOW 0x80 #define ARM_GIC_TM27_PRIO_HIGH 0x00 -static inline void Install_tm27_vector(void (*handler)(rtems_vector_number)) +static inline void Install_tm27_vector( rtems_interrupt_handler handler ) { - rtems_status_code sc = rtems_interrupt_handler_install( + static rtems_interrupt_entry entry_low; + static rtems_interrupt_entry entry_high; + rtems_status_code sc; + + rtems_interrupt_entry_initialize( + &entry_low, + handler, + NULL, + "tm27 low" + ); + sc = rtems_interrupt_entry_install( ARM_GIC_TM27_IRQ_LOW, - "tm27 low", RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) handler, - NULL + &entry_low ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); sc = arm_gic_irq_set_priority( ARM_GIC_TM27_IRQ_LOW, ARM_GIC_TM27_PRIO_LOW ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); - sc = rtems_interrupt_handler_install( + rtems_interrupt_entry_initialize( + &entry_high, + handler, + NULL, + "tm27 high" + ); + sc = rtems_interrupt_entry_install( ARM_GIC_TM27_IRQ_HIGH, - "tm27 high", RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) handler, - NULL + &entry_high ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); sc = arm_gic_irq_set_priority( ARM_GIC_TM27_IRQ_HIGH, ARM_GIC_TM27_PRIO_HIGH ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); } static inline void Cause_tm27_intr(void) { - rtems_status_code sc = arm_gic_irq_generate_software_irq( + rtems_status_code sc; + + sc = arm_gic_irq_generate_software_irq( ARM_GIC_TM27_IRQ_LOW, 1U << _SMP_Get_current_processor() ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); } static inline void Clear_tm27_intr(void) @@ -89,11 +125,13 @@ static inline void Clear_tm27_intr(void) static inline void Lower_tm27_intr(void) { - rtems_status_code sc = arm_gic_irq_generate_software_irq( + rtems_status_code sc; + + sc = arm_gic_irq_generate_software_irq( ARM_GIC_TM27_IRQ_HIGH, 1U << _SMP_Get_current_processor() ); - assert(sc == RTEMS_SUCCESSFUL); + _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL ); } #endif /* LIBBSP_ARM_SHARED_ARM_GIC_TM27_H */ diff --git a/bsps/include/dev/irq/arm-gic.h b/bsps/include/dev/irq/arm-gic.h index eba519c749..4e418de68f 100644 --- a/bsps/include/dev/irq/arm-gic.h +++ b/bsps/include/dev/irq/arm-gic.h @@ -1,17 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file + * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief ARM GIC Support + * @brief This header file provides interfaces of the ARM Generic Interrupt + * Controller (GIC) support. */ /* - * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_SHARED_ARM_GIC_H @@ -26,11 +46,14 @@ extern "C" { #endif /* __cplusplus */ /** - * @defgroup arm_gic ARM GIC + * @defgroup DevIRQGIC ARM Generic Interrupt Controller (GIC) Support * - * @ingroup RTEMSBSPsARMShared + * @ingroup RTEMSImplClassicIntr * - * @brief ARM_GIC Support Package + * @brief This group contains the Interrupt Manager implementation parts + * specific to the ARM Generic Interrupt Controller. + * + * @{ */ #define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5) @@ -229,6 +252,8 @@ static inline void gic_id_set_handling_model( dist->icdicfr[i] = icdicfr; } +/* @} */ + #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h index 0d3ef9a1c1..8829c32384 100644 --- a/bsps/include/dev/irq/arm-gicv3.h +++ b/bsps/include/dev/irq/arm-gicv3.h @@ -3,13 +3,14 @@ /** * @file * - * @ingroup arm_gic + * @ingroup DevIRQGIC * - * @brief This header file contains interfaces to access an Arm GICv3. + * @brief This header file provides interfaces of the ARM Generic Interrupt + * Controller (GIC) support specific to the GICv3. */ /* - * Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2022 embedded brains GmbH & Co. KG * Copyright (C) 2019 On-Line Applications Research Corporation (OAR) * * Redistribution and use in source and binary forms, with or without @@ -44,6 +45,12 @@ extern "C" { #endif +/** + * @addtogroup DevIRQGIC + * + * @{ + */ + #define PRIORITY_DEFAULT 127 #define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23) @@ -116,13 +123,16 @@ extern "C" { #else /* ARM_MULTILIB_ARCH_V4 */ /* AArch64 GICv3 registers are not named in GCC */ -#define ICC_IGRPEN0 "S3_0_C12_C12_6, %0" -#define ICC_IGRPEN1 "S3_0_C12_C12_7, %0" +#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6, %0" +#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7, %0" #define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0" +#define ICC_IGRPEN0 ICC_IGRPEN0_EL1 +#define ICC_IGRPEN1 ICC_IGRPEN1_EL1 #define ICC_PMR "S3_0_C4_C6_0, %0" #define ICC_EOIR1 "S3_0_C12_C12_1, %0" #define ICC_SRE "S3_0_C12_C12_5, %0" #define ICC_BPR0 "S3_0_C12_C8_3, %0" +#define ICC_BPR1 "S3_0_C12_C12_3, %0" #define ICC_CTLR "S3_0_C12_C12_4, %0" #define ICC_IAR1 "%0, S3_0_C12_C12_0" #define MPIDR "%0, mpidr_el1" @@ -302,10 +312,25 @@ static void gicv3_init_dist(volatile gic_dist *dist) static void gicv3_init_cpu_interface(uint32_t cpu_index) { - uint32_t sre_value = 0x7; - WRITE_SR(ICC_SRE, sre_value); - WRITE_SR(ICC_PMR, GIC_CPUIF_ICCPMR_PRIORITY(0xff)); - WRITE_SR(ICC_BPR0, GIC_CPUIF_ICCBPR_BINARY_POINT(0x0)); + /* Initialize Interrupt Controller System Register Enable Register */ +#ifdef BSP_ARM_GIC_ICC_SRE + WRITE_SR(ICC_SRE, BSP_ARM_GIC_ICC_SRE); +#endif + + /* Initialize Interrupt Controller Interrupt Priority Mask Register */ +#ifdef BSP_ARM_GIC_ICC_PMR + WRITE_SR(ICC_PMR, BSP_ARM_GIC_ICC_PMR); +#endif + + /* Initialize Interrupt Controller Binary Point Register 0 */ +#ifdef BSP_ARM_GIC_ICC_BPR0 + WRITE_SR(ICC_BPR0, BSP_ARM_GIC_ICC_BPR0); +#endif + + /* Initialize Interrupt Controller Binary Point Register 1 */ +#ifdef BSP_ARM_GIC_ICC_BPR1 + WRITE_SR(ICC_BPR1, BSP_ARM_GIC_ICC_BPR1); +#endif volatile gic_redist *redist = gicv3_get_redist(cpu_index); uint32_t waker = redist->icrwaker; @@ -321,10 +346,20 @@ static void gicv3_init_cpu_interface(uint32_t cpu_index) sgi_ppi->icspiprior[id] = PRIORITY_DEFAULT; } - /* Enable interrupt groups 0 and 1 */ - WRITE_SR(ICC_IGRPEN0, 0x1); - WRITE_SR(ICC_IGRPEN1, 0x1); - WRITE_SR(ICC_CTLR, 0x0); + /* Initialize Interrupt Controller Interrupt Group Enable 0 Register */ +#ifdef BSP_ARM_GIC_ICC_IGRPEN0 + WRITE_SR(ICC_IGRPEN0, BSP_ARM_GIC_ICC_IGRPEN0); +#endif + + /* Initialize Interrupt Controller Interrupt Group Enable 1 Register */ +#ifdef BSP_ARM_GIC_ICC_IGRPEN1 + WRITE_SR(ICC_IGRPEN1, BSP_ARM_GIC_ICC_IGRPEN1); +#endif + + /* Initialize Interrupt Controller Control Register */ +#ifdef BSP_ARM_GIC_ICC_CTRL + WRITE_SR(ICC_CTLR, BSP_ARM_GIC_ICC_CTRL); +#endif } static inline void gicv3_get_attributes( @@ -359,6 +394,8 @@ static inline void gicv3_get_attributes( } } +/** @} */ + #ifdef __cplusplus } #endif diff --git a/bsps/include/dev/nand/xnandpsu.h b/bsps/include/dev/nand/xnandpsu.h new file mode 100644 index 0000000000..ac9496a745 --- /dev/null +++ b/bsps/include/dev/nand/xnandpsu.h @@ -0,0 +1,642 @@ +/****************************************************************************** +* Copyright (C) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xnandpsu.h +* @addtogroup Overview +* @{ +* @details +* +* This file implements a driver to support Arasan NAND controller +* present in Zynq Ultrascale Mp. +* +* <b>Driver Initialization</b> +* +* The function call XNandPsu_CfgInitialize() should be called by the application +* before any other function in the driver. The initialization function takes +* device specific data (like device id, instance id, and base address) and +* initializes the XNandPsu instance with the device specific data. +* +* <b>Device Geometry</b> +* +* NAND flash device is memory device and it is segmented into areas called +* Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device +* can have multiple LUN. LUN is sequential raw of multiple blocks of the same +* size. A block is the smallest erasable unit of data within the Flash array of +* a LUN. The size of each block is based on a power of 2. There is no +* restriction on the number of blocks within the LUN. A block contains a number +* of pages. A page is the smallest addressable unit for read and program +* operations. The arrangement of LUN, blocks, and pages is referred to by this +* module as the part's geometry. +* +* The cells within the part can be programmed from a logic 1 to a logic 0 +* and not the other way around. To change a cell back to a logic 1, the +* entire block containing that cell must be erased. When a block is erased +* all bytes contain the value 0xFF. The number of times a block can be +* erased is finite. Eventually the block will wear out and will no longer +* be capable of erasure. As of this writing, the typical flash block can +* be erased 100,000 or more times. +* +* The jobs done by this driver typically are: +* - 8-bit operational mode +* - Read, Write, and Erase operation +* +* <b>Write Operation</b> +* +* The write call can be used to write a minimum of one byte and a maximum +* entire flash. If the address offset specified to write is out of flash or if +* the number of bytes specified from the offset exceed flash boundaries +* an error is reported back to the user. The write is blocking in nature in that +* the control is returned back to user only after the write operation is +* completed successfully or an error is reported. +* +* <b>Read Operation</b> +* +* The read call can be used to read a minimum of one byte and maximum of +* entire flash. If the address offset specified to read is out of flash or if +* the number of bytes specified from the offset exceed flash boundaries +* an error is reported back to the user. The read is blocking in nature in that +* the control is returned back to user only after the read operation is +* completed successfully or an error is reported. +* +* <b>Erase Operation</b> +* +* The erase operations are provided to erase a Block in the Flash memory. The +* erase call is blocking in nature in that the control is returned back to user +* only after the erase operation is completed successfully or an error is +* reported. +* +* @note Driver has been renamed to nandpsu after change in +* naming convention. +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads, +* mutual exclusion, virtual memory, cache control, or HW write protection +* management must be satisfied by the layer above this driver. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- ---------- ----------------------------------------------- +* 1.0 nm 05/06/2014 First release +* 2.0 sb 01/12/2015 Removed Null checks for Buffer passed +* as parameter to Read API's +* - XNandPsu_Read() +* - XNandPsu_ReadPage +* Modified +* - XNandPsu_SetFeature() +* - XNandPsu_GetFeature() +* and made them public. +* Removed Failure Return for BCF Error check in +* XNandPsu_ReadPage() and added BCH_Error counter +* in the instance pointer structure. +* Added XNandPsu_Prepare_Cmd API +* Replaced +* - XNandPsu_IntrStsEnable +* - XNandPsu_IntrStsClear +* - XNandPsu_IntrClear +* - XNandPsu_SetProgramReg +* with XNandPsu_WriteReg call +* Modified xnandpsu.c file API's with above changes. +* Corrected the program command for Set Feature API. +* Modified +* - XNandPsu_OnfiReadStatus +* - XNandPsu_GetFeature +* - XNandPsu_SetFeature +* to add support for DDR mode. +* Changed Convention for SLC/MLC +* SLC --> HAMMING +* MLC --> BCH +* SlcMlc --> IsBCH +* Added support for writing BBT signature and version +* in page section by enabling XNANDPSU_BBT_NO_OOB. +* Removed extra DMA mode initialization from +* the XNandPsu_CfgInitialize API. +* Modified +* - XNandPsu_SetEccAddrSize +* ECC address now is calculated based upon the +* size of spare area +* Modified Block Erase API, removed clearing of +* packet register before erase. +* Clearing Data Interface Register before +* XNandPsu_OnfiReset call. +* Modified XNandPsu_ChangeTimingMode API supporting +* SDR and NVDDR interface for timing modes 0 to 5. +* Modified Bbt Signature and Version Offset value for +* Oob and No-Oob region. +* 1.0 kpc 17/06/2015 Increased the timeout for complete event to avoid +* timeout errors for erase operation on slower devices. +* 1.1 mi 09/16/16 Removed compilation warnings with extra compiler flags. +* 1.1 nsk 11/07/16 Change memcpy to Xil_MemCpy, CR#960462 +* 1.2 nsk 01/19/17 Fix for the failure of reading nand first redundant +* parameter page. CR#966603 +* ms 02/12/17 Fix for the compilation warning in _g.c file. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/10/17 Modified Comment lines in nandpsu_example.c to +* follow doxygen rules. +* 1.2 nsk 08/08/17 Added support to import example in SDK +* 1.4 nsk 04/10/18 Added ICCARM compiler support. CR#997552. +* 1.5 mus 11/08/18 Updated BBT signature array size in +* XNandPsu_BbtDesc structure to fix the compilation +* warnings. +# 1.6 sd 06/02/20 Added Clock support +* 1.6 sd 20/03/20 Added compilation flag +* 1.8 sg 03/18/21 Added validation check for parameter page. +* 1.9 akm 07/15/21 Initialize NandInstPtr with Data Interface & Timing mode info. +* 1.10 akm 10/20/21 Fix gcc warnings. +* 1.10 akm 12/21/21 Validate input parameters before use. +* 1.10 akm 01/05/22 Remove assert checks form static and internal APIs. +* 1.11 akm 03/31/22 Fix unused parameter warning. +* 1.11 akm 03/31/22 Fix misleading-indentation warning. +* +* </pre> +* +******************************************************************************/ + +#ifndef XNANDPSU_H /* prevent circular inclusions */ +#define XNANDPSU_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include <string.h> +#include "xstatus.h" +#include "xil_assert.h" +#include "xnandpsu_hw.h" +#include "xnandpsu_onfi.h" +#include "xil_cache.h" +#if defined (XCLOCKING) +#include "xil_clocking.h" +#endif +/************************** Constant Definitions *****************************/ + +#define XNANDPSU_DEBUG + +#ifdef __rtems__ +#define XNANDPSU_MAX_TARGETS 2U /**< ce_n0, ce_n1 */ +#else +#define XNANDPSU_MAX_TARGETS 1U /**< ce_n0, ce_n1 */ +#endif +#define XNANDPSU_MAX_PKT_SIZE 0x7FFU /**< Max packet size */ +#define XNANDPSU_MAX_PKT_COUNT 0xFFFU /**< Max packet count */ + +#define XNANDPSU_PAGE_SIZE_512 512U /**< 512 bytes page */ +#define XNANDPSU_PAGE_SIZE_2K 2048U /**< 2K bytes page */ +#define XNANDPSU_PAGE_SIZE_4K 4096U /**< 4K bytes page */ +#define XNANDPSU_PAGE_SIZE_8K 8192U /**< 8K bytes page */ +#define XNANDPSU_PAGE_SIZE_16K 16384U /**< 16K bytes page */ +#define XNANDPSU_PAGE_SIZE_1K_16BIT 1024U /**< 16-bit 2K bytes page */ +#define XNANDPSU_MAX_PAGE_SIZE 16384U /**< Max page size supported */ + +#define XNANDPSU_HAMMING 0x1U /**< Hamming Flash */ +#define XNANDPSU_BCH 0x2U /**< BCH Flash */ + +#define XNANDPSU_MAX_BLOCKS 16384U /**< Max number of Blocks */ +#define XNANDPSU_MAX_SPARE_SIZE 0x800U /**< Max spare bytes of a NAND + flash page of 16K */ +#define XNANDPSU_MAX_LUNS 8U /**< Max number of LUNs */ +#define XNANDPSU_MAX_PAGES_PER_BLOCK 512U /**< Max number pages per block */ + +#define XNANDPSU_INTR_POLL_TIMEOUT 0xF000000U + +#define XNANDPSU_SDR_CLK ((u16)100U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_0 ((u16)20U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_1 ((u16)33U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_2 ((u16)50U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_3 ((u16)66U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_4 ((u16)83U * (u16)1000U * (u16)1000U) +#define XNANDPSU_NVDDR_CLK_5 ((u16)100U * (u16)1000U * (u16)1000U) + +#define XNANDPSU_MAX_TIMING_MODE 5 + +#ifdef __rtems__ +#define XNANDPSU_PAGE_CACHE_UNAVAILABLE -2 +#define XNANDPSU_PAGE_CACHE_NONE -1 +#endif + +/** + * The XNandPsu_Config structure contains configuration information for NAND + * controller. + */ +typedef struct { + u16 DeviceId; /**< Instance ID of NAND flash controller */ + u32 BaseAddress; /**< Base address of NAND flash controller */ + u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not */ +#if defined (XCLOCKING) + u32 RefClk; /**< Input clocks */ +#endif +} XNandPsu_Config; + +/** + * The XNandPsu_DataInterface enum contains flash operating mode. + */ +typedef enum { + XNANDPSU_SDR = 0U, /**< Single Data Rate */ + XNANDPSU_NVDDR /**< Double Data Rate */ +} XNandPsu_DataInterface; + +/** + * XNandPsu_TimingMode enum contains timing modes. + */ +typedef enum { + XNANDPSU_SDR0 = 0U, + XNANDPSU_SDR1, + XNANDPSU_SDR2, + XNANDPSU_SDR3, + XNANDPSU_SDR4, + XNANDPSU_SDR5, + XNANDPSU_NVDDR0, + XNANDPSU_NVDDR1, + XNANDPSU_NVDDR2, + XNANDPSU_NVDDR3, + XNANDPSU_NVDDR4, + XNANDPSU_NVDDR5 +} XNandPsu_TimingMode; + +/** + * The XNandPsu_SWMode enum contains the driver operating mode. + */ +typedef enum { + XNANDPSU_POLLING = 0, /**< Polling */ + XNANDPSU_INTERRUPT /**< Interrupt */ +} XNandPsu_SWMode; + +/** + * The XNandPsu_DmaMode enum contains the controller MDMA mode. + */ +typedef enum { + XNANDPSU_PIO = 0, /**< PIO Mode */ + XNANDPSU_SDMA, /**< SDMA Mode */ + XNANDPSU_MDMA /**< MDMA Mode */ +} XNandPsu_DmaMode; + +/** + * The XNandPsu_EccMode enum contains ECC functionality. + */ +typedef enum { + XNANDPSU_NONE = 0, + XNANDPSU_HWECC, + XNANDPSU_EZNAND, + XNANDPSU_ONDIE +} XNandPsu_EccMode; + +/** + * Bad block table descriptor + */ +typedef struct { + u32 PageOffset[XNANDPSU_MAX_TARGETS]; + /**< Page offset where BBT resides */ + u32 SigOffset; /**< Signature offset in Spare area */ + u32 VerOffset; /**< Offset of BBT version */ + u32 SigLength; /**< Length of the signature */ + u32 MaxBlocks; /**< Max blocks to search for BBT */ + char Signature[5]; /**< BBT signature */ + u8 Version[XNANDPSU_MAX_TARGETS]; + /**< BBT version */ + u32 Valid; /**< BBT descriptor is valid or not */ +} XNandPsu_BbtDesc; + +/** + * Bad block pattern + */ +typedef struct { + u32 Options; /**< Options to search the bad block pattern */ + u32 Offset; /**< Offset to search for specified pattern */ + u32 Length; /**< Number of bytes to check the pattern */ + u8 Pattern[2]; /**< Pattern format to search for */ +} XNandPsu_BadBlockPattern; + +/** + * The XNandPsu_Geometry structure contains the ONFI geometry information. + */ +typedef struct { + /* Parameter page information */ + u32 BytesPerPage; /**< Number of bytes per page */ + u16 SpareBytesPerPage; /**< Number of spare bytes per page */ + u32 PagesPerBlock; /**< Number of pages per block */ + u32 BlocksPerLun; /**< Number of blocks per LUN */ + u8 NumLuns; /**< Number of LUN's */ + u8 RowAddrCycles; /**< Row address cycles */ + u8 ColAddrCycles; /**< Column address cycles */ + u8 NumBitsPerCell; /**< Number of bits per cell (Hamming/BCH) */ + u8 NumBitsECC; /**< Number of bits ECC correctability */ + u32 EccCodeWordSize; /**< ECC codeword size */ + /* Driver specific information */ + u32 BlockSize; /**< Block size */ + u32 NumTargetPages; /**< Total number of pages in a Target */ + u32 NumTargetBlocks; /**< Total number of blocks in a Target */ + u64 TargetSize; /**< Target size in bytes */ + u8 NumTargets; /**< Number of targets present */ + u32 NumPages; /**< Total number of pages */ + u32 NumBlocks; /**< Total number of blocks */ + u64 DeviceSize; /**< Total flash size in bytes */ +} XNandPsu_Geometry; + +/** + * The XNandPsu_Features structure contains the ONFI features information. + */ +typedef struct { + u32 NvDdr; + u32 EzNand; + u32 OnDie; + u32 ExtPrmPage; +} XNandPsu_Features; + +/** + * The XNandPsu_EccMatrix structure contains ECC features information. + */ +typedef struct { + u16 PageSize; + u16 CodeWordSize; + u8 NumEccBits; + u8 IsBCH; + u16 EccAddr; + u16 EccSize; +} XNandPsu_EccMatrix; + +/** + * The XNandPsu_EccCfg structure contains ECC configuration. + */ +typedef struct { + u16 EccAddr; + u16 EccSize; + u16 CodeWordSize; + u8 NumEccBits; + u8 IsBCH; +} XNandPsu_EccCfg; + +/** + * The XNandPsu structure contains the driver instance data. The user is + * required to allocate a variable of this type for the NAND controller. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +#ifdef __ICCARM__ +#pragma pack(push, 1) +#endif +typedef struct { + u32 IsReady; /**< Device is initialized and ready */ + XNandPsu_Config Config; + u32 Ecc_Stat_PerPage_flips; /**< Ecc Correctable Error Counter for Current Page */ + u32 Ecc_Stats_total_flips; /**< Total Ecc Errors Corrected */ + XNandPsu_DataInterface DataInterface; + XNandPsu_TimingMode TimingMode; + XNandPsu_SWMode Mode; /**< Driver operating mode */ + XNandPsu_DmaMode DmaMode; /**< MDMA mode enabled/disabled */ + XNandPsu_EccMode EccMode; /**< ECC Mode */ + XNandPsu_EccCfg EccCfg; /**< ECC configuration */ + XNandPsu_Geometry Geometry; /**< Flash geometry */ + XNandPsu_Features Features; /**< ONFI features */ +#ifdef __rtems__ + int32_t PartialDataPageIndex; /**< Cached page index */ +#endif +#ifdef __ICCARM__ + u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE]; /**< Partial read/write buffer */ +#pragma pack(pop) +#else + u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE] __attribute__ ((aligned(64))); +#endif + /* Bad block table definitions */ + XNandPsu_BbtDesc BbtDesc; /**< Bad block table descriptor */ + XNandPsu_BbtDesc BbtMirrorDesc; /**< Mirror BBT descriptor */ + XNandPsu_BadBlockPattern BbPattern; /**< Bad block pattern to + search */ + u8 Bbt[XNANDPSU_MAX_BLOCKS >> 2]; /**< Bad block table array */ +} XNandPsu; + +/******************* Macro Definitions (Inline Functions) *******************/ + +/*****************************************************************************/ +/** + * This macro sets the bitmask in the register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param RegOffset is the register offset. + * @param BitMask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_SetBits(XNandPsu *InstancePtr, u32 RegOffset, + * u32 BitMask) + * + *****************************************************************************/ +#define XNandPsu_SetBits(InstancePtr, RegOffset, BitMask) \ + XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset), \ + ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset)) | (BitMask)))) + +/*****************************************************************************/ +/** + * This macro clears the bitmask in the register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param RegOffset is the register offset. + * @param BitMask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_ClrBits(XNandPsu *InstancePtr, u32 RegOffset, + * u32 BitMask) + * + *****************************************************************************/ +#define XNandPsu_ClrBits(InstancePtr, RegOffset, BitMask) \ + XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset), \ + ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset)) & ~(BitMask)))) + +/*****************************************************************************/ +/** + * This macro clears and updates the bitmask in the register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param RegOffset is the register offset. + * @param Mask is the bitmask. + * @param Value is the register value to write. + * + * @note C-style signature: + * void XNandPsu_ReadModifyWrite(XNandPsu *InstancePtr, + * u32 RegOffset, u32 Mask, u32 Val) + * + *****************************************************************************/ +#define XNandPsu_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value) \ + XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \ + (RegOffset), \ + ((u32)((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,\ + (u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value)))) + +/*****************************************************************************/ +/** + * This macro enables bitmask in Interrupt Signal Enable register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param Mask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_IntrSigEnable(XNandPsu *InstancePtr, u32 Mask) + * + *****************************************************************************/ +#define XNandPsu_IntrSigEnable(InstancePtr, Mask) \ + XNandPsu_SetBits((InstancePtr), \ + XNANDPSU_INTR_SIG_EN_OFFSET, \ + (Mask)) + +/*****************************************************************************/ +/** + * This macro clears bitmask in Interrupt Signal Enable register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param Mask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_IntrSigClear(XNandPsu *InstancePtr, u32 Mask) + * + *****************************************************************************/ +#define XNandPsu_IntrSigClear(InstancePtr, Mask) \ + XNandPsu_ClrBits((InstancePtr), \ + XNANDPSU_INTR_SIG_EN_OFFSET, \ + (Mask)) + +/*****************************************************************************/ +/** + * This macro enables bitmask in Interrupt Status Enable register. + * + * @param InstancePtr is a pointer to the XNandPsu instance of the + * controller. + * @param Mask is the bitmask. + * + * @note C-style signature: + * void XNandPsu_IntrStsEnable(XNandPsu *InstancePtr, u32 Mask) + * + *****************************************************************************/ +#define XNandPsu_IntrStsEnable(InstancePtr, Mask) \ + XNandPsu_SetBits((InstancePtr), \ + XNANDPSU_INTR_STS_EN_OFFSET, \ + (Mask)) + +/*****************************************************************************/ +/** + * This macro checks for the ONFI ID. + * + * @param Buff is the buffer holding ONFI ID + * + * @note none. + * + *****************************************************************************/ +#define IS_ONFI(Buff) \ + ((Buff)[0] == (u8)'O') && ((Buff)[1] == (u8)'N') && \ + ((Buff)[2] == (u8)'F') && ((Buff)[3] == (u8)'I') + +/************************** Function Prototypes *****************************/ + +s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr, + u32 EffectiveAddr); + +s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length); + +s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length, + u8 *SrcBuf); + +s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, + u8 *DestBuf); + +s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block); + +s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf); + +s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf); + +s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr, + XNandPsu_DataInterface NewIntf, + XNandPsu_TimingMode NewMode); + +s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature, + u8 *Buf); + +s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature, + u8 *Buf); + +s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr); + +s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block); + +#ifdef __rtems__ +#include <stdbool.h> +/*****************************************************************************/ +/** +* This function changes the marking of a block in the RAM based Bad Block Table(BBT). It +* also updates the Bad Block Table(BBT) in the flash if necessary. +* +* @param InstancePtr is the pointer to the XNandPsu instance. +* @param Block is the block number. +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* +******************************************************************************/ +s32 XNandPsu_MarkBlock(XNandPsu *InstancePtr, u32 Block, u8 BlockMark); + +/*****************************************************************************/ +/** +* This function changes the marking of a block in the RAM based Bad Block Table(BBT). It +* does not update the Bad Block Table(BBT) in the flash. +* +* @param InstancePtr is the pointer to the XNandPsu instance. +* @param Block is the block number. +* +* @return +* - true if the BBT needs updating. +* - false if the BBT does not need updating. +* +******************************************************************************/ +bool XNandPsu_StageBlockMark(XNandPsu *InstancePtr, u32 Block, u8 BlockMark); + +/*****************************************************************************/ +/** +* This function updates the primary and mirror Bad Block Table(BBT) in the +* flash. +* +* @param InstancePtr is the pointer to the XNandPsu instance. +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* +******************************************************************************/ +s32 XNandPsu_UpdateBbt(XNandPsu *InstancePtr, u32 Target); +#endif + +void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr); + +void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr); + +void XNandPsu_EnableEccMode(XNandPsu *InstancePtr); + +void XNandPsu_DisableEccMode(XNandPsu *InstancePtr); + +void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState, + u8 DmaMode, u8 AddrCycles); + +/* XNandPsu_LookupConfig in xnandpsu_sinit.c */ +XNandPsu_Config *XNandPsu_LookupConfig(u16 DevID); + + +#ifdef __cplusplus +} +#endif + +#endif /* XNANDPSU_H end of protection macro */ +/** @} */ diff --git a/bsps/include/dev/nand/xnandpsu_bbm.h b/bsps/include/dev/nand/xnandpsu_bbm.h new file mode 100644 index 0000000000..b6b39dc990 --- /dev/null +++ b/bsps/include/dev/nand/xnandpsu_bbm.h @@ -0,0 +1,180 @@ +/****************************************************************************** +* Copyright (C) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xnandpsu_bbm.h +* @addtogroup Overview +* @{ +* +* This file implements the Bad Block Management(BBM) functionality. This is +* similar to the Bad Block Management which is a part of the MTD subsystem in +* Linux. The factory marked bad blocks are scanned initially and a Bad Block +* Table(BBT) is created in the memory. This table is also written to the flash +* so that upon reboot, the BBT is read back from the flash and loaded into the +* memory instead of scanning every time. The Bad Block Table(BBT) is written +* into one of the the last four blocks in the flash memory. The last four +* blocks are marked as Reserved so that user can't erase/program those blocks. +* +* There are two bad block tables, a primary table and a mirror table. The +* tables are versioned and incrementing version number is used to detect and +* recover from interrupted updates. Each table is stored in a separate block, +* beginning in the first page of that block. Only two blocks would be necessary +* in the absence of bad blocks within the last four; the range of four provides +* a little slack in case one or two of those blocks is bad. These blocks are +* marked as reserved and cannot be programmed by the user. A NAND Flash device +* with 3 or more factory bad blocks in the last 4 cannot be used. The bad block +* table signature is written into the spare data area of the pages containing +* bad block table so that upon rebooting the bad block table signature is +* searched and the bad block table is loaded into RAM. The signature is "Bbt0" +* for primary Bad Block Table and "1tbB" for Mirror Bad Block Table. The +* version offset follows the signature offset in the spare data area. The +* version number increments on every update to the bad block table and the +* version wraps at 0xff. +* +* Each block in the Bad Block Table(BBT) is represented by 2 bits. +* The two bits are encoded as follows in RAM BBT. +* 0'b00 -> Good Block +* 0'b01 -> Block is bad due to wear +* 0'b10 -> Reserved block +* 0'b11 -> Factory marked bad block +* +* While writing to the flash the two bits are encoded as follows. +* 0'b00 -> Factory marked bad block +* 0'b01 -> Reserved block +* 0'b10 -> Block is bad due to wear +* 0'b11 -> Good Block +* +* The user can check for the validity of the block using the API +* XNandPsu_IsBlockBad and take the action based on the return value. Also user +* can update the bad block table using XNandPsu_MarkBlockBad API. +* +* @note None +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- ---------- ----------------------------------------------- +* 1.0 nm 05/06/2014 First release +* 2.0 sb 01/12/2015 Added support for writing BBT signature and version +* in page section by enabling XNANDPSU_BBT_NO_OOB. +* Modified Bbt Signature and Version Offset value for +* Oob and No-Oob region. +* </pre> +* +******************************************************************************/ +#ifndef XNANDPSU_BBM_H /* prevent circular inclusions */ +#define XNANDPSU_BBM_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xnandpsu.h" + +/************************** Constant Definitions *****************************/ +/* Block definitions for RAM based Bad Block Table (BBT) */ +#define XNANDPSU_BLOCK_GOOD 0x0U /**< Block is good */ +#define XNANDPSU_BLOCK_BAD 0x1U /**< Block is bad */ +#define XNANDPSU_BLOCK_RESERVED 0x2U /**< Reserved block */ +#define XNANDPSU_BLOCK_FACTORY_BAD 0x3U /**< Factory marked bad + block */ +/* Block definitions for FLASH based Bad Block Table (BBT) */ +#define XNANDPSU_FLASH_BLOCK_GOOD 0x3U /**< Block is good */ +#define XNANDPSU_FLASH_BLOCK_BAD 0x2U /**< Block is bad */ +#define XNANDPSU_FLASH_BLOCK_RESERVED 0x1U /**< Reserved block */ +#define XNANDPSU_FLASH_BLOCK_FAC_BAD 0x0U /**< Factory marked bad + block */ + +#define XNANDPSU_BBT_SCAN_2ND_PAGE 0x00000001U /**< Scan the + second page + for bad block + information + */ +#define XNANDPSU_BBT_DESC_PAGE_OFFSET 0U /**< Page offset of Bad + Block Table Desc */ +#define XNANDPSU_BBT_DESC_SIG_OFFSET 8U /**< Bad Block Table + signature offset */ +#define XNANDPSU_BBT_DESC_VER_OFFSET 12U /**< Bad block Table + version offset */ +#define XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET 0U /**< Bad Block Table + signature offset in + page memory */ +#define XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET 4U /**< Bad block Table + version offset in + page memory */ +#define XNANDPSU_BBT_DESC_SIG_LEN 4U /**< Bad block Table + signature length */ +#define XNANDPSU_BBT_DESC_MAX_BLOCKS 64U /**< Bad block Table + max blocks */ + +#define XNANDPSU_BBT_BLOCK_SHIFT 2U /**< Block shift value + for a block in BBT */ +#define XNANDPSU_BBT_ENTRY_NUM_BLOCKS 4U /**< Num of blocks in + one BBT entry */ +#define XNANDPSU_BB_PTRN_OFF_SML_PAGE 5U /**< Bad block pattern + offset in a page */ +#define XNANDPSU_BB_PTRN_LEN_SML_PAGE 1U /**< Bad block pattern + length */ +#define XNANDPSU_BB_PTRN_OFF_LARGE_PAGE 0U /**< Bad block pattern + offset in a large + page */ +#define XNANDPSU_BB_PTRN_LEN_LARGE_PAGE 2U /**< Bad block pattern + length */ +#define XNANDPSU_BB_PATTERN 0xFFU /**< Bad block pattern + to search in a page + */ +#define XNANDPSU_BLOCK_TYPE_MASK 0x03U /**< Block type mask */ +#define XNANDPSU_BLOCK_SHIFT_MASK 0x06U /**< Block shift mask + for a Bad Block Table + entry byte */ + +#define XNANDPSU_ONDIE_SIG_OFFSET 0x4U +#define XNANDPSU_ONDIE_VER_OFFSET 0x14U + +#define XNANDPSU_BBT_VERSION_LENGTH 1U +#define XNANDPSU_BBT_SIG_LENGTH 4U + +#define XNANDPSU_BBT_BUF_LENGTH ((XNANDPSU_MAX_BLOCKS >> \ + XNANDPSU_BBT_BLOCK_SHIFT) + \ + (XNANDPSU_BBT_DESC_SIG_OFFSET + \ + XNANDPSU_BBT_SIG_LENGTH + \ + XNANDPSU_BBT_VERSION_LENGTH)) +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro returns the Block shift value corresponding to a Block. +* +* @param Block is the block number. +* +* @return Block shift value +* +* @note None. +* +*****************************************************************************/ +#define XNandPsu_BbtBlockShift(Block) \ + (u8)(((Block) * 2U) & XNANDPSU_BLOCK_SHIFT_MASK) + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XNandPsu_InitBbtDesc(XNandPsu *InstancePtr); + +s32 XNandPsu_IsBlockBad(XNandPsu *InstancePtr, u32 Block); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/bsps/include/dev/nand/xnandpsu_hw.h b/bsps/include/dev/nand/xnandpsu_hw.h new file mode 100644 index 0000000000..e3a648b136 --- /dev/null +++ b/bsps/include/dev/nand/xnandpsu_hw.h @@ -0,0 +1,483 @@ +/****************************************************************************** +* Copyright (C) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xnandpsu_hw.h +* @addtogroup Overview +* @{ +* +* This file contains identifiers and low-level macros/functions for the Arasan +* NAND flash controller driver. +* +* See xnandpsu.h for more information. +* +* @note None +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- ---------- ----------------------------------------------- +* 1.0 nm 05/06/2014 First Release +* 2.0 sb 11/04/2014 Changed XNANDPSU_ECC_SLC_MLC_MASK to +* XNANDPSU_ECC_HAMMING_BCH_MASK. +* 1.7 akm 09/03/20 Updated the Makefile to support parallel make +* execution. +* </pre> +* +******************************************************************************/ + +#ifndef XNANDPSU_HW_H /* prevent circular inclusions */ +#define XNANDPSU_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/************************** Register Offset Definitions **********************/ + +#define XNANDPSU_PKT_OFFSET 0x00U /**< Packet Register */ +#define XNANDPSU_MEM_ADDR1_OFFSET 0x04U /**< Memory Address + Register 1 */ +#define XNANDPSU_MEM_ADDR2_OFFSET 0x08U /**< Memory Address + Register 2 */ +#define XNANDPSU_CMD_OFFSET 0x0CU /**< Command Register */ +#define XNANDPSU_PROG_OFFSET 0x10U /**< Program Register */ +#define XNANDPSU_INTR_STS_EN_OFFSET 0x14U /**< Interrupt Status + Enable Register */ +#define XNANDPSU_INTR_SIG_EN_OFFSET 0x18U /**< Interrupt Signal + Enable Register */ +#define XNANDPSU_INTR_STS_OFFSET 0x1CU /**< Interrupt Status + Register */ +#define XNANDPSU_READY_BUSY_OFFSET 0x20U /**< Ready/Busy status + Register */ +#define XNANDPSU_FLASH_STS_OFFSET 0x28U /**< Flash Status Register */ +#define XNANDPSU_TIMING_OFFSET 0x2CU /**< Timing Register */ +#define XNANDPSU_BUF_DATA_PORT_OFFSET 0x30U /**< Buffer Data Port + Register */ +#define XNANDPSU_ECC_OFFSET 0x34U /**< ECC Register */ +#define XNANDPSU_ECC_ERR_CNT_OFFSET 0x38U /**< ECC Error Count + Register */ +#define XNANDPSU_ECC_SPR_CMD_OFFSET 0x3CU /**< ECC Spare Command + Register */ +#define XNANDPSU_ECC_CNT_1BIT_OFFSET 0x40U /**< Error Count 1bit + Register */ +#define XNANDPSU_ECC_CNT_2BIT_OFFSET 0x44U /**< Error Count 2bit + Register */ +#define XNANDPSU_ECC_CNT_3BIT_OFFSET 0x48U /**< Error Count 3bit + Register */ +#define XNANDPSU_ECC_CNT_4BIT_OFFSET 0x4CU /**< Error Count 4bit + Register */ +#define XNANDPSU_CPU_REL_OFFSET 0x58U /**< CPU Release Register */ +#define XNANDPSU_ECC_CNT_5BIT_OFFSET 0x5CU /**< Error Count 5bit + Register */ +#define XNANDPSU_ECC_CNT_6BIT_OFFSET 0x60U /**< Error Count 6bit + Register */ +#define XNANDPSU_ECC_CNT_7BIT_OFFSET 0x64U /**< Error Count 7bit + Register */ +#define XNANDPSU_ECC_CNT_8BIT_OFFSET 0x68U /**< Error Count 8bit + Register */ +#define XNANDPSU_DATA_INTF_OFFSET 0x6CU /**< Data Interface Register */ +#define XNANDPSU_DMA_SYS_ADDR0_OFFSET 0x50U /**< DMA System Address 0 + Register */ +#define XNANDPSU_DMA_SYS_ADDR1_OFFSET 0x24U /**< DMA System Address 1 + Register */ +#define XNANDPSU_DMA_BUF_BND_OFFSET 0x54U /**< DMA Buffer Boundary + Register */ +#define XNANDPSU_SLV_DMA_CONF_OFFSET 0x80U /**< Slave DMA Configuration + Register */ + +/** @name Packet Register bit definitions and masks + * @{ + */ +#define XNANDPSU_PKT_PKT_SIZE_MASK 0x000007FFU /**< Packet Size */ +#define XNANDPSU_PKT_PKT_CNT_MASK 0x00FFF000U /**< Packet Count*/ +#define XNANDPSU_PKT_PKT_CNT_SHIFT 12U /**< Packet Count Shift */ +/* @} */ + +/** @name Memory Address Register 1 bit definitions and masks + * @{ + */ +#define XNANDPSU_MEM_ADDR1_COL_ADDR_MASK 0x0000FFFFU /**< Column Address + Mask */ +#define XNANDPSU_MEM_ADDR1_PG_ADDR_MASK 0xFFFF0000U /**< Page, Block + Address Mask */ +#define XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT 16U /**< Page Shift */ +/* @} */ + +/** @name Memory Address Register 2 bit definitions and masks + * @{ + */ +#define XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK 0x000000FFU /**< Memory Address + */ +#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK 0x01000000U /**< Bus Width */ +#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK 0x0E000000U /**< BCH Mode + Value */ +#define XNANDPSU_MEM_ADDR2_MODE_MASK 0x30000000U /**< Flash + Connection Mode */ +#define XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK 0xC0000000U /**< Chip Select */ +#define XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT 30U /**< Chip select + shift */ +#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT 24U /**< Bus width shift */ +#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT 25U +/* @} */ + +/** @name Command Register bit definitions and masks + * @{ + */ +#define XNANDPSU_CMD_CMD1_MASK 0x000000FFU /**< 1st Cycle + Command */ +#define XNANDPSU_CMD_CMD2_MASK 0x0000FF00U /**< 2nd Cycle + Command */ +#define XNANDPSU_CMD_PG_SIZE_MASK 0x03800000U /**< Page Size */ +#define XNANDPSU_CMD_DMA_EN_MASK 0x0C000000U /**< DMA Enable + Mode */ +#define XNANDPSU_CMD_ADDR_CYCLES_MASK 0x70000000U /**< Number of + Address Cycles */ +#define XNANDPSU_CMD_ECC_ON_MASK 0x80000000U /**< ECC ON/OFF */ +#define XNANDPSU_CMD_CMD2_SHIFT 8U /**< 2nd Cycle Command + Shift */ +#define XNANDPSU_CMD_PG_SIZE_SHIFT 23U /**< Page Size Shift */ +#define XNANDPSU_CMD_DMA_EN_SHIFT 26U /**< DMA Enable Shift */ +#define XNANDPSU_CMD_ADDR_CYCLES_SHIFT 28U /**< Number of Address + Cycles Shift */ +#define XNANDPSU_CMD_ECC_ON_SHIFT 31U /**< ECC ON/OFF */ +/* @} */ + +/** @name Program Register bit definitions and masks + * @{ + */ +#define XNANDPSU_PROG_RD_MASK 0x00000001U /**< Read */ +#define XNANDPSU_PROG_MUL_DIE_MASK 0x00000002U /**< Multi Die */ +#define XNANDPSU_PROG_BLK_ERASE_MASK 0x00000004U /**< Block Erase */ +#define XNANDPSU_PROG_RD_STS_MASK 0x00000008U /**< Read Status */ +#define XNANDPSU_PROG_PG_PROG_MASK 0x00000010U /**< Page Program */ +#define XNANDPSU_PROG_MUL_DIE_RD_MASK 0x00000020U /**< Multi Die Rd */ +#define XNANDPSU_PROG_RD_ID_MASK 0x00000040U /**< Read ID */ +#define XNANDPSU_PROG_RD_PRM_PG_MASK 0x00000080U /**< Read Param + Page */ +#define XNANDPSU_PROG_RST_MASK 0x00000100U /**< Reset */ +#define XNANDPSU_PROG_GET_FEATURES_MASK 0x00000200U /**< Get Features */ +#define XNANDPSU_PROG_SET_FEATURES_MASK 0x00000400U /**< Set Features */ +#define XNANDPSU_PROG_RD_UNQ_ID_MASK 0x00000800U /**< Read Unique + ID */ +#define XNANDPSU_PROG_RD_STS_ENH_MASK 0x00001000U /**< Read Status + Enhanced */ +#define XNANDPSU_PROG_RD_INTRLVD_MASK 0x00002000U /**< Read + Interleaved */ +#define XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK 0x00004000U /**< Change Read + Column + Enhanced */ +#define XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK 0x00008000U /**< Copy Back + Interleaved */ +#define XNANDPSU_PROG_RD_CACHE_START_MASK 0x00010000U /**< Read Cache + Start */ +#define XNANDPSU_PROG_RD_CACHE_SEQ_MASK 0x00020000U /**< Read Cache + Sequential */ +#define XNANDPSU_PROG_RD_CACHE_RAND_MASK 0x00040000U /**< Read Cache + Random */ +#define XNANDPSU_PROG_RD_CACHE_END_MASK 0x00080000U /**< Read Cache + End */ +#define XNANDPSU_PROG_SMALL_DATA_MOVE_MASK 0x00100000U /**< Small Data + Move */ +#define XNANDPSU_PROG_CHNG_ROW_ADDR_MASK 0x00200000U /**< Change Row + Address */ +#define XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK 0x00400000U /**< Change Row + Address End */ +#define XNANDPSU_PROG_RST_LUN_MASK 0x00800000U /**< Reset LUN */ +#define XNANDPSU_PROG_PGM_PG_CLR_MASK 0x01000000U /**< Enhanced + Program Page + Register Clear */ +#define XNANDPSU_PROG_VOL_SEL_MASK 0x02000000U /**< Volume Select */ +#define XNANDPSU_PROG_ODT_CONF_MASK 0x04000000U /**< ODT Configure */ +/* @} */ + +/** @name Interrupt Status Enable Register bit definitions and masks + * @{ + */ +#define XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer + Write Ready + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer + Read Ready + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer + Complete + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi + Bit Error + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single + Bit Error + Status + Enable, + BCH Detect + Error + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA + Status + Enable */ +#define XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error + AHB Status + Enable */ +/* @} */ + +/** @name Interrupt Signal Enable Register bit definitions and masks + * @{ + */ +#define XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer + Write Ready + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer + Read Ready + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer + Complete + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi + Bit Error + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single + Bit Error + Signal + Enable, + BCH Detect + Error + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA + Signal + Enable */ +#define XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error + AHB Signal + Enable */ +/* @} */ + +/** @name Interrupt Status Register bit definitions and masks + * @{ + */ +#define XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer + Write + Ready */ +#define XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer + Read + Ready */ +#define XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer + Complete */ +#define XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi + Bit Error */ +#define XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single + Bit Error, + BCH Detect + Error */ +#define XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA + Interrupt + */ +#define XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error + AHB */ +/* @} */ + +/** @name Interrupt bit definitions and masks + * @{ + */ +#define XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer Write + Ready Status + Enable */ +#define XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer Read + Ready Status + Enable */ +#define XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer + Complete Status + Enable */ +#define XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi Bit Error + Status Enable */ +#define XNANDPSU_INTR_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single Bit Error + Status Enable, + BCH Detect Error + Status Enable */ +#define XNANDPSU_INTR_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA Status + Enable */ +#define XNANDPSU_INTR_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error AHB Status + Enable */ +/* @} */ + +/** @name ID2 Register bit definitions and masks + * @{ + */ +#define XNANDPSU_ID2_DEVICE_ID2_MASK 0x000000FFU /**< MSB Device ID */ +/* @} */ + +/** @name Flash Status Register bit definitions and masks + * @{ + */ +#define XNANDPSU_FLASH_STS_FLASH_STS_MASK 0x0000FFFFU /**< Flash Status + Value */ +/* @} */ + +/** @name Timing Register bit definitions and masks + * @{ + */ +#define XNANDPSU_TIMING_TCCS_TIME_MASK 0x00000003U /**< Change column + setup time */ +#define XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK 0x00000004U /**< Slow/Fast device + */ +#define XNANDPSU_TIMING_DQS_BUFF_SEL_MASK 0x00000078U /**< Write/Read data + transaction value + */ +#define XNANDPSU_TIMING_TADL_TIME_MASK 0x00007F80U /**< Address latch + enable to Data + loading time */ +/* @} */ + +/** @name ECC Register bit definitions and masks + * @{ + */ +#define XNANDPSU_ECC_ADDR_MASK 0x0000FFFFU /**< ECC address */ +#define XNANDPSU_ECC_SIZE_MASK 0x01FF0000U /**< ECC size */ +#define XNANDPSU_ECC_HAMMING_BCH_MASK 0x02000000U /**< Hamming/BCH + support */ +/* @} */ + +/** @name ECC Error Count Register bit definitions and masks + * @{ + */ +#define XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK 0x000000FFU /**< Packet + bound error + count */ +#define XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK 0x0000FF00U /**< Page + bound error + count */ +/* @} */ + +/** @name ECC Spare Command Register bit definitions and masks + * @{ + */ +#define XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK 0x000000FFU /**< ECC + spare + command */ +#define XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK 0x70000000U /**< Number + of ECC/ + spare + address + cycles */ +/* @} */ + +/** @name Data Interface Register bit definitions and masks + * @{ + */ +#define XNANDPSU_DATA_INTF_SDR_MASK 0x00000007U /**< SDR mode */ +#define XNANDPSU_DATA_INTF_NVDDR_MASK 0x00000038U /**< NVDDR mode */ +#define XNANDPSU_DATA_INTF_NVDDR2_MASK 0x000001C0U /**< NVDDR2 mode */ +#define XNANDPSU_DATA_INTF_DATA_INTF_MASK 0x00000600U /**< Data + Interface */ +#define XNANDPSU_DATA_INTF_NVDDR_SHIFT 3U /**< NVDDR mode shift */ +#define XNANDPSU_DATA_INTF_DATA_INTF_SHIFT 9U /**< Data Interface Shift */ +/* @} */ + +/** @name DMA Buffer Boundary Register bit definitions and masks + * @{ + */ +#define XNANDPSU_DMA_BUF_BND_BND_MASK 0x00000007U /**< DMA buffer + boundary */ +#define XNANDPSU_DMA_BUF_BND_4K 0x0U +#define XNANDPSU_DMA_BUF_BND_8K 0x1U +#define XNANDPSU_DMA_BUF_BND_16K 0x2U +#define XNANDPSU_DMA_BUF_BND_32K 0x3U +#define XNANDPSU_DMA_BUF_BND_64K 0x4U +#define XNANDPSU_DMA_BUF_BND_128K 0x5U +#define XNANDPSU_DMA_BUF_BND_256K 0x6U +#define XNANDPSU_DMA_BUF_BND_512K 0x7U +/* @} */ + +/** @name Slave DMA Configuration Register bit definitions and masks + * @{ + */ +#define XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK 0x00000001U /**< Slave + DMA + Transfer + Direction + */ +#define XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK 0x001FFFFEU /**< Slave + DMA + Transfer + Count */ +#define XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK 0x00E00000U /**< Slave + DMA + Burst + Size */ +#define XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK 0x0F000000U /**< DMA + Timeout + Counter + Value */ +#define XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK 0x10000000U /**< Slave + DMA + Enable */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddress is the base address of controller registers. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register. +* +* @note C-style signature: +* u32 XNandPsu_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XNandPsu_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/****************************************************************************/ +/** +* +* This macro writes the given register. +* +* @param BaseAddress is the the base address of controller registers. +* @param RegOffset is the register offset to be written. +* @param Data is the the 32-bit value to write to the register. +* +* @return None. +* +* @note C-style signature: +* void XNandPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +******************************************************************************/ +#define XNandPsu_WriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32(((BaseAddress) + (RegOffset)), (Data)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* XNANDPSU_HW_H end of protection macro */ +/** @} */ diff --git a/bsps/include/dev/nand/xnandpsu_onfi.h b/bsps/include/dev/nand/xnandpsu_onfi.h new file mode 100644 index 0000000000..97ea3c404e --- /dev/null +++ b/bsps/include/dev/nand/xnandpsu_onfi.h @@ -0,0 +1,316 @@ +/****************************************************************************** +* Copyright (C) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xnandpsu_onfi.h +* @addtogroup Overview +* @{ +* +* This file defines all the ONFI 3.1 specific commands and values. +* +* @note None +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- ---------- ----------------------------------------------- +* 1.0 nm 05/06/2014 First release +* 1.4 nsk 04/10/2018 Added ICCARM compiler support. +* </pre> +* +******************************************************************************/ +#ifndef XNANDPSU_ONFI_H /* prevent circular inclusions */ +#define XNANDPSU_ONFI_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ +/* Standard ONFI 3.1 Commands */ +/* ONFI 3.1 Mandatory Commands */ +#define ONFI_CMD_RD1 0x00U /**< Read (1st cycle) */ +#define ONFI_CMD_RD2 0x30U /**< Read (2nd cycle) */ +#define ONFI_CMD_CHNG_RD_COL1 0x05U /**< Change Read Column + (1st cycle) */ +#define ONFI_CMD_CHNG_RD_COL2 0xE0U /**< Change Read Column + (2nd cycle) */ +#define ONFI_CMD_BLK_ERASE1 0x60U /**< Block Erase (1st cycle) */ +#define ONFI_CMD_BLK_ERASE2 0xD0U /**< Block Erase (2nd cycle) */ +#define ONFI_CMD_RD_STS 0x70U /**< Read Status */ +#define ONFI_CMD_PG_PROG1 0x80U /**< Page Program(1st cycle) */ +#define ONFI_CMD_PG_PROG2 0x10U /**< Page Program(2nd cycle) */ +#define ONFI_CMD_CHNG_WR_COL 0x85U /**< Change Write Column */ +#define ONFI_CMD_RD_ID 0x90U /**< Read ID */ +#define ONFI_CMD_RD_PRM_PG 0xECU /**< Read Parameter Page */ +#define ONFI_CMD_RST 0xFFU /**< Reset */ +/* ONFI 3.1 Optional Commands */ +#define ONFI_CMD_MUL_RD1 0x00U /**< Multiplane Read + (1st cycle) */ +#define ONFI_CMD_MUL_RD2 0x32U /**< Multiplane Read + (2nd cycle) */ +#define ONFI_CMD_CPBK_RD1 0x00U /**< Copyback Read + (1st cycle) */ +#define ONFI_CMD_CPBK_RD2 0x35U /**< Copyback Read + (2nd cycle) */ +#define ONFI_CMD_CHNG_RD_COL_ENHCD1 0x06U /**< Change Read Column + Enhanced (1st cycle) */ +#define ONFI_CMD_CHNG_RD_COL_ENHCD2 0xE0U /**< Change Read Column + Enhanced (2nd cycle) */ +#define ONFI_CMD_RD_CACHE_RND1 0x00U /**< Read Cache Random + (1st cycle) */ +#define ONFI_CMD_RD_CACHE_RND2 0x31U /**< Read Cache Random + (2nd cycle) */ +#define ONFI_CMD_RD_CACHE_SEQ 0x31U /**< Read Cache Sequential */ +#define ONFI_CMD_RD_CACHE_END 0x3FU /**< Read Cache End */ +#define ONFI_CMD_MUL_BLK_ERASE1 0x60U /**< Multiplane Block Erase + (1st cycle) */ +#define ONFI_CMD_MUL_BLK_ERASE2 0xD1U /**< Multiplane Block Erase + (2nd cycle) */ +#define ONFI_CMD_RD_STS_ENHCD 0x78U /**< Read Status Enhanced */ +#define ONFI_CMD_BLK_ERASE_INTRLVD2 0xD1U /**< Block Erase Interleaved + (2nd cycle) */ +#define ONFI_CMD_MUL_PG_PROG1 0x80U /**< Multiplane Page Program + (1st cycle) */ +#define ONFI_CMD_MUL_PG_PROG2 0x11U /**< Multiplane Page Program + (2nd cycle) */ +#define ONFI_CMD_PG_CACHE_PROG1 0x80U /**< Page Cache Program + (1st cycle) */ +#define ONFI_CMD_PG_CACHE_PROG2 0x15U /**< Page Cache Program + (2nd cycle) */ +#define ONFI_CMD_CPBK_PROG1 0x85U /**< Copyback Program + (1st cycle) */ +#define ONFI_CMD_CPBK_PROG2 0x10U /**< Copyback Program + (2nd cycle) */ +#define ONFI_CMD_MUL_CPBK_PROG1 0x85U /**< Multiplane Copyback + Program (1st cycle) */ +#define ONFI_CMD_MUL_CPBK_PROG2 0x10U /**< Multiplane Copyback + Program (2nd cycle) */ +#define ONFI_CMD_SMALL_DATA_MV1 0x85U /**< Small Data Move + (1st cycle) */ +#define ONFI_CMD_SMALL_DATA_MV2 0x10U /**< Small Data Move + (2nd cycle) */ +#define ONFI_CMD_CHNG_ROW_ADDR 0x85U /**< Change Row Address */ +#define ONFI_CMD_VOL_SEL 0xE1U /**< Volume Select */ +#define ONFI_CMD_ODT_CONF 0xE2U /**< ODT Configure */ +#define ONFI_CMD_RD_UNIQID 0xEDU /**< Read Unique ID */ +#define ONFI_CMD_GET_FEATURES 0xEEU /**< Get Features */ +#define ONFI_CMD_SET_FEATURES 0xEFU /**< Set Features */ +#define ONFI_CMD_LUN_GET_FEATURES 0xD4U /**< LUN Get Features */ +#define ONFI_CMD_LUN_SET_FEATURES 0xD5U /**< LUN Set Features */ +#define ONFI_CMD_RST_LUN 0xFAU /**< Reset LUN */ +#define ONFI_CMD_SYN_RST 0xFCU /**< Synchronous Reset */ + +/* ONFI Status Register bit offsets */ +#define ONFI_STS_FAIL 0x01U /**< FAIL */ +#define ONFI_STS_FAILC 0x02U /**< FAILC */ +#define ONFI_STS_CSP 0x08U /**< CSP */ +#define ONFI_STS_VSP 0x10U /**< VSP */ +#define ONFI_STS_ARDY 0x20U /**< ARDY */ +#define ONFI_STS_RDY 0x40U /**< RDY */ +#define ONFI_STS_WP 0x80U /**< WP_n */ + +/* ONFI constants */ +#define ONFI_CRC_LEN 254U /**< ONFI CRC Buf Length */ +#define ONFI_PRM_PG_LEN 256U /**< Parameter Page Length */ +#define ONFI_MND_PRM_PGS 3U /**< Number of mandatory + parameter pages */ +#define ONFI_SIG_LEN 4U /**< Signature Length */ +#define ONFI_CMD_INVALID 0x00U /**< Invalid Command */ + +#define ONFI_READ_ID_LEN 4U /**< ONFI ID length */ +#define ONFI_READ_ID_ADDR 0x20U /**< ONFI Read ID Address */ +#define ONFI_READ_ID_ADDR_CYCLES 1U /**< ONFI Read ID Address + cycles */ + +#define ONFI_PRM_PG_ADDR_CYCLES 1U /**< ONFI Read Parameter page + address cycles */ + +/** + * This enum defines the ONFI 3.1 commands. + */ +enum OnfiCommandList { + READ=0, /**< Read */ + MULTIPLANE_READ, /**< Multiplane Read */ + COPYBACK_READ, /**< Copyback Read */ + CHANGE_READ_COLUMN, /**< Change Read Column */ + CHANGE_READ_COLUMN_ENHANCED, /**< Change Read Column Enhanced */ + READ_CACHE_RANDOM, /**< Read Cache Random */ + READ_CACHE_SEQUENTIAL, /**< Read Cache Sequential */ + READ_CACHE_END, /**< Read Cache End */ + BLOCK_ERASE, /**< Block Erase */ + MULTIPLANE_BLOCK_ERASE, /**< Multiplane Block Erase */ + READ_STATUS, /**< Read Status */ + READ_STATUS_ENHANCED, /**< Read Status Enhanced */ + PAGE_PROGRAM, /**< Page Program */ + MULTIPLANE_PAGE_PROGRAM, /**< Multiplane Page Program */ + PAGE_CACHE_PROGRAM, /**< Page Cache Program */ + COPYBACK_PROGRAM, /**< Copyback Program */ + MULTIPLANE_COPYBACK_PROGRAM, /**< Multiplance Copyback Program */ + SMALL_DATA_MOVE, /**< Small Data Move */ + CHANGE_WRITE_COLUMN, /**< Change Write Column */ + CHANGE_ROW_ADDR, /**< Change Row Address */ + READ_ID, /**< Read ID */ + VOLUME_SELECT, /**< Volume Select */ + ODT_CONFIGURE, /**< ODT Configure */ + READ_PARAM_PAGE, /**< Read Parameter Page */ + READ_UNIQUE_ID, /**< Read Unique ID */ + GET_FEATURES, /**< Get Features */ + SET_FEATURES, /**< Set Features */ + LUN_GET_FEATURES, /**< LUN Get Features */ + LUN_SET_FEATURES, /**< LUN Set Features */ + RESET_LUN, /**< Reset LUN */ + SYN_RESET, /**< Synchronous Reset */ + RESET, /**< Reset */ + MAX_CMDS /**< Dummy Command */ +}; + +/**************************** Type Definitions *******************************/ +/* Parameter page structure of ONFI 3.1 specification. */ +#ifdef __ICCARM__ +#pragma pack(push, 1) +#endif +typedef struct { + /* Revision information and features block */ + u8 Signature[4]; /**< Parameter page signature */ + u16 Revision; /**< Revision Number */ + u16 Features; /**< Features supported */ + u16 OptionalCmds; /**< Optional commands supported */ + u8 JedecJtgPrmAdvCmd; /**< ONFI JEDEC JTG primary advanced + command support */ + u8 Reserved0; /**< Reserved (11) */ + u16 ExtParamPageLen; /**< Extended Parameter Page Length */ + u8 NumOfParamPages; /**< Number of Parameter Pages */ + u8 Reserved1[17]; /**< Reserved (15-31) */ + /* Manufacturer information block */ + u8 DeviceManufacturer[12]; /**< Device manufacturer */ + u8 DeviceModel[20]; /**< Device model */ + u8 JedecManufacturerId; /**< JEDEC Manufacturer ID */ + u8 DateCode[2]; /**< Date code */ + u8 Reserved2[13]; /**< Reserved (67-79) */ + /* Memory organization block */ + u32 BytesPerPage; /**< Number of data bytes per page */ + u16 SpareBytesPerPage; /**< Number of spare bytes per page */ + u32 BytesPerPartialPage; /**< Number of data bytes per + partial page */ + u16 SpareBytesPerPartialPage; /**< Number of spare bytes per + partial page */ + u32 PagesPerBlock; /**< Number of pages per block */ + u32 BlocksPerLun; /**< Number of blocks per LUN */ + u8 NumLuns; /**< Number of LUN's */ + u8 AddrCycles; /**< Number of address cycles */ + u8 BitsPerCell; /**< Number of bits per cell */ + u16 MaxBadBlocksPerLun; /**< Bad blocks maximum per LUN */ + u16 BlockEndurance; /**< Block endurance */ + u8 GuaranteedValidBlock; /**< Guaranteed valid blocks at + beginning of target */ + u16 BlockEnduranceGVB; /**< Block endurance for guaranteed + valid block */ + u8 ProgramsPerPage; /**< Number of programs per page */ + u8 PartialProgAttr; /**< Partial programming attributes */ + u8 EccBits; /**< Number of bits ECC + correctability */ + u8 PlaneAddrBits; /**< Number of plane address bits */ + u8 PlaneOperationAttr; /**< Multi-plane operation + attributes */ + u8 EzNandSupport; /**< EZ NAND support */ + u8 Reserved3[12]; /**< Reserved (116 - 127) */ + /* Electrical parameters block */ + u8 IOPinCapacitance; /**< I/O pin capacitance, maximum */ + u16 SDRTimingMode; /**< SDR Timing mode support */ + u16 SDRPagecacheTimingMode; /**< SDR Program cache timing mode */ + u16 TProg; /**< Maximum page program time */ + u16 TBers; /**< Maximum block erase time */ + u16 TR; /**< Maximum page read time */ + u16 TCcs; /**< Maximum change column setup + time */ + u8 NVDDRTimingMode; /**< NVDDR timing mode support */ + u8 NVDDR2TimingMode; /**< NVDDR2 timing mode support */ + u8 SynFeatures; /**< NVDDR/NVDDR2 features */ + u16 ClkInputPinCap; /**< CLK input pin capacitance */ + u16 IOPinCap; /**< I/O pin capacitance */ + u16 InputPinCap; /**< Input pin capacitance typical */ + u8 InputPinCapMax; /**< Input pin capacitance maximum */ + u8 DrvStrength; /**< Driver strength support */ + u16 TMr; /**< Maximum multi-plane read time */ + u16 TAdl; /**< Program page register clear + enhancement value */ + u16 TEr; /**< Typical page read time for + EZ NAND */ + u8 NVDDR2Features; /**< NVDDR2 Features */ + u8 NVDDR2WarmupCycles; /**< NVDDR2 Warmup Cycles */ + u8 Reserved4[4]; /**< Reserved (160 - 163) */ + /* Vendor block */ + u16 VendorRevisionNum; /**< Vendor specific revision number */ + u8 VendorSpecific[88]; /**< Vendor specific */ + u16 Crc; /**< Integrity CRC */ +#ifdef __ICCARM__ +} OnfiParamPage; +#pragma pack(pop) +#else +}__attribute__((packed))OnfiParamPage; +#endif + +/* ONFI extended parameter page structure. */ +#ifdef __ICCARM__ +#pragma pack(push, 1) +#endif +typedef struct { + u16 Crc; + u8 Sig[4]; + u8 Reserved1[10]; + u8 Section0Type; + u8 Section0Len; + u8 Section1Type; + u8 Section1Len; + u8 ResSection[12]; + u8 SectionData[256]; +#ifdef __ICCARM__ +} OnfiExtPrmPage; +#pragma pack(pop) +#else +}__attribute__((packed))OnfiExtPrmPage; +#endif + +/* Driver extended parameter page information. */ +#ifdef __ICCARM__ +#pragma pack(push, 1) +#endif +typedef struct { + u8 NumEccBits; + u8 CodeWordSize; + u16 MaxBadBlocks; + u16 BlockEndurance; + u16 Reserved; +#ifdef __ICCARM__ +} OnfiExtEccBlock; +#pragma pack(pop) +#else +}__attribute__((packed))OnfiExtEccBlock; +#endif + +typedef struct { + u8 Command1; /**< Command Cycle 1 */ + u8 Command2; /**< Command Cycle 2 */ +} OnfiCmdFormat; + +extern const OnfiCmdFormat OnfiCmd[MAX_CMDS]; + +/************************** Function Prototypes ******************************/ + +u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length); + +#ifdef __cplusplus +} +#endif + +#endif /* XNANDPSU_ONFI_H end of protection macro */ +/** @} */ diff --git a/bsps/include/dev/serial/arm-pl011-regs.h b/bsps/include/dev/serial/arm-pl011-regs.h index eaf560ed8b..d6ea9ae11a 100644 --- a/bsps/include/dev/serial/arm-pl011-regs.h +++ b/bsps/include/dev/serial/arm-pl011-regs.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -7,11 +9,28 @@ */ /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_SHARED_ARM_PL011_REGS_H diff --git a/bsps/include/dev/serial/arm-pl011.h b/bsps/include/dev/serial/arm-pl011.h index 75ceb676a8..a22fa1ac06 100644 --- a/bsps/include/dev/serial/arm-pl011.h +++ b/bsps/include/dev/serial/arm-pl011.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -7,11 +9,28 @@ */ /* - * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ARM_SHARED_ARM_PL011_H diff --git a/bsps/include/dev/serial/zynq-uart-regs.h b/bsps/include/dev/serial/zynq-uart-regs.h index 8b6e7d513b..5e872d16c3 100644 --- a/bsps/include/dev/serial/zynq-uart-regs.h +++ b/bsps/include/dev/serial/zynq-uart-regs.h @@ -7,7 +7,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (C) 2013 embedded brains GmbH + * Copyright (C) 2013 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -43,6 +43,8 @@ #include <bsp/utility.h> +#define ZYNQ_UART_DEFAULT_BAUD 115200 + #define ZYNQ_UART_FIFO_DEPTH 64 typedef struct zynq_uart { @@ -158,6 +160,24 @@ typedef struct zynq_uart { #define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) } zynq_uart; +void zynq_uart_initialize(volatile zynq_uart *regs); + +int zynq_uart_read_char_polled(volatile zynq_uart *regs); + +void zynq_uart_write_char_polled(volatile zynq_uart *regs, char c); + +/** + * Flush TX FIFO and wait until it is empty. Used in bsp_reset. + */ +void zynq_uart_reset_tx_flush(volatile zynq_uart *regs); + +int zynq_cal_baud_rate( + uint32_t baudrate, + uint32_t* brgr, + uint32_t* bauddiv, + uint32_t modereg +); + /** @} */ #endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */ diff --git a/bsps/include/dev/serial/zynq-uart-zynq.h b/bsps/include/dev/serial/zynq-uart-zynq.h new file mode 100644 index 0000000000..169037b33a --- /dev/null +++ b/bsps/include/dev/serial/zynq-uart-zynq.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup zynq_uart + * + * @brief This header file provides interfaces with respect to the Zynq + * platform. + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_SERIAL_ZYNQ_UART_ZYNQ_H +#define _DEV_SERIAL_ZYNQ_UART_ZYNQ_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @addtogroup zynq_uart + * + * @{ + */ + +/** + * @brief This constant defines the Xilinx Zynq UART 0 base address. + */ +#define ZYNQ_UART_0_BASE_ADDR 0xe0000000 + +/** + * @brief This constant defines the Xilinx Zynq UART 1 base address. + */ +#define ZYNQ_UART_1_BASE_ADDR 0xe0001000 + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _DEV_SERIAL_ZYNQ_UART_ZYNQ_H */ diff --git a/bsps/include/dev/serial/zynq-uart-zynqmp.h b/bsps/include/dev/serial/zynq-uart-zynqmp.h new file mode 100644 index 0000000000..9f29003053 --- /dev/null +++ b/bsps/include/dev/serial/zynq-uart-zynqmp.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup zynq_uart + * + * @brief This header file provides interfaces with respect to the Zynq + * UltraScale+ MPSoC and RFSoC platforms. + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H +#define _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @addtogroup zynq_uart + * + * @{ + */ + +/** + * @brief This constant defines the Xilinx Zynq UART 0 base address. + */ +#define ZYNQ_UART_0_BASE_ADDR 0xff000000 + +/** + * @brief This constant defines the Xilinx Zynq UART 1 base address. + */ +#define ZYNQ_UART_1_BASE_ADDR 0xff010000 + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H */ diff --git a/bsps/include/dev/serial/zynq-uart.h b/bsps/include/dev/serial/zynq-uart.h index b21e16f6de..002adcdbd6 100644 --- a/bsps/include/dev/serial/zynq-uart.h +++ b/bsps/include/dev/serial/zynq-uart.h @@ -7,7 +7,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (C) 2013, XXX embedded brains GmbH + * Copyright (C) 2013, XXX embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -34,7 +34,7 @@ #ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_H #define LIBBSP_ARM_XILINX_ZYNQ_UART_H -#include <rtems/termiostypes.h> +#include <rtems/termiosdevice.h> #ifdef __cplusplus extern "C" { @@ -59,29 +59,6 @@ typedef struct { extern const rtems_termios_device_handler zynq_uart_handler; -#define ZYNQ_UART_DEFAULT_BAUD 115200 - -void zynq_uart_initialize(rtems_termios_device_context *base); - -int zynq_uart_read_polled(rtems_termios_device_context *base); - -void zynq_uart_write_polled( - rtems_termios_device_context *base, - char c -); - -/** - * Flush TX FIFO and wait until it is empty. Used in bsp_reset. - */ -void zynq_uart_reset_tx_flush(zynq_uart_context *ctx); - -int zynq_cal_baud_rate( - uint32_t baudrate, - uint32_t* brgr, - uint32_t* bauddiv, - uint32_t modereg -); - #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/bsps/include/dev/spi/xqspipsu-flash-helper.h b/bsps/include/dev/spi/xqspipsu-flash-helper.h new file mode 100644 index 0000000000..e689660881 --- /dev/null +++ b/bsps/include/dev/spi/xqspipsu-flash-helper.h @@ -0,0 +1,192 @@ +/****************************************************************************** +* Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#include "xqspipsu.h" + +int QspiPsu_NOR_Initialize( + XQspiPsu *QspiPsuInstancePtr, + u16 QspiPsuIntrId +); + +/*****************************************************************************/ +/** + * + * This function erases the sectors in the serial Flash connected to the + * QSPIPSU interface. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param Address contains the address of the first sector which needs to + * be erased. + * @param ByteCount contains the total size to be erased. + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + * @note None. + * + ******************************************************************************/ +int QspiPsu_NOR_Erase( + XQspiPsu *QspiPsuPtr, + u32 Address, + u32 ByteCount +); + +/*****************************************************************************/ +/** + * + * This function writes to the serial Flash connected to the QSPIPSU interface. + * All the data put into the buffer must be in the same page of the device with + * page boundaries being on 256 byte boundaries. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param Address contains the address to write data to in the Flash. + * @param ByteCount contains the number of bytes to write. + * @param WriteBfrPtr is pointer to the write buffer (which is to be transmitted) + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + * @note None. + * + ******************************************************************************/ +int QspiPsu_NOR_Write_Page( + XQspiPsu *QspiPsuPtr, + u32 Address, + u32 ByteCount, + u8 *WriteBfrPtr +); + +/*****************************************************************************/ +/** + * + * This function writes to the serial Flash connected to the QSPIPSU interface. + * Writes will be broken into device page sized and aligned writes as necessary. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param Address contains the address to write data to in the Flash. + * @param ByteCount contains the number of bytes to write. + * @param WriteBfrPtr is pointer to the write buffer (which is to be transmitted) + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + * @note None. + * + ******************************************************************************/ +int QspiPsu_NOR_Write( + XQspiPsu *QspiPsuPtr, + u32 Address, + u32 ByteCount, + u8 *WriteBfrPtr +); + +/*****************************************************************************/ +/** + * + * This function performs a read. Default setting is in DMA mode. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param Address contains the address of the first sector which needs to + * be erased. + * @param ByteCount contains the total size to be erased. + * @param ReadBfrPtr is pointer to the read buffer to which valid received data + * should be written + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + * @note None. + * + ******************************************************************************/ +int QspiPsu_NOR_Read( + XQspiPsu *QspiPsuPtr, + u32 Address, + u32 ByteCount, + u8 **ReadBfrPtr +); + +/*****************************************************************************/ +/** + * + * This function performs a read of the ECC Status Register for a given address. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param Address contains the address of the ECC unit for which the ECCSR + * needs to be read. The ECC unit contains 16 bytes of user data + * and all bytes in an ECC unit will return the same ECCSR. + * @param ReadBfrPtr is a pointer to a single byte to which the ECCSR will + * be written. + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + * @note Only the three least significant bits of the returned byte are + * meaningful. If all bits are 0, ECC is enabled for this unit and + * no errors have been encountered. + * Bit 0 is 1: ECC is disabled for the requested unit. + * Bit 1 is 1: A single bit error has been corrected in user data. + * Bit 2 is 1: A single bit error has been found in the ECC data + * and may indicate user data corruption. + * + ******************************************************************************/ +int QspiPsu_NOR_Read_Ecc( + XQspiPsu *QspiPsuPtr, + u32 Address, + u8 *ReadBfrPtr +); + +/*****************************************************************************/ +/** + * + * This function returns the size of attached flash parts. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * + * @return The size of attached flash in bytes. + * + ******************************************************************************/ +u32 QspiPsu_NOR_Get_Device_Size(XQspiPsu *QspiPsuPtr); + +/*****************************************************************************/ +/** + * + * This function returns the sector size of attached flash parts. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * + * @return The sector size of attached flash in bytes. + * + ******************************************************************************/ +u32 QspiPsu_NOR_Get_Sector_Size(XQspiPsu *QspiPsuPtr); + +/*****************************************************************************/ +/** + * + * This function performs a read of the RDID configuration space. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param ReadBfrPtr is a pointer to a buffer to be filled with + * configuration data. + * @param ReadLen is the total length of the configuration space to read. + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + ******************************************************************************/ +int QspiPsu_NOR_RDID(XQspiPsu *QspiPsuPtr, u8 *ReadBfrPtr, u32 ReadLen); + +/*****************************************************************************/ +/** + * + * This function performs a read of the SFDP configuration space. + * + * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use. + * @param ReadBfrPtr is a pointer to a buffer to be filled with + * configuration data. + * @param ReadLen is the total length of the configuration space to read. + * + * @return XST_SUCCESS if successful, else XST_FAILURE. + * + ******************************************************************************/ +int QspiPsu_NOR_RDSFDP( + XQspiPsu *QspiPsuPtr, + u32 Address, + u32 ByteCount, + u8 **ReadBfrPtr +); diff --git a/bsps/include/dev/spi/xqspipsu.h b/bsps/include/dev/spi/xqspipsu.h new file mode 100644 index 0000000000..92d38eb0c8 --- /dev/null +++ b/bsps/include/dev/spi/xqspipsu.h @@ -0,0 +1,570 @@ +/****************************************************************************** +* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/*****************************************************************************/ +/** + * + * @file xqspipsu.h + * @addtogroup Overview + * @{ + * @details + * + * This section explains the implementation the functions required to use the + * QSPIPSU hardware to perform a transfer. These are accessible to the user + * via xqspipsu.h. + * + * Generic QSPI interface allows for communication to any QSPI slave device. + * GQSPI contains a GENFIFO into which the bus transfers required are to be + * pushed with appropriate configuration. The controller provides TX and RX + * FIFO's and a DMA to be used for RX transfers. The controller executes each + * GENFIFO entry noting the configuration and places data on the bus as required + * + * The different options in GENFIFO are as follows: + * - IMM_DATA : Can be one byte of data to be transmitted, number of clocks or + * number of bytes in transfer. + * - DATA_XFER : Indicates that data/clocks need to be transmitted or received. + * - EXPONENT : e when 2^e bytes are involved in transfer. + * - SPI_MODE : SPI/Dual SPI/Quad SPI + * - CS : Lower or Upper CS or Both + * - Bus : Lower or Upper Bus or Both + * - TX : When selected, controller transmits data in IMM or fetches number of + * bytes mentioned form TX FIFO. If not selected, dummies are pumped. + * - RX : When selected, controller receives and fills the RX FIFO/allows RX DMA + * of requested number of bytes. If not selected, RX data is discarded. + * - Stripe : Byte stripe over lower and upper bus or not. + * - Poll : Polls response to match for to a set value (used along with POLL_CFG + * registers) and then proceeds to next GENFIFO entry. + * This feature is not currently used in the driver. + * + * GENFIFO has manual and auto start options. + * All DMA requests need a 4-byte aligned destination address buffer and + * size of transfer should also be a multiple of 4. + * This driver supports DMA RX and IO RX. + * + * <b>Initialization & Configuration</b> + * + * This driver uses the GQSPI controller with RX DMA. It supports both + * interrupt and polled transfers. Manual start of GENFIFO is used. + * XQspiPsu_CfgInitialize() initializes the instance variables. + * Additional setting can be done using SetOptions/ClearOptions functions + * and SelectSlave function. + * + * <b>Transfer</b> + * + * Polled or Interrupt transfers can be done. The transfer function needs the + * message(s) to be transmitted in the form of an array of type XQspiPsu_Msg. + * This is supposed to contain the byte count and any TX/RX buffers as required. + * Flags can be used indicate further information such as whether the message + * should be striped. The transfer functions form and write GENFIFO entries, + * check the status of the transfer and report back to the application + * when done. + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- --- -------- -----------------------------------------------. + * 1.0 hk 08/21/14 First release + * sk 03/13/15 Added IO mode support. + * hk 03/18/15 Switch to I/O mode before clearing RX FIFO. + * Clear and disable DMA interrupts/status in abort. + * Use DMA DONE bit instead of BUSY as recommended. + * sk 04/24/15 Modified the code according to MISRAC-2012. + * sk 06/17/15 Removed NULL checks for Rx/Tx buffers. As + * writing/reading from 0x0 location is permitted. + * 1.1 sk 04/12/16 Added debug message prints. + * 1.2 nsk 07/01/16 Added LQSPI support + * Modified XQspiPsu_Select() macro in xqspipsu.h + * Added XQspiPsu_GetLqspiConfigReg() in xqspipsu.h + * Added required macros in xqspipsu_hw.h + * Modified XQspiPsu_SetOptions() to support + * LQSPI options and updated OptionsTable in + * xqspipsu_options.c + * rk 07/15/16 Added support for TapDelays at different frequencies. + * nsk 08/05/16 Added example support PollData and PollTimeout + * Added XQSPIPSU_MSG_FLAG_POLL macro in xqspipsu.h + * Added XQspiPsu_Create_PollConfigData and + * XQspiPsu_PollData() functions in xqspipsu.c + * 1.3 nsk 09/16/16 Update PollData and Polltimeout support for dual parallel + * configuration. Updated XQspiPsu_PollData() and + * XQspiPsu_Create_PollConfigData() functions in xqspipsu.c + * and also modified the polldata example + * ms 03/17/17 Added readme.txt file in examples folder for doxygen + * generation. + * ms 04/05/17 Modified Comment lines in functions of qspipsu + * examples to recognize it as documentation block + * and modified filename tag to include them in + * doxygen examples. + * 1.4 tjs 05/26/17 Added support for accessing upper DDR (0x800000000) + * while booting images from QSPI + * 1.5 tjs 08/08/17 Added index.html file for importing examples + * from system.mss + * 1.5 nsk 08/14/17 Added CCI support + * 1.5 tjs 09/14/17 Modified the checks for 4 byte addressing and commands. + * 1.6 tjs 10/16/17 Flow for accessing flash is made similar to u-boot + * and linux For CR-984966 + * 1.6 tjs 11/02/17 Resolved the compilation errors for ICCARM. CR-988625 + * 1.7 tjs 11/16/17 Removed the unsupported 4 Byte write and sector erase + * commands. + * 1.7 tjs 12/01/17 Added support for MT25QL02G Flash from Micron. CR-990642 + * 1.7 tjs 12/19/17 Added support for S25FL064L from Spansion. CR-990724 + * 1.7 tjs 01/11/18 Added support for MX66L1G45G flash from Macronix CR-992367 + * 1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560) + * 1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448) + * Added XQspiPsu_SetWP() in xqspipsu_options.c + * Added XQspiPsu_WriteProtectToggle() in xqspipsu.c and + * also added write protect example. + * 1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882) + * 1.7 tjs 26/03/18 In dual parallel mode enable both CS when issuing Write + * enable command. CR-998478 + * 1.8 tjs 05/02/18 Added support for IS25LP064 and IS25WP064. + * 1.8 tjs 06/26/18 Added an example for accessing 64bit dma within + * 32 bit application. CR#1004701 + * 1.8 tjs 06/26/18 Removed checkpatch warnings + * 1.8 tjs 07/09/19 Fixed cppcheck, doxygen and gcc warnings. + * 1.8 tjs 07/18/18 Setup64BRxDma() should be called only if the RxAddress is + * greater than 32 bit address space. (CR#1006862) + * 1.8 tjs 07/18/18 Added support for the low density ISSI flash parts. + * 1.8 tjs 09/06/18 Fixed the code in XQspiPsu_GenFifoEntryData() for data + * transfer length up to 255 for reducing the extra loop. + * 1.9 tjs 11/22/17 Added the check for A72 and R5 processors (CR-987075) + * 1.9 tjs 04/17/18 Updated register addresses as per the latest revision + * of versal (CR#999610) + * 1.9 aru 01/17/19 Fixed the violations for MISRAC-2012 + * in safety mode .Done changes such as added U suffix, + * Declared pointer param as const. + * 1.9 nsk 02/01/19 Clear DMA_DST_ADDR_MSB register on 32bit machine, if the + * address is of only 32bit (CR#1020031) + * 1.9 nsk 02/01/19 Added QSPI idling support + * + * 1.9 akm 03/08/19 Set recommended clock and data tap delay values for 40MHZ, + * 100MHZ and 150MHZ frequencies(CR#1023187) + * 1.9 nsk 03/27/19 Update 64bit dma support + * (CR#1018102). + * 1.9 akm 04/03/19 Fixed data alignment warnings on IAR compiler. + * 1.9 akm 04/03/19 Fixed compilation error in XQspiPsu_LqspiRead() + * function on IAR compiler. + * 1.10 sk 08/20/19 Fixed issues in poll timeout feature. + * 1.10 akm 08/22/19 Set recommended tap delay values for 37.5MHZ, 100MHZ and + * 150MHZ frequencies in Versal. + * 1.10 akm 09/05/19 Added Multi Die Erase and Muti Die Read support. + * 1.11 akm 11/07/19 Removed LQSPI register access in Versal. + * 1.11 akm 11/15/19 Fixed Coverity deadcode warning in + * XQspipsu_Calculate_Tapdelay(). + * 1.11 akm 02/19/20 Added XQspiPsu_StartDmaTransfer() and XQspiPsu_CheckDmaDone() + * APIs for non-blocking transfer. + * 1.11 sd 01/02/20 Added clocking support + * 1.11 akm 03/09/20 Reorganize the source code, enable qspi controller and + * interrupts in XQspiPsu_CfgInitialize() API. + * 1.11 akm 03/26/20 Fixed issue by updating XQspiPsu_CfgInitialize to return + * XST_DEVICE_IS_STARTED instead of asserting, when the + * instance is already configured(CR#1058525). + * 1.12 akm 09/02/20 Updated the Makefile to support parallel make execution. + * 1.13 akm 01/04/21 Fix MISRA-C violations. + * 1.13 sne 04/23/21 Fixed doxygen warnings. + * 1.14 akm 06/24/21 Allow enough time for the controller to reset the FIFOs. + * 1.14 akm 08/12/21 Perform Dcache invalidate at the end of the DMA transfer. + * + * </pre> + * + ******************************************************************************/ + +#ifndef XQSPIPSU_H_ /**< prevent circular inclusions */ +#define XQSPIPSU_H_ /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xqspipsu_hw.h" +#include "xil_cache.h" +#include "xil_mem.h" +#if defined (XCLOCKING) +#include "xil_clocking.h" +#endif + +/**************************** Type Definitions *******************************/ +/** + * The handler data type allows the user to define a callback function to + * handle the asynchronous processing for the QSPIPSU device. The application + * using this driver is expected to define a handler of this type to support + * interrupt driven mode. The handler executes in an interrupt context, so + * only minimal processing should be performed. + * + * @param CallBackRef is the callback reference passed in by the upper + * layer when setting the callback functions, and passed back to + * the upper layer when the callback is invoked. Its type is + * not important to the driver, so it is a void pointer. + * @param StatusEvent holds one or more status events that have occurred. + * See the XQspiPsu_SetStatusHandler() for details on the status + * events that can be passed in the callback. + * @param ByteCount indicates how many bytes of data were successfully + * transferred. This may be less than the number of bytes + * requested if the status event indicates an error. + */ +typedef void (*XQspiPsu_StatusHandler) (const void *CallBackRef, u32 StatusEvent, + u32 ByteCount); + +/** + * This typedef contains configuration information for a flash message. + */ +typedef struct { + u8 *TxBfrPtr; /**< Tx Buffer pointer */ + u8 *RxBfrPtr; /**< Rx Buffer pointer */ + u32 ByteCount; /**< Byte Count */ + u32 BusWidth; /**< Bus Width */ + u32 Flags; /**< Flags */ + u8 PollData; /**< Poll Data */ + u32 PollTimeout;/**< Poll Timeout */ + u8 PollStatusCmd; /**< Poll Status command */ + u8 PollBusMask; /**< Poll Bus mask */ + u64 RxAddr64bit; /**< 64 bit Rx address */ + u8 Xfer64bit; /**< 64 bit Tx address */ +} XQspiPsu_Msg; + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + UINTPTR BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ + u8 ConnectionMode; /**< Single, Stacked and Parallel mode */ + u8 BusWidth; /**< Bus width available on board */ + u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not */ +#if defined (XCLOCKING) + u32 RefClk; /**< Input clocks */ +#endif +} XQspiPsu_Config; + +/** + * The XQspiPsu driver instance data. The user is required to allocate a + * variable of this type for every QSPIPSU device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XQspiPsu_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ + + u8 *SendBufferPtr; /**< Buffer to send (state) */ + u8 *RecvBufferPtr; /**< Buffer to receive (state) */ + u64 RecvBuffer; /**< Buffer Address to receive (state) */ + u8 *GenFifoBufferPtr; /**< Gen FIFO entries */ + s32 TxBytes; /**< Number of bytes to transfer (state) */ + s32 RxBytes; /**< Number of bytes left to transfer(state) */ + s32 GenFifoEntries; /**< Number of Gen FIFO entries remaining */ +#ifdef __rtems__ + volatile +#endif + u32 IsBusy; /**< A transfer is in progress (state) */ + u32 ReadMode; /**< DMA or IO mode */ + u32 GenFifoCS; /**< Gen FIFO chip selection */ + u32 GenFifoBus; /**< Gen FIFO bus */ + s32 NumMsg; /**< Number of messages */ + s32 MsgCnt; /**< Message Count */ + s32 IsUnaligned; /**< Unaligned information */ + u8 IsManualstart; /**< Manual start information */ + XQspiPsu_Msg *Msg; /**< Message */ + XQspiPsu_StatusHandler StatusHandler; /**< Status Handler */ + void *StatusRef; /**< Callback reference for status handler */ +} XQspiPsu; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/** + * Definitions for Intel, STM, Winbond and Spansion Serial Flash Device + * geometry. + */ +#define BYTES256_PER_PAGE 256U /**< 256 Bytes per Page */ +#define BYTES512_PER_PAGE 512U /**< 512 Bytes per Page */ +#define BYTES1024_PER_PAGE 1024U /**< 1024 Bytes per Page */ +#define PAGES16_PER_SECTOR 16U /**< 16 Pages per Sector */ +#define PAGES128_PER_SECTOR 128U /**< 128 Pages per Sector */ +#define PAGES256_PER_SECTOR 256U /**< 256 Pages per Sector */ +#define PAGES512_PER_SECTOR 512U /**< 512 Pages per Sector */ +#define PAGES1024_PER_SECTOR 1024U /**< 1024 Pages per Sector */ +#define NUM_OF_SECTORS2 2U /**< 2 Sectors */ +#define NUM_OF_SECTORS4 4U /**< 4 Sectors */ +#define NUM_OF_SECTORS8 8U /**< 8 Sector */ +#define NUM_OF_SECTORS16 16U /**< 16 Sectors */ +#define NUM_OF_SECTORS32 32U /**< 32 Sectors */ +#define NUM_OF_SECTORS64 64U /**< 64 Sectors */ +#define NUM_OF_SECTORS128 128U /**< 128 Sectors */ +#define NUM_OF_SECTORS256 256U /**< 256 Sectors */ +#define NUM_OF_SECTORS512 512U /**< 512 Sectors */ +#define NUM_OF_SECTORS1024 1024U /**< 1024 Sectors */ +#define NUM_OF_SECTORS2048 2048U /**< 2048 Sectors */ +#define NUM_OF_SECTORS4096 4096U /**< 4096 Sectors */ +#define NUM_OF_SECTORS8192 8192U /**< 8192 Sectors */ +#define SECTOR_SIZE_64K 0X10000U /**< 64K Sector */ +#define SECTOR_SIZE_128K 0X20000U /**< 128K Sector */ +#define SECTOR_SIZE_256K 0X40000U /**< 256K Sector */ +#define SECTOR_SIZE_512K 0X80000U /**< 512K Sector */ + + +#define XQSPIPSU_READMODE_DMA 0x0U /**< DMA read mode */ +#define XQSPIPSU_READMODE_IO 0x1U /**< IO read mode */ + +#define XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1U /**< Select lower flash */ +#define XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2U /**< Select upper flash */ +#define XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3U /**< Select both flash */ + +#define XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1U /**< Select lower bus flash */ +#define XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2U /**< Select upper bus flash */ +#define XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3U /**< Select both bus flash */ + +#define XQSPIPSU_SELECT_MODE_SPI 0x1U /**< Select SPI mode */ +#define XQSPIPSU_SELECT_MODE_DUALSPI 0x2U /**< Select dual SPI mode */ +#define XQSPIPSU_SELECT_MODE_QUADSPI 0x4U /**< Select quad SPI mode */ + +#define XQSPIPSU_GENFIFO_CS_SETUP 0x05U /**< Chip select setup in GENFIO */ +#define XQSPIPSU_GENFIFO_CS_HOLD 0x04U /**< Chip select hold in GENFIFO */ + +#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2U /**< Clk Active low option */ +#define XQSPIPSU_CLK_PHASE_1_OPTION 0x4U /**< Clk phase 1 option */ +#define XQSPIPSU_MANUAL_START_OPTION 0x8U /**< Manual start option */ +#if !defined (versal) +#define XQSPIPSU_LQSPI_MODE_OPTION 0x20U /**< LQSPI mode option */ + +#define XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB 1U /**< LQSPI less Than 16 MB */ +#endif + +#define XQSPIPSU_GENFIFO_EXP_START 0x100U /**< Genfifo start */ + +#define XQSPIPSU_DMA_BYTES_MAX 0x10000000U /**< DMA bytes max */ + +#define XQSPIPSU_CLK_PRESCALE_2 0x00U /**< Clock prescale 2 */ +#define XQSPIPSU_CLK_PRESCALE_4 0x01U /**< Clock prescale 4 */ +#define XQSPIPSU_CLK_PRESCALE_8 0x02U /**< Clock prescale 8 */ +#define XQSPIPSU_CLK_PRESCALE_16 0x03U /**< Clock prescale 16 */ +#define XQSPIPSU_CLK_PRESCALE_32 0x04U /**< Clock prescale 32 */ +#define XQSPIPSU_CLK_PRESCALE_64 0x05U /**< Clock prescale 64 */ +#define XQSPIPSU_CLK_PRESCALE_128 0x06U /**< Clock prescale 128 */ +#define XQSPIPSU_CLK_PRESCALE_256 0x07U /**< Clock prescale 256 */ +#define XQSPIPSU_CR_PRESC_MAXIMUM 7U /**< Prescale max */ + +#define XQSPIPSU_CONNECTION_MODE_SINGLE 0U /**< Single mode connection */ +#define XQSPIPSU_CONNECTION_MODE_STACKED 1U /**< Stacked mode connection */ +#define XQSPIPSU_CONNECTION_MODE_PARALLEL 2U /**< Parallel mode connection */ + +/*QSPI Frequencies*/ +#define XQSPIPSU_FREQ_37_5MHZ 37500000U /**< Frequency 375 Mhz */ +#define XQSPIPSU_FREQ_40MHZ 40000000U /**< Frequency 40 Mhz */ +#define XQSPIPSU_FREQ_100MHZ 100000000U /**< Frequency 100 Mhz */ +#define XQSPIPSU_FREQ_150MHZ 150000000U /**< Frequency 150 Mhz */ + +/* Add more flags as required */ +#define XQSPIPSU_MSG_FLAG_STRIPE 0x1U /**< Stripe Msg flag */ +#define XQSPIPSU_MSG_FLAG_RX 0x2U /**< Rx Msg flag */ +#define XQSPIPSU_MSG_FLAG_TX 0x4U /**< Tx Msg flag */ +#define XQSPIPSU_MSG_FLAG_POLL 0x8U /**< POLL Msg flag */ + +#define XQSPIPSU_RXADDR_OVER_32BIT 0x100000000U /**< Rx address over 32 bit */ + +#define XQSPIPSU_SET_WP 1 /**< GQSPI configuration to toggle WP of flash */ + +/** + * select QSPI controller + */ +#define XQspiPsu_Select(InstancePtr, Mask) \ + XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPSU_SEL_OFFSET, (Mask)) + +/** + * Enable QSPI Controller + */ +#define XQspiPsu_Enable(InstancePtr) \ + XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK) + +/** + * Disable QSPI controller */ +#define XQspiPsu_Disable(InstancePtr) \ + XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPSU_EN_OFFSET, 0x0U) + +/** + * Read Configuration register of LQSPI Controller + */ +#if !defined (versal) +#define XQspiPsu_GetLqspiConfigReg(InstancePtr) \ + XQspiPsu_In32((XQSPIPS_BASEADDR) + \ + XQSPIPSU_LQSPI_CR_OFFSET) +#endif + +/*****************************************************************************/ +/** + * + * This function enables the manual start option + * + * @param InstancePtr is a pointer to the XQspiPsu instance. + * + * @return None + * + * @note None. + * + ******************************************************************************/ +static inline void XQspiPsu_ManualStartEnable(XQspiPsu *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); +#ifdef DEBUG + xil_printf("\nXQspiPsu_ManualStartEnable\r\n"); +#endif + + if (InstancePtr->IsManualstart == (u8)TRUE) { +#ifdef DEBUG + xil_printf("\nManual Start\r\n"); +#endif + XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET, + XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET) | + XQSPIPSU_CFG_START_GEN_FIFO_MASK); + } +} +/*****************************************************************************/ +/** + * + * This function writes the GENFIFO entry to assert CS. + * + * @param InstancePtr is a pointer to the XQspiPsu instance. + * + * @return None + * + * @note None. + * + ******************************************************************************/ +static inline void XQspiPsu_GenFifoEntryCSAssert(const XQspiPsu *InstancePtr) +{ + u32 GenFifoEntry; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); +#ifdef DEBUG + xil_printf("\nXQspiPsu_GenFifoEntryCSAssert\r\n"); +#endif + + GenFifoEntry = 0x0U; + GenFifoEntry |= (XQSPIPSU_GENFIFO_MODE_SPI | InstancePtr->GenFifoCS | + InstancePtr->GenFifoBus | XQSPIPSU_GENFIFO_CS_SETUP); +#ifdef DEBUG + xil_printf("\nFifoEntry=%08x\r\n", GenFifoEntry); +#endif + XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, + XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry); +} + +/*****************************************************************************/ +/** + * + * This function writes the GENFIFO entry to de-assert CS. + * + * @param InstancePtr is a pointer to the XQspiPsu instance. + * + * @return None + * + * @note None. + * + ******************************************************************************/ +static inline void XQspiPsu_GenFifoEntryCSDeAssert(const XQspiPsu *InstancePtr) +{ + u32 GenFifoEntry; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); +#ifdef DEBUG + xil_printf("\nXQspiPsu_GenFifoEntryCSDeAssert\r\n"); +#endif + + GenFifoEntry = 0x0U; + GenFifoEntry |= (XQSPIPSU_GENFIFO_MODE_SPI | InstancePtr->GenFifoBus | + XQSPIPSU_GENFIFO_CS_HOLD); +#ifdef DEBUG + xil_printf("\nFifoEntry=%08x\r\n", GenFifoEntry); +#endif + XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, + XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry); +} + +/*****************************************************************************/ +/** + * + * This is a stub for the status callback. The stub is here in case the upper + * layers forget to set the handler. + * + * @param CallBackRef is a pointer to the upper layer callback reference + * @param StatusEvent is the event that just occurred. + * @param ByteCount is the number of bytes transferred up until the event + * occurred. + * + * @return None. + * + * @note None. + * + ******************************************************************************/ +static inline void StubStatusHandler(const void *CallBackRef, u32 StatusEvent, + u32 ByteCount) +{ + (const void) CallBackRef; + (void) StatusEvent; + (void) ByteCount; + + Xil_AssertVoidAlways(); +} +/************************** Function Prototypes ******************************/ + +/* Initialization and reset */ +XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId); +s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, + const XQspiPsu_Config *ConfigPtr, + UINTPTR EffectiveAddr); +void XQspiPsu_Reset(XQspiPsu *InstancePtr); +void XQspiPsu_Abort(XQspiPsu *InstancePtr); + +/* Transfer functions and handlers */ +s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + u32 NumMsg); +s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + u32 NumMsg); +s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr); +void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef, + XQspiPsu_StatusHandler FuncPointer); + +/* Non blocking Transfer functions */ +s32 XQspiPsu_StartDmaTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + u32 NumMsg); +s32 XQspiPsu_CheckDmaDone(XQspiPsu *InstancePtr); + +/* Configuration functions */ +s32 XQspiPsu_SetClkPrescaler(const XQspiPsu *InstancePtr, u8 Prescaler); +void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus); +s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options); +s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options); +u32 XQspiPsu_GetOptions(const XQspiPsu *InstancePtr); +s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode); +void XQspiPsu_SetWP(const XQspiPsu *InstancePtr, u8 Value); +void XQspiPsu_WriteProtectToggle(const XQspiPsu *InstancePtr, u32 Toggle); +void XQspiPsu_Idle(const XQspiPsu *InstancePtr); + +/************************** Variable Prototypes ******************************/ + +/** + * This table contains configuration information for each QSPIPSU device + * in the system. + */ +#ifndef __rtems__ +extern XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES]; +#endif /* __rtems__ */ + +#ifdef __cplusplus +} +#endif + + +#endif /* XQSPIPSU_H_ */ +/** @} */ diff --git a/bsps/include/dev/spi/xqspipsu_control.h b/bsps/include/dev/spi/xqspipsu_control.h new file mode 100644 index 0000000000..76b0a8ce7c --- /dev/null +++ b/bsps/include/dev/spi/xqspipsu_control.h @@ -0,0 +1,102 @@ +/****************************************************************************** +* Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/*****************************************************************************/ +/** + * + * @file xqspipsu_control.h + * @addtogroup Overview + * @{ + * + * This is the header file for the implementation of QSPIPSU driver. + * Generic QSPI interface allows for communication to any QSPI slave device. + * GQSPI contains a GENFIFO into which the bus transfers required are to be + * pushed with appropriate configuration. The controller provides TX and RX + * FIFO's and a DMA to be used for RX transfers. The controller executes each + * GENFIFO entry noting the configuration and places data on the bus as required + * + * + * <pre> + * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- --- -------- -----------------------------------------------. + * 1.11 akm 03/09/20 First release + * 1.13 akm 01/04/21 Fix MISRA-C violations. + * 1.15 akm 03/03/22 Enable tapdelay settings for applications on + * Microblaze platform. + * + * </pre> + * + ******************************************************************************/ + +/** @cond INTERNAL */ +#ifndef XQSPIPSU_CONTROL_H_ /**< prevent circular inclusions */ +#define XQSPIPSU_CONTROL_H_ /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xqspipsu.h" + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__) +#define TAPDLY_BYPASS_VALVE_40MHZ 0x01U +#define TAPDLY_BYPASS_VALVE_100MHZ 0x01U +#define USE_DLY_LPBK 0x01U +#define USE_DATA_DLY_ADJ 0x01U +#define DATA_DLY_ADJ_DLY 0X02U +#define LPBK_DLY_ADJ_DLY0 0X02U +#define LPBK_DLY_ADJ_DLY1 0X02U +#endif + +#ifdef __MICROBLAZE__ +#define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */ +#endif +/************************** Function Prototypes ******************************/ +void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg); +u32 XQspiPsu_SetIOMode(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg); +void XQspiPsu_IORead(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + u32 StatusReg); +void XQspiPsu_PollDataConfig(XQspiPsu *InstancePtr, XQspiPsu_Msg *FlashMsg); +void XQspiPsu_TXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg); +void XQspiPsu_SetupRxDma(const XQspiPsu *InstancePtr, + XQspiPsu_Msg *Msg); +void XQspiPsu_Setup64BRxDma(const XQspiPsu *InstancePtr, + XQspiPsu_Msg *Msg); +void XQspiPsu_RXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg); +void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + u32 *GenFifoEntry); +void XQspiPsu_GenFifoEntryDataLen(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, + u32 *GenFifoEntry); +u32 XQspiPsu_CreatePollDataConfig(const XQspiPsu *InstancePtr, + const XQspiPsu_Msg *FlashMsg); +void XQspiPsu_PollDataHandler(XQspiPsu *InstancePtr, u32 StatusReg); +u32 XQspiPsu_SelectSpiMode(u8 SpiMode); +void XQspiPsu_SetDefaultConfig(XQspiPsu *InstancePtr); +void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, u32 Size); +void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, s32 Size); + +#if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__) +s32 XQspipsu_Set_TapDelay(const XQspiPsu *InstancePtr, u32 TapdelayBypass, + u32 LPBKDelay, u32 Datadelay); +s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu *InstancePtr, u8 Prescaler); +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* XQSPIPSU_CONTROL_H_ */ +/** @endcond */ +/** @} */ diff --git a/bsps/include/dev/spi/xqspipsu_flash_config.h b/bsps/include/dev/spi/xqspipsu_flash_config.h new file mode 100644 index 0000000000..0b04fffc28 --- /dev/null +++ b/bsps/include/dev/spi/xqspipsu_flash_config.h @@ -0,0 +1,357 @@ +/****************************************************************************** +* Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xqspipsu_flash_config.h +* +* +* This file contains flash configuration table and flash related defines. +* This file should be included in the example files and compiled along with +* the examples (*.c). +* +* @note +* +* None. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- ----------------------------------------------- +* 1.12 akm 07/07/20 First release +* 1.12 akm 07/07/20 Add support for Macronix flash(MX66U2G45G, MX66L2G45G) +* and ISSI flash(IS25LP01G, IS25WP01G) parts. +* 1.13 akm 12/10/20 Set Read command as per the qspi bus width. +* 1.14 akm 07/16/21 Enable Quad Mode for Winbond flashes. +* 1.15 akm 11/19/21 Fix read/write failures on Spansion flash parts. +* +*</pre> +* + ******************************************************************************/ + +#ifndef XQSPIPSU_FLASH_CONFIG_H_ /* prevent circular inclusions */ +#define XQSPIPSU_FLASH_CONFIG_H_ /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xparameters.h" /* SDK generated parameters */ +#include "xqspipsu.h" /* QSPIPSU device driver */ + +/************************** Constant Definitions *****************************/ + +/* + * The following constants define the commands which may be sent to the Flash + * device. + */ +#define WRITE_STATUS_CMD 0x01 +#define WRITE_CMD 0x02 +#define READ_CMD 0x03 +#define WRITE_DISABLE_CMD 0x04 +#define READ_STATUS_CMD 0x05 +#define WRITE_ENABLE_CMD 0x06 +#define VOLATILE_WRITE_ENABLE_CMD 0x50 +#define QUAD_MODE_ENABLE_BIT 0x06 +#define FAST_READ_CMD 0x0B +#define DUAL_READ_CMD 0x3B +#define QUAD_READ_CMD 0x6B +#define BULK_ERASE_CMD 0xC7 +#define SEC_ERASE_CMD 0xD8 +#define READ_ID 0x9F +#define READ_SFDP 0x5A +#define READ_CONFIG_CMD 0x35 +#define WRITE_CONFIG_CMD 0x01 +#define ENTER_4B_ADDR_MODE 0xB7 +#define EXIT_4B_ADDR_MODE 0xE9 +#define EXIT_4B_ADDR_MODE_ISSI 0x29 +/* 4-byte address opcodes */ +#define READ_CMD_4B 0x13 +#define FAST_READ_CMD_4B 0x0C +#define DUAL_READ_CMD_4B 0x3C +#define QUAD_READ_CMD_4B 0x6C +#define WRITE_CMD_4B 0x12 +#define SEC_ERASE_CMD_4B 0xDC + +#define BANK_REG_RD 0x16 +#define BANK_REG_WR 0x17 +#define READ_ECCSR 0x18 +/* Bank register is called Extended Address Register in Micron */ +#define EXTADD_REG_RD 0xC8 +#define EXTADD_REG_WR 0xC5 +#define DIE_ERASE_CMD 0xC4 +#define READ_FLAG_STATUS_CMD 0x70 + +#define WRITE_STATUS_REG_2_CMD 0x31 +#define READ_STATUS_REG_2_CMD 0x35 +#define WB_QUAD_MODE_ENABLE_BIT 0x01 + +/* + * The following constants define the offsets within a FlashBuffer data + * type for each kind of data. Note that the read data offset is not the + * same as the write data because the QSPIPSU driver is designed to allow full + * duplex transfers such that the number of bytes received is the number + * sent and received. + */ +#define COMMAND_OFFSET 0 /* Flash instruction */ +#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */ +#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */ +#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */ +#define ADDRESS_4_OFFSET 4 /* LSB byte of address to read or write + * when 4 byte address + */ +#define DATA_OFFSET 5 /* Start of Data for Read/Write */ +#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad + * reads + */ +#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and + * quad reads + */ +#define DUMMY_CLOCKS 8 /* Number of dummy bytes for fast, dual and + * quad reads + */ +#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */ +#define BULK_ERASE_SIZE 1 /* Bulk Erase command size */ +#define SEC_ERASE_SIZE 4 /* Sector Erase command + Sector address */ +#define BANK_SEL_SIZE 2 /* BRWR or EARWR command + 1 byte bank + * value + */ +#define RD_CFG_SIZE 2 /* 1 byte Configuration register + RD CFG + * command + */ +#define WR_CFG_SIZE 3 /* WRR command + 1 byte each Status and + * Config Reg + */ +#define DIE_ERASE_SIZE 4 /* Die Erase command + Die address */ + +/* + * The following constants specify the extra bytes which are sent to the + * Flash on the QSPIPSu interface, that are not data, but control information + * which includes the command and address + */ +#define OVERHEAD_SIZE 4 + +/* + * Base address of Flash1 + */ +#define FLASH1BASE 0x0000000 + +/* + * Sixteen MB + */ +#define SIXTEENMB 0x1000000 + + +/* + * Mask for quad enable bit in Flash configuration register + */ +#define FLASH_QUAD_EN_MASK 0x02 + +#define FLASH_SRWD_MASK 0x80 + +/* + * Bank mask + */ +#define BANKMASK 0xF000000 + +/* + * Bus width + */ +#define BUSWIDTH_SINGLE 0 +#define BUSWIDTH_DOUBLE 1 + +/* + * Identification of Flash + * Micron: + * Byte 0 is Manufacturer ID; + * Byte 1 is first byte of Device ID - 0xBB or 0xBA + * Byte 2 is second byte of Device ID describes flash size: + * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20 + * Spansion: + * Byte 0 is Manufacturer ID; + * Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02 + * Byte 2 is second byte of Device ID describes flash size: + * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20 + */ +#define MICRON_ID_BYTE0 0x20 +#define SPANSION_ID_BYTE0 0x01 +#define WINBOND_ID_BYTE0 0xEF +#define MACRONIX_ID_BYTE0 0xC2 +#define ISSI_ID_BYTE0 0x9D + +/**************************** Type Definitions *******************************/ + +typedef struct{ + u32 jedec_id; /* JEDEC ID */ + + u32 SectSize; /* Individual sector size or combined sector + * size in case of parallel config + */ + u32 NumSect; /* Total no. of sectors in one/two + * flash devices + */ + u32 PageSize; /* Individual page size or + * combined page size in case of parallel + * config + */ + u32 NumPage; /* Total no. of pages in one/two flash + * devices + */ + u32 FlashDeviceSize; /* This is the size of one flash device + * NOT the combination of both devices, + * if present + */ + u32 SectMask; /* Mask to get sector start address */ + u8 NumDie; /* No. of die forming a single flash */ +} FlashInfo; + +/************************** Variable Definitions *****************************/ +FlashInfo Flash_Config_Table[] = { + /* Spansion */ + /*s25fl064l*/ + {0x016017, SECTOR_SIZE_64K, NUM_OF_SECTORS128, BYTES256_PER_PAGE, + 0x8000, 0x800000, 0xFFFF0000, 1}, + /*s25fl128l*/ + {0x016018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*s25fl256l*/ + {0x016019, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE, + 0x20000, 0x2000000, 0xFFFF0000, 1}, + /*s25fl512s*/ + {0x010220, SECTOR_SIZE_256K, NUM_OF_SECTORS256, BYTES512_PER_PAGE, + 0x20000, 0x4000000, 0xFFFC0000, 1}, + /* Spansion 1Gbit is handled as 512Mbit stacked */ + /* Micron */ + /*n25q128a11*/ + {0x20bb18, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*n25q128a13*/ + {0x20ba18, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*n25q256ax1*/ + {0x20bb19, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE, + 0x20000, 0x2000000, 0xFFFF0000, 1}, + /*n25q256a*/ + {0x20ba19, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE, + 0x20000, 0x2000000, 0xFFFF0000, 1}, + /*mt25qu512a*/ + {0x20bb20, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE, + 0x40000, 0x4000000, 0xFFFF0000, 2}, + /*n25q512ax3*/ + {0x20ba20, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE, + 0x40000, 0x4000000, 0xFFFF0000, 2}, + /*n25q00a*/ + {0x20bb21, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 4}, + /*n25q00*/ + {0x20ba21, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 4}, + /*mt25qu02g*/ + {0x20bb22, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE, + 0x100000, 0x10000000, 0xFFFF0000, 4}, + /*mt25ql02g*/ + {0x20ba22, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE, + 0x100000, 0x10000000, 0xFFFF0000, 4}, + /* Winbond */ + /*w25q128fw*/ + {0xef6018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*w25q128jv*/ + {0xef7018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*w25h02jv*/ + {0xef9022, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE, + 0x100000, 0x10000000, 0xFFFF0000, 4}, + /* Macronix */ + /*mx66l1g45g*/ + {0xc2201b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 4}, + /*mx66l1g55g*/ + {0xc2261b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 4}, + /*mx66u1g45g*/ + {0xc2253b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 4}, + /*mx66l2g45g*/ + {0xc2201c, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE, + 0x100000, 0x10000000, 0xFFFF0000, 1}, + /*mx66u2g45g*/ + {0xc2253c, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE, + 0x100000, 0x10000000, 0xFFFF0000, 1}, + /* ISSI */ + /*is25wp080d*/ + {0x9d7014, SECTOR_SIZE_64K, NUM_OF_SECTORS16, BYTES256_PER_PAGE, + 0x1000, 0x100000, 0xFFFF0000, 1}, + /*is25lp080d*/ + {0x9d6014, SECTOR_SIZE_64K, NUM_OF_SECTORS16, BYTES256_PER_PAGE, + 0x1000, 0x100000, 0xFFFF0000, 1}, + /*is25wp016d*/ + {0x9d7015, SECTOR_SIZE_64K, NUM_OF_SECTORS32, BYTES256_PER_PAGE, + 0x2000, 0x200000, 0xFFFF0000, 1}, + /*is25lp016d*/ + {0x9d6015, SECTOR_SIZE_64K, NUM_OF_SECTORS32, BYTES256_PER_PAGE, + 0x2000, 0x200000, 0xFFFF0000, 1}, + /*is25wp032*/ + {0x9d7016, SECTOR_SIZE_64K, NUM_OF_SECTORS64, BYTES256_PER_PAGE, + 0x4000, 0x400000, 0xFFFF0000, 1}, + /*is25lp032*/ + {0x9d6016, SECTOR_SIZE_64K, NUM_OF_SECTORS64, BYTES256_PER_PAGE, + 0x4000, 0x400000, 0xFFFF0000, 1}, + /*is25wp064*/ + {0x9d7017, SECTOR_SIZE_64K, NUM_OF_SECTORS128, BYTES256_PER_PAGE, + 0x8000, 0x800000, 0xFFFF0000, 1}, + /*is25lp064*/ + {0x9d6017, SECTOR_SIZE_64K, NUM_OF_SECTORS128, BYTES256_PER_PAGE, + 0x8000, 0x800000, 0xFFFF0000, 1}, + /*is25wp128*/ + {0x9d7018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*is25lp128*/ + {0x9d6018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE, + 0x10000, 0x1000000, 0xFFFF0000, 1}, + /*is25lp256d*/ + {0x9d6019, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE, + 0x20000, 0x2000000, 0xFFFF0000, 1}, + /*is25wp256d*/ + {0x9d7019, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE, + 0x20000, 0x2000000, 0xFFFF0000, 1}, + /*is25lp512m*/ + {0x9d601a, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE, + 0x40000, 0x4000000, 0xFFFF0000, 2}, + /*is25wp512m*/ + {0x9d701a, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE, + 0x40000, 0x4000000, 0xFFFF0000, 2}, + /*is25lp01g*/ + {0x9d601b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 1}, + /*is25wp01g*/ + {0x9d701b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE, + 0x80000, 0x8000000, 0xFFFF0000, 1} +}; + +static INLINE u32 CalculateFCTIndex(u32 ReadId, u32 *FCTIndex) +{ + u32 Index; + + for (Index = 0; Index < sizeof(Flash_Config_Table)/sizeof(Flash_Config_Table[0]); + Index++) { + if (ReadId == Flash_Config_Table[Index].jedec_id) { + *FCTIndex = Index; + return XST_SUCCESS; + } + } + + return XST_FAILURE; +} + +#ifdef __cplusplus +} +#endif + +#endif /* XQSPIPSU_FLASH_CONFIG_H_ */ +/** @} */ diff --git a/bsps/include/dev/spi/xqspipsu_hw.h b/bsps/include/dev/spi/xqspipsu_hw.h new file mode 100644 index 0000000000..a798f9bb89 --- /dev/null +++ b/bsps/include/dev/spi/xqspipsu_hw.h @@ -0,0 +1,1006 @@ +/****************************************************************************** +* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xqspipsu_hw.h +* @addtogroup Overview +* @{ +* +* This file contains low level access functions using the base address +* directly without an instance. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- -----------------------------------------------. +* 1.0 hk 08/21/14 First release +* hk 03/18/15 Add DMA status register masks required. +* sk 04/24/15 Modified the code according to MISRAC-2012. +* 1.2 nsk 07/01/16 Added LQSPI supported Masks +* rk 07/15/16 Added support for TapDelays at different frequencies. +* 1.7 tjs 03/14/18 Added support in EL1 NS mode. +* 1.9 tjs 04/17/18 Updated register addresses as per the latest revision +* of versal (CR#999610) +* 1.9 aru 01/17/19 Fixed the violations for MISRAC-2012 +* in safety mode .Done changes such as added U suffix +* 1.11 akm 11/07/19 Removed LQSPI register access in Versal. +* 1.15 akm 12/02/21 Fix Doxygen warnings. +* +* </pre> +* +******************************************************************************/ +#ifndef XQSPIPSU_HW_H /**< prevent circular inclusions */ +#define XQSPIPSU_HW_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ +/** + * @name Device Base Address + * Below macros gives QSPI, QSPIPSU base address. + * @{ + */ +/** + * QSPI Base Address + */ +#if defined (versal) +#define XQSPIPS_BASEADDR 0XF1030000U +#else +#define XQSPIPS_BASEADDR 0XFF0F0000U +#endif + +#if defined (versal) +#define XQSPIPSU_BASEADDR 0XF1030100U +#else +#define XQSPIPSU_BASEADDR 0xFF0F0100U +#endif +#define XQSPIPSU_OFFSET 0x100U +/** @} */ + +/** + * @name XQSPIPS Enable Register information + * QSPIPSU Enable Register + * @{ + */ +/** + * Register: XQSPIPS_EN_REG + */ +#define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U ) +#define XQSPIPS_EN_SHIFT 0U +#define XQSPIPS_EN_WIDTH 1U +#define XQSPIPS_EN_MASK 0X00000001U +/** @} */ + +/** + * @name XQSPIPSU configuration Register information + * This register contains bits for configuring GQSPI controller + * @{ + */ +/** + * Register: XQSPIPSU_CFG + */ +#define XQSPIPSU_CFG_OFFSET 0X00000000U + +#define XQSPIPSU_CFG_MODE_EN_SHIFT 30U +#define XQSPIPSU_CFG_MODE_EN_WIDTH 2U +#define XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000U +#define XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000U + +#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT 29U +#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH 1U +#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000U + +#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT 28U +#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH 1U +#define XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000U + +#define XQSPIPSU_CFG_ENDIAN_SHIFT 26U +#define XQSPIPSU_CFG_ENDIAN_WIDTH 1U +#define XQSPIPSU_CFG_ENDIAN_MASK 0X04000000U + +#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT 20U +#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH 1U +#define XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000U + +#define XQSPIPSU_CFG_WP_HOLD_SHIFT 19U +#define XQSPIPSU_CFG_WP_HOLD_WIDTH 1U +#define XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000U + +#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT 3U +#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH 3U +#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038U + +#define XQSPIPSU_CFG_CLK_PHA_SHIFT 2U +#define XQSPIPSU_CFG_CLK_PHA_WIDTH 1U +#define XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004U + +#define XQSPIPSU_CFG_CLK_POL_SHIFT 1U +#define XQSPIPSU_CFG_CLK_POL_WIDTH 1U +#define XQSPIPSU_CFG_CLK_POL_MASK 0X00000002U +/** @} */ + +/** + * @name XQSPIPSU LQSPI Register information + * This register contains bits for configuring LQSPI + * @{ + */ +/** + * Register: XQSPIPSU_LQSPI + */ +#if !defined (versal) +#define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U +#define XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000U /**< LQSPI mode enable */ +#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000U /**< Both memories or one */ +#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK 0x20000000U /**< Separate memory bus */ +#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK 0x10000000U /**< Upper memory page */ +#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK 0x01000000U /**< Upper memory page */ +#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK 0x02000000U /**< Enable mode bits */ +#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK 0x01000000U /**< Mode on */ +#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK 0x00FF0000U /**< Mode value for dual I/O + or quad I/O */ +#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FFU /**< Read instr code */ +#define XQSPIPS_LQSPI_CR_RST_STATE 0x80000003U /**< Default LQSPI CR value */ +#define XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013U /**< Default 4 Byte LQSPI CR value */ +#define XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1U /**< Default LQSPI CFG value */ +#endif +/** @} */ + +/** + * @name XQSPIPSU Interrupt Status Register information + * QSPIPSU Interrupt Status Register + * @{ + */ +/** + * Register: XQSPIPSU_ISR + */ +#define XQSPIPSU_ISR_OFFSET 0X00000004U + +#define XQSPIPSU_ISR_RXEMPTY_SHIFT 11U +#define XQSPIPSU_ISR_RXEMPTY_WIDTH 1U +#define XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800U + +#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT 10U +#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH 1U +#define XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400U + +#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT 9U +#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH 1U +#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200U + +#define XQSPIPSU_ISR_TXEMPTY_SHIFT 8U +#define XQSPIPSU_ISR_TXEMPTY_WIDTH 1U +#define XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100U + +#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT 7U +#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH 1U +#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080U + +#define XQSPIPSU_ISR_RXFULL_SHIFT 5U +#define XQSPIPSU_ISR_RXFULL_WIDTH 1U +#define XQSPIPSU_ISR_RXFULL_MASK 0X00000020U + +#define XQSPIPSU_ISR_RXNEMPTY_SHIFT 4U +#define XQSPIPSU_ISR_RXNEMPTY_WIDTH 1U +#define XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010U + +#define XQSPIPSU_ISR_TXFULL_SHIFT 3U +#define XQSPIPSU_ISR_TXFULL_WIDTH 1U +#define XQSPIPSU_ISR_TXFULL_MASK 0X00000008U + +#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT 2U +#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH 1U +#define XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004U + +#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT 1U +#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH 1U +#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002U + +#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U +/** @} */ + +/** + * @name XQSPIPSU Interrupt Enable Register information + * This register bits for enabling interrupts + * @{ + */ +/** + * Register: XQSPIPSU_IER + */ +#define XQSPIPSU_IER_OFFSET 0X00000008U + +#define XQSPIPSU_IER_RXEMPTY_SHIFT 11U +#define XQSPIPSU_IER_RXEMPTY_WIDTH 1U +#define XQSPIPSU_IER_RXEMPTY_MASK 0X00000800U + +#define XQSPIPSU_IER_GENFIFOFULL_SHIFT 10U +#define XQSPIPSU_IER_GENFIFOFULL_WIDTH 1U +#define XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400U + +#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT 9U +#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH 1U +#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200U + +#define XQSPIPSU_IER_TXEMPTY_SHIFT 8U +#define XQSPIPSU_IER_TXEMPTY_WIDTH 1U +#define XQSPIPSU_IER_TXEMPTY_MASK 0X00000100U + +#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT 7U +#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH 1U +#define XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080U + +#define XQSPIPSU_IER_RXFULL_SHIFT 5U +#define XQSPIPSU_IER_RXFULL_WIDTH 1U +#define XQSPIPSU_IER_RXFULL_MASK 0X00000020U + +#define XQSPIPSU_IER_RXNEMPTY_SHIFT 4U +#define XQSPIPSU_IER_RXNEMPTY_WIDTH 1U +#define XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010U + +#define XQSPIPSU_IER_TXFULL_SHIFT 3U +#define XQSPIPSU_IER_TXFULL_WIDTH 1U +#define XQSPIPSU_IER_TXFULL_MASK 0X00000008U + +#define XQSPIPSU_IER_TXNOT_FULL_SHIFT 2U +#define XQSPIPSU_IER_TXNOT_FULL_WIDTH 1U +#define XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004U + +#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT 1U +#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH 1U +#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002U +/** @} */ + +/** + * @name XQSPIPSU Interrupt Disable Register information + * This register bits for disabling interrupts + * @{ + */ +/** + * Register: XQSPIPSU_IDR + */ +#define XQSPIPSU_IDR_OFFSET 0X0000000CU + +#define XQSPIPSU_IDR_RXEMPTY_SHIFT 11U +#define XQSPIPSU_IDR_RXEMPTY_WIDTH 1U +#define XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800U + +#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT 10U +#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH 1U +#define XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400U + +#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT 9U +#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH 1U +#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200U + +#define XQSPIPSU_IDR_TXEMPTY_SHIFT 8U +#define XQSPIPSU_IDR_TXEMPTY_WIDTH 1U +#define XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100U + +#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT 7U +#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH 1U +#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080U + +#define XQSPIPSU_IDR_RXFULL_SHIFT 5U +#define XQSPIPSU_IDR_RXFULL_WIDTH 1U +#define XQSPIPSU_IDR_RXFULL_MASK 0X00000020U + +#define XQSPIPSU_IDR_RXNEMPTY_SHIFT 4U +#define XQSPIPSU_IDR_RXNEMPTY_WIDTH 1U +#define XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010U + +#define XQSPIPSU_IDR_TXFULL_SHIFT 3U +#define XQSPIPSU_IDR_TXFULL_WIDTH 1U +#define XQSPIPSU_IDR_TXFULL_MASK 0X00000008U + +#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT 2U +#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH 1U +#define XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004U + +#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT 1U +#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH 1U +#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002U + +#define XQSPIPSU_IDR_ALL_MASK 0X0FBEU +/** @} */ + +/** + * @name XQSPIPSU Interrupt Mask Register information + * This register bits for masking interrupts + * @{ + */ +/** + * Register: XQSPIPSU_IMR + */ +#define XQSPIPSU_IMR_OFFSET 0X00000010U + +#define XQSPIPSU_IMR_RXEMPTY_SHIFT 11U +#define XQSPIPSU_IMR_RXEMPTY_WIDTH 1U +#define XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800U + +#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT 10U +#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH 1U +#define XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400U + +#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT 9U +#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH 1U +#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200U + +#define XQSPIPSU_IMR_TXEMPTY_SHIFT 8U +#define XQSPIPSU_IMR_TXEMPTY_WIDTH 1U +#define XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100U + +#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT 7U +#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH 1U +#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080U + +#define XQSPIPSU_IMR_RXFULL_SHIFT 5U +#define XQSPIPSU_IMR_RXFULL_WIDTH 1U +#define XQSPIPSU_IMR_RXFULL_MASK 0X00000020U + +#define XQSPIPSU_IMR_RXNEMPTY_SHIFT 4U +#define XQSPIPSU_IMR_RXNEMPTY_WIDTH 1U +#define XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010U + +#define XQSPIPSU_IMR_TXFULL_SHIFT 3U +#define XQSPIPSU_IMR_TXFULL_WIDTH 1U +#define XQSPIPSU_IMR_TXFULL_MASK 0X00000008U + +#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT 2U +#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH 1U +#define XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004U + +#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT 1U +#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH 1U +#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002U +/** @} */ + +/** + * @name XQSPIPSU Enable Register information + * This register bits for enabling QSPI controller + * @{ + */ +/** + * Register: XQSPIPSU_EN_REG + */ +#define XQSPIPSU_EN_OFFSET 0X00000014U + +#define XQSPIPSU_EN_SHIFT 0U +#define XQSPIPSU_EN_WIDTH 1U +#define XQSPIPSU_EN_MASK 0X00000001U +/** @} */ + +/** + * @name XQSPIPSU TX Data Register information + * This register bits for configuring TXFIFO + * @{ + */ +/** + * Register: XQSPIPSU_TXD + */ +#define XQSPIPSU_TXD_OFFSET 0X0000001CU + +#define XQSPIPSU_TXD_SHIFT 0U +#define XQSPIPSU_TXD_WIDTH 32U +#define XQSPIPSU_TXD_MASK 0XFFFFFFFFU + +#define XQSPIPSU_TXD_DEPTH 64 +/** @} */ + +/** + * @name XQSPIPSU RX Data Register information + * This register bits for configuring RXFIFO + * @{ + */ +/** + * Register: XQSPIPSU_RXD + */ +#define XQSPIPSU_RXD_OFFSET 0X00000020U + +#define XQSPIPSU_RXD_SHIFT 0U +#define XQSPIPSU_RXD_WIDTH 32U +#define XQSPIPSU_RXD_MASK 0XFFFFFFFFU +/** @} */ + +/** + * @name XQSPIPSU TX/RX Threshold Register information + * This register bits for configuring TX/RX Threshold + * @{ + */ +/** + * Register: XQSPIPSU_TX_THRESHOLD + */ +#define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U + +#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT 0U +#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH 6U +#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003FU +#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01U + +#define XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002CU + +#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT 0U +#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH 6U +#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003FU +#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01U + +#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U +/** @} */ + +/** + * @name XQSPIPSU GPIO Register information + * @{ + */ +/** + * Register: XQSPIPSU_GPIO + */ +#define XQSPIPSU_GPIO_OFFSET 0X00000030U + +#define XQSPIPSU_GPIO_WP_N_SHIFT 0U +#define XQSPIPSU_GPIO_WP_N_WIDTH 1U +#define XQSPIPSU_GPIO_WP_N_MASK 0X00000001U +/** @} */ + +/** + * @name XQSPIPSU Loopback Master Clock Delay Adjustment Register information + * This register contains bits for configuring loopback + * @{ + */ +/** + * Register: XQSPIPSU_LPBK_DLY_ADJ + */ +#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U + +#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT 5U +#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH 1U +#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020U + +#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT 3U +#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH 2U +#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018U + +#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT 0U +#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH 3U +#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007U +/** @} */ + +/** + * @name XQSPIPSU GEN_FIFO Register information + * This register contains bits for configuring GENFIFO + * @{ + */ +/** + * Register: XQSPIPSU_GEN_FIFO + */ +#define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U + +#define XQSPIPSU_GEN_FIFO_DATA_SHIFT 0U +#define XQSPIPSU_GEN_FIFO_DATA_WIDTH 20U +#define XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFFU +/** @} */ + +/** + * @name XQSPIPSU Select Register information + * This register contains bits for selection GQSPI/LQSPI controller + * @{ + */ +/** + * Register: XQSPIPSU_SEL + */ +#define XQSPIPSU_SEL_OFFSET 0X00000044U + +#define XQSPIPSU_SEL_SHIFT 0U +#define XQSPIPSU_SEL_WIDTH 1U +#if !defined (versal) +#define XQSPIPSU_SEL_LQSPI_MASK 0X0U +#endif +#define XQSPIPSU_SEL_GQSPI_MASK 0X00000001U +/** @} */ + +/** + * @name XQSPIPSU FIFO Control Register information + * This register contains bits for controlling TXFIFO and RXFIFO + * @{ + */ +/** + * Register: XQSPIPSU_FIFO_CTRL + */ +#define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU + +#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT 2U +#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH 1U +#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004U + +#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT 1U +#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH 1U +#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002U + +#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT 0U +#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH 1U +#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001U +/** @} */ + +/** + * @name XQSPIPSU GENFIFO Threshold Register information + * This register contains bits for configuring GENFIFO threshold + * @{ + */ +/** + * Register: XQSPIPSU_GF_THRESHOLD + */ +#define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U + +#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT 0U +#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH 5U +#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK 0X0000001FU +#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10U +/** @} */ + +/** + * @name XQSPIPSU Poll configuration Register information + * This register contains bits for configuring Poll feature + * @{ + */ +/** + * Register: XQSPIPSU_POLL_CFG + */ +#define XQSPIPSU_POLL_CFG_OFFSET 0X00000054U + +#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT 31U +#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH 1U +#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000U + +#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT 30U +#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH 1U +#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000U + +#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT 8U +#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH 8U +#define XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00U + +#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT 0U +#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH 8U +#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FFU + +#define XQSPIPSU_P_TO_OFFSET 0X00000058U + +#define XQSPIPSU_P_TO_VALUE_SHIFT 0U +#define XQSPIPSU_P_TO_VALUE_WIDTH 32U +#define XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFFU +/** @} */ + +/** + * @name XQSPIPSU Transfer Status Register information + * This register contains bits for transfer status + * @{ + */ +/** + * Register: XQSPIPSU_XFER_STS + */ +#define XQSPIPSU_XFER_STS_OFFSET 0X0000005CU + +#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT 0U +#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH 32U +#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFFU +/** @} */ + +/** + * @name XQSPIPSU GEN_FIFO Snapshot Register information + * This register contains bits for configuring GENFIFO + * @{ + */ +/** + * Register: XQSPIPSU_GF_SNAPSHOT + */ +#define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U + +#define XQSPIPSU_GF_SNAPSHOT_SHIFT 0U +#define XQSPIPSU_GF_SNAPSHOT_WIDTH 20U +#define XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFFU +/** @} */ + +/** + * @name XQSPIPSU Receive Data Copy Register information + * @{ + */ +/** + * Register: XQSPIPSU_RX_COPY + */ +#define XQSPIPSU_RX_COPY_OFFSET 0X00000064U + +#define XQSPIPSU_RX_COPY_UPPER_SHIFT 8U +#define XQSPIPSU_RX_COPY_UPPER_WIDTH 8U +#define XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00U + +#define XQSPIPSU_RX_COPY_LOWER_SHIFT 0U +#define XQSPIPSU_RX_COPY_LOWER_WIDTH 8U +#define XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FFU +/** @} */ + +/** + * @name XQSPIPSU Module Identification Register information + * @{ + */ +/** + * Register: XQSPIPSU_MOD_ID + */ +#define XQSPIPSU_MOD_ID_OFFSET 0X000000FCU + +#define XQSPIPSU_MOD_ID_SHIFT 0U +#define XQSPIPSU_MOD_ID_WIDTH 32U +#define XQSPIPSU_MOD_ID_MASK 0XFFFFFFFFU +/** @} */ + +/** + * @name XQSPIPSU DMA Transfer Register information + * This register contains bits for configuring DMA + * @{ + */ +/** + * Register: XQSPIPSU_QSPIDMA_DST_ADDR + */ +#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U + +#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH 30U +#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFCU + +#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704U + +#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH 27U +#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFCU + +#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708U + +#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT 13U +#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH 3U +#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000U + +#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5U +#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8U +#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0U + +#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT 1U +#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH 4U +#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001EU + +#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT 0U +#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001U + +#define XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070CU + +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT 25U +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH 7U +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24U +#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT 23U +#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22U +#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT 10U +#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH 12U +#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH 8U +#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FCU + +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT 0U +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001U + +#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x403FFA00U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT 7U +#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT 6U +#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT 5U +#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT 4U +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT 3U +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004U + +#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002U + +#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FCU +#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FEU + +#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT 7U +#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT 6U +#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT 5U +#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT 4U +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT 3U +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004U + +#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071CU + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT 7U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT 6U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT 5U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT 4U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT 3U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004U + +#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002U + +#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720U + +#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT 7U +#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080U + +#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT 6U +#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040U + +#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT 5U +#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020U + +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT 4U +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010U + +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT 3U +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008U + +#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT 2U +#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004U + +#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT 27U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT 24U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH 3U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT 22U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH 1U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT 19U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH 3U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT 16U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH 3U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT 4U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH 12U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0U + +#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4U +#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000FU + +#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728U + +#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT 0U +#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH 12U +#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFFU + +#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFCU + +#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT 0U +#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH 32U +#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFFU +/** @} */ + +/** + * @name XQSPIPSU Generic FIFO masks information + * Generic FIFO masks information + * @{ + */ +/** + * Generic FIFO masks + */ +#define XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFFU +#define XQSPIPSU_GENFIFO_DATA_XFER 0x100U +#define XQSPIPSU_GENFIFO_EXP 0x200U +#define XQSPIPSU_GENFIFO_MODE_SPI 0x400U +#define XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800U +#define XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00U +#define XQSPIPSU_GENFIFO_MODE_MASK 0xC00U /* And with ~MASK first */ +#define XQSPIPSU_GENFIFO_CS_LOWER 0x1000U +#define XQSPIPSU_GENFIFO_CS_UPPER 0x2000U +#define XQSPIPSU_GENFIFO_BUS_LOWER 0x4000U +#define XQSPIPSU_GENFIFO_BUS_UPPER 0x8000U +#define XQSPIPSU_GENFIFO_BUS_BOTH 0xC000U /* inverse is no bus */ +#define XQSPIPSU_GENFIFO_BUS_MASK 0xC000U /* And with ~MASK first */ +#define XQSPIPSU_GENFIFO_TX 0x10000U /* inverse is zero pump */ +#define XQSPIPSU_GENFIFO_RX 0x20000U /* inverse is RX discard */ +#define XQSPIPSU_GENFIFO_STRIPE 0x40000U +#define XQSPIPSU_GENFIFO_POLL 0x80000U +/** @} */ + +/** + * @name XQSPIPSU RX Data Delay Register information + * @{ + */ +/** + * QSPI Data delay register + */ +#define XQSPIPSU_DATA_DLY_ADJ_OFFSET 0X000000F8U + +#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT 31U +#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH 1U +#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK 0X80000000U + +#define XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT 28U +#define XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH 3U +#define XQSPIPSU_DATA_DLY_ADJ_DLY_MASK 0X70000000U +/** @} */ + +/** + * @name TAPDLY Bypass register information + * @{ + */ +/** + * Tapdelay Bypass register + */ + +#if defined versal +#define IOU_TAPDLY_BYPASS_OFFSET 0X0000003CU +#else +#define IOU_TAPDLY_BYPASS_OFFSET 0X00000390U +#endif + +#define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02U +#if !defined (versal) +#define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01U +#define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U +#endif + +#if defined versal +#define IOU_TAPDLY_RESET_STATE 0x4U +#else +#define IOU_TAPDLY_RESET_STATE 0x7U +#endif +/** @} */ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XQspiPsu_In32 Xil_In32 /**< Read the 32 bit register value */ +#define XQspiPsu_Out32 Xil_Out32 /**< Write the 32 bit register value */ + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XQspiPsu_ReadReg(u32 BaseAddress. s32 RegOffset) +* +******************************************************************************/ +#define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XQspiPsu_WriteReg(u32 BaseAddress, s32 RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + + +#ifdef __cplusplus +} +#endif + + +#endif /**< XQSPIPSU_H */ +/** @} */ diff --git a/bsps/include/fsl/edma.h b/bsps/include/fsl/edma.h index a2727f0c0e..bf37c0e3fc 100644 --- a/bsps/include/fsl/edma.h +++ b/bsps/include/fsl/edma.h @@ -7,7 +7,7 @@ */ /* - * Copyright (C) 2008-2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2008, 2020 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/include/fsl/regs-edma.h b/bsps/include/fsl/regs-edma.h index 4afdb9b4e4..2c87057af1 100644 --- a/bsps/include/fsl/regs-edma.h +++ b/bsps/include/fsl/regs-edma.h @@ -5,7 +5,7 @@ */ /* - * Copyright (C) 2011-2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2011, 2020 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/include/grlib/ahbstat-regs.h b/bsps/include/grlib/ahbstat-regs.h new file mode 100644 index 0000000000..6e50814da7 --- /dev/null +++ b/bsps/include/grlib/ahbstat-regs.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBAHBSTAT + * + * @brief This header file defines the AHBSTAT register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/ahbstat-header */ + +#ifndef _GRLIB_AHBSTAT_REGS_H +#define _GRLIB_AHBSTAT_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/ahbstat */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBSTAT AHBSTAT + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the AHBSTAT interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBSTATAHBS AHB Status register (AHBS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBSTAT_AHBS_ME 0x2000U + +#define AHBSTAT_AHBS_FW 0x1000U + +#define AHBSTAT_AHBS_CF 0x800U + +#define AHBSTAT_AHBS_AF 0x400U + +#define AHBSTAT_AHBS_CE 0x200U + +#define AHBSTAT_AHBS_NE 0x100U + +#define AHBSTAT_AHBS_HWRITE 0x80U + +#define AHBSTAT_AHBS_HMASTER_SHIFT 3 +#define AHBSTAT_AHBS_HMASTER_MASK 0x78U +#define AHBSTAT_AHBS_HMASTER_GET( _reg ) \ + ( ( ( _reg ) & AHBSTAT_AHBS_HMASTER_MASK ) >> \ + AHBSTAT_AHBS_HMASTER_SHIFT ) +#define AHBSTAT_AHBS_HMASTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBSTAT_AHBS_HMASTER_MASK ) | \ + ( ( ( _val ) << AHBSTAT_AHBS_HMASTER_SHIFT ) & \ + AHBSTAT_AHBS_HMASTER_MASK ) ) +#define AHBSTAT_AHBS_HMASTER( _val ) \ + ( ( ( _val ) << AHBSTAT_AHBS_HMASTER_SHIFT ) & \ + AHBSTAT_AHBS_HMASTER_MASK ) + +#define AHBSTAT_AHBS_HSIZE_SHIFT 0 +#define AHBSTAT_AHBS_HSIZE_MASK 0x7U +#define AHBSTAT_AHBS_HSIZE_GET( _reg ) \ + ( ( ( _reg ) & AHBSTAT_AHBS_HSIZE_MASK ) >> \ + AHBSTAT_AHBS_HSIZE_SHIFT ) +#define AHBSTAT_AHBS_HSIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBSTAT_AHBS_HSIZE_MASK ) | \ + ( ( ( _val ) << AHBSTAT_AHBS_HSIZE_SHIFT ) & \ + AHBSTAT_AHBS_HSIZE_MASK ) ) +#define AHBSTAT_AHBS_HSIZE( _val ) \ + ( ( ( _val ) << AHBSTAT_AHBS_HSIZE_SHIFT ) & \ + AHBSTAT_AHBS_HSIZE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBSTATAHBFAR \ + * AHB Failing address register (AHBFAR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBSTAT_AHBFAR_HADDR_SHIFT 0 +#define AHBSTAT_AHBFAR_HADDR_MASK 0xffffffffU +#define AHBSTAT_AHBFAR_HADDR_GET( _reg ) \ + ( ( ( _reg ) & AHBSTAT_AHBFAR_HADDR_MASK ) >> \ + AHBSTAT_AHBFAR_HADDR_SHIFT ) +#define AHBSTAT_AHBFAR_HADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBSTAT_AHBFAR_HADDR_MASK ) | \ + ( ( ( _val ) << AHBSTAT_AHBFAR_HADDR_SHIFT ) & \ + AHBSTAT_AHBFAR_HADDR_MASK ) ) +#define AHBSTAT_AHBFAR_HADDR( _val ) \ + ( ( ( _val ) << AHBSTAT_AHBFAR_HADDR_SHIFT ) & \ + AHBSTAT_AHBFAR_HADDR_MASK ) + +/** @} */ + +/** + * @brief This structure defines the AHBSTAT register block memory map. + */ +typedef struct ahbstat { + /** + * @brief See @ref RTEMSDeviceGRLIBAHBSTATAHBS. + */ + uint32_t ahbs; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBSTATAHBFAR. + */ + uint32_t ahbfar; +} ahbstat; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_AHBSTAT_REGS_H */ diff --git a/bsps/include/grlib/ahbstat.h b/bsps/include/grlib/ahbstat.h index 0baaad0732..c6502ab4b0 100644 --- a/bsps/include/grlib/ahbstat.h +++ b/bsps/include/grlib/ahbstat.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* AHBSTAT driver interface * * COPYRIGHT (c) 2011. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AHBSTAT_H__ diff --git a/bsps/include/grlib/ahbtrace-regs.h b/bsps/include/grlib/ahbtrace-regs.h new file mode 100644 index 0000000000..4526326894 --- /dev/null +++ b/bsps/include/grlib/ahbtrace-regs.h @@ -0,0 +1,313 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBAHBTRACE + * + * @brief This header file defines the AHBTRACE register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/ahbtrace-header */ + +#ifndef _GRLIB_AHBTRACE_REGS_H +#define _GRLIB_AHBTRACE_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/ahbtrace */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACE AHBTRACE + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the AHBTRACE interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACECTRL Trace buffer control register (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBTRACE_CTRL_DCNT_SHIFT 16 +#define AHBTRACE_CTRL_DCNT_MASK 0x7f0000U +#define AHBTRACE_CTRL_DCNT_GET( _reg ) \ + ( ( ( _reg ) & AHBTRACE_CTRL_DCNT_MASK ) >> \ + AHBTRACE_CTRL_DCNT_SHIFT ) +#define AHBTRACE_CTRL_DCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_CTRL_DCNT_MASK ) | \ + ( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & \ + AHBTRACE_CTRL_DCNT_MASK ) ) +#define AHBTRACE_CTRL_DCNT( _val ) \ + ( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & \ + AHBTRACE_CTRL_DCNT_MASK ) + +#define AHBTRACE_CTRL_PF 0x100U + +#define AHBTRACE_CTRL_BW_SHIFT 6 +#define AHBTRACE_CTRL_BW_MASK 0xc0U +#define AHBTRACE_CTRL_BW_GET( _reg ) \ + ( ( ( _reg ) & AHBTRACE_CTRL_BW_MASK ) >> \ + AHBTRACE_CTRL_BW_SHIFT ) +#define AHBTRACE_CTRL_BW_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_CTRL_BW_MASK ) | \ + ( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & \ + AHBTRACE_CTRL_BW_MASK ) ) +#define AHBTRACE_CTRL_BW( _val ) \ + ( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & \ + AHBTRACE_CTRL_BW_MASK ) + +#define AHBTRACE_CTRL_RF 0x20U + +#define AHBTRACE_CTRL_AF 0x10U + +#define AHBTRACE_CTRL_FR 0x8U + +#define AHBTRACE_CTRL_FW 0x4U + +#define AHBTRACE_CTRL_DM 0x2U + +#define AHBTRACE_CTRL_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACEINDEX Trace buffer index register (INDEX) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBTRACE_INDEX_INDEX_SHIFT 4 +#define AHBTRACE_INDEX_INDEX_MASK 0x7f0U +#define AHBTRACE_INDEX_INDEX_GET( _reg ) \ + ( ( ( _reg ) & AHBTRACE_INDEX_INDEX_MASK ) >> \ + AHBTRACE_INDEX_INDEX_SHIFT ) +#define AHBTRACE_INDEX_INDEX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_INDEX_INDEX_MASK ) | \ + ( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & \ + AHBTRACE_INDEX_INDEX_MASK ) ) +#define AHBTRACE_INDEX_INDEX( _val ) \ + ( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & \ + AHBTRACE_INDEX_INDEX_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACETIMETAG \ + * Trace buffer time tag register (TIMETAG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBTRACE_TIMETAG_TIMETAG_SHIFT 0 +#define AHBTRACE_TIMETAG_TIMETAG_MASK 0xffffffffU +#define AHBTRACE_TIMETAG_TIMETAG_GET( _reg ) \ + ( ( ( _reg ) & AHBTRACE_TIMETAG_TIMETAG_MASK ) >> \ + AHBTRACE_TIMETAG_TIMETAG_SHIFT ) +#define AHBTRACE_TIMETAG_TIMETAG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_TIMETAG_TIMETAG_MASK ) | \ + ( ( ( _val ) << AHBTRACE_TIMETAG_TIMETAG_SHIFT ) & \ + AHBTRACE_TIMETAG_TIMETAG_MASK ) ) +#define AHBTRACE_TIMETAG_TIMETAG( _val ) \ + ( ( ( _val ) << AHBTRACE_TIMETAG_TIMETAG_SHIFT ) & \ + AHBTRACE_TIMETAG_TIMETAG_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACEMSFILT \ + * Trace buffer master/slave filter register (MSFILT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBTRACE_MSFILT_SMASK_15_0_SHIFT 16 +#define AHBTRACE_MSFILT_SMASK_15_0_MASK 0xffff0000U +#define AHBTRACE_MSFILT_SMASK_15_0_GET( _reg ) \ + ( ( ( _reg ) & AHBTRACE_MSFILT_SMASK_15_0_MASK ) >> \ + AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) +#define AHBTRACE_MSFILT_SMASK_15_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_MSFILT_SMASK_15_0_MASK ) | \ + ( ( ( _val ) << AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) & \ + AHBTRACE_MSFILT_SMASK_15_0_MASK ) ) +#define AHBTRACE_MSFILT_SMASK_15_0( _val ) \ + ( ( ( _val ) << AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) & \ + AHBTRACE_MSFILT_SMASK_15_0_MASK ) + +#define AHBTRACE_MSFILT_MMASK_15_0_SHIFT 0 +#define AHBTRACE_MSFILT_MMASK_15_0_MASK 0xffffU +#define AHBTRACE_MSFILT_MMASK_15_0_GET( _reg ) \ + ( ( ( _reg ) & AHBTRACE_MSFILT_MMASK_15_0_MASK ) >> \ + AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) +#define AHBTRACE_MSFILT_MMASK_15_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_MSFILT_MMASK_15_0_MASK ) | \ + ( ( ( _val ) << AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) & \ + AHBTRACE_MSFILT_MMASK_15_0_MASK ) ) +#define AHBTRACE_MSFILT_MMASK_15_0( _val ) \ + ( ( ( _val ) << AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) & \ + AHBTRACE_MSFILT_MMASK_15_0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACETBBA \ + * Trace buffer break address registers (TBBA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBTRACE_TBBA_BADDR_31_2_SHIFT 2 +#define AHBTRACE_TBBA_BADDR_31_2_MASK 0xfffffffcU +#define AHBTRACE_TBBA_BADDR_31_2_GET( _reg ) \ + ( ( ( _reg ) & AHBTRACE_TBBA_BADDR_31_2_MASK ) >> \ + AHBTRACE_TBBA_BADDR_31_2_SHIFT ) +#define AHBTRACE_TBBA_BADDR_31_2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_TBBA_BADDR_31_2_MASK ) | \ + ( ( ( _val ) << AHBTRACE_TBBA_BADDR_31_2_SHIFT ) & \ + AHBTRACE_TBBA_BADDR_31_2_MASK ) ) +#define AHBTRACE_TBBA_BADDR_31_2( _val ) \ + ( ( ( _val ) << AHBTRACE_TBBA_BADDR_31_2_SHIFT ) & \ + AHBTRACE_TBBA_BADDR_31_2_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACETBBM \ + * Trace buffer break mask registers (TBBM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBTRACE_TBBM_BMASK_31_2_SHIFT 2 +#define AHBTRACE_TBBM_BMASK_31_2_MASK 0xfffffffcU +#define AHBTRACE_TBBM_BMASK_31_2_GET( _reg ) \ + ( ( ( _reg ) & AHBTRACE_TBBM_BMASK_31_2_MASK ) >> \ + AHBTRACE_TBBM_BMASK_31_2_SHIFT ) +#define AHBTRACE_TBBM_BMASK_31_2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~AHBTRACE_TBBM_BMASK_31_2_MASK ) | \ + ( ( ( _val ) << AHBTRACE_TBBM_BMASK_31_2_SHIFT ) & \ + AHBTRACE_TBBM_BMASK_31_2_MASK ) ) +#define AHBTRACE_TBBM_BMASK_31_2( _val ) \ + ( ( ( _val ) << AHBTRACE_TBBM_BMASK_31_2_SHIFT ) & \ + AHBTRACE_TBBM_BMASK_31_2_MASK ) + +#define AHBTRACE_TBBM_LD 0x2U + +#define AHBTRACE_TBBM_ST 0x1U + +/** @} */ + +/** + * @brief This structure defines the AHBTRACE register block memory map. + */ +typedef struct ahbtrace { + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACECTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACEINDEX. + */ + uint32_t index; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACETIMETAG. + */ + uint32_t timetag; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACEMSFILT. + */ + uint32_t msfilt; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBA. + */ + uint32_t tbba_0; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBM. + */ + uint32_t tbbm_0; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBA. + */ + uint32_t tbba_1; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBM. + */ + uint32_t tbbm_1; +} ahbtrace; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_AHBTRACE_REGS_H */ diff --git a/bsps/include/grlib/ambapp.h b/bsps/include/grlib/ambapp.h index bcc26e1efe..1afd802860 100644 --- a/bsps/include/grlib/ambapp.h +++ b/bsps/include/grlib/ambapp.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup amba @@ -7,9 +9,26 @@ * COPYRIGHT (c) 2009. * Aeroflex Gaisler. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AMBAPP_H__ diff --git a/bsps/include/grlib/ambapp_bus.h b/bsps/include/grlib/ambapp_bus.h index 87cd52bc69..b62ebc0fa3 100644 --- a/bsps/include/grlib/ambapp_bus.h +++ b/bsps/include/grlib/ambapp_bus.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* General part of a AMBA Plug & Play bus driver. * * COPYRIGHT (c) 2008. @@ -8,9 +10,26 @@ * the code size smaller for systems with multiple AMBA Plug & * Play buses. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AMBAPP_BUS_H__ diff --git a/bsps/include/grlib/ambapp_bus_grlib.h b/bsps/include/grlib/ambapp_bus_grlib.h index 2def4bc2b4..b6e5ddfb06 100644 --- a/bsps/include/grlib/ambapp_bus_grlib.h +++ b/bsps/include/grlib/ambapp_bus_grlib.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* LEON3 GRLIB AMBA Plug & Play bus driver interface. * * COPYRIGHT (c) 2008. @@ -6,9 +8,26 @@ * This is driver is a wrapper for the general AMBA Plug & Play bus * driver. This is the root bus driver for GRLIB systems. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AMBAPP_BUS_GRLIB_H__ diff --git a/bsps/include/grlib/ambapp_ids.h b/bsps/include/grlib/ambapp_ids.h index 629b4fb37a..df578d093a 100644 --- a/bsps/include/grlib/ambapp_ids.h +++ b/bsps/include/grlib/ambapp_ids.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup amba @@ -11,9 +13,26 @@ * This header file provide all known VENDOR and DEVICE IDs available * in the AMBA Plug & Play information. Taken from GRLIB 3386. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * */ diff --git a/bsps/include/grlib/apbuart-regs.h b/bsps/include/grlib/apbuart-regs.h new file mode 100644 index 0000000000..c3ea2d0f8e --- /dev/null +++ b/bsps/include/grlib/apbuart-regs.h @@ -0,0 +1,281 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBAPBUART + * + * @brief This header file defines the APBUART register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/apbuart-header */ + +#ifndef _GRLIB_APBUART_REGS_H +#define _GRLIB_APBUART_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/apbuart */ + +/** + * @defgroup RTEMSDeviceGRLIBAPBUART APBUART + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the APBUART interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBAPBUARTDATA UART data register (DATA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define APBUART_DATA_DATA_SHIFT 0 +#define APBUART_DATA_DATA_MASK 0xffU +#define APBUART_DATA_DATA_GET( _reg ) \ + ( ( ( _reg ) & APBUART_DATA_DATA_MASK ) >> \ + APBUART_DATA_DATA_SHIFT ) +#define APBUART_DATA_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~APBUART_DATA_DATA_MASK ) | \ + ( ( ( _val ) << APBUART_DATA_DATA_SHIFT ) & \ + APBUART_DATA_DATA_MASK ) ) +#define APBUART_DATA_DATA( _val ) \ + ( ( ( _val ) << APBUART_DATA_DATA_SHIFT ) & \ + APBUART_DATA_DATA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAPBUARTSTATUS UART status register (STATUS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define APBUART_STATUS_RCNT_SHIFT 26 +#define APBUART_STATUS_RCNT_MASK 0xfc000000U +#define APBUART_STATUS_RCNT_GET( _reg ) \ + ( ( ( _reg ) & APBUART_STATUS_RCNT_MASK ) >> \ + APBUART_STATUS_RCNT_SHIFT ) +#define APBUART_STATUS_RCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~APBUART_STATUS_RCNT_MASK ) | \ + ( ( ( _val ) << APBUART_STATUS_RCNT_SHIFT ) & \ + APBUART_STATUS_RCNT_MASK ) ) +#define APBUART_STATUS_RCNT( _val ) \ + ( ( ( _val ) << APBUART_STATUS_RCNT_SHIFT ) & \ + APBUART_STATUS_RCNT_MASK ) + +#define APBUART_STATUS_TCNT_SHIFT 20 +#define APBUART_STATUS_TCNT_MASK 0x3f00000U +#define APBUART_STATUS_TCNT_GET( _reg ) \ + ( ( ( _reg ) & APBUART_STATUS_TCNT_MASK ) >> \ + APBUART_STATUS_TCNT_SHIFT ) +#define APBUART_STATUS_TCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~APBUART_STATUS_TCNT_MASK ) | \ + ( ( ( _val ) << APBUART_STATUS_TCNT_SHIFT ) & \ + APBUART_STATUS_TCNT_MASK ) ) +#define APBUART_STATUS_TCNT( _val ) \ + ( ( ( _val ) << APBUART_STATUS_TCNT_SHIFT ) & \ + APBUART_STATUS_TCNT_MASK ) + +#define APBUART_STATUS_RF 0x400U + +#define APBUART_STATUS_TF 0x200U + +#define APBUART_STATUS_RH 0x100U + +#define APBUART_STATUS_TH 0x80U + +#define APBUART_STATUS_FE 0x40U + +#define APBUART_STATUS_PE 0x20U + +#define APBUART_STATUS_OV 0x10U + +#define APBUART_STATUS_BR 0x8U + +#define APBUART_STATUS_TE 0x4U + +#define APBUART_STATUS_TS 0x2U + +#define APBUART_STATUS_DR 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAPBUARTCTRL UART control register (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define APBUART_CTRL_FA 0x80000000U + +#define APBUART_CTRL_SI 0x4000U + +#define APBUART_CTRL_DI 0x2000U + +#define APBUART_CTRL_BI 0x1000U + +#define APBUART_CTRL_DB 0x800U + +#define APBUART_CTRL_RF 0x400U + +#define APBUART_CTRL_TF 0x200U + +#define APBUART_CTRL_EC 0x100U + +#define APBUART_CTRL_LB 0x80U + +#define APBUART_CTRL_FL 0x40U + +#define APBUART_CTRL_PE 0x20U + +#define APBUART_CTRL_PS 0x10U + +#define APBUART_CTRL_TI 0x8U + +#define APBUART_CTRL_RI 0x4U + +#define APBUART_CTRL_TE 0x2U + +#define APBUART_CTRL_RE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAPBUARTSCALER UART scaler reload register (SCALER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT 0 +#define APBUART_SCALER_SCALER_RELOAD_VALUE_MASK 0xfffffU +#define APBUART_SCALER_SCALER_RELOAD_VALUE_GET( _reg ) \ + ( ( ( _reg ) & APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) >> \ + APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT ) +#define APBUART_SCALER_SCALER_RELOAD_VALUE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) | \ + ( ( ( _val ) << APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT ) & \ + APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) ) +#define APBUART_SCALER_SCALER_RELOAD_VALUE( _val ) \ + ( ( ( _val ) << APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT ) & \ + APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAPBUARTFIFO UART FIFO debug register (FIFO) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define APBUART_FIFO_DATA_SHIFT 0 +#define APBUART_FIFO_DATA_MASK 0xffU +#define APBUART_FIFO_DATA_GET( _reg ) \ + ( ( ( _reg ) & APBUART_FIFO_DATA_MASK ) >> \ + APBUART_FIFO_DATA_SHIFT ) +#define APBUART_FIFO_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~APBUART_FIFO_DATA_MASK ) | \ + ( ( ( _val ) << APBUART_FIFO_DATA_SHIFT ) & \ + APBUART_FIFO_DATA_MASK ) ) +#define APBUART_FIFO_DATA( _val ) \ + ( ( ( _val ) << APBUART_FIFO_DATA_SHIFT ) & \ + APBUART_FIFO_DATA_MASK ) + +/** @} */ + +/** + * @brief This structure defines the APBUART register block memory map. + */ +typedef struct apbuart { + /** + * @brief See @ref RTEMSDeviceGRLIBAPBUARTDATA. + */ + uint32_t data; + + /** + * @brief See @ref RTEMSDeviceGRLIBAPBUARTSTATUS. + */ + uint32_t status; + + /** + * @brief See @ref RTEMSDeviceGRLIBAPBUARTCTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSDeviceGRLIBAPBUARTSCALER. + */ + uint32_t scaler; + + /** + * @brief See @ref RTEMSDeviceGRLIBAPBUARTFIFO. + */ + uint32_t fifo; +} apbuart; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_APBUART_REGS_H */ diff --git a/bsps/include/grlib/apbuart.h b/bsps/include/grlib/apbuart.h index f54689abc2..b53c338407 100644 --- a/bsps/include/grlib/apbuart.h +++ b/bsps/include/grlib/apbuart.h @@ -1,77 +1,110 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file - * @ingroup uart + * + * @ingroup RTEMSDeviceGRLIBAPBUART + * + * @brief This header file defines the APBUART interface. */ /* - * COPYRIGHT (c) 2007. - * Gaisler Research + * Copyright (C) 2021 embedded brains GmbH & Co. KG * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __APBUART_H__ -#define __APBUART_H__ - -/** - * @defgroup uart UART +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: * - * @ingroup RTEMSBSPsSharedGRLIB + * https://www.rtems.org/bugs.html * - * @brief Driver interface for APBUART + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: * - * @{ + * https://docs.rtems.org */ -#include "ambapp.h" -#include "grlib.h" +/* Generated from spec:/dev/grlib/if/apbuart-header-2 */ + +#ifndef _GRLIB_APBUART_H +#define _GRLIB_APBUART_H + +#include <grlib/apbuart-regs.h> #ifdef __cplusplus extern "C" { #endif -#define APBUART_CTRL_RE 0x1 -#define APBUART_CTRL_TE 0x2 -#define APBUART_CTRL_RI 0x4 -#define APBUART_CTRL_TI 0x8 -#define APBUART_CTRL_PS 0x10 -#define APBUART_CTRL_PE 0x20 -#define APBUART_CTRL_FL 0x40 -#define APBUART_CTRL_LB 0x80 -#define APBUART_CTRL_EC 0x100 -#define APBUART_CTRL_TF 0x200 -#define APBUART_CTRL_RF 0x400 -#define APBUART_CTRL_DB 0x800 -#define APBUART_CTRL_BI 0x1000 -#define APBUART_CTRL_DI 0x2000 -#define APBUART_CTRL_FA 0x80000000 +/* Generated from spec:/dev/grlib/if/apbuart-inbyte-nonblocking */ -#define APBUART_STATUS_DR 0x1 -#define APBUART_STATUS_TS 0x2 -#define APBUART_STATUS_TE 0x4 -#define APBUART_STATUS_BR 0x8 -#define APBUART_STATUS_OV 0x10 -#define APBUART_STATUS_PE 0x20 -#define APBUART_STATUS_FE 0x40 -#define APBUART_STATUS_ERR 0x78 -#define APBUART_STATUS_TH 0x80 -#define APBUART_STATUS_RH 0x100 -#define APBUART_STATUS_TF 0x200 -#define APBUART_STATUS_RF 0x400 +/** + * @ingroup RTEMSDeviceGRLIBAPBUART + * + * @brief Clears all errors and tries to get one character from the receiver + * FIFO. + * + * @param regs is the pointer to the APBUART register block. + * + * @retval -1 The receiver FIFO was empty. + * + * @return Returns the first character of the receiver FIFO if it was + * non-empty. + */ +int apbuart_inbyte_nonblocking( apbuart *regs ); + +/* Generated from spec:/dev/grlib/if/apbuart-outbyte-polled */ -void apbuart_outbyte_wait(const struct apbuart_regs *regs); +/** + * @ingroup RTEMSDeviceGRLIBAPBUART + * + * @brief Waits until an empty transmitter FIFO was observed and then stores + * the character to the data register. + * + * @param regs is the pointer to the APBUART register block. + * + * @param ch is the character to output. + */ +void apbuart_outbyte_polled( apbuart *regs, char ch ); -void apbuart_outbyte_polled(struct apbuart_regs *regs, char ch); +/* Generated from spec:/dev/grlib/if/apbuart-outbyte-wait */ -int apbuart_inbyte_nonblocking(struct apbuart_regs *regs); +/** + * @ingroup RTEMSDeviceGRLIBAPBUART + * + * @brief Ensures that at least once an empty transmitter FIFO was observed. + * + * @param regs is the pointer to the APBUART register block. + */ +void apbuart_outbyte_wait( const apbuart *regs ); #ifdef __cplusplus } #endif -/** @} */ - -#endif /* __APBUART_H__ */ +#endif /* _GRLIB_APBUART_H */ diff --git a/bsps/include/grlib/apbuart_cons.h b/bsps/include/grlib/apbuart_cons.h index d0ac9244af..a2846580cc 100644 --- a/bsps/include/grlib/apbuart_cons.h +++ b/bsps/include/grlib/apbuart_cons.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* APBUART Console driver interface * * COPYRIGHT (c) 2015. * Cobham Gaisler. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __APBUART_CONS_H__ diff --git a/bsps/include/grlib/apbuart_termios.h b/bsps/include/grlib/apbuart_termios.h index ca6b5d3b3e..a19b99b609 100644 --- a/bsps/include/grlib/apbuart_termios.h +++ b/bsps/include/grlib/apbuart_termios.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * COPYRIGHT (c) 1989-1998. * On-Line Applications Research Corporation (OAR). @@ -6,16 +8,33 @@ * COPYRIGHT (c) 2004. * Gaisler Research. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef APBUART_TERMIOS_H #define APBUART_TERMIOS_H #include <rtems/termiostypes.h> -#include "grlib.h" +#include "apbuart.h" #ifdef __cplusplus extern "C" { @@ -23,7 +42,7 @@ extern "C" { struct apbuart_context { rtems_termios_device_context base; - struct apbuart_regs *regs; + apbuart *regs; unsigned int freq_hz; rtems_vector_number irq; volatile int sending; diff --git a/bsps/include/grlib/b1553brm.h b/bsps/include/grlib/b1553brm.h index bb7294de43..0e4a5f4881 100644 --- a/bsps/include/grlib/b1553brm.h +++ b/bsps/include/grlib/b1553brm.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup 1553 @@ -7,9 +9,26 @@ * COPYRIGHT (c) 2006. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __B1553BRM_H__ diff --git a/bsps/include/grlib/b1553rt.h b/bsps/include/grlib/b1553rt.h index fbe4b706de..d3aa3eb34a 100644 --- a/bsps/include/grlib/b1553rt.h +++ b/bsps/include/grlib/b1553rt.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* B1553RT driver interface * * COPYRIGHT (c) 2009. * Aeroflex Gaisler AB * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __B1553RT_H__ diff --git a/bsps/include/grlib/bspcommon.h b/bsps/include/grlib/bspcommon.h index d3470009f8..996fe6e80b 100644 --- a/bsps/include/grlib/bspcommon.h +++ b/bsps/include/grlib/bspcommon.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* Common BSP/driver configuration routines. * * COPYRIGHT (c) 2015. * Cobham Gaisler. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * */ diff --git a/bsps/include/grlib/canmux.h b/bsps/include/grlib/canmux.h index 02727f44c7..1b59f7d468 100644 --- a/bsps/include/grlib/canmux.h +++ b/bsps/include/grlib/canmux.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * Header file for RTEMS CAN_MUX driver * * COPYRIGHT (c) 2008. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __CANMUX_H__ diff --git a/bsps/include/grlib/cons.h b/bsps/include/grlib/cons.h index c30e41cf14..6f1f7ed44f 100644 --- a/bsps/include/grlib/cons.h +++ b/bsps/include/grlib/cons.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* Console driver interface to UART drivers * * - First console device that has System Console flag set will be @@ -8,9 +10,26 @@ * COPYRIGHT (c) 2010. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __CONS_H__ diff --git a/bsps/include/grlib/debug_defs.h b/bsps/include/grlib/debug_defs.h index 6425bd6f01..bd425de152 100644 --- a/bsps/include/grlib/debug_defs.h +++ b/bsps/include/grlib/debug_defs.h @@ -1,3 +1,32 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * COPYRIGHT (c) 2007. + * Cobham Gaisler. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + /** * @file * @ingroup RTEMSBSPsSharedGRLIB diff --git a/bsps/include/grlib/dsu4-regs.h b/bsps/include/grlib/dsu4-regs.h new file mode 100644 index 0000000000..3695430198 --- /dev/null +++ b/bsps/include/grlib/dsu4-regs.h @@ -0,0 +1,788 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBDSU4 + * + * @brief This header file defines the DSU4 register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/dsu4-header */ + +#ifndef _GRLIB_DSU4_REGS_H +#define _GRLIB_DSU4_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/dsu4 */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4 DSU4 + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the DSU4 interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4CTRL DSU control register (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_CTRL_PW 0x800U + +#define DSU4_CTRL_HL 0x400U + +#define DSU4_CTRL_PE 0x200U + +#define DSU4_CTRL_EB 0x100U + +#define DSU4_CTRL_EE 0x80U + +#define DSU4_CTRL_DM 0x40U + +#define DSU4_CTRL_BZ 0x20U + +#define DSU4_CTRL_BX 0x10U + +#define DSU4_CTRL_BS 0x8U + +#define DSU4_CTRL_BW 0x4U + +#define DSU4_CTRL_BE 0x2U + +#define DSU4_CTRL_TE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4DTTC DSU time tag counter register (DTTC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_DTTC_TIMETAG_SHIFT 0 +#define DSU4_DTTC_TIMETAG_MASK 0xffffffffU +#define DSU4_DTTC_TIMETAG_GET( _reg ) \ + ( ( ( _reg ) & DSU4_DTTC_TIMETAG_MASK ) >> \ + DSU4_DTTC_TIMETAG_SHIFT ) +#define DSU4_DTTC_TIMETAG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_DTTC_TIMETAG_MASK ) | \ + ( ( ( _val ) << DSU4_DTTC_TIMETAG_SHIFT ) & \ + DSU4_DTTC_TIMETAG_MASK ) ) +#define DSU4_DTTC_TIMETAG( _val ) \ + ( ( ( _val ) << DSU4_DTTC_TIMETAG_SHIFT ) & \ + DSU4_DTTC_TIMETAG_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4BRSS DSU break and single step register (BRSS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_BRSS_SS_3_0_SHIFT 16 +#define DSU4_BRSS_SS_3_0_MASK 0xf0000U +#define DSU4_BRSS_SS_3_0_GET( _reg ) \ + ( ( ( _reg ) & DSU4_BRSS_SS_3_0_MASK ) >> \ + DSU4_BRSS_SS_3_0_SHIFT ) +#define DSU4_BRSS_SS_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_BRSS_SS_3_0_MASK ) | \ + ( ( ( _val ) << DSU4_BRSS_SS_3_0_SHIFT ) & \ + DSU4_BRSS_SS_3_0_MASK ) ) +#define DSU4_BRSS_SS_3_0( _val ) \ + ( ( ( _val ) << DSU4_BRSS_SS_3_0_SHIFT ) & \ + DSU4_BRSS_SS_3_0_MASK ) + +#define DSU4_BRSS_BN_3_0_SHIFT 0 +#define DSU4_BRSS_BN_3_0_MASK 0xfU +#define DSU4_BRSS_BN_3_0_GET( _reg ) \ + ( ( ( _reg ) & DSU4_BRSS_BN_3_0_MASK ) >> \ + DSU4_BRSS_BN_3_0_SHIFT ) +#define DSU4_BRSS_BN_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_BRSS_BN_3_0_MASK ) | \ + ( ( ( _val ) << DSU4_BRSS_BN_3_0_SHIFT ) & \ + DSU4_BRSS_BN_3_0_MASK ) ) +#define DSU4_BRSS_BN_3_0( _val ) \ + ( ( ( _val ) << DSU4_BRSS_BN_3_0_SHIFT ) & \ + DSU4_BRSS_BN_3_0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4DBGM DSU debug mode mask register (DBGM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_DBGM_DM_3_0_SHIFT 16 +#define DSU4_DBGM_DM_3_0_MASK 0xf0000U +#define DSU4_DBGM_DM_3_0_GET( _reg ) \ + ( ( ( _reg ) & DSU4_DBGM_DM_3_0_MASK ) >> \ + DSU4_DBGM_DM_3_0_SHIFT ) +#define DSU4_DBGM_DM_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_DBGM_DM_3_0_MASK ) | \ + ( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & \ + DSU4_DBGM_DM_3_0_MASK ) ) +#define DSU4_DBGM_DM_3_0( _val ) \ + ( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & \ + DSU4_DBGM_DM_3_0_MASK ) + +#define DSU4_DBGM_ED_3_0_SHIFT 0 +#define DSU4_DBGM_ED_3_0_MASK 0xfU +#define DSU4_DBGM_ED_3_0_GET( _reg ) \ + ( ( ( _reg ) & DSU4_DBGM_ED_3_0_MASK ) >> \ + DSU4_DBGM_ED_3_0_SHIFT ) +#define DSU4_DBGM_ED_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_DBGM_ED_3_0_MASK ) | \ + ( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & \ + DSU4_DBGM_ED_3_0_MASK ) ) +#define DSU4_DBGM_ED_3_0( _val ) \ + ( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & \ + DSU4_DBGM_ED_3_0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4DTR DSU trap register (DTR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_DTR_EM 0x1000U + +#define DSU4_DTR_TRAPTYPE_SHIFT 4 +#define DSU4_DTR_TRAPTYPE_MASK 0xff0U +#define DSU4_DTR_TRAPTYPE_GET( _reg ) \ + ( ( ( _reg ) & DSU4_DTR_TRAPTYPE_MASK ) >> \ + DSU4_DTR_TRAPTYPE_SHIFT ) +#define DSU4_DTR_TRAPTYPE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_DTR_TRAPTYPE_MASK ) | \ + ( ( ( _val ) << DSU4_DTR_TRAPTYPE_SHIFT ) & \ + DSU4_DTR_TRAPTYPE_MASK ) ) +#define DSU4_DTR_TRAPTYPE( _val ) \ + ( ( ( _val ) << DSU4_DTR_TRAPTYPE_SHIFT ) & \ + DSU4_DTR_TRAPTYPE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4DASI DSU ASI diagnostic access register (DASI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_DASI_ASI_SHIFT 0 +#define DSU4_DASI_ASI_MASK 0xffU +#define DSU4_DASI_ASI_GET( _reg ) \ + ( ( ( _reg ) & DSU4_DASI_ASI_MASK ) >> \ + DSU4_DASI_ASI_SHIFT ) +#define DSU4_DASI_ASI_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_DASI_ASI_MASK ) | \ + ( ( ( _val ) << DSU4_DASI_ASI_SHIFT ) & \ + DSU4_DASI_ASI_MASK ) ) +#define DSU4_DASI_ASI( _val ) \ + ( ( ( _val ) << DSU4_DASI_ASI_SHIFT ) & \ + DSU4_DASI_ASI_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ATBC AHB trace buffer control register (ATBC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ATBC_DCNT_SHIFT 16 +#define DSU4_ATBC_DCNT_MASK 0xff0000U +#define DSU4_ATBC_DCNT_GET( _reg ) \ + ( ( ( _reg ) & DSU4_ATBC_DCNT_MASK ) >> \ + DSU4_ATBC_DCNT_SHIFT ) +#define DSU4_ATBC_DCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ATBC_DCNT_MASK ) | \ + ( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & \ + DSU4_ATBC_DCNT_MASK ) ) +#define DSU4_ATBC_DCNT( _val ) \ + ( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & \ + DSU4_ATBC_DCNT_MASK ) + +#define DSU4_ATBC_DF 0x100U + +#define DSU4_ATBC_SF 0x80U + +#define DSU4_ATBC_TE 0x40U + +#define DSU4_ATBC_TF 0x20U + +#define DSU4_ATBC_BW_SHIFT 3 +#define DSU4_ATBC_BW_MASK 0x18U +#define DSU4_ATBC_BW_GET( _reg ) \ + ( ( ( _reg ) & DSU4_ATBC_BW_MASK ) >> \ + DSU4_ATBC_BW_SHIFT ) +#define DSU4_ATBC_BW_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ATBC_BW_MASK ) | \ + ( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & \ + DSU4_ATBC_BW_MASK ) ) +#define DSU4_ATBC_BW( _val ) \ + ( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & \ + DSU4_ATBC_BW_MASK ) + +#define DSU4_ATBC_BR 0x4U + +#define DSU4_ATBC_DM 0x2U + +#define DSU4_ATBC_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ATBI AHB trace buffer index register (ATBI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ATBI_INDEX_SHIFT 4 +#define DSU4_ATBI_INDEX_MASK 0xff0U +#define DSU4_ATBI_INDEX_GET( _reg ) \ + ( ( ( _reg ) & DSU4_ATBI_INDEX_MASK ) >> \ + DSU4_ATBI_INDEX_SHIFT ) +#define DSU4_ATBI_INDEX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ATBI_INDEX_MASK ) | \ + ( ( ( _val ) << DSU4_ATBI_INDEX_SHIFT ) & \ + DSU4_ATBI_INDEX_MASK ) ) +#define DSU4_ATBI_INDEX( _val ) \ + ( ( ( _val ) << DSU4_ATBI_INDEX_SHIFT ) & \ + DSU4_ATBI_INDEX_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ATBFC \ + * AHB trace buffer filter control register (ATBFC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ATBFC_WPF_SHIFT 12 +#define DSU4_ATBFC_WPF_MASK 0x3000U +#define DSU4_ATBFC_WPF_GET( _reg ) \ + ( ( ( _reg ) & DSU4_ATBFC_WPF_MASK ) >> \ + DSU4_ATBFC_WPF_SHIFT ) +#define DSU4_ATBFC_WPF_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ATBFC_WPF_MASK ) | \ + ( ( ( _val ) << DSU4_ATBFC_WPF_SHIFT ) & \ + DSU4_ATBFC_WPF_MASK ) ) +#define DSU4_ATBFC_WPF( _val ) \ + ( ( ( _val ) << DSU4_ATBFC_WPF_SHIFT ) & \ + DSU4_ATBFC_WPF_MASK ) + +#define DSU4_ATBFC_BPF_SHIFT 8 +#define DSU4_ATBFC_BPF_MASK 0x300U +#define DSU4_ATBFC_BPF_GET( _reg ) \ + ( ( ( _reg ) & DSU4_ATBFC_BPF_MASK ) >> \ + DSU4_ATBFC_BPF_SHIFT ) +#define DSU4_ATBFC_BPF_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ATBFC_BPF_MASK ) | \ + ( ( ( _val ) << DSU4_ATBFC_BPF_SHIFT ) & \ + DSU4_ATBFC_BPF_MASK ) ) +#define DSU4_ATBFC_BPF( _val ) \ + ( ( ( _val ) << DSU4_ATBFC_BPF_SHIFT ) & \ + DSU4_ATBFC_BPF_MASK ) + +#define DSU4_ATBFC_PF 0x8U + +#define DSU4_ATBFC_AF 0x4U + +#define DSU4_ATBFC_FR 0x2U + +#define DSU4_ATBFC_FW 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ATBFM \ + * AHB trace buffer filter mask register (ATBFM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ATBFM_SMASK_15_0_SHIFT 16 +#define DSU4_ATBFM_SMASK_15_0_MASK 0xffff0000U +#define DSU4_ATBFM_SMASK_15_0_GET( _reg ) \ + ( ( ( _reg ) & DSU4_ATBFM_SMASK_15_0_MASK ) >> \ + DSU4_ATBFM_SMASK_15_0_SHIFT ) +#define DSU4_ATBFM_SMASK_15_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ATBFM_SMASK_15_0_MASK ) | \ + ( ( ( _val ) << DSU4_ATBFM_SMASK_15_0_SHIFT ) & \ + DSU4_ATBFM_SMASK_15_0_MASK ) ) +#define DSU4_ATBFM_SMASK_15_0( _val ) \ + ( ( ( _val ) << DSU4_ATBFM_SMASK_15_0_SHIFT ) & \ + DSU4_ATBFM_SMASK_15_0_MASK ) + +#define DSU4_ATBFM_MMASK_15_0_SHIFT 0 +#define DSU4_ATBFM_MMASK_15_0_MASK 0xffffU +#define DSU4_ATBFM_MMASK_15_0_GET( _reg ) \ + ( ( ( _reg ) & DSU4_ATBFM_MMASK_15_0_MASK ) >> \ + DSU4_ATBFM_MMASK_15_0_SHIFT ) +#define DSU4_ATBFM_MMASK_15_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ATBFM_MMASK_15_0_MASK ) | \ + ( ( ( _val ) << DSU4_ATBFM_MMASK_15_0_SHIFT ) & \ + DSU4_ATBFM_MMASK_15_0_MASK ) ) +#define DSU4_ATBFM_MMASK_15_0( _val ) \ + ( ( ( _val ) << DSU4_ATBFM_MMASK_15_0_SHIFT ) & \ + DSU4_ATBFM_MMASK_15_0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ATBBA \ + * AHB trace buffer break address registers (ATBBA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ATBBA_BADDR_31_2_SHIFT 2 +#define DSU4_ATBBA_BADDR_31_2_MASK 0xfffffffcU +#define DSU4_ATBBA_BADDR_31_2_GET( _reg ) \ + ( ( ( _reg ) & DSU4_ATBBA_BADDR_31_2_MASK ) >> \ + DSU4_ATBBA_BADDR_31_2_SHIFT ) +#define DSU4_ATBBA_BADDR_31_2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ATBBA_BADDR_31_2_MASK ) | \ + ( ( ( _val ) << DSU4_ATBBA_BADDR_31_2_SHIFT ) & \ + DSU4_ATBBA_BADDR_31_2_MASK ) ) +#define DSU4_ATBBA_BADDR_31_2( _val ) \ + ( ( ( _val ) << DSU4_ATBBA_BADDR_31_2_SHIFT ) & \ + DSU4_ATBBA_BADDR_31_2_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ATBBM \ + * AHB trace buffer break mask registers (ATBBM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ATBBM_BMASK_31_2_SHIFT 2 +#define DSU4_ATBBM_BMASK_31_2_MASK 0xfffffffcU +#define DSU4_ATBBM_BMASK_31_2_GET( _reg ) \ + ( ( ( _reg ) & DSU4_ATBBM_BMASK_31_2_MASK ) >> \ + DSU4_ATBBM_BMASK_31_2_SHIFT ) +#define DSU4_ATBBM_BMASK_31_2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ATBBM_BMASK_31_2_MASK ) | \ + ( ( ( _val ) << DSU4_ATBBM_BMASK_31_2_SHIFT ) & \ + DSU4_ATBBM_BMASK_31_2_MASK ) ) +#define DSU4_ATBBM_BMASK_31_2( _val ) \ + ( ( ( _val ) << DSU4_ATBBM_BMASK_31_2_SHIFT ) & \ + DSU4_ATBBM_BMASK_31_2_MASK ) + +#define DSU4_ATBBM_LD 0x2U + +#define DSU4_ATBBM_ST 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ICNT Instruction trace count register (ICNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ICNT_CE 0x80000000U + +#define DSU4_ICNT_IC 0x40000000U + +#define DSU4_ICNT_PE 0x20000000U + +#define DSU4_ICNT_ICOUNT_28_0_SHIFT 0 +#define DSU4_ICNT_ICOUNT_28_0_MASK 0x1fffffffU +#define DSU4_ICNT_ICOUNT_28_0_GET( _reg ) \ + ( ( ( _reg ) & DSU4_ICNT_ICOUNT_28_0_MASK ) >> \ + DSU4_ICNT_ICOUNT_28_0_SHIFT ) +#define DSU4_ICNT_ICOUNT_28_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ICNT_ICOUNT_28_0_MASK ) | \ + ( ( ( _val ) << DSU4_ICNT_ICOUNT_28_0_SHIFT ) & \ + DSU4_ICNT_ICOUNT_28_0_MASK ) ) +#define DSU4_ICNT_ICOUNT_28_0( _val ) \ + ( ( ( _val ) << DSU4_ICNT_ICOUNT_28_0_SHIFT ) & \ + DSU4_ICNT_ICOUNT_28_0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4AHBWPC \ + * AHB watchpoint control register (AHBWPC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_AHBWPC_IN 0x40U + +#define DSU4_AHBWPC_CP 0x20U + +#define DSU4_AHBWPC_EN 0x10U + +#define DSU4_AHBWPC_IN 0x4U + +#define DSU4_AHBWPC_CP 0x2U + +#define DSU4_AHBWPC_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4AHBWPD AHB watchpoint data registers (AHBWPD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_AHBWPD_DATA_SHIFT 0 +#define DSU4_AHBWPD_DATA_MASK 0xffffffffU +#define DSU4_AHBWPD_DATA_GET( _reg ) \ + ( ( ( _reg ) & DSU4_AHBWPD_DATA_MASK ) >> \ + DSU4_AHBWPD_DATA_SHIFT ) +#define DSU4_AHBWPD_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_AHBWPD_DATA_MASK ) | \ + ( ( ( _val ) << DSU4_AHBWPD_DATA_SHIFT ) & \ + DSU4_AHBWPD_DATA_MASK ) ) +#define DSU4_AHBWPD_DATA( _val ) \ + ( ( ( _val ) << DSU4_AHBWPD_DATA_SHIFT ) & \ + DSU4_AHBWPD_DATA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4AHBWPM AHB watchpoint mask registers (AHBWPM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_AHBWPM_MASK_SHIFT 0 +#define DSU4_AHBWPM_MASK_MASK 0xffffffffU +#define DSU4_AHBWPM_MASK_GET( _reg ) \ + ( ( ( _reg ) & DSU4_AHBWPM_MASK_MASK ) >> \ + DSU4_AHBWPM_MASK_SHIFT ) +#define DSU4_AHBWPM_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_AHBWPM_MASK_MASK ) | \ + ( ( ( _val ) << DSU4_AHBWPM_MASK_SHIFT ) & \ + DSU4_AHBWPM_MASK_MASK ) ) +#define DSU4_AHBWPM_MASK( _val ) \ + ( ( ( _val ) << DSU4_AHBWPM_MASK_SHIFT ) & \ + DSU4_AHBWPM_MASK_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ITBC0 \ + * Instruction trace buffer control register 0 (ITBC0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ITBC0_TFILT_SHIFT 28 +#define DSU4_ITBC0_TFILT_MASK 0xf0000000U +#define DSU4_ITBC0_TFILT_GET( _reg ) \ + ( ( ( _reg ) & DSU4_ITBC0_TFILT_MASK ) >> \ + DSU4_ITBC0_TFILT_SHIFT ) +#define DSU4_ITBC0_TFILT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ITBC0_TFILT_MASK ) | \ + ( ( ( _val ) << DSU4_ITBC0_TFILT_SHIFT ) & \ + DSU4_ITBC0_TFILT_MASK ) ) +#define DSU4_ITBC0_TFILT( _val ) \ + ( ( ( _val ) << DSU4_ITBC0_TFILT_SHIFT ) & \ + DSU4_ITBC0_TFILT_MASK ) + +#define DSU4_ITBC0_ITPOINTER_SHIFT 0 +#define DSU4_ITBC0_ITPOINTER_MASK 0xffffU +#define DSU4_ITBC0_ITPOINTER_GET( _reg ) \ + ( ( ( _reg ) & DSU4_ITBC0_ITPOINTER_MASK ) >> \ + DSU4_ITBC0_ITPOINTER_SHIFT ) +#define DSU4_ITBC0_ITPOINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ITBC0_ITPOINTER_MASK ) | \ + ( ( ( _val ) << DSU4_ITBC0_ITPOINTER_SHIFT ) & \ + DSU4_ITBC0_ITPOINTER_MASK ) ) +#define DSU4_ITBC0_ITPOINTER( _val ) \ + ( ( ( _val ) << DSU4_ITBC0_ITPOINTER_SHIFT ) & \ + DSU4_ITBC0_ITPOINTER_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ITBC1 \ + * Instruction trace buffer control register 1 (ITBC1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ITBC1_WO 0x8000000U + +#define DSU4_ITBC1_TLIM_SHIFT 24 +#define DSU4_ITBC1_TLIM_MASK 0x7000000U +#define DSU4_ITBC1_TLIM_GET( _reg ) \ + ( ( ( _reg ) & DSU4_ITBC1_TLIM_MASK ) >> \ + DSU4_ITBC1_TLIM_SHIFT ) +#define DSU4_ITBC1_TLIM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~DSU4_ITBC1_TLIM_MASK ) | \ + ( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & \ + DSU4_ITBC1_TLIM_MASK ) ) +#define DSU4_ITBC1_TLIM( _val ) \ + ( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & \ + DSU4_ITBC1_TLIM_MASK ) + +#define DSU4_ITBC1_TOV 0x800000U + +/** @} */ + +/** + * @brief This structure defines the DSU4 register block memory map. + */ +typedef struct dsu4 { + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4CTRL. + */ + uint32_t ctrl; + + uint32_t reserved_4_8; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4DTTC. + */ + uint32_t dttc; + + uint32_t reserved_c_20[ 5 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4BRSS. + */ + uint32_t brss; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4DBGM. + */ + uint32_t dbgm; + + uint32_t reserved_28_40[ 6 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBC. + */ + uint32_t atbc; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBI. + */ + uint32_t atbi; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBFC. + */ + uint32_t atbfc; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBFM. + */ + uint32_t atbfm; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBBA. + */ + uint32_t atbba_0; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBBM. + */ + uint32_t atbbm_0; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBBA. + */ + uint32_t atbba_1; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBBM. + */ + uint32_t atbbm_1; + + uint32_t reserved_60_70[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ICNT. + */ + uint32_t icnt; + + uint32_t reserved_74_80[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPC. + */ + uint32_t ahbwpc; + + uint32_t reserved_84_90[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPD. + */ + uint32_t ahbwpd_0; + + uint32_t reserved_94_9c[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPD. + */ + uint32_t ahbwpd_1; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPM. + */ + uint32_t ahbwpm_0; + + uint32_t reserved_a4_ac[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPM. + */ + uint32_t ahbwpm_1; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPD. + */ + uint32_t ahbwpd_2; + + uint32_t reserved_b4_bc[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPD. + */ + uint32_t ahbwpd_3; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPM. + */ + uint32_t ahbwpm_2; + + uint32_t reserved_c4_cc[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPM. + */ + uint32_t ahbwpm_3; + + uint32_t reserved_d0_110000[ 278476 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ITBC0. + */ + uint32_t itbc0; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ITBC1. + */ + uint32_t itbc1; + + uint32_t reserved_110008_400020[ 770054 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4DTR. + */ + uint32_t dtr; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4DASI. + */ + uint32_t dasi; +} dsu4; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_DSU4_REGS_H */ diff --git a/bsps/include/grlib/ftmctrl-regs.h b/bsps/include/grlib/ftmctrl-regs.h new file mode 100644 index 0000000000..fb4203270c --- /dev/null +++ b/bsps/include/grlib/ftmctrl-regs.h @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBFTMCTRL + * + * @brief This header file defines the FTMCTRL register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/ftmctrl-header */ + +#ifndef _GRLIB_FTMCTRL_REGS_H +#define _GRLIB_FTMCTRL_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/ftmctrl */ + +/** + * @defgroup RTEMSDeviceGRLIBFTMCTRL FTMCTRL + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the FTMCTRL interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG1 \ + * Memory configuration register 1 (MCFG1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define FTMCTRL_MCFG1_PBRDY 0x40000000U + +#define FTMCTRL_MCFG1_ABRDY 0x20000000U + +#define FTMCTRL_MCFG1_IOBUSW_SHIFT 27 +#define FTMCTRL_MCFG1_IOBUSW_MASK 0x18000000U +#define FTMCTRL_MCFG1_IOBUSW_GET( _reg ) \ + ( ( ( _reg ) & FTMCTRL_MCFG1_IOBUSW_MASK ) >> \ + FTMCTRL_MCFG1_IOBUSW_SHIFT ) +#define FTMCTRL_MCFG1_IOBUSW_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG1_IOBUSW_MASK ) | \ + ( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & \ + FTMCTRL_MCFG1_IOBUSW_MASK ) ) +#define FTMCTRL_MCFG1_IOBUSW( _val ) \ + ( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & \ + FTMCTRL_MCFG1_IOBUSW_MASK ) + +#define FTMCTRL_MCFG1_IBRDY 0x4000000U + +#define FTMCTRL_MCFG1_BEXCN 0x2000000U + +#define FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT 20 +#define FTMCTRL_MCFG1_IO_WAITSTATES_MASK 0xf00000U +#define FTMCTRL_MCFG1_IO_WAITSTATES_GET( _reg ) \ + ( ( ( _reg ) & FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) >> \ + FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) +#define FTMCTRL_MCFG1_IO_WAITSTATES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) | \ + ( ( ( _val ) << FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) & \ + FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) ) +#define FTMCTRL_MCFG1_IO_WAITSTATES( _val ) \ + ( ( ( _val ) << FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) & \ + FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) + +#define FTMCTRL_MCFG1_IOEN 0x80000U + +#define FTMCTRL_MCFG1_R 0x40000U + +#define FTMCTRL_MCFG1_ROMBANKSZ_SHIFT 14 +#define FTMCTRL_MCFG1_ROMBANKSZ_MASK 0x3c000U +#define FTMCTRL_MCFG1_ROMBANKSZ_GET( _reg ) \ + ( ( ( _reg ) & FTMCTRL_MCFG1_ROMBANKSZ_MASK ) >> \ + FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) +#define FTMCTRL_MCFG1_ROMBANKSZ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG1_ROMBANKSZ_MASK ) | \ + ( ( ( _val ) << FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) & \ + FTMCTRL_MCFG1_ROMBANKSZ_MASK ) ) +#define FTMCTRL_MCFG1_ROMBANKSZ( _val ) \ + ( ( ( _val ) << FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) & \ + FTMCTRL_MCFG1_ROMBANKSZ_MASK ) + +#define FTMCTRL_MCFG1_PWEN 0x800U + +#define FTMCTRL_MCFG1_PROM_WIDTH_SHIFT 8 +#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x300U +#define FTMCTRL_MCFG1_PROM_WIDTH_GET( _reg ) \ + ( ( ( _reg ) & FTMCTRL_MCFG1_PROM_WIDTH_MASK ) >> \ + FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) +#define FTMCTRL_MCFG1_PROM_WIDTH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WIDTH_MASK ) | \ + ( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \ + FTMCTRL_MCFG1_PROM_WIDTH_MASK ) ) +#define FTMCTRL_MCFG1_PROM_WIDTH( _val ) \ + ( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \ + FTMCTRL_MCFG1_PROM_WIDTH_MASK ) + +#define FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT 4 +#define FTMCTRL_MCFG1_PROM_WRITE_WS_MASK 0xf0U +#define FTMCTRL_MCFG1_PROM_WRITE_WS_GET( _reg ) \ + ( ( ( _reg ) & FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) >> \ + FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT ) +#define FTMCTRL_MCFG1_PROM_WRITE_WS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) | \ + ( ( ( _val ) << FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT ) & \ + FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) ) +#define FTMCTRL_MCFG1_PROM_WRITE_WS( _val ) \ + ( ( ( _val ) << FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT ) & \ + FTMCTRL_MCFG1_PROM_WRITE_WS_MASK ) + +#define FTMCTRL_MCFG1_PROM_READ_WS_SHIFT 0 +#define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0xfU +#define FTMCTRL_MCFG1_PROM_READ_WS_GET( _reg ) \ + ( ( ( _reg ) & FTMCTRL_MCFG1_PROM_READ_WS_MASK ) >> \ + FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) +#define FTMCTRL_MCFG1_PROM_READ_WS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_READ_WS_MASK ) | \ + ( ( ( _val ) << FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) & \ + FTMCTRL_MCFG1_PROM_READ_WS_MASK ) ) +#define FTMCTRL_MCFG1_PROM_READ_WS( _val ) \ + ( ( ( _val ) << FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) & \ + FTMCTRL_MCFG1_PROM_READ_WS_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG3 \ + * Memory configuration register 3 (MCFG3) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define FTMCTRL_MCFG3_ME 0x8000000U + +#define FTMCTRL_MCFG3_WB 0x800U + +#define FTMCTRL_MCFG3_RB 0x400U + +#define FTMCTRL_MCFG3_PE 0x100U + +#define FTMCTRL_MCFG3_TCB_SHIFT 0 +#define FTMCTRL_MCFG3_TCB_MASK 0xffU +#define FTMCTRL_MCFG3_TCB_GET( _reg ) \ + ( ( ( _reg ) & FTMCTRL_MCFG3_TCB_MASK ) >> \ + FTMCTRL_MCFG3_TCB_SHIFT ) +#define FTMCTRL_MCFG3_TCB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG3_TCB_MASK ) | \ + ( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & \ + FTMCTRL_MCFG3_TCB_MASK ) ) +#define FTMCTRL_MCFG3_TCB( _val ) \ + ( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & \ + FTMCTRL_MCFG3_TCB_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG5 \ + * Memory configuration register 5 (MCFG5) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define FTMCTRL_MCFG5_IOHWS_SHIFT 23 +#define FTMCTRL_MCFG5_IOHWS_MASK 0x3f800000U +#define FTMCTRL_MCFG5_IOHWS_GET( _reg ) \ + ( ( ( _reg ) & FTMCTRL_MCFG5_IOHWS_MASK ) >> \ + FTMCTRL_MCFG5_IOHWS_SHIFT ) +#define FTMCTRL_MCFG5_IOHWS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG5_IOHWS_MASK ) | \ + ( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & \ + FTMCTRL_MCFG5_IOHWS_MASK ) ) +#define FTMCTRL_MCFG5_IOHWS( _val ) \ + ( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & \ + FTMCTRL_MCFG5_IOHWS_MASK ) + +#define FTMCTRL_MCFG5_ROMHWS_SHIFT 7 +#define FTMCTRL_MCFG5_ROMHWS_MASK 0x3f80U +#define FTMCTRL_MCFG5_ROMHWS_GET( _reg ) \ + ( ( ( _reg ) & FTMCTRL_MCFG5_ROMHWS_MASK ) >> \ + FTMCTRL_MCFG5_ROMHWS_SHIFT ) +#define FTMCTRL_MCFG5_ROMHWS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG5_ROMHWS_MASK ) | \ + ( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & \ + FTMCTRL_MCFG5_ROMHWS_MASK ) ) +#define FTMCTRL_MCFG5_ROMHWS( _val ) \ + ( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & \ + FTMCTRL_MCFG5_ROMHWS_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG7 \ + * Memory configuration register 7 (MCFG7) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define FTMCTRL_MCFG7_BRDYNCNT_SHIFT 16 +#define FTMCTRL_MCFG7_BRDYNCNT_MASK 0xffff0000U +#define FTMCTRL_MCFG7_BRDYNCNT_GET( _reg ) \ + ( ( ( _reg ) & FTMCTRL_MCFG7_BRDYNCNT_MASK ) >> \ + FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) +#define FTMCTRL_MCFG7_BRDYNCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNCNT_MASK ) | \ + ( ( ( _val ) << FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) & \ + FTMCTRL_MCFG7_BRDYNCNT_MASK ) ) +#define FTMCTRL_MCFG7_BRDYNCNT( _val ) \ + ( ( ( _val ) << FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) & \ + FTMCTRL_MCFG7_BRDYNCNT_MASK ) + +#define FTMCTRL_MCFG7_BRDYNRLD_SHIFT 0 +#define FTMCTRL_MCFG7_BRDYNRLD_MASK 0xffffU +#define FTMCTRL_MCFG7_BRDYNRLD_GET( _reg ) \ + ( ( ( _reg ) & FTMCTRL_MCFG7_BRDYNRLD_MASK ) >> \ + FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) +#define FTMCTRL_MCFG7_BRDYNRLD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNRLD_MASK ) | \ + ( ( ( _val ) << FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) & \ + FTMCTRL_MCFG7_BRDYNRLD_MASK ) ) +#define FTMCTRL_MCFG7_BRDYNRLD( _val ) \ + ( ( ( _val ) << FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) & \ + FTMCTRL_MCFG7_BRDYNRLD_MASK ) + +/** @} */ + +/** + * @brief This structure defines the FTMCTRL register block memory map. + */ +typedef struct ftmctrl { + /** + * @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG1. + */ + uint32_t mcfg1; + + uint32_t reserved_4_8; + + /** + * @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG3. + */ + uint32_t mcfg3; + + uint32_t reserved_c_10; + + /** + * @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG5. + */ + uint32_t mcfg5; + + uint32_t reserved_14_18; + + /** + * @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG7. + */ + uint32_t mcfg7; +} ftmctrl; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_FTMCTRL_REGS_H */ diff --git a/bsps/include/grlib/genirq.h b/bsps/include/grlib/genirq.h index 673be173b1..3c99b5a704 100644 --- a/bsps/include/grlib/genirq.h +++ b/bsps/include/grlib/genirq.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* General Shared Interrupt handling function interface * * The functions does not manipulate the IRQ controller or the @@ -8,9 +10,26 @@ * COPYRIGHT (c) 2008. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GENIRQ_H__ diff --git a/bsps/include/grlib/gpiolib.h b/bsps/include/grlib/gpiolib.h index f82d4fa2c2..c0f865fff2 100644 --- a/bsps/include/grlib/gpiolib.h +++ b/bsps/include/grlib/gpiolib.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GPIO Library interface * * COPYRIGHT (c) 2009. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GPIOLIB_H__ @@ -59,7 +78,7 @@ extern int gpiolib_irq_register(void *handle, void *func, void *arg); /*** Driver Interface ***/ struct gpiolib_info { - char devName[64]; + char devName[80]; }; struct gpiolib_drv_ops { diff --git a/bsps/include/grlib/gptimer-regs.h b/bsps/include/grlib/gptimer-regs.h new file mode 100644 index 0000000000..f71343a442 --- /dev/null +++ b/bsps/include/grlib/gptimer-regs.h @@ -0,0 +1,379 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBGPTIMER + * + * @brief This header file defines the GPTIMER register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/gptimer-header */ + +#ifndef _GRLIB_GPTIMER_REGS_H +#define _GRLIB_GPTIMER_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/group */ + +/** + * @defgroup RTEMSDeviceGRLIB GRLIB + * + * @ingroup RTEMSDeviceDrivers + * + * @brief This group contains the GRLIB interfaces. + */ + +/* Generated from spec:/dev/grlib/if/gptimer-timer */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERTimer GPTIMER TIMER + * + * @ingroup RTEMSDeviceGRLIBGPTIMER + * + * @brief This group contains the GPTIMER TIMER interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERTimerTCNTVAL \ + * Timer n counter value register (TCNTVAL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_TCNTVAL_TCVAL_SHIFT 0 +#define GPTIMER_TCNTVAL_TCVAL_MASK 0xffffffffU +#define GPTIMER_TCNTVAL_TCVAL_GET( _reg ) \ + ( ( ( _reg ) & GPTIMER_TCNTVAL_TCVAL_MASK ) >> \ + GPTIMER_TCNTVAL_TCVAL_SHIFT ) +#define GPTIMER_TCNTVAL_TCVAL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_TCNTVAL_TCVAL_MASK ) | \ + ( ( ( _val ) << GPTIMER_TCNTVAL_TCVAL_SHIFT ) & \ + GPTIMER_TCNTVAL_TCVAL_MASK ) ) +#define GPTIMER_TCNTVAL_TCVAL( _val ) \ + ( ( ( _val ) << GPTIMER_TCNTVAL_TCVAL_SHIFT ) & \ + GPTIMER_TCNTVAL_TCVAL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERTimerTRLDVAL \ + * Timer n counter reload value register (TRLDVAL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_TRLDVAL_TRLDVAL_SHIFT 0 +#define GPTIMER_TRLDVAL_TRLDVAL_MASK 0xffffffffU +#define GPTIMER_TRLDVAL_TRLDVAL_GET( _reg ) \ + ( ( ( _reg ) & GPTIMER_TRLDVAL_TRLDVAL_MASK ) >> \ + GPTIMER_TRLDVAL_TRLDVAL_SHIFT ) +#define GPTIMER_TRLDVAL_TRLDVAL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_TRLDVAL_TRLDVAL_MASK ) | \ + ( ( ( _val ) << GPTIMER_TRLDVAL_TRLDVAL_SHIFT ) & \ + GPTIMER_TRLDVAL_TRLDVAL_MASK ) ) +#define GPTIMER_TRLDVAL_TRLDVAL( _val ) \ + ( ( ( _val ) << GPTIMER_TRLDVAL_TRLDVAL_SHIFT ) & \ + GPTIMER_TRLDVAL_TRLDVAL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERTimerTCTRL Timer n control register (TCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_TCTRL_WS 0x100U + +#define GPTIMER_TCTRL_WN 0x80U + +#define GPTIMER_TCTRL_DH 0x40U + +#define GPTIMER_TCTRL_CH 0x20U + +#define GPTIMER_TCTRL_IP 0x10U + +#define GPTIMER_TCTRL_IE 0x8U + +#define GPTIMER_TCTRL_LD 0x4U + +#define GPTIMER_TCTRL_RS 0x2U + +#define GPTIMER_TCTRL_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERTimerTLATCH Timer n latch register (TLATCH) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_TLATCH_LTCV_SHIFT 0 +#define GPTIMER_TLATCH_LTCV_MASK 0xffffffffU +#define GPTIMER_TLATCH_LTCV_GET( _reg ) \ + ( ( ( _reg ) & GPTIMER_TLATCH_LTCV_MASK ) >> \ + GPTIMER_TLATCH_LTCV_SHIFT ) +#define GPTIMER_TLATCH_LTCV_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_TLATCH_LTCV_MASK ) | \ + ( ( ( _val ) << GPTIMER_TLATCH_LTCV_SHIFT ) & \ + GPTIMER_TLATCH_LTCV_MASK ) ) +#define GPTIMER_TLATCH_LTCV( _val ) \ + ( ( ( _val ) << GPTIMER_TLATCH_LTCV_SHIFT ) & \ + GPTIMER_TLATCH_LTCV_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GPTIMER TIMER register block memory map. + */ +typedef struct gptimer_timer { + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTCNTVAL. + */ + uint32_t tcntval; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTRLDVAL. + */ + uint32_t trldval; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTCTRL. + */ + uint32_t tctrl; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTLATCH. + */ + uint32_t tlatch; +} gptimer_timer; + +/** @} */ + +/* Generated from spec:/dev/grlib/if/gptimer */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMER GPTIMER + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GPTIMER interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERSCALER Scaler value register (SCALER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_SCALER_SCALER_SHIFT 0 +#define GPTIMER_SCALER_SCALER_MASK 0xffffU +#define GPTIMER_SCALER_SCALER_GET( _reg ) \ + ( ( ( _reg ) & GPTIMER_SCALER_SCALER_MASK ) >> \ + GPTIMER_SCALER_SCALER_SHIFT ) +#define GPTIMER_SCALER_SCALER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_SCALER_SCALER_MASK ) | \ + ( ( ( _val ) << GPTIMER_SCALER_SCALER_SHIFT ) & \ + GPTIMER_SCALER_SCALER_MASK ) ) +#define GPTIMER_SCALER_SCALER( _val ) \ + ( ( ( _val ) << GPTIMER_SCALER_SCALER_SHIFT ) & \ + GPTIMER_SCALER_SCALER_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERSRELOAD \ + * Scaler reload value register (SRELOAD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_SRELOAD_SRELOAD_SHIFT 0 +#define GPTIMER_SRELOAD_SRELOAD_MASK 0xffffU +#define GPTIMER_SRELOAD_SRELOAD_GET( _reg ) \ + ( ( ( _reg ) & GPTIMER_SRELOAD_SRELOAD_MASK ) >> \ + GPTIMER_SRELOAD_SRELOAD_SHIFT ) +#define GPTIMER_SRELOAD_SRELOAD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_SRELOAD_SRELOAD_MASK ) | \ + ( ( ( _val ) << GPTIMER_SRELOAD_SRELOAD_SHIFT ) & \ + GPTIMER_SRELOAD_SRELOAD_MASK ) ) +#define GPTIMER_SRELOAD_SRELOAD( _val ) \ + ( ( ( _val ) << GPTIMER_SRELOAD_SRELOAD_SHIFT ) & \ + GPTIMER_SRELOAD_SRELOAD_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERCONFIG Configuration register (CONFIG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_CONFIG_EV 0x2000U + +#define GPTIMER_CONFIG_ES 0x1000U + +#define GPTIMER_CONFIG_EL 0x800U + +#define GPTIMER_CONFIG_EE 0x400U + +#define GPTIMER_CONFIG_DF 0x200U + +#define GPTIMER_CONFIG_SI 0x100U + +#define GPTIMER_CONFIG_IRQ_SHIFT 3 +#define GPTIMER_CONFIG_IRQ_MASK 0xf8U +#define GPTIMER_CONFIG_IRQ_GET( _reg ) \ + ( ( ( _reg ) & GPTIMER_CONFIG_IRQ_MASK ) >> \ + GPTIMER_CONFIG_IRQ_SHIFT ) +#define GPTIMER_CONFIG_IRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_CONFIG_IRQ_MASK ) | \ + ( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & \ + GPTIMER_CONFIG_IRQ_MASK ) ) +#define GPTIMER_CONFIG_IRQ( _val ) \ + ( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & \ + GPTIMER_CONFIG_IRQ_MASK ) + +#define GPTIMER_CONFIG_TIMERS_SHIFT 0 +#define GPTIMER_CONFIG_TIMERS_MASK 0x7U +#define GPTIMER_CONFIG_TIMERS_GET( _reg ) \ + ( ( ( _reg ) & GPTIMER_CONFIG_TIMERS_MASK ) >> \ + GPTIMER_CONFIG_TIMERS_SHIFT ) +#define GPTIMER_CONFIG_TIMERS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_CONFIG_TIMERS_MASK ) | \ + ( ( ( _val ) << GPTIMER_CONFIG_TIMERS_SHIFT ) & \ + GPTIMER_CONFIG_TIMERS_MASK ) ) +#define GPTIMER_CONFIG_TIMERS( _val ) \ + ( ( ( _val ) << GPTIMER_CONFIG_TIMERS_SHIFT ) & \ + GPTIMER_CONFIG_TIMERS_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERLATCHCFG \ + * Timer latch configuration register (LATCHCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_LATCHCFG_LATCHSEL_SHIFT 0 +#define GPTIMER_LATCHCFG_LATCHSEL_MASK 0xffffffffU +#define GPTIMER_LATCHCFG_LATCHSEL_GET( _reg ) \ + ( ( ( _reg ) & GPTIMER_LATCHCFG_LATCHSEL_MASK ) >> \ + GPTIMER_LATCHCFG_LATCHSEL_SHIFT ) +#define GPTIMER_LATCHCFG_LATCHSEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GPTIMER_LATCHCFG_LATCHSEL_MASK ) | \ + ( ( ( _val ) << GPTIMER_LATCHCFG_LATCHSEL_SHIFT ) & \ + GPTIMER_LATCHCFG_LATCHSEL_MASK ) ) +#define GPTIMER_LATCHCFG_LATCHSEL( _val ) \ + ( ( ( _val ) << GPTIMER_LATCHCFG_LATCHSEL_SHIFT ) & \ + GPTIMER_LATCHCFG_LATCHSEL_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GPTIMER register block memory map. + */ +typedef struct gptimer { + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERSCALER. + */ + uint32_t scaler; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERSRELOAD. + */ + uint32_t sreload; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERCONFIG. + */ + uint32_t config; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERLATCHCFG. + */ + uint32_t latchcfg; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimer. + */ + gptimer_timer timer[ 15 ]; +} gptimer; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GPTIMER_REGS_H */ diff --git a/bsps/include/grlib/gptimer.h b/bsps/include/grlib/gptimer.h index ee0120d2bd..b5e2c13cbe 100644 --- a/bsps/include/grlib/gptimer.h +++ b/bsps/include/grlib/gptimer.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GPTIMER and GRTIMER timer driver * * COPYRIGHT (c) 2015. * Cobham Gaisler. * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * */ diff --git a/bsps/include/grlib/gr1553b-regs.h b/bsps/include/grlib/gr1553b-regs.h new file mode 100644 index 0000000000..9003a9036c --- /dev/null +++ b/bsps/include/grlib/gr1553b-regs.h @@ -0,0 +1,1393 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGR1553B + * + * @brief This header file defines the GR1553B register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/gr1553b-header */ + +#ifndef _GRLIB_GR1553B_REGS_H +#define _GRLIB_GR1553B_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/gr1553b */ + +/** + * @defgroup RTEMSDeviceGR1553B GR1553B + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GR1553B interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGR1553BIRQ GR1553B IRQ Register (IRQ) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_IRQ_BMTOF 0x20000U + +#define GR1553B_IRQ_BMD 0x10000U + +#define GR1553B_IRQ_RTTE 0x400U + +#define GR1553B_IRQ_RTD 0x200U + +#define GR1553B_IRQ_RTEV 0x100U + +#define GR1553B_IRQ_BCWK 0x4U + +#define GR1553B_IRQ_BCD 0x2U + +#define GR1553B_IRQ_BCEV 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BIRQE GR1553B IRQ Enable Register (IRQE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_IRQE_BMTOE 0x20000U + +#define GR1553B_IRQE_BMDE 0x10000U + +#define GR1553B_IRQE_RTTEE 0x400U + +#define GR1553B_IRQE_RTDE 0x200U + +#define GR1553B_IRQE_RTEVE 0x100U + +#define GR1553B_IRQE_BCWKE 0x4U + +#define GR1553B_IRQE_BCDE 0x2U + +#define GR1553B_IRQE_BCEVE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BHC GR1553B Hardware Configuration Register (HC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_HC_MOD 0x80000000U + +#define GR1553B_HC_CVER 0x1000U + +#define GR1553B_HC_XKEYS 0x800U + +#define GR1553B_HC_ENDIAN_SHIFT 9 +#define GR1553B_HC_ENDIAN_MASK 0x600U +#define GR1553B_HC_ENDIAN_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_HC_ENDIAN_MASK ) >> \ + GR1553B_HC_ENDIAN_SHIFT ) +#define GR1553B_HC_ENDIAN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_HC_ENDIAN_MASK ) | \ + ( ( ( _val ) << GR1553B_HC_ENDIAN_SHIFT ) & \ + GR1553B_HC_ENDIAN_MASK ) ) +#define GR1553B_HC_ENDIAN( _val ) \ + ( ( ( _val ) << GR1553B_HC_ENDIAN_SHIFT ) & \ + GR1553B_HC_ENDIAN_MASK ) + +#define GR1553B_HC_SCLK 0x100U + +#define GR1553B_HC_CCFREQ_SHIFT 0 +#define GR1553B_HC_CCFREQ_MASK 0xffU +#define GR1553B_HC_CCFREQ_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_HC_CCFREQ_MASK ) >> \ + GR1553B_HC_CCFREQ_SHIFT ) +#define GR1553B_HC_CCFREQ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_HC_CCFREQ_MASK ) | \ + ( ( ( _val ) << GR1553B_HC_CCFREQ_SHIFT ) & \ + GR1553B_HC_CCFREQ_MASK ) ) +#define GR1553B_HC_CCFREQ( _val ) \ + ( ( ( _val ) << GR1553B_HC_CCFREQ_SHIFT ) & \ + GR1553B_HC_CCFREQ_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCSC \ + * GR1553B BC Status and Config Register (BCSC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCSC_BCSUP 0x80000000U + +#define GR1553B_BCSC_BCFEAT_SHIFT 28 +#define GR1553B_BCSC_BCFEAT_MASK 0x70000000U +#define GR1553B_BCSC_BCFEAT_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BCSC_BCFEAT_MASK ) >> \ + GR1553B_BCSC_BCFEAT_SHIFT ) +#define GR1553B_BCSC_BCFEAT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCSC_BCFEAT_MASK ) | \ + ( ( ( _val ) << GR1553B_BCSC_BCFEAT_SHIFT ) & \ + GR1553B_BCSC_BCFEAT_MASK ) ) +#define GR1553B_BCSC_BCFEAT( _val ) \ + ( ( ( _val ) << GR1553B_BCSC_BCFEAT_SHIFT ) & \ + GR1553B_BCSC_BCFEAT_MASK ) + +#define GR1553B_BCSC_BCCHK 0x10000U + +#define GR1553B_BCSC_ASADL_SHIFT 11 +#define GR1553B_BCSC_ASADL_MASK 0xf800U +#define GR1553B_BCSC_ASADL_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BCSC_ASADL_MASK ) >> \ + GR1553B_BCSC_ASADL_SHIFT ) +#define GR1553B_BCSC_ASADL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCSC_ASADL_MASK ) | \ + ( ( ( _val ) << GR1553B_BCSC_ASADL_SHIFT ) & \ + GR1553B_BCSC_ASADL_MASK ) ) +#define GR1553B_BCSC_ASADL( _val ) \ + ( ( ( _val ) << GR1553B_BCSC_ASADL_SHIFT ) & \ + GR1553B_BCSC_ASADL_MASK ) + +#define GR1553B_BCSC_ASST_SHIFT 8 +#define GR1553B_BCSC_ASST_MASK 0x300U +#define GR1553B_BCSC_ASST_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BCSC_ASST_MASK ) >> \ + GR1553B_BCSC_ASST_SHIFT ) +#define GR1553B_BCSC_ASST_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCSC_ASST_MASK ) | \ + ( ( ( _val ) << GR1553B_BCSC_ASST_SHIFT ) & \ + GR1553B_BCSC_ASST_MASK ) ) +#define GR1553B_BCSC_ASST( _val ) \ + ( ( ( _val ) << GR1553B_BCSC_ASST_SHIFT ) & \ + GR1553B_BCSC_ASST_MASK ) + +#define GR1553B_BCSC_SCADL_SHIFT 3 +#define GR1553B_BCSC_SCADL_MASK 0xf8U +#define GR1553B_BCSC_SCADL_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BCSC_SCADL_MASK ) >> \ + GR1553B_BCSC_SCADL_SHIFT ) +#define GR1553B_BCSC_SCADL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCSC_SCADL_MASK ) | \ + ( ( ( _val ) << GR1553B_BCSC_SCADL_SHIFT ) & \ + GR1553B_BCSC_SCADL_MASK ) ) +#define GR1553B_BCSC_SCADL( _val ) \ + ( ( ( _val ) << GR1553B_BCSC_SCADL_SHIFT ) & \ + GR1553B_BCSC_SCADL_MASK ) + +#define GR1553B_BCSC_SCST_SHIFT 0 +#define GR1553B_BCSC_SCST_MASK 0x7U +#define GR1553B_BCSC_SCST_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BCSC_SCST_MASK ) >> \ + GR1553B_BCSC_SCST_SHIFT ) +#define GR1553B_BCSC_SCST_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCSC_SCST_MASK ) | \ + ( ( ( _val ) << GR1553B_BCSC_SCST_SHIFT ) & \ + GR1553B_BCSC_SCST_MASK ) ) +#define GR1553B_BCSC_SCST( _val ) \ + ( ( ( _val ) << GR1553B_BCSC_SCST_SHIFT ) & \ + GR1553B_BCSC_SCST_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCA GR1553B BC Action Register (BCA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCA_BCKEY_SHIFT 16 +#define GR1553B_BCA_BCKEY_MASK 0xffff0000U +#define GR1553B_BCA_BCKEY_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BCA_BCKEY_MASK ) >> \ + GR1553B_BCA_BCKEY_SHIFT ) +#define GR1553B_BCA_BCKEY_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCA_BCKEY_MASK ) | \ + ( ( ( _val ) << GR1553B_BCA_BCKEY_SHIFT ) & \ + GR1553B_BCA_BCKEY_MASK ) ) +#define GR1553B_BCA_BCKEY( _val ) \ + ( ( ( _val ) << GR1553B_BCA_BCKEY_SHIFT ) & \ + GR1553B_BCA_BCKEY_MASK ) + +#define GR1553B_BCA_ASSTP 0x200U + +#define GR1553B_BCA_ASSRT 0x100U + +#define GR1553B_BCA_CLRT 0x10U + +#define GR1553B_BCA_SETT 0x8U + +#define GR1553B_BCA_SCSTP 0x4U + +#define GR1553B_BCA_SCSUS 0x2U + +#define GR1553B_BCA_SCSRT 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCTNP \ + * GR1553B BC Transfer list next pointer register (BCTNP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCTNP_POINTER_SHIFT 0 +#define GR1553B_BCTNP_POINTER_MASK 0xffffffffU +#define GR1553B_BCTNP_POINTER_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BCTNP_POINTER_MASK ) >> \ + GR1553B_BCTNP_POINTER_SHIFT ) +#define GR1553B_BCTNP_POINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCTNP_POINTER_MASK ) | \ + ( ( ( _val ) << GR1553B_BCTNP_POINTER_SHIFT ) & \ + GR1553B_BCTNP_POINTER_MASK ) ) +#define GR1553B_BCTNP_POINTER( _val ) \ + ( ( ( _val ) << GR1553B_BCTNP_POINTER_SHIFT ) & \ + GR1553B_BCTNP_POINTER_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCANP \ + * GR1553B BC Asynchronous list next pointer register (BCANP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCANP_POINTER_SHIFT 0 +#define GR1553B_BCANP_POINTER_MASK 0xffffffffU +#define GR1553B_BCANP_POINTER_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BCANP_POINTER_MASK ) >> \ + GR1553B_BCANP_POINTER_SHIFT ) +#define GR1553B_BCANP_POINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCANP_POINTER_MASK ) | \ + ( ( ( _val ) << GR1553B_BCANP_POINTER_SHIFT ) & \ + GR1553B_BCANP_POINTER_MASK ) ) +#define GR1553B_BCANP_POINTER( _val ) \ + ( ( ( _val ) << GR1553B_BCANP_POINTER_SHIFT ) & \ + GR1553B_BCANP_POINTER_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCT GR1553B BC Timer register (BCT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCT_SCTM_SHIFT 0 +#define GR1553B_BCT_SCTM_MASK 0xffffffU +#define GR1553B_BCT_SCTM_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BCT_SCTM_MASK ) >> \ + GR1553B_BCT_SCTM_SHIFT ) +#define GR1553B_BCT_SCTM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCT_SCTM_MASK ) | \ + ( ( ( _val ) << GR1553B_BCT_SCTM_SHIFT ) & \ + GR1553B_BCT_SCTM_MASK ) ) +#define GR1553B_BCT_SCTM( _val ) \ + ( ( ( _val ) << GR1553B_BCT_SCTM_SHIFT ) & \ + GR1553B_BCT_SCTM_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCRP \ + * GR1553B BC Transfer-triggered IRQ ring position register (BCRP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCRP_POSITION_SHIFT 0 +#define GR1553B_BCRP_POSITION_MASK 0xffffffffU +#define GR1553B_BCRP_POSITION_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BCRP_POSITION_MASK ) >> \ + GR1553B_BCRP_POSITION_SHIFT ) +#define GR1553B_BCRP_POSITION_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCRP_POSITION_MASK ) | \ + ( ( ( _val ) << GR1553B_BCRP_POSITION_SHIFT ) & \ + GR1553B_BCRP_POSITION_MASK ) ) +#define GR1553B_BCRP_POSITION( _val ) \ + ( ( ( _val ) << GR1553B_BCRP_POSITION_SHIFT ) & \ + GR1553B_BCRP_POSITION_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCBS GR1553B BC per-RT Bus swap register (BCBS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCBS_SWAP_SHIFT 0 +#define GR1553B_BCBS_SWAP_MASK 0xffffffffU +#define GR1553B_BCBS_SWAP_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BCBS_SWAP_MASK ) >> \ + GR1553B_BCBS_SWAP_SHIFT ) +#define GR1553B_BCBS_SWAP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCBS_SWAP_MASK ) | \ + ( ( ( _val ) << GR1553B_BCBS_SWAP_SHIFT ) & \ + GR1553B_BCBS_SWAP_MASK ) ) +#define GR1553B_BCBS_SWAP( _val ) \ + ( ( ( _val ) << GR1553B_BCBS_SWAP_SHIFT ) & \ + GR1553B_BCBS_SWAP_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCTCP \ + * GR1553B BC Transfer list current slot pointer (BCTCP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCTCP_POINTER_SHIFT 0 +#define GR1553B_BCTCP_POINTER_MASK 0xffffffffU +#define GR1553B_BCTCP_POINTER_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BCTCP_POINTER_MASK ) >> \ + GR1553B_BCTCP_POINTER_SHIFT ) +#define GR1553B_BCTCP_POINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCTCP_POINTER_MASK ) | \ + ( ( ( _val ) << GR1553B_BCTCP_POINTER_SHIFT ) & \ + GR1553B_BCTCP_POINTER_MASK ) ) +#define GR1553B_BCTCP_POINTER( _val ) \ + ( ( ( _val ) << GR1553B_BCTCP_POINTER_SHIFT ) & \ + GR1553B_BCTCP_POINTER_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCACP \ + * GR1553B BC Asynchronous list current slot pointer (BCACP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCACP_POINTER_SHIFT 0 +#define GR1553B_BCACP_POINTER_MASK 0xffffffffU +#define GR1553B_BCACP_POINTER_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BCACP_POINTER_MASK ) >> \ + GR1553B_BCACP_POINTER_SHIFT ) +#define GR1553B_BCACP_POINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BCACP_POINTER_MASK ) | \ + ( ( ( _val ) << GR1553B_BCACP_POINTER_SHIFT ) & \ + GR1553B_BCACP_POINTER_MASK ) ) +#define GR1553B_BCACP_POINTER( _val ) \ + ( ( ( _val ) << GR1553B_BCACP_POINTER_SHIFT ) & \ + GR1553B_BCACP_POINTER_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTS GR1553B RT Status register (RTS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTS_RTSUP 0x80000000U + +#define GR1553B_RTS_ACT 0x8U + +#define GR1553B_RTS_SHDA 0x4U + +#define GR1553B_RTS_SHDB 0x2U + +#define GR1553B_RTS_RUN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTC GR1553B RT Config register (RTC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTC_RTKEY_SHIFT 16 +#define GR1553B_RTC_RTKEY_MASK 0xffff0000U +#define GR1553B_RTC_RTKEY_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTC_RTKEY_MASK ) >> \ + GR1553B_RTC_RTKEY_SHIFT ) +#define GR1553B_RTC_RTKEY_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTC_RTKEY_MASK ) | \ + ( ( ( _val ) << GR1553B_RTC_RTKEY_SHIFT ) & \ + GR1553B_RTC_RTKEY_MASK ) ) +#define GR1553B_RTC_RTKEY( _val ) \ + ( ( ( _val ) << GR1553B_RTC_RTKEY_SHIFT ) & \ + GR1553B_RTC_RTKEY_MASK ) + +#define GR1553B_RTC_SYS 0x8000U + +#define GR1553B_RTC_SYDS 0x4000U + +#define GR1553B_RTC_BRS 0x2000U + +#define GR1553B_RTC_RTEIS 0x40U + +#define GR1553B_RTC_RTADDR_SHIFT 1 +#define GR1553B_RTC_RTADDR_MASK 0x3eU +#define GR1553B_RTC_RTADDR_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTC_RTADDR_MASK ) >> \ + GR1553B_RTC_RTADDR_SHIFT ) +#define GR1553B_RTC_RTADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTC_RTADDR_MASK ) | \ + ( ( ( _val ) << GR1553B_RTC_RTADDR_SHIFT ) & \ + GR1553B_RTC_RTADDR_MASK ) ) +#define GR1553B_RTC_RTADDR( _val ) \ + ( ( ( _val ) << GR1553B_RTC_RTADDR_SHIFT ) & \ + GR1553B_RTC_RTADDR_MASK ) + +#define GR1553B_RTC_RTEN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTBS GR1553B RT Bus status register (RTBS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTBS_TFDE 0x100U + +#define GR1553B_RTBS_SREQ 0x10U + +#define GR1553B_RTBS_BUSY 0x8U + +#define GR1553B_RTBS_SSF 0x4U + +#define GR1553B_RTBS_DBCA 0x2U + +#define GR1553B_RTBS_TFLG 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTSW GR1553B RT Status words register (RTSW) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTSW_BITW_SHIFT 16 +#define GR1553B_RTSW_BITW_MASK 0xffff0000U +#define GR1553B_RTSW_BITW_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTSW_BITW_MASK ) >> \ + GR1553B_RTSW_BITW_SHIFT ) +#define GR1553B_RTSW_BITW_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTSW_BITW_MASK ) | \ + ( ( ( _val ) << GR1553B_RTSW_BITW_SHIFT ) & \ + GR1553B_RTSW_BITW_MASK ) ) +#define GR1553B_RTSW_BITW( _val ) \ + ( ( ( _val ) << GR1553B_RTSW_BITW_SHIFT ) & \ + GR1553B_RTSW_BITW_MASK ) + +#define GR1553B_RTSW_VECW_SHIFT 0 +#define GR1553B_RTSW_VECW_MASK 0xffffU +#define GR1553B_RTSW_VECW_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTSW_VECW_MASK ) >> \ + GR1553B_RTSW_VECW_SHIFT ) +#define GR1553B_RTSW_VECW_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTSW_VECW_MASK ) | \ + ( ( ( _val ) << GR1553B_RTSW_VECW_SHIFT ) & \ + GR1553B_RTSW_VECW_MASK ) ) +#define GR1553B_RTSW_VECW( _val ) \ + ( ( ( _val ) << GR1553B_RTSW_VECW_SHIFT ) & \ + GR1553B_RTSW_VECW_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTSY GR1553B RT Sync register (RTSY) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTSY_SYTM_SHIFT 16 +#define GR1553B_RTSY_SYTM_MASK 0xffff0000U +#define GR1553B_RTSY_SYTM_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTSY_SYTM_MASK ) >> \ + GR1553B_RTSY_SYTM_SHIFT ) +#define GR1553B_RTSY_SYTM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTSY_SYTM_MASK ) | \ + ( ( ( _val ) << GR1553B_RTSY_SYTM_SHIFT ) & \ + GR1553B_RTSY_SYTM_MASK ) ) +#define GR1553B_RTSY_SYTM( _val ) \ + ( ( ( _val ) << GR1553B_RTSY_SYTM_SHIFT ) & \ + GR1553B_RTSY_SYTM_MASK ) + +#define GR1553B_RTSY_SYD_SHIFT 0 +#define GR1553B_RTSY_SYD_MASK 0xffffU +#define GR1553B_RTSY_SYD_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTSY_SYD_MASK ) >> \ + GR1553B_RTSY_SYD_SHIFT ) +#define GR1553B_RTSY_SYD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTSY_SYD_MASK ) | \ + ( ( ( _val ) << GR1553B_RTSY_SYD_SHIFT ) & \ + GR1553B_RTSY_SYD_MASK ) ) +#define GR1553B_RTSY_SYD( _val ) \ + ( ( ( _val ) << GR1553B_RTSY_SYD_SHIFT ) & \ + GR1553B_RTSY_SYD_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTSTBA \ + * GR1553B RT Subaddress table base address register (RTSTBA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTSTBA_SATB_SHIFT 9 +#define GR1553B_RTSTBA_SATB_MASK 0xfffffe00U +#define GR1553B_RTSTBA_SATB_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTSTBA_SATB_MASK ) >> \ + GR1553B_RTSTBA_SATB_SHIFT ) +#define GR1553B_RTSTBA_SATB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTSTBA_SATB_MASK ) | \ + ( ( ( _val ) << GR1553B_RTSTBA_SATB_SHIFT ) & \ + GR1553B_RTSTBA_SATB_MASK ) ) +#define GR1553B_RTSTBA_SATB( _val ) \ + ( ( ( _val ) << GR1553B_RTSTBA_SATB_SHIFT ) & \ + GR1553B_RTSTBA_SATB_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTMCC \ + * GR1553B RT Mode code control register (RTMCC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTMCC_RRTB_SHIFT 28 +#define GR1553B_RTMCC_RRTB_MASK 0x30000000U +#define GR1553B_RTMCC_RRTB_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_RRTB_MASK ) >> \ + GR1553B_RTMCC_RRTB_SHIFT ) +#define GR1553B_RTMCC_RRTB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_RRTB_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_RRTB_SHIFT ) & \ + GR1553B_RTMCC_RRTB_MASK ) ) +#define GR1553B_RTMCC_RRTB( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_RRTB_SHIFT ) & \ + GR1553B_RTMCC_RRTB_MASK ) + +#define GR1553B_RTMCC_RRT_SHIFT 26 +#define GR1553B_RTMCC_RRT_MASK 0xc000000U +#define GR1553B_RTMCC_RRT_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_RRT_MASK ) >> \ + GR1553B_RTMCC_RRT_SHIFT ) +#define GR1553B_RTMCC_RRT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_RRT_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_RRT_SHIFT ) & \ + GR1553B_RTMCC_RRT_MASK ) ) +#define GR1553B_RTMCC_RRT( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_RRT_SHIFT ) & \ + GR1553B_RTMCC_RRT_MASK ) + +#define GR1553B_RTMCC_ITFB_SHIFT 24 +#define GR1553B_RTMCC_ITFB_MASK 0x3000000U +#define GR1553B_RTMCC_ITFB_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_ITFB_MASK ) >> \ + GR1553B_RTMCC_ITFB_SHIFT ) +#define GR1553B_RTMCC_ITFB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_ITFB_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_ITFB_SHIFT ) & \ + GR1553B_RTMCC_ITFB_MASK ) ) +#define GR1553B_RTMCC_ITFB( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_ITFB_SHIFT ) & \ + GR1553B_RTMCC_ITFB_MASK ) + +#define GR1553B_RTMCC_ITF_SHIFT 22 +#define GR1553B_RTMCC_ITF_MASK 0xc00000U +#define GR1553B_RTMCC_ITF_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_ITF_MASK ) >> \ + GR1553B_RTMCC_ITF_SHIFT ) +#define GR1553B_RTMCC_ITF_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_ITF_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_ITF_SHIFT ) & \ + GR1553B_RTMCC_ITF_MASK ) ) +#define GR1553B_RTMCC_ITF( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_ITF_SHIFT ) & \ + GR1553B_RTMCC_ITF_MASK ) + +#define GR1553B_RTMCC_ISTB_SHIFT 20 +#define GR1553B_RTMCC_ISTB_MASK 0x300000U +#define GR1553B_RTMCC_ISTB_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_ISTB_MASK ) >> \ + GR1553B_RTMCC_ISTB_SHIFT ) +#define GR1553B_RTMCC_ISTB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_ISTB_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_ISTB_SHIFT ) & \ + GR1553B_RTMCC_ISTB_MASK ) ) +#define GR1553B_RTMCC_ISTB( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_ISTB_SHIFT ) & \ + GR1553B_RTMCC_ISTB_MASK ) + +#define GR1553B_RTMCC_IST_SHIFT 18 +#define GR1553B_RTMCC_IST_MASK 0xc0000U +#define GR1553B_RTMCC_IST_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_IST_MASK ) >> \ + GR1553B_RTMCC_IST_SHIFT ) +#define GR1553B_RTMCC_IST_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_IST_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_IST_SHIFT ) & \ + GR1553B_RTMCC_IST_MASK ) ) +#define GR1553B_RTMCC_IST( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_IST_SHIFT ) & \ + GR1553B_RTMCC_IST_MASK ) + +#define GR1553B_RTMCC_DBC_SHIFT 16 +#define GR1553B_RTMCC_DBC_MASK 0x30000U +#define GR1553B_RTMCC_DBC_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_DBC_MASK ) >> \ + GR1553B_RTMCC_DBC_SHIFT ) +#define GR1553B_RTMCC_DBC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_DBC_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_DBC_SHIFT ) & \ + GR1553B_RTMCC_DBC_MASK ) ) +#define GR1553B_RTMCC_DBC( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_DBC_SHIFT ) & \ + GR1553B_RTMCC_DBC_MASK ) + +#define GR1553B_RTMCC_TBW_SHIFT 14 +#define GR1553B_RTMCC_TBW_MASK 0xc000U +#define GR1553B_RTMCC_TBW_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_TBW_MASK ) >> \ + GR1553B_RTMCC_TBW_SHIFT ) +#define GR1553B_RTMCC_TBW_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_TBW_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_TBW_SHIFT ) & \ + GR1553B_RTMCC_TBW_MASK ) ) +#define GR1553B_RTMCC_TBW( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_TBW_SHIFT ) & \ + GR1553B_RTMCC_TBW_MASK ) + +#define GR1553B_RTMCC_TVW_SHIFT 12 +#define GR1553B_RTMCC_TVW_MASK 0x3000U +#define GR1553B_RTMCC_TVW_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_TVW_MASK ) >> \ + GR1553B_RTMCC_TVW_SHIFT ) +#define GR1553B_RTMCC_TVW_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_TVW_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_TVW_SHIFT ) & \ + GR1553B_RTMCC_TVW_MASK ) ) +#define GR1553B_RTMCC_TVW( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_TVW_SHIFT ) & \ + GR1553B_RTMCC_TVW_MASK ) + +#define GR1553B_RTMCC_TSB_SHIFT 10 +#define GR1553B_RTMCC_TSB_MASK 0xc00U +#define GR1553B_RTMCC_TSB_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_TSB_MASK ) >> \ + GR1553B_RTMCC_TSB_SHIFT ) +#define GR1553B_RTMCC_TSB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_TSB_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_TSB_SHIFT ) & \ + GR1553B_RTMCC_TSB_MASK ) ) +#define GR1553B_RTMCC_TSB( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_TSB_SHIFT ) & \ + GR1553B_RTMCC_TSB_MASK ) + +#define GR1553B_RTMCC_TS_SHIFT 8 +#define GR1553B_RTMCC_TS_MASK 0x300U +#define GR1553B_RTMCC_TS_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_TS_MASK ) >> \ + GR1553B_RTMCC_TS_SHIFT ) +#define GR1553B_RTMCC_TS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_TS_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_TS_SHIFT ) & \ + GR1553B_RTMCC_TS_MASK ) ) +#define GR1553B_RTMCC_TS( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_TS_SHIFT ) & \ + GR1553B_RTMCC_TS_MASK ) + +#define GR1553B_RTMCC_SDB_SHIFT 6 +#define GR1553B_RTMCC_SDB_MASK 0xc0U +#define GR1553B_RTMCC_SDB_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_SDB_MASK ) >> \ + GR1553B_RTMCC_SDB_SHIFT ) +#define GR1553B_RTMCC_SDB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_SDB_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_SDB_SHIFT ) & \ + GR1553B_RTMCC_SDB_MASK ) ) +#define GR1553B_RTMCC_SDB( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_SDB_SHIFT ) & \ + GR1553B_RTMCC_SDB_MASK ) + +#define GR1553B_RTMCC_SD_SHIFT 4 +#define GR1553B_RTMCC_SD_MASK 0x30U +#define GR1553B_RTMCC_SD_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_SD_MASK ) >> \ + GR1553B_RTMCC_SD_SHIFT ) +#define GR1553B_RTMCC_SD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_SD_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_SD_SHIFT ) & \ + GR1553B_RTMCC_SD_MASK ) ) +#define GR1553B_RTMCC_SD( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_SD_SHIFT ) & \ + GR1553B_RTMCC_SD_MASK ) + +#define GR1553B_RTMCC_SB_SHIFT 2 +#define GR1553B_RTMCC_SB_MASK 0xcU +#define GR1553B_RTMCC_SB_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_SB_MASK ) >> \ + GR1553B_RTMCC_SB_SHIFT ) +#define GR1553B_RTMCC_SB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_SB_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_SB_SHIFT ) & \ + GR1553B_RTMCC_SB_MASK ) ) +#define GR1553B_RTMCC_SB( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_SB_SHIFT ) & \ + GR1553B_RTMCC_SB_MASK ) + +#define GR1553B_RTMCC_S_SHIFT 0 +#define GR1553B_RTMCC_S_MASK 0x3U +#define GR1553B_RTMCC_S_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTMCC_S_MASK ) >> \ + GR1553B_RTMCC_S_SHIFT ) +#define GR1553B_RTMCC_S_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTMCC_S_MASK ) | \ + ( ( ( _val ) << GR1553B_RTMCC_S_SHIFT ) & \ + GR1553B_RTMCC_S_MASK ) ) +#define GR1553B_RTMCC_S( _val ) \ + ( ( ( _val ) << GR1553B_RTMCC_S_SHIFT ) & \ + GR1553B_RTMCC_S_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTTTC \ + * GR1553B RT Time tag control register (RTTTC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTTTC_TRES_SHIFT 16 +#define GR1553B_RTTTC_TRES_MASK 0xffff0000U +#define GR1553B_RTTTC_TRES_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTTTC_TRES_MASK ) >> \ + GR1553B_RTTTC_TRES_SHIFT ) +#define GR1553B_RTTTC_TRES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTTTC_TRES_MASK ) | \ + ( ( ( _val ) << GR1553B_RTTTC_TRES_SHIFT ) & \ + GR1553B_RTTTC_TRES_MASK ) ) +#define GR1553B_RTTTC_TRES( _val ) \ + ( ( ( _val ) << GR1553B_RTTTC_TRES_SHIFT ) & \ + GR1553B_RTTTC_TRES_MASK ) + +#define GR1553B_RTTTC_TVAL_SHIFT 0 +#define GR1553B_RTTTC_TVAL_MASK 0xffffU +#define GR1553B_RTTTC_TVAL_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTTTC_TVAL_MASK ) >> \ + GR1553B_RTTTC_TVAL_SHIFT ) +#define GR1553B_RTTTC_TVAL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTTTC_TVAL_MASK ) | \ + ( ( ( _val ) << GR1553B_RTTTC_TVAL_SHIFT ) & \ + GR1553B_RTTTC_TVAL_MASK ) ) +#define GR1553B_RTTTC_TVAL( _val ) \ + ( ( ( _val ) << GR1553B_RTTTC_TVAL_SHIFT ) & \ + GR1553B_RTTTC_TVAL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTELM \ + * GR1553B RT Event log size mask register (RTELM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTELM_MASK_SHIFT 0 +#define GR1553B_RTELM_MASK_MASK 0xffffffffU +#define GR1553B_RTELM_MASK_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTELM_MASK_MASK ) >> \ + GR1553B_RTELM_MASK_SHIFT ) +#define GR1553B_RTELM_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTELM_MASK_MASK ) | \ + ( ( ( _val ) << GR1553B_RTELM_MASK_SHIFT ) & \ + GR1553B_RTELM_MASK_MASK ) ) +#define GR1553B_RTELM_MASK( _val ) \ + ( ( ( _val ) << GR1553B_RTELM_MASK_SHIFT ) & \ + GR1553B_RTELM_MASK_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTELP \ + * GR1553B RT Event log position register (RTELP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTELP_POINTER_SHIFT 0 +#define GR1553B_RTELP_POINTER_MASK 0xffffffffU +#define GR1553B_RTELP_POINTER_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTELP_POINTER_MASK ) >> \ + GR1553B_RTELP_POINTER_SHIFT ) +#define GR1553B_RTELP_POINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTELP_POINTER_MASK ) | \ + ( ( ( _val ) << GR1553B_RTELP_POINTER_SHIFT ) & \ + GR1553B_RTELP_POINTER_MASK ) ) +#define GR1553B_RTELP_POINTER( _val ) \ + ( ( ( _val ) << GR1553B_RTELP_POINTER_SHIFT ) & \ + GR1553B_RTELP_POINTER_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTELIP \ + * GR1553B RT Event Log interrupt position register (RTELIP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTELIP_POINTER_SHIFT 0 +#define GR1553B_RTELIP_POINTER_MASK 0xffffffffU +#define GR1553B_RTELIP_POINTER_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_RTELIP_POINTER_MASK ) >> \ + GR1553B_RTELIP_POINTER_SHIFT ) +#define GR1553B_RTELIP_POINTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_RTELIP_POINTER_MASK ) | \ + ( ( ( _val ) << GR1553B_RTELIP_POINTER_SHIFT ) & \ + GR1553B_RTELIP_POINTER_MASK ) ) +#define GR1553B_RTELIP_POINTER( _val ) \ + ( ( ( _val ) << GR1553B_RTELIP_POINTER_SHIFT ) & \ + GR1553B_RTELIP_POINTER_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMS GR1553B BM Status register (BMS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMS_BMSUP 0x80000000U + +#define GR1553B_BMS_KEYEN 0x40000000U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMC GR1553B BM Control register (BMC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMC_BMKEY_SHIFT 16 +#define GR1553B_BMC_BMKEY_MASK 0xffff0000U +#define GR1553B_BMC_BMKEY_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BMC_BMKEY_MASK ) >> \ + GR1553B_BMC_BMKEY_SHIFT ) +#define GR1553B_BMC_BMKEY_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BMC_BMKEY_MASK ) | \ + ( ( ( _val ) << GR1553B_BMC_BMKEY_SHIFT ) & \ + GR1553B_BMC_BMKEY_MASK ) ) +#define GR1553B_BMC_BMKEY( _val ) \ + ( ( ( _val ) << GR1553B_BMC_BMKEY_SHIFT ) & \ + GR1553B_BMC_BMKEY_MASK ) + +#define GR1553B_BMC_WRSTP 0x20U + +#define GR1553B_BMC_EXST 0x10U + +#define GR1553B_BMC_IMCL 0x8U + +#define GR1553B_BMC_UDWL 0x4U + +#define GR1553B_BMC_MANL 0x2U + +#define GR1553B_BMC_BMEN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMRTAF \ + * GR1553B BM RT Address filter register (BMRTAF) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMRTAF_MASK_SHIFT 0 +#define GR1553B_BMRTAF_MASK_MASK 0xffffffffU +#define GR1553B_BMRTAF_MASK_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BMRTAF_MASK_MASK ) >> \ + GR1553B_BMRTAF_MASK_SHIFT ) +#define GR1553B_BMRTAF_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BMRTAF_MASK_MASK ) | \ + ( ( ( _val ) << GR1553B_BMRTAF_MASK_SHIFT ) & \ + GR1553B_BMRTAF_MASK_MASK ) ) +#define GR1553B_BMRTAF_MASK( _val ) \ + ( ( ( _val ) << GR1553B_BMRTAF_MASK_SHIFT ) & \ + GR1553B_BMRTAF_MASK_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMRTSF \ + * GR1553B BM RT Subaddress filter register (BMRTSF) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMRTSF_MASK_SHIFT 0 +#define GR1553B_BMRTSF_MASK_MASK 0xffffffffU +#define GR1553B_BMRTSF_MASK_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BMRTSF_MASK_MASK ) >> \ + GR1553B_BMRTSF_MASK_SHIFT ) +#define GR1553B_BMRTSF_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BMRTSF_MASK_MASK ) | \ + ( ( ( _val ) << GR1553B_BMRTSF_MASK_SHIFT ) & \ + GR1553B_BMRTSF_MASK_MASK ) ) +#define GR1553B_BMRTSF_MASK( _val ) \ + ( ( ( _val ) << GR1553B_BMRTSF_MASK_SHIFT ) & \ + GR1553B_BMRTSF_MASK_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMRTMC \ + * GR1553B BM RT Mode code filter register (BMRTMC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMRTMC_STSB 0x40000U + +#define GR1553B_BMRTMC_STS 0x20000U + +#define GR1553B_BMRTMC_TLC 0x10000U + +#define GR1553B_BMRTMC_TSW 0x8000U + +#define GR1553B_BMRTMC_RRTB 0x4000U + +#define GR1553B_BMRTMC_RRT 0x2000U + +#define GR1553B_BMRTMC_ITFB 0x1000U + +#define GR1553B_BMRTMC_ITF 0x800U + +#define GR1553B_BMRTMC_ISTB 0x400U + +#define GR1553B_BMRTMC_IST 0x200U + +#define GR1553B_BMRTMC_DBC 0x100U + +#define GR1553B_BMRTMC_TBW 0x80U + +#define GR1553B_BMRTMC_TVW 0x40U + +#define GR1553B_BMRTMC_TSB 0x20U + +#define GR1553B_BMRTMC_TS 0x10U + +#define GR1553B_BMRTMC_SDB 0x8U + +#define GR1553B_BMRTMC_SD 0x4U + +#define GR1553B_BMRTMC_SB 0x2U + +#define GR1553B_BMRTMC_S 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMLBS GR1553B BM Log buffer start (BMLBS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMLBS_START_SHIFT 0 +#define GR1553B_BMLBS_START_MASK 0xffffffffU +#define GR1553B_BMLBS_START_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BMLBS_START_MASK ) >> \ + GR1553B_BMLBS_START_SHIFT ) +#define GR1553B_BMLBS_START_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BMLBS_START_MASK ) | \ + ( ( ( _val ) << GR1553B_BMLBS_START_SHIFT ) & \ + GR1553B_BMLBS_START_MASK ) ) +#define GR1553B_BMLBS_START( _val ) \ + ( ( ( _val ) << GR1553B_BMLBS_START_SHIFT ) & \ + GR1553B_BMLBS_START_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMLBE GR1553B BM Log buffer end (BMLBE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMLBE_END_SHIFT 0 +#define GR1553B_BMLBE_END_MASK 0xffffffffU +#define GR1553B_BMLBE_END_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BMLBE_END_MASK ) >> \ + GR1553B_BMLBE_END_SHIFT ) +#define GR1553B_BMLBE_END_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BMLBE_END_MASK ) | \ + ( ( ( _val ) << GR1553B_BMLBE_END_SHIFT ) & \ + GR1553B_BMLBE_END_MASK ) ) +#define GR1553B_BMLBE_END( _val ) \ + ( ( ( _val ) << GR1553B_BMLBE_END_SHIFT ) & \ + GR1553B_BMLBE_END_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMLBP GR1553B BM Log buffer position (BMLBP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMLBP_POSITION_SHIFT 0 +#define GR1553B_BMLBP_POSITION_MASK 0xffffffffU +#define GR1553B_BMLBP_POSITION_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BMLBP_POSITION_MASK ) >> \ + GR1553B_BMLBP_POSITION_SHIFT ) +#define GR1553B_BMLBP_POSITION_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BMLBP_POSITION_MASK ) | \ + ( ( ( _val ) << GR1553B_BMLBP_POSITION_SHIFT ) & \ + GR1553B_BMLBP_POSITION_MASK ) ) +#define GR1553B_BMLBP_POSITION( _val ) \ + ( ( ( _val ) << GR1553B_BMLBP_POSITION_SHIFT ) & \ + GR1553B_BMLBP_POSITION_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMTTC \ + * GR1553B BM Time tag control register (BMTTC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMTTC_TRES_SHIFT 24 +#define GR1553B_BMTTC_TRES_MASK 0xff000000U +#define GR1553B_BMTTC_TRES_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BMTTC_TRES_MASK ) >> \ + GR1553B_BMTTC_TRES_SHIFT ) +#define GR1553B_BMTTC_TRES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BMTTC_TRES_MASK ) | \ + ( ( ( _val ) << GR1553B_BMTTC_TRES_SHIFT ) & \ + GR1553B_BMTTC_TRES_MASK ) ) +#define GR1553B_BMTTC_TRES( _val ) \ + ( ( ( _val ) << GR1553B_BMTTC_TRES_SHIFT ) & \ + GR1553B_BMTTC_TRES_MASK ) + +#define GR1553B_BMTTC_TVAL_SHIFT 0 +#define GR1553B_BMTTC_TVAL_MASK 0xffffffU +#define GR1553B_BMTTC_TVAL_GET( _reg ) \ + ( ( ( _reg ) & GR1553B_BMTTC_TVAL_MASK ) >> \ + GR1553B_BMTTC_TVAL_SHIFT ) +#define GR1553B_BMTTC_TVAL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR1553B_BMTTC_TVAL_MASK ) | \ + ( ( ( _val ) << GR1553B_BMTTC_TVAL_SHIFT ) & \ + GR1553B_BMTTC_TVAL_MASK ) ) +#define GR1553B_BMTTC_TVAL( _val ) \ + ( ( ( _val ) << GR1553B_BMTTC_TVAL_SHIFT ) & \ + GR1553B_BMTTC_TVAL_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GR1553B register block memory map. + */ +typedef struct gr1553b { + /** + * @brief See @ref RTEMSDeviceGR1553BIRQ. + */ + uint32_t irq; + + /** + * @brief See @ref RTEMSDeviceGR1553BIRQE. + */ + uint32_t irqe; + + uint32_t reserved_8_10[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGR1553BHC. + */ + uint32_t hc; + + uint32_t reserved_14_40[ 11 ]; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCSC. + */ + uint32_t bcsc; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCA. + */ + uint32_t bca; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCTNP. + */ + uint32_t bctnp; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCANP. + */ + uint32_t bcanp; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCT. + */ + uint32_t bct; + + uint32_t reserved_54_58; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCRP. + */ + uint32_t bcrp; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCBS. + */ + uint32_t bcbs; + + uint32_t reserved_60_68[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCTCP. + */ + uint32_t bctcp; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCACP. + */ + uint32_t bcacp; + + uint32_t reserved_70_80[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTS. + */ + uint32_t rts; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTC. + */ + uint32_t rtc; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTBS. + */ + uint32_t rtbs; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTSW. + */ + uint32_t rtsw; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTSY. + */ + uint32_t rtsy; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTSTBA. + */ + uint32_t rtstba; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTMCC. + */ + uint32_t rtmcc; + + uint32_t reserved_9c_a4[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTTTC. + */ + uint32_t rtttc; + + uint32_t reserved_a8_ac; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTELM. + */ + uint32_t rtelm; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTELP. + */ + uint32_t rtelp; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTELIP. + */ + uint32_t rtelip; + + uint32_t reserved_b8_c0[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMS. + */ + uint32_t bms; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMC. + */ + uint32_t bmc; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMRTAF. + */ + uint32_t bmrtaf; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMRTSF. + */ + uint32_t bmrtsf; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMRTMC. + */ + uint32_t bmrtmc; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMLBS. + */ + uint32_t bmlbs; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMLBE. + */ + uint32_t bmlbe; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMLBP. + */ + uint32_t bmlbp; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMTTC. + */ + uint32_t bmttc; +} gr1553b; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GR1553B_REGS_H */ diff --git a/bsps/include/grlib/gr1553b.h b/bsps/include/grlib/gr1553b.h index 006417b530..178a0ae19d 100644 --- a/bsps/include/grlib/gr1553b.h +++ b/bsps/include/grlib/gr1553b.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GR1553B driver, used by BC, RT and/or BM driver * * COPYRIGHT (c) 2010. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * * OVERVIEW * ======== diff --git a/bsps/include/grlib/gr1553bc.h b/bsps/include/grlib/gr1553bc.h index caf6f77722..55f7e1a48a 100644 --- a/bsps/include/grlib/gr1553bc.h +++ b/bsps/include/grlib/gr1553bc.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GR1553B BC driver * * COPYRIGHT (c) 2010. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * * OVERVIEW * ======== diff --git a/bsps/include/grlib/gr1553bc_list.h b/bsps/include/grlib/gr1553bc_list.h index 5024923968..1290eeb778 100644 --- a/bsps/include/grlib/gr1553bc_list.h +++ b/bsps/include/grlib/gr1553bc_list.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * GR1553B BC driver, Descriptor LIST handling * * COPYRIGHT (c) 2010. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GR1553BC_LIST_H__ diff --git a/bsps/include/grlib/gr1553bm.h b/bsps/include/grlib/gr1553bm.h index 058bc59a45..6cb15fd1e5 100644 --- a/bsps/include/grlib/gr1553bm.h +++ b/bsps/include/grlib/gr1553bm.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GR1553B BM driver * * COPYRIGHT (c) 2010. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GR1553BM_H__ diff --git a/bsps/include/grlib/gr1553rt.h b/bsps/include/grlib/gr1553rt.h index 5d52e84c11..b35f767653 100644 --- a/bsps/include/grlib/gr1553rt.h +++ b/bsps/include/grlib/gr1553rt.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GR1553B RT driver * * COPYRIGHT (c) 2010. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GR1553RT_H__ diff --git a/bsps/include/grlib/gr_701.h b/bsps/include/grlib/gr_701.h index acfd9237a2..bee42fbe96 100644 --- a/bsps/include/grlib/gr_701.h +++ b/bsps/include/grlib/gr_701.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GR-701 PCI Target driver. * * COPYRIGHT (c) 2008. @@ -10,9 +12,26 @@ * Driver resources for the AMBA PnP bus provided can be set using * gr701_set_resources(). * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GR_701_H__ diff --git a/bsps/include/grlib/gr_cpci_gr740.h b/bsps/include/grlib/gr_cpci_gr740.h index 55c28acb4c..6402bf6c6d 100644 --- a/bsps/include/grlib/gr_cpci_gr740.h +++ b/bsps/include/grlib/gr_cpci_gr740.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GR-CPCI-GR740 PCI Peripheral driver * * COPYRIGHT (c) 2017. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * * Configures the GR-CPIC-GR740 interface PCI board in peripheral * mode. This driver provides a AMBA PnP bus by using the general part diff --git a/bsps/include/grlib/gr_rasta_adcdac.h b/bsps/include/grlib/gr_rasta_adcdac.h index 9e16cab96b..e1512f2fb0 100644 --- a/bsps/include/grlib/gr_rasta_adcdac.h +++ b/bsps/include/grlib/gr_rasta_adcdac.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GR-RASTA-ADCDAC PCI Target driver. * * COPYRIGHT (c) 2008. @@ -10,9 +12,26 @@ * Driver resources for the AMBA PnP bus provided can be set using * gr_rasta_adcdac_set_resources(). * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GR_RASTA_ADCDAC_H__ diff --git a/bsps/include/grlib/gr_rasta_io.h b/bsps/include/grlib/gr_rasta_io.h index 72a44f5151..ffadf93c9e 100644 --- a/bsps/include/grlib/gr_rasta_io.h +++ b/bsps/include/grlib/gr_rasta_io.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GR-RASTA-IO PCI Target driver. * * COPYRIGHT (c) 2008. @@ -10,9 +12,26 @@ * Driver resources for the AMBA PnP bus provided can be set using * gr_rasta_io_set_resources(). * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GR_RASTA_IO_H__ diff --git a/bsps/include/grlib/gr_rasta_spw_router.h b/bsps/include/grlib/gr_rasta_spw_router.h index 1cc9e41979..15deacd7a2 100644 --- a/bsps/include/grlib/gr_rasta_spw_router.h +++ b/bsps/include/grlib/gr_rasta_spw_router.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GR-RASTA-SPW-ROUTER PCI Peripheral driver * * COPYRIGHT (c) 2015. * Cobham Gaisler. * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * */ diff --git a/bsps/include/grlib/gr_rasta_tmtc.h b/bsps/include/grlib/gr_rasta_tmtc.h index 2b10ce2df3..9feeab3479 100644 --- a/bsps/include/grlib/gr_rasta_tmtc.h +++ b/bsps/include/grlib/gr_rasta_tmtc.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GR-RASTA-TMTC PCI Target driver. * * COPYRIGHT (c) 2008. @@ -10,9 +12,26 @@ * Driver resources for the AMBA PnP bus provided can be set using * gr_rasta_tmtc_set_resources(). * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GR_RASTA_TMTC_H__ diff --git a/bsps/include/grlib/gr_tmtc_1553.h b/bsps/include/grlib/gr_tmtc_1553.h index b6ac43da00..faa8e4f6fe 100644 --- a/bsps/include/grlib/gr_tmtc_1553.h +++ b/bsps/include/grlib/gr_tmtc_1553.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GR-TMTC-1553 PCI Target driver. * * COPYRIGHT (c) 2010. @@ -10,9 +12,26 @@ * Driver resources for the AMBA PnP bus provided can be set using * gr_tmtc_1553_set_resources(). * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GR_TMTC_1553_H__ diff --git a/bsps/include/grlib/gradcdac.h b/bsps/include/grlib/gradcdac.h index 31facc2e51..ef3fa7b66c 100644 --- a/bsps/include/grlib/gradcdac.h +++ b/bsps/include/grlib/gradcdac.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* ADC / DAC (GRADCDAC) interface * * COPYRIGHT (c) 2009. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRADCDAC_H__ diff --git a/bsps/include/grlib/grascs.h b/bsps/include/grlib/grascs.h index b393e77888..e0c14089fb 100644 --- a/bsps/include/grlib/grascs.h +++ b/bsps/include/grlib/grascs.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * Header file for GRASCS RTEMS driver * * COPYRIGHT (c) 2008. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRASCS_H__ diff --git a/bsps/include/grlib/grcan-regs.h b/bsps/include/grlib/grcan-regs.h new file mode 100644 index 0000000000..85a5e56367 --- /dev/null +++ b/bsps/include/grlib/grcan-regs.h @@ -0,0 +1,723 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRCAN + * + * @brief This header file defines the GRCAN register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grcan-header */ + +#ifndef _GRLIB_GRCAN_REGS_H +#define _GRLIB_GRCAN_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grcan */ + +/** + * @defgroup RTEMSDeviceGRCAN GRCAN + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRCAN interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRCANCanCONF Configuration Register (CanCONF) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANCONF_SCALER_SHIFT 24 +#define GRCAN_CANCONF_SCALER_MASK 0xff000000U +#define GRCAN_CANCONF_SCALER_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANCONF_SCALER_MASK ) >> \ + GRCAN_CANCONF_SCALER_SHIFT ) +#define GRCAN_CANCONF_SCALER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANCONF_SCALER_MASK ) | \ + ( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & \ + GRCAN_CANCONF_SCALER_MASK ) ) +#define GRCAN_CANCONF_SCALER( _val ) \ + ( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & \ + GRCAN_CANCONF_SCALER_MASK ) + +#define GRCAN_CANCONF_PS1_SHIFT 20 +#define GRCAN_CANCONF_PS1_MASK 0xf00000U +#define GRCAN_CANCONF_PS1_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANCONF_PS1_MASK ) >> \ + GRCAN_CANCONF_PS1_SHIFT ) +#define GRCAN_CANCONF_PS1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANCONF_PS1_MASK ) | \ + ( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & \ + GRCAN_CANCONF_PS1_MASK ) ) +#define GRCAN_CANCONF_PS1( _val ) \ + ( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & \ + GRCAN_CANCONF_PS1_MASK ) + +#define GRCAN_CANCONF_PS2_SHIFT 16 +#define GRCAN_CANCONF_PS2_MASK 0xf0000U +#define GRCAN_CANCONF_PS2_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANCONF_PS2_MASK ) >> \ + GRCAN_CANCONF_PS2_SHIFT ) +#define GRCAN_CANCONF_PS2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANCONF_PS2_MASK ) | \ + ( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & \ + GRCAN_CANCONF_PS2_MASK ) ) +#define GRCAN_CANCONF_PS2( _val ) \ + ( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & \ + GRCAN_CANCONF_PS2_MASK ) + +#define GRCAN_CANCONF_RSJ_SHIFT 12 +#define GRCAN_CANCONF_RSJ_MASK 0x7000U +#define GRCAN_CANCONF_RSJ_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANCONF_RSJ_MASK ) >> \ + GRCAN_CANCONF_RSJ_SHIFT ) +#define GRCAN_CANCONF_RSJ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANCONF_RSJ_MASK ) | \ + ( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & \ + GRCAN_CANCONF_RSJ_MASK ) ) +#define GRCAN_CANCONF_RSJ( _val ) \ + ( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & \ + GRCAN_CANCONF_RSJ_MASK ) + +#define GRCAN_CANCONF_BPR_SHIFT 8 +#define GRCAN_CANCONF_BPR_MASK 0x300U +#define GRCAN_CANCONF_BPR_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANCONF_BPR_MASK ) >> \ + GRCAN_CANCONF_BPR_SHIFT ) +#define GRCAN_CANCONF_BPR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANCONF_BPR_MASK ) | \ + ( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & \ + GRCAN_CANCONF_BPR_MASK ) ) +#define GRCAN_CANCONF_BPR( _val ) \ + ( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & \ + GRCAN_CANCONF_BPR_MASK ) + +#define GRCAN_CANCONF_SAM 0x20U + +#define GRCAN_CANCONF_SILNT 0x10U + +#define GRCAN_CANCONF_SELECT 0x8U + +#define GRCAN_CANCONF_ENABLE1 0x4U + +#define GRCAN_CANCONF_ENABLE0 0x2U + +#define GRCAN_CANCONF_ABORT 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanSTAT Status Register (CanSTAT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANSTAT_TXCHANNELS_SHIFT 28 +#define GRCAN_CANSTAT_TXCHANNELS_MASK 0xf0000000U +#define GRCAN_CANSTAT_TXCHANNELS_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANSTAT_TXCHANNELS_MASK ) >> \ + GRCAN_CANSTAT_TXCHANNELS_SHIFT ) +#define GRCAN_CANSTAT_TXCHANNELS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANSTAT_TXCHANNELS_MASK ) | \ + ( ( ( _val ) << GRCAN_CANSTAT_TXCHANNELS_SHIFT ) & \ + GRCAN_CANSTAT_TXCHANNELS_MASK ) ) +#define GRCAN_CANSTAT_TXCHANNELS( _val ) \ + ( ( ( _val ) << GRCAN_CANSTAT_TXCHANNELS_SHIFT ) & \ + GRCAN_CANSTAT_TXCHANNELS_MASK ) + +#define GRCAN_CANSTAT_RXCHANNELS_SHIFT 24 +#define GRCAN_CANSTAT_RXCHANNELS_MASK 0xf000000U +#define GRCAN_CANSTAT_RXCHANNELS_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANSTAT_RXCHANNELS_MASK ) >> \ + GRCAN_CANSTAT_RXCHANNELS_SHIFT ) +#define GRCAN_CANSTAT_RXCHANNELS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANSTAT_RXCHANNELS_MASK ) | \ + ( ( ( _val ) << GRCAN_CANSTAT_RXCHANNELS_SHIFT ) & \ + GRCAN_CANSTAT_RXCHANNELS_MASK ) ) +#define GRCAN_CANSTAT_RXCHANNELS( _val ) \ + ( ( ( _val ) << GRCAN_CANSTAT_RXCHANNELS_SHIFT ) & \ + GRCAN_CANSTAT_RXCHANNELS_MASK ) + +#define GRCAN_CANSTAT_TXERRCNT_SHIFT 16 +#define GRCAN_CANSTAT_TXERRCNT_MASK 0xff0000U +#define GRCAN_CANSTAT_TXERRCNT_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANSTAT_TXERRCNT_MASK ) >> \ + GRCAN_CANSTAT_TXERRCNT_SHIFT ) +#define GRCAN_CANSTAT_TXERRCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANSTAT_TXERRCNT_MASK ) | \ + ( ( ( _val ) << GRCAN_CANSTAT_TXERRCNT_SHIFT ) & \ + GRCAN_CANSTAT_TXERRCNT_MASK ) ) +#define GRCAN_CANSTAT_TXERRCNT( _val ) \ + ( ( ( _val ) << GRCAN_CANSTAT_TXERRCNT_SHIFT ) & \ + GRCAN_CANSTAT_TXERRCNT_MASK ) + +#define GRCAN_CANSTAT_RXERRCNT_SHIFT 8 +#define GRCAN_CANSTAT_RXERRCNT_MASK 0xff00U +#define GRCAN_CANSTAT_RXERRCNT_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANSTAT_RXERRCNT_MASK ) >> \ + GRCAN_CANSTAT_RXERRCNT_SHIFT ) +#define GRCAN_CANSTAT_RXERRCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANSTAT_RXERRCNT_MASK ) | \ + ( ( ( _val ) << GRCAN_CANSTAT_RXERRCNT_SHIFT ) & \ + GRCAN_CANSTAT_RXERRCNT_MASK ) ) +#define GRCAN_CANSTAT_RXERRCNT( _val ) \ + ( ( ( _val ) << GRCAN_CANSTAT_RXERRCNT_SHIFT ) & \ + GRCAN_CANSTAT_RXERRCNT_MASK ) + +#define GRCAN_CANSTAT_ACTIVE 0x10U + +#define GRCAN_CANSTAT_AHBERR 0x8U + +#define GRCAN_CANSTAT_OR 0x4U + +#define GRCAN_CANSTAT_OFF 0x2U + +#define GRCAN_CANSTAT_PASS 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanCTRL Control Register (CanCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANCTRL_RESET 0x2U + +#define GRCAN_CANCTRL_ENABLE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanMASK SYNC Mask Filter Register (CanMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANMASK_MASK_SHIFT 0 +#define GRCAN_CANMASK_MASK_MASK 0x1fffffffU +#define GRCAN_CANMASK_MASK_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANMASK_MASK_MASK ) >> \ + GRCAN_CANMASK_MASK_SHIFT ) +#define GRCAN_CANMASK_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANMASK_MASK_MASK ) | \ + ( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & \ + GRCAN_CANMASK_MASK_MASK ) ) +#define GRCAN_CANMASK_MASK( _val ) \ + ( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & \ + GRCAN_CANMASK_MASK_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanCODE SYNC Code Filter Register (CanCODE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANCODE_SYNC_SHIFT 0 +#define GRCAN_CANCODE_SYNC_MASK 0x1fffffffU +#define GRCAN_CANCODE_SYNC_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANCODE_SYNC_MASK ) >> \ + GRCAN_CANCODE_SYNC_SHIFT ) +#define GRCAN_CANCODE_SYNC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANCODE_SYNC_MASK ) | \ + ( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & \ + GRCAN_CANCODE_SYNC_MASK ) ) +#define GRCAN_CANCODE_SYNC( _val ) \ + ( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & \ + GRCAN_CANCODE_SYNC_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanTxCTRL \ + * Transmit Channel Control Register (CanTxCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANTXCTRL_SINGLE 0x4U + +#define GRCAN_CANTXCTRL_ONGOING 0x2U + +#define GRCAN_CANTXCTRL_ENABLE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanTxADDR \ + * Transmit Channel Address Register (CanTxADDR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANTXADDR_ADDR_SHIFT 10 +#define GRCAN_CANTXADDR_ADDR_MASK 0xfffffc00U +#define GRCAN_CANTXADDR_ADDR_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANTXADDR_ADDR_MASK ) >> \ + GRCAN_CANTXADDR_ADDR_SHIFT ) +#define GRCAN_CANTXADDR_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANTXADDR_ADDR_MASK ) | \ + ( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & \ + GRCAN_CANTXADDR_ADDR_MASK ) ) +#define GRCAN_CANTXADDR_ADDR( _val ) \ + ( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & \ + GRCAN_CANTXADDR_ADDR_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanTxSIZE \ + * Transmit Channel Size Register (CanTxSIZE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANTXSIZE_SIZE_SHIFT 6 +#define GRCAN_CANTXSIZE_SIZE_MASK 0x1fffc0U +#define GRCAN_CANTXSIZE_SIZE_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANTXSIZE_SIZE_MASK ) >> \ + GRCAN_CANTXSIZE_SIZE_SHIFT ) +#define GRCAN_CANTXSIZE_SIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANTXSIZE_SIZE_MASK ) | \ + ( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & \ + GRCAN_CANTXSIZE_SIZE_MASK ) ) +#define GRCAN_CANTXSIZE_SIZE( _val ) \ + ( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & \ + GRCAN_CANTXSIZE_SIZE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanTxWR Transmit Channel Write Register (CanTxWR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANTXWR_WRITE_SHIFT 4 +#define GRCAN_CANTXWR_WRITE_MASK 0xffff0U +#define GRCAN_CANTXWR_WRITE_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANTXWR_WRITE_MASK ) >> \ + GRCAN_CANTXWR_WRITE_SHIFT ) +#define GRCAN_CANTXWR_WRITE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANTXWR_WRITE_MASK ) | \ + ( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & \ + GRCAN_CANTXWR_WRITE_MASK ) ) +#define GRCAN_CANTXWR_WRITE( _val ) \ + ( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & \ + GRCAN_CANTXWR_WRITE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanTxRD Transmit Channel Read Register (CanTxRD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANTXRD_READ_SHIFT 4 +#define GRCAN_CANTXRD_READ_MASK 0xffff0U +#define GRCAN_CANTXRD_READ_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANTXRD_READ_MASK ) >> \ + GRCAN_CANTXRD_READ_SHIFT ) +#define GRCAN_CANTXRD_READ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANTXRD_READ_MASK ) | \ + ( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & \ + GRCAN_CANTXRD_READ_MASK ) ) +#define GRCAN_CANTXRD_READ( _val ) \ + ( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & \ + GRCAN_CANTXRD_READ_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanTxIRQ \ + * Transmit Channel Interrupt Register (CanTxIRQ) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANTXIRQ_IRQ_SHIFT 4 +#define GRCAN_CANTXIRQ_IRQ_MASK 0xffff0U +#define GRCAN_CANTXIRQ_IRQ_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANTXIRQ_IRQ_MASK ) >> \ + GRCAN_CANTXIRQ_IRQ_SHIFT ) +#define GRCAN_CANTXIRQ_IRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANTXIRQ_IRQ_MASK ) | \ + ( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \ + GRCAN_CANTXIRQ_IRQ_MASK ) ) +#define GRCAN_CANTXIRQ_IRQ( _val ) \ + ( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \ + GRCAN_CANTXIRQ_IRQ_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxCTRL \ + * Receive Channel Control Register (CanRxCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXCTRL_ONGOING 0x2U + +#define GRCAN_CANRXCTRL_ENABLE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxADDR \ + * Receive Channel Address Register (CanRxADDR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXADDR_ADDR_SHIFT 10 +#define GRCAN_CANRXADDR_ADDR_MASK 0xfffffc00U +#define GRCAN_CANRXADDR_ADDR_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANRXADDR_ADDR_MASK ) >> \ + GRCAN_CANRXADDR_ADDR_SHIFT ) +#define GRCAN_CANRXADDR_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANRXADDR_ADDR_MASK ) | \ + ( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & \ + GRCAN_CANRXADDR_ADDR_MASK ) ) +#define GRCAN_CANRXADDR_ADDR( _val ) \ + ( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & \ + GRCAN_CANRXADDR_ADDR_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxSIZE \ + * Receive Channel Size Register (CanRxSIZE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXSIZE_SIZE_SHIFT 6 +#define GRCAN_CANRXSIZE_SIZE_MASK 0x1fffc0U +#define GRCAN_CANRXSIZE_SIZE_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANRXSIZE_SIZE_MASK ) >> \ + GRCAN_CANRXSIZE_SIZE_SHIFT ) +#define GRCAN_CANRXSIZE_SIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANRXSIZE_SIZE_MASK ) | \ + ( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & \ + GRCAN_CANRXSIZE_SIZE_MASK ) ) +#define GRCAN_CANRXSIZE_SIZE( _val ) \ + ( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & \ + GRCAN_CANRXSIZE_SIZE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxWR Receive Channel Write Register (CanRxWR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXWR_WRITE_SHIFT 4 +#define GRCAN_CANRXWR_WRITE_MASK 0xffff0U +#define GRCAN_CANRXWR_WRITE_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANRXWR_WRITE_MASK ) >> \ + GRCAN_CANRXWR_WRITE_SHIFT ) +#define GRCAN_CANRXWR_WRITE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANRXWR_WRITE_MASK ) | \ + ( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & \ + GRCAN_CANRXWR_WRITE_MASK ) ) +#define GRCAN_CANRXWR_WRITE( _val ) \ + ( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & \ + GRCAN_CANRXWR_WRITE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxRD Receive Channel Read Register (CanRxRD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXRD_READ_SHIFT 4 +#define GRCAN_CANRXRD_READ_MASK 0xffff0U +#define GRCAN_CANRXRD_READ_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANRXRD_READ_MASK ) >> \ + GRCAN_CANRXRD_READ_SHIFT ) +#define GRCAN_CANRXRD_READ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANRXRD_READ_MASK ) | \ + ( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & \ + GRCAN_CANRXRD_READ_MASK ) ) +#define GRCAN_CANRXRD_READ( _val ) \ + ( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & \ + GRCAN_CANRXRD_READ_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxIRQ \ + * Receive Channel Interrupt Register (CanRxIRQ) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXIRQ_IRQ_SHIFT 4 +#define GRCAN_CANRXIRQ_IRQ_MASK 0xffff0U +#define GRCAN_CANRXIRQ_IRQ_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANRXIRQ_IRQ_MASK ) >> \ + GRCAN_CANRXIRQ_IRQ_SHIFT ) +#define GRCAN_CANRXIRQ_IRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANRXIRQ_IRQ_MASK ) | \ + ( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & \ + GRCAN_CANRXIRQ_IRQ_MASK ) ) +#define GRCAN_CANRXIRQ_IRQ( _val ) \ + ( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & \ + GRCAN_CANRXIRQ_IRQ_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxMASK \ + * Receive Channel Mask Register (CanRxMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXMASK_AM_SHIFT 0 +#define GRCAN_CANRXMASK_AM_MASK 0x1fffffffU +#define GRCAN_CANRXMASK_AM_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANRXMASK_AM_MASK ) >> \ + GRCAN_CANRXMASK_AM_SHIFT ) +#define GRCAN_CANRXMASK_AM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANRXMASK_AM_MASK ) | \ + ( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & \ + GRCAN_CANRXMASK_AM_MASK ) ) +#define GRCAN_CANRXMASK_AM( _val ) \ + ( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & \ + GRCAN_CANRXMASK_AM_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxCODE \ + * Receive Channel Code Register (CanRxCODE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXCODE_AC_SHIFT 0 +#define GRCAN_CANRXCODE_AC_MASK 0x1fffffffU +#define GRCAN_CANRXCODE_AC_GET( _reg ) \ + ( ( ( _reg ) & GRCAN_CANRXCODE_AC_MASK ) >> \ + GRCAN_CANRXCODE_AC_SHIFT ) +#define GRCAN_CANRXCODE_AC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCAN_CANRXCODE_AC_MASK ) | \ + ( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & \ + GRCAN_CANRXCODE_AC_MASK ) ) +#define GRCAN_CANRXCODE_AC( _val ) \ + ( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & \ + GRCAN_CANRXCODE_AC_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GRCAN register block memory map. + */ +typedef struct grcan { + /** + * @brief See @ref RTEMSDeviceGRCANCanCONF. + */ + uint32_t canconf; + + /** + * @brief See @ref RTEMSDeviceGRCANCanSTAT. + */ + uint32_t canstat; + + /** + * @brief See @ref RTEMSDeviceGRCANCanCTRL. + */ + uint32_t canctrl; + + uint32_t reserved_c_18[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRCANCanMASK. + */ + uint32_t canmask; + + /** + * @brief See @ref RTEMSDeviceGRCANCanCODE. + */ + uint32_t cancode; + + uint32_t reserved_20_200[ 120 ]; + + /** + * @brief See @ref RTEMSDeviceGRCANCanTxCTRL. + */ + uint32_t cantxctrl; + + /** + * @brief See @ref RTEMSDeviceGRCANCanTxADDR. + */ + uint32_t cantxaddr; + + /** + * @brief See @ref RTEMSDeviceGRCANCanTxSIZE. + */ + uint32_t cantxsize; + + /** + * @brief See @ref RTEMSDeviceGRCANCanTxWR. + */ + uint32_t cantxwr; + + /** + * @brief See @ref RTEMSDeviceGRCANCanTxRD. + */ + uint32_t cantxrd; + + /** + * @brief See @ref RTEMSDeviceGRCANCanTxIRQ. + */ + uint32_t cantxirq; + + uint32_t reserved_218_300[ 58 ]; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxCTRL. + */ + uint32_t canrxctrl; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxADDR. + */ + uint32_t canrxaddr; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxSIZE. + */ + uint32_t canrxsize; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxWR. + */ + uint32_t canrxwr; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxRD. + */ + uint32_t canrxrd; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxIRQ. + */ + uint32_t canrxirq; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxMASK. + */ + uint32_t canrxmask; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxCODE. + */ + uint32_t canrxcode; +} grcan; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRCAN_REGS_H */ diff --git a/bsps/include/grlib/grcan.h b/bsps/include/grlib/grcan.h index a956bef124..cb30a8a75b 100644 --- a/bsps/include/grlib/grcan.h +++ b/bsps/include/grlib/grcan.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup can @@ -8,9 +10,26 @@ * COPYRIGHT (c) 2007. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRCAN_H__ diff --git a/bsps/include/grlib/grclkgate-regs.h b/bsps/include/grlib/grclkgate-regs.h new file mode 100644 index 0000000000..22dae51207 --- /dev/null +++ b/bsps/include/grlib/grclkgate-regs.h @@ -0,0 +1,212 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRCLKGATE + * + * @brief This header file defines the GRCLKGATE register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grclkgate-header */ + +#ifndef _GRLIB_GRCLKGATE_REGS_H +#define _GRLIB_GRCLKGATE_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grclkgate */ + +/** + * @defgroup RTEMSDeviceGRCLKGATE GRCLKGATE + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRCLKGATE interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRCLKGATEUNLOCK Unlock register (UNLOCK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCLKGATE_UNLOCK_UNLOCK_SHIFT 0 +#define GRCLKGATE_UNLOCK_UNLOCK_MASK 0xffffffffU +#define GRCLKGATE_UNLOCK_UNLOCK_GET( _reg ) \ + ( ( ( _reg ) & GRCLKGATE_UNLOCK_UNLOCK_MASK ) >> \ + GRCLKGATE_UNLOCK_UNLOCK_SHIFT ) +#define GRCLKGATE_UNLOCK_UNLOCK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCLKGATE_UNLOCK_UNLOCK_MASK ) | \ + ( ( ( _val ) << GRCLKGATE_UNLOCK_UNLOCK_SHIFT ) & \ + GRCLKGATE_UNLOCK_UNLOCK_MASK ) ) +#define GRCLKGATE_UNLOCK_UNLOCK( _val ) \ + ( ( ( _val ) << GRCLKGATE_UNLOCK_UNLOCK_SHIFT ) & \ + GRCLKGATE_UNLOCK_UNLOCK_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCLKGATECLKEN Clock enable register (CLKEN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCLKGATE_CLKEN_ENABLE_SHIFT 0 +#define GRCLKGATE_CLKEN_ENABLE_MASK 0xffffffffU +#define GRCLKGATE_CLKEN_ENABLE_GET( _reg ) \ + ( ( ( _reg ) & GRCLKGATE_CLKEN_ENABLE_MASK ) >> \ + GRCLKGATE_CLKEN_ENABLE_SHIFT ) +#define GRCLKGATE_CLKEN_ENABLE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCLKGATE_CLKEN_ENABLE_MASK ) | \ + ( ( ( _val ) << GRCLKGATE_CLKEN_ENABLE_SHIFT ) & \ + GRCLKGATE_CLKEN_ENABLE_MASK ) ) +#define GRCLKGATE_CLKEN_ENABLE( _val ) \ + ( ( ( _val ) << GRCLKGATE_CLKEN_ENABLE_SHIFT ) & \ + GRCLKGATE_CLKEN_ENABLE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCLKGATERESET Reset register (RESET) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCLKGATE_RESET_RESET_SHIFT 0 +#define GRCLKGATE_RESET_RESET_MASK 0xffffffffU +#define GRCLKGATE_RESET_RESET_GET( _reg ) \ + ( ( ( _reg ) & GRCLKGATE_RESET_RESET_MASK ) >> \ + GRCLKGATE_RESET_RESET_SHIFT ) +#define GRCLKGATE_RESET_RESET_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCLKGATE_RESET_RESET_MASK ) | \ + ( ( ( _val ) << GRCLKGATE_RESET_RESET_SHIFT ) & \ + GRCLKGATE_RESET_RESET_MASK ) ) +#define GRCLKGATE_RESET_RESET( _val ) \ + ( ( ( _val ) << GRCLKGATE_RESET_RESET_SHIFT ) & \ + GRCLKGATE_RESET_RESET_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCLKGATEOVERRIDE CPU/FPU override register (OVERRIDE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT 16 +#define GRCLKGATE_OVERRIDE_FOVERRIDE_MASK 0xf0000U +#define GRCLKGATE_OVERRIDE_FOVERRIDE_GET( _reg ) \ + ( ( ( _reg ) & GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) >> \ + GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT ) +#define GRCLKGATE_OVERRIDE_FOVERRIDE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) | \ + ( ( ( _val ) << GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT ) & \ + GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) ) +#define GRCLKGATE_OVERRIDE_FOVERRIDE( _val ) \ + ( ( ( _val ) << GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT ) & \ + GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) + +#define GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT 0 +#define GRCLKGATE_OVERRIDE_OVERRIDE_MASK 0xfU +#define GRCLKGATE_OVERRIDE_OVERRIDE_GET( _reg ) \ + ( ( ( _reg ) & GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) >> \ + GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT ) +#define GRCLKGATE_OVERRIDE_OVERRIDE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) | \ + ( ( ( _val ) << GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT ) & \ + GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) ) +#define GRCLKGATE_OVERRIDE_OVERRIDE( _val ) \ + ( ( ( _val ) << GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT ) & \ + GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GRCLKGATE register block memory map. + */ +typedef struct grclkgate { + /** + * @brief See @ref RTEMSDeviceGRCLKGATEUNLOCK. + */ + uint32_t unlock; + + /** + * @brief See @ref RTEMSDeviceGRCLKGATECLKEN. + */ + uint32_t clken; + + /** + * @brief See @ref RTEMSDeviceGRCLKGATERESET. + */ + uint32_t reset; + + /** + * @brief See @ref RTEMSDeviceGRCLKGATEOVERRIDE. + */ + uint32_t override; +} grclkgate; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRCLKGATE_REGS_H */ diff --git a/bsps/include/grlib/grctm.h b/bsps/include/grlib/grctm.h index 5ff81559aa..0f4f3bcd78 100644 --- a/bsps/include/grlib/grctm.h +++ b/bsps/include/grlib/grctm.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GRCTM - CCSDS Time Manager - register driver interface. * * COPYRIGHT (c) 2009. * Cobham Gaisler AB * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRCTM_H__ diff --git a/bsps/include/grlib/grethgbit-regs.h b/bsps/include/grlib/grethgbit-regs.h new file mode 100644 index 0000000000..8d8f4ce8bf --- /dev/null +++ b/bsps/include/grlib/grethgbit-regs.h @@ -0,0 +1,446 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRETHGBIT + * + * @brief This header file defines the GRETH_GBIT register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grethgbit-header */ + +#ifndef _GRLIB_GRETHGBIT_REGS_H +#define _GRLIB_GRETHGBIT_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grethgbit */ + +/** + * @defgroup RTEMSDeviceGRETHGBIT GRETH_GBIT + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRETH_GBIT interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRETHGBITCR control register (CR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_CR_EA 0x80000000U + +#define GRETHGBIT_CR_BS_SHIFT 28 +#define GRETHGBIT_CR_BS_MASK 0x70000000U +#define GRETHGBIT_CR_BS_GET( _reg ) \ + ( ( ( _reg ) & GRETHGBIT_CR_BS_MASK ) >> \ + GRETHGBIT_CR_BS_SHIFT ) +#define GRETHGBIT_CR_BS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_CR_BS_MASK ) | \ + ( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \ + GRETHGBIT_CR_BS_MASK ) ) +#define GRETHGBIT_CR_BS( _val ) \ + ( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \ + GRETHGBIT_CR_BS_MASK ) + +#define GRETHGBIT_CR_GA 0x8000000U + +#define GRETHGBIT_CR_MA 0x4000000U + +#define GRETHGBIT_CR_MC 0x2000000U + +#define GRETHGBIT_CR_ED 0x4000U + +#define GRETHGBIT_CR_RD 0x2000U + +#define GRETHGBIT_CR_DD 0x1000U + +#define GRETHGBIT_CR_ME 0x800U + +#define GRETHGBIT_CR_PI 0x400U + +#define GRETHGBIT_CR_BM 0x200U + +#define GRETHGBIT_CR_GB 0x100U + +#define GRETHGBIT_CR_SP 0x80U + +#define GRETHGBIT_CR_RS 0x40U + +#define GRETHGBIT_CR_PM 0x20U + +#define GRETHGBIT_CR_FD 0x10U + +#define GRETHGBIT_CR_RI 0x8U + +#define GRETHGBIT_CR_TI 0x4U + +#define GRETHGBIT_CR_RE 0x2U + +#define GRETHGBIT_CR_TE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITSR status register. (SR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_SR_PS 0x100U + +#define GRETHGBIT_SR_IA 0x80U + +#define GRETHGBIT_SR_TS 0x40U + +#define GRETHGBIT_SR_TA 0x20U + +#define GRETHGBIT_SR_RA 0x10U + +#define GRETHGBIT_SR_TI 0x8U + +#define GRETHGBIT_SR_RI 0x4U + +#define GRETHGBIT_SR_TE 0x2U + +#define GRETHGBIT_SR_RE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITMACMSB MAC address MSB. (MACMSB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_MACMSB_MSB_SHIFT 0 +#define GRETHGBIT_MACMSB_MSB_MASK 0xffffU +#define GRETHGBIT_MACMSB_MSB_GET( _reg ) \ + ( ( ( _reg ) & GRETHGBIT_MACMSB_MSB_MASK ) >> \ + GRETHGBIT_MACMSB_MSB_SHIFT ) +#define GRETHGBIT_MACMSB_MSB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_MACMSB_MSB_MASK ) | \ + ( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \ + GRETHGBIT_MACMSB_MSB_MASK ) ) +#define GRETHGBIT_MACMSB_MSB( _val ) \ + ( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \ + GRETHGBIT_MACMSB_MSB_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITMACLSB MAC address LSB. (MACLSB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_MACLSB_LSB_SHIFT 0 +#define GRETHGBIT_MACLSB_LSB_MASK 0xffffffffU +#define GRETHGBIT_MACLSB_LSB_GET( _reg ) \ + ( ( ( _reg ) & GRETHGBIT_MACLSB_LSB_MASK ) >> \ + GRETHGBIT_MACLSB_LSB_SHIFT ) +#define GRETHGBIT_MACLSB_LSB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_MACLSB_LSB_MASK ) | \ + ( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \ + GRETHGBIT_MACLSB_LSB_MASK ) ) +#define GRETHGBIT_MACLSB_LSB( _val ) \ + ( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \ + GRETHGBIT_MACLSB_LSB_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITMDIO MDIO control/status register. (MDIO) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_MDIO_DATA_SHIFT 16 +#define GRETHGBIT_MDIO_DATA_MASK 0xffff0000U +#define GRETHGBIT_MDIO_DATA_GET( _reg ) \ + ( ( ( _reg ) & GRETHGBIT_MDIO_DATA_MASK ) >> \ + GRETHGBIT_MDIO_DATA_SHIFT ) +#define GRETHGBIT_MDIO_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_MDIO_DATA_MASK ) | \ + ( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \ + GRETHGBIT_MDIO_DATA_MASK ) ) +#define GRETHGBIT_MDIO_DATA( _val ) \ + ( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \ + GRETHGBIT_MDIO_DATA_MASK ) + +#define GRETHGBIT_MDIO_PHYADDR_SHIFT 11 +#define GRETHGBIT_MDIO_PHYADDR_MASK 0xf800U +#define GRETHGBIT_MDIO_PHYADDR_GET( _reg ) \ + ( ( ( _reg ) & GRETHGBIT_MDIO_PHYADDR_MASK ) >> \ + GRETHGBIT_MDIO_PHYADDR_SHIFT ) +#define GRETHGBIT_MDIO_PHYADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_MDIO_PHYADDR_MASK ) | \ + ( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \ + GRETHGBIT_MDIO_PHYADDR_MASK ) ) +#define GRETHGBIT_MDIO_PHYADDR( _val ) \ + ( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \ + GRETHGBIT_MDIO_PHYADDR_MASK ) + +#define GRETHGBIT_MDIO_REGADDR_SHIFT 6 +#define GRETHGBIT_MDIO_REGADDR_MASK 0x7c0U +#define GRETHGBIT_MDIO_REGADDR_GET( _reg ) \ + ( ( ( _reg ) & GRETHGBIT_MDIO_REGADDR_MASK ) >> \ + GRETHGBIT_MDIO_REGADDR_SHIFT ) +#define GRETHGBIT_MDIO_REGADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_MDIO_REGADDR_MASK ) | \ + ( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \ + GRETHGBIT_MDIO_REGADDR_MASK ) ) +#define GRETHGBIT_MDIO_REGADDR( _val ) \ + ( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \ + GRETHGBIT_MDIO_REGADDR_MASK ) + +#define GRETHGBIT_MDIO_BU 0x8U + +#define GRETHGBIT_MDIO_LF 0x4U + +#define GRETHGBIT_MDIO_RD 0x2U + +#define GRETHGBIT_MDIO_WR 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITTDTBA \ + * transmitter descriptor table base address register. (TDTBA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_TDTBA_BASEADDR_SHIFT 10 +#define GRETHGBIT_TDTBA_BASEADDR_MASK 0xfffffc00U +#define GRETHGBIT_TDTBA_BASEADDR_GET( _reg ) \ + ( ( ( _reg ) & GRETHGBIT_TDTBA_BASEADDR_MASK ) >> \ + GRETHGBIT_TDTBA_BASEADDR_SHIFT ) +#define GRETHGBIT_TDTBA_BASEADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_TDTBA_BASEADDR_MASK ) | \ + ( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \ + GRETHGBIT_TDTBA_BASEADDR_MASK ) ) +#define GRETHGBIT_TDTBA_BASEADDR( _val ) \ + ( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \ + GRETHGBIT_TDTBA_BASEADDR_MASK ) + +#define GRETHGBIT_TDTBA_DESCPNT_SHIFT 3 +#define GRETHGBIT_TDTBA_DESCPNT_MASK 0x3f8U +#define GRETHGBIT_TDTBA_DESCPNT_GET( _reg ) \ + ( ( ( _reg ) & GRETHGBIT_TDTBA_DESCPNT_MASK ) >> \ + GRETHGBIT_TDTBA_DESCPNT_SHIFT ) +#define GRETHGBIT_TDTBA_DESCPNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_TDTBA_DESCPNT_MASK ) | \ + ( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \ + GRETHGBIT_TDTBA_DESCPNT_MASK ) ) +#define GRETHGBIT_TDTBA_DESCPNT( _val ) \ + ( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \ + GRETHGBIT_TDTBA_DESCPNT_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITRDTBA \ + * receiver descriptor table base address register. (RDTBA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_RDTBA_BASEADDR_SHIFT 10 +#define GRETHGBIT_RDTBA_BASEADDR_MASK 0xfffffc00U +#define GRETHGBIT_RDTBA_BASEADDR_GET( _reg ) \ + ( ( ( _reg ) & GRETHGBIT_RDTBA_BASEADDR_MASK ) >> \ + GRETHGBIT_RDTBA_BASEADDR_SHIFT ) +#define GRETHGBIT_RDTBA_BASEADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_RDTBA_BASEADDR_MASK ) | \ + ( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \ + GRETHGBIT_RDTBA_BASEADDR_MASK ) ) +#define GRETHGBIT_RDTBA_BASEADDR( _val ) \ + ( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \ + GRETHGBIT_RDTBA_BASEADDR_MASK ) + +#define GRETHGBIT_RDTBA_DESCPNT_SHIFT 3 +#define GRETHGBIT_RDTBA_DESCPNT_MASK 0x3f8U +#define GRETHGBIT_RDTBA_DESCPNT_GET( _reg ) \ + ( ( ( _reg ) & GRETHGBIT_RDTBA_DESCPNT_MASK ) >> \ + GRETHGBIT_RDTBA_DESCPNT_SHIFT ) +#define GRETHGBIT_RDTBA_DESCPNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_RDTBA_DESCPNT_MASK ) | \ + ( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \ + GRETHGBIT_RDTBA_DESCPNT_MASK ) ) +#define GRETHGBIT_RDTBA_DESCPNT( _val ) \ + ( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \ + GRETHGBIT_RDTBA_DESCPNT_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITEDCLMACMSB EDCL MAC address MSB. (EDCLMACMSB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_EDCLMACMSB_MSB_SHIFT 0 +#define GRETHGBIT_EDCLMACMSB_MSB_MASK 0xffffU +#define GRETHGBIT_EDCLMACMSB_MSB_GET( _reg ) \ + ( ( ( _reg ) & GRETHGBIT_EDCLMACMSB_MSB_MASK ) >> \ + GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) +#define GRETHGBIT_EDCLMACMSB_MSB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_EDCLMACMSB_MSB_MASK ) | \ + ( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \ + GRETHGBIT_EDCLMACMSB_MSB_MASK ) ) +#define GRETHGBIT_EDCLMACMSB_MSB( _val ) \ + ( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \ + GRETHGBIT_EDCLMACMSB_MSB_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITEDCLMACLSB EDCL MAC address LSB. (EDCLMACLSB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_EDCLMACLSB_LSB_SHIFT 0 +#define GRETHGBIT_EDCLMACLSB_LSB_MASK 0xffffffffU +#define GRETHGBIT_EDCLMACLSB_LSB_GET( _reg ) \ + ( ( ( _reg ) & GRETHGBIT_EDCLMACLSB_LSB_MASK ) >> \ + GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) +#define GRETHGBIT_EDCLMACLSB_LSB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRETHGBIT_EDCLMACLSB_LSB_MASK ) | \ + ( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \ + GRETHGBIT_EDCLMACLSB_LSB_MASK ) ) +#define GRETHGBIT_EDCLMACLSB_LSB( _val ) \ + ( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \ + GRETHGBIT_EDCLMACLSB_LSB_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GRETH_GBIT register block memory map. + */ +typedef struct grethgbit { + /** + * @brief See @ref RTEMSDeviceGRETHGBITCR. + */ + uint32_t cr; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITSR. + */ + uint32_t sr; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITMACMSB. + */ + uint32_t macmsb; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITMACLSB. + */ + uint32_t maclsb; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITMDIO. + */ + uint32_t mdio; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITTDTBA. + */ + uint32_t tdtba; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITRDTBA. + */ + uint32_t rdtba; + + uint32_t reserved_1c_28[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITEDCLMACMSB. + */ + uint32_t edclmacmsb; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITEDCLMACLSB. + */ + uint32_t edclmaclsb; +} grethgbit; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRETHGBIT_REGS_H */ diff --git a/bsps/include/grlib/grgpio-regs.h b/bsps/include/grlib/grgpio-regs.h new file mode 100644 index 0000000000..8c3c7ffb16 --- /dev/null +++ b/bsps/include/grlib/grgpio-regs.h @@ -0,0 +1,630 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRGPIO + * + * @brief This header file defines the GRGPIO register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grgpio-header */ + +#ifndef _GRLIB_GRGPIO_REGS_H +#define _GRLIB_GRGPIO_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grgpio */ + +/** + * @defgroup RTEMSDeviceGRGPIO GRGPIO + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRGPIO interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRGPIODATA I/O port data register (DATA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_DATA_DATA_SHIFT 0 +#define GRGPIO_DATA_DATA_MASK 0xffffffffU +#define GRGPIO_DATA_DATA_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_DATA_DATA_MASK ) >> \ + GRGPIO_DATA_DATA_SHIFT ) +#define GRGPIO_DATA_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_DATA_DATA_MASK ) | \ + ( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & \ + GRGPIO_DATA_DATA_MASK ) ) +#define GRGPIO_DATA_DATA( _val ) \ + ( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & \ + GRGPIO_DATA_DATA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOOUTPUT I/O port output register (OUTPUT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_OUTPUT_DATA_SHIFT 0 +#define GRGPIO_OUTPUT_DATA_MASK 0xffffffffU +#define GRGPIO_OUTPUT_DATA_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_OUTPUT_DATA_MASK ) >> \ + GRGPIO_OUTPUT_DATA_SHIFT ) +#define GRGPIO_OUTPUT_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_OUTPUT_DATA_MASK ) | \ + ( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & \ + GRGPIO_OUTPUT_DATA_MASK ) ) +#define GRGPIO_OUTPUT_DATA( _val ) \ + ( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & \ + GRGPIO_OUTPUT_DATA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIODIRECTION I/O port direction register (DIRECTION) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_DIRECTION_DIR_SHIFT 0 +#define GRGPIO_DIRECTION_DIR_MASK 0xffffffffU +#define GRGPIO_DIRECTION_DIR_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_DIRECTION_DIR_MASK ) >> \ + GRGPIO_DIRECTION_DIR_SHIFT ) +#define GRGPIO_DIRECTION_DIR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_DIRECTION_DIR_MASK ) | \ + ( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & \ + GRGPIO_DIRECTION_DIR_MASK ) ) +#define GRGPIO_DIRECTION_DIR( _val ) \ + ( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & \ + GRGPIO_DIRECTION_DIR_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIMASK Interrupt mask register (IMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IMASK_MASK_SHIFT 0 +#define GRGPIO_IMASK_MASK_MASK 0xffffffffU +#define GRGPIO_IMASK_MASK_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_IMASK_MASK_MASK ) >> \ + GRGPIO_IMASK_MASK_SHIFT ) +#define GRGPIO_IMASK_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IMASK_MASK_MASK ) | \ + ( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & \ + GRGPIO_IMASK_MASK_MASK ) ) +#define GRGPIO_IMASK_MASK( _val ) \ + ( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & \ + GRGPIO_IMASK_MASK_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIPOL Interrupt polarity register (IPOL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IPOL_POL_SHIFT 0 +#define GRGPIO_IPOL_POL_MASK 0xffffffffU +#define GRGPIO_IPOL_POL_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_IPOL_POL_MASK ) >> \ + GRGPIO_IPOL_POL_SHIFT ) +#define GRGPIO_IPOL_POL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IPOL_POL_MASK ) | \ + ( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & \ + GRGPIO_IPOL_POL_MASK ) ) +#define GRGPIO_IPOL_POL( _val ) \ + ( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & \ + GRGPIO_IPOL_POL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIEDGE Interrupt edge register (IEDGE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IEDGE_EDGE_SHIFT 0 +#define GRGPIO_IEDGE_EDGE_MASK 0xffffffffU +#define GRGPIO_IEDGE_EDGE_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_IEDGE_EDGE_MASK ) >> \ + GRGPIO_IEDGE_EDGE_SHIFT ) +#define GRGPIO_IEDGE_EDGE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IEDGE_EDGE_MASK ) | \ + ( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & \ + GRGPIO_IEDGE_EDGE_MASK ) ) +#define GRGPIO_IEDGE_EDGE( _val ) \ + ( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & \ + GRGPIO_IEDGE_EDGE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOBYPASS Bypass register (BYPASS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_BYPASS_BYPASS_SHIFT 0 +#define GRGPIO_BYPASS_BYPASS_MASK 0xffffffffU +#define GRGPIO_BYPASS_BYPASS_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_BYPASS_BYPASS_MASK ) >> \ + GRGPIO_BYPASS_BYPASS_SHIFT ) +#define GRGPIO_BYPASS_BYPASS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_BYPASS_BYPASS_MASK ) | \ + ( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & \ + GRGPIO_BYPASS_BYPASS_MASK ) ) +#define GRGPIO_BYPASS_BYPASS( _val ) \ + ( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & \ + GRGPIO_BYPASS_BYPASS_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOCAP Capability register (CAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_CAP_PU 0x40000U + +#define GRGPIO_CAP_IER 0x20000U + +#define GRGPIO_CAP_IFL 0x10000U + +#define GRGPIO_CAP_IRQGEN_SHIFT 8 +#define GRGPIO_CAP_IRQGEN_MASK 0x1f00U +#define GRGPIO_CAP_IRQGEN_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_CAP_IRQGEN_MASK ) >> \ + GRGPIO_CAP_IRQGEN_SHIFT ) +#define GRGPIO_CAP_IRQGEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_CAP_IRQGEN_MASK ) | \ + ( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & \ + GRGPIO_CAP_IRQGEN_MASK ) ) +#define GRGPIO_CAP_IRQGEN( _val ) \ + ( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & \ + GRGPIO_CAP_IRQGEN_MASK ) + +#define GRGPIO_CAP_NLINES_SHIFT 0 +#define GRGPIO_CAP_NLINES_MASK 0x1fU +#define GRGPIO_CAP_NLINES_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_CAP_NLINES_MASK ) >> \ + GRGPIO_CAP_NLINES_SHIFT ) +#define GRGPIO_CAP_NLINES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_CAP_NLINES_MASK ) | \ + ( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & \ + GRGPIO_CAP_NLINES_MASK ) ) +#define GRGPIO_CAP_NLINES( _val ) \ + ( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & \ + GRGPIO_CAP_NLINES_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIRQMAPR \ + * Interrupt map register n, where n = 0 .. 3 (IRQMAPR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT 24 +#define GRGPIO_IRQMAPR_IRQMAP_I_0_MASK 0x1f000000U +#define GRGPIO_IRQMAPR_IRQMAP_I_0_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) >> \ + GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) +#define GRGPIO_IRQMAPR_IRQMAP_I_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) | \ + ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \ + GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) ) +#define GRGPIO_IRQMAPR_IRQMAP_I_0( _val ) \ + ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \ + GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) + +#define GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT 16 +#define GRGPIO_IRQMAPR_IRQMAP_I_1_MASK 0x1f0000U +#define GRGPIO_IRQMAPR_IRQMAP_I_1_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) >> \ + GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) +#define GRGPIO_IRQMAPR_IRQMAP_I_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) | \ + ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) & \ + GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) ) +#define GRGPIO_IRQMAPR_IRQMAP_I_1( _val ) \ + ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) & \ + GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) + +#define GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT 8 +#define GRGPIO_IRQMAPR_IRQMAP_I_2_MASK 0x1f00U +#define GRGPIO_IRQMAPR_IRQMAP_I_2_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) >> \ + GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) +#define GRGPIO_IRQMAPR_IRQMAP_I_2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) | \ + ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) & \ + GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) ) +#define GRGPIO_IRQMAPR_IRQMAP_I_2( _val ) \ + ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) & \ + GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) + +#define GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT 0 +#define GRGPIO_IRQMAPR_IRQMAP_I_3_MASK 0x1fU +#define GRGPIO_IRQMAPR_IRQMAP_I_3_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) >> \ + GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) +#define GRGPIO_IRQMAPR_IRQMAP_I_3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) | \ + ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \ + GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) ) +#define GRGPIO_IRQMAPR_IRQMAP_I_3( _val ) \ + ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \ + GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIAVAIL Interrupt available register (IAVAIL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IAVAIL_IMASK_SHIFT 0 +#define GRGPIO_IAVAIL_IMASK_MASK 0xffffffffU +#define GRGPIO_IAVAIL_IMASK_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_IAVAIL_IMASK_MASK ) >> \ + GRGPIO_IAVAIL_IMASK_SHIFT ) +#define GRGPIO_IAVAIL_IMASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IAVAIL_IMASK_MASK ) | \ + ( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & \ + GRGPIO_IAVAIL_IMASK_MASK ) ) +#define GRGPIO_IAVAIL_IMASK( _val ) \ + ( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & \ + GRGPIO_IAVAIL_IMASK_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIFLAG Interrupt flag register (IFLAG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IFLAG_IFLAG_SHIFT 0 +#define GRGPIO_IFLAG_IFLAG_MASK 0xffffffffU +#define GRGPIO_IFLAG_IFLAG_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_IFLAG_IFLAG_MASK ) >> \ + GRGPIO_IFLAG_IFLAG_SHIFT ) +#define GRGPIO_IFLAG_IFLAG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IFLAG_IFLAG_MASK ) | \ + ( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & \ + GRGPIO_IFLAG_IFLAG_MASK ) ) +#define GRGPIO_IFLAG_IFLAG( _val ) \ + ( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & \ + GRGPIO_IFLAG_IFLAG_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIPEN Interrupt enable register (IPEN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IPEN_IPEN_SHIFT 0 +#define GRGPIO_IPEN_IPEN_MASK 0xffffffffU +#define GRGPIO_IPEN_IPEN_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_IPEN_IPEN_MASK ) >> \ + GRGPIO_IPEN_IPEN_SHIFT ) +#define GRGPIO_IPEN_IPEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_IPEN_IPEN_MASK ) | \ + ( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & \ + GRGPIO_IPEN_IPEN_MASK ) ) +#define GRGPIO_IPEN_IPEN( _val ) \ + ( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & \ + GRGPIO_IPEN_IPEN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOPULSE Pulse register (PULSE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_PULSE_PULSE_SHIFT 0 +#define GRGPIO_PULSE_PULSE_MASK 0xffffffffU +#define GRGPIO_PULSE_PULSE_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_PULSE_PULSE_MASK ) >> \ + GRGPIO_PULSE_PULSE_SHIFT ) +#define GRGPIO_PULSE_PULSE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_PULSE_PULSE_MASK ) | \ + ( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & \ + GRGPIO_PULSE_PULSE_MASK ) ) +#define GRGPIO_PULSE_PULSE( _val ) \ + ( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & \ + GRGPIO_PULSE_PULSE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOLOR Logical-OR registers (LOR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_LOR_DATA_SHIFT 0 +#define GRGPIO_LOR_DATA_MASK 0xffffffffU +#define GRGPIO_LOR_DATA_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_LOR_DATA_MASK ) >> \ + GRGPIO_LOR_DATA_SHIFT ) +#define GRGPIO_LOR_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_LOR_DATA_MASK ) | \ + ( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & \ + GRGPIO_LOR_DATA_MASK ) ) +#define GRGPIO_LOR_DATA( _val ) \ + ( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & \ + GRGPIO_LOR_DATA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOLAND Logical-AND registers (LAND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_LAND_DATA_SHIFT 0 +#define GRGPIO_LAND_DATA_MASK 0xffffffffU +#define GRGPIO_LAND_DATA_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_LAND_DATA_MASK ) >> \ + GRGPIO_LAND_DATA_SHIFT ) +#define GRGPIO_LAND_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_LAND_DATA_MASK ) | \ + ( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & \ + GRGPIO_LAND_DATA_MASK ) ) +#define GRGPIO_LAND_DATA( _val ) \ + ( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & \ + GRGPIO_LAND_DATA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOLXOR Logical-XOR registers (LXOR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_LXOR_DATA_SHIFT 0 +#define GRGPIO_LXOR_DATA_MASK 0xffffffffU +#define GRGPIO_LXOR_DATA_GET( _reg ) \ + ( ( ( _reg ) & GRGPIO_LXOR_DATA_MASK ) >> \ + GRGPIO_LXOR_DATA_SHIFT ) +#define GRGPIO_LXOR_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRGPIO_LXOR_DATA_MASK ) | \ + ( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & \ + GRGPIO_LXOR_DATA_MASK ) ) +#define GRGPIO_LXOR_DATA( _val ) \ + ( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & \ + GRGPIO_LXOR_DATA_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GRGPIO register block memory map. + */ +typedef struct grgpio { + /** + * @brief See @ref RTEMSDeviceGRGPIODATA. + */ + uint32_t data; + + /** + * @brief See @ref RTEMSDeviceGRGPIOOUTPUT. + */ + uint32_t output; + + /** + * @brief See @ref RTEMSDeviceGRGPIODIRECTION. + */ + uint32_t direction; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIMASK. + */ + uint32_t imask; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIPOL. + */ + uint32_t ipol; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIEDGE. + */ + uint32_t iedge; + + /** + * @brief See @ref RTEMSDeviceGRGPIOBYPASS. + */ + uint32_t bypass; + + /** + * @brief See @ref RTEMSDeviceGRGPIOCAP. + */ + uint32_t cap; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIRQMAPR. + */ + uint32_t irqmapr[ 8 ]; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIAVAIL. + */ + uint32_t iavail; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIFLAG. + */ + uint32_t iflag; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIPEN. + */ + uint32_t ipen; + + /** + * @brief See @ref RTEMSDeviceGRGPIOPULSE. + */ + uint32_t pulse; + + uint32_t reserved_50_54; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLOR. + */ + uint32_t lor_output; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLOR. + */ + uint32_t lor_direction; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLOR. + */ + uint32_t lor_imask; + + uint32_t reserved_60_64; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLAND. + */ + uint32_t land_output; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLAND. + */ + uint32_t land_direction; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLAND. + */ + uint32_t land_imask; + + uint32_t reserved_70_74; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLXOR. + */ + uint32_t lxor_output; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLXOR. + */ + uint32_t lxor_direction; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLXOR. + */ + uint32_t lxor_imask; +} grgpio; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRGPIO_REGS_H */ diff --git a/bsps/include/grlib/grgpio.h b/bsps/include/grlib/grgpio.h index c49054548c..6d4a28dc81 100644 --- a/bsps/include/grlib/grgpio.h +++ b/bsps/include/grlib/grgpio.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * GRGPIO GPIO Driver interface. * * COPYRIGHT (c) 2009. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRGPIO_H__ diff --git a/bsps/include/grlib/griommu-regs.h b/bsps/include/grlib/griommu-regs.h new file mode 100644 index 0000000000..4140101a14 --- /dev/null +++ b/bsps/include/grlib/griommu-regs.h @@ -0,0 +1,878 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRIOMMU + * + * @brief This header file defines the GRIOMMU register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/griommu-header */ + +#ifndef _GRLIB_GRIOMMU_REGS_H +#define _GRLIB_GRIOMMU_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/griommu */ + +/** + * @defgroup RTEMSDeviceGRIOMMU GRIOMMU + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRIOMMU interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRIOMMUCAP0 Capability register 0 (CAP0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_CAP0_A 0x80000000U + +#define GRIOMMU_CAP0_AC 0x40000000U + +#define GRIOMMU_CAP0_CA 0x20000000U + +#define GRIOMMU_CAP0_CP 0x10000000U + +#define GRIOMMU_CAP0_NARB_SHIFT 20 +#define GRIOMMU_CAP0_NARB_MASK 0xf00000U +#define GRIOMMU_CAP0_NARB_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP0_NARB_MASK ) >> \ + GRIOMMU_CAP0_NARB_SHIFT ) +#define GRIOMMU_CAP0_NARB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP0_NARB_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP0_NARB_SHIFT ) & \ + GRIOMMU_CAP0_NARB_MASK ) ) +#define GRIOMMU_CAP0_NARB( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP0_NARB_SHIFT ) & \ + GRIOMMU_CAP0_NARB_MASK ) + +#define GRIOMMU_CAP0_CS 0x80000U + +#define GRIOMMU_CAP0_FT_SHIFT 17 +#define GRIOMMU_CAP0_FT_MASK 0x60000U +#define GRIOMMU_CAP0_FT_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP0_FT_MASK ) >> \ + GRIOMMU_CAP0_FT_SHIFT ) +#define GRIOMMU_CAP0_FT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP0_FT_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP0_FT_SHIFT ) & \ + GRIOMMU_CAP0_FT_MASK ) ) +#define GRIOMMU_CAP0_FT( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP0_FT_SHIFT ) & \ + GRIOMMU_CAP0_FT_MASK ) + +#define GRIOMMU_CAP0_ST 0x10000U + +#define GRIOMMU_CAP0_I 0x8000U + +#define GRIOMMU_CAP0_IT 0x4000U + +#define GRIOMMU_CAP0_IA 0x2000U + +#define GRIOMMU_CAP0_IP 0x1000U + +#define GRIOMMU_CAP0_MB 0x100U + +#define GRIOMMU_CAP0_GRPS_SHIFT 4 +#define GRIOMMU_CAP0_GRPS_MASK 0xf0U +#define GRIOMMU_CAP0_GRPS_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP0_GRPS_MASK ) >> \ + GRIOMMU_CAP0_GRPS_SHIFT ) +#define GRIOMMU_CAP0_GRPS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP0_GRPS_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP0_GRPS_SHIFT ) & \ + GRIOMMU_CAP0_GRPS_MASK ) ) +#define GRIOMMU_CAP0_GRPS( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP0_GRPS_SHIFT ) & \ + GRIOMMU_CAP0_GRPS_MASK ) + +#define GRIOMMU_CAP0_MSTS_SHIFT 0 +#define GRIOMMU_CAP0_MSTS_MASK 0xfU +#define GRIOMMU_CAP0_MSTS_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP0_MSTS_MASK ) >> \ + GRIOMMU_CAP0_MSTS_SHIFT ) +#define GRIOMMU_CAP0_MSTS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP0_MSTS_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP0_MSTS_SHIFT ) & \ + GRIOMMU_CAP0_MSTS_MASK ) ) +#define GRIOMMU_CAP0_MSTS( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP0_MSTS_SHIFT ) & \ + GRIOMMU_CAP0_MSTS_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUCAP1 Capability register 1 (CAP1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_CAP1_CADDR_SHIFT 20 +#define GRIOMMU_CAP1_CADDR_MASK 0xfff00000U +#define GRIOMMU_CAP1_CADDR_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP1_CADDR_MASK ) >> \ + GRIOMMU_CAP1_CADDR_SHIFT ) +#define GRIOMMU_CAP1_CADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP1_CADDR_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP1_CADDR_SHIFT ) & \ + GRIOMMU_CAP1_CADDR_MASK ) ) +#define GRIOMMU_CAP1_CADDR( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP1_CADDR_SHIFT ) & \ + GRIOMMU_CAP1_CADDR_MASK ) + +#define GRIOMMU_CAP1_CMASK_SHIFT 16 +#define GRIOMMU_CAP1_CMASK_MASK 0xf0000U +#define GRIOMMU_CAP1_CMASK_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP1_CMASK_MASK ) >> \ + GRIOMMU_CAP1_CMASK_SHIFT ) +#define GRIOMMU_CAP1_CMASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP1_CMASK_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP1_CMASK_SHIFT ) & \ + GRIOMMU_CAP1_CMASK_MASK ) ) +#define GRIOMMU_CAP1_CMASK( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP1_CMASK_SHIFT ) & \ + GRIOMMU_CAP1_CMASK_MASK ) + +#define GRIOMMU_CAP1_CTAGBITS_SHIFT 8 +#define GRIOMMU_CAP1_CTAGBITS_MASK 0xff00U +#define GRIOMMU_CAP1_CTAGBITS_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP1_CTAGBITS_MASK ) >> \ + GRIOMMU_CAP1_CTAGBITS_SHIFT ) +#define GRIOMMU_CAP1_CTAGBITS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP1_CTAGBITS_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP1_CTAGBITS_SHIFT ) & \ + GRIOMMU_CAP1_CTAGBITS_MASK ) ) +#define GRIOMMU_CAP1_CTAGBITS( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP1_CTAGBITS_SHIFT ) & \ + GRIOMMU_CAP1_CTAGBITS_MASK ) + +#define GRIOMMU_CAP1_CISIZE_SHIFT 5 +#define GRIOMMU_CAP1_CISIZE_MASK 0xe0U +#define GRIOMMU_CAP1_CISIZE_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP1_CISIZE_MASK ) >> \ + GRIOMMU_CAP1_CISIZE_SHIFT ) +#define GRIOMMU_CAP1_CISIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP1_CISIZE_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP1_CISIZE_SHIFT ) & \ + GRIOMMU_CAP1_CISIZE_MASK ) ) +#define GRIOMMU_CAP1_CISIZE( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP1_CISIZE_SHIFT ) & \ + GRIOMMU_CAP1_CISIZE_MASK ) + +#define GRIOMMU_CAP1_CLINES_SHIFT 0 +#define GRIOMMU_CAP1_CLINES_MASK 0x1fU +#define GRIOMMU_CAP1_CLINES_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP1_CLINES_MASK ) >> \ + GRIOMMU_CAP1_CLINES_SHIFT ) +#define GRIOMMU_CAP1_CLINES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP1_CLINES_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP1_CLINES_SHIFT ) & \ + GRIOMMU_CAP1_CLINES_MASK ) ) +#define GRIOMMU_CAP1_CLINES( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP1_CLINES_SHIFT ) & \ + GRIOMMU_CAP1_CLINES_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUCAP2 Capability register 2 (CAP2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_CAP2_TMASK_SHIFT 24 +#define GRIOMMU_CAP2_TMASK_MASK 0xff000000U +#define GRIOMMU_CAP2_TMASK_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP2_TMASK_MASK ) >> \ + GRIOMMU_CAP2_TMASK_SHIFT ) +#define GRIOMMU_CAP2_TMASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP2_TMASK_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP2_TMASK_SHIFT ) & \ + GRIOMMU_CAP2_TMASK_MASK ) ) +#define GRIOMMU_CAP2_TMASK( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP2_TMASK_SHIFT ) & \ + GRIOMMU_CAP2_TMASK_MASK ) + +#define GRIOMMU_CAP2_MTYPE_SHIFT 18 +#define GRIOMMU_CAP2_MTYPE_MASK 0xc0000U +#define GRIOMMU_CAP2_MTYPE_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP2_MTYPE_MASK ) >> \ + GRIOMMU_CAP2_MTYPE_SHIFT ) +#define GRIOMMU_CAP2_MTYPE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP2_MTYPE_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP2_MTYPE_SHIFT ) & \ + GRIOMMU_CAP2_MTYPE_MASK ) ) +#define GRIOMMU_CAP2_MTYPE( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP2_MTYPE_SHIFT ) & \ + GRIOMMU_CAP2_MTYPE_MASK ) + +#define GRIOMMU_CAP2_TTYPE_SHIFT 16 +#define GRIOMMU_CAP2_TTYPE_MASK 0x30000U +#define GRIOMMU_CAP2_TTYPE_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP2_TTYPE_MASK ) >> \ + GRIOMMU_CAP2_TTYPE_SHIFT ) +#define GRIOMMU_CAP2_TTYPE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP2_TTYPE_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP2_TTYPE_SHIFT ) & \ + GRIOMMU_CAP2_TTYPE_MASK ) ) +#define GRIOMMU_CAP2_TTYPE( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP2_TTYPE_SHIFT ) & \ + GRIOMMU_CAP2_TTYPE_MASK ) + +#define GRIOMMU_CAP2_TTAGBITS_SHIFT 8 +#define GRIOMMU_CAP2_TTAGBITS_MASK 0xff00U +#define GRIOMMU_CAP2_TTAGBITS_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP2_TTAGBITS_MASK ) >> \ + GRIOMMU_CAP2_TTAGBITS_SHIFT ) +#define GRIOMMU_CAP2_TTAGBITS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP2_TTAGBITS_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP2_TTAGBITS_SHIFT ) & \ + GRIOMMU_CAP2_TTAGBITS_MASK ) ) +#define GRIOMMU_CAP2_TTAGBITS( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP2_TTAGBITS_SHIFT ) & \ + GRIOMMU_CAP2_TTAGBITS_MASK ) + +#define GRIOMMU_CAP2_ISIZE_SHIFT 5 +#define GRIOMMU_CAP2_ISIZE_MASK 0xe0U +#define GRIOMMU_CAP2_ISIZE_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP2_ISIZE_MASK ) >> \ + GRIOMMU_CAP2_ISIZE_SHIFT ) +#define GRIOMMU_CAP2_ISIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP2_ISIZE_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP2_ISIZE_SHIFT ) & \ + GRIOMMU_CAP2_ISIZE_MASK ) ) +#define GRIOMMU_CAP2_ISIZE( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP2_ISIZE_SHIFT ) & \ + GRIOMMU_CAP2_ISIZE_MASK ) + +#define GRIOMMU_CAP2_TLBENT_SHIFT 0 +#define GRIOMMU_CAP2_TLBENT_MASK 0x1fU +#define GRIOMMU_CAP2_TLBENT_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CAP2_TLBENT_MASK ) >> \ + GRIOMMU_CAP2_TLBENT_SHIFT ) +#define GRIOMMU_CAP2_TLBENT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CAP2_TLBENT_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CAP2_TLBENT_SHIFT ) & \ + GRIOMMU_CAP2_TLBENT_MASK ) ) +#define GRIOMMU_CAP2_TLBENT( _val ) \ + ( ( ( _val ) << GRIOMMU_CAP2_TLBENT_SHIFT ) & \ + GRIOMMU_CAP2_TLBENT_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUCTRL Control register (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_CTRL_PGSZ_SHIFT 18 +#define GRIOMMU_CTRL_PGSZ_MASK 0x1c0000U +#define GRIOMMU_CTRL_PGSZ_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CTRL_PGSZ_MASK ) >> \ + GRIOMMU_CTRL_PGSZ_SHIFT ) +#define GRIOMMU_CTRL_PGSZ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CTRL_PGSZ_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CTRL_PGSZ_SHIFT ) & \ + GRIOMMU_CTRL_PGSZ_MASK ) ) +#define GRIOMMU_CTRL_PGSZ( _val ) \ + ( ( ( _val ) << GRIOMMU_CTRL_PGSZ_SHIFT ) & \ + GRIOMMU_CTRL_PGSZ_MASK ) + +#define GRIOMMU_CTRL_LB 0x20000U + +#define GRIOMMU_CTRL_SP 0x10000U + +#define GRIOMMU_CTRL_ITR_SHIFT 12 +#define GRIOMMU_CTRL_ITR_MASK 0xf000U +#define GRIOMMU_CTRL_ITR_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CTRL_ITR_MASK ) >> \ + GRIOMMU_CTRL_ITR_SHIFT ) +#define GRIOMMU_CTRL_ITR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CTRL_ITR_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CTRL_ITR_SHIFT ) & \ + GRIOMMU_CTRL_ITR_MASK ) ) +#define GRIOMMU_CTRL_ITR( _val ) \ + ( ( ( _val ) << GRIOMMU_CTRL_ITR_SHIFT ) & \ + GRIOMMU_CTRL_ITR_MASK ) + +#define GRIOMMU_CTRL_DP 0x800U + +#define GRIOMMU_CTRL_SIV 0x400U + +#define GRIOMMU_CTRL_HPROT_SHIFT 8 +#define GRIOMMU_CTRL_HPROT_MASK 0x300U +#define GRIOMMU_CTRL_HPROT_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CTRL_HPROT_MASK ) >> \ + GRIOMMU_CTRL_HPROT_SHIFT ) +#define GRIOMMU_CTRL_HPROT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CTRL_HPROT_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CTRL_HPROT_SHIFT ) & \ + GRIOMMU_CTRL_HPROT_MASK ) ) +#define GRIOMMU_CTRL_HPROT( _val ) \ + ( ( ( _val ) << GRIOMMU_CTRL_HPROT_SHIFT ) & \ + GRIOMMU_CTRL_HPROT_MASK ) + +#define GRIOMMU_CTRL_AU 0x80U + +#define GRIOMMU_CTRL_WP 0x40U + +#define GRIOMMU_CTRL_DM 0x20U + +#define GRIOMMU_CTRL_GS 0x10U + +#define GRIOMMU_CTRL_CE 0x8U + +#define GRIOMMU_CTRL_PM_SHIFT 1 +#define GRIOMMU_CTRL_PM_MASK 0x6U +#define GRIOMMU_CTRL_PM_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_CTRL_PM_MASK ) >> \ + GRIOMMU_CTRL_PM_SHIFT ) +#define GRIOMMU_CTRL_PM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_CTRL_PM_MASK ) | \ + ( ( ( _val ) << GRIOMMU_CTRL_PM_SHIFT ) & \ + GRIOMMU_CTRL_PM_MASK ) ) +#define GRIOMMU_CTRL_PM( _val ) \ + ( ( ( _val ) << GRIOMMU_CTRL_PM_SHIFT ) & \ + GRIOMMU_CTRL_PM_MASK ) + +#define GRIOMMU_CTRL_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUFLUSH TLB/cache flush register (FLUSH) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_FLUSH_FGRP_SHIFT 4 +#define GRIOMMU_FLUSH_FGRP_MASK 0xf0U +#define GRIOMMU_FLUSH_FGRP_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_FLUSH_FGRP_MASK ) >> \ + GRIOMMU_FLUSH_FGRP_SHIFT ) +#define GRIOMMU_FLUSH_FGRP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_FLUSH_FGRP_MASK ) | \ + ( ( ( _val ) << GRIOMMU_FLUSH_FGRP_SHIFT ) & \ + GRIOMMU_FLUSH_FGRP_MASK ) ) +#define GRIOMMU_FLUSH_FGRP( _val ) \ + ( ( ( _val ) << GRIOMMU_FLUSH_FGRP_SHIFT ) & \ + GRIOMMU_FLUSH_FGRP_MASK ) + +#define GRIOMMU_FLUSH_GF 0x2U + +#define GRIOMMU_FLUSH_F 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUSTATUS Status register (STATUS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_STATUS_PE 0x20U + +#define GRIOMMU_STATUS_DE 0x10U + +#define GRIOMMU_STATUS_FC 0x8U + +#define GRIOMMU_STATUS_FL 0x4U + +#define GRIOMMU_STATUS_AD 0x2U + +#define GRIOMMU_STATUS_TE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUIMASK Interrupt mask register (IMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_IMASK_PEI 0x20U + +#define GRIOMMU_IMASK_FCI 0x8U + +#define GRIOMMU_IMASK_FLI 0x4U + +#define GRIOMMU_IMASK_ADI 0x2U + +#define GRIOMMU_IMASK_TEI 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUAHBFAS AHB failing access register (AHBFAS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_AHBFAS_FADDR_31_5_SHIFT 5 +#define GRIOMMU_AHBFAS_FADDR_31_5_MASK 0xffffffe0U +#define GRIOMMU_AHBFAS_FADDR_31_5_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_AHBFAS_FADDR_31_5_MASK ) >> \ + GRIOMMU_AHBFAS_FADDR_31_5_SHIFT ) +#define GRIOMMU_AHBFAS_FADDR_31_5_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_AHBFAS_FADDR_31_5_MASK ) | \ + ( ( ( _val ) << GRIOMMU_AHBFAS_FADDR_31_5_SHIFT ) & \ + GRIOMMU_AHBFAS_FADDR_31_5_MASK ) ) +#define GRIOMMU_AHBFAS_FADDR_31_5( _val ) \ + ( ( ( _val ) << GRIOMMU_AHBFAS_FADDR_31_5_SHIFT ) & \ + GRIOMMU_AHBFAS_FADDR_31_5_MASK ) + +#define GRIOMMU_AHBFAS_FW 0x10U + +#define GRIOMMU_AHBFAS_FMASTER_SHIFT 0 +#define GRIOMMU_AHBFAS_FMASTER_MASK 0xfU +#define GRIOMMU_AHBFAS_FMASTER_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_AHBFAS_FMASTER_MASK ) >> \ + GRIOMMU_AHBFAS_FMASTER_SHIFT ) +#define GRIOMMU_AHBFAS_FMASTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_AHBFAS_FMASTER_MASK ) | \ + ( ( ( _val ) << GRIOMMU_AHBFAS_FMASTER_SHIFT ) & \ + GRIOMMU_AHBFAS_FMASTER_MASK ) ) +#define GRIOMMU_AHBFAS_FMASTER( _val ) \ + ( ( ( _val ) << GRIOMMU_AHBFAS_FMASTER_SHIFT ) & \ + GRIOMMU_AHBFAS_FMASTER_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUMSTCFG \ + * Master configuration register 0 - 9 (MSTCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_MSTCFG_VENDOR_SHIFT 24 +#define GRIOMMU_MSTCFG_VENDOR_MASK 0xff000000U +#define GRIOMMU_MSTCFG_VENDOR_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_MSTCFG_VENDOR_MASK ) >> \ + GRIOMMU_MSTCFG_VENDOR_SHIFT ) +#define GRIOMMU_MSTCFG_VENDOR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_MSTCFG_VENDOR_MASK ) | \ + ( ( ( _val ) << GRIOMMU_MSTCFG_VENDOR_SHIFT ) & \ + GRIOMMU_MSTCFG_VENDOR_MASK ) ) +#define GRIOMMU_MSTCFG_VENDOR( _val ) \ + ( ( ( _val ) << GRIOMMU_MSTCFG_VENDOR_SHIFT ) & \ + GRIOMMU_MSTCFG_VENDOR_MASK ) + +#define GRIOMMU_MSTCFG_DEVICE_SHIFT 12 +#define GRIOMMU_MSTCFG_DEVICE_MASK 0xfff000U +#define GRIOMMU_MSTCFG_DEVICE_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_MSTCFG_DEVICE_MASK ) >> \ + GRIOMMU_MSTCFG_DEVICE_SHIFT ) +#define GRIOMMU_MSTCFG_DEVICE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_MSTCFG_DEVICE_MASK ) | \ + ( ( ( _val ) << GRIOMMU_MSTCFG_DEVICE_SHIFT ) & \ + GRIOMMU_MSTCFG_DEVICE_MASK ) ) +#define GRIOMMU_MSTCFG_DEVICE( _val ) \ + ( ( ( _val ) << GRIOMMU_MSTCFG_DEVICE_SHIFT ) & \ + GRIOMMU_MSTCFG_DEVICE_MASK ) + +#define GRIOMMU_MSTCFG_BS 0x10U + +#define GRIOMMU_MSTCFG_GROUP_SHIFT 0 +#define GRIOMMU_MSTCFG_GROUP_MASK 0xfU +#define GRIOMMU_MSTCFG_GROUP_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_MSTCFG_GROUP_MASK ) >> \ + GRIOMMU_MSTCFG_GROUP_SHIFT ) +#define GRIOMMU_MSTCFG_GROUP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_MSTCFG_GROUP_MASK ) | \ + ( ( ( _val ) << GRIOMMU_MSTCFG_GROUP_SHIFT ) & \ + GRIOMMU_MSTCFG_GROUP_MASK ) ) +#define GRIOMMU_MSTCFG_GROUP( _val ) \ + ( ( ( _val ) << GRIOMMU_MSTCFG_GROUP_SHIFT ) & \ + GRIOMMU_MSTCFG_GROUP_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUGRPCTRL Group control register 0 - 7 (GRPCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_GRPCTRL_BASE_31_4_SHIFT 4 +#define GRIOMMU_GRPCTRL_BASE_31_4_MASK 0xfffffff0U +#define GRIOMMU_GRPCTRL_BASE_31_4_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_GRPCTRL_BASE_31_4_MASK ) >> \ + GRIOMMU_GRPCTRL_BASE_31_4_SHIFT ) +#define GRIOMMU_GRPCTRL_BASE_31_4_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_GRPCTRL_BASE_31_4_MASK ) | \ + ( ( ( _val ) << GRIOMMU_GRPCTRL_BASE_31_4_SHIFT ) & \ + GRIOMMU_GRPCTRL_BASE_31_4_MASK ) ) +#define GRIOMMU_GRPCTRL_BASE_31_4( _val ) \ + ( ( ( _val ) << GRIOMMU_GRPCTRL_BASE_31_4_SHIFT ) & \ + GRIOMMU_GRPCTRL_BASE_31_4_MASK ) + +#define GRIOMMU_GRPCTRL_P 0x2U + +#define GRIOMMU_GRPCTRL_AG 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUDIAGCTRL \ + * Diagnostic cache access register (DIAGCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_DIAGCTRL_DA 0x80000000U + +#define GRIOMMU_DIAGCTRL_RW 0x40000000U + +#define GRIOMMU_DIAGCTRL_DP 0x200000U + +#define GRIOMMU_DIAGCTRL_TP 0x100000U + +#define GRIOMMU_DIAGCTRL_SETADDR_SHIFT 0 +#define GRIOMMU_DIAGCTRL_SETADDR_MASK 0x7ffffU +#define GRIOMMU_DIAGCTRL_SETADDR_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_DIAGCTRL_SETADDR_MASK ) >> \ + GRIOMMU_DIAGCTRL_SETADDR_SHIFT ) +#define GRIOMMU_DIAGCTRL_SETADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_DIAGCTRL_SETADDR_MASK ) | \ + ( ( ( _val ) << GRIOMMU_DIAGCTRL_SETADDR_SHIFT ) & \ + GRIOMMU_DIAGCTRL_SETADDR_MASK ) ) +#define GRIOMMU_DIAGCTRL_SETADDR( _val ) \ + ( ( ( _val ) << GRIOMMU_DIAGCTRL_SETADDR_SHIFT ) & \ + GRIOMMU_DIAGCTRL_SETADDR_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUDIAGD \ + * Diagnostic cache access data register 0 - 7 (DIAGD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_DIAGD_CDATAN_SHIFT 0 +#define GRIOMMU_DIAGD_CDATAN_MASK 0xffffffffU +#define GRIOMMU_DIAGD_CDATAN_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_DIAGD_CDATAN_MASK ) >> \ + GRIOMMU_DIAGD_CDATAN_SHIFT ) +#define GRIOMMU_DIAGD_CDATAN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_DIAGD_CDATAN_MASK ) | \ + ( ( ( _val ) << GRIOMMU_DIAGD_CDATAN_SHIFT ) & \ + GRIOMMU_DIAGD_CDATAN_MASK ) ) +#define GRIOMMU_DIAGD_CDATAN( _val ) \ + ( ( ( _val ) << GRIOMMU_DIAGD_CDATAN_SHIFT ) & \ + GRIOMMU_DIAGD_CDATAN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUDIAGT \ + * Diagnostic cache access tag register (DIAGT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_DIAGT_TAG_SHIFT 1 +#define GRIOMMU_DIAGT_TAG_MASK 0xfffffffeU +#define GRIOMMU_DIAGT_TAG_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_DIAGT_TAG_MASK ) >> \ + GRIOMMU_DIAGT_TAG_SHIFT ) +#define GRIOMMU_DIAGT_TAG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_DIAGT_TAG_MASK ) | \ + ( ( ( _val ) << GRIOMMU_DIAGT_TAG_SHIFT ) & \ + GRIOMMU_DIAGT_TAG_MASK ) ) +#define GRIOMMU_DIAGT_TAG( _val ) \ + ( ( ( _val ) << GRIOMMU_DIAGT_TAG_SHIFT ) & \ + GRIOMMU_DIAGT_TAG_MASK ) + +#define GRIOMMU_DIAGT_V 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUDERRI Data RAM error injection register (DERRI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_DERRI_DPERRINJ_SHIFT 0 +#define GRIOMMU_DERRI_DPERRINJ_MASK 0xffffffffU +#define GRIOMMU_DERRI_DPERRINJ_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_DERRI_DPERRINJ_MASK ) >> \ + GRIOMMU_DERRI_DPERRINJ_SHIFT ) +#define GRIOMMU_DERRI_DPERRINJ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_DERRI_DPERRINJ_MASK ) | \ + ( ( ( _val ) << GRIOMMU_DERRI_DPERRINJ_SHIFT ) & \ + GRIOMMU_DERRI_DPERRINJ_MASK ) ) +#define GRIOMMU_DERRI_DPERRINJ( _val ) \ + ( ( ( _val ) << GRIOMMU_DERRI_DPERRINJ_SHIFT ) & \ + GRIOMMU_DERRI_DPERRINJ_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUTERRI Tag RAM error injection register (TERRI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_TERRI_TPERRINJ_SHIFT 0 +#define GRIOMMU_TERRI_TPERRINJ_MASK 0xffffffffU +#define GRIOMMU_TERRI_TPERRINJ_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_TERRI_TPERRINJ_MASK ) >> \ + GRIOMMU_TERRI_TPERRINJ_SHIFT ) +#define GRIOMMU_TERRI_TPERRINJ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_TERRI_TPERRINJ_MASK ) | \ + ( ( ( _val ) << GRIOMMU_TERRI_TPERRINJ_SHIFT ) & \ + GRIOMMU_TERRI_TPERRINJ_MASK ) ) +#define GRIOMMU_TERRI_TPERRINJ( _val ) \ + ( ( ( _val ) << GRIOMMU_TERRI_TPERRINJ_SHIFT ) & \ + GRIOMMU_TERRI_TPERRINJ_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUASMPCTRL \ + * ASMP access control registers 0 - 3 (ASMPCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_ASMPCTRL_FC 0x40000U + +#define GRIOMMU_ASMPCTRL_SC 0x20000U + +#define GRIOMMU_ASMPCTRL_MC 0x10000U + +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT 0 +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK 0xffffU +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_GET( _reg ) \ + ( ( ( _reg ) & GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) >> \ + GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT ) +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) | \ + ( ( ( _val ) << GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT ) & \ + GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) ) +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL( _val ) \ + ( ( ( _val ) << GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT ) & \ + GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GRIOMMU register block memory map. + */ +typedef struct griommu { + /** + * @brief See @ref RTEMSDeviceGRIOMMUCAP0. + */ + uint32_t cap0; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUCAP1. + */ + uint32_t cap1; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUCAP2. + */ + uint32_t cap2; + + uint32_t reserved_c_10; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUCTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUFLUSH. + */ + uint32_t flush; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUSTATUS. + */ + uint32_t status; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUIMASK. + */ + uint32_t imask; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUAHBFAS. + */ + uint32_t ahbfas; + + uint32_t reserved_24_40[ 7 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUMSTCFG. + */ + uint32_t mstcfg_0; + + uint32_t reserved_44_64[ 8 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUMSTCFG. + */ + uint32_t mstcfg_1; + + uint32_t reserved_68_80[ 6 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUGRPCTRL. + */ + uint32_t grpctrl_0; + + uint32_t reserved_84_9c[ 6 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUGRPCTRL. + */ + uint32_t grpctrl_1; + + uint32_t reserved_a0_c0[ 8 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUDIAGCTRL. + */ + uint32_t diagctrl; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUDIAGD. + */ + uint32_t diagd_0; + + uint32_t reserved_c8_e0[ 6 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUDIAGD. + */ + uint32_t diagd_1; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUDIAGT. + */ + uint32_t diagt; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUDERRI. + */ + uint32_t derri; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUTERRI. + */ + uint32_t terri; + + uint32_t reserved_f0_100[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUASMPCTRL. + */ + uint32_t asmpctrl_0; + + uint32_t reserved_104_10c[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUASMPCTRL. + */ + uint32_t asmpctrl_1; +} griommu; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRIOMMU_REGS_H */ diff --git a/bsps/include/grlib/griommu.h b/bsps/include/grlib/griommu.h index 2bafe4c513..c2f077d025 100644 --- a/bsps/include/grlib/griommu.h +++ b/bsps/include/grlib/griommu.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * GRIOMMU Driver Interface * * COPYRIGHT (c) 2017 * Cobham Gaisler AB * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * * OVERVIEW * ======== diff --git a/bsps/include/grlib/grlib.h b/bsps/include/grlib/grlib.h index 49d9999807..2a98d3a6d5 100644 --- a/bsps/include/grlib/grlib.h +++ b/bsps/include/grlib/grlib.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup amba @@ -8,9 +10,26 @@ * COPYRIGHT (c) 2012 * Aeroflex Gaisler * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRLIB_H__ diff --git a/bsps/include/grlib/grlib_impl.h b/bsps/include/grlib/grlib_impl.h index 919f6d69ab..1f6c60c05b 100644 --- a/bsps/include/grlib/grlib_impl.h +++ b/bsps/include/grlib/grlib_impl.h @@ -1,9 +1,28 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * Copyright (C) 2017 Cobham Gaisler AB * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef GRLIB_IMPL_H @@ -66,24 +85,24 @@ extern "C" { #if (((__RTEMS_MAJOR__ << 16) | (__RTEMS_MINOR__ << 8) | __RTEMS_REVISION__) >= 0x050000) -RTEMS_INLINE_ROUTINE void *grlib_malloc(size_t size) +static inline void *grlib_malloc(size_t size) { return rtems_malloc(size); } -RTEMS_INLINE_ROUTINE void *grlib_calloc(size_t nelem, size_t elsize) +static inline void *grlib_calloc(size_t nelem, size_t elsize) { return rtems_calloc(nelem, elsize); } #else -RTEMS_INLINE_ROUTINE void *grlib_malloc(size_t size) +static inline void *grlib_malloc(size_t size) { return malloc(size); } -RTEMS_INLINE_ROUTINE void *grlib_calloc(size_t nelem, size_t elsize) +static inline void *grlib_calloc(size_t nelem, size_t elsize) { return calloc(nelem, elsize); } @@ -92,7 +111,7 @@ RTEMS_INLINE_ROUTINE void *grlib_calloc(size_t nelem, size_t elsize) #ifdef __sparc__ -RTEMS_INLINE_ROUTINE unsigned char grlib_read_uncached8(unsigned int address) +static inline unsigned char grlib_read_uncached8(unsigned int address) { unsigned char tmp; __asm__ (" lduba [%1]1, %0 " @@ -102,7 +121,7 @@ RTEMS_INLINE_ROUTINE unsigned char grlib_read_uncached8(unsigned int address) return tmp; } -RTEMS_INLINE_ROUTINE unsigned short grlib_read_uncached16(unsigned int addr) { +static inline unsigned short grlib_read_uncached16(unsigned int addr) { unsigned short tmp; __asm__ (" lduha [%1]1, %0 " : "=r"(tmp) @@ -112,7 +131,7 @@ RTEMS_INLINE_ROUTINE unsigned short grlib_read_uncached16(unsigned int addr) { } -RTEMS_INLINE_ROUTINE unsigned int grlib_read_uncached32(unsigned int address) +static inline unsigned int grlib_read_uncached32(unsigned int address) { unsigned int tmp; __asm__ (" lda [%1]1, %0 " @@ -122,7 +141,7 @@ RTEMS_INLINE_ROUTINE unsigned int grlib_read_uncached32(unsigned int address) return tmp; } -RTEMS_INLINE_ROUTINE uint64_t grlib_read_uncached64(uint64_t *address) +static inline uint64_t grlib_read_uncached64(uint64_t *address) { uint64_t tmp; __asm__ (" ldda [%1]1, %0 " @@ -147,7 +166,7 @@ static __inline__ unsigned short grlib_read_uncached16(unsigned int address) { return tmp; } -RTEMS_INLINE_ROUTINE unsigned int grlib_read_uncached32(unsigned int address) +static inline unsigned int grlib_read_uncached32(unsigned int address) { unsigned int tmp = (*(volatile unsigned int *)(address)); return tmp; diff --git a/bsps/include/grlib/grpci.h b/bsps/include/grlib/grpci.h index 2321706200..5c05d0bdc4 100644 --- a/bsps/include/grlib/grpci.h +++ b/bsps/include/grlib/grpci.h @@ -1,3 +1,32 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * COPYRIGHT (c) 2015. + * Cobham Gaisler. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + #ifndef __GRPCI_H__ #define __GRPCI_H__ diff --git a/bsps/include/grlib/grpci2-regs.h b/bsps/include/grlib/grpci2-regs.h new file mode 100644 index 0000000000..380e24a4cf --- /dev/null +++ b/bsps/include/grlib/grpci2-regs.h @@ -0,0 +1,875 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRPCI2 + * + * @brief This header file defines the GRPCI2 register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grpci2-header */ + +#ifndef _GRLIB_GRPCI2_REGS_H +#define _GRLIB_GRPCI2_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grpci2 */ + +/** + * @defgroup RTEMSDeviceGRPCI2 GRPCI2 + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRPCI2 interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRPCI2CTRL Control register (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_CTRL_RE 0x80000000U + +#define GRPCI2_CTRL_MR 0x40000000U + +#define GRPCI2_CTRL_TR 0x20000000U + +#define GRPCI2_CTRL_SI 0x8000000U + +#define GRPCI2_CTRL_PE 0x4000000U + +#define GRPCI2_CTRL_ER 0x2000000U + +#define GRPCI2_CTRL_EI 0x1000000U + +#define GRPCI2_CTRL_BUS_NUMBER_SHIFT 16 +#define GRPCI2_CTRL_BUS_NUMBER_MASK 0xff0000U +#define GRPCI2_CTRL_BUS_NUMBER_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_CTRL_BUS_NUMBER_MASK ) >> \ + GRPCI2_CTRL_BUS_NUMBER_SHIFT ) +#define GRPCI2_CTRL_BUS_NUMBER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_CTRL_BUS_NUMBER_MASK ) | \ + ( ( ( _val ) << GRPCI2_CTRL_BUS_NUMBER_SHIFT ) & \ + GRPCI2_CTRL_BUS_NUMBER_MASK ) ) +#define GRPCI2_CTRL_BUS_NUMBER( _val ) \ + ( ( ( _val ) << GRPCI2_CTRL_BUS_NUMBER_SHIFT ) & \ + GRPCI2_CTRL_BUS_NUMBER_MASK ) + +#define GRPCI2_CTRL_DFA 0x800U + +#define GRPCI2_CTRL_IB 0x400U + +#define GRPCI2_CTRL_CB 0x200U + +#define GRPCI2_CTRL_DIF 0x100U + +#define GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT 4 +#define GRPCI2_CTRL_DEVICE_INT_MASK_MASK 0xf0U +#define GRPCI2_CTRL_DEVICE_INT_MASK_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) >> \ + GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT ) +#define GRPCI2_CTRL_DEVICE_INT_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) | \ + ( ( ( _val ) << GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT ) & \ + GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) ) +#define GRPCI2_CTRL_DEVICE_INT_MASK( _val ) \ + ( ( ( _val ) << GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT ) & \ + GRPCI2_CTRL_DEVICE_INT_MASK_MASK ) + +#define GRPCI2_CTRL_HOST_INT_MASK_SHIFT 0 +#define GRPCI2_CTRL_HOST_INT_MASK_MASK 0xfU +#define GRPCI2_CTRL_HOST_INT_MASK_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_CTRL_HOST_INT_MASK_MASK ) >> \ + GRPCI2_CTRL_HOST_INT_MASK_SHIFT ) +#define GRPCI2_CTRL_HOST_INT_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_CTRL_HOST_INT_MASK_MASK ) | \ + ( ( ( _val ) << GRPCI2_CTRL_HOST_INT_MASK_SHIFT ) & \ + GRPCI2_CTRL_HOST_INT_MASK_MASK ) ) +#define GRPCI2_CTRL_HOST_INT_MASK( _val ) \ + ( ( ( _val ) << GRPCI2_CTRL_HOST_INT_MASK_SHIFT ) & \ + GRPCI2_CTRL_HOST_INT_MASK_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2STATCAP Status and Capability register (STATCAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_STATCAP_HOST 0x80000000U + +#define GRPCI2_STATCAP_MST 0x40000000U + +#define GRPCI2_STATCAP_TAR 0x20000000U + +#define GRPCI2_STATCAP_DMA 0x10000000U + +#define GRPCI2_STATCAP_DI 0x8000000U + +#define GRPCI2_STATCAP_HI 0x4000000U + +#define GRPCI2_STATCAP_IRQ_MODE_SHIFT 24 +#define GRPCI2_STATCAP_IRQ_MODE_MASK 0x3000000U +#define GRPCI2_STATCAP_IRQ_MODE_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_STATCAP_IRQ_MODE_MASK ) >> \ + GRPCI2_STATCAP_IRQ_MODE_SHIFT ) +#define GRPCI2_STATCAP_IRQ_MODE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_STATCAP_IRQ_MODE_MASK ) | \ + ( ( ( _val ) << GRPCI2_STATCAP_IRQ_MODE_SHIFT ) & \ + GRPCI2_STATCAP_IRQ_MODE_MASK ) ) +#define GRPCI2_STATCAP_IRQ_MODE( _val ) \ + ( ( ( _val ) << GRPCI2_STATCAP_IRQ_MODE_SHIFT ) & \ + GRPCI2_STATCAP_IRQ_MODE_MASK ) + +#define GRPCI2_STATCAP_TRACE 0x800000U + +#define GRPCI2_STATCAP_CFGDO 0x100000U + +#define GRPCI2_STATCAP_CFGER 0x80000U + +#define GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT 12 +#define GRPCI2_STATCAP_CORE_INT_STATUS_MASK 0x7f000U +#define GRPCI2_STATCAP_CORE_INT_STATUS_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) >> \ + GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT ) +#define GRPCI2_STATCAP_CORE_INT_STATUS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) | \ + ( ( ( _val ) << GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT ) & \ + GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) ) +#define GRPCI2_STATCAP_CORE_INT_STATUS( _val ) \ + ( ( ( _val ) << GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT ) & \ + GRPCI2_STATCAP_CORE_INT_STATUS_MASK ) + +#define GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT 8 +#define GRPCI2_STATCAP_HOST_INT_STATUS_MASK 0xf00U +#define GRPCI2_STATCAP_HOST_INT_STATUS_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) >> \ + GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT ) +#define GRPCI2_STATCAP_HOST_INT_STATUS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) | \ + ( ( ( _val ) << GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT ) & \ + GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) ) +#define GRPCI2_STATCAP_HOST_INT_STATUS( _val ) \ + ( ( ( _val ) << GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT ) & \ + GRPCI2_STATCAP_HOST_INT_STATUS_MASK ) + +#define GRPCI2_STATCAP_FDEPTH_SHIFT 2 +#define GRPCI2_STATCAP_FDEPTH_MASK 0x1cU +#define GRPCI2_STATCAP_FDEPTH_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_STATCAP_FDEPTH_MASK ) >> \ + GRPCI2_STATCAP_FDEPTH_SHIFT ) +#define GRPCI2_STATCAP_FDEPTH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_STATCAP_FDEPTH_MASK ) | \ + ( ( ( _val ) << GRPCI2_STATCAP_FDEPTH_SHIFT ) & \ + GRPCI2_STATCAP_FDEPTH_MASK ) ) +#define GRPCI2_STATCAP_FDEPTH( _val ) \ + ( ( ( _val ) << GRPCI2_STATCAP_FDEPTH_SHIFT ) & \ + GRPCI2_STATCAP_FDEPTH_MASK ) + +#define GRPCI2_STATCAP_FNUM_SHIFT 0 +#define GRPCI2_STATCAP_FNUM_MASK 0x3U +#define GRPCI2_STATCAP_FNUM_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_STATCAP_FNUM_MASK ) >> \ + GRPCI2_STATCAP_FNUM_SHIFT ) +#define GRPCI2_STATCAP_FNUM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_STATCAP_FNUM_MASK ) | \ + ( ( ( _val ) << GRPCI2_STATCAP_FNUM_SHIFT ) & \ + GRPCI2_STATCAP_FNUM_MASK ) ) +#define GRPCI2_STATCAP_FNUM( _val ) \ + ( ( ( _val ) << GRPCI2_STATCAP_FNUM_SHIFT ) & \ + GRPCI2_STATCAP_FNUM_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2BCIM PCI master prefetch burst limit (BCIM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT 16 +#define GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK 0xffff0000U +#define GRPCI2_BCIM_AHB_MASTER_UNMASK_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) >> \ + GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT ) +#define GRPCI2_BCIM_AHB_MASTER_UNMASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) | \ + ( ( ( _val ) << GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT ) & \ + GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) ) +#define GRPCI2_BCIM_AHB_MASTER_UNMASK( _val ) \ + ( ( ( _val ) << GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT ) & \ + GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK ) + +#define GRPCI2_BCIM_BURST_LENGTH_SHIFT 0 +#define GRPCI2_BCIM_BURST_LENGTH_MASK 0xffU +#define GRPCI2_BCIM_BURST_LENGTH_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_BCIM_BURST_LENGTH_MASK ) >> \ + GRPCI2_BCIM_BURST_LENGTH_SHIFT ) +#define GRPCI2_BCIM_BURST_LENGTH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_BCIM_BURST_LENGTH_MASK ) | \ + ( ( ( _val ) << GRPCI2_BCIM_BURST_LENGTH_SHIFT ) & \ + GRPCI2_BCIM_BURST_LENGTH_MASK ) ) +#define GRPCI2_BCIM_BURST_LENGTH( _val ) \ + ( ( ( _val ) << GRPCI2_BCIM_BURST_LENGTH_SHIFT ) & \ + GRPCI2_BCIM_BURST_LENGTH_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2AHB2PCI AHB to PCI mapping for PCI IO (AHB2PCI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT 16 +#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK 0xffff0000U +#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) >> \ + GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT ) +#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) | \ + ( ( ( _val ) << GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT ) & \ + GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) ) +#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO( _val ) \ + ( ( ( _val ) << GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT ) & \ + GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2DMACTRL DMA control and status register (DMACTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_DMACTRL_SAFE 0x80000000U + +#define GRPCI2_DMACTRL_CHIRQ_SHIFT 12 +#define GRPCI2_DMACTRL_CHIRQ_MASK 0xff000U +#define GRPCI2_DMACTRL_CHIRQ_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_DMACTRL_CHIRQ_MASK ) >> \ + GRPCI2_DMACTRL_CHIRQ_SHIFT ) +#define GRPCI2_DMACTRL_CHIRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_DMACTRL_CHIRQ_MASK ) | \ + ( ( ( _val ) << GRPCI2_DMACTRL_CHIRQ_SHIFT ) & \ + GRPCI2_DMACTRL_CHIRQ_MASK ) ) +#define GRPCI2_DMACTRL_CHIRQ( _val ) \ + ( ( ( _val ) << GRPCI2_DMACTRL_CHIRQ_SHIFT ) & \ + GRPCI2_DMACTRL_CHIRQ_MASK ) + +#define GRPCI2_DMACTRL_MA 0x800U + +#define GRPCI2_DMACTRL_TA 0x400U + +#define GRPCI2_DMACTRL_PE 0x200U + +#define GRPCI2_DMACTRL_AE 0x100U + +#define GRPCI2_DMACTRL_DE 0x80U + +#define GRPCI2_DMACTRL_NUMCH_SHIFT 4 +#define GRPCI2_DMACTRL_NUMCH_MASK 0x70U +#define GRPCI2_DMACTRL_NUMCH_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_DMACTRL_NUMCH_MASK ) >> \ + GRPCI2_DMACTRL_NUMCH_SHIFT ) +#define GRPCI2_DMACTRL_NUMCH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_DMACTRL_NUMCH_MASK ) | \ + ( ( ( _val ) << GRPCI2_DMACTRL_NUMCH_SHIFT ) & \ + GRPCI2_DMACTRL_NUMCH_MASK ) ) +#define GRPCI2_DMACTRL_NUMCH( _val ) \ + ( ( ( _val ) << GRPCI2_DMACTRL_NUMCH_SHIFT ) & \ + GRPCI2_DMACTRL_NUMCH_MASK ) + +#define GRPCI2_DMACTRL_ACTIVE 0x8U + +#define GRPCI2_DMACTRL_DIS 0x4U + +#define GRPCI2_DMACTRL_IE 0x2U + +#define GRPCI2_DMACTRL_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2DMABASE \ + * DMA descriptor base address register (DMABASE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_DMABASE_BASE_SHIFT 0 +#define GRPCI2_DMABASE_BASE_MASK 0xffffffffU +#define GRPCI2_DMABASE_BASE_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_DMABASE_BASE_MASK ) >> \ + GRPCI2_DMABASE_BASE_SHIFT ) +#define GRPCI2_DMABASE_BASE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_DMABASE_BASE_MASK ) | \ + ( ( ( _val ) << GRPCI2_DMABASE_BASE_SHIFT ) & \ + GRPCI2_DMABASE_BASE_MASK ) ) +#define GRPCI2_DMABASE_BASE( _val ) \ + ( ( ( _val ) << GRPCI2_DMABASE_BASE_SHIFT ) & \ + GRPCI2_DMABASE_BASE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2DMACHAN DMA channel active register (DMACHAN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_DMACHAN_CHAN_SHIFT 0 +#define GRPCI2_DMACHAN_CHAN_MASK 0xffffffffU +#define GRPCI2_DMACHAN_CHAN_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_DMACHAN_CHAN_MASK ) >> \ + GRPCI2_DMACHAN_CHAN_SHIFT ) +#define GRPCI2_DMACHAN_CHAN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_DMACHAN_CHAN_MASK ) | \ + ( ( ( _val ) << GRPCI2_DMACHAN_CHAN_SHIFT ) & \ + GRPCI2_DMACHAN_CHAN_MASK ) ) +#define GRPCI2_DMACHAN_CHAN( _val ) \ + ( ( ( _val ) << GRPCI2_DMACHAN_CHAN_SHIFT ) & \ + GRPCI2_DMACHAN_CHAN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2PCI2AHB \ + * PCI BAR to AHB address mapping register (PCI2AHB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_PCI2AHB_ADDR_SHIFT 0 +#define GRPCI2_PCI2AHB_ADDR_MASK 0xffffffffU +#define GRPCI2_PCI2AHB_ADDR_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_PCI2AHB_ADDR_MASK ) >> \ + GRPCI2_PCI2AHB_ADDR_SHIFT ) +#define GRPCI2_PCI2AHB_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_PCI2AHB_ADDR_MASK ) | \ + ( ( ( _val ) << GRPCI2_PCI2AHB_ADDR_SHIFT ) & \ + GRPCI2_PCI2AHB_ADDR_MASK ) ) +#define GRPCI2_PCI2AHB_ADDR( _val ) \ + ( ( ( _val ) << GRPCI2_PCI2AHB_ADDR_SHIFT ) & \ + GRPCI2_PCI2AHB_ADDR_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2AHBM2PCI \ + * AHB master to PCI memory address mapping register (AHBM2PCI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_AHBM2PCI_ADDR_SHIFT 0 +#define GRPCI2_AHBM2PCI_ADDR_MASK 0xffffffffU +#define GRPCI2_AHBM2PCI_ADDR_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_AHBM2PCI_ADDR_MASK ) >> \ + GRPCI2_AHBM2PCI_ADDR_SHIFT ) +#define GRPCI2_AHBM2PCI_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_AHBM2PCI_ADDR_MASK ) | \ + ( ( ( _val ) << GRPCI2_AHBM2PCI_ADDR_SHIFT ) & \ + GRPCI2_AHBM2PCI_ADDR_MASK ) ) +#define GRPCI2_AHBM2PCI_ADDR( _val ) \ + ( ( ( _val ) << GRPCI2_AHBM2PCI_ADDR_SHIFT ) & \ + GRPCI2_AHBM2PCI_ADDR_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TCTRC \ + * PCI trace Control and Status register (TCTRC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TCTRC_TRIG_INDEX_SHIFT 16 +#define GRPCI2_TCTRC_TRIG_INDEX_MASK 0xffff0000U +#define GRPCI2_TCTRC_TRIG_INDEX_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_TCTRC_TRIG_INDEX_MASK ) >> \ + GRPCI2_TCTRC_TRIG_INDEX_SHIFT ) +#define GRPCI2_TCTRC_TRIG_INDEX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TCTRC_TRIG_INDEX_MASK ) | \ + ( ( ( _val ) << GRPCI2_TCTRC_TRIG_INDEX_SHIFT ) & \ + GRPCI2_TCTRC_TRIG_INDEX_MASK ) ) +#define GRPCI2_TCTRC_TRIG_INDEX( _val ) \ + ( ( ( _val ) << GRPCI2_TCTRC_TRIG_INDEX_SHIFT ) & \ + GRPCI2_TCTRC_TRIG_INDEX_MASK ) + +#define GRPCI2_TCTRC_AR 0x8000U + +#define GRPCI2_TCTRC_EN 0x4000U + +#define GRPCI2_TCTRC_DEPTH_SHIFT 4 +#define GRPCI2_TCTRC_DEPTH_MASK 0xff0U +#define GRPCI2_TCTRC_DEPTH_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_TCTRC_DEPTH_MASK ) >> \ + GRPCI2_TCTRC_DEPTH_SHIFT ) +#define GRPCI2_TCTRC_DEPTH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TCTRC_DEPTH_MASK ) | \ + ( ( ( _val ) << GRPCI2_TCTRC_DEPTH_SHIFT ) & \ + GRPCI2_TCTRC_DEPTH_MASK ) ) +#define GRPCI2_TCTRC_DEPTH( _val ) \ + ( ( ( _val ) << GRPCI2_TCTRC_DEPTH_SHIFT ) & \ + GRPCI2_TCTRC_DEPTH_MASK ) + +#define GRPCI2_TCTRC_SO 0x2U + +#define GRPCI2_TCTRC_SA 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TMODE PCI trace counter and mode register (TMODE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TMODE_TRACING_MODE_SHIFT 24 +#define GRPCI2_TMODE_TRACING_MODE_MASK 0xf000000U +#define GRPCI2_TMODE_TRACING_MODE_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_TMODE_TRACING_MODE_MASK ) >> \ + GRPCI2_TMODE_TRACING_MODE_SHIFT ) +#define GRPCI2_TMODE_TRACING_MODE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TMODE_TRACING_MODE_MASK ) | \ + ( ( ( _val ) << GRPCI2_TMODE_TRACING_MODE_SHIFT ) & \ + GRPCI2_TMODE_TRACING_MODE_MASK ) ) +#define GRPCI2_TMODE_TRACING_MODE( _val ) \ + ( ( ( _val ) << GRPCI2_TMODE_TRACING_MODE_SHIFT ) & \ + GRPCI2_TMODE_TRACING_MODE_MASK ) + +#define GRPCI2_TMODE_TRIG_COUNT_SHIFT 16 +#define GRPCI2_TMODE_TRIG_COUNT_MASK 0xff0000U +#define GRPCI2_TMODE_TRIG_COUNT_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_TMODE_TRIG_COUNT_MASK ) >> \ + GRPCI2_TMODE_TRIG_COUNT_SHIFT ) +#define GRPCI2_TMODE_TRIG_COUNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TMODE_TRIG_COUNT_MASK ) | \ + ( ( ( _val ) << GRPCI2_TMODE_TRIG_COUNT_SHIFT ) & \ + GRPCI2_TMODE_TRIG_COUNT_MASK ) ) +#define GRPCI2_TMODE_TRIG_COUNT( _val ) \ + ( ( ( _val ) << GRPCI2_TMODE_TRIG_COUNT_SHIFT ) & \ + GRPCI2_TMODE_TRIG_COUNT_MASK ) + +#define GRPCI2_TMODE_DELAYED_STOP_SHIFT 0 +#define GRPCI2_TMODE_DELAYED_STOP_MASK 0xffffU +#define GRPCI2_TMODE_DELAYED_STOP_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_TMODE_DELAYED_STOP_MASK ) >> \ + GRPCI2_TMODE_DELAYED_STOP_SHIFT ) +#define GRPCI2_TMODE_DELAYED_STOP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TMODE_DELAYED_STOP_MASK ) | \ + ( ( ( _val ) << GRPCI2_TMODE_DELAYED_STOP_SHIFT ) & \ + GRPCI2_TMODE_DELAYED_STOP_MASK ) ) +#define GRPCI2_TMODE_DELAYED_STOP( _val ) \ + ( ( ( _val ) << GRPCI2_TMODE_DELAYED_STOP_SHIFT ) & \ + GRPCI2_TMODE_DELAYED_STOP_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TADP PCI trace AD pattern register (TADP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TADP_PATTERN_SHIFT 0 +#define GRPCI2_TADP_PATTERN_MASK 0xffffffffU +#define GRPCI2_TADP_PATTERN_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_TADP_PATTERN_MASK ) >> \ + GRPCI2_TADP_PATTERN_SHIFT ) +#define GRPCI2_TADP_PATTERN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TADP_PATTERN_MASK ) | \ + ( ( ( _val ) << GRPCI2_TADP_PATTERN_SHIFT ) & \ + GRPCI2_TADP_PATTERN_MASK ) ) +#define GRPCI2_TADP_PATTERN( _val ) \ + ( ( ( _val ) << GRPCI2_TADP_PATTERN_SHIFT ) & \ + GRPCI2_TADP_PATTERN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TADM PCI trace AD mask register (TADM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TADM_MASK_SHIFT 0 +#define GRPCI2_TADM_MASK_MASK 0xffffffffU +#define GRPCI2_TADM_MASK_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_TADM_MASK_MASK ) >> \ + GRPCI2_TADM_MASK_SHIFT ) +#define GRPCI2_TADM_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TADM_MASK_MASK ) | \ + ( ( ( _val ) << GRPCI2_TADM_MASK_SHIFT ) & \ + GRPCI2_TADM_MASK_MASK ) ) +#define GRPCI2_TADM_MASK( _val ) \ + ( ( ( _val ) << GRPCI2_TADM_MASK_SHIFT ) & \ + GRPCI2_TADM_MASK_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TCP PCI trace Ctrl signal pattern register (TCP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TCP_CBE_3_0_SHIFT 16 +#define GRPCI2_TCP_CBE_3_0_MASK 0xf0000U +#define GRPCI2_TCP_CBE_3_0_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_TCP_CBE_3_0_MASK ) >> \ + GRPCI2_TCP_CBE_3_0_SHIFT ) +#define GRPCI2_TCP_CBE_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TCP_CBE_3_0_MASK ) | \ + ( ( ( _val ) << GRPCI2_TCP_CBE_3_0_SHIFT ) & \ + GRPCI2_TCP_CBE_3_0_MASK ) ) +#define GRPCI2_TCP_CBE_3_0( _val ) \ + ( ( ( _val ) << GRPCI2_TCP_CBE_3_0_SHIFT ) & \ + GRPCI2_TCP_CBE_3_0_MASK ) + +#define GRPCI2_TCP_FRAME 0x8000U + +#define GRPCI2_TCP_IRDY 0x4000U + +#define GRPCI2_TCP_TRDY 0x2000U + +#define GRPCI2_TCP_STOP 0x1000U + +#define GRPCI2_TCP_DEVSEL 0x800U + +#define GRPCI2_TCP_PAR 0x400U + +#define GRPCI2_TCP_PERR 0x200U + +#define GRPCI2_TCP_SERR 0x100U + +#define GRPCI2_TCP_IDSEL 0x80U + +#define GRPCI2_TCP_REQ 0x40U + +#define GRPCI2_TCP_GNT 0x20U + +#define GRPCI2_TCP_LOCK 0x10U + +#define GRPCI2_TCP_RST 0x8U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TCM PCI trace Ctrl signal mask register (TCM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TCM_CBE_3_0_SHIFT 16 +#define GRPCI2_TCM_CBE_3_0_MASK 0xf0000U +#define GRPCI2_TCM_CBE_3_0_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_TCM_CBE_3_0_MASK ) >> \ + GRPCI2_TCM_CBE_3_0_SHIFT ) +#define GRPCI2_TCM_CBE_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TCM_CBE_3_0_MASK ) | \ + ( ( ( _val ) << GRPCI2_TCM_CBE_3_0_SHIFT ) & \ + GRPCI2_TCM_CBE_3_0_MASK ) ) +#define GRPCI2_TCM_CBE_3_0( _val ) \ + ( ( ( _val ) << GRPCI2_TCM_CBE_3_0_SHIFT ) & \ + GRPCI2_TCM_CBE_3_0_MASK ) + +#define GRPCI2_TCM_FRAME 0x8000U + +#define GRPCI2_TCM_IRDY 0x4000U + +#define GRPCI2_TCM_TRDY 0x2000U + +#define GRPCI2_TCM_STOP 0x1000U + +#define GRPCI2_TCM_DEVSEL 0x800U + +#define GRPCI2_TCM_PAR 0x400U + +#define GRPCI2_TCM_PERR 0x200U + +#define GRPCI2_TCM_SERR 0x100U + +#define GRPCI2_TCM_IDSEL 0x80U + +#define GRPCI2_TCM_REQ 0x40U + +#define GRPCI2_TCM_GNT 0x20U + +#define GRPCI2_TCM_LOCK 0x10U + +#define GRPCI2_TCM_RST 0x8U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TADS PCI trace PCI AD state register (TADS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TADS_SIGNAL_SHIFT 0 +#define GRPCI2_TADS_SIGNAL_MASK 0xffffffffU +#define GRPCI2_TADS_SIGNAL_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_TADS_SIGNAL_MASK ) >> \ + GRPCI2_TADS_SIGNAL_SHIFT ) +#define GRPCI2_TADS_SIGNAL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TADS_SIGNAL_MASK ) | \ + ( ( ( _val ) << GRPCI2_TADS_SIGNAL_SHIFT ) & \ + GRPCI2_TADS_SIGNAL_MASK ) ) +#define GRPCI2_TADS_SIGNAL( _val ) \ + ( ( ( _val ) << GRPCI2_TADS_SIGNAL_SHIFT ) & \ + GRPCI2_TADS_SIGNAL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TCS \ + * PCI trace PCI Ctrl signal state register (TCS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TCS_CBE_3_0_SHIFT 16 +#define GRPCI2_TCS_CBE_3_0_MASK 0xf0000U +#define GRPCI2_TCS_CBE_3_0_GET( _reg ) \ + ( ( ( _reg ) & GRPCI2_TCS_CBE_3_0_MASK ) >> \ + GRPCI2_TCS_CBE_3_0_SHIFT ) +#define GRPCI2_TCS_CBE_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRPCI2_TCS_CBE_3_0_MASK ) | \ + ( ( ( _val ) << GRPCI2_TCS_CBE_3_0_SHIFT ) & \ + GRPCI2_TCS_CBE_3_0_MASK ) ) +#define GRPCI2_TCS_CBE_3_0( _val ) \ + ( ( ( _val ) << GRPCI2_TCS_CBE_3_0_SHIFT ) & \ + GRPCI2_TCS_CBE_3_0_MASK ) + +#define GRPCI2_TCS_FRAME 0x8000U + +#define GRPCI2_TCS_IRDY 0x4000U + +#define GRPCI2_TCS_TRDY 0x2000U + +#define GRPCI2_TCS_STOP 0x1000U + +#define GRPCI2_TCS_DEVSEL 0x800U + +#define GRPCI2_TCS_PAR 0x400U + +#define GRPCI2_TCS_PERR 0x200U + +#define GRPCI2_TCS_SERR 0x100U + +#define GRPCI2_TCS_IDSEL 0x80U + +#define GRPCI2_TCS_REQ 0x40U + +#define GRPCI2_TCS_GNT 0x20U + +#define GRPCI2_TCS_LOCK 0x10U + +#define GRPCI2_TCS_RST 0x8U + +/** @} */ + +/** + * @brief This structure defines the GRPCI2 register block memory map. + */ +typedef struct grpci2 { + /** + * @brief See @ref RTEMSDeviceGRPCI2CTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSDeviceGRPCI2STATCAP. + */ + uint32_t statcap; + + /** + * @brief See @ref RTEMSDeviceGRPCI2BCIM. + */ + uint32_t bcim; + + /** + * @brief See @ref RTEMSDeviceGRPCI2AHB2PCI. + */ + uint32_t ahb2pci; + + /** + * @brief See @ref RTEMSDeviceGRPCI2DMACTRL. + */ + uint32_t dmactrl; + + /** + * @brief See @ref RTEMSDeviceGRPCI2DMABASE. + */ + uint32_t dmabase; + + /** + * @brief See @ref RTEMSDeviceGRPCI2DMACHAN. + */ + uint32_t dmachan; + + uint32_t reserved_1c_20; + + /** + * @brief See @ref RTEMSDeviceGRPCI2PCI2AHB. + */ + uint32_t pci2ahb_0; + + uint32_t reserved_24_34[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGRPCI2PCI2AHB. + */ + uint32_t pci2ahb_1; + + uint32_t reserved_38_40[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRPCI2AHBM2PCI. + */ + uint32_t ahbm2pci_0; + + uint32_t reserved_44_7c[ 14 ]; + + /** + * @brief See @ref RTEMSDeviceGRPCI2AHBM2PCI. + */ + uint32_t ahbm2pci_1; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TCTRC. + */ + uint32_t tctrc; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TMODE. + */ + uint32_t tmode; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TADP. + */ + uint32_t tadp; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TADM. + */ + uint32_t tadm; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TCP. + */ + uint32_t tcp; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TCM. + */ + uint32_t tcm; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TADS. + */ + uint32_t tads; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TCS. + */ + uint32_t tcs; +} grpci2; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRPCI2_REGS_H */ diff --git a/bsps/include/grlib/grpci2.h b/bsps/include/grlib/grpci2.h index c356b5641f..871bbae6a9 100644 --- a/bsps/include/grlib/grpci2.h +++ b/bsps/include/grlib/grpci2.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GRLIB GRPCI2 PCI HOST driver. * * COPYRIGHT (c) 2011 * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRPCI2_H__ diff --git a/bsps/include/grlib/grpci2dma.h b/bsps/include/grlib/grpci2dma.h index c1a2663a86..4e27c61d9b 100644 --- a/bsps/include/grlib/grpci2dma.h +++ b/bsps/include/grlib/grpci2dma.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * GRPCI2 DMA Driver * * COPYRIGHT (c) 2017 * Cobham Gaisler AB * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * * OVERVIEW * ======== diff --git a/bsps/include/grlib/grpwm.h b/bsps/include/grlib/grpwm.h index 6898f8ac2e..ab9d7a91e4 100644 --- a/bsps/include/grlib/grpwm.h +++ b/bsps/include/grlib/grpwm.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * GRPWM PWM Driver interface. * * COPYRIGHT (c) 2009. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRPWM_H__ diff --git a/bsps/include/grlib/grslink.h b/bsps/include/grlib/grslink.h index 575a24aee4..385f1cced0 100644 --- a/bsps/include/grlib/grslink.h +++ b/bsps/include/grlib/grslink.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * Header file for RTEMS GRSLINK SLINK master driver * * COPYRIGHT (c) 2009. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRSLINK_H__ diff --git a/bsps/include/grlib/grspw.h b/bsps/include/grlib/grspw.h index 50ca744bde..1e7cb29e1c 100644 --- a/bsps/include/grlib/grspw.h +++ b/bsps/include/grlib/grspw.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup spw @@ -7,9 +9,26 @@ * COPYRIGHT (c) 2007. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRSPW_H__ diff --git a/bsps/include/grlib/grspw2-regs.h b/bsps/include/grlib/grspw2-regs.h new file mode 100644 index 0000000000..6293230cfe --- /dev/null +++ b/bsps/include/grlib/grspw2-regs.h @@ -0,0 +1,1429 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRSPW2 + * + * @brief This header file defines the GRSPW2 register block interface. + */ + +/* + * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grspw2-header */ + +#ifndef _GRLIB_GRSPW2_REGS_H +#define _GRLIB_GRSPW2_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grspw2-dma */ + +/** + * @defgroup RTEMSDeviceGRSPW2DMA GRSPW2 DMA + * + * @ingroup RTEMSDeviceGRSPW2 + * + * @brief This group contains the GRSPW2 DMA interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRSPW2DMADMACTRL DMA control/status (DMACTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DMACTRL_INTNUM_SHIFT 26 +#define GRSPW2_DMACTRL_INTNUM_MASK 0xfc000000U +#define GRSPW2_DMACTRL_INTNUM_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_DMACTRL_INTNUM_MASK ) >> \ + GRSPW2_DMACTRL_INTNUM_SHIFT ) +#define GRSPW2_DMACTRL_INTNUM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMACTRL_INTNUM_MASK ) | \ + ( ( ( _val ) << GRSPW2_DMACTRL_INTNUM_SHIFT ) & \ + GRSPW2_DMACTRL_INTNUM_MASK ) ) +#define GRSPW2_DMACTRL_INTNUM( _val ) \ + ( ( ( _val ) << GRSPW2_DMACTRL_INTNUM_SHIFT ) & \ + GRSPW2_DMACTRL_INTNUM_MASK ) + +#define GRSPW2_DMACTRL_RES_SHIFT 24 +#define GRSPW2_DMACTRL_RES_MASK 0x3000000U +#define GRSPW2_DMACTRL_RES_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_DMACTRL_RES_MASK ) >> \ + GRSPW2_DMACTRL_RES_SHIFT ) +#define GRSPW2_DMACTRL_RES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMACTRL_RES_MASK ) | \ + ( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & \ + GRSPW2_DMACTRL_RES_MASK ) ) +#define GRSPW2_DMACTRL_RES( _val ) \ + ( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & \ + GRSPW2_DMACTRL_RES_MASK ) + +#define GRSPW2_DMACTRL_EP 0x800000U + +#define GRSPW2_DMACTRL_TR 0x400000U + +#define GRSPW2_DMACTRL_IE 0x200000U + +#define GRSPW2_DMACTRL_IT 0x100000U + +#define GRSPW2_DMACTRL_RP 0x80000U + +#define GRSPW2_DMACTRL_TP 0x40000U + +#define GRSPW2_DMACTRL_TL 0x20000U + +#define GRSPW2_DMACTRL_LE 0x10000U + +#define GRSPW2_DMACTRL_SP 0x8000U + +#define GRSPW2_DMACTRL_SA 0x4000U + +#define GRSPW2_DMACTRL_EN 0x2000U + +#define GRSPW2_DMACTRL_NS 0x1000U + +#define GRSPW2_DMACTRL_RD 0x800U + +#define GRSPW2_DMACTRL_RX 0x400U + +#define GRSPW2_DMACTRL_AT 0x200U + +#define GRSPW2_DMACTRL_RA 0x100U + +#define GRSPW2_DMACTRL_TA 0x80U + +#define GRSPW2_DMACTRL_PR 0x40U + +#define GRSPW2_DMACTRL_PS 0x20U + +#define GRSPW2_DMACTRL_AI 0x10U + +#define GRSPW2_DMACTRL_RI 0x8U + +#define GRSPW2_DMACTRL_TI 0x4U + +#define GRSPW2_DMACTRL_RE 0x2U + +#define GRSPW2_DMACTRL_TE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2DMADMAMAXLEN DMA RX maximum length (DMAMAXLEN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT 2 +#define GRSPW2_DMAMAXLEN_RXMAXLEN_MASK 0x1fffffcU +#define GRSPW2_DMAMAXLEN_RXMAXLEN_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) >> \ + GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT ) +#define GRSPW2_DMAMAXLEN_RXMAXLEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) | \ + ( ( ( _val ) << GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT ) & \ + GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) ) +#define GRSPW2_DMAMAXLEN_RXMAXLEN( _val ) \ + ( ( ( _val ) << GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT ) & \ + GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) + +#define GRSPW2_DMAMAXLEN_RES_SHIFT 0 +#define GRSPW2_DMAMAXLEN_RES_MASK 0x3U +#define GRSPW2_DMAMAXLEN_RES_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_DMAMAXLEN_RES_MASK ) >> \ + GRSPW2_DMAMAXLEN_RES_SHIFT ) +#define GRSPW2_DMAMAXLEN_RES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMAMAXLEN_RES_MASK ) | \ + ( ( ( _val ) << GRSPW2_DMAMAXLEN_RES_SHIFT ) & \ + GRSPW2_DMAMAXLEN_RES_MASK ) ) +#define GRSPW2_DMAMAXLEN_RES( _val ) \ + ( ( ( _val ) << GRSPW2_DMAMAXLEN_RES_SHIFT ) & \ + GRSPW2_DMAMAXLEN_RES_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2DMADMATXDESC \ + * DMA transmit descriptor table address (DMATXDESC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT 0 +#define GRSPW2_DMATXDESC_DESCBASEADDR_MASK 0xffffffffU +#define GRSPW2_DMATXDESC_DESCBASEADDR_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) >> \ + GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT ) +#define GRSPW2_DMATXDESC_DESCBASEADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) | \ + ( ( ( _val ) << GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT ) & \ + GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) ) +#define GRSPW2_DMATXDESC_DESCBASEADDR( _val ) \ + ( ( ( _val ) << GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT ) & \ + GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) + +#define GRSPW2_DMATXDESC_DESCSEL_SHIFT 4 +#define GRSPW2_DMATXDESC_DESCSEL_MASK 0xfffffff0U +#define GRSPW2_DMATXDESC_DESCSEL_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_DMATXDESC_DESCSEL_MASK ) >> \ + GRSPW2_DMATXDESC_DESCSEL_SHIFT ) +#define GRSPW2_DMATXDESC_DESCSEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMATXDESC_DESCSEL_MASK ) | \ + ( ( ( _val ) << GRSPW2_DMATXDESC_DESCSEL_SHIFT ) & \ + GRSPW2_DMATXDESC_DESCSEL_MASK ) ) +#define GRSPW2_DMATXDESC_DESCSEL( _val ) \ + ( ( ( _val ) << GRSPW2_DMATXDESC_DESCSEL_SHIFT ) & \ + GRSPW2_DMATXDESC_DESCSEL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2DMADMARXDESC \ + * DMA receive descriptor table address (DMARXDESC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT 10 +#define GRSPW2_DMARXDESC_DESCBASEADDR_MASK 0xfffffc00U +#define GRSPW2_DMARXDESC_DESCBASEADDR_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) >> \ + GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT ) +#define GRSPW2_DMARXDESC_DESCBASEADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) | \ + ( ( ( _val ) << GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT ) & \ + GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) ) +#define GRSPW2_DMARXDESC_DESCBASEADDR( _val ) \ + ( ( ( _val ) << GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT ) & \ + GRSPW2_DMARXDESC_DESCBASEADDR_MASK ) + +#define GRSPW2_DMARXDESC_DESCSEL_SHIFT 3 +#define GRSPW2_DMARXDESC_DESCSEL_MASK 0x3f8U +#define GRSPW2_DMARXDESC_DESCSEL_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_DMARXDESC_DESCSEL_MASK ) >> \ + GRSPW2_DMARXDESC_DESCSEL_SHIFT ) +#define GRSPW2_DMARXDESC_DESCSEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMARXDESC_DESCSEL_MASK ) | \ + ( ( ( _val ) << GRSPW2_DMARXDESC_DESCSEL_SHIFT ) & \ + GRSPW2_DMARXDESC_DESCSEL_MASK ) ) +#define GRSPW2_DMARXDESC_DESCSEL( _val ) \ + ( ( ( _val ) << GRSPW2_DMARXDESC_DESCSEL_SHIFT ) & \ + GRSPW2_DMARXDESC_DESCSEL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2DMADMAADDR DMA address (DMAADDR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DMAADDR_MASK_SHIFT 8 +#define GRSPW2_DMAADDR_MASK_MASK 0xff00U +#define GRSPW2_DMAADDR_MASK_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_DMAADDR_MASK_MASK ) >> \ + GRSPW2_DMAADDR_MASK_SHIFT ) +#define GRSPW2_DMAADDR_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMAADDR_MASK_MASK ) | \ + ( ( ( _val ) << GRSPW2_DMAADDR_MASK_SHIFT ) & \ + GRSPW2_DMAADDR_MASK_MASK ) ) +#define GRSPW2_DMAADDR_MASK( _val ) \ + ( ( ( _val ) << GRSPW2_DMAADDR_MASK_SHIFT ) & \ + GRSPW2_DMAADDR_MASK_MASK ) + +#define GRSPW2_DMAADDR_ADDR_SHIFT 0 +#define GRSPW2_DMAADDR_ADDR_MASK 0xffU +#define GRSPW2_DMAADDR_ADDR_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_DMAADDR_ADDR_MASK ) >> \ + GRSPW2_DMAADDR_ADDR_SHIFT ) +#define GRSPW2_DMAADDR_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DMAADDR_ADDR_MASK ) | \ + ( ( ( _val ) << GRSPW2_DMAADDR_ADDR_SHIFT ) & \ + GRSPW2_DMAADDR_ADDR_MASK ) ) +#define GRSPW2_DMAADDR_ADDR( _val ) \ + ( ( ( _val ) << GRSPW2_DMAADDR_ADDR_SHIFT ) & \ + GRSPW2_DMAADDR_ADDR_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GRSPW2 DMA register block memory map. + */ +typedef struct grspw2_dma { + /** + * @brief See @ref RTEMSDeviceGRSPW2DMADMACTRL. + */ + uint32_t dmactrl; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DMADMAMAXLEN. + */ + uint32_t dmamaxlen; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DMADMATXDESC. + */ + uint32_t dmatxdesc; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DMADMARXDESC. + */ + uint32_t dmarxdesc; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DMADMAADDR. + */ + uint32_t dmaaddr; + + uint32_t reserved_14_20[ 3 ]; +} grspw2_dma; + +/** @} */ + +/* Generated from spec:/dev/grlib/if/grspw2 */ + +/** + * @defgroup RTEMSDeviceGRSPW2 GRSPW2 + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRSPW2 interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRSPW2CTRL Control (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_CTRL_RA 0x80000000U + +#define GRSPW2_CTRL_RX 0x40000000U + +#define GRSPW2_CTRL_RC 0x20000000U + +#define GRSPW2_CTRL_NCH_SHIFT 27 +#define GRSPW2_CTRL_NCH_MASK 0x18000000U +#define GRSPW2_CTRL_NCH_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_CTRL_NCH_MASK ) >> \ + GRSPW2_CTRL_NCH_SHIFT ) +#define GRSPW2_CTRL_NCH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_CTRL_NCH_MASK ) | \ + ( ( ( _val ) << GRSPW2_CTRL_NCH_SHIFT ) & \ + GRSPW2_CTRL_NCH_MASK ) ) +#define GRSPW2_CTRL_NCH( _val ) \ + ( ( ( _val ) << GRSPW2_CTRL_NCH_SHIFT ) & \ + GRSPW2_CTRL_NCH_MASK ) + +#define GRSPW2_CTRL_PO 0x4000000U + +#define GRSPW2_CTRL_CC 0x2000000U + +#define GRSPW2_CTRL_ID 0x1000000U + +#define GRSPW2_CTRL_R 0x800000U + +#define GRSPW2_CTRL_LE 0x400000U + +#define GRSPW2_CTRL_PS 0x200000U + +#define GRSPW2_CTRL_NP 0x100000U + +#define GRSPW2_CTRL_PNPA_SHIFT 18 +#define GRSPW2_CTRL_PNPA_MASK 0xc0000U +#define GRSPW2_CTRL_PNPA_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_CTRL_PNPA_MASK ) >> \ + GRSPW2_CTRL_PNPA_SHIFT ) +#define GRSPW2_CTRL_PNPA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_CTRL_PNPA_MASK ) | \ + ( ( ( _val ) << GRSPW2_CTRL_PNPA_SHIFT ) & \ + GRSPW2_CTRL_PNPA_MASK ) ) +#define GRSPW2_CTRL_PNPA( _val ) \ + ( ( ( _val ) << GRSPW2_CTRL_PNPA_SHIFT ) & \ + GRSPW2_CTRL_PNPA_MASK ) + +#define GRSPW2_CTRL_RD 0x20000U + +#define GRSPW2_CTRL_RE 0x10000U + +#define GRSPW2_CTRL_PE 0x8000U + +#define GRSPW2_CTRL_R 0x4000U + +#define GRSPW2_CTRL_TL 0x2000U + +#define GRSPW2_CTRL_TF 0x1000U + +#define GRSPW2_CTRL_TR 0x800U + +#define GRSPW2_CTRL_TT 0x400U + +#define GRSPW2_CTRL_LI 0x200U + +#define GRSPW2_CTRL_TQ 0x100U + +#define GRSPW2_CTRL_R 0x80U + +#define GRSPW2_CTRL_RS 0x40U + +#define GRSPW2_CTRL_PM 0x20U + +#define GRSPW2_CTRL_TI 0x10U + +#define GRSPW2_CTRL_IE 0x8U + +#define GRSPW2_CTRL_AS 0x4U + +#define GRSPW2_CTRL_LS 0x2U + +#define GRSPW2_CTRL_LD 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2STS Status (STS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_STS_NRXD_SHIFT 26 +#define GRSPW2_STS_NRXD_MASK 0xc000000U +#define GRSPW2_STS_NRXD_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_STS_NRXD_MASK ) >> \ + GRSPW2_STS_NRXD_SHIFT ) +#define GRSPW2_STS_NRXD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_STS_NRXD_MASK ) | \ + ( ( ( _val ) << GRSPW2_STS_NRXD_SHIFT ) & \ + GRSPW2_STS_NRXD_MASK ) ) +#define GRSPW2_STS_NRXD( _val ) \ + ( ( ( _val ) << GRSPW2_STS_NRXD_SHIFT ) & \ + GRSPW2_STS_NRXD_MASK ) + +#define GRSPW2_STS_NTXD 0x2000000U + +#define GRSPW2_STS_LS_SHIFT 21 +#define GRSPW2_STS_LS_MASK 0xe00000U +#define GRSPW2_STS_LS_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_STS_LS_MASK ) >> \ + GRSPW2_STS_LS_SHIFT ) +#define GRSPW2_STS_LS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_STS_LS_MASK ) | \ + ( ( ( _val ) << GRSPW2_STS_LS_SHIFT ) & \ + GRSPW2_STS_LS_MASK ) ) +#define GRSPW2_STS_LS( _val ) \ + ( ( ( _val ) << GRSPW2_STS_LS_SHIFT ) & \ + GRSPW2_STS_LS_MASK ) + +#define GRSPW2_STS_AP 0x200U + +#define GRSPW2_STS_EE 0x100U + +#define GRSPW2_STS_IA 0x80U + +#define GRSPW2_STS_RES_SHIFT 5 +#define GRSPW2_STS_RES_MASK 0x60U +#define GRSPW2_STS_RES_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_STS_RES_MASK ) >> \ + GRSPW2_STS_RES_SHIFT ) +#define GRSPW2_STS_RES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_STS_RES_MASK ) | \ + ( ( ( _val ) << GRSPW2_STS_RES_SHIFT ) & \ + GRSPW2_STS_RES_MASK ) ) +#define GRSPW2_STS_RES( _val ) \ + ( ( ( _val ) << GRSPW2_STS_RES_SHIFT ) & \ + GRSPW2_STS_RES_MASK ) + +#define GRSPW2_STS_PE 0x10U + +#define GRSPW2_STS_DE 0x8U + +#define GRSPW2_STS_ER 0x4U + +#define GRSPW2_STS_CE 0x2U + +#define GRSPW2_STS_TO 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2DEFADDR Default address (DEFADDR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DEFADDR_DEFMASK_SHIFT 8 +#define GRSPW2_DEFADDR_DEFMASK_MASK 0xff00U +#define GRSPW2_DEFADDR_DEFMASK_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_DEFADDR_DEFMASK_MASK ) >> \ + GRSPW2_DEFADDR_DEFMASK_SHIFT ) +#define GRSPW2_DEFADDR_DEFMASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DEFADDR_DEFMASK_MASK ) | \ + ( ( ( _val ) << GRSPW2_DEFADDR_DEFMASK_SHIFT ) & \ + GRSPW2_DEFADDR_DEFMASK_MASK ) ) +#define GRSPW2_DEFADDR_DEFMASK( _val ) \ + ( ( ( _val ) << GRSPW2_DEFADDR_DEFMASK_SHIFT ) & \ + GRSPW2_DEFADDR_DEFMASK_MASK ) + +#define GRSPW2_DEFADDR_DEFADDR_SHIFT 0 +#define GRSPW2_DEFADDR_DEFADDR_MASK 0xffU +#define GRSPW2_DEFADDR_DEFADDR_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_DEFADDR_DEFADDR_MASK ) >> \ + GRSPW2_DEFADDR_DEFADDR_SHIFT ) +#define GRSPW2_DEFADDR_DEFADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DEFADDR_DEFADDR_MASK ) | \ + ( ( ( _val ) << GRSPW2_DEFADDR_DEFADDR_SHIFT ) & \ + GRSPW2_DEFADDR_DEFADDR_MASK ) ) +#define GRSPW2_DEFADDR_DEFADDR( _val ) \ + ( ( ( _val ) << GRSPW2_DEFADDR_DEFADDR_SHIFT ) & \ + GRSPW2_DEFADDR_DEFADDR_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2CLKDIV Clock divisor (CLKDIV) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_CLKDIV_CLKDIVSTART_SHIFT 8 +#define GRSPW2_CLKDIV_CLKDIVSTART_MASK 0xff00U +#define GRSPW2_CLKDIV_CLKDIVSTART_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_CLKDIV_CLKDIVSTART_MASK ) >> \ + GRSPW2_CLKDIV_CLKDIVSTART_SHIFT ) +#define GRSPW2_CLKDIV_CLKDIVSTART_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_CLKDIV_CLKDIVSTART_MASK ) | \ + ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVSTART_SHIFT ) & \ + GRSPW2_CLKDIV_CLKDIVSTART_MASK ) ) +#define GRSPW2_CLKDIV_CLKDIVSTART( _val ) \ + ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVSTART_SHIFT ) & \ + GRSPW2_CLKDIV_CLKDIVSTART_MASK ) + +#define GRSPW2_CLKDIV_CLKDIVRUN_SHIFT 0 +#define GRSPW2_CLKDIV_CLKDIVRUN_MASK 0xffU +#define GRSPW2_CLKDIV_CLKDIVRUN_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_CLKDIV_CLKDIVRUN_MASK ) >> \ + GRSPW2_CLKDIV_CLKDIVRUN_SHIFT ) +#define GRSPW2_CLKDIV_CLKDIVRUN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_CLKDIV_CLKDIVRUN_MASK ) | \ + ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVRUN_SHIFT ) & \ + GRSPW2_CLKDIV_CLKDIVRUN_MASK ) ) +#define GRSPW2_CLKDIV_CLKDIVRUN( _val ) \ + ( ( ( _val ) << GRSPW2_CLKDIV_CLKDIVRUN_SHIFT ) & \ + GRSPW2_CLKDIV_CLKDIVRUN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2DKEY Destination key (DKEY) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DKEY_DESTKEY_SHIFT 0 +#define GRSPW2_DKEY_DESTKEY_MASK 0xffU +#define GRSPW2_DKEY_DESTKEY_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_DKEY_DESTKEY_MASK ) >> \ + GRSPW2_DKEY_DESTKEY_SHIFT ) +#define GRSPW2_DKEY_DESTKEY_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_DKEY_DESTKEY_MASK ) | \ + ( ( ( _val ) << GRSPW2_DKEY_DESTKEY_SHIFT ) & \ + GRSPW2_DKEY_DESTKEY_MASK ) ) +#define GRSPW2_DKEY_DESTKEY( _val ) \ + ( ( ( _val ) << GRSPW2_DKEY_DESTKEY_SHIFT ) & \ + GRSPW2_DKEY_DESTKEY_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2TC Time-code (TC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_TC_TCTRL_SHIFT 6 +#define GRSPW2_TC_TCTRL_MASK 0xc0U +#define GRSPW2_TC_TCTRL_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_TC_TCTRL_MASK ) >> \ + GRSPW2_TC_TCTRL_SHIFT ) +#define GRSPW2_TC_TCTRL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_TC_TCTRL_MASK ) | \ + ( ( ( _val ) << GRSPW2_TC_TCTRL_SHIFT ) & \ + GRSPW2_TC_TCTRL_MASK ) ) +#define GRSPW2_TC_TCTRL( _val ) \ + ( ( ( _val ) << GRSPW2_TC_TCTRL_SHIFT ) & \ + GRSPW2_TC_TCTRL_MASK ) + +#define GRSPW2_TC_TIMECNT_SHIFT 0 +#define GRSPW2_TC_TIMECNT_MASK 0x3fU +#define GRSPW2_TC_TIMECNT_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_TC_TIMECNT_MASK ) >> \ + GRSPW2_TC_TIMECNT_SHIFT ) +#define GRSPW2_TC_TIMECNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_TC_TIMECNT_MASK ) | \ + ( ( ( _val ) << GRSPW2_TC_TIMECNT_SHIFT ) & \ + GRSPW2_TC_TIMECNT_MASK ) ) +#define GRSPW2_TC_TIMECNT( _val ) \ + ( ( ( _val ) << GRSPW2_TC_TIMECNT_SHIFT ) & \ + GRSPW2_TC_TIMECNT_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2INTCTRL Interrupt distribution control (INTCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_INTCTRL_INTNUM_SHIFT 26 +#define GRSPW2_INTCTRL_INTNUM_MASK 0xfc000000U +#define GRSPW2_INTCTRL_INTNUM_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_INTCTRL_INTNUM_MASK ) >> \ + GRSPW2_INTCTRL_INTNUM_SHIFT ) +#define GRSPW2_INTCTRL_INTNUM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCTRL_INTNUM_MASK ) | \ + ( ( ( _val ) << GRSPW2_INTCTRL_INTNUM_SHIFT ) & \ + GRSPW2_INTCTRL_INTNUM_MASK ) ) +#define GRSPW2_INTCTRL_INTNUM( _val ) \ + ( ( ( _val ) << GRSPW2_INTCTRL_INTNUM_SHIFT ) & \ + GRSPW2_INTCTRL_INTNUM_MASK ) + +#define GRSPW2_INTCTRL_RS 0x2000000U + +#define GRSPW2_INTCTRL_EE 0x1000000U + +#define GRSPW2_INTCTRL_IA 0x800000U + +#define GRSPW2_INTCTRL_RES 0x2U + +#define GRSPW2_INTCTRL_TQ_SHIFT 21 +#define GRSPW2_INTCTRL_TQ_MASK 0x600000U +#define GRSPW2_INTCTRL_TQ_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_INTCTRL_TQ_MASK ) >> \ + GRSPW2_INTCTRL_TQ_SHIFT ) +#define GRSPW2_INTCTRL_TQ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCTRL_TQ_MASK ) | \ + ( ( ( _val ) << GRSPW2_INTCTRL_TQ_SHIFT ) & \ + GRSPW2_INTCTRL_TQ_MASK ) ) +#define GRSPW2_INTCTRL_TQ( _val ) \ + ( ( ( _val ) << GRSPW2_INTCTRL_TQ_SHIFT ) & \ + GRSPW2_INTCTRL_TQ_MASK ) + +#define GRSPW2_INTCTRL_AQ 0x100000U + +#define GRSPW2_INTCTRL_IQ 0x80000U + +#define GRSPW2_INTCTRL_RES 0x40000U + +#define GRSPW2_INTCTRL_AA_SHIFT 16 +#define GRSPW2_INTCTRL_AA_MASK 0x30000U +#define GRSPW2_INTCTRL_AA_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_INTCTRL_AA_MASK ) >> \ + GRSPW2_INTCTRL_AA_SHIFT ) +#define GRSPW2_INTCTRL_AA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCTRL_AA_MASK ) | \ + ( ( ( _val ) << GRSPW2_INTCTRL_AA_SHIFT ) & \ + GRSPW2_INTCTRL_AA_MASK ) ) +#define GRSPW2_INTCTRL_AA( _val ) \ + ( ( ( _val ) << GRSPW2_INTCTRL_AA_SHIFT ) & \ + GRSPW2_INTCTRL_AA_MASK ) + +#define GRSPW2_INTCTRL_AT 0x8000U + +#define GRSPW2_INTCTRL_IT 0x4000U + +#define GRSPW2_INTCTRL_RES 0x2000U + +#define GRSPW2_INTCTRL_ID_SHIFT 8 +#define GRSPW2_INTCTRL_ID_MASK 0x1f00U +#define GRSPW2_INTCTRL_ID_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_INTCTRL_ID_MASK ) >> \ + GRSPW2_INTCTRL_ID_SHIFT ) +#define GRSPW2_INTCTRL_ID_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCTRL_ID_MASK ) | \ + ( ( ( _val ) << GRSPW2_INTCTRL_ID_SHIFT ) & \ + GRSPW2_INTCTRL_ID_MASK ) ) +#define GRSPW2_INTCTRL_ID( _val ) \ + ( ( ( _val ) << GRSPW2_INTCTRL_ID_SHIFT ) & \ + GRSPW2_INTCTRL_ID_MASK ) + +#define GRSPW2_INTCTRL_II 0x80U + +#define GRSPW2_INTCTRL_TXINT 0x40U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2INTRX Interrupt-code receive (INTRX) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_INTRX_RXIRQ_SHIFT 0 +#define GRSPW2_INTRX_RXIRQ_MASK 0xffffffffU +#define GRSPW2_INTRX_RXIRQ_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_INTRX_RXIRQ_MASK ) >> \ + GRSPW2_INTRX_RXIRQ_SHIFT ) +#define GRSPW2_INTRX_RXIRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTRX_RXIRQ_MASK ) | \ + ( ( ( _val ) << GRSPW2_INTRX_RXIRQ_SHIFT ) & \ + GRSPW2_INTRX_RXIRQ_MASK ) ) +#define GRSPW2_INTRX_RXIRQ( _val ) \ + ( ( ( _val ) << GRSPW2_INTRX_RXIRQ_SHIFT ) & \ + GRSPW2_INTRX_RXIRQ_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2INTTO Interrupt timeout (INTTO) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_INTTO_INTTO_SHIFT 0 +#define GRSPW2_INTTO_INTTO_MASK 0xffffffffU +#define GRSPW2_INTTO_INTTO_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_INTTO_INTTO_MASK ) >> \ + GRSPW2_INTTO_INTTO_SHIFT ) +#define GRSPW2_INTTO_INTTO_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTTO_INTTO_MASK ) | \ + ( ( ( _val ) << GRSPW2_INTTO_INTTO_SHIFT ) & \ + GRSPW2_INTTO_INTTO_MASK ) ) +#define GRSPW2_INTTO_INTTO( _val ) \ + ( ( ( _val ) << GRSPW2_INTTO_INTTO_SHIFT ) & \ + GRSPW2_INTTO_INTTO_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2INTTOEXT Interrupt timeout extended (INTTOEXT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_INTTOEXT_INTTOEXT_SHIFT 0 +#define GRSPW2_INTTOEXT_INTTOEXT_MASK 0xffffffffU +#define GRSPW2_INTTOEXT_INTTOEXT_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_INTTOEXT_INTTOEXT_MASK ) >> \ + GRSPW2_INTTOEXT_INTTOEXT_SHIFT ) +#define GRSPW2_INTTOEXT_INTTOEXT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTTOEXT_INTTOEXT_MASK ) | \ + ( ( ( _val ) << GRSPW2_INTTOEXT_INTTOEXT_SHIFT ) & \ + GRSPW2_INTTOEXT_INTTOEXT_MASK ) ) +#define GRSPW2_INTTOEXT_INTTOEXT( _val ) \ + ( ( ( _val ) << GRSPW2_INTTOEXT_INTTOEXT_SHIFT ) & \ + GRSPW2_INTTOEXT_INTTOEXT_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2TICKMASK Interrupt tick-out mask (TICKMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_TICKMASK_MASK_SHIFT 0 +#define GRSPW2_TICKMASK_MASK_MASK 0xffffffffU +#define GRSPW2_TICKMASK_MASK_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_TICKMASK_MASK_MASK ) >> \ + GRSPW2_TICKMASK_MASK_SHIFT ) +#define GRSPW2_TICKMASK_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_TICKMASK_MASK_MASK ) | \ + ( ( ( _val ) << GRSPW2_TICKMASK_MASK_SHIFT ) & \ + GRSPW2_TICKMASK_MASK_MASK ) ) +#define GRSPW2_TICKMASK_MASK( _val ) \ + ( ( ( _val ) << GRSPW2_TICKMASK_MASK_SHIFT ) & \ + GRSPW2_TICKMASK_MASK_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2AUTOACKTICKMASKEXT \ + * Interrupt-code auto acknowledge mask / interrupt tick-out mask extended (AUTOACK_TICKMASKEXT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT 0 +#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK 0xffffffffU +#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) >> \ + GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT ) +#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) | \ + ( ( ( _val ) << GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT ) & \ + GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) ) +#define GRSPW2_AUTOACK_TICKMASKEXT_AAMASK( _val ) \ + ( ( ( _val ) << GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_SHIFT ) & \ + GRSPW2_AUTOACK_TICKMASKEXT_AAMASK_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2INTCFG \ + * Interrupt distribution configuration (INTCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_INTCFG_INTNUM3_SHIFT 26 +#define GRSPW2_INTCFG_INTNUM3_MASK 0xfc000000U +#define GRSPW2_INTCFG_INTNUM3_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM3_MASK ) >> \ + GRSPW2_INTCFG_INTNUM3_SHIFT ) +#define GRSPW2_INTCFG_INTNUM3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM3_MASK ) | \ + ( ( ( _val ) << GRSPW2_INTCFG_INTNUM3_SHIFT ) & \ + GRSPW2_INTCFG_INTNUM3_MASK ) ) +#define GRSPW2_INTCFG_INTNUM3( _val ) \ + ( ( ( _val ) << GRSPW2_INTCFG_INTNUM3_SHIFT ) & \ + GRSPW2_INTCFG_INTNUM3_MASK ) + +#define GRSPW2_INTCFG_INTNUM2_SHIFT 20 +#define GRSPW2_INTCFG_INTNUM2_MASK 0x3f00000U +#define GRSPW2_INTCFG_INTNUM2_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM2_MASK ) >> \ + GRSPW2_INTCFG_INTNUM2_SHIFT ) +#define GRSPW2_INTCFG_INTNUM2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM2_MASK ) | \ + ( ( ( _val ) << GRSPW2_INTCFG_INTNUM2_SHIFT ) & \ + GRSPW2_INTCFG_INTNUM2_MASK ) ) +#define GRSPW2_INTCFG_INTNUM2( _val ) \ + ( ( ( _val ) << GRSPW2_INTCFG_INTNUM2_SHIFT ) & \ + GRSPW2_INTCFG_INTNUM2_MASK ) + +#define GRSPW2_INTCFG_INTNUM1_SHIFT 14 +#define GRSPW2_INTCFG_INTNUM1_MASK 0xfc000U +#define GRSPW2_INTCFG_INTNUM1_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM1_MASK ) >> \ + GRSPW2_INTCFG_INTNUM1_SHIFT ) +#define GRSPW2_INTCFG_INTNUM1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM1_MASK ) | \ + ( ( ( _val ) << GRSPW2_INTCFG_INTNUM1_SHIFT ) & \ + GRSPW2_INTCFG_INTNUM1_MASK ) ) +#define GRSPW2_INTCFG_INTNUM1( _val ) \ + ( ( ( _val ) << GRSPW2_INTCFG_INTNUM1_SHIFT ) & \ + GRSPW2_INTCFG_INTNUM1_MASK ) + +#define GRSPW2_INTCFG_INTNUM0_SHIFT 8 +#define GRSPW2_INTCFG_INTNUM0_MASK 0x3f00U +#define GRSPW2_INTCFG_INTNUM0_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_INTCFG_INTNUM0_MASK ) >> \ + GRSPW2_INTCFG_INTNUM0_SHIFT ) +#define GRSPW2_INTCFG_INTNUM0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCFG_INTNUM0_MASK ) | \ + ( ( ( _val ) << GRSPW2_INTCFG_INTNUM0_SHIFT ) & \ + GRSPW2_INTCFG_INTNUM0_MASK ) ) +#define GRSPW2_INTCFG_INTNUM0( _val ) \ + ( ( ( _val ) << GRSPW2_INTCFG_INTNUM0_SHIFT ) & \ + GRSPW2_INTCFG_INTNUM0_MASK ) + +#define GRSPW2_INTCFG_NUMINT_SHIFT 4 +#define GRSPW2_INTCFG_NUMINT_MASK 0xf0U +#define GRSPW2_INTCFG_NUMINT_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_INTCFG_NUMINT_MASK ) >> \ + GRSPW2_INTCFG_NUMINT_SHIFT ) +#define GRSPW2_INTCFG_NUMINT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_INTCFG_NUMINT_MASK ) | \ + ( ( ( _val ) << GRSPW2_INTCFG_NUMINT_SHIFT ) & \ + GRSPW2_INTCFG_NUMINT_MASK ) ) +#define GRSPW2_INTCFG_NUMINT( _val ) \ + ( ( ( _val ) << GRSPW2_INTCFG_NUMINT_SHIFT ) & \ + GRSPW2_INTCFG_NUMINT_MASK ) + +#define GRSPW2_INTCFG_PR 0x8U + +#define GRSPW2_INTCFG_IR 0x4U + +#define GRSPW2_INTCFG_IT 0x2U + +#define GRSPW2_INTCFG_EE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2ISR Interrupt distribution ISR (ISR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_ISR_ISR_SHIFT 0 +#define GRSPW2_ISR_ISR_MASK 0xffffffffU +#define GRSPW2_ISR_ISR_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_ISR_ISR_MASK ) >> \ + GRSPW2_ISR_ISR_SHIFT ) +#define GRSPW2_ISR_ISR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_ISR_ISR_MASK ) | \ + ( ( ( _val ) << GRSPW2_ISR_ISR_SHIFT ) & \ + GRSPW2_ISR_ISR_MASK ) ) +#define GRSPW2_ISR_ISR( _val ) \ + ( ( ( _val ) << GRSPW2_ISR_ISR_SHIFT ) & \ + GRSPW2_ISR_ISR_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2ISREXT \ + * Interrupt distribution ISR extended (ISREXT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_ISREXT_ISR_SHIFT 0 +#define GRSPW2_ISREXT_ISR_MASK 0xffffffffU +#define GRSPW2_ISREXT_ISR_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_ISREXT_ISR_MASK ) >> \ + GRSPW2_ISREXT_ISR_SHIFT ) +#define GRSPW2_ISREXT_ISR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_ISREXT_ISR_MASK ) | \ + ( ( ( _val ) << GRSPW2_ISREXT_ISR_SHIFT ) & \ + GRSPW2_ISREXT_ISR_MASK ) ) +#define GRSPW2_ISREXT_ISR( _val ) \ + ( ( ( _val ) << GRSPW2_ISREXT_ISR_SHIFT ) & \ + GRSPW2_ISREXT_ISR_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2PRESCALER \ + * Interrupt distribution prescaler reload (PRESCALER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_PRESCALER_R 0x80000000U + +#define GRSPW2_PRESCALER_RL_SHIFT 0 +#define GRSPW2_PRESCALER_RL_MASK 0x7fffffffU +#define GRSPW2_PRESCALER_RL_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_PRESCALER_RL_MASK ) >> \ + GRSPW2_PRESCALER_RL_SHIFT ) +#define GRSPW2_PRESCALER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PRESCALER_RL_MASK ) | \ + ( ( ( _val ) << GRSPW2_PRESCALER_RL_SHIFT ) & \ + GRSPW2_PRESCALER_RL_MASK ) ) +#define GRSPW2_PRESCALER_RL( _val ) \ + ( ( ( _val ) << GRSPW2_PRESCALER_RL_SHIFT ) & \ + GRSPW2_PRESCALER_RL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2ISRTIMER \ + * Interrupt distribution ISR timer reload (ISRTIMER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_ISRTIMER_EN 0x80000000U + +#define GRSPW2_ISRTIMER_RL_SHIFT 0 +#define GRSPW2_ISRTIMER_RL_MASK 0x7fffffffU +#define GRSPW2_ISRTIMER_RL_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_ISRTIMER_RL_MASK ) >> \ + GRSPW2_ISRTIMER_RL_SHIFT ) +#define GRSPW2_ISRTIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_ISRTIMER_RL_MASK ) | \ + ( ( ( _val ) << GRSPW2_ISRTIMER_RL_SHIFT ) & \ + GRSPW2_ISRTIMER_RL_MASK ) ) +#define GRSPW2_ISRTIMER_RL( _val ) \ + ( ( ( _val ) << GRSPW2_ISRTIMER_RL_SHIFT ) & \ + GRSPW2_ISRTIMER_RL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2IATIMER \ + * Interrupt distribution INT / ACK timer reload (IATIMER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_IATIMER_EN 0x80000000U + +#define GRSPW2_IATIMER_RL_SHIFT 0 +#define GRSPW2_IATIMER_RL_MASK 0x7fffffffU +#define GRSPW2_IATIMER_RL_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_IATIMER_RL_MASK ) >> \ + GRSPW2_IATIMER_RL_SHIFT ) +#define GRSPW2_IATIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_IATIMER_RL_MASK ) | \ + ( ( ( _val ) << GRSPW2_IATIMER_RL_SHIFT ) & \ + GRSPW2_IATIMER_RL_MASK ) ) +#define GRSPW2_IATIMER_RL( _val ) \ + ( ( ( _val ) << GRSPW2_IATIMER_RL_SHIFT ) & \ + GRSPW2_IATIMER_RL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2ICTIMER \ + * Interrupt distribution change timer reload (ICTIMER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_ICTIMER_EN 0x80000000U + +#define GRSPW2_ICTIMER_RL_SHIFT 0 +#define GRSPW2_ICTIMER_RL_MASK 0x7fffffffU +#define GRSPW2_ICTIMER_RL_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_ICTIMER_RL_MASK ) >> \ + GRSPW2_ICTIMER_RL_SHIFT ) +#define GRSPW2_ICTIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_ICTIMER_RL_MASK ) | \ + ( ( ( _val ) << GRSPW2_ICTIMER_RL_SHIFT ) & \ + GRSPW2_ICTIMER_RL_MASK ) ) +#define GRSPW2_ICTIMER_RL( _val ) \ + ( ( ( _val ) << GRSPW2_ICTIMER_RL_SHIFT ) & \ + GRSPW2_ICTIMER_RL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2PNPVEND \ + * SpaceWire Plug-and-Play - Device Vendor and Product ID (PNPVEND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_PNPVEND_VEND_SHIFT 16 +#define GRSPW2_PNPVEND_VEND_MASK 0xffff0000U +#define GRSPW2_PNPVEND_VEND_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_PNPVEND_VEND_MASK ) >> \ + GRSPW2_PNPVEND_VEND_SHIFT ) +#define GRSPW2_PNPVEND_VEND_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPVEND_VEND_MASK ) | \ + ( ( ( _val ) << GRSPW2_PNPVEND_VEND_SHIFT ) & \ + GRSPW2_PNPVEND_VEND_MASK ) ) +#define GRSPW2_PNPVEND_VEND( _val ) \ + ( ( ( _val ) << GRSPW2_PNPVEND_VEND_SHIFT ) & \ + GRSPW2_PNPVEND_VEND_MASK ) + +#define GRSPW2_PNPVEND_PROD_SHIFT 0 +#define GRSPW2_PNPVEND_PROD_MASK 0xffffU +#define GRSPW2_PNPVEND_PROD_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_PNPVEND_PROD_MASK ) >> \ + GRSPW2_PNPVEND_PROD_SHIFT ) +#define GRSPW2_PNPVEND_PROD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPVEND_PROD_MASK ) | \ + ( ( ( _val ) << GRSPW2_PNPVEND_PROD_SHIFT ) & \ + GRSPW2_PNPVEND_PROD_MASK ) ) +#define GRSPW2_PNPVEND_PROD( _val ) \ + ( ( ( _val ) << GRSPW2_PNPVEND_PROD_SHIFT ) & \ + GRSPW2_PNPVEND_PROD_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2PNPOA0 \ + * SpaceWire Plug-and-Play - Owner Address 0 (PNPOA0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_PNPOA0_RA_SHIFT 0 +#define GRSPW2_PNPOA0_RA_MASK 0xffffffffU +#define GRSPW2_PNPOA0_RA_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_PNPOA0_RA_MASK ) >> \ + GRSPW2_PNPOA0_RA_SHIFT ) +#define GRSPW2_PNPOA0_RA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPOA0_RA_MASK ) | \ + ( ( ( _val ) << GRSPW2_PNPOA0_RA_SHIFT ) & \ + GRSPW2_PNPOA0_RA_MASK ) ) +#define GRSPW2_PNPOA0_RA( _val ) \ + ( ( ( _val ) << GRSPW2_PNPOA0_RA_SHIFT ) & \ + GRSPW2_PNPOA0_RA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2PNPOA1 \ + * SpaceWire Plug-and-Play - Owner Address 1 (PNPOA1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_PNPOA1_RA_SHIFT 0 +#define GRSPW2_PNPOA1_RA_MASK 0xffffffffU +#define GRSPW2_PNPOA1_RA_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_PNPOA1_RA_MASK ) >> \ + GRSPW2_PNPOA1_RA_SHIFT ) +#define GRSPW2_PNPOA1_RA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPOA1_RA_MASK ) | \ + ( ( ( _val ) << GRSPW2_PNPOA1_RA_SHIFT ) & \ + GRSPW2_PNPOA1_RA_MASK ) ) +#define GRSPW2_PNPOA1_RA( _val ) \ + ( ( ( _val ) << GRSPW2_PNPOA1_RA_SHIFT ) & \ + GRSPW2_PNPOA1_RA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2PNPOA2 \ + * SpaceWire Plug-and-Play - Owner Address 2 (PNPOA2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_PNPOA2_RA_SHIFT 0 +#define GRSPW2_PNPOA2_RA_MASK 0xffffffffU +#define GRSPW2_PNPOA2_RA_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_PNPOA2_RA_MASK ) >> \ + GRSPW2_PNPOA2_RA_SHIFT ) +#define GRSPW2_PNPOA2_RA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPOA2_RA_MASK ) | \ + ( ( ( _val ) << GRSPW2_PNPOA2_RA_SHIFT ) & \ + GRSPW2_PNPOA2_RA_MASK ) ) +#define GRSPW2_PNPOA2_RA( _val ) \ + ( ( ( _val ) << GRSPW2_PNPOA2_RA_SHIFT ) & \ + GRSPW2_PNPOA2_RA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2PNPDEVID \ + * SpaceWire Plug-and-Play - Device ID (PNPDEVID) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_PNPDEVID_DID_SHIFT 0 +#define GRSPW2_PNPDEVID_DID_MASK 0xffffffffU +#define GRSPW2_PNPDEVID_DID_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_PNPDEVID_DID_MASK ) >> \ + GRSPW2_PNPDEVID_DID_SHIFT ) +#define GRSPW2_PNPDEVID_DID_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPDEVID_DID_MASK ) | \ + ( ( ( _val ) << GRSPW2_PNPDEVID_DID_SHIFT ) & \ + GRSPW2_PNPDEVID_DID_MASK ) ) +#define GRSPW2_PNPDEVID_DID( _val ) \ + ( ( ( _val ) << GRSPW2_PNPDEVID_DID_SHIFT ) & \ + GRSPW2_PNPDEVID_DID_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2PNPUVEND \ + * SpaceWire Plug-and-Play - Unit Vendor and Product ID (PNPUVEND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_PNPUVEND_VEND_SHIFT 16 +#define GRSPW2_PNPUVEND_VEND_MASK 0xffff0000U +#define GRSPW2_PNPUVEND_VEND_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_PNPUVEND_VEND_MASK ) >> \ + GRSPW2_PNPUVEND_VEND_SHIFT ) +#define GRSPW2_PNPUVEND_VEND_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPUVEND_VEND_MASK ) | \ + ( ( ( _val ) << GRSPW2_PNPUVEND_VEND_SHIFT ) & \ + GRSPW2_PNPUVEND_VEND_MASK ) ) +#define GRSPW2_PNPUVEND_VEND( _val ) \ + ( ( ( _val ) << GRSPW2_PNPUVEND_VEND_SHIFT ) & \ + GRSPW2_PNPUVEND_VEND_MASK ) + +#define GRSPW2_PNPUVEND_PROD_SHIFT 0 +#define GRSPW2_PNPUVEND_PROD_MASK 0xffffU +#define GRSPW2_PNPUVEND_PROD_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_PNPUVEND_PROD_MASK ) >> \ + GRSPW2_PNPUVEND_PROD_SHIFT ) +#define GRSPW2_PNPUVEND_PROD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPUVEND_PROD_MASK ) | \ + ( ( ( _val ) << GRSPW2_PNPUVEND_PROD_SHIFT ) & \ + GRSPW2_PNPUVEND_PROD_MASK ) ) +#define GRSPW2_PNPUVEND_PROD( _val ) \ + ( ( ( _val ) << GRSPW2_PNPUVEND_PROD_SHIFT ) & \ + GRSPW2_PNPUVEND_PROD_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2PNPUSN \ + * SpaceWire Plug-and-Play - Unit Serial Number (PNPUSN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_PNPUSN_USN_SHIFT 0 +#define GRSPW2_PNPUSN_USN_MASK 0xffffffffU +#define GRSPW2_PNPUSN_USN_GET( _reg ) \ + ( ( ( _reg ) & GRSPW2_PNPUSN_USN_MASK ) >> \ + GRSPW2_PNPUSN_USN_SHIFT ) +#define GRSPW2_PNPUSN_USN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPW2_PNPUSN_USN_MASK ) | \ + ( ( ( _val ) << GRSPW2_PNPUSN_USN_SHIFT ) & \ + GRSPW2_PNPUSN_USN_MASK ) ) +#define GRSPW2_PNPUSN_USN( _val ) \ + ( ( ( _val ) << GRSPW2_PNPUSN_USN_SHIFT ) & \ + GRSPW2_PNPUSN_USN_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GRSPW2 register block memory map. + */ +typedef struct grspw2 { + /** + * @brief See @ref RTEMSDeviceGRSPW2CTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSDeviceGRSPW2STS. + */ + uint32_t sts; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DEFADDR. + */ + uint32_t defaddr; + + /** + * @brief See @ref RTEMSDeviceGRSPW2CLKDIV. + */ + uint32_t clkdiv; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DKEY. + */ + uint32_t dkey; + + /** + * @brief See @ref RTEMSDeviceGRSPW2TC. + */ + uint32_t tc; + + uint32_t reserved_18_20[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DMA. + */ + grspw2_dma dma[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPW2INTCTRL. + */ + uint32_t intctrl; + + /** + * @brief See @ref RTEMSDeviceGRSPW2INTRX. + */ + uint32_t intrx; + + uint32_t reserved_a8_ac; + + /** + * @brief See @ref RTEMSDeviceGRSPW2INTTO. + */ + uint32_t intto; + + /** + * @brief See @ref RTEMSDeviceGRSPW2INTTOEXT. + */ + uint32_t inttoext; + + /** + * @brief See @ref RTEMSDeviceGRSPW2TICKMASK. + */ + uint32_t tickmask; + + /** + * @brief See @ref RTEMSDeviceGRSPW2AUTOACKTICKMASKEXT. + */ + uint32_t autoack_tickmaskext; + + /** + * @brief See @ref RTEMSDeviceGRSPW2INTCFG. + */ + uint32_t intcfg; + + uint32_t reserved_c0_c4; + + /** + * @brief See @ref RTEMSDeviceGRSPW2ISR. + */ + uint32_t isr; + + /** + * @brief See @ref RTEMSDeviceGRSPW2ISREXT. + */ + uint32_t isrext; + + uint32_t reserved_cc_d0; + + /** + * @brief See @ref RTEMSDeviceGRSPW2PRESCALER. + */ + uint32_t prescaler; + + /** + * @brief See @ref RTEMSDeviceGRSPW2ISRTIMER. + */ + uint32_t isrtimer; + + /** + * @brief See @ref RTEMSDeviceGRSPW2IATIMER. + */ + uint32_t iatimer; + + /** + * @brief See @ref RTEMSDeviceGRSPW2ICTIMER. + */ + uint32_t ictimer; + + /** + * @brief See @ref RTEMSDeviceGRSPW2PNPVEND. + */ + uint32_t pnpvend; + + uint32_t reserved_e4_e8; + + /** + * @brief See @ref RTEMSDeviceGRSPW2PNPOA0. + */ + uint32_t pnpoa0; + + /** + * @brief See @ref RTEMSDeviceGRSPW2PNPOA1. + */ + uint32_t pnpoa1; + + /** + * @brief See @ref RTEMSDeviceGRSPW2PNPOA2. + */ + uint32_t pnpoa2; + + /** + * @brief See @ref RTEMSDeviceGRSPW2PNPDEVID. + */ + uint32_t pnpdevid; + + /** + * @brief See @ref RTEMSDeviceGRSPW2PNPUVEND. + */ + uint32_t pnpuvend; + + /** + * @brief See @ref RTEMSDeviceGRSPW2PNPUSN. + */ + uint32_t pnpusn; +} grspw2; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRSPW2_REGS_H */ diff --git a/bsps/include/grlib/grspw_pkt.h b/bsps/include/grlib/grspw_pkt.h index ede60b72a8..489f240098 100644 --- a/bsps/include/grlib/grspw_pkt.h +++ b/bsps/include/grlib/grspw_pkt.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * GRSPW/GRSPW2 SpaceWire Kernel Library Interface * * COPYRIGHT (c) 2011 * Cobham Gaisler AB * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRSPW_PKT_H__ diff --git a/bsps/include/grlib/grspw_router.h b/bsps/include/grlib/grspw_router.h index 8547f19de3..55c67b599c 100644 --- a/bsps/include/grlib/grspw_router.h +++ b/bsps/include/grlib/grspw_router.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * GRSPW ROUTER APB-Register Driver. * * COPYRIGHT (c) 2010-2017. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRSPW_ROUTER_H__ diff --git a/bsps/include/grlib/grspwrouter-regs.h b/bsps/include/grlib/grspwrouter-regs.h new file mode 100644 index 0000000000..5b18ea8cad --- /dev/null +++ b/bsps/include/grlib/grspwrouter-regs.h @@ -0,0 +1,1759 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRSPWROUTER + * + * @brief This header file defines the GRSPWROUTER register block interface. + */ + +/* + * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grspwrouter-header */ + +#ifndef _GRLIB_GRSPWROUTER_REGS_H +#define _GRLIB_GRSPWROUTER_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grspwrouter-portstats */ + +/** + * @defgroup RTEMSDeviceGRSPWRouterPortStats SpaceWire Router Port Statistics + * + * @ingroup RTEMSDeviceGRSPWROUTER + * + * @brief This group contains the SpaceWire Router Port Statistics interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRSPWRouterPortStatsOCHARCNT \ + * Outgoing character counter, ports > 0 (OCHARCNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_OCHARCNT_OR 0x80000000U + +#define GRSPWROUTER_OCHARCNT_CC_SHIFT 0 +#define GRSPWROUTER_OCHARCNT_CC_MASK 0x7fffffffU +#define GRSPWROUTER_OCHARCNT_CC_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_OCHARCNT_CC_MASK ) >> \ + GRSPWROUTER_OCHARCNT_CC_SHIFT ) +#define GRSPWROUTER_OCHARCNT_CC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_OCHARCNT_CC_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_OCHARCNT_CC_SHIFT ) & \ + GRSPWROUTER_OCHARCNT_CC_MASK ) ) +#define GRSPWROUTER_OCHARCNT_CC( _val ) \ + ( ( ( _val ) << GRSPWROUTER_OCHARCNT_CC_SHIFT ) & \ + GRSPWROUTER_OCHARCNT_CC_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWRouterPortStatsICHARCNT \ + * Incoming character counter, ports > 0 (ICHARCNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_ICHARCNT_OR 0x80000000U + +#define GRSPWROUTER_ICHARCNT_CC_SHIFT 0 +#define GRSPWROUTER_ICHARCNT_CC_MASK 0x7fffffffU +#define GRSPWROUTER_ICHARCNT_CC_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_ICHARCNT_CC_MASK ) >> \ + GRSPWROUTER_ICHARCNT_CC_SHIFT ) +#define GRSPWROUTER_ICHARCNT_CC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_ICHARCNT_CC_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_ICHARCNT_CC_SHIFT ) & \ + GRSPWROUTER_ICHARCNT_CC_MASK ) ) +#define GRSPWROUTER_ICHARCNT_CC( _val ) \ + ( ( ( _val ) << GRSPWROUTER_ICHARCNT_CC_SHIFT ) & \ + GRSPWROUTER_ICHARCNT_CC_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWRouterPortStatsOPKTCNT \ + * Outgoing packet counter, ports > 0 (OPKTCNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_OPKTCNT_OR 0x80000000U + +#define GRSPWROUTER_OPKTCNT_PC_SHIFT 0 +#define GRSPWROUTER_OPKTCNT_PC_MASK 0x7fffffffU +#define GRSPWROUTER_OPKTCNT_PC_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_OPKTCNT_PC_MASK ) >> \ + GRSPWROUTER_OPKTCNT_PC_SHIFT ) +#define GRSPWROUTER_OPKTCNT_PC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_OPKTCNT_PC_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_OPKTCNT_PC_SHIFT ) & \ + GRSPWROUTER_OPKTCNT_PC_MASK ) ) +#define GRSPWROUTER_OPKTCNT_PC( _val ) \ + ( ( ( _val ) << GRSPWROUTER_OPKTCNT_PC_SHIFT ) & \ + GRSPWROUTER_OPKTCNT_PC_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWRouterPortStatsIPKTCNT \ + * Incoming packet counter, ports > 0 (IPKTCNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_IPKTCNT_OR 0x80000000U + +#define GRSPWROUTER_IPKTCNT_PC_SHIFT 0 +#define GRSPWROUTER_IPKTCNT_PC_MASK 0x7fffffffU +#define GRSPWROUTER_IPKTCNT_PC_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_IPKTCNT_PC_MASK ) >> \ + GRSPWROUTER_IPKTCNT_PC_SHIFT ) +#define GRSPWROUTER_IPKTCNT_PC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_IPKTCNT_PC_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_IPKTCNT_PC_SHIFT ) & \ + GRSPWROUTER_IPKTCNT_PC_MASK ) ) +#define GRSPWROUTER_IPKTCNT_PC( _val ) \ + ( ( ( _val ) << GRSPWROUTER_IPKTCNT_PC_SHIFT ) & \ + GRSPWROUTER_IPKTCNT_PC_MASK ) + +/** @} */ + +/** + * @brief This structure defines the SpaceWire Router Port Statistics register + * block memory map. + */ +typedef struct grspwrouter_portstats { + /** + * @brief See @ref RTEMSDeviceGRSPWRouterPortStatsOCHARCNT. + */ + uint32_t ocharcnt; + + /** + * @brief See @ref RTEMSDeviceGRSPWRouterPortStatsICHARCNT. + */ + uint32_t icharcnt; + + /** + * @brief See @ref RTEMSDeviceGRSPWRouterPortStatsOPKTCNT. + */ + uint32_t opktcnt; + + /** + * @brief See @ref RTEMSDeviceGRSPWRouterPortStatsIPKTCNT. + */ + uint32_t ipktcnt; +} grspwrouter_portstats; + +/** @} */ + +/* Generated from spec:/dev/grlib/if/grspwrouter */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTER SpaceWire Router + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the SpaceWire Router interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERRTPMAP \ + * Routing table port mapping, addresses 1-31 and 32-255 (RTPMAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_RTPMAP_PE_SHIFT 1 +#define GRSPWROUTER_RTPMAP_PE_MASK 0xfffffffeU +#define GRSPWROUTER_RTPMAP_PE_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_RTPMAP_PE_MASK ) >> \ + GRSPWROUTER_RTPMAP_PE_SHIFT ) +#define GRSPWROUTER_RTPMAP_PE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_RTPMAP_PE_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_RTPMAP_PE_SHIFT ) & \ + GRSPWROUTER_RTPMAP_PE_MASK ) ) +#define GRSPWROUTER_RTPMAP_PE( _val ) \ + ( ( ( _val ) << GRSPWROUTER_RTPMAP_PE_SHIFT ) & \ + GRSPWROUTER_RTPMAP_PE_MASK ) + +#define GRSPWROUTER_RTPMAP_PD 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERRTACTRL \ + * Routing table address control, addresses 1-31 and 32-255 (RTACTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_RTACTRL_SR 0x8U + +#define GRSPWROUTER_RTACTRL_EN 0x4U + +#define GRSPWROUTER_RTACTRL_PR 0x2U + +#define GRSPWROUTER_RTACTRL_HD 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERPCTRLCFG \ + * Port control, port 0 (configuration port) (PCTRLCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_PCTRLCFG_PL 0x20000U + +#define GRSPWROUTER_PCTRLCFG_TS 0x10000U + +#define GRSPWROUTER_PCTRLCFG_TR 0x200U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERPCTRL Port control, ports > 0 (PCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_PCTRL_RD_SHIFT 24 +#define GRSPWROUTER_PCTRL_RD_MASK 0xff000000U +#define GRSPWROUTER_PCTRL_RD_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PCTRL_RD_MASK ) >> \ + GRSPWROUTER_PCTRL_RD_SHIFT ) +#define GRSPWROUTER_PCTRL_RD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL_RD_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PCTRL_RD_SHIFT ) & \ + GRSPWROUTER_PCTRL_RD_MASK ) ) +#define GRSPWROUTER_PCTRL_RD( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PCTRL_RD_SHIFT ) & \ + GRSPWROUTER_PCTRL_RD_MASK ) + +#define GRSPWROUTER_PCTRL_RES_SHIFT 22 +#define GRSPWROUTER_PCTRL_RES_MASK 0xc00000U +#define GRSPWROUTER_PCTRL_RES_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PCTRL_RES_MASK ) >> \ + GRSPWROUTER_PCTRL_RES_SHIFT ) +#define GRSPWROUTER_PCTRL_RES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL_RES_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PCTRL_RES_SHIFT ) & \ + GRSPWROUTER_PCTRL_RES_MASK ) ) +#define GRSPWROUTER_PCTRL_RES( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PCTRL_RES_SHIFT ) & \ + GRSPWROUTER_PCTRL_RES_MASK ) + +#define GRSPWROUTER_PCTRL_ST 0x200000U + +#define GRSPWROUTER_PCTRL_SR 0x100000U + +#define GRSPWROUTER_PCTRL_AD 0x80000U + +#define GRSPWROUTER_PCTRL_LR 0x40000U + +#define GRSPWROUTER_PCTRL_PL 0x20000U + +#define GRSPWROUTER_PCTRL_TS 0x10000U + +#define GRSPWROUTER_PCTRL_IC 0x8000U + +#define GRSPWROUTER_PCTRL_ET 0x4000U + +#define GRSPWROUTER_PCTRL_NF 0x2000U + +#define GRSPWROUTER_PCTRL_PS 0x1000U + +#define GRSPWROUTER_PCTRL_BE 0x800U + +#define GRSPWROUTER_PCTRL_DI 0x400U + +#define GRSPWROUTER_PCTRL_TR 0x200U + +#define GRSPWROUTER_PCTRL_PR 0x100U + +#define GRSPWROUTER_PCTRL_TF 0x80U + +#define GRSPWROUTER_PCTRL_RS 0x40U + +#define GRSPWROUTER_PCTRL_TE 0x20U + +#define GRSPWROUTER_PCTRL_R 0x10U + +#define GRSPWROUTER_PCTRL_CE 0x8U + +#define GRSPWROUTER_PCTRL_AS 0x4U + +#define GRSPWROUTER_PCTRL_LS 0x2U + +#define GRSPWROUTER_PCTRL_LD 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERPSTSCFG \ + * Port status, port 0 (configuration port) (PSTSCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_PSTSCFG_EO 0x80000000U + +#define GRSPWROUTER_PSTSCFG_EE 0x40000000U + +#define GRSPWROUTER_PSTSCFG_PL 0x20000000U + +#define GRSPWROUTER_PSTSCFG_TT 0x10000000U + +#define GRSPWROUTER_PSTSCFG_PT 0x8000000U + +#define GRSPWROUTER_PSTSCFG_HC 0x4000000U + +#define GRSPWROUTER_PSTSCFG_PI 0x2000000U + +#define GRSPWROUTER_PSTSCFG_CE 0x1000000U + +#define GRSPWROUTER_PSTSCFG_EC_SHIFT 20 +#define GRSPWROUTER_PSTSCFG_EC_MASK 0xf00000U +#define GRSPWROUTER_PSTSCFG_EC_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PSTSCFG_EC_MASK ) >> \ + GRSPWROUTER_PSTSCFG_EC_SHIFT ) +#define GRSPWROUTER_PSTSCFG_EC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_EC_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PSTSCFG_EC_SHIFT ) & \ + GRSPWROUTER_PSTSCFG_EC_MASK ) ) +#define GRSPWROUTER_PSTSCFG_EC( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PSTSCFG_EC_SHIFT ) & \ + GRSPWROUTER_PSTSCFG_EC_MASK ) + +#define GRSPWROUTER_PSTSCFG_R 0x80000U + +#define GRSPWROUTER_PSTSCFG_TS 0x40000U + +#define GRSPWROUTER_PSTSCFG_ME 0x20000U + +#define GRSPWROUTER_PSTSCFG_IP_SHIFT 7 +#define GRSPWROUTER_PSTSCFG_IP_MASK 0xf80U +#define GRSPWROUTER_PSTSCFG_IP_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PSTSCFG_IP_MASK ) >> \ + GRSPWROUTER_PSTSCFG_IP_SHIFT ) +#define GRSPWROUTER_PSTSCFG_IP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_IP_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PSTSCFG_IP_SHIFT ) & \ + GRSPWROUTER_PSTSCFG_IP_MASK ) ) +#define GRSPWROUTER_PSTSCFG_IP( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PSTSCFG_IP_SHIFT ) & \ + GRSPWROUTER_PSTSCFG_IP_MASK ) + +#define GRSPWROUTER_PSTSCFG_RES_SHIFT 5 +#define GRSPWROUTER_PSTSCFG_RES_MASK 0x60U +#define GRSPWROUTER_PSTSCFG_RES_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PSTSCFG_RES_MASK ) >> \ + GRSPWROUTER_PSTSCFG_RES_SHIFT ) +#define GRSPWROUTER_PSTSCFG_RES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_RES_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PSTSCFG_RES_SHIFT ) & \ + GRSPWROUTER_PSTSCFG_RES_MASK ) ) +#define GRSPWROUTER_PSTSCFG_RES( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PSTSCFG_RES_SHIFT ) & \ + GRSPWROUTER_PSTSCFG_RES_MASK ) + +#define GRSPWROUTER_PSTSCFG_CP 0x10U + +#define GRSPWROUTER_PSTSCFG_PC_SHIFT 0 +#define GRSPWROUTER_PSTSCFG_PC_MASK 0xfU +#define GRSPWROUTER_PSTSCFG_PC_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PSTSCFG_PC_MASK ) >> \ + GRSPWROUTER_PSTSCFG_PC_SHIFT ) +#define GRSPWROUTER_PSTSCFG_PC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTSCFG_PC_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PSTSCFG_PC_SHIFT ) & \ + GRSPWROUTER_PSTSCFG_PC_MASK ) ) +#define GRSPWROUTER_PSTSCFG_PC( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PSTSCFG_PC_SHIFT ) & \ + GRSPWROUTER_PSTSCFG_PC_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERPSTS Port status, ports > 0 (PSTS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_PSTS_PT_SHIFT 30 +#define GRSPWROUTER_PSTS_PT_MASK 0xc0000000U +#define GRSPWROUTER_PSTS_PT_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PSTS_PT_MASK ) >> \ + GRSPWROUTER_PSTS_PT_SHIFT ) +#define GRSPWROUTER_PSTS_PT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTS_PT_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PSTS_PT_SHIFT ) & \ + GRSPWROUTER_PSTS_PT_MASK ) ) +#define GRSPWROUTER_PSTS_PT( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PSTS_PT_SHIFT ) & \ + GRSPWROUTER_PSTS_PT_MASK ) + +#define GRSPWROUTER_PSTS_PL 0x20000000U + +#define GRSPWROUTER_PSTS_TT 0x10000000U + +#define GRSPWROUTER_PSTS_RS 0x8000000U + +#define GRSPWROUTER_PSTS_SR 0x4000000U + +#define GRSPWROUTER_PSTS_LR 0x400000U + +#define GRSPWROUTER_PSTS_SP 0x200000U + +#define GRSPWROUTER_PSTS_AC 0x100000U + +#define GRSPWROUTER_PSTS_AP 0x80000U + +#define GRSPWROUTER_PSTS_TS 0x40000U + +#define GRSPWROUTER_PSTS_ME 0x20000U + +#define GRSPWROUTER_PSTS_TF 0x10000U + +#define GRSPWROUTER_PSTS_RE 0x8000U + +#define GRSPWROUTER_PSTS_LS_SHIFT 12 +#define GRSPWROUTER_PSTS_LS_MASK 0x7000U +#define GRSPWROUTER_PSTS_LS_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PSTS_LS_MASK ) >> \ + GRSPWROUTER_PSTS_LS_SHIFT ) +#define GRSPWROUTER_PSTS_LS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTS_LS_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PSTS_LS_SHIFT ) & \ + GRSPWROUTER_PSTS_LS_MASK ) ) +#define GRSPWROUTER_PSTS_LS( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PSTS_LS_SHIFT ) & \ + GRSPWROUTER_PSTS_LS_MASK ) + +#define GRSPWROUTER_PSTS_IP_SHIFT 7 +#define GRSPWROUTER_PSTS_IP_MASK 0xf80U +#define GRSPWROUTER_PSTS_IP_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PSTS_IP_MASK ) >> \ + GRSPWROUTER_PSTS_IP_SHIFT ) +#define GRSPWROUTER_PSTS_IP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PSTS_IP_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PSTS_IP_SHIFT ) & \ + GRSPWROUTER_PSTS_IP_MASK ) ) +#define GRSPWROUTER_PSTS_IP( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PSTS_IP_SHIFT ) & \ + GRSPWROUTER_PSTS_IP_MASK ) + +#define GRSPWROUTER_PSTS_PR 0x40U + +#define GRSPWROUTER_PSTS_PB 0x20U + +#define GRSPWROUTER_PSTS_IA 0x10U + +#define GRSPWROUTER_PSTS_CE 0x8U + +#define GRSPWROUTER_PSTS_ER 0x4U + +#define GRSPWROUTER_PSTS_DE 0x2U + +#define GRSPWROUTER_PSTS_PE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERPTIMER Port timer reload (PTIMER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_PTIMER_RL_SHIFT 0 +#define GRSPWROUTER_PTIMER_RL_MASK 0x3ffU +#define GRSPWROUTER_PTIMER_RL_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PTIMER_RL_MASK ) >> \ + GRSPWROUTER_PTIMER_RL_SHIFT ) +#define GRSPWROUTER_PTIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PTIMER_RL_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PTIMER_RL_SHIFT ) & \ + GRSPWROUTER_PTIMER_RL_MASK ) ) +#define GRSPWROUTER_PTIMER_RL( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PTIMER_RL_SHIFT ) & \ + GRSPWROUTER_PTIMER_RL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERPCTRL2CFG \ + * Port control 2, port 0 (configuration port) (PCTRL2CFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_PCTRL2CFG_SM_SHIFT 24 +#define GRSPWROUTER_PCTRL2CFG_SM_MASK 0xff000000U +#define GRSPWROUTER_PCTRL2CFG_SM_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PCTRL2CFG_SM_MASK ) >> \ + GRSPWROUTER_PCTRL2CFG_SM_SHIFT ) +#define GRSPWROUTER_PCTRL2CFG_SM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2CFG_SM_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PCTRL2CFG_SM_SHIFT ) & \ + GRSPWROUTER_PCTRL2CFG_SM_MASK ) ) +#define GRSPWROUTER_PCTRL2CFG_SM( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PCTRL2CFG_SM_SHIFT ) & \ + GRSPWROUTER_PCTRL2CFG_SM_MASK ) + +#define GRSPWROUTER_PCTRL2CFG_SV_SHIFT 16 +#define GRSPWROUTER_PCTRL2CFG_SV_MASK 0xff0000U +#define GRSPWROUTER_PCTRL2CFG_SV_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PCTRL2CFG_SV_MASK ) >> \ + GRSPWROUTER_PCTRL2CFG_SV_SHIFT ) +#define GRSPWROUTER_PCTRL2CFG_SV_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2CFG_SV_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PCTRL2CFG_SV_SHIFT ) & \ + GRSPWROUTER_PCTRL2CFG_SV_MASK ) ) +#define GRSPWROUTER_PCTRL2CFG_SV( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PCTRL2CFG_SV_SHIFT ) & \ + GRSPWROUTER_PCTRL2CFG_SV_MASK ) + +#define GRSPWROUTER_PCTRL2CFG_OR 0x8000U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERPCTRL2 Port control 2, ports > 0 (PCTRL2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_PCTRL2_SM_SHIFT 24 +#define GRSPWROUTER_PCTRL2_SM_MASK 0xff000000U +#define GRSPWROUTER_PCTRL2_SM_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PCTRL2_SM_MASK ) >> \ + GRSPWROUTER_PCTRL2_SM_SHIFT ) +#define GRSPWROUTER_PCTRL2_SM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2_SM_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PCTRL2_SM_SHIFT ) & \ + GRSPWROUTER_PCTRL2_SM_MASK ) ) +#define GRSPWROUTER_PCTRL2_SM( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PCTRL2_SM_SHIFT ) & \ + GRSPWROUTER_PCTRL2_SM_MASK ) + +#define GRSPWROUTER_PCTRL2_SV_SHIFT 16 +#define GRSPWROUTER_PCTRL2_SV_MASK 0xff0000U +#define GRSPWROUTER_PCTRL2_SV_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PCTRL2_SV_MASK ) >> \ + GRSPWROUTER_PCTRL2_SV_SHIFT ) +#define GRSPWROUTER_PCTRL2_SV_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2_SV_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PCTRL2_SV_SHIFT ) & \ + GRSPWROUTER_PCTRL2_SV_MASK ) ) +#define GRSPWROUTER_PCTRL2_SV( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PCTRL2_SV_SHIFT ) & \ + GRSPWROUTER_PCTRL2_SV_MASK ) + +#define GRSPWROUTER_PCTRL2_OR 0x8000U + +#define GRSPWROUTER_PCTRL2_UR 0x4000U + +#define GRSPWROUTER_PCTRL2_R 0x2000U + +#define GRSPWROUTER_PCTRL2_AT 0x1000U + +#define GRSPWROUTER_PCTRL2_AR 0x800U + +#define GRSPWROUTER_PCTRL2_IT 0x400U + +#define GRSPWROUTER_PCTRL2_IR 0x200U + +#define GRSPWROUTER_PCTRL2_SD_SHIFT 1 +#define GRSPWROUTER_PCTRL2_SD_MASK 0x3eU +#define GRSPWROUTER_PCTRL2_SD_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PCTRL2_SD_MASK ) >> \ + GRSPWROUTER_PCTRL2_SD_SHIFT ) +#define GRSPWROUTER_PCTRL2_SD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PCTRL2_SD_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PCTRL2_SD_SHIFT ) & \ + GRSPWROUTER_PCTRL2_SD_MASK ) ) +#define GRSPWROUTER_PCTRL2_SD( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PCTRL2_SD_SHIFT ) & \ + GRSPWROUTER_PCTRL2_SD_MASK ) + +#define GRSPWROUTER_PCTRL2_SC 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERRTRCFG \ + * Router configuration / status (RTRCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_RTRCFG_SP_SHIFT 27 +#define GRSPWROUTER_RTRCFG_SP_MASK 0xf8000000U +#define GRSPWROUTER_RTRCFG_SP_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_RTRCFG_SP_MASK ) >> \ + GRSPWROUTER_RTRCFG_SP_SHIFT ) +#define GRSPWROUTER_RTRCFG_SP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_RTRCFG_SP_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_RTRCFG_SP_SHIFT ) & \ + GRSPWROUTER_RTRCFG_SP_MASK ) ) +#define GRSPWROUTER_RTRCFG_SP( _val ) \ + ( ( ( _val ) << GRSPWROUTER_RTRCFG_SP_SHIFT ) & \ + GRSPWROUTER_RTRCFG_SP_MASK ) + +#define GRSPWROUTER_RTRCFG_AP_SHIFT 22 +#define GRSPWROUTER_RTRCFG_AP_MASK 0x7c00000U +#define GRSPWROUTER_RTRCFG_AP_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_RTRCFG_AP_MASK ) >> \ + GRSPWROUTER_RTRCFG_AP_SHIFT ) +#define GRSPWROUTER_RTRCFG_AP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_RTRCFG_AP_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_RTRCFG_AP_SHIFT ) & \ + GRSPWROUTER_RTRCFG_AP_MASK ) ) +#define GRSPWROUTER_RTRCFG_AP( _val ) \ + ( ( ( _val ) << GRSPWROUTER_RTRCFG_AP_SHIFT ) & \ + GRSPWROUTER_RTRCFG_AP_MASK ) + +#define GRSPWROUTER_RTRCFG_FP_SHIFT 17 +#define GRSPWROUTER_RTRCFG_FP_MASK 0x3e0000U +#define GRSPWROUTER_RTRCFG_FP_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_RTRCFG_FP_MASK ) >> \ + GRSPWROUTER_RTRCFG_FP_SHIFT ) +#define GRSPWROUTER_RTRCFG_FP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_RTRCFG_FP_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_RTRCFG_FP_SHIFT ) & \ + GRSPWROUTER_RTRCFG_FP_MASK ) ) +#define GRSPWROUTER_RTRCFG_FP( _val ) \ + ( ( ( _val ) << GRSPWROUTER_RTRCFG_FP_SHIFT ) & \ + GRSPWROUTER_RTRCFG_FP_MASK ) + +#define GRSPWROUTER_RTRCFG_R 0x10000U + +#define GRSPWROUTER_RTRCFG_SR 0x8000U + +#define GRSPWROUTER_RTRCFG_PE 0x4000U + +#define GRSPWROUTER_RTRCFG_IC 0x2000U + +#define GRSPWROUTER_RTRCFG_IS 0x1000U + +#define GRSPWROUTER_RTRCFG_IP 0x800U + +#define GRSPWROUTER_RTRCFG_AI 0x400U + +#define GRSPWROUTER_RTRCFG_AT 0x200U + +#define GRSPWROUTER_RTRCFG_IE 0x100U + +#define GRSPWROUTER_RTRCFG_RE 0x80U + +#define GRSPWROUTER_RTRCFG_EE 0x40U + +#define GRSPWROUTER_RTRCFG_R 0x20U + +#define GRSPWROUTER_RTRCFG_SA 0x10U + +#define GRSPWROUTER_RTRCFG_TF 0x8U + +#define GRSPWROUTER_RTRCFG_RM 0x4U + +#define GRSPWROUTER_RTRCFG_TA 0x2U + +#define GRSPWROUTER_RTRCFG_PP 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERTC Time-code (TC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_TC_RE 0x200U + +#define GRSPWROUTER_TC_EN 0x100U + +#define GRSPWROUTER_TC_CF_SHIFT 6 +#define GRSPWROUTER_TC_CF_MASK 0xc0U +#define GRSPWROUTER_TC_CF_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_TC_CF_MASK ) >> \ + GRSPWROUTER_TC_CF_SHIFT ) +#define GRSPWROUTER_TC_CF_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_TC_CF_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_TC_CF_SHIFT ) & \ + GRSPWROUTER_TC_CF_MASK ) ) +#define GRSPWROUTER_TC_CF( _val ) \ + ( ( ( _val ) << GRSPWROUTER_TC_CF_SHIFT ) & \ + GRSPWROUTER_TC_CF_MASK ) + +#define GRSPWROUTER_TC_TC_SHIFT 0 +#define GRSPWROUTER_TC_TC_MASK 0x3fU +#define GRSPWROUTER_TC_TC_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_TC_TC_MASK ) >> \ + GRSPWROUTER_TC_TC_SHIFT ) +#define GRSPWROUTER_TC_TC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_TC_TC_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_TC_TC_SHIFT ) & \ + GRSPWROUTER_TC_TC_MASK ) ) +#define GRSPWROUTER_TC_TC( _val ) \ + ( ( ( _val ) << GRSPWROUTER_TC_TC_SHIFT ) & \ + GRSPWROUTER_TC_TC_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERVER Version / instance ID (VER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_VER_MA_SHIFT 24 +#define GRSPWROUTER_VER_MA_MASK 0xff000000U +#define GRSPWROUTER_VER_MA_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_VER_MA_MASK ) >> \ + GRSPWROUTER_VER_MA_SHIFT ) +#define GRSPWROUTER_VER_MA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_VER_MA_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_VER_MA_SHIFT ) & \ + GRSPWROUTER_VER_MA_MASK ) ) +#define GRSPWROUTER_VER_MA( _val ) \ + ( ( ( _val ) << GRSPWROUTER_VER_MA_SHIFT ) & \ + GRSPWROUTER_VER_MA_MASK ) + +#define GRSPWROUTER_VER_MI_SHIFT 16 +#define GRSPWROUTER_VER_MI_MASK 0xff0000U +#define GRSPWROUTER_VER_MI_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_VER_MI_MASK ) >> \ + GRSPWROUTER_VER_MI_SHIFT ) +#define GRSPWROUTER_VER_MI_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_VER_MI_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_VER_MI_SHIFT ) & \ + GRSPWROUTER_VER_MI_MASK ) ) +#define GRSPWROUTER_VER_MI( _val ) \ + ( ( ( _val ) << GRSPWROUTER_VER_MI_SHIFT ) & \ + GRSPWROUTER_VER_MI_MASK ) + +#define GRSPWROUTER_VER_PA_SHIFT 8 +#define GRSPWROUTER_VER_PA_MASK 0xff00U +#define GRSPWROUTER_VER_PA_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_VER_PA_MASK ) >> \ + GRSPWROUTER_VER_PA_SHIFT ) +#define GRSPWROUTER_VER_PA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_VER_PA_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_VER_PA_SHIFT ) & \ + GRSPWROUTER_VER_PA_MASK ) ) +#define GRSPWROUTER_VER_PA( _val ) \ + ( ( ( _val ) << GRSPWROUTER_VER_PA_SHIFT ) & \ + GRSPWROUTER_VER_PA_MASK ) + +#define GRSPWROUTER_VER_ID_SHIFT 0 +#define GRSPWROUTER_VER_ID_MASK 0xffU +#define GRSPWROUTER_VER_ID_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_VER_ID_MASK ) >> \ + GRSPWROUTER_VER_ID_SHIFT ) +#define GRSPWROUTER_VER_ID_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_VER_ID_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_VER_ID_SHIFT ) & \ + GRSPWROUTER_VER_ID_MASK ) ) +#define GRSPWROUTER_VER_ID( _val ) \ + ( ( ( _val ) << GRSPWROUTER_VER_ID_SHIFT ) & \ + GRSPWROUTER_VER_ID_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERIDIV Initialization divisor (IDIV) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_IDIV_ID_SHIFT 0 +#define GRSPWROUTER_IDIV_ID_MASK 0xffU +#define GRSPWROUTER_IDIV_ID_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_IDIV_ID_MASK ) >> \ + GRSPWROUTER_IDIV_ID_SHIFT ) +#define GRSPWROUTER_IDIV_ID_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_IDIV_ID_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_IDIV_ID_SHIFT ) & \ + GRSPWROUTER_IDIV_ID_MASK ) ) +#define GRSPWROUTER_IDIV_ID( _val ) \ + ( ( ( _val ) << GRSPWROUTER_IDIV_ID_SHIFT ) & \ + GRSPWROUTER_IDIV_ID_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERCFGWE \ + * Configuration port write enable (CFGWE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_CFGWE_WE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERPRESCALER Timer prescaler reload (PRESCALER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_PRESCALER_RL_SHIFT 0 +#define GRSPWROUTER_PRESCALER_RL_MASK 0xffffffffU +#define GRSPWROUTER_PRESCALER_RL_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PRESCALER_RL_MASK ) >> \ + GRSPWROUTER_PRESCALER_RL_SHIFT ) +#define GRSPWROUTER_PRESCALER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PRESCALER_RL_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PRESCALER_RL_SHIFT ) & \ + GRSPWROUTER_PRESCALER_RL_MASK ) ) +#define GRSPWROUTER_PRESCALER_RL( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PRESCALER_RL_SHIFT ) & \ + GRSPWROUTER_PRESCALER_RL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERIMASK Interrupt mask (IMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_IMASK_PE 0x400U + +#define GRSPWROUTER_IMASK_SR 0x200U + +#define GRSPWROUTER_IMASK_RS 0x100U + +#define GRSPWROUTER_IMASK_TT 0x80U + +#define GRSPWROUTER_IMASK_PL 0x40U + +#define GRSPWROUTER_IMASK_TS 0x20U + +#define GRSPWROUTER_IMASK_AC 0x10U + +#define GRSPWROUTER_IMASK_RE 0x8U + +#define GRSPWROUTER_IMASK_IA 0x4U + +#define GRSPWROUTER_IMASK_LE 0x2U + +#define GRSPWROUTER_IMASK_ME 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERIPMASK Interrupt port mask (IPMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_IPMASK_IE_SHIFT 0 +#define GRSPWROUTER_IPMASK_IE_MASK 0xffffffffU +#define GRSPWROUTER_IPMASK_IE_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_IPMASK_IE_MASK ) >> \ + GRSPWROUTER_IPMASK_IE_SHIFT ) +#define GRSPWROUTER_IPMASK_IE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_IPMASK_IE_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_IPMASK_IE_SHIFT ) & \ + GRSPWROUTER_IPMASK_IE_MASK ) ) +#define GRSPWROUTER_IPMASK_IE( _val ) \ + ( ( ( _val ) << GRSPWROUTER_IPMASK_IE_SHIFT ) & \ + GRSPWROUTER_IPMASK_IE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERPIP Port interrupt pending (PIP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_PIP_IP_SHIFT 0 +#define GRSPWROUTER_PIP_IP_MASK 0xffffffffU +#define GRSPWROUTER_PIP_IP_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PIP_IP_MASK ) >> \ + GRSPWROUTER_PIP_IP_SHIFT ) +#define GRSPWROUTER_PIP_IP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PIP_IP_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PIP_IP_SHIFT ) & \ + GRSPWROUTER_PIP_IP_MASK ) ) +#define GRSPWROUTER_PIP_IP( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PIP_IP_SHIFT ) & \ + GRSPWROUTER_PIP_IP_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERICODEGEN \ + * Interrupt code generation (ICODEGEN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_ICODEGEN_HI 0x200000U + +#define GRSPWROUTER_ICODEGEN_UA 0x100000U + +#define GRSPWROUTER_ICODEGEN_AH 0x80000U + +#define GRSPWROUTER_ICODEGEN_IT 0x40000U + +#define GRSPWROUTER_ICODEGEN_TE 0x1U + +#define GRSPWROUTER_ICODEGEN_EN 0x20000U + +#define GRSPWROUTER_ICODEGEN_IN_SHIFT 6 +#define GRSPWROUTER_ICODEGEN_IN_MASK 0xffc0U +#define GRSPWROUTER_ICODEGEN_IN_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_ICODEGEN_IN_MASK ) >> \ + GRSPWROUTER_ICODEGEN_IN_SHIFT ) +#define GRSPWROUTER_ICODEGEN_IN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_ICODEGEN_IN_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_ICODEGEN_IN_SHIFT ) & \ + GRSPWROUTER_ICODEGEN_IN_MASK ) ) +#define GRSPWROUTER_ICODEGEN_IN( _val ) \ + ( ( ( _val ) << GRSPWROUTER_ICODEGEN_IN_SHIFT ) & \ + GRSPWROUTER_ICODEGEN_IN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERISR0 \ + * Interrupt code distribution ISR register, interrupt 0-31 (ISR0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_ISR0_IB_SHIFT 0 +#define GRSPWROUTER_ISR0_IB_MASK 0xffffffffU +#define GRSPWROUTER_ISR0_IB_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_ISR0_IB_MASK ) >> \ + GRSPWROUTER_ISR0_IB_SHIFT ) +#define GRSPWROUTER_ISR0_IB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_ISR0_IB_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_ISR0_IB_SHIFT ) & \ + GRSPWROUTER_ISR0_IB_MASK ) ) +#define GRSPWROUTER_ISR0_IB( _val ) \ + ( ( ( _val ) << GRSPWROUTER_ISR0_IB_SHIFT ) & \ + GRSPWROUTER_ISR0_IB_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERISR1 \ + * Interrupt code distribution ISR register, interrupt 32-63 (ISR1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_ISR1_IB_SHIFT 0 +#define GRSPWROUTER_ISR1_IB_MASK 0xffffffffU +#define GRSPWROUTER_ISR1_IB_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_ISR1_IB_MASK ) >> \ + GRSPWROUTER_ISR1_IB_SHIFT ) +#define GRSPWROUTER_ISR1_IB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_ISR1_IB_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_ISR1_IB_SHIFT ) & \ + GRSPWROUTER_ISR1_IB_MASK ) ) +#define GRSPWROUTER_ISR1_IB( _val ) \ + ( ( ( _val ) << GRSPWROUTER_ISR1_IB_SHIFT ) & \ + GRSPWROUTER_ISR1_IB_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERISRTIMER \ + * Interrupt code distribution ISR timer reload (ISRTIMER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_ISRTIMER_RL_SHIFT 0 +#define GRSPWROUTER_ISRTIMER_RL_MASK 0xffffffffU +#define GRSPWROUTER_ISRTIMER_RL_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_ISRTIMER_RL_MASK ) >> \ + GRSPWROUTER_ISRTIMER_RL_SHIFT ) +#define GRSPWROUTER_ISRTIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_ISRTIMER_RL_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_ISRTIMER_RL_SHIFT ) & \ + GRSPWROUTER_ISRTIMER_RL_MASK ) ) +#define GRSPWROUTER_ISRTIMER_RL( _val ) \ + ( ( ( _val ) << GRSPWROUTER_ISRTIMER_RL_SHIFT ) & \ + GRSPWROUTER_ISRTIMER_RL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAITIMER \ + * Interrupt code distribution ACK-to-INT timer reload (AITIMER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AITIMER_RL_SHIFT 0 +#define GRSPWROUTER_AITIMER_RL_MASK 0xffffffffU +#define GRSPWROUTER_AITIMER_RL_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_AITIMER_RL_MASK ) >> \ + GRSPWROUTER_AITIMER_RL_SHIFT ) +#define GRSPWROUTER_AITIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_AITIMER_RL_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_AITIMER_RL_SHIFT ) & \ + GRSPWROUTER_AITIMER_RL_MASK ) ) +#define GRSPWROUTER_AITIMER_RL( _val ) \ + ( ( ( _val ) << GRSPWROUTER_AITIMER_RL_SHIFT ) & \ + GRSPWROUTER_AITIMER_RL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERISRCTIMER \ + * Interrupt code distribution ISR change timer reload (ISRCTIMER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_ISRCTIMER_RL_SHIFT 0 +#define GRSPWROUTER_ISRCTIMER_RL_MASK 0x1fU +#define GRSPWROUTER_ISRCTIMER_RL_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_ISRCTIMER_RL_MASK ) >> \ + GRSPWROUTER_ISRCTIMER_RL_SHIFT ) +#define GRSPWROUTER_ISRCTIMER_RL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_ISRCTIMER_RL_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_ISRCTIMER_RL_SHIFT ) & \ + GRSPWROUTER_ISRCTIMER_RL_MASK ) ) +#define GRSPWROUTER_ISRCTIMER_RL( _val ) \ + ( ( ( _val ) << GRSPWROUTER_ISRCTIMER_RL_SHIFT ) & \ + GRSPWROUTER_ISRCTIMER_RL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERLRUNSTAT Link running status (LRUNSTAT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_LRUNSTAT_LR_SHIFT 1 +#define GRSPWROUTER_LRUNSTAT_LR_MASK 0xfffffffeU +#define GRSPWROUTER_LRUNSTAT_LR_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_LRUNSTAT_LR_MASK ) >> \ + GRSPWROUTER_LRUNSTAT_LR_SHIFT ) +#define GRSPWROUTER_LRUNSTAT_LR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_LRUNSTAT_LR_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_LRUNSTAT_LR_SHIFT ) & \ + GRSPWROUTER_LRUNSTAT_LR_MASK ) ) +#define GRSPWROUTER_LRUNSTAT_LR( _val ) \ + ( ( ( _val ) << GRSPWROUTER_LRUNSTAT_LR_SHIFT ) & \ + GRSPWROUTER_LRUNSTAT_LR_MASK ) + +#define GRSPWROUTER_LRUNSTAT_R 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERCAP Capability (CAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_CAP_AF_SHIFT 24 +#define GRSPWROUTER_CAP_AF_MASK 0x3000000U +#define GRSPWROUTER_CAP_AF_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_CAP_AF_MASK ) >> \ + GRSPWROUTER_CAP_AF_SHIFT ) +#define GRSPWROUTER_CAP_AF_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_CAP_AF_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_CAP_AF_SHIFT ) & \ + GRSPWROUTER_CAP_AF_MASK ) ) +#define GRSPWROUTER_CAP_AF( _val ) \ + ( ( ( _val ) << GRSPWROUTER_CAP_AF_SHIFT ) & \ + GRSPWROUTER_CAP_AF_MASK ) + +#define GRSPWROUTER_CAP_R 0x800000U + +#define GRSPWROUTER_CAP_PF_SHIFT 20 +#define GRSPWROUTER_CAP_PF_MASK 0x700000U +#define GRSPWROUTER_CAP_PF_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_CAP_PF_MASK ) >> \ + GRSPWROUTER_CAP_PF_SHIFT ) +#define GRSPWROUTER_CAP_PF_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_CAP_PF_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_CAP_PF_SHIFT ) & \ + GRSPWROUTER_CAP_PF_MASK ) ) +#define GRSPWROUTER_CAP_PF( _val ) \ + ( ( ( _val ) << GRSPWROUTER_CAP_PF_SHIFT ) & \ + GRSPWROUTER_CAP_PF_MASK ) + +#define GRSPWROUTER_CAP_R 0x80000U + +#define GRSPWROUTER_CAP_RM_SHIFT 16 +#define GRSPWROUTER_CAP_RM_MASK 0x70000U +#define GRSPWROUTER_CAP_RM_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_CAP_RM_MASK ) >> \ + GRSPWROUTER_CAP_RM_SHIFT ) +#define GRSPWROUTER_CAP_RM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_CAP_RM_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_CAP_RM_SHIFT ) & \ + GRSPWROUTER_CAP_RM_MASK ) ) +#define GRSPWROUTER_CAP_RM( _val ) \ + ( ( ( _val ) << GRSPWROUTER_CAP_RM_SHIFT ) & \ + GRSPWROUTER_CAP_RM_MASK ) + +#define GRSPWROUTER_CAP_R 0x8000U + +#define GRSPWROUTER_CAP_AA 0x4000U + +#define GRSPWROUTER_CAP_AX 0x2000U + +#define GRSPWROUTER_CAP_DP 0x1000U + +#define GRSPWROUTER_CAP_ID 0x800U + +#define GRSPWROUTER_CAP_SD 0x400U + +#define GRSPWROUTER_CAP_PC_SHIFT 5 +#define GRSPWROUTER_CAP_PC_MASK 0x3e0U +#define GRSPWROUTER_CAP_PC_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_CAP_PC_MASK ) >> \ + GRSPWROUTER_CAP_PC_SHIFT ) +#define GRSPWROUTER_CAP_PC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_CAP_PC_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_CAP_PC_SHIFT ) & \ + GRSPWROUTER_CAP_PC_MASK ) ) +#define GRSPWROUTER_CAP_PC( _val ) \ + ( ( ( _val ) << GRSPWROUTER_CAP_PC_SHIFT ) & \ + GRSPWROUTER_CAP_PC_MASK ) + +#define GRSPWROUTER_CAP_CC_SHIFT 0 +#define GRSPWROUTER_CAP_CC_MASK 0x1fU +#define GRSPWROUTER_CAP_CC_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_CAP_CC_MASK ) >> \ + GRSPWROUTER_CAP_CC_SHIFT ) +#define GRSPWROUTER_CAP_CC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_CAP_CC_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_CAP_CC_SHIFT ) & \ + GRSPWROUTER_CAP_CC_MASK ) ) +#define GRSPWROUTER_CAP_CC( _val ) \ + ( ( ( _val ) << GRSPWROUTER_CAP_CC_SHIFT ) & \ + GRSPWROUTER_CAP_CC_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERPNPVEND \ + * SpaceWire Plug-and-Play - Device Vendor and Product ID (PNPVEND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_PNPVEND_VI_SHIFT 16 +#define GRSPWROUTER_PNPVEND_VI_MASK 0xffff0000U +#define GRSPWROUTER_PNPVEND_VI_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PNPVEND_VI_MASK ) >> \ + GRSPWROUTER_PNPVEND_VI_SHIFT ) +#define GRSPWROUTER_PNPVEND_VI_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PNPVEND_VI_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PNPVEND_VI_SHIFT ) & \ + GRSPWROUTER_PNPVEND_VI_MASK ) ) +#define GRSPWROUTER_PNPVEND_VI( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PNPVEND_VI_SHIFT ) & \ + GRSPWROUTER_PNPVEND_VI_MASK ) + +#define GRSPWROUTER_PNPVEND_PI_SHIFT 0 +#define GRSPWROUTER_PNPVEND_PI_MASK 0x3ffffffU +#define GRSPWROUTER_PNPVEND_PI_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PNPVEND_PI_MASK ) >> \ + GRSPWROUTER_PNPVEND_PI_SHIFT ) +#define GRSPWROUTER_PNPVEND_PI_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PNPVEND_PI_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PNPVEND_PI_SHIFT ) & \ + GRSPWROUTER_PNPVEND_PI_MASK ) ) +#define GRSPWROUTER_PNPVEND_PI( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PNPVEND_PI_SHIFT ) & \ + GRSPWROUTER_PNPVEND_PI_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERPNPUVEND \ + * SpaceWire Plug-and-Play - Unit Vendor and Product ID (PNPUVEND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_PNPUVEND_VI_SHIFT 16 +#define GRSPWROUTER_PNPUVEND_VI_MASK 0xffff0000U +#define GRSPWROUTER_PNPUVEND_VI_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PNPUVEND_VI_MASK ) >> \ + GRSPWROUTER_PNPUVEND_VI_SHIFT ) +#define GRSPWROUTER_PNPUVEND_VI_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PNPUVEND_VI_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PNPUVEND_VI_SHIFT ) & \ + GRSPWROUTER_PNPUVEND_VI_MASK ) ) +#define GRSPWROUTER_PNPUVEND_VI( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PNPUVEND_VI_SHIFT ) & \ + GRSPWROUTER_PNPUVEND_VI_MASK ) + +#define GRSPWROUTER_PNPUVEND_PI_SHIFT 0 +#define GRSPWROUTER_PNPUVEND_PI_MASK 0x3ffffffU +#define GRSPWROUTER_PNPUVEND_PI_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PNPUVEND_PI_MASK ) >> \ + GRSPWROUTER_PNPUVEND_PI_SHIFT ) +#define GRSPWROUTER_PNPUVEND_PI_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PNPUVEND_PI_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PNPUVEND_PI_SHIFT ) & \ + GRSPWROUTER_PNPUVEND_PI_MASK ) ) +#define GRSPWROUTER_PNPUVEND_PI( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PNPUVEND_PI_SHIFT ) & \ + GRSPWROUTER_PNPUVEND_PI_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERPNPUSN \ + * SpaceWire Plug-and-Play - Unit Serial Number (PNPUSN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_PNPUSN_SN_SHIFT 0 +#define GRSPWROUTER_PNPUSN_SN_MASK 0xffffffffU +#define GRSPWROUTER_PNPUSN_SN_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PNPUSN_SN_MASK ) >> \ + GRSPWROUTER_PNPUSN_SN_SHIFT ) +#define GRSPWROUTER_PNPUSN_SN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PNPUSN_SN_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PNPUSN_SN_SHIFT ) & \ + GRSPWROUTER_PNPUSN_SN_MASK ) ) +#define GRSPWROUTER_PNPUSN_SN( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PNPUSN_SN_SHIFT ) & \ + GRSPWROUTER_PNPUSN_SN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERPNPNETDISC \ + * SpaceWire Plug-and-Play - Port network discovery enable (PNPNETDISC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_PNPNETDISC_ND_SHIFT 0 +#define GRSPWROUTER_PNPNETDISC_ND_MASK 0xffffffffU +#define GRSPWROUTER_PNPNETDISC_ND_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_PNPNETDISC_ND_MASK ) >> \ + GRSPWROUTER_PNPNETDISC_ND_SHIFT ) +#define GRSPWROUTER_PNPNETDISC_ND_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_PNPNETDISC_ND_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_PNPNETDISC_ND_SHIFT ) & \ + GRSPWROUTER_PNPNETDISC_ND_MASK ) ) +#define GRSPWROUTER_PNPNETDISC_ND( _val ) \ + ( ( ( _val ) << GRSPWROUTER_PNPNETDISC_ND_SHIFT ) & \ + GRSPWROUTER_PNPNETDISC_ND_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERMAXPLEN \ + * Maximum packet length, ports > 0 (MAXPLEN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_MAXPLEN_ML_SHIFT 0 +#define GRSPWROUTER_MAXPLEN_ML_MASK 0x1ffffffU +#define GRSPWROUTER_MAXPLEN_ML_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_MAXPLEN_ML_MASK ) >> \ + GRSPWROUTER_MAXPLEN_ML_SHIFT ) +#define GRSPWROUTER_MAXPLEN_ML_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_MAXPLEN_ML_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_MAXPLEN_ML_SHIFT ) & \ + GRSPWROUTER_MAXPLEN_ML_MASK ) ) +#define GRSPWROUTER_MAXPLEN_ML( _val ) \ + ( ( ( _val ) << GRSPWROUTER_MAXPLEN_ML_SHIFT ) & \ + GRSPWROUTER_MAXPLEN_ML_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERCREDCNT \ + * Credit counter, SpaceWire ports (CREDCNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_CREDCNT_OC_SHIFT 6 +#define GRSPWROUTER_CREDCNT_OC_MASK 0xfc0U +#define GRSPWROUTER_CREDCNT_OC_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_CREDCNT_OC_MASK ) >> \ + GRSPWROUTER_CREDCNT_OC_SHIFT ) +#define GRSPWROUTER_CREDCNT_OC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_CREDCNT_OC_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_CREDCNT_OC_SHIFT ) & \ + GRSPWROUTER_CREDCNT_OC_MASK ) ) +#define GRSPWROUTER_CREDCNT_OC( _val ) \ + ( ( ( _val ) << GRSPWROUTER_CREDCNT_OC_SHIFT ) & \ + GRSPWROUTER_CREDCNT_OC_MASK ) + +#define GRSPWROUTER_CREDCNT_IC_SHIFT 0 +#define GRSPWROUTER_CREDCNT_IC_MASK 0x3fU +#define GRSPWROUTER_CREDCNT_IC_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_CREDCNT_IC_MASK ) >> \ + GRSPWROUTER_CREDCNT_IC_SHIFT ) +#define GRSPWROUTER_CREDCNT_IC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_CREDCNT_IC_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_CREDCNT_IC_SHIFT ) & \ + GRSPWROUTER_CREDCNT_IC_MASK ) ) +#define GRSPWROUTER_CREDCNT_IC( _val ) \ + ( ( ( _val ) << GRSPWROUTER_CREDCNT_IC_SHIFT ) & \ + GRSPWROUTER_CREDCNT_IC_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERGPO \ + * General purpose out, bits 0-31, 32-63, 64-95, and 96-127 (GPO) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_GPO_GPO_SHIFT 0 +#define GRSPWROUTER_GPO_GPO_MASK 0xffffffffU +#define GRSPWROUTER_GPO_GPO_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_GPO_GPO_MASK ) >> \ + GRSPWROUTER_GPO_GPO_SHIFT ) +#define GRSPWROUTER_GPO_GPO_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_GPO_GPO_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_GPO_GPO_SHIFT ) & \ + GRSPWROUTER_GPO_GPO_MASK ) ) +#define GRSPWROUTER_GPO_GPO( _val ) \ + ( ( ( _val ) << GRSPWROUTER_GPO_GPO_SHIFT ) & \ + GRSPWROUTER_GPO_GPO_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERGPI \ + * General purpose in, bits 0-31, 32-63, 64-95, and 96-127 (GPI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_GPI_GPI_SHIFT 0 +#define GRSPWROUTER_GPI_GPI_MASK 0xffffffffU +#define GRSPWROUTER_GPI_GPI_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_GPI_GPI_MASK ) >> \ + GRSPWROUTER_GPI_GPI_SHIFT ) +#define GRSPWROUTER_GPI_GPI_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_GPI_GPI_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_GPI_GPI_SHIFT ) & \ + GRSPWROUTER_GPI_GPI_MASK ) ) +#define GRSPWROUTER_GPI_GPI( _val ) \ + ( ( ( _val ) << GRSPWROUTER_GPI_GPI_SHIFT ) & \ + GRSPWROUTER_GPI_GPI_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERRTCOMB \ + * Routing table, combined port mapping and address control, addresses 1-255 (RTCOMB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_RTCOMB_SR 0x80000000U + +#define GRSPWROUTER_RTCOMB_EN 0x40000000U + +#define GRSPWROUTER_RTCOMB_PR 0x20000000U + +#define GRSPWROUTER_RTCOMB_HD 0x10000000U + +#define GRSPWROUTER_RTCOMB_PE_SHIFT 1 +#define GRSPWROUTER_RTCOMB_PE_MASK 0xffffffeU +#define GRSPWROUTER_RTCOMB_PE_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_RTCOMB_PE_MASK ) >> \ + GRSPWROUTER_RTCOMB_PE_SHIFT ) +#define GRSPWROUTER_RTCOMB_PE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_RTCOMB_PE_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_RTCOMB_PE_SHIFT ) & \ + GRSPWROUTER_RTCOMB_PE_MASK ) ) +#define GRSPWROUTER_RTCOMB_PE( _val ) \ + ( ( ( _val ) << GRSPWROUTER_RTCOMB_PE_SHIFT ) & \ + GRSPWROUTER_RTCOMB_PE_MASK ) + +#define GRSPWROUTER_RTCOMB_PD 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAPBAREA APB address area (APBAREA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_APBAREA_APB_SHIFT 0 +#define GRSPWROUTER_APBAREA_APB_MASK 0xffffffffU +#define GRSPWROUTER_APBAREA_APB_GET( _reg ) \ + ( ( ( _reg ) & GRSPWROUTER_APBAREA_APB_MASK ) >> \ + GRSPWROUTER_APBAREA_APB_SHIFT ) +#define GRSPWROUTER_APBAREA_APB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GRSPWROUTER_APBAREA_APB_MASK ) | \ + ( ( ( _val ) << GRSPWROUTER_APBAREA_APB_SHIFT ) & \ + GRSPWROUTER_APBAREA_APB_MASK ) ) +#define GRSPWROUTER_APBAREA_APB( _val ) \ + ( ( ( _val ) << GRSPWROUTER_APBAREA_APB_SHIFT ) & \ + GRSPWROUTER_APBAREA_APB_MASK ) + +/** @} */ + +/** + * @brief This structure defines the SpaceWire Router register block memory + * map. + */ +typedef struct grspwrouter { + uint32_t reserved_0_4; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERRTPMAP. + */ + uint32_t rtpmap[ 255 ]; + + uint32_t reserved_400_404; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERRTACTRL. + */ + uint32_t rtactrl[ 255 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERPCTRLCFG. + */ + uint32_t pctrlcfg; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERPCTRL. + */ + uint32_t pctrl[ 31 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERPSTSCFG. + */ + uint32_t pstscfg; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERPSTS. + */ + uint32_t psts[ 31 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERPTIMER. + */ + uint32_t ptimer[ 32 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERPCTRL2CFG. + */ + uint32_t pctrl2cfg; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERPCTRL2. + */ + uint32_t pctrl2[ 31 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERRTRCFG. + */ + uint32_t rtrcfg; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERTC. + */ + uint32_t tc; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERVER. + */ + uint32_t ver; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERIDIV. + */ + uint32_t idiv; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERCFGWE. + */ + uint32_t cfgwe; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERPRESCALER. + */ + uint32_t prescaler; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERIMASK. + */ + uint32_t imask; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERIPMASK. + */ + uint32_t ipmask; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERPIP. + */ + uint32_t pip; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERICODEGEN. + */ + uint32_t icodegen; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERISR0. + */ + uint32_t isr0; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERISR1. + */ + uint32_t isr1; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERISRTIMER. + */ + uint32_t isrtimer; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAITIMER. + */ + uint32_t aitimer; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERISRCTIMER. + */ + uint32_t isrctimer; + + uint32_t reserved_a3c_a40; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERLRUNSTAT. + */ + uint32_t lrunstat; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERCAP. + */ + uint32_t cap; + + uint32_t reserved_a48_a50[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERPNPVEND. + */ + uint32_t pnpvend; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERPNPUVEND. + */ + uint32_t pnpuvend; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERPNPUSN. + */ + uint32_t pnpusn; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERPNPNETDISC. + */ + uint32_t pnpnetdisc; + + uint32_t reserved_a60_c10[ 108 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWRouterPortStats. + */ + grspwrouter_portstats portstats[ 31 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERMAXPLEN. + */ + uint32_t maxplen[ 32 ]; + + uint32_t reserved_e80_e84; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERCREDCNT. + */ + uint32_t credcnt[ 31 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERGPO. + */ + uint32_t gpo[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERGPI. + */ + uint32_t gpi[ 4 ]; + + uint32_t reserved_f20_1004[ 57 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERRTCOMB. + */ + uint32_t rtcomb[ 255 ]; + + uint32_t reserved_1400_2000[ 768 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAPBAREA. + */ + uint32_t apbarea[ 1024 ]; +} grspwrouter; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRSPWROUTER_REGS_H */ diff --git a/bsps/include/grlib/grtc.h b/bsps/include/grlib/grtc.h index 3ee1fa547c..17ad165e9b 100644 --- a/bsps/include/grlib/grtc.h +++ b/bsps/include/grlib/grtc.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GRTC Telecommand (TC) decoder driver interface * * COPYRIGHT (c) 2007. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRTC_H__ diff --git a/bsps/include/grlib/grtm.h b/bsps/include/grlib/grtm.h index 625f8389b7..8e667faa97 100644 --- a/bsps/include/grlib/grtm.h +++ b/bsps/include/grlib/grtm.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GRTM Telemetry (TM) driver interface * * COPYRIGHT (c) 2007. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GRTM_H__ diff --git a/bsps/include/grlib/i2cmst.h b/bsps/include/grlib/i2cmst.h index 01dbcf5bfb..a37583ec04 100644 --- a/bsps/include/grlib/i2cmst.h +++ b/bsps/include/grlib/i2cmst.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup i2c @@ -7,9 +9,26 @@ * COPYRIGHT (c) 2007 Cobham Gaisler AB * with parts from the RTEMS MPC83xx I2C driver (c) 2007 Embedded Brains GmbH. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _I2CMST_H diff --git a/bsps/include/grlib/irqamp-regs.h b/bsps/include/grlib/irqamp-regs.h new file mode 100644 index 0000000000..ee7b8ce9cf --- /dev/null +++ b/bsps/include/grlib/irqamp-regs.h @@ -0,0 +1,874 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBIRQAMP + * + * @brief This header file defines the IRQAMP register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/irqamp-header */ + +#ifndef _GRLIB_IRQAMP_REGS_H +#define _GRLIB_IRQAMP_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/irqamp-timestamp */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPTimestamp IRQ(A)MP Timestamp + * + * @ingroup RTEMSDeviceGRLIBIRQAMP + * + * @brief This group contains the IRQ(A)MP Timestamp interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPTimestampITCNT \ + * Interrupt timestamp counter n register (ITCNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ITCNT_TCNT_SHIFT 0 +#define IRQAMP_ITCNT_TCNT_MASK 0xffffffffU +#define IRQAMP_ITCNT_TCNT_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ITCNT_TCNT_MASK ) >> \ + IRQAMP_ITCNT_TCNT_SHIFT ) +#define IRQAMP_ITCNT_TCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ITCNT_TCNT_MASK ) | \ + ( ( ( _val ) << IRQAMP_ITCNT_TCNT_SHIFT ) & \ + IRQAMP_ITCNT_TCNT_MASK ) ) +#define IRQAMP_ITCNT_TCNT( _val ) \ + ( ( ( _val ) << IRQAMP_ITCNT_TCNT_SHIFT ) & \ + IRQAMP_ITCNT_TCNT_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPTimestampITSTMPC \ + * Interrupt timestamp n control register (ITSTMPC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ITSTMPC_TSTAMP_SHIFT 27 +#define IRQAMP_ITSTMPC_TSTAMP_MASK 0xf8000000U +#define IRQAMP_ITSTMPC_TSTAMP_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ITSTMPC_TSTAMP_MASK ) >> \ + IRQAMP_ITSTMPC_TSTAMP_SHIFT ) +#define IRQAMP_ITSTMPC_TSTAMP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ITSTMPC_TSTAMP_MASK ) | \ + ( ( ( _val ) << IRQAMP_ITSTMPC_TSTAMP_SHIFT ) & \ + IRQAMP_ITSTMPC_TSTAMP_MASK ) ) +#define IRQAMP_ITSTMPC_TSTAMP( _val ) \ + ( ( ( _val ) << IRQAMP_ITSTMPC_TSTAMP_SHIFT ) & \ + IRQAMP_ITSTMPC_TSTAMP_MASK ) + +#define IRQAMP_ITSTMPC_S1 0x4000000U + +#define IRQAMP_ITSTMPC_S2 0x2000000U + +#define IRQAMP_ITSTMPC_KS 0x20U + +#define IRQAMP_ITSTMPC_TSISEL_SHIFT 0 +#define IRQAMP_ITSTMPC_TSISEL_MASK 0x1fU +#define IRQAMP_ITSTMPC_TSISEL_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ITSTMPC_TSISEL_MASK ) >> \ + IRQAMP_ITSTMPC_TSISEL_SHIFT ) +#define IRQAMP_ITSTMPC_TSISEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ITSTMPC_TSISEL_MASK ) | \ + ( ( ( _val ) << IRQAMP_ITSTMPC_TSISEL_SHIFT ) & \ + IRQAMP_ITSTMPC_TSISEL_MASK ) ) +#define IRQAMP_ITSTMPC_TSISEL( _val ) \ + ( ( ( _val ) << IRQAMP_ITSTMPC_TSISEL_SHIFT ) & \ + IRQAMP_ITSTMPC_TSISEL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPTimestampITSTMPAS \ + * Interrupt Assertion Timestamp n register (ITSTMPAS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ITSTMPAS_TASSERTION_SHIFT 0 +#define IRQAMP_ITSTMPAS_TASSERTION_MASK 0xffffffffU +#define IRQAMP_ITSTMPAS_TASSERTION_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ITSTMPAS_TASSERTION_MASK ) >> \ + IRQAMP_ITSTMPAS_TASSERTION_SHIFT ) +#define IRQAMP_ITSTMPAS_TASSERTION_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ITSTMPAS_TASSERTION_MASK ) | \ + ( ( ( _val ) << IRQAMP_ITSTMPAS_TASSERTION_SHIFT ) & \ + IRQAMP_ITSTMPAS_TASSERTION_MASK ) ) +#define IRQAMP_ITSTMPAS_TASSERTION( _val ) \ + ( ( ( _val ) << IRQAMP_ITSTMPAS_TASSERTION_SHIFT ) & \ + IRQAMP_ITSTMPAS_TASSERTION_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPTimestampITSTMPAC \ + * Interrupt Acknowledge Timestamp n register (ITSTMPAC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT 0 +#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK 0xffffffffU +#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) >> \ + IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT ) +#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) | \ + ( ( ( _val ) << IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT ) & \ + IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) ) +#define IRQAMP_ITSTMPAC_TACKNOWLEDGE( _val ) \ + ( ( ( _val ) << IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT ) & \ + IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) + +/** @} */ + +/** + * @brief This structure defines the IRQ(A)MP Timestamp register block memory + * map. + */ +typedef struct irqamp_timestamp { + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestampITCNT. + */ + uint32_t itcnt; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestampITSTMPC. + */ + uint32_t itstmpc; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestampITSTMPAS. + */ + uint32_t itstmpas; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestampITSTMPAC. + */ + uint32_t itstmpac; +} irqamp_timestamp; + +/** @} */ + +/* Generated from spec:/dev/grlib/if/irqamp */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMP IRQ(A)MP + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the IRQ(A)MP interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPILEVEL Interrupt level register (ILEVEL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ILEVEL_IL_15_1_SHIFT 1 +#define IRQAMP_ILEVEL_IL_15_1_MASK 0xfffeU +#define IRQAMP_ILEVEL_IL_15_1_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ILEVEL_IL_15_1_MASK ) >> \ + IRQAMP_ILEVEL_IL_15_1_SHIFT ) +#define IRQAMP_ILEVEL_IL_15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ILEVEL_IL_15_1_MASK ) | \ + ( ( ( _val ) << IRQAMP_ILEVEL_IL_15_1_SHIFT ) & \ + IRQAMP_ILEVEL_IL_15_1_MASK ) ) +#define IRQAMP_ILEVEL_IL_15_1( _val ) \ + ( ( ( _val ) << IRQAMP_ILEVEL_IL_15_1_SHIFT ) & \ + IRQAMP_ILEVEL_IL_15_1_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPIPEND Interrupt pending register (IPEND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_IPEND_EIP_31_16_SHIFT 16 +#define IRQAMP_IPEND_EIP_31_16_MASK 0xffff0000U +#define IRQAMP_IPEND_EIP_31_16_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_IPEND_EIP_31_16_MASK ) >> \ + IRQAMP_IPEND_EIP_31_16_SHIFT ) +#define IRQAMP_IPEND_EIP_31_16_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IPEND_EIP_31_16_MASK ) | \ + ( ( ( _val ) << IRQAMP_IPEND_EIP_31_16_SHIFT ) & \ + IRQAMP_IPEND_EIP_31_16_MASK ) ) +#define IRQAMP_IPEND_EIP_31_16( _val ) \ + ( ( ( _val ) << IRQAMP_IPEND_EIP_31_16_SHIFT ) & \ + IRQAMP_IPEND_EIP_31_16_MASK ) + +#define IRQAMP_IPEND_IP_15_1_SHIFT 1 +#define IRQAMP_IPEND_IP_15_1_MASK 0xfffeU +#define IRQAMP_IPEND_IP_15_1_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_IPEND_IP_15_1_MASK ) >> \ + IRQAMP_IPEND_IP_15_1_SHIFT ) +#define IRQAMP_IPEND_IP_15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IPEND_IP_15_1_MASK ) | \ + ( ( ( _val ) << IRQAMP_IPEND_IP_15_1_SHIFT ) & \ + IRQAMP_IPEND_IP_15_1_MASK ) ) +#define IRQAMP_IPEND_IP_15_1( _val ) \ + ( ( ( _val ) << IRQAMP_IPEND_IP_15_1_SHIFT ) & \ + IRQAMP_IPEND_IP_15_1_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPIFORCE0 \ + * Interrupt force register for processor 0 (IFORCE0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_IFORCE0_IF_15_1_SHIFT 1 +#define IRQAMP_IFORCE0_IF_15_1_MASK 0xfffeU +#define IRQAMP_IFORCE0_IF_15_1_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_IFORCE0_IF_15_1_MASK ) >> \ + IRQAMP_IFORCE0_IF_15_1_SHIFT ) +#define IRQAMP_IFORCE0_IF_15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IFORCE0_IF_15_1_MASK ) | \ + ( ( ( _val ) << IRQAMP_IFORCE0_IF_15_1_SHIFT ) & \ + IRQAMP_IFORCE0_IF_15_1_MASK ) ) +#define IRQAMP_IFORCE0_IF_15_1( _val ) \ + ( ( ( _val ) << IRQAMP_IFORCE0_IF_15_1_SHIFT ) & \ + IRQAMP_IFORCE0_IF_15_1_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPICLEAR Interrupt clear register (ICLEAR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ICLEAR_EIC_31_16_SHIFT 16 +#define IRQAMP_ICLEAR_EIC_31_16_MASK 0xffff0000U +#define IRQAMP_ICLEAR_EIC_31_16_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ICLEAR_EIC_31_16_MASK ) >> \ + IRQAMP_ICLEAR_EIC_31_16_SHIFT ) +#define IRQAMP_ICLEAR_EIC_31_16_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ICLEAR_EIC_31_16_MASK ) | \ + ( ( ( _val ) << IRQAMP_ICLEAR_EIC_31_16_SHIFT ) & \ + IRQAMP_ICLEAR_EIC_31_16_MASK ) ) +#define IRQAMP_ICLEAR_EIC_31_16( _val ) \ + ( ( ( _val ) << IRQAMP_ICLEAR_EIC_31_16_SHIFT ) & \ + IRQAMP_ICLEAR_EIC_31_16_MASK ) + +#define IRQAMP_ICLEAR_IC_15_1_SHIFT 1 +#define IRQAMP_ICLEAR_IC_15_1_MASK 0xfffeU +#define IRQAMP_ICLEAR_IC_15_1_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ICLEAR_IC_15_1_MASK ) >> \ + IRQAMP_ICLEAR_IC_15_1_SHIFT ) +#define IRQAMP_ICLEAR_IC_15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ICLEAR_IC_15_1_MASK ) | \ + ( ( ( _val ) << IRQAMP_ICLEAR_IC_15_1_SHIFT ) & \ + IRQAMP_ICLEAR_IC_15_1_MASK ) ) +#define IRQAMP_ICLEAR_IC_15_1( _val ) \ + ( ( ( _val ) << IRQAMP_ICLEAR_IC_15_1_SHIFT ) & \ + IRQAMP_ICLEAR_IC_15_1_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPMPSTAT \ + * Multiprocessor status register (MPSTAT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_MPSTAT_NCPU_SHIFT 28 +#define IRQAMP_MPSTAT_NCPU_MASK 0xf0000000U +#define IRQAMP_MPSTAT_NCPU_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_MPSTAT_NCPU_MASK ) >> \ + IRQAMP_MPSTAT_NCPU_SHIFT ) +#define IRQAMP_MPSTAT_NCPU_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_MPSTAT_NCPU_MASK ) | \ + ( ( ( _val ) << IRQAMP_MPSTAT_NCPU_SHIFT ) & \ + IRQAMP_MPSTAT_NCPU_MASK ) ) +#define IRQAMP_MPSTAT_NCPU( _val ) \ + ( ( ( _val ) << IRQAMP_MPSTAT_NCPU_SHIFT ) & \ + IRQAMP_MPSTAT_NCPU_MASK ) + +#define IRQAMP_MPSTAT_BA 0x8000000U + +#define IRQAMP_MPSTAT_ER 0x4000000U + +#define IRQAMP_MPSTAT_EIRQ_SHIFT 16 +#define IRQAMP_MPSTAT_EIRQ_MASK 0xf0000U +#define IRQAMP_MPSTAT_EIRQ_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_MPSTAT_EIRQ_MASK ) >> \ + IRQAMP_MPSTAT_EIRQ_SHIFT ) +#define IRQAMP_MPSTAT_EIRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_MPSTAT_EIRQ_MASK ) | \ + ( ( ( _val ) << IRQAMP_MPSTAT_EIRQ_SHIFT ) & \ + IRQAMP_MPSTAT_EIRQ_MASK ) ) +#define IRQAMP_MPSTAT_EIRQ( _val ) \ + ( ( ( _val ) << IRQAMP_MPSTAT_EIRQ_SHIFT ) & \ + IRQAMP_MPSTAT_EIRQ_MASK ) + +#define IRQAMP_MPSTAT_STATUS_SHIFT 0 +#define IRQAMP_MPSTAT_STATUS_MASK 0xfU +#define IRQAMP_MPSTAT_STATUS_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_MPSTAT_STATUS_MASK ) >> \ + IRQAMP_MPSTAT_STATUS_SHIFT ) +#define IRQAMP_MPSTAT_STATUS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_MPSTAT_STATUS_MASK ) | \ + ( ( ( _val ) << IRQAMP_MPSTAT_STATUS_SHIFT ) & \ + IRQAMP_MPSTAT_STATUS_MASK ) ) +#define IRQAMP_MPSTAT_STATUS( _val ) \ + ( ( ( _val ) << IRQAMP_MPSTAT_STATUS_SHIFT ) & \ + IRQAMP_MPSTAT_STATUS_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPBRDCST Broadcast register (BRDCST) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_BRDCST_BM15_1_SHIFT 1 +#define IRQAMP_BRDCST_BM15_1_MASK 0xfffeU +#define IRQAMP_BRDCST_BM15_1_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_BRDCST_BM15_1_MASK ) >> \ + IRQAMP_BRDCST_BM15_1_SHIFT ) +#define IRQAMP_BRDCST_BM15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_BRDCST_BM15_1_MASK ) | \ + ( ( ( _val ) << IRQAMP_BRDCST_BM15_1_SHIFT ) & \ + IRQAMP_BRDCST_BM15_1_MASK ) ) +#define IRQAMP_BRDCST_BM15_1( _val ) \ + ( ( ( _val ) << IRQAMP_BRDCST_BM15_1_SHIFT ) & \ + IRQAMP_BRDCST_BM15_1_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPERRSTAT Error Mode Status Register (ERRSTAT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT 0 +#define IRQAMP_ERRSTAT_ERRMODE_3_0_MASK 0xfU +#define IRQAMP_ERRSTAT_ERRMODE_3_0_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) >> \ + IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT ) +#define IRQAMP_ERRSTAT_ERRMODE_3_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) | \ + ( ( ( _val ) << IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT ) & \ + IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) ) +#define IRQAMP_ERRSTAT_ERRMODE_3_0( _val ) \ + ( ( ( _val ) << IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT ) & \ + IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPWDOGCTRL \ + * Watchdog control register (WDOGCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_WDOGCTRL_NWDOG_SHIFT 27 +#define IRQAMP_WDOGCTRL_NWDOG_MASK 0xf8000000U +#define IRQAMP_WDOGCTRL_NWDOG_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_WDOGCTRL_NWDOG_MASK ) >> \ + IRQAMP_WDOGCTRL_NWDOG_SHIFT ) +#define IRQAMP_WDOGCTRL_NWDOG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_NWDOG_MASK ) | \ + ( ( ( _val ) << IRQAMP_WDOGCTRL_NWDOG_SHIFT ) & \ + IRQAMP_WDOGCTRL_NWDOG_MASK ) ) +#define IRQAMP_WDOGCTRL_NWDOG( _val ) \ + ( ( ( _val ) << IRQAMP_WDOGCTRL_NWDOG_SHIFT ) & \ + IRQAMP_WDOGCTRL_NWDOG_MASK ) + +#define IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT 16 +#define IRQAMP_WDOGCTRL_WDOGIRQ_MASK 0xf0000U +#define IRQAMP_WDOGCTRL_WDOGIRQ_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) >> \ + IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT ) +#define IRQAMP_WDOGCTRL_WDOGIRQ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) | \ + ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT ) & \ + IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) ) +#define IRQAMP_WDOGCTRL_WDOGIRQ( _val ) \ + ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT ) & \ + IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) + +#define IRQAMP_WDOGCTRL_WDOGMSK_SHIFT 0 +#define IRQAMP_WDOGCTRL_WDOGMSK_MASK 0xfU +#define IRQAMP_WDOGCTRL_WDOGMSK_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_WDOGCTRL_WDOGMSK_MASK ) >> \ + IRQAMP_WDOGCTRL_WDOGMSK_SHIFT ) +#define IRQAMP_WDOGCTRL_WDOGMSK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_WDOGMSK_MASK ) | \ + ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGMSK_SHIFT ) & \ + IRQAMP_WDOGCTRL_WDOGMSK_MASK ) ) +#define IRQAMP_WDOGCTRL_WDOGMSK( _val ) \ + ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGMSK_SHIFT ) & \ + IRQAMP_WDOGCTRL_WDOGMSK_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPASMPCTRL \ + * Asymmetric multiprocessing control register (ASMPCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ASMPCTRL_NCTRL_SHIFT 28 +#define IRQAMP_ASMPCTRL_NCTRL_MASK 0xf0000000U +#define IRQAMP_ASMPCTRL_NCTRL_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ASMPCTRL_NCTRL_MASK ) >> \ + IRQAMP_ASMPCTRL_NCTRL_SHIFT ) +#define IRQAMP_ASMPCTRL_NCTRL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ASMPCTRL_NCTRL_MASK ) | \ + ( ( ( _val ) << IRQAMP_ASMPCTRL_NCTRL_SHIFT ) & \ + IRQAMP_ASMPCTRL_NCTRL_MASK ) ) +#define IRQAMP_ASMPCTRL_NCTRL( _val ) \ + ( ( ( _val ) << IRQAMP_ASMPCTRL_NCTRL_SHIFT ) & \ + IRQAMP_ASMPCTRL_NCTRL_MASK ) + +#define IRQAMP_ASMPCTRL_ICF 0x2U + +#define IRQAMP_ASMPCTRL_L 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPICSELR \ + * Interrupt controller select register (ICSELR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ICSELR_ICSEL0_SHIFT 28 +#define IRQAMP_ICSELR_ICSEL0_MASK 0xf0000000U +#define IRQAMP_ICSELR_ICSEL0_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL0_MASK ) >> \ + IRQAMP_ICSELR_ICSEL0_SHIFT ) +#define IRQAMP_ICSELR_ICSEL0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL0_MASK ) | \ + ( ( ( _val ) << IRQAMP_ICSELR_ICSEL0_SHIFT ) & \ + IRQAMP_ICSELR_ICSEL0_MASK ) ) +#define IRQAMP_ICSELR_ICSEL0( _val ) \ + ( ( ( _val ) << IRQAMP_ICSELR_ICSEL0_SHIFT ) & \ + IRQAMP_ICSELR_ICSEL0_MASK ) + +#define IRQAMP_ICSELR_ICSEL1_SHIFT 24 +#define IRQAMP_ICSELR_ICSEL1_MASK 0xf000000U +#define IRQAMP_ICSELR_ICSEL1_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL1_MASK ) >> \ + IRQAMP_ICSELR_ICSEL1_SHIFT ) +#define IRQAMP_ICSELR_ICSEL1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL1_MASK ) | \ + ( ( ( _val ) << IRQAMP_ICSELR_ICSEL1_SHIFT ) & \ + IRQAMP_ICSELR_ICSEL1_MASK ) ) +#define IRQAMP_ICSELR_ICSEL1( _val ) \ + ( ( ( _val ) << IRQAMP_ICSELR_ICSEL1_SHIFT ) & \ + IRQAMP_ICSELR_ICSEL1_MASK ) + +#define IRQAMP_ICSELR_ICSEL2_SHIFT 20 +#define IRQAMP_ICSELR_ICSEL2_MASK 0xf00000U +#define IRQAMP_ICSELR_ICSEL2_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL2_MASK ) >> \ + IRQAMP_ICSELR_ICSEL2_SHIFT ) +#define IRQAMP_ICSELR_ICSEL2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL2_MASK ) | \ + ( ( ( _val ) << IRQAMP_ICSELR_ICSEL2_SHIFT ) & \ + IRQAMP_ICSELR_ICSEL2_MASK ) ) +#define IRQAMP_ICSELR_ICSEL2( _val ) \ + ( ( ( _val ) << IRQAMP_ICSELR_ICSEL2_SHIFT ) & \ + IRQAMP_ICSELR_ICSEL2_MASK ) + +#define IRQAMP_ICSELR_ICSEL3_SHIFT 16 +#define IRQAMP_ICSELR_ICSEL3_MASK 0xf0000U +#define IRQAMP_ICSELR_ICSEL3_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL3_MASK ) >> \ + IRQAMP_ICSELR_ICSEL3_SHIFT ) +#define IRQAMP_ICSELR_ICSEL3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL3_MASK ) | \ + ( ( ( _val ) << IRQAMP_ICSELR_ICSEL3_SHIFT ) & \ + IRQAMP_ICSELR_ICSEL3_MASK ) ) +#define IRQAMP_ICSELR_ICSEL3( _val ) \ + ( ( ( _val ) << IRQAMP_ICSELR_ICSEL3_SHIFT ) & \ + IRQAMP_ICSELR_ICSEL3_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPPIMASK \ + * Processor n interrupt mask register (PIMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_PIMASK_EIM_31_16_SHIFT 16 +#define IRQAMP_PIMASK_EIM_31_16_MASK 0xffff0000U +#define IRQAMP_PIMASK_EIM_31_16_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_PIMASK_EIM_31_16_MASK ) >> \ + IRQAMP_PIMASK_EIM_31_16_SHIFT ) +#define IRQAMP_PIMASK_EIM_31_16_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_PIMASK_EIM_31_16_MASK ) | \ + ( ( ( _val ) << IRQAMP_PIMASK_EIM_31_16_SHIFT ) & \ + IRQAMP_PIMASK_EIM_31_16_MASK ) ) +#define IRQAMP_PIMASK_EIM_31_16( _val ) \ + ( ( ( _val ) << IRQAMP_PIMASK_EIM_31_16_SHIFT ) & \ + IRQAMP_PIMASK_EIM_31_16_MASK ) + +#define IRQAMP_PIMASK_IM15_1_SHIFT 1 +#define IRQAMP_PIMASK_IM15_1_MASK 0xfffeU +#define IRQAMP_PIMASK_IM15_1_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_PIMASK_IM15_1_MASK ) >> \ + IRQAMP_PIMASK_IM15_1_SHIFT ) +#define IRQAMP_PIMASK_IM15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_PIMASK_IM15_1_MASK ) | \ + ( ( ( _val ) << IRQAMP_PIMASK_IM15_1_SHIFT ) & \ + IRQAMP_PIMASK_IM15_1_MASK ) ) +#define IRQAMP_PIMASK_IM15_1( _val ) \ + ( ( ( _val ) << IRQAMP_PIMASK_IM15_1_SHIFT ) & \ + IRQAMP_PIMASK_IM15_1_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPPIFORCE \ + * Processor n interrupt force register (PIFORCE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_PIFORCE_FC_15_1_SHIFT 17 +#define IRQAMP_PIFORCE_FC_15_1_MASK 0xfffe0000U +#define IRQAMP_PIFORCE_FC_15_1_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_PIFORCE_FC_15_1_MASK ) >> \ + IRQAMP_PIFORCE_FC_15_1_SHIFT ) +#define IRQAMP_PIFORCE_FC_15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_PIFORCE_FC_15_1_MASK ) | \ + ( ( ( _val ) << IRQAMP_PIFORCE_FC_15_1_SHIFT ) & \ + IRQAMP_PIFORCE_FC_15_1_MASK ) ) +#define IRQAMP_PIFORCE_FC_15_1( _val ) \ + ( ( ( _val ) << IRQAMP_PIFORCE_FC_15_1_SHIFT ) & \ + IRQAMP_PIFORCE_FC_15_1_MASK ) + +#define IRQAMP_PIFORCE_IF15_1_SHIFT 1 +#define IRQAMP_PIFORCE_IF15_1_MASK 0xfffeU +#define IRQAMP_PIFORCE_IF15_1_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_PIFORCE_IF15_1_MASK ) >> \ + IRQAMP_PIFORCE_IF15_1_SHIFT ) +#define IRQAMP_PIFORCE_IF15_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_PIFORCE_IF15_1_MASK ) | \ + ( ( ( _val ) << IRQAMP_PIFORCE_IF15_1_SHIFT ) & \ + IRQAMP_PIFORCE_IF15_1_MASK ) ) +#define IRQAMP_PIFORCE_IF15_1( _val ) \ + ( ( ( _val ) << IRQAMP_PIFORCE_IF15_1_SHIFT ) & \ + IRQAMP_PIFORCE_IF15_1_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPPEXTACK \ + * Processor n extended interrupt acknowledge register (PEXTACK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_PEXTACK_EID_4_0_SHIFT 0 +#define IRQAMP_PEXTACK_EID_4_0_MASK 0x1fU +#define IRQAMP_PEXTACK_EID_4_0_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_PEXTACK_EID_4_0_MASK ) >> \ + IRQAMP_PEXTACK_EID_4_0_SHIFT ) +#define IRQAMP_PEXTACK_EID_4_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_PEXTACK_EID_4_0_MASK ) | \ + ( ( ( _val ) << IRQAMP_PEXTACK_EID_4_0_SHIFT ) & \ + IRQAMP_PEXTACK_EID_4_0_MASK ) ) +#define IRQAMP_PEXTACK_EID_4_0( _val ) \ + ( ( ( _val ) << IRQAMP_PEXTACK_EID_4_0_SHIFT ) & \ + IRQAMP_PEXTACK_EID_4_0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPBADDR \ + * Processor n Boot Address register (BADDR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_BADDR_BOOTADDR_31_3_SHIFT 3 +#define IRQAMP_BADDR_BOOTADDR_31_3_MASK 0xfffffff8U +#define IRQAMP_BADDR_BOOTADDR_31_3_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_BADDR_BOOTADDR_31_3_MASK ) >> \ + IRQAMP_BADDR_BOOTADDR_31_3_SHIFT ) +#define IRQAMP_BADDR_BOOTADDR_31_3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_BADDR_BOOTADDR_31_3_MASK ) | \ + ( ( ( _val ) << IRQAMP_BADDR_BOOTADDR_31_3_SHIFT ) & \ + IRQAMP_BADDR_BOOTADDR_31_3_MASK ) ) +#define IRQAMP_BADDR_BOOTADDR_31_3( _val ) \ + ( ( ( _val ) << IRQAMP_BADDR_BOOTADDR_31_3_SHIFT ) & \ + IRQAMP_BADDR_BOOTADDR_31_3_MASK ) + +#define IRQAMP_BADDR_AS 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPIRQMAP Interrupt map register n (IRQMAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT 24 +#define IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK 0xff000000U +#define IRQAMP_IRQMAP_IRQMAP_4_N_0_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) >> \ + IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT ) +#define IRQAMP_IRQMAP_IRQMAP_4_N_0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) | \ + ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT ) & \ + IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) ) +#define IRQAMP_IRQMAP_IRQMAP_4_N_0( _val ) \ + ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT ) & \ + IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) + +#define IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT 16 +#define IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK 0xff0000U +#define IRQAMP_IRQMAP_IRQMAP_4_N_1_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) >> \ + IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT ) +#define IRQAMP_IRQMAP_IRQMAP_4_N_1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) | \ + ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT ) & \ + IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) ) +#define IRQAMP_IRQMAP_IRQMAP_4_N_1( _val ) \ + ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT ) & \ + IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) + +#define IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT 8 +#define IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK 0xff00U +#define IRQAMP_IRQMAP_IRQMAP_4_N_2_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) >> \ + IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT ) +#define IRQAMP_IRQMAP_IRQMAP_4_N_2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) | \ + ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT ) & \ + IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) ) +#define IRQAMP_IRQMAP_IRQMAP_4_N_2( _val ) \ + ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT ) & \ + IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) + +#define IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT 0 +#define IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK 0xffU +#define IRQAMP_IRQMAP_IRQMAP_4_N_3_GET( _reg ) \ + ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) >> \ + IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT ) +#define IRQAMP_IRQMAP_IRQMAP_4_N_3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) | \ + ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT ) & \ + IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) ) +#define IRQAMP_IRQMAP_IRQMAP_4_N_3( _val ) \ + ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT ) & \ + IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) + +/** @} */ + +/** + * @brief This structure defines the IRQ(A)MP register block memory map. + */ +typedef struct irqamp { + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPILEVEL. + */ + uint32_t ilevel; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPIPEND. + */ + uint32_t ipend; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPIFORCE0. + */ + uint32_t iforce0; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPICLEAR. + */ + uint32_t iclear; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPMPSTAT. + */ + uint32_t mpstat; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPBRDCST. + */ + uint32_t brdcst; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPERRSTAT. + */ + uint32_t errstat; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPWDOGCTRL. + */ + uint32_t wdogctrl; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPASMPCTRL. + */ + uint32_t asmpctrl; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPICSELR. + */ + uint32_t icselr[ 2 ]; + + uint32_t reserved_2c_40[ 5 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPPIMASK. + */ + uint32_t pimask[ 16 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPPIFORCE. + */ + uint32_t piforce[ 16 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPPEXTACK. + */ + uint32_t pextack[ 16 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestamp. + */ + irqamp_timestamp itstmp[ 16 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPBADDR. + */ + uint32_t baddr[ 16 ]; + + uint32_t reserved_240_300[ 48 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPIRQMAP. + */ + uint32_t irqmap[ 16 ]; + + uint32_t reserved_340_400[ 48 ]; +} irqamp; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_IRQAMP_REGS_H */ diff --git a/bsps/include/grlib/irqamp.h b/bsps/include/grlib/irqamp.h new file mode 100644 index 0000000000..dd7c5235f0 --- /dev/null +++ b/bsps/include/grlib/irqamp.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBIRQAMP + * + * @brief This header file defines the IRQ(A)MP interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/irqamp-header-2 */ + +#ifndef _GRLIB_IRQAMP_H +#define _GRLIB_IRQAMP_H + +#include <stddef.h> +#include <grlib/io.h> +#include <grlib/irqamp-regs.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/irqamp-get-timestamp */ + +/** + * @ingroup RTEMSDeviceGRLIBIRQAMP + * + * @brief Gets the interrupt timestamping register bock. + * + * @param irqamp_regs is the IRQ(A)MP register block. + * + * @retval NULL The IRQ(A)MP does not support the interrupt timestamping + * feature. + * + * @return Returns the interrupt timestamping register block. + */ +static inline irqamp_timestamp *irqamp_get_timestamp_registers( + irqamp *irqamp_regs +) +{ + irqamp_timestamp *timestamp_regs; + uint32_t itstmpc; + + timestamp_regs = &irqamp_regs->itstmp[ 0 ]; + itstmpc = grlib_load_32( ×tamp_regs->itstmpc ); + + if ( IRQAMP_ITSTMPC_TSTAMP_GET( itstmpc ) == 0 ) { + return NULL; + } + + return timestamp_regs; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_IRQAMP_H */ diff --git a/bsps/include/grlib/l2c.h b/bsps/include/grlib/l2c.h index 52473ddf2a..2867d5bca5 100644 --- a/bsps/include/grlib/l2c.h +++ b/bsps/include/grlib/l2c.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * GRLIB L2CACHE Driver * * COPYRIGHT (c) 2017 * Cobham Gaisler AB * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * * OVERVIEW * ======== diff --git a/bsps/include/grlib/l2cache-regs.h b/bsps/include/grlib/l2cache-regs.h new file mode 100644 index 0000000000..24d2e561b1 --- /dev/null +++ b/bsps/include/grlib/l2cache-regs.h @@ -0,0 +1,807 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBL2CACHE + * + * @brief This header file defines the L2CACHE register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/l2cache-header */ + +#ifndef _GRLIB_L2CACHE_REGS_H +#define _GRLIB_L2CACHE_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/l2cache */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHE L2CACHE + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the L2CACHE interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CC L2C Control register (L2CC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CC_EN 0x80000000U + +#define L2CACHE_L2CC_EDAC 0x40000000U + +#define L2CACHE_L2CC_REPL_SHIFT 28 +#define L2CACHE_L2CC_REPL_MASK 0x30000000U +#define L2CACHE_L2CC_REPL_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CC_REPL_MASK ) >> \ + L2CACHE_L2CC_REPL_SHIFT ) +#define L2CACHE_L2CC_REPL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CC_REPL_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CC_REPL_SHIFT ) & \ + L2CACHE_L2CC_REPL_MASK ) ) +#define L2CACHE_L2CC_REPL( _val ) \ + ( ( ( _val ) << L2CACHE_L2CC_REPL_SHIFT ) & \ + L2CACHE_L2CC_REPL_MASK ) + +#define L2CACHE_L2CC_BBS_SHIFT 16 +#define L2CACHE_L2CC_BBS_MASK 0x70000U +#define L2CACHE_L2CC_BBS_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CC_BBS_MASK ) >> \ + L2CACHE_L2CC_BBS_SHIFT ) +#define L2CACHE_L2CC_BBS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CC_BBS_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CC_BBS_SHIFT ) & \ + L2CACHE_L2CC_BBS_MASK ) ) +#define L2CACHE_L2CC_BBS( _val ) \ + ( ( ( _val ) << L2CACHE_L2CC_BBS_SHIFT ) & \ + L2CACHE_L2CC_BBS_MASK ) + +#define L2CACHE_L2CC_INDEX_WAY_SHIFT 12 +#define L2CACHE_L2CC_INDEX_WAY_MASK 0xf000U +#define L2CACHE_L2CC_INDEX_WAY_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CC_INDEX_WAY_MASK ) >> \ + L2CACHE_L2CC_INDEX_WAY_SHIFT ) +#define L2CACHE_L2CC_INDEX_WAY_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CC_INDEX_WAY_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CC_INDEX_WAY_SHIFT ) & \ + L2CACHE_L2CC_INDEX_WAY_MASK ) ) +#define L2CACHE_L2CC_INDEX_WAY( _val ) \ + ( ( ( _val ) << L2CACHE_L2CC_INDEX_WAY_SHIFT ) & \ + L2CACHE_L2CC_INDEX_WAY_MASK ) + +#define L2CACHE_L2CC_LOCK_SHIFT 8 +#define L2CACHE_L2CC_LOCK_MASK 0xf00U +#define L2CACHE_L2CC_LOCK_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CC_LOCK_MASK ) >> \ + L2CACHE_L2CC_LOCK_SHIFT ) +#define L2CACHE_L2CC_LOCK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CC_LOCK_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CC_LOCK_SHIFT ) & \ + L2CACHE_L2CC_LOCK_MASK ) ) +#define L2CACHE_L2CC_LOCK( _val ) \ + ( ( ( _val ) << L2CACHE_L2CC_LOCK_SHIFT ) & \ + L2CACHE_L2CC_LOCK_MASK ) + +#define L2CACHE_L2CC_HPRHB 0x20U + +#define L2CACHE_L2CC_HPB 0x10U + +#define L2CACHE_L2CC_UC 0x8U + +#define L2CACHE_L2CC_HC 0x4U + +#define L2CACHE_L2CC_WP 0x2U + +#define L2CACHE_L2CC_HP 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CS L2C Status register (L2CS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CS_LS 0x1000000U + +#define L2CACHE_L2CS_AT 0x800000U + +#define L2CACHE_L2CS_MP 0x400000U + +#define L2CACHE_L2CS_MTRR_SHIFT 16 +#define L2CACHE_L2CS_MTRR_MASK 0x3f0000U +#define L2CACHE_L2CS_MTRR_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CS_MTRR_MASK ) >> \ + L2CACHE_L2CS_MTRR_SHIFT ) +#define L2CACHE_L2CS_MTRR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CS_MTRR_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CS_MTRR_SHIFT ) & \ + L2CACHE_L2CS_MTRR_MASK ) ) +#define L2CACHE_L2CS_MTRR( _val ) \ + ( ( ( _val ) << L2CACHE_L2CS_MTRR_SHIFT ) & \ + L2CACHE_L2CS_MTRR_MASK ) + +#define L2CACHE_L2CS_BBUS_W_SHIFT 13 +#define L2CACHE_L2CS_BBUS_W_MASK 0xe000U +#define L2CACHE_L2CS_BBUS_W_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CS_BBUS_W_MASK ) >> \ + L2CACHE_L2CS_BBUS_W_SHIFT ) +#define L2CACHE_L2CS_BBUS_W_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CS_BBUS_W_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CS_BBUS_W_SHIFT ) & \ + L2CACHE_L2CS_BBUS_W_MASK ) ) +#define L2CACHE_L2CS_BBUS_W( _val ) \ + ( ( ( _val ) << L2CACHE_L2CS_BBUS_W_SHIFT ) & \ + L2CACHE_L2CS_BBUS_W_MASK ) + +#define L2CACHE_L2CS_WAY_SIZE_SHIFT 2 +#define L2CACHE_L2CS_WAY_SIZE_MASK 0x1ffcU +#define L2CACHE_L2CS_WAY_SIZE_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CS_WAY_SIZE_MASK ) >> \ + L2CACHE_L2CS_WAY_SIZE_SHIFT ) +#define L2CACHE_L2CS_WAY_SIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CS_WAY_SIZE_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CS_WAY_SIZE_SHIFT ) & \ + L2CACHE_L2CS_WAY_SIZE_MASK ) ) +#define L2CACHE_L2CS_WAY_SIZE( _val ) \ + ( ( ( _val ) << L2CACHE_L2CS_WAY_SIZE_SHIFT ) & \ + L2CACHE_L2CS_WAY_SIZE_MASK ) + +#define L2CACHE_L2CS_WAY_SHIFT 0 +#define L2CACHE_L2CS_WAY_MASK 0x3U +#define L2CACHE_L2CS_WAY_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CS_WAY_MASK ) >> \ + L2CACHE_L2CS_WAY_SHIFT ) +#define L2CACHE_L2CS_WAY_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CS_WAY_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CS_WAY_SHIFT ) & \ + L2CACHE_L2CS_WAY_MASK ) ) +#define L2CACHE_L2CS_WAY( _val ) \ + ( ( ( _val ) << L2CACHE_L2CS_WAY_SHIFT ) & \ + L2CACHE_L2CS_WAY_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CFMA \ + * L2C Flush (Memory address) register (L2CFMA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CFMA_ADDR_SHIFT 5 +#define L2CACHE_L2CFMA_ADDR_MASK 0xffffffe0U +#define L2CACHE_L2CFMA_ADDR_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CFMA_ADDR_MASK ) >> \ + L2CACHE_L2CFMA_ADDR_SHIFT ) +#define L2CACHE_L2CFMA_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CFMA_ADDR_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CFMA_ADDR_SHIFT ) & \ + L2CACHE_L2CFMA_ADDR_MASK ) ) +#define L2CACHE_L2CFMA_ADDR( _val ) \ + ( ( ( _val ) << L2CACHE_L2CFMA_ADDR_SHIFT ) & \ + L2CACHE_L2CFMA_ADDR_MASK ) + +#define L2CACHE_L2CFMA_DI 0x8U + +#define L2CACHE_L2CFMA_FMODE_SHIFT 0 +#define L2CACHE_L2CFMA_FMODE_MASK 0x7U +#define L2CACHE_L2CFMA_FMODE_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CFMA_FMODE_MASK ) >> \ + L2CACHE_L2CFMA_FMODE_SHIFT ) +#define L2CACHE_L2CFMA_FMODE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CFMA_FMODE_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CFMA_FMODE_SHIFT ) & \ + L2CACHE_L2CFMA_FMODE_MASK ) ) +#define L2CACHE_L2CFMA_FMODE( _val ) \ + ( ( ( _val ) << L2CACHE_L2CFMA_FMODE_SHIFT ) & \ + L2CACHE_L2CFMA_FMODE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CFSI \ + * L2C Flush (Set, Index) register (L2CFSI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CFSI_INDEX_SHIFT 16 +#define L2CACHE_L2CFSI_INDEX_MASK 0xffff0000U +#define L2CACHE_L2CFSI_INDEX_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CFSI_INDEX_MASK ) >> \ + L2CACHE_L2CFSI_INDEX_SHIFT ) +#define L2CACHE_L2CFSI_INDEX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CFSI_INDEX_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CFSI_INDEX_SHIFT ) & \ + L2CACHE_L2CFSI_INDEX_MASK ) ) +#define L2CACHE_L2CFSI_INDEX( _val ) \ + ( ( ( _val ) << L2CACHE_L2CFSI_INDEX_SHIFT ) & \ + L2CACHE_L2CFSI_INDEX_MASK ) + +#define L2CACHE_L2CFSI_TAG_SHIFT 10 +#define L2CACHE_L2CFSI_TAG_MASK 0xfffffc00U +#define L2CACHE_L2CFSI_TAG_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CFSI_TAG_MASK ) >> \ + L2CACHE_L2CFSI_TAG_SHIFT ) +#define L2CACHE_L2CFSI_TAG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CFSI_TAG_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CFSI_TAG_SHIFT ) & \ + L2CACHE_L2CFSI_TAG_MASK ) ) +#define L2CACHE_L2CFSI_TAG( _val ) \ + ( ( ( _val ) << L2CACHE_L2CFSI_TAG_SHIFT ) & \ + L2CACHE_L2CFSI_TAG_MASK ) + +#define L2CACHE_L2CFSI_FL 0x200U + +#define L2CACHE_L2CFSI_VB 0x100U + +#define L2CACHE_L2CFSI_DB 0x80U + +#define L2CACHE_L2CFSI_WAY_SHIFT 4 +#define L2CACHE_L2CFSI_WAY_MASK 0x30U +#define L2CACHE_L2CFSI_WAY_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CFSI_WAY_MASK ) >> \ + L2CACHE_L2CFSI_WAY_SHIFT ) +#define L2CACHE_L2CFSI_WAY_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CFSI_WAY_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CFSI_WAY_SHIFT ) & \ + L2CACHE_L2CFSI_WAY_MASK ) ) +#define L2CACHE_L2CFSI_WAY( _val ) \ + ( ( ( _val ) << L2CACHE_L2CFSI_WAY_SHIFT ) & \ + L2CACHE_L2CFSI_WAY_MASK ) + +#define L2CACHE_L2CFSI_DI 0x8U + +#define L2CACHE_L2CFSI_WF 0x4U + +#define L2CACHE_L2CFSI_FMODE_SHIFT 0 +#define L2CACHE_L2CFSI_FMODE_MASK 0x3U +#define L2CACHE_L2CFSI_FMODE_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CFSI_FMODE_MASK ) >> \ + L2CACHE_L2CFSI_FMODE_SHIFT ) +#define L2CACHE_L2CFSI_FMODE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CFSI_FMODE_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CFSI_FMODE_SHIFT ) & \ + L2CACHE_L2CFSI_FMODE_MASK ) ) +#define L2CACHE_L2CFSI_FMODE( _val ) \ + ( ( ( _val ) << L2CACHE_L2CFSI_FMODE_SHIFT ) & \ + L2CACHE_L2CFSI_FMODE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CERR \ + * L2CError status/control register (L2CERR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT 28 +#define L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK 0xf0000000U +#define L2CACHE_L2CERR_AHB_MASTER_INDEX_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) >> \ + L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT ) +#define L2CACHE_L2CERR_AHB_MASTER_INDEX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT ) & \ + L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) ) +#define L2CACHE_L2CERR_AHB_MASTER_INDEX( _val ) \ + ( ( ( _val ) << L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT ) & \ + L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK ) + +#define L2CACHE_L2CERR_SCRUB 0x8000000U + +#define L2CACHE_L2CERR_TYPE_SHIFT 24 +#define L2CACHE_L2CERR_TYPE_MASK 0x7000000U +#define L2CACHE_L2CERR_TYPE_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CERR_TYPE_MASK ) >> \ + L2CACHE_L2CERR_TYPE_SHIFT ) +#define L2CACHE_L2CERR_TYPE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_TYPE_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CERR_TYPE_SHIFT ) & \ + L2CACHE_L2CERR_TYPE_MASK ) ) +#define L2CACHE_L2CERR_TYPE( _val ) \ + ( ( ( _val ) << L2CACHE_L2CERR_TYPE_SHIFT ) & \ + L2CACHE_L2CERR_TYPE_MASK ) + +#define L2CACHE_L2CERR_TAG_DATA 0x800000U + +#define L2CACHE_L2CERR_COR_UCOR 0x400000U + +#define L2CACHE_L2CERR_MULTI 0x200000U + +#define L2CACHE_L2CERR_VALID 0x100000U + +#define L2CACHE_L2CERR_DISERESP 0x80000U + +#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT 16 +#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK 0x70000U +#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) >> \ + L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT ) +#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT ) & \ + L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) ) +#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER( _val ) \ + ( ( ( _val ) << L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT ) & \ + L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK ) + +#define L2CACHE_L2CERR_IRQ_PENDING_SHIFT 12 +#define L2CACHE_L2CERR_IRQ_PENDING_MASK 0xf000U +#define L2CACHE_L2CERR_IRQ_PENDING_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CERR_IRQ_PENDING_MASK ) >> \ + L2CACHE_L2CERR_IRQ_PENDING_SHIFT ) +#define L2CACHE_L2CERR_IRQ_PENDING_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_IRQ_PENDING_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CERR_IRQ_PENDING_SHIFT ) & \ + L2CACHE_L2CERR_IRQ_PENDING_MASK ) ) +#define L2CACHE_L2CERR_IRQ_PENDING( _val ) \ + ( ( ( _val ) << L2CACHE_L2CERR_IRQ_PENDING_SHIFT ) & \ + L2CACHE_L2CERR_IRQ_PENDING_MASK ) + +#define L2CACHE_L2CERR_IRQ_MASK_SHIFT 8 +#define L2CACHE_L2CERR_IRQ_MASK_MASK 0xf00U +#define L2CACHE_L2CERR_IRQ_MASK_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CERR_IRQ_MASK_MASK ) >> \ + L2CACHE_L2CERR_IRQ_MASK_SHIFT ) +#define L2CACHE_L2CERR_IRQ_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_IRQ_MASK_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CERR_IRQ_MASK_SHIFT ) & \ + L2CACHE_L2CERR_IRQ_MASK_MASK ) ) +#define L2CACHE_L2CERR_IRQ_MASK( _val ) \ + ( ( ( _val ) << L2CACHE_L2CERR_IRQ_MASK_SHIFT ) & \ + L2CACHE_L2CERR_IRQ_MASK_MASK ) + +#define L2CACHE_L2CERR_SELECT_CB_SHIFT 6 +#define L2CACHE_L2CERR_SELECT_CB_MASK 0xc0U +#define L2CACHE_L2CERR_SELECT_CB_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CERR_SELECT_CB_MASK ) >> \ + L2CACHE_L2CERR_SELECT_CB_SHIFT ) +#define L2CACHE_L2CERR_SELECT_CB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_SELECT_CB_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CERR_SELECT_CB_SHIFT ) & \ + L2CACHE_L2CERR_SELECT_CB_MASK ) ) +#define L2CACHE_L2CERR_SELECT_CB( _val ) \ + ( ( ( _val ) << L2CACHE_L2CERR_SELECT_CB_SHIFT ) & \ + L2CACHE_L2CERR_SELECT_CB_MASK ) + +#define L2CACHE_L2CERR_SELECT_TCB_SHIFT 4 +#define L2CACHE_L2CERR_SELECT_TCB_MASK 0x30U +#define L2CACHE_L2CERR_SELECT_TCB_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CERR_SELECT_TCB_MASK ) >> \ + L2CACHE_L2CERR_SELECT_TCB_SHIFT ) +#define L2CACHE_L2CERR_SELECT_TCB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERR_SELECT_TCB_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CERR_SELECT_TCB_SHIFT ) & \ + L2CACHE_L2CERR_SELECT_TCB_MASK ) ) +#define L2CACHE_L2CERR_SELECT_TCB( _val ) \ + ( ( ( _val ) << L2CACHE_L2CERR_SELECT_TCB_SHIFT ) & \ + L2CACHE_L2CERR_SELECT_TCB_MASK ) + +#define L2CACHE_L2CERR_XCB 0x8U + +#define L2CACHE_L2CERR_RCB 0x4U + +#define L2CACHE_L2CERR_COMP 0x2U + +#define L2CACHE_L2CERR_RST 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CERRA \ + * L2C Error address register (L2CERRA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CERRA_EADDR_SHIFT 0 +#define L2CACHE_L2CERRA_EADDR_MASK 0xffffffffU +#define L2CACHE_L2CERRA_EADDR_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CERRA_EADDR_MASK ) >> \ + L2CACHE_L2CERRA_EADDR_SHIFT ) +#define L2CACHE_L2CERRA_EADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CERRA_EADDR_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CERRA_EADDR_SHIFT ) & \ + L2CACHE_L2CERRA_EADDR_MASK ) ) +#define L2CACHE_L2CERRA_EADDR( _val ) \ + ( ( ( _val ) << L2CACHE_L2CERRA_EADDR_SHIFT ) & \ + L2CACHE_L2CERRA_EADDR_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CTCB L2C TAG-Check-Bits register (L2CTCB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CTCB_TCB_SHIFT 0 +#define L2CACHE_L2CTCB_TCB_MASK 0x7fU +#define L2CACHE_L2CTCB_TCB_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CTCB_TCB_MASK ) >> \ + L2CACHE_L2CTCB_TCB_SHIFT ) +#define L2CACHE_L2CTCB_TCB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CTCB_TCB_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CTCB_TCB_SHIFT ) & \ + L2CACHE_L2CTCB_TCB_MASK ) ) +#define L2CACHE_L2CTCB_TCB( _val ) \ + ( ( ( _val ) << L2CACHE_L2CTCB_TCB_SHIFT ) & \ + L2CACHE_L2CTCB_TCB_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CCB L2C Data-Check-Bits register (L2CCB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CCB_CB_SHIFT 0 +#define L2CACHE_L2CCB_CB_MASK 0xfffffffU +#define L2CACHE_L2CCB_CB_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CCB_CB_MASK ) >> \ + L2CACHE_L2CCB_CB_SHIFT ) +#define L2CACHE_L2CCB_CB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CCB_CB_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CCB_CB_SHIFT ) & \ + L2CACHE_L2CCB_CB_MASK ) ) +#define L2CACHE_L2CCB_CB( _val ) \ + ( ( ( _val ) << L2CACHE_L2CCB_CB_SHIFT ) & \ + L2CACHE_L2CCB_CB_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CSCRUB \ + * L2C Scrub control/status register (L2CSCRUB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CSCRUB_INDEX_SHIFT 16 +#define L2CACHE_L2CSCRUB_INDEX_MASK 0xffff0000U +#define L2CACHE_L2CSCRUB_INDEX_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CSCRUB_INDEX_MASK ) >> \ + L2CACHE_L2CSCRUB_INDEX_SHIFT ) +#define L2CACHE_L2CSCRUB_INDEX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CSCRUB_INDEX_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CSCRUB_INDEX_SHIFT ) & \ + L2CACHE_L2CSCRUB_INDEX_MASK ) ) +#define L2CACHE_L2CSCRUB_INDEX( _val ) \ + ( ( ( _val ) << L2CACHE_L2CSCRUB_INDEX_SHIFT ) & \ + L2CACHE_L2CSCRUB_INDEX_MASK ) + +#define L2CACHE_L2CSCRUB_WAY_SHIFT 2 +#define L2CACHE_L2CSCRUB_WAY_MASK 0xcU +#define L2CACHE_L2CSCRUB_WAY_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CSCRUB_WAY_MASK ) >> \ + L2CACHE_L2CSCRUB_WAY_SHIFT ) +#define L2CACHE_L2CSCRUB_WAY_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CSCRUB_WAY_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CSCRUB_WAY_SHIFT ) & \ + L2CACHE_L2CSCRUB_WAY_MASK ) ) +#define L2CACHE_L2CSCRUB_WAY( _val ) \ + ( ( ( _val ) << L2CACHE_L2CSCRUB_WAY_SHIFT ) & \ + L2CACHE_L2CSCRUB_WAY_MASK ) + +#define L2CACHE_L2CSCRUB_PEN 0x2U + +#define L2CACHE_L2CSCRUB_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CSDEL L2C Scrub delay register (L2CSDEL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CSDEL_DEL_SHIFT 0 +#define L2CACHE_L2CSDEL_DEL_MASK 0xffffU +#define L2CACHE_L2CSDEL_DEL_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CSDEL_DEL_MASK ) >> \ + L2CACHE_L2CSDEL_DEL_SHIFT ) +#define L2CACHE_L2CSDEL_DEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CSDEL_DEL_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CSDEL_DEL_SHIFT ) & \ + L2CACHE_L2CSDEL_DEL_MASK ) ) +#define L2CACHE_L2CSDEL_DEL( _val ) \ + ( ( ( _val ) << L2CACHE_L2CSDEL_DEL_SHIFT ) & \ + L2CACHE_L2CSDEL_DEL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CEINJ \ + * L2C Error injection register (L2CEINJ) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CEINJ_ADDR_SHIFT 2 +#define L2CACHE_L2CEINJ_ADDR_MASK 0xfffffffcU +#define L2CACHE_L2CEINJ_ADDR_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CEINJ_ADDR_MASK ) >> \ + L2CACHE_L2CEINJ_ADDR_SHIFT ) +#define L2CACHE_L2CEINJ_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CEINJ_ADDR_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CEINJ_ADDR_SHIFT ) & \ + L2CACHE_L2CEINJ_ADDR_MASK ) ) +#define L2CACHE_L2CEINJ_ADDR( _val ) \ + ( ( ( _val ) << L2CACHE_L2CEINJ_ADDR_SHIFT ) & \ + L2CACHE_L2CEINJ_ADDR_MASK ) + +#define L2CACHE_L2CEINJ_INJ 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CACCC \ + * L2C Access control register (L2CACCC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CACCC_DSC 0x4000U + +#define L2CACHE_L2CACCC_SH 0x2000U + +#define L2CACHE_L2CACCC_SPLITQ 0x400U + +#define L2CACHE_L2CACCC_NHM 0x200U + +#define L2CACHE_L2CACCC_BERR 0x100U + +#define L2CACHE_L2CACCC_OAPM 0x80U + +#define L2CACHE_L2CACCC_FLINE 0x40U + +#define L2CACHE_L2CACCC_DBPF 0x20U + +#define L2CACHE_L2CACCC_128WF 0x10U + +#define L2CACHE_L2CACCC_DBPWS 0x4U + +#define L2CACHE_L2CACCC_SPLIT 0x2U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CEINJCFG \ + * L2C injection configuration register (L2CEINJCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CEINJCFG_EDI 0x400U + +#define L2CACHE_L2CEINJCFG_TER 0x200U + +#define L2CACHE_L2CEINJCFG_IMD 0x100U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CMTRR \ + * L2C Memory type range register (L2CMTRR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CMTRR_ADDR_SHIFT 18 +#define L2CACHE_L2CMTRR_ADDR_MASK 0xfffc0000U +#define L2CACHE_L2CMTRR_ADDR_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CMTRR_ADDR_MASK ) >> \ + L2CACHE_L2CMTRR_ADDR_SHIFT ) +#define L2CACHE_L2CMTRR_ADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CMTRR_ADDR_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CMTRR_ADDR_SHIFT ) & \ + L2CACHE_L2CMTRR_ADDR_MASK ) ) +#define L2CACHE_L2CMTRR_ADDR( _val ) \ + ( ( ( _val ) << L2CACHE_L2CMTRR_ADDR_SHIFT ) & \ + L2CACHE_L2CMTRR_ADDR_MASK ) + +#define L2CACHE_L2CMTRR_ACC_SHIFT 16 +#define L2CACHE_L2CMTRR_ACC_MASK 0x30000U +#define L2CACHE_L2CMTRR_ACC_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CMTRR_ACC_MASK ) >> \ + L2CACHE_L2CMTRR_ACC_SHIFT ) +#define L2CACHE_L2CMTRR_ACC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CMTRR_ACC_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CMTRR_ACC_SHIFT ) & \ + L2CACHE_L2CMTRR_ACC_MASK ) ) +#define L2CACHE_L2CMTRR_ACC( _val ) \ + ( ( ( _val ) << L2CACHE_L2CMTRR_ACC_SHIFT ) & \ + L2CACHE_L2CMTRR_ACC_MASK ) + +#define L2CACHE_L2CMTRR_MASK_SHIFT 2 +#define L2CACHE_L2CMTRR_MASK_MASK 0xfffcU +#define L2CACHE_L2CMTRR_MASK_GET( _reg ) \ + ( ( ( _reg ) & L2CACHE_L2CMTRR_MASK_MASK ) >> \ + L2CACHE_L2CMTRR_MASK_SHIFT ) +#define L2CACHE_L2CMTRR_MASK_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L2CACHE_L2CMTRR_MASK_MASK ) | \ + ( ( ( _val ) << L2CACHE_L2CMTRR_MASK_SHIFT ) & \ + L2CACHE_L2CMTRR_MASK_MASK ) ) +#define L2CACHE_L2CMTRR_MASK( _val ) \ + ( ( ( _val ) << L2CACHE_L2CMTRR_MASK_SHIFT ) & \ + L2CACHE_L2CMTRR_MASK_MASK ) + +#define L2CACHE_L2CMTRR_WP 0x2U + +#define L2CACHE_L2CMTRR_AC 0x1U + +/** @} */ + +/** + * @brief This structure defines the L2CACHE register block memory map. + */ +typedef struct l2cache { + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CC. + */ + uint32_t l2cc; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CS. + */ + uint32_t l2cs; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CFMA. + */ + uint32_t l2cfma; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CFSI. + */ + uint32_t l2cfsi; + + uint32_t reserved_10_20[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CERR. + */ + uint32_t l2cerr; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CERRA. + */ + uint32_t l2cerra; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CTCB. + */ + uint32_t l2ctcb; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CCB. + */ + uint32_t l2ccb; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CSCRUB. + */ + uint32_t l2cscrub; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CSDEL. + */ + uint32_t l2csdel; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CEINJ. + */ + uint32_t l2ceinj; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CACCC. + */ + uint32_t l2caccc; + + uint32_t reserved_40_4c[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CEINJCFG. + */ + uint32_t l2ceinjcfg; + + uint32_t reserved_50_80[ 12 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CMTRR. + */ + uint32_t l2cmtrr; +} l2cache; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_L2CACHE_REGS_H */ diff --git a/bsps/include/grlib/l4stat-regs.h b/bsps/include/grlib/l4stat-regs.h new file mode 100644 index 0000000000..971898f476 --- /dev/null +++ b/bsps/include/grlib/l4stat-regs.h @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBL4STAT + * + * @brief This header file defines the L4STAT register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/l4stat-header */ + +#ifndef _GRLIB_L4STAT_REGS_H +#define _GRLIB_L4STAT_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/l4stat */ + +/** + * @defgroup RTEMSDeviceGRLIBL4STAT L4STAT + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the L4STAT interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBL4STATCVAL Counter 0-15 value register (CVAL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L4STAT_CVAL_CVAL_SHIFT 0 +#define L4STAT_CVAL_CVAL_MASK 0xffffffffU +#define L4STAT_CVAL_CVAL_GET( _reg ) \ + ( ( ( _reg ) & L4STAT_CVAL_CVAL_MASK ) >> \ + L4STAT_CVAL_CVAL_SHIFT ) +#define L4STAT_CVAL_CVAL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L4STAT_CVAL_CVAL_MASK ) | \ + ( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & \ + L4STAT_CVAL_CVAL_MASK ) ) +#define L4STAT_CVAL_CVAL( _val ) \ + ( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & \ + L4STAT_CVAL_CVAL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL4STATCCTRL Counter 0-15 control register (CCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L4STAT_CCTRL_NCPU_SHIFT 28 +#define L4STAT_CCTRL_NCPU_MASK 0xf0000000U +#define L4STAT_CCTRL_NCPU_GET( _reg ) \ + ( ( ( _reg ) & L4STAT_CCTRL_NCPU_MASK ) >> \ + L4STAT_CCTRL_NCPU_SHIFT ) +#define L4STAT_CCTRL_NCPU_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L4STAT_CCTRL_NCPU_MASK ) | \ + ( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \ + L4STAT_CCTRL_NCPU_MASK ) ) +#define L4STAT_CCTRL_NCPU( _val ) \ + ( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \ + L4STAT_CCTRL_NCPU_MASK ) + +#define L4STAT_CCTRL_NCNT_SHIFT 23 +#define L4STAT_CCTRL_NCNT_MASK 0xf800000U +#define L4STAT_CCTRL_NCNT_GET( _reg ) \ + ( ( ( _reg ) & L4STAT_CCTRL_NCNT_MASK ) >> \ + L4STAT_CCTRL_NCNT_SHIFT ) +#define L4STAT_CCTRL_NCNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L4STAT_CCTRL_NCNT_MASK ) | \ + ( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \ + L4STAT_CCTRL_NCNT_MASK ) ) +#define L4STAT_CCTRL_NCNT( _val ) \ + ( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \ + L4STAT_CCTRL_NCNT_MASK ) + +#define L4STAT_CCTRL_MC 0x400000U + +#define L4STAT_CCTRL_IA 0x200000U + +#define L4STAT_CCTRL_DS 0x100000U + +#define L4STAT_CCTRL_EE 0x80000U + +#define L4STAT_CCTRL_AE 0x40000U + +#define L4STAT_CCTRL_EL 0x20000U + +#define L4STAT_CCTRL_CD 0x10000U + +#define L4STAT_CCTRL_SU_SHIFT 14 +#define L4STAT_CCTRL_SU_MASK 0xc000U +#define L4STAT_CCTRL_SU_GET( _reg ) \ + ( ( ( _reg ) & L4STAT_CCTRL_SU_MASK ) >> \ + L4STAT_CCTRL_SU_SHIFT ) +#define L4STAT_CCTRL_SU_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L4STAT_CCTRL_SU_MASK ) | \ + ( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \ + L4STAT_CCTRL_SU_MASK ) ) +#define L4STAT_CCTRL_SU( _val ) \ + ( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \ + L4STAT_CCTRL_SU_MASK ) + +#define L4STAT_CCTRL_CL 0x2000U + +#define L4STAT_CCTRL_EN 0x1000U + +#define L4STAT_CCTRL_EVENT_ID_SHIFT 4 +#define L4STAT_CCTRL_EVENT_ID_MASK 0xff0U +#define L4STAT_CCTRL_EVENT_ID_GET( _reg ) \ + ( ( ( _reg ) & L4STAT_CCTRL_EVENT_ID_MASK ) >> \ + L4STAT_CCTRL_EVENT_ID_SHIFT ) +#define L4STAT_CCTRL_EVENT_ID_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L4STAT_CCTRL_EVENT_ID_MASK ) | \ + ( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \ + L4STAT_CCTRL_EVENT_ID_MASK ) ) +#define L4STAT_CCTRL_EVENT_ID( _val ) \ + ( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \ + L4STAT_CCTRL_EVENT_ID_MASK ) + +#define L4STAT_CCTRL_CPU_AHBM_SHIFT 0 +#define L4STAT_CCTRL_CPU_AHBM_MASK 0xfU +#define L4STAT_CCTRL_CPU_AHBM_GET( _reg ) \ + ( ( ( _reg ) & L4STAT_CCTRL_CPU_AHBM_MASK ) >> \ + L4STAT_CCTRL_CPU_AHBM_SHIFT ) +#define L4STAT_CCTRL_CPU_AHBM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L4STAT_CCTRL_CPU_AHBM_MASK ) | \ + ( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \ + L4STAT_CCTRL_CPU_AHBM_MASK ) ) +#define L4STAT_CCTRL_CPU_AHBM( _val ) \ + ( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \ + L4STAT_CCTRL_CPU_AHBM_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL4STATCSVAL \ + * Counter 0-15 max/latch register (CSVAL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L4STAT_CSVAL_CSVAL_SHIFT 0 +#define L4STAT_CSVAL_CSVAL_MASK 0xffffffffU +#define L4STAT_CSVAL_CSVAL_GET( _reg ) \ + ( ( ( _reg ) & L4STAT_CSVAL_CSVAL_MASK ) >> \ + L4STAT_CSVAL_CSVAL_SHIFT ) +#define L4STAT_CSVAL_CSVAL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L4STAT_CSVAL_CSVAL_MASK ) | \ + ( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & \ + L4STAT_CSVAL_CSVAL_MASK ) ) +#define L4STAT_CSVAL_CSVAL( _val ) \ + ( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & \ + L4STAT_CSVAL_CSVAL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL4STATTSTAMP Timestamp register (TSTAMP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L4STAT_TSTAMP_TSTAMP_SHIFT 0 +#define L4STAT_TSTAMP_TSTAMP_MASK 0xffffffffU +#define L4STAT_TSTAMP_TSTAMP_GET( _reg ) \ + ( ( ( _reg ) & L4STAT_TSTAMP_TSTAMP_MASK ) >> \ + L4STAT_TSTAMP_TSTAMP_SHIFT ) +#define L4STAT_TSTAMP_TSTAMP_SET( _reg, _val ) \ + ( ( ( _reg ) & ~L4STAT_TSTAMP_TSTAMP_MASK ) | \ + ( ( ( _val ) << L4STAT_TSTAMP_TSTAMP_SHIFT ) & \ + L4STAT_TSTAMP_TSTAMP_MASK ) ) +#define L4STAT_TSTAMP_TSTAMP( _val ) \ + ( ( ( _val ) << L4STAT_TSTAMP_TSTAMP_SHIFT ) & \ + L4STAT_TSTAMP_TSTAMP_MASK ) + +/** @} */ + +/** + * @brief This structure defines the L4STAT register block memory map. + */ +typedef struct l4stat { + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATCVAL. + */ + uint32_t cval_0; + + uint32_t reserved_4_3c[ 14 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATCVAL. + */ + uint32_t cval_1; + + uint32_t reserved_40_80[ 16 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATCCTRL. + */ + uint32_t cctrl_0; + + uint32_t reserved_84_cc[ 18 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATCCTRL. + */ + uint32_t cctrl_1; + + uint32_t reserved_d0_100[ 12 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATCSVAL. + */ + uint32_t csval_0; + + uint32_t reserved_104_13c[ 14 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATCSVAL. + */ + uint32_t csval_1; + + uint32_t reserved_140_180[ 16 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATTSTAMP. + */ + uint32_t tstamp; +} l4stat; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_L4STAT_REGS_H */ diff --git a/bsps/include/grlib/l4stat.h b/bsps/include/grlib/l4stat.h index 94fbe4b095..ddbde084ce 100644 --- a/bsps/include/grlib/l4stat.h +++ b/bsps/include/grlib/l4stat.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * L4STAT APB-Register Driver. * * COPYRIGHT (c) 2017. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __L4STAT_H__ diff --git a/bsps/include/grlib/mctrl.h b/bsps/include/grlib/mctrl.h index db449cb11a..e2d7eadb43 100644 --- a/bsps/include/grlib/mctrl.h +++ b/bsps/include/grlib/mctrl.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * Memory Controller driver interface * * COPYRIGHT (c) 2015. * Cobham Gaisler. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __MCTRL_H__ diff --git a/bsps/include/grlib/memscrub-regs.h b/bsps/include/grlib/memscrub-regs.h new file mode 100644 index 0000000000..bfeacc7d20 --- /dev/null +++ b/bsps/include/grlib/memscrub-regs.h @@ -0,0 +1,568 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBMEMSCRUB + * + * @brief This header file defines the MEMSCRUB register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/memscrub-header */ + +#ifndef _GRLIB_MEMSCRUB_REGS_H +#define _GRLIB_MEMSCRUB_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/memscrub */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUB MEMSCRUB + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the MEMSCRUB interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBAHBS AHB Status register (AHBS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_AHBS_CECNT_SHIFT 22 +#define MEMSCRUB_AHBS_CECNT_MASK 0xffc00000U +#define MEMSCRUB_AHBS_CECNT_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_AHBS_CECNT_MASK ) >> \ + MEMSCRUB_AHBS_CECNT_SHIFT ) +#define MEMSCRUB_AHBS_CECNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBS_CECNT_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_AHBS_CECNT_SHIFT ) & \ + MEMSCRUB_AHBS_CECNT_MASK ) ) +#define MEMSCRUB_AHBS_CECNT( _val ) \ + ( ( ( _val ) << MEMSCRUB_AHBS_CECNT_SHIFT ) & \ + MEMSCRUB_AHBS_CECNT_MASK ) + +#define MEMSCRUB_AHBS_UECNT_SHIFT 14 +#define MEMSCRUB_AHBS_UECNT_MASK 0x3fc000U +#define MEMSCRUB_AHBS_UECNT_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_AHBS_UECNT_MASK ) >> \ + MEMSCRUB_AHBS_UECNT_SHIFT ) +#define MEMSCRUB_AHBS_UECNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBS_UECNT_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_AHBS_UECNT_SHIFT ) & \ + MEMSCRUB_AHBS_UECNT_MASK ) ) +#define MEMSCRUB_AHBS_UECNT( _val ) \ + ( ( ( _val ) << MEMSCRUB_AHBS_UECNT_SHIFT ) & \ + MEMSCRUB_AHBS_UECNT_MASK ) + +#define MEMSCRUB_AHBS_DONE 0x2000U + +#define MEMSCRUB_AHBS_SEC 0x800U + +#define MEMSCRUB_AHBS_SBC 0x400U + +#define MEMSCRUB_AHBS_CE 0x200U + +#define MEMSCRUB_AHBS_NE 0x100U + +#define MEMSCRUB_AHBS_HWRITE 0x80U + +#define MEMSCRUB_AHBS_HMASTER_SHIFT 3 +#define MEMSCRUB_AHBS_HMASTER_MASK 0x78U +#define MEMSCRUB_AHBS_HMASTER_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_AHBS_HMASTER_MASK ) >> \ + MEMSCRUB_AHBS_HMASTER_SHIFT ) +#define MEMSCRUB_AHBS_HMASTER_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBS_HMASTER_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_AHBS_HMASTER_SHIFT ) & \ + MEMSCRUB_AHBS_HMASTER_MASK ) ) +#define MEMSCRUB_AHBS_HMASTER( _val ) \ + ( ( ( _val ) << MEMSCRUB_AHBS_HMASTER_SHIFT ) & \ + MEMSCRUB_AHBS_HMASTER_MASK ) + +#define MEMSCRUB_AHBS_HSIZE_SHIFT 0 +#define MEMSCRUB_AHBS_HSIZE_MASK 0x7U +#define MEMSCRUB_AHBS_HSIZE_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_AHBS_HSIZE_MASK ) >> \ + MEMSCRUB_AHBS_HSIZE_SHIFT ) +#define MEMSCRUB_AHBS_HSIZE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBS_HSIZE_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_AHBS_HSIZE_SHIFT ) & \ + MEMSCRUB_AHBS_HSIZE_MASK ) ) +#define MEMSCRUB_AHBS_HSIZE( _val ) \ + ( ( ( _val ) << MEMSCRUB_AHBS_HSIZE_SHIFT ) & \ + MEMSCRUB_AHBS_HSIZE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBAHBFAR \ + * AHB Failing Address Register (AHBFAR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT 0 +#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK 0xffffffffU +#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) >> \ + MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT ) +#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT ) & \ + MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) ) +#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS( _val ) \ + ( ( ( _val ) << MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT ) & \ + MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBAHBERC \ + * AHB Error configuration register (AHBERC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_AHBERC_CECNTT_SHIFT 22 +#define MEMSCRUB_AHBERC_CECNTT_MASK 0xffc00000U +#define MEMSCRUB_AHBERC_CECNTT_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_AHBERC_CECNTT_MASK ) >> \ + MEMSCRUB_AHBERC_CECNTT_SHIFT ) +#define MEMSCRUB_AHBERC_CECNTT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBERC_CECNTT_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_AHBERC_CECNTT_SHIFT ) & \ + MEMSCRUB_AHBERC_CECNTT_MASK ) ) +#define MEMSCRUB_AHBERC_CECNTT( _val ) \ + ( ( ( _val ) << MEMSCRUB_AHBERC_CECNTT_SHIFT ) & \ + MEMSCRUB_AHBERC_CECNTT_MASK ) + +#define MEMSCRUB_AHBERC_UECNTT_SHIFT 14 +#define MEMSCRUB_AHBERC_UECNTT_MASK 0x3fc000U +#define MEMSCRUB_AHBERC_UECNTT_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_AHBERC_UECNTT_MASK ) >> \ + MEMSCRUB_AHBERC_UECNTT_SHIFT ) +#define MEMSCRUB_AHBERC_UECNTT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_AHBERC_UECNTT_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_AHBERC_UECNTT_SHIFT ) & \ + MEMSCRUB_AHBERC_UECNTT_MASK ) ) +#define MEMSCRUB_AHBERC_UECNTT( _val ) \ + ( ( ( _val ) << MEMSCRUB_AHBERC_UECNTT_SHIFT ) & \ + MEMSCRUB_AHBERC_UECNTT_MASK ) + +#define MEMSCRUB_AHBERC_CECTE 0x2U + +#define MEMSCRUB_AHBERC_UECTE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBSTAT Status register (STAT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_STAT_RUNCOUNT_SHIFT 22 +#define MEMSCRUB_STAT_RUNCOUNT_MASK 0xffc00000U +#define MEMSCRUB_STAT_RUNCOUNT_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_STAT_RUNCOUNT_MASK ) >> \ + MEMSCRUB_STAT_RUNCOUNT_SHIFT ) +#define MEMSCRUB_STAT_RUNCOUNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_STAT_RUNCOUNT_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_STAT_RUNCOUNT_SHIFT ) & \ + MEMSCRUB_STAT_RUNCOUNT_MASK ) ) +#define MEMSCRUB_STAT_RUNCOUNT( _val ) \ + ( ( ( _val ) << MEMSCRUB_STAT_RUNCOUNT_SHIFT ) & \ + MEMSCRUB_STAT_RUNCOUNT_MASK ) + +#define MEMSCRUB_STAT_BLKCOUNT_SHIFT 14 +#define MEMSCRUB_STAT_BLKCOUNT_MASK 0x3fc000U +#define MEMSCRUB_STAT_BLKCOUNT_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_STAT_BLKCOUNT_MASK ) >> \ + MEMSCRUB_STAT_BLKCOUNT_SHIFT ) +#define MEMSCRUB_STAT_BLKCOUNT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_STAT_BLKCOUNT_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_STAT_BLKCOUNT_SHIFT ) & \ + MEMSCRUB_STAT_BLKCOUNT_MASK ) ) +#define MEMSCRUB_STAT_BLKCOUNT( _val ) \ + ( ( ( _val ) << MEMSCRUB_STAT_BLKCOUNT_SHIFT ) & \ + MEMSCRUB_STAT_BLKCOUNT_MASK ) + +#define MEMSCRUB_STAT_DONE 0x2000U + +#define MEMSCRUB_STAT_BURSTLEN_SHIFT 1 +#define MEMSCRUB_STAT_BURSTLEN_MASK 0x1eU +#define MEMSCRUB_STAT_BURSTLEN_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_STAT_BURSTLEN_MASK ) >> \ + MEMSCRUB_STAT_BURSTLEN_SHIFT ) +#define MEMSCRUB_STAT_BURSTLEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_STAT_BURSTLEN_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_STAT_BURSTLEN_SHIFT ) & \ + MEMSCRUB_STAT_BURSTLEN_MASK ) ) +#define MEMSCRUB_STAT_BURSTLEN( _val ) \ + ( ( ( _val ) << MEMSCRUB_STAT_BURSTLEN_SHIFT ) & \ + MEMSCRUB_STAT_BURSTLEN_MASK ) + +#define MEMSCRUB_STAT_ACTIVE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBCONFIG Configuration register (CONFIG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_CONFIG_DELAY_SHIFT 8 +#define MEMSCRUB_CONFIG_DELAY_MASK 0xff00U +#define MEMSCRUB_CONFIG_DELAY_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_CONFIG_DELAY_MASK ) >> \ + MEMSCRUB_CONFIG_DELAY_SHIFT ) +#define MEMSCRUB_CONFIG_DELAY_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_CONFIG_DELAY_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_CONFIG_DELAY_SHIFT ) & \ + MEMSCRUB_CONFIG_DELAY_MASK ) ) +#define MEMSCRUB_CONFIG_DELAY( _val ) \ + ( ( ( _val ) << MEMSCRUB_CONFIG_DELAY_SHIFT ) & \ + MEMSCRUB_CONFIG_DELAY_MASK ) + +#define MEMSCRUB_CONFIG_IRQD 0x80U + +#define MEMSCRUB_CONFIG_SERA 0x20U + +#define MEMSCRUB_CONFIG_LOOP 0x10U + +#define MEMSCRUB_CONFIG_MODE_SHIFT 2 +#define MEMSCRUB_CONFIG_MODE_MASK 0xcU +#define MEMSCRUB_CONFIG_MODE_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_CONFIG_MODE_MASK ) >> \ + MEMSCRUB_CONFIG_MODE_SHIFT ) +#define MEMSCRUB_CONFIG_MODE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_CONFIG_MODE_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_CONFIG_MODE_SHIFT ) & \ + MEMSCRUB_CONFIG_MODE_MASK ) ) +#define MEMSCRUB_CONFIG_MODE( _val ) \ + ( ( ( _val ) << MEMSCRUB_CONFIG_MODE_SHIFT ) & \ + MEMSCRUB_CONFIG_MODE_MASK ) + +#define MEMSCRUB_CONFIG_ES 0x2U + +#define MEMSCRUB_CONFIG_SCEN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBRANGEL Range low address register (RANGEL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_RANGEL_RLADDR_SHIFT 0 +#define MEMSCRUB_RANGEL_RLADDR_MASK 0xffffffffU +#define MEMSCRUB_RANGEL_RLADDR_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_RANGEL_RLADDR_MASK ) >> \ + MEMSCRUB_RANGEL_RLADDR_SHIFT ) +#define MEMSCRUB_RANGEL_RLADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_RANGEL_RLADDR_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_RANGEL_RLADDR_SHIFT ) & \ + MEMSCRUB_RANGEL_RLADDR_MASK ) ) +#define MEMSCRUB_RANGEL_RLADDR( _val ) \ + ( ( ( _val ) << MEMSCRUB_RANGEL_RLADDR_SHIFT ) & \ + MEMSCRUB_RANGEL_RLADDR_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBRANGEH \ + * Range high address register (RANGEH) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_RANGEH_RHADDR_SHIFT 0 +#define MEMSCRUB_RANGEH_RHADDR_MASK 0xffffffffU +#define MEMSCRUB_RANGEH_RHADDR_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_RANGEH_RHADDR_MASK ) >> \ + MEMSCRUB_RANGEH_RHADDR_SHIFT ) +#define MEMSCRUB_RANGEH_RHADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_RANGEH_RHADDR_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_RANGEH_RHADDR_SHIFT ) & \ + MEMSCRUB_RANGEH_RHADDR_MASK ) ) +#define MEMSCRUB_RANGEH_RHADDR( _val ) \ + ( ( ( _val ) << MEMSCRUB_RANGEH_RHADDR_SHIFT ) & \ + MEMSCRUB_RANGEH_RHADDR_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBPOS Position register (POS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_POS_POSITION_SHIFT 0 +#define MEMSCRUB_POS_POSITION_MASK 0xffffffffU +#define MEMSCRUB_POS_POSITION_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_POS_POSITION_MASK ) >> \ + MEMSCRUB_POS_POSITION_SHIFT ) +#define MEMSCRUB_POS_POSITION_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_POS_POSITION_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_POS_POSITION_SHIFT ) & \ + MEMSCRUB_POS_POSITION_MASK ) ) +#define MEMSCRUB_POS_POSITION( _val ) \ + ( ( ( _val ) << MEMSCRUB_POS_POSITION_SHIFT ) & \ + MEMSCRUB_POS_POSITION_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBETHRES Error threshold register (ETHRES) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_ETHRES_RECT_SHIFT 22 +#define MEMSCRUB_ETHRES_RECT_MASK 0xffc00000U +#define MEMSCRUB_ETHRES_RECT_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_ETHRES_RECT_MASK ) >> \ + MEMSCRUB_ETHRES_RECT_SHIFT ) +#define MEMSCRUB_ETHRES_RECT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_ETHRES_RECT_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_ETHRES_RECT_SHIFT ) & \ + MEMSCRUB_ETHRES_RECT_MASK ) ) +#define MEMSCRUB_ETHRES_RECT( _val ) \ + ( ( ( _val ) << MEMSCRUB_ETHRES_RECT_SHIFT ) & \ + MEMSCRUB_ETHRES_RECT_MASK ) + +#define MEMSCRUB_ETHRES_BECT_SHIFT 14 +#define MEMSCRUB_ETHRES_BECT_MASK 0x3fc000U +#define MEMSCRUB_ETHRES_BECT_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_ETHRES_BECT_MASK ) >> \ + MEMSCRUB_ETHRES_BECT_SHIFT ) +#define MEMSCRUB_ETHRES_BECT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_ETHRES_BECT_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_ETHRES_BECT_SHIFT ) & \ + MEMSCRUB_ETHRES_BECT_MASK ) ) +#define MEMSCRUB_ETHRES_BECT( _val ) \ + ( ( ( _val ) << MEMSCRUB_ETHRES_BECT_SHIFT ) & \ + MEMSCRUB_ETHRES_BECT_MASK ) + +#define MEMSCRUB_ETHRES_RECTE 0x2U + +#define MEMSCRUB_ETHRES_BECTE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBINIT Initialisation data register (INIT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_INIT_DATA_SHIFT 0 +#define MEMSCRUB_INIT_DATA_MASK 0xffffffffU +#define MEMSCRUB_INIT_DATA_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_INIT_DATA_MASK ) >> \ + MEMSCRUB_INIT_DATA_SHIFT ) +#define MEMSCRUB_INIT_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_INIT_DATA_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_INIT_DATA_SHIFT ) & \ + MEMSCRUB_INIT_DATA_MASK ) ) +#define MEMSCRUB_INIT_DATA( _val ) \ + ( ( ( _val ) << MEMSCRUB_INIT_DATA_SHIFT ) & \ + MEMSCRUB_INIT_DATA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBRANGEL2 \ + * Second range low address register (RANGEL2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_RANGEL2_RLADDR_SHIFT 0 +#define MEMSCRUB_RANGEL2_RLADDR_MASK 0xffffffffU +#define MEMSCRUB_RANGEL2_RLADDR_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_RANGEL2_RLADDR_MASK ) >> \ + MEMSCRUB_RANGEL2_RLADDR_SHIFT ) +#define MEMSCRUB_RANGEL2_RLADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_RANGEL2_RLADDR_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_RANGEL2_RLADDR_SHIFT ) & \ + MEMSCRUB_RANGEL2_RLADDR_MASK ) ) +#define MEMSCRUB_RANGEL2_RLADDR( _val ) \ + ( ( ( _val ) << MEMSCRUB_RANGEL2_RLADDR_SHIFT ) & \ + MEMSCRUB_RANGEL2_RLADDR_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBRANGEH2 \ + * Second range high address register (RANGEH2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_RANGEH2_RHADDR_SHIFT 0 +#define MEMSCRUB_RANGEH2_RHADDR_MASK 0xffffffffU +#define MEMSCRUB_RANGEH2_RHADDR_GET( _reg ) \ + ( ( ( _reg ) & MEMSCRUB_RANGEH2_RHADDR_MASK ) >> \ + MEMSCRUB_RANGEH2_RHADDR_SHIFT ) +#define MEMSCRUB_RANGEH2_RHADDR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MEMSCRUB_RANGEH2_RHADDR_MASK ) | \ + ( ( ( _val ) << MEMSCRUB_RANGEH2_RHADDR_SHIFT ) & \ + MEMSCRUB_RANGEH2_RHADDR_MASK ) ) +#define MEMSCRUB_RANGEH2_RHADDR( _val ) \ + ( ( ( _val ) << MEMSCRUB_RANGEH2_RHADDR_SHIFT ) & \ + MEMSCRUB_RANGEH2_RHADDR_MASK ) + +/** @} */ + +/** + * @brief This structure defines the MEMSCRUB register block memory map. + */ +typedef struct memscrub { + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBAHBS. + */ + uint32_t ahbs; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBAHBFAR. + */ + uint32_t ahbfar; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBAHBERC. + */ + uint32_t ahberc; + + uint32_t reserved_c_10; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBSTAT. + */ + uint32_t stat; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBCONFIG. + */ + uint32_t config; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBRANGEL. + */ + uint32_t rangel; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBRANGEH. + */ + uint32_t rangeh; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBPOS. + */ + uint32_t pos; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBETHRES. + */ + uint32_t ethres; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBINIT. + */ + uint32_t init; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBRANGEL2. + */ + uint32_t rangel2; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBRANGEH2. + */ + uint32_t rangeh2; +} memscrub; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_MEMSCRUB_REGS_H */ diff --git a/bsps/include/grlib/memscrub.h b/bsps/include/grlib/memscrub.h index 1e55d8e127..84919927c3 100644 --- a/bsps/include/grlib/memscrub.h +++ b/bsps/include/grlib/memscrub.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* MEMSCRUB driver interface * * COPYRIGHT (c) 2017. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __MEMSCRUB_H__ diff --git a/bsps/include/grlib/mmctrl-regs.h b/bsps/include/grlib/mmctrl-regs.h new file mode 100644 index 0000000000..3e860ef96a --- /dev/null +++ b/bsps/include/grlib/mmctrl-regs.h @@ -0,0 +1,434 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBMMCTRL + * + * @brief This header file defines the MMCTRL register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/mmctrl-header */ + +#ifndef _GRLIB_MMCTRL_REGS_H +#define _GRLIB_MMCTRL_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/mmctrl */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRL MMCTRL + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the MMCTRL interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLSDCFG1 \ + * SDRAM configuration register 1 (SDCFG1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_SDCFG1_RF 0x80000000U + +#define MMCTRL_SDCFG1_TRP 0x40000000U + +#define MMCTRL_SDCFG1_TRFC_SHIFT 27 +#define MMCTRL_SDCFG1_TRFC_MASK 0x38000000U +#define MMCTRL_SDCFG1_TRFC_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_SDCFG1_TRFC_MASK ) >> \ + MMCTRL_SDCFG1_TRFC_SHIFT ) +#define MMCTRL_SDCFG1_TRFC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_SDCFG1_TRFC_MASK ) | \ + ( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & \ + MMCTRL_SDCFG1_TRFC_MASK ) ) +#define MMCTRL_SDCFG1_TRFC( _val ) \ + ( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & \ + MMCTRL_SDCFG1_TRFC_MASK ) + +#define MMCTRL_SDCFG1_TC 0x4000000U + +#define MMCTRL_SDCFG1_BANKSZ_SHIFT 23 +#define MMCTRL_SDCFG1_BANKSZ_MASK 0x3800000U +#define MMCTRL_SDCFG1_BANKSZ_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_SDCFG1_BANKSZ_MASK ) >> \ + MMCTRL_SDCFG1_BANKSZ_SHIFT ) +#define MMCTRL_SDCFG1_BANKSZ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_SDCFG1_BANKSZ_MASK ) | \ + ( ( ( _val ) << MMCTRL_SDCFG1_BANKSZ_SHIFT ) & \ + MMCTRL_SDCFG1_BANKSZ_MASK ) ) +#define MMCTRL_SDCFG1_BANKSZ( _val ) \ + ( ( ( _val ) << MMCTRL_SDCFG1_BANKSZ_SHIFT ) & \ + MMCTRL_SDCFG1_BANKSZ_MASK ) + +#define MMCTRL_SDCFG1_COLSZ_SHIFT 21 +#define MMCTRL_SDCFG1_COLSZ_MASK 0x600000U +#define MMCTRL_SDCFG1_COLSZ_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_SDCFG1_COLSZ_MASK ) >> \ + MMCTRL_SDCFG1_COLSZ_SHIFT ) +#define MMCTRL_SDCFG1_COLSZ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_SDCFG1_COLSZ_MASK ) | \ + ( ( ( _val ) << MMCTRL_SDCFG1_COLSZ_SHIFT ) & \ + MMCTRL_SDCFG1_COLSZ_MASK ) ) +#define MMCTRL_SDCFG1_COLSZ( _val ) \ + ( ( ( _val ) << MMCTRL_SDCFG1_COLSZ_SHIFT ) & \ + MMCTRL_SDCFG1_COLSZ_MASK ) + +#define MMCTRL_SDCFG1_COMMAND_SHIFT 18 +#define MMCTRL_SDCFG1_COMMAND_MASK 0x1c0000U +#define MMCTRL_SDCFG1_COMMAND_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_SDCFG1_COMMAND_MASK ) >> \ + MMCTRL_SDCFG1_COMMAND_SHIFT ) +#define MMCTRL_SDCFG1_COMMAND_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_SDCFG1_COMMAND_MASK ) | \ + ( ( ( _val ) << MMCTRL_SDCFG1_COMMAND_SHIFT ) & \ + MMCTRL_SDCFG1_COMMAND_MASK ) ) +#define MMCTRL_SDCFG1_COMMAND( _val ) \ + ( ( ( _val ) << MMCTRL_SDCFG1_COMMAND_SHIFT ) & \ + MMCTRL_SDCFG1_COMMAND_MASK ) + +#define MMCTRL_SDCFG1_MS 0x10000U + +#define MMCTRL_SDCFG1_64 0x8000U + +#define MMCTRL_SDCFG1_RFLOAD_SHIFT 0 +#define MMCTRL_SDCFG1_RFLOAD_MASK 0x7fffU +#define MMCTRL_SDCFG1_RFLOAD_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_SDCFG1_RFLOAD_MASK ) >> \ + MMCTRL_SDCFG1_RFLOAD_SHIFT ) +#define MMCTRL_SDCFG1_RFLOAD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_SDCFG1_RFLOAD_MASK ) | \ + ( ( ( _val ) << MMCTRL_SDCFG1_RFLOAD_SHIFT ) & \ + MMCTRL_SDCFG1_RFLOAD_MASK ) ) +#define MMCTRL_SDCFG1_RFLOAD( _val ) \ + ( ( ( _val ) << MMCTRL_SDCFG1_RFLOAD_SHIFT ) & \ + MMCTRL_SDCFG1_RFLOAD_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLSDCFG2 \ + * SDRAM configuration register 2 (SDCFG2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_SDCFG2_CE 0x40000000U + +#define MMCTRL_SDCFG2_EN2T 0x8000U + +#define MMCTRL_SDCFG2_DCS 0x4000U + +#define MMCTRL_SDCFG2_BPARK 0x2000U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLMUXCFG Mux configuration register (MUXCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_MUXCFG_ERRLOC_SHIFT 20 +#define MMCTRL_MUXCFG_ERRLOC_MASK 0xfff00000U +#define MMCTRL_MUXCFG_ERRLOC_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_MUXCFG_ERRLOC_MASK ) >> \ + MMCTRL_MUXCFG_ERRLOC_SHIFT ) +#define MMCTRL_MUXCFG_ERRLOC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_MUXCFG_ERRLOC_MASK ) | \ + ( ( ( _val ) << MMCTRL_MUXCFG_ERRLOC_SHIFT ) & \ + MMCTRL_MUXCFG_ERRLOC_MASK ) ) +#define MMCTRL_MUXCFG_ERRLOC( _val ) \ + ( ( ( _val ) << MMCTRL_MUXCFG_ERRLOC_SHIFT ) & \ + MMCTRL_MUXCFG_ERRLOC_MASK ) + +#define MMCTRL_MUXCFG_DDERR 0x80000U + +#define MMCTRL_MUXCFG_DWIDTH_SHIFT 16 +#define MMCTRL_MUXCFG_DWIDTH_MASK 0x70000U +#define MMCTRL_MUXCFG_DWIDTH_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_MUXCFG_DWIDTH_MASK ) >> \ + MMCTRL_MUXCFG_DWIDTH_SHIFT ) +#define MMCTRL_MUXCFG_DWIDTH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_MUXCFG_DWIDTH_MASK ) | \ + ( ( ( _val ) << MMCTRL_MUXCFG_DWIDTH_SHIFT ) & \ + MMCTRL_MUXCFG_DWIDTH_MASK ) ) +#define MMCTRL_MUXCFG_DWIDTH( _val ) \ + ( ( ( _val ) << MMCTRL_MUXCFG_DWIDTH_SHIFT ) & \ + MMCTRL_MUXCFG_DWIDTH_MASK ) + +#define MMCTRL_MUXCFG_BEID_SHIFT 12 +#define MMCTRL_MUXCFG_BEID_MASK 0xf000U +#define MMCTRL_MUXCFG_BEID_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_MUXCFG_BEID_MASK ) >> \ + MMCTRL_MUXCFG_BEID_SHIFT ) +#define MMCTRL_MUXCFG_BEID_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_MUXCFG_BEID_MASK ) | \ + ( ( ( _val ) << MMCTRL_MUXCFG_BEID_SHIFT ) & \ + MMCTRL_MUXCFG_BEID_MASK ) ) +#define MMCTRL_MUXCFG_BEID( _val ) \ + ( ( ( _val ) << MMCTRL_MUXCFG_BEID_SHIFT ) & \ + MMCTRL_MUXCFG_BEID_MASK ) + +#define MMCTRL_MUXCFG_DATAMUX_SHIFT 5 +#define MMCTRL_MUXCFG_DATAMUX_MASK 0xe0U +#define MMCTRL_MUXCFG_DATAMUX_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_MUXCFG_DATAMUX_MASK ) >> \ + MMCTRL_MUXCFG_DATAMUX_SHIFT ) +#define MMCTRL_MUXCFG_DATAMUX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_MUXCFG_DATAMUX_MASK ) | \ + ( ( ( _val ) << MMCTRL_MUXCFG_DATAMUX_SHIFT ) & \ + MMCTRL_MUXCFG_DATAMUX_MASK ) ) +#define MMCTRL_MUXCFG_DATAMUX( _val ) \ + ( ( ( _val ) << MMCTRL_MUXCFG_DATAMUX_SHIFT ) & \ + MMCTRL_MUXCFG_DATAMUX_MASK ) + +#define MMCTRL_MUXCFG_CEN 0x10U + +#define MMCTRL_MUXCFG_BAUPD 0x8U + +#define MMCTRL_MUXCFG_BAEN 0x4U + +#define MMCTRL_MUXCFG_CODE 0x2U + +#define MMCTRL_MUXCFG_EDEN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLFTDA FT diagnostic address register (FTDA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_FTDA_FTDA_SHIFT 2 +#define MMCTRL_FTDA_FTDA_MASK 0xfffffffcU +#define MMCTRL_FTDA_FTDA_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_FTDA_FTDA_MASK ) >> \ + MMCTRL_FTDA_FTDA_SHIFT ) +#define MMCTRL_FTDA_FTDA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_FTDA_FTDA_MASK ) | \ + ( ( ( _val ) << MMCTRL_FTDA_FTDA_SHIFT ) & \ + MMCTRL_FTDA_FTDA_MASK ) ) +#define MMCTRL_FTDA_FTDA( _val ) \ + ( ( ( _val ) << MMCTRL_FTDA_FTDA_SHIFT ) & \ + MMCTRL_FTDA_FTDA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLFTDC FT diagnostic checkbits register (FTDC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_FTDC_CBD_SHIFT 24 +#define MMCTRL_FTDC_CBD_MASK 0xff000000U +#define MMCTRL_FTDC_CBD_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_FTDC_CBD_MASK ) >> \ + MMCTRL_FTDC_CBD_SHIFT ) +#define MMCTRL_FTDC_CBD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_FTDC_CBD_MASK ) | \ + ( ( ( _val ) << MMCTRL_FTDC_CBD_SHIFT ) & \ + MMCTRL_FTDC_CBD_MASK ) ) +#define MMCTRL_FTDC_CBD( _val ) \ + ( ( ( _val ) << MMCTRL_FTDC_CBD_SHIFT ) & \ + MMCTRL_FTDC_CBD_MASK ) + +#define MMCTRL_FTDC_CBC_SHIFT 16 +#define MMCTRL_FTDC_CBC_MASK 0xff0000U +#define MMCTRL_FTDC_CBC_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_FTDC_CBC_MASK ) >> \ + MMCTRL_FTDC_CBC_SHIFT ) +#define MMCTRL_FTDC_CBC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_FTDC_CBC_MASK ) | \ + ( ( ( _val ) << MMCTRL_FTDC_CBC_SHIFT ) & \ + MMCTRL_FTDC_CBC_MASK ) ) +#define MMCTRL_FTDC_CBC( _val ) \ + ( ( ( _val ) << MMCTRL_FTDC_CBC_SHIFT ) & \ + MMCTRL_FTDC_CBC_MASK ) + +#define MMCTRL_FTDC_CBB_SHIFT 8 +#define MMCTRL_FTDC_CBB_MASK 0xff00U +#define MMCTRL_FTDC_CBB_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_FTDC_CBB_MASK ) >> \ + MMCTRL_FTDC_CBB_SHIFT ) +#define MMCTRL_FTDC_CBB_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_FTDC_CBB_MASK ) | \ + ( ( ( _val ) << MMCTRL_FTDC_CBB_SHIFT ) & \ + MMCTRL_FTDC_CBB_MASK ) ) +#define MMCTRL_FTDC_CBB( _val ) \ + ( ( ( _val ) << MMCTRL_FTDC_CBB_SHIFT ) & \ + MMCTRL_FTDC_CBB_MASK ) + +#define MMCTRL_FTDC_CBA_SHIFT 0 +#define MMCTRL_FTDC_CBA_MASK 0xffU +#define MMCTRL_FTDC_CBA_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_FTDC_CBA_MASK ) >> \ + MMCTRL_FTDC_CBA_SHIFT ) +#define MMCTRL_FTDC_CBA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_FTDC_CBA_MASK ) | \ + ( ( ( _val ) << MMCTRL_FTDC_CBA_SHIFT ) & \ + MMCTRL_FTDC_CBA_MASK ) ) +#define MMCTRL_FTDC_CBA( _val ) \ + ( ( ( _val ) << MMCTRL_FTDC_CBA_SHIFT ) & \ + MMCTRL_FTDC_CBA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLFTDD FT diagnostic data register (FTDD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_FTDD_DATA_SHIFT 0 +#define MMCTRL_FTDD_DATA_MASK 0xffffffffU +#define MMCTRL_FTDD_DATA_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_FTDD_DATA_MASK ) >> \ + MMCTRL_FTDD_DATA_SHIFT ) +#define MMCTRL_FTDD_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_FTDD_DATA_MASK ) | \ + ( ( ( _val ) << MMCTRL_FTDD_DATA_SHIFT ) & \ + MMCTRL_FTDD_DATA_MASK ) ) +#define MMCTRL_FTDD_DATA( _val ) \ + ( ( ( _val ) << MMCTRL_FTDD_DATA_SHIFT ) & \ + MMCTRL_FTDD_DATA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLFTBND FT boundary address register (FTBND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_FTBND_FTBND_31_3_SHIFT 3 +#define MMCTRL_FTBND_FTBND_31_3_MASK 0xfffffff8U +#define MMCTRL_FTBND_FTBND_31_3_GET( _reg ) \ + ( ( ( _reg ) & MMCTRL_FTBND_FTBND_31_3_MASK ) >> \ + MMCTRL_FTBND_FTBND_31_3_SHIFT ) +#define MMCTRL_FTBND_FTBND_31_3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~MMCTRL_FTBND_FTBND_31_3_MASK ) | \ + ( ( ( _val ) << MMCTRL_FTBND_FTBND_31_3_SHIFT ) & \ + MMCTRL_FTBND_FTBND_31_3_MASK ) ) +#define MMCTRL_FTBND_FTBND_31_3( _val ) \ + ( ( ( _val ) << MMCTRL_FTBND_FTBND_31_3_SHIFT ) & \ + MMCTRL_FTBND_FTBND_31_3_MASK ) + +/** @} */ + +/** + * @brief This structure defines the MMCTRL register block memory map. + */ +typedef struct mmctrl { + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLSDCFG1. + */ + uint32_t sdcfg1; + + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLSDCFG2. + */ + uint32_t sdcfg2; + + uint32_t reserved_8_20[ 6 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLMUXCFG. + */ + uint32_t muxcfg; + + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLFTDA. + */ + uint32_t ftda; + + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLFTDC. + */ + uint32_t ftdc; + + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLFTDD. + */ + uint32_t ftdd; + + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLFTBND. + */ + uint32_t ftbnd; +} mmctrl; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_MMCTRL_REGS_H */ diff --git a/bsps/include/grlib/occan.h b/bsps/include/grlib/occan.h index 1112a3e8dc..ea851b3fad 100644 --- a/bsps/include/grlib/occan.h +++ b/bsps/include/grlib/occan.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup can @@ -8,9 +10,26 @@ * COPYRIGHT (c) 2007. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __OCCAN_DRIVER_H__ diff --git a/bsps/include/grlib/pcif.h b/bsps/include/grlib/pcif.h index 0221fcdd50..0875db86e7 100644 --- a/bsps/include/grlib/pcif.h +++ b/bsps/include/grlib/pcif.h @@ -1,3 +1,32 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * COPYRIGHT (c) 2015. + * Cobham Gaisler. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + #ifndef __PCIF_H__ #define __PCIF_H__ diff --git a/bsps/include/grlib/satcan.h b/bsps/include/grlib/satcan.h index ab9f5e0cd4..229b1fd099 100644 --- a/bsps/include/grlib/satcan.h +++ b/bsps/include/grlib/satcan.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * Header file for RTEMS SATCAN FPGA driver * * COPYRIGHT (c) 2009. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SATCAN_H__ diff --git a/bsps/include/grlib/spictrl-regs.h b/bsps/include/grlib/spictrl-regs.h new file mode 100644 index 0000000000..c70f7545b1 --- /dev/null +++ b/bsps/include/grlib/spictrl-regs.h @@ -0,0 +1,464 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBSPICTRL + * + * @brief This header file defines the SPICTRL register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/spictrl-header */ + +#ifndef _GRLIB_SPICTRL_REGS_H +#define _GRLIB_SPICTRL_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/spictrl */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRL SPICTRL + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the SPICTRL interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLCAP Capability register (CAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_CAP_SSSZ_SHIFT 24 +#define SPICTRL_CAP_SSSZ_MASK 0xff000000U +#define SPICTRL_CAP_SSSZ_GET( _reg ) \ + ( ( ( _reg ) & SPICTRL_CAP_SSSZ_MASK ) >> \ + SPICTRL_CAP_SSSZ_SHIFT ) +#define SPICTRL_CAP_SSSZ_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_CAP_SSSZ_MASK ) | \ + ( ( ( _val ) << SPICTRL_CAP_SSSZ_SHIFT ) & \ + SPICTRL_CAP_SSSZ_MASK ) ) +#define SPICTRL_CAP_SSSZ( _val ) \ + ( ( ( _val ) << SPICTRL_CAP_SSSZ_SHIFT ) & \ + SPICTRL_CAP_SSSZ_MASK ) + +#define SPICTRL_CAP_MAXWLEN_SHIFT 20 +#define SPICTRL_CAP_MAXWLEN_MASK 0xf00000U +#define SPICTRL_CAP_MAXWLEN_GET( _reg ) \ + ( ( ( _reg ) & SPICTRL_CAP_MAXWLEN_MASK ) >> \ + SPICTRL_CAP_MAXWLEN_SHIFT ) +#define SPICTRL_CAP_MAXWLEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_CAP_MAXWLEN_MASK ) | \ + ( ( ( _val ) << SPICTRL_CAP_MAXWLEN_SHIFT ) & \ + SPICTRL_CAP_MAXWLEN_MASK ) ) +#define SPICTRL_CAP_MAXWLEN( _val ) \ + ( ( ( _val ) << SPICTRL_CAP_MAXWLEN_SHIFT ) & \ + SPICTRL_CAP_MAXWLEN_MASK ) + +#define SPICTRL_CAP_TWEN 0x80000U + +#define SPICTRL_CAP_AMODE 0x40000U + +#define SPICTRL_CAP_ASELA 0x20000U + +#define SPICTRL_CAP_SSEN 0x10000U + +#define SPICTRL_CAP_FDEPTH_SHIFT 8 +#define SPICTRL_CAP_FDEPTH_MASK 0xff00U +#define SPICTRL_CAP_FDEPTH_GET( _reg ) \ + ( ( ( _reg ) & SPICTRL_CAP_FDEPTH_MASK ) >> \ + SPICTRL_CAP_FDEPTH_SHIFT ) +#define SPICTRL_CAP_FDEPTH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_CAP_FDEPTH_MASK ) | \ + ( ( ( _val ) << SPICTRL_CAP_FDEPTH_SHIFT ) & \ + SPICTRL_CAP_FDEPTH_MASK ) ) +#define SPICTRL_CAP_FDEPTH( _val ) \ + ( ( ( _val ) << SPICTRL_CAP_FDEPTH_SHIFT ) & \ + SPICTRL_CAP_FDEPTH_MASK ) + +#define SPICTRL_CAP_SR 0x80U + +#define SPICTRL_CAP_FT_SHIFT 5 +#define SPICTRL_CAP_FT_MASK 0x60U +#define SPICTRL_CAP_FT_GET( _reg ) \ + ( ( ( _reg ) & SPICTRL_CAP_FT_MASK ) >> \ + SPICTRL_CAP_FT_SHIFT ) +#define SPICTRL_CAP_FT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_CAP_FT_MASK ) | \ + ( ( ( _val ) << SPICTRL_CAP_FT_SHIFT ) & \ + SPICTRL_CAP_FT_MASK ) ) +#define SPICTRL_CAP_FT( _val ) \ + ( ( ( _val ) << SPICTRL_CAP_FT_SHIFT ) & \ + SPICTRL_CAP_FT_MASK ) + +#define SPICTRL_CAP_REV_SHIFT 0 +#define SPICTRL_CAP_REV_MASK 0x1fU +#define SPICTRL_CAP_REV_GET( _reg ) \ + ( ( ( _reg ) & SPICTRL_CAP_REV_MASK ) >> \ + SPICTRL_CAP_REV_SHIFT ) +#define SPICTRL_CAP_REV_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_CAP_REV_MASK ) | \ + ( ( ( _val ) << SPICTRL_CAP_REV_SHIFT ) & \ + SPICTRL_CAP_REV_MASK ) ) +#define SPICTRL_CAP_REV( _val ) \ + ( ( ( _val ) << SPICTRL_CAP_REV_SHIFT ) & \ + SPICTRL_CAP_REV_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLMODE Mode register (MODE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_MODE_LOOP 0x40000000U + +#define SPICTRL_MODE_CPOL 0x20000000U + +#define SPICTRL_MODE_CPHA 0x10000000U + +#define SPICTRL_MODE_DIV_16 0x8000000U + +#define SPICTRL_MODE_REV 0x4000000U + +#define SPICTRL_MODE_MX 0x2000000U + +#define SPICTRL_MODE_EN 0x1000000U + +#define SPICTRL_MODE_LEN_SHIFT 20 +#define SPICTRL_MODE_LEN_MASK 0xf00000U +#define SPICTRL_MODE_LEN_GET( _reg ) \ + ( ( ( _reg ) & SPICTRL_MODE_LEN_MASK ) >> \ + SPICTRL_MODE_LEN_SHIFT ) +#define SPICTRL_MODE_LEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_MODE_LEN_MASK ) | \ + ( ( ( _val ) << SPICTRL_MODE_LEN_SHIFT ) & \ + SPICTRL_MODE_LEN_MASK ) ) +#define SPICTRL_MODE_LEN( _val ) \ + ( ( ( _val ) << SPICTRL_MODE_LEN_SHIFT ) & \ + SPICTRL_MODE_LEN_MASK ) + +#define SPICTRL_MODE_PM_SHIFT 16 +#define SPICTRL_MODE_PM_MASK 0xf0000U +#define SPICTRL_MODE_PM_GET( _reg ) \ + ( ( ( _reg ) & SPICTRL_MODE_PM_MASK ) >> \ + SPICTRL_MODE_PM_SHIFT ) +#define SPICTRL_MODE_PM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_MODE_PM_MASK ) | \ + ( ( ( _val ) << SPICTRL_MODE_PM_SHIFT ) & \ + SPICTRL_MODE_PM_MASK ) ) +#define SPICTRL_MODE_PM( _val ) \ + ( ( ( _val ) << SPICTRL_MODE_PM_SHIFT ) & \ + SPICTRL_MODE_PM_MASK ) + +#define SPICTRL_MODE_TWEN 0x8000U + +#define SPICTRL_MODE_ASEL 0x4000U + +#define SPICTRL_MODE_FACT 0x2000U + +#define SPICTRL_MODE_OD 0x1000U + +#define SPICTRL_MODE_CG_SHIFT 7 +#define SPICTRL_MODE_CG_MASK 0xf80U +#define SPICTRL_MODE_CG_GET( _reg ) \ + ( ( ( _reg ) & SPICTRL_MODE_CG_MASK ) >> \ + SPICTRL_MODE_CG_SHIFT ) +#define SPICTRL_MODE_CG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_MODE_CG_MASK ) | \ + ( ( ( _val ) << SPICTRL_MODE_CG_SHIFT ) & \ + SPICTRL_MODE_CG_MASK ) ) +#define SPICTRL_MODE_CG( _val ) \ + ( ( ( _val ) << SPICTRL_MODE_CG_SHIFT ) & \ + SPICTRL_MODE_CG_MASK ) + +#define SPICTRL_MODE_ASELDEL_SHIFT 5 +#define SPICTRL_MODE_ASELDEL_MASK 0x60U +#define SPICTRL_MODE_ASELDEL_GET( _reg ) \ + ( ( ( _reg ) & SPICTRL_MODE_ASELDEL_MASK ) >> \ + SPICTRL_MODE_ASELDEL_SHIFT ) +#define SPICTRL_MODE_ASELDEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_MODE_ASELDEL_MASK ) | \ + ( ( ( _val ) << SPICTRL_MODE_ASELDEL_SHIFT ) & \ + SPICTRL_MODE_ASELDEL_MASK ) ) +#define SPICTRL_MODE_ASELDEL( _val ) \ + ( ( ( _val ) << SPICTRL_MODE_ASELDEL_SHIFT ) & \ + SPICTRL_MODE_ASELDEL_MASK ) + +#define SPICTRL_MODE_TAC 0x10U + +#define SPICTRL_MODE_TTO 0x8U + +#define SPICTRL_MODE_IGSEL 0x4U + +#define SPICTRL_MODE_CITE 0x2U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLEVENT Event register (EVENT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_EVENT_TIP 0x80000000U + +#define SPICTRL_EVENT_LT 0x4000U + +#define SPICTRL_EVENT_OV 0x1000U + +#define SPICTRL_EVENT_UN 0x800U + +#define SPICTRL_EVENT_MME 0x400U + +#define SPICTRL_EVENT_NE 0x200U + +#define SPICTRL_EVENT_NF 0x100U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLMASK Mask register (MASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_MASK_TIPE 0x80000000U + +#define SPICTRL_MASK_LTE 0x4000U + +#define SPICTRL_MASK_OVE 0x1000U + +#define SPICTRL_MASK_UNE 0x800U + +#define SPICTRL_MASK_MMEE 0x400U + +#define SPICTRL_MASK_NEEE 0x200U + +#define SPICTRL_MASK_NFE 0x100U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLCMD Command register (CMD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_CMD_LST 0x400000U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLTX Transmit register (TX) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_TX_TDATA_SHIFT 0 +#define SPICTRL_TX_TDATA_MASK 0xffffffffU +#define SPICTRL_TX_TDATA_GET( _reg ) \ + ( ( ( _reg ) & SPICTRL_TX_TDATA_MASK ) >> \ + SPICTRL_TX_TDATA_SHIFT ) +#define SPICTRL_TX_TDATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_TX_TDATA_MASK ) | \ + ( ( ( _val ) << SPICTRL_TX_TDATA_SHIFT ) & \ + SPICTRL_TX_TDATA_MASK ) ) +#define SPICTRL_TX_TDATA( _val ) \ + ( ( ( _val ) << SPICTRL_TX_TDATA_SHIFT ) & \ + SPICTRL_TX_TDATA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLRX Receive register (RX) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_RX_RDATA_SHIFT 0 +#define SPICTRL_RX_RDATA_MASK 0xffffffffU +#define SPICTRL_RX_RDATA_GET( _reg ) \ + ( ( ( _reg ) & SPICTRL_RX_RDATA_MASK ) >> \ + SPICTRL_RX_RDATA_SHIFT ) +#define SPICTRL_RX_RDATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_RX_RDATA_MASK ) | \ + ( ( ( _val ) << SPICTRL_RX_RDATA_SHIFT ) & \ + SPICTRL_RX_RDATA_MASK ) ) +#define SPICTRL_RX_RDATA( _val ) \ + ( ( ( _val ) << SPICTRL_RX_RDATA_SHIFT ) & \ + SPICTRL_RX_RDATA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLSLVSEL Slave select register (SLVSEL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_SLVSEL_SLVSEL_SHIFT 0 +#define SPICTRL_SLVSEL_SLVSEL_MASK 0x3U +#define SPICTRL_SLVSEL_SLVSEL_GET( _reg ) \ + ( ( ( _reg ) & SPICTRL_SLVSEL_SLVSEL_MASK ) >> \ + SPICTRL_SLVSEL_SLVSEL_SHIFT ) +#define SPICTRL_SLVSEL_SLVSEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_SLVSEL_SLVSEL_MASK ) | \ + ( ( ( _val ) << SPICTRL_SLVSEL_SLVSEL_SHIFT ) & \ + SPICTRL_SLVSEL_SLVSEL_MASK ) ) +#define SPICTRL_SLVSEL_SLVSEL( _val ) \ + ( ( ( _val ) << SPICTRL_SLVSEL_SLVSEL_SHIFT ) & \ + SPICTRL_SLVSEL_SLVSEL_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLASLVSEL \ + * Automatic slave select register (ASLVSEL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_ASLVSEL_ASLVSEL_SHIFT 0 +#define SPICTRL_ASLVSEL_ASLVSEL_MASK 0x3U +#define SPICTRL_ASLVSEL_ASLVSEL_GET( _reg ) \ + ( ( ( _reg ) & SPICTRL_ASLVSEL_ASLVSEL_MASK ) >> \ + SPICTRL_ASLVSEL_ASLVSEL_SHIFT ) +#define SPICTRL_ASLVSEL_ASLVSEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPICTRL_ASLVSEL_ASLVSEL_MASK ) | \ + ( ( ( _val ) << SPICTRL_ASLVSEL_ASLVSEL_SHIFT ) & \ + SPICTRL_ASLVSEL_ASLVSEL_MASK ) ) +#define SPICTRL_ASLVSEL_ASLVSEL( _val ) \ + ( ( ( _val ) << SPICTRL_ASLVSEL_ASLVSEL_SHIFT ) & \ + SPICTRL_ASLVSEL_ASLVSEL_MASK ) + +/** @} */ + +/** + * @brief This structure defines the SPICTRL register block memory map. + */ +typedef struct spictrl { + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLCAP. + */ + uint32_t cap; + + uint32_t reserved_4_20[ 7 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLMODE. + */ + uint32_t mode; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLEVENT. + */ + uint32_t event; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLMASK. + */ + uint32_t mask; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLCMD. + */ + uint32_t cmd; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLTX. + */ + uint32_t tx; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLRX. + */ + uint32_t rx; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLSLVSEL. + */ + uint32_t slvsel; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLASLVSEL. + */ + uint32_t aslvsel; +} spictrl; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_SPICTRL_REGS_H */ diff --git a/bsps/include/grlib/spictrl.h b/bsps/include/grlib/spictrl.h index 98922fbd30..a4232c3a6d 100644 --- a/bsps/include/grlib/spictrl.h +++ b/bsps/include/grlib/spictrl.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * SPICTRL SPI Driver interface. * * COPYRIGHT (c) 2009. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SPICTRL_H__ diff --git a/bsps/include/grlib/spwcuc.h b/bsps/include/grlib/spwcuc.h index e420367640..15d44a0a7e 100644 --- a/bsps/include/grlib/spwcuc.h +++ b/bsps/include/grlib/spwcuc.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* SPWCUC - SpaceWire - CCSDS unsegmented Code Transfer Protocol GRLIB core * register driver interface. * * COPYRIGHT (c) 2009. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SPWCUC_H__ diff --git a/bsps/include/grlib/spwpnp-regs.h b/bsps/include/grlib/spwpnp-regs.h new file mode 100644 index 0000000000..00c688bc55 --- /dev/null +++ b/bsps/include/grlib/spwpnp-regs.h @@ -0,0 +1,553 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBSPWPNP + * + * @brief This header file defines the SPWPNP register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/spwpnp-header */ + +#ifndef _GRLIB_SPWPNP_REGS_H +#define _GRLIB_SPWPNP_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/spwpnp */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNP SpaceWire Plug-and-Play + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the SpaceWire Plug-and-Play interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPVEND \ + * SpaceWire Plug-and-Play - Device Vendor and Product ID (PNPVEND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPVEND_VEND_SHIFT 16 +#define SPWPNP_PNPVEND_VEND_MASK 0xffff0000U +#define SPWPNP_PNPVEND_VEND_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPVEND_VEND_MASK ) >> \ + SPWPNP_PNPVEND_VEND_SHIFT ) +#define SPWPNP_PNPVEND_VEND_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPVEND_VEND_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPVEND_VEND_SHIFT ) & \ + SPWPNP_PNPVEND_VEND_MASK ) ) +#define SPWPNP_PNPVEND_VEND( _val ) \ + ( ( ( _val ) << SPWPNP_PNPVEND_VEND_SHIFT ) & \ + SPWPNP_PNPVEND_VEND_MASK ) + +#define SPWPNP_PNPVEND_PROD_SHIFT 0 +#define SPWPNP_PNPVEND_PROD_MASK 0xffffU +#define SPWPNP_PNPVEND_PROD_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPVEND_PROD_MASK ) >> \ + SPWPNP_PNPVEND_PROD_SHIFT ) +#define SPWPNP_PNPVEND_PROD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPVEND_PROD_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPVEND_PROD_SHIFT ) & \ + SPWPNP_PNPVEND_PROD_MASK ) ) +#define SPWPNP_PNPVEND_PROD( _val ) \ + ( ( ( _val ) << SPWPNP_PNPVEND_PROD_SHIFT ) & \ + SPWPNP_PNPVEND_PROD_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPVER \ + * SpaceWire Plug-and-Play - Version (PNPVER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPVER_MAJOR_SHIFT 24 +#define SPWPNP_PNPVER_MAJOR_MASK 0xff000000U +#define SPWPNP_PNPVER_MAJOR_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPVER_MAJOR_MASK ) >> \ + SPWPNP_PNPVER_MAJOR_SHIFT ) +#define SPWPNP_PNPVER_MAJOR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPVER_MAJOR_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPVER_MAJOR_SHIFT ) & \ + SPWPNP_PNPVER_MAJOR_MASK ) ) +#define SPWPNP_PNPVER_MAJOR( _val ) \ + ( ( ( _val ) << SPWPNP_PNPVER_MAJOR_SHIFT ) & \ + SPWPNP_PNPVER_MAJOR_MASK ) + +#define SPWPNP_PNPVER_MINOR_SHIFT 16 +#define SPWPNP_PNPVER_MINOR_MASK 0xff0000U +#define SPWPNP_PNPVER_MINOR_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPVER_MINOR_MASK ) >> \ + SPWPNP_PNPVER_MINOR_SHIFT ) +#define SPWPNP_PNPVER_MINOR_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPVER_MINOR_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPVER_MINOR_SHIFT ) & \ + SPWPNP_PNPVER_MINOR_MASK ) ) +#define SPWPNP_PNPVER_MINOR( _val ) \ + ( ( ( _val ) << SPWPNP_PNPVER_MINOR_SHIFT ) & \ + SPWPNP_PNPVER_MINOR_MASK ) + +#define SPWPNP_PNPVER_PATCH_SHIFT 8 +#define SPWPNP_PNPVER_PATCH_MASK 0xff00U +#define SPWPNP_PNPVER_PATCH_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPVER_PATCH_MASK ) >> \ + SPWPNP_PNPVER_PATCH_SHIFT ) +#define SPWPNP_PNPVER_PATCH_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPVER_PATCH_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPVER_PATCH_SHIFT ) & \ + SPWPNP_PNPVER_PATCH_MASK ) ) +#define SPWPNP_PNPVER_PATCH( _val ) \ + ( ( ( _val ) << SPWPNP_PNPVER_PATCH_SHIFT ) & \ + SPWPNP_PNPVER_PATCH_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPDEVSTS \ + * SpaceWire Plug-and-Play - Device Status (PNPDEVSTS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPDEVSTS_STATUS_SHIFT 0 +#define SPWPNP_PNPDEVSTS_STATUS_MASK 0xffU +#define SPWPNP_PNPDEVSTS_STATUS_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPDEVSTS_STATUS_MASK ) >> \ + SPWPNP_PNPDEVSTS_STATUS_SHIFT ) +#define SPWPNP_PNPDEVSTS_STATUS_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPDEVSTS_STATUS_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPDEVSTS_STATUS_SHIFT ) & \ + SPWPNP_PNPDEVSTS_STATUS_MASK ) ) +#define SPWPNP_PNPDEVSTS_STATUS( _val ) \ + ( ( ( _val ) << SPWPNP_PNPDEVSTS_STATUS_SHIFT ) & \ + SPWPNP_PNPDEVSTS_STATUS_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPACTLNK \ + * SpaceWire Plug-and-Play - Active Links (PNPACTLNK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPACTLNK_ACTIVE_SHIFT 1 +#define SPWPNP_PNPACTLNK_ACTIVE_MASK 0xfffffffeU +#define SPWPNP_PNPACTLNK_ACTIVE_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPACTLNK_ACTIVE_MASK ) >> \ + SPWPNP_PNPACTLNK_ACTIVE_SHIFT ) +#define SPWPNP_PNPACTLNK_ACTIVE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPACTLNK_ACTIVE_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPACTLNK_ACTIVE_SHIFT ) & \ + SPWPNP_PNPACTLNK_ACTIVE_MASK ) ) +#define SPWPNP_PNPACTLNK_ACTIVE( _val ) \ + ( ( ( _val ) << SPWPNP_PNPACTLNK_ACTIVE_SHIFT ) & \ + SPWPNP_PNPACTLNK_ACTIVE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPOA0 \ + * SpaceWire Plug-and-Play - Owner Address 0 (PNPOA0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPOA0_RA_SHIFT 0 +#define SPWPNP_PNPOA0_RA_MASK 0xffffffffU +#define SPWPNP_PNPOA0_RA_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPOA0_RA_MASK ) >> \ + SPWPNP_PNPOA0_RA_SHIFT ) +#define SPWPNP_PNPOA0_RA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPOA0_RA_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPOA0_RA_SHIFT ) & \ + SPWPNP_PNPOA0_RA_MASK ) ) +#define SPWPNP_PNPOA0_RA( _val ) \ + ( ( ( _val ) << SPWPNP_PNPOA0_RA_SHIFT ) & \ + SPWPNP_PNPOA0_RA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPOA1 \ + * SpaceWire Plug-and-Play - Owner Address 1 (PNPOA1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPOA1_RA_SHIFT 0 +#define SPWPNP_PNPOA1_RA_MASK 0xffffffffU +#define SPWPNP_PNPOA1_RA_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPOA1_RA_MASK ) >> \ + SPWPNP_PNPOA1_RA_SHIFT ) +#define SPWPNP_PNPOA1_RA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPOA1_RA_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPOA1_RA_SHIFT ) & \ + SPWPNP_PNPOA1_RA_MASK ) ) +#define SPWPNP_PNPOA1_RA( _val ) \ + ( ( ( _val ) << SPWPNP_PNPOA1_RA_SHIFT ) & \ + SPWPNP_PNPOA1_RA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPOA2 \ + * SpaceWire Plug-and-Play - Owner Address 2 (PNPOA2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPOA2_RA_SHIFT 0 +#define SPWPNP_PNPOA2_RA_MASK 0xffffffffU +#define SPWPNP_PNPOA2_RA_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPOA2_RA_MASK ) >> \ + SPWPNP_PNPOA2_RA_SHIFT ) +#define SPWPNP_PNPOA2_RA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPOA2_RA_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPOA2_RA_SHIFT ) & \ + SPWPNP_PNPOA2_RA_MASK ) ) +#define SPWPNP_PNPOA2_RA( _val ) \ + ( ( ( _val ) << SPWPNP_PNPOA2_RA_SHIFT ) & \ + SPWPNP_PNPOA2_RA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPDEVID \ + * SpaceWire Plug-and-Play - Device ID (PNPDEVID) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPDEVID_DID_SHIFT 0 +#define SPWPNP_PNPDEVID_DID_MASK 0xffffffffU +#define SPWPNP_PNPDEVID_DID_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPDEVID_DID_MASK ) >> \ + SPWPNP_PNPDEVID_DID_SHIFT ) +#define SPWPNP_PNPDEVID_DID_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPDEVID_DID_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPDEVID_DID_SHIFT ) & \ + SPWPNP_PNPDEVID_DID_MASK ) ) +#define SPWPNP_PNPDEVID_DID( _val ) \ + ( ( ( _val ) << SPWPNP_PNPDEVID_DID_SHIFT ) & \ + SPWPNP_PNPDEVID_DID_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPUVEND \ + * SpaceWire Plug-and-Play - Unit Vendor and Product ID (PNPUVEND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPUVEND_VEND_SHIFT 16 +#define SPWPNP_PNPUVEND_VEND_MASK 0xffff0000U +#define SPWPNP_PNPUVEND_VEND_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPUVEND_VEND_MASK ) >> \ + SPWPNP_PNPUVEND_VEND_SHIFT ) +#define SPWPNP_PNPUVEND_VEND_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPUVEND_VEND_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPUVEND_VEND_SHIFT ) & \ + SPWPNP_PNPUVEND_VEND_MASK ) ) +#define SPWPNP_PNPUVEND_VEND( _val ) \ + ( ( ( _val ) << SPWPNP_PNPUVEND_VEND_SHIFT ) & \ + SPWPNP_PNPUVEND_VEND_MASK ) + +#define SPWPNP_PNPUVEND_PROD_SHIFT 0 +#define SPWPNP_PNPUVEND_PROD_MASK 0xffffU +#define SPWPNP_PNPUVEND_PROD_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPUVEND_PROD_MASK ) >> \ + SPWPNP_PNPUVEND_PROD_SHIFT ) +#define SPWPNP_PNPUVEND_PROD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPUVEND_PROD_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPUVEND_PROD_SHIFT ) & \ + SPWPNP_PNPUVEND_PROD_MASK ) ) +#define SPWPNP_PNPUVEND_PROD( _val ) \ + ( ( ( _val ) << SPWPNP_PNPUVEND_PROD_SHIFT ) & \ + SPWPNP_PNPUVEND_PROD_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPUSN \ + * SpaceWire Plug-and-Play - Unit Serial Number (PNPUSN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPUSN_USN_SHIFT 0 +#define SPWPNP_PNPUSN_USN_MASK 0xffffffffU +#define SPWPNP_PNPUSN_USN_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPUSN_USN_MASK ) >> \ + SPWPNP_PNPUSN_USN_SHIFT ) +#define SPWPNP_PNPUSN_USN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPUSN_USN_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPUSN_USN_SHIFT ) & \ + SPWPNP_PNPUSN_USN_MASK ) ) +#define SPWPNP_PNPUSN_USN( _val ) \ + ( ( ( _val ) << SPWPNP_PNPUSN_USN_SHIFT ) & \ + SPWPNP_PNPUSN_USN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPVSTRL \ + * SpaceWire Plug-and-Play - Vendor String Length (PNPVSTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPVSTRL_LEN_SHIFT 0 +#define SPWPNP_PNPVSTRL_LEN_MASK 0x7fffU +#define SPWPNP_PNPVSTRL_LEN_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPVSTRL_LEN_MASK ) >> \ + SPWPNP_PNPVSTRL_LEN_SHIFT ) +#define SPWPNP_PNPVSTRL_LEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPVSTRL_LEN_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPVSTRL_LEN_SHIFT ) & \ + SPWPNP_PNPVSTRL_LEN_MASK ) ) +#define SPWPNP_PNPVSTRL_LEN( _val ) \ + ( ( ( _val ) << SPWPNP_PNPVSTRL_LEN_SHIFT ) & \ + SPWPNP_PNPVSTRL_LEN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPPSTRL \ + * SpaceWire Plug-and-Play - Product String Length (PNPPSTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPPSTRL_LEN_SHIFT 0 +#define SPWPNP_PNPPSTRL_LEN_MASK 0x7fffU +#define SPWPNP_PNPPSTRL_LEN_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPPSTRL_LEN_MASK ) >> \ + SPWPNP_PNPPSTRL_LEN_SHIFT ) +#define SPWPNP_PNPPSTRL_LEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPPSTRL_LEN_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPPSTRL_LEN_SHIFT ) & \ + SPWPNP_PNPPSTRL_LEN_MASK ) ) +#define SPWPNP_PNPPSTRL_LEN( _val ) \ + ( ( ( _val ) << SPWPNP_PNPPSTRL_LEN_SHIFT ) & \ + SPWPNP_PNPPSTRL_LEN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPPCNT \ + * SpaceWire Plug-and-Play - Protocol Count (PNPPCNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPPCNT_PC_SHIFT 0 +#define SPWPNP_PNPPCNT_PC_MASK 0x1fU +#define SPWPNP_PNPPCNT_PC_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPPCNT_PC_MASK ) >> \ + SPWPNP_PNPPCNT_PC_SHIFT ) +#define SPWPNP_PNPPCNT_PC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPPCNT_PC_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPPCNT_PC_SHIFT ) & \ + SPWPNP_PNPPCNT_PC_MASK ) ) +#define SPWPNP_PNPPCNT_PC( _val ) \ + ( ( ( _val ) << SPWPNP_PNPPCNT_PC_SHIFT ) & \ + SPWPNP_PNPPCNT_PC_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPACNT \ + * SpaceWire Plug-and-Play - Application Count (PNPACNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPACNT_AC_SHIFT 0 +#define SPWPNP_PNPACNT_AC_MASK 0xffU +#define SPWPNP_PNPACNT_AC_GET( _reg ) \ + ( ( ( _reg ) & SPWPNP_PNPACNT_AC_MASK ) >> \ + SPWPNP_PNPACNT_AC_SHIFT ) +#define SPWPNP_PNPACNT_AC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWPNP_PNPACNT_AC_MASK ) | \ + ( ( ( _val ) << SPWPNP_PNPACNT_AC_SHIFT ) & \ + SPWPNP_PNPACNT_AC_MASK ) ) +#define SPWPNP_PNPACNT_AC( _val ) \ + ( ( ( _val ) << SPWPNP_PNPACNT_AC_SHIFT ) & \ + SPWPNP_PNPACNT_AC_MASK ) + +/** @} */ + +/** + * @brief This set of defines the SpaceWire Plug-and-Play address map. + */ +typedef struct spwpnp { + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPVEND. + */ + uint32_t pnpvend; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPVER. + */ + uint32_t pnpver; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPDEVSTS. + */ + uint32_t pnpdevsts; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPACTLNK. + */ + uint32_t pnpactlnk; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPOA0. + */ + uint32_t pnpoa0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPOA1. + */ + uint32_t pnpoa1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPOA2. + */ + uint32_t pnpoa2; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPDEVID. + */ + uint32_t pnpdevid; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPUVEND. + */ + uint32_t pnpuvend; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPUSN. + */ + uint32_t pnpusn; + + uint16_t reserved_e_4000[ 8185 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPVSTRL. + */ + uint32_t pnpvstrl; + + uint32_t reserved_4004_6000[ 2047 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPPSTRL. + */ + uint32_t pnppstrl; + + uint32_t reserved_6004_8000[ 2047 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPPCNT. + */ + uint32_t pnppcnt; + + uint32_t reserved_8004_c000[ 4095 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPACNT. + */ + uint32_t pnpacnt; +} spwpnp; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_SPWPNP_REGS_H */ diff --git a/bsps/include/grlib/spwtdp-regs.h b/bsps/include/grlib/spwtdp-regs.h new file mode 100644 index 0000000000..2e951e4544 --- /dev/null +++ b/bsps/include/grlib/spwtdp-regs.h @@ -0,0 +1,1268 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBSPWTDP + * + * @brief This header file defines the SPWTDP register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/spwtdp-header */ + +#ifndef _GRLIB_SPWTDP_REGS_H +#define _GRLIB_SPWTDP_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/spwtdp */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDP SPWTDP + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the SPWTDP interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCONF0 Configuration 0 (CONF0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CONF0_JE 0x1000000U + +#define SPWTDP_CONF0_ST 0x200000U + +#define SPWTDP_CONF0_EP 0x100000U + +#define SPWTDP_CONF0_ET 0x80000U + +#define SPWTDP_CONF0_SP 0x40000U + +#define SPWTDP_CONF0_SE 0x20000U + +#define SPWTDP_CONF0_LE 0x10000U + +#define SPWTDP_CONF0_AE 0x8000U + +#define SPWTDP_CONF0_MAPPING_SHIFT 8 +#define SPWTDP_CONF0_MAPPING_MASK 0x1f00U +#define SPWTDP_CONF0_MAPPING_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_CONF0_MAPPING_MASK ) >> \ + SPWTDP_CONF0_MAPPING_SHIFT ) +#define SPWTDP_CONF0_MAPPING_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_CONF0_MAPPING_MASK ) | \ + ( ( ( _val ) << SPWTDP_CONF0_MAPPING_SHIFT ) & \ + SPWTDP_CONF0_MAPPING_MASK ) ) +#define SPWTDP_CONF0_MAPPING( _val ) \ + ( ( ( _val ) << SPWTDP_CONF0_MAPPING_SHIFT ) & \ + SPWTDP_CONF0_MAPPING_MASK ) + +#define SPWTDP_CONF0_TD 0x80U + +#define SPWTDP_CONF0_MU 0x40U + +#define SPWTDP_CONF0_SEL_SHIFT 4 +#define SPWTDP_CONF0_SEL_MASK 0x30U +#define SPWTDP_CONF0_SEL_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_CONF0_SEL_MASK ) >> \ + SPWTDP_CONF0_SEL_SHIFT ) +#define SPWTDP_CONF0_SEL_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_CONF0_SEL_MASK ) | \ + ( ( ( _val ) << SPWTDP_CONF0_SEL_SHIFT ) & \ + SPWTDP_CONF0_SEL_MASK ) ) +#define SPWTDP_CONF0_SEL( _val ) \ + ( ( ( _val ) << SPWTDP_CONF0_SEL_SHIFT ) & \ + SPWTDP_CONF0_SEL_MASK ) + +#define SPWTDP_CONF0_ME 0x8U + +#define SPWTDP_CONF0_RE 0x4U + +#define SPWTDP_CONF0_TE 0x2U + +#define SPWTDP_CONF0_RS 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCONF3 Configuration 3 (CONF3) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CONF3_STM_SHIFT 16 +#define SPWTDP_CONF3_STM_MASK 0x3f0000U +#define SPWTDP_CONF3_STM_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_CONF3_STM_MASK ) >> \ + SPWTDP_CONF3_STM_SHIFT ) +#define SPWTDP_CONF3_STM_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_CONF3_STM_MASK ) | \ + ( ( ( _val ) << SPWTDP_CONF3_STM_SHIFT ) & \ + SPWTDP_CONF3_STM_MASK ) ) +#define SPWTDP_CONF3_STM( _val ) \ + ( ( ( _val ) << SPWTDP_CONF3_STM_SHIFT ) & \ + SPWTDP_CONF3_STM_MASK ) + +#define SPWTDP_CONF3_DI64R 0x2000U + +#define SPWTDP_CONF3_DI64T 0x1000U + +#define SPWTDP_CONF3_DI64 0x800U + +#define SPWTDP_CONF3_DI 0x400U + +#define SPWTDP_CONF3_INRX_SHIFT 5 +#define SPWTDP_CONF3_INRX_MASK 0x3e0U +#define SPWTDP_CONF3_INRX_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_CONF3_INRX_MASK ) >> \ + SPWTDP_CONF3_INRX_SHIFT ) +#define SPWTDP_CONF3_INRX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_CONF3_INRX_MASK ) | \ + ( ( ( _val ) << SPWTDP_CONF3_INRX_SHIFT ) & \ + SPWTDP_CONF3_INRX_MASK ) ) +#define SPWTDP_CONF3_INRX( _val ) \ + ( ( ( _val ) << SPWTDP_CONF3_INRX_SHIFT ) & \ + SPWTDP_CONF3_INRX_MASK ) + +#define SPWTDP_CONF3_INTX_SHIFT 0 +#define SPWTDP_CONF3_INTX_MASK 0x1fU +#define SPWTDP_CONF3_INTX_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_CONF3_INTX_MASK ) >> \ + SPWTDP_CONF3_INTX_SHIFT ) +#define SPWTDP_CONF3_INTX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_CONF3_INTX_MASK ) | \ + ( ( ( _val ) << SPWTDP_CONF3_INTX_SHIFT ) & \ + SPWTDP_CONF3_INTX_MASK ) ) +#define SPWTDP_CONF3_INTX( _val ) \ + ( ( ( _val ) << SPWTDP_CONF3_INTX_SHIFT ) & \ + SPWTDP_CONF3_INTX_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCTRL Control (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CTRL_NC 0x80000000U + +#define SPWTDP_CTRL_IS 0x40000000U + +#define SPWTDP_CTRL_SPWTC_SHIFT 16 +#define SPWTDP_CTRL_SPWTC_MASK 0xff0000U +#define SPWTDP_CTRL_SPWTC_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_CTRL_SPWTC_MASK ) >> \ + SPWTDP_CTRL_SPWTC_SHIFT ) +#define SPWTDP_CTRL_SPWTC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_CTRL_SPWTC_MASK ) | \ + ( ( ( _val ) << SPWTDP_CTRL_SPWTC_SHIFT ) & \ + SPWTDP_CTRL_SPWTC_MASK ) ) +#define SPWTDP_CTRL_SPWTC( _val ) \ + ( ( ( _val ) << SPWTDP_CTRL_SPWTC_SHIFT ) & \ + SPWTDP_CTRL_SPWTC_MASK ) + +#define SPWTDP_CTRL_CPF_SHIFT 0 +#define SPWTDP_CTRL_CPF_MASK 0xffffU +#define SPWTDP_CTRL_CPF_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_CTRL_CPF_MASK ) >> \ + SPWTDP_CTRL_CPF_SHIFT ) +#define SPWTDP_CTRL_CPF_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_CTRL_CPF_MASK ) | \ + ( ( ( _val ) << SPWTDP_CTRL_CPF_SHIFT ) & \ + SPWTDP_CTRL_CPF_MASK ) ) +#define SPWTDP_CTRL_CPF( _val ) \ + ( ( ( _val ) << SPWTDP_CTRL_CPF_SHIFT ) & \ + SPWTDP_CTRL_CPF_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCET0 Command Elapsed Time 0 (CET0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CET0_CET0_SHIFT 0 +#define SPWTDP_CET0_CET0_MASK 0xffffffffU +#define SPWTDP_CET0_CET0_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_CET0_CET0_MASK ) >> \ + SPWTDP_CET0_CET0_SHIFT ) +#define SPWTDP_CET0_CET0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_CET0_CET0_MASK ) | \ + ( ( ( _val ) << SPWTDP_CET0_CET0_SHIFT ) & \ + SPWTDP_CET0_CET0_MASK ) ) +#define SPWTDP_CET0_CET0( _val ) \ + ( ( ( _val ) << SPWTDP_CET0_CET0_SHIFT ) & \ + SPWTDP_CET0_CET0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCET1 Command Elapsed Time 1 (CET1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CET1_CET1_SHIFT 0 +#define SPWTDP_CET1_CET1_MASK 0xffffffffU +#define SPWTDP_CET1_CET1_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_CET1_CET1_MASK ) >> \ + SPWTDP_CET1_CET1_SHIFT ) +#define SPWTDP_CET1_CET1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_CET1_CET1_MASK ) | \ + ( ( ( _val ) << SPWTDP_CET1_CET1_SHIFT ) & \ + SPWTDP_CET1_CET1_MASK ) ) +#define SPWTDP_CET1_CET1( _val ) \ + ( ( ( _val ) << SPWTDP_CET1_CET1_SHIFT ) & \ + SPWTDP_CET1_CET1_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCET2 Command Elapsed Time 2 (CET2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CET2_CET2_SHIFT 0 +#define SPWTDP_CET2_CET2_MASK 0xffffffffU +#define SPWTDP_CET2_CET2_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_CET2_CET2_MASK ) >> \ + SPWTDP_CET2_CET2_SHIFT ) +#define SPWTDP_CET2_CET2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_CET2_CET2_MASK ) | \ + ( ( ( _val ) << SPWTDP_CET2_CET2_SHIFT ) & \ + SPWTDP_CET2_CET2_MASK ) ) +#define SPWTDP_CET2_CET2( _val ) \ + ( ( ( _val ) << SPWTDP_CET2_CET2_SHIFT ) & \ + SPWTDP_CET2_CET2_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCET3 Command Elapsed Time 3 (CET3) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CET3_CET3_SHIFT 0 +#define SPWTDP_CET3_CET3_MASK 0xffffffffU +#define SPWTDP_CET3_CET3_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_CET3_CET3_MASK ) >> \ + SPWTDP_CET3_CET3_SHIFT ) +#define SPWTDP_CET3_CET3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_CET3_CET3_MASK ) | \ + ( ( ( _val ) << SPWTDP_CET3_CET3_SHIFT ) & \ + SPWTDP_CET3_CET3_MASK ) ) +#define SPWTDP_CET3_CET3( _val ) \ + ( ( ( _val ) << SPWTDP_CET3_CET3_SHIFT ) & \ + SPWTDP_CET3_CET3_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCET4 Command Elapsed Time 4 (CET4) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CET4_CET4_SHIFT 24 +#define SPWTDP_CET4_CET4_MASK 0xff000000U +#define SPWTDP_CET4_CET4_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_CET4_CET4_MASK ) >> \ + SPWTDP_CET4_CET4_SHIFT ) +#define SPWTDP_CET4_CET4_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_CET4_CET4_MASK ) | \ + ( ( ( _val ) << SPWTDP_CET4_CET4_SHIFT ) & \ + SPWTDP_CET4_CET4_MASK ) ) +#define SPWTDP_CET4_CET4( _val ) \ + ( ( ( _val ) << SPWTDP_CET4_CET4_SHIFT ) & \ + SPWTDP_CET4_CET4_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDPF Datation Preamble Field (DPF) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DPF_DPF_SHIFT 0 +#define SPWTDP_DPF_DPF_MASK 0xffffU +#define SPWTDP_DPF_DPF_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_DPF_DPF_MASK ) >> \ + SPWTDP_DPF_DPF_SHIFT ) +#define SPWTDP_DPF_DPF_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_DPF_DPF_MASK ) | \ + ( ( ( _val ) << SPWTDP_DPF_DPF_SHIFT ) & \ + SPWTDP_DPF_DPF_MASK ) ) +#define SPWTDP_DPF_DPF( _val ) \ + ( ( ( _val ) << SPWTDP_DPF_DPF_SHIFT ) & \ + SPWTDP_DPF_DPF_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDET0 Datation Elapsed Time 0 (DET0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DET0_DET0_SHIFT 0 +#define SPWTDP_DET0_DET0_MASK 0xffffffffU +#define SPWTDP_DET0_DET0_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_DET0_DET0_MASK ) >> \ + SPWTDP_DET0_DET0_SHIFT ) +#define SPWTDP_DET0_DET0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_DET0_DET0_MASK ) | \ + ( ( ( _val ) << SPWTDP_DET0_DET0_SHIFT ) & \ + SPWTDP_DET0_DET0_MASK ) ) +#define SPWTDP_DET0_DET0( _val ) \ + ( ( ( _val ) << SPWTDP_DET0_DET0_SHIFT ) & \ + SPWTDP_DET0_DET0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDET1 Datation Elapsed Time 1 (DET1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DET1_DET1_SHIFT 0 +#define SPWTDP_DET1_DET1_MASK 0xffffffffU +#define SPWTDP_DET1_DET1_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_DET1_DET1_MASK ) >> \ + SPWTDP_DET1_DET1_SHIFT ) +#define SPWTDP_DET1_DET1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_DET1_DET1_MASK ) | \ + ( ( ( _val ) << SPWTDP_DET1_DET1_SHIFT ) & \ + SPWTDP_DET1_DET1_MASK ) ) +#define SPWTDP_DET1_DET1( _val ) \ + ( ( ( _val ) << SPWTDP_DET1_DET1_SHIFT ) & \ + SPWTDP_DET1_DET1_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDET2 Datation Elapsed Time 2 (DET2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DET2_DET2_SHIFT 0 +#define SPWTDP_DET2_DET2_MASK 0xffffffffU +#define SPWTDP_DET2_DET2_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_DET2_DET2_MASK ) >> \ + SPWTDP_DET2_DET2_SHIFT ) +#define SPWTDP_DET2_DET2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_DET2_DET2_MASK ) | \ + ( ( ( _val ) << SPWTDP_DET2_DET2_SHIFT ) & \ + SPWTDP_DET2_DET2_MASK ) ) +#define SPWTDP_DET2_DET2( _val ) \ + ( ( ( _val ) << SPWTDP_DET2_DET2_SHIFT ) & \ + SPWTDP_DET2_DET2_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDET3 Datation Elapsed Time 3 (DET3) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DET3_DET3_SHIFT 0 +#define SPWTDP_DET3_DET3_MASK 0xffffffffU +#define SPWTDP_DET3_DET3_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_DET3_DET3_MASK ) >> \ + SPWTDP_DET3_DET3_SHIFT ) +#define SPWTDP_DET3_DET3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_DET3_DET3_MASK ) | \ + ( ( ( _val ) << SPWTDP_DET3_DET3_SHIFT ) & \ + SPWTDP_DET3_DET3_MASK ) ) +#define SPWTDP_DET3_DET3( _val ) \ + ( ( ( _val ) << SPWTDP_DET3_DET3_SHIFT ) & \ + SPWTDP_DET3_DET3_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDET4 Datation Elapsed Time 4 (DET4) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DET4_DET4_SHIFT 24 +#define SPWTDP_DET4_DET4_MASK 0xff000000U +#define SPWTDP_DET4_DET4_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_DET4_DET4_MASK ) >> \ + SPWTDP_DET4_DET4_SHIFT ) +#define SPWTDP_DET4_DET4_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_DET4_DET4_MASK ) | \ + ( ( ( _val ) << SPWTDP_DET4_DET4_SHIFT ) & \ + SPWTDP_DET4_DET4_MASK ) ) +#define SPWTDP_DET4_DET4( _val ) \ + ( ( ( _val ) << SPWTDP_DET4_DET4_SHIFT ) & \ + SPWTDP_DET4_DET4_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTRPFRX Time-Stamp Preamble Field Rx (TRPFRX) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TRPFRX_TRPF_SHIFT 0 +#define SPWTDP_TRPFRX_TRPF_MASK 0xffffU +#define SPWTDP_TRPFRX_TRPF_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_TRPFRX_TRPF_MASK ) >> \ + SPWTDP_TRPFRX_TRPF_SHIFT ) +#define SPWTDP_TRPFRX_TRPF_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_TRPFRX_TRPF_MASK ) | \ + ( ( ( _val ) << SPWTDP_TRPFRX_TRPF_SHIFT ) & \ + SPWTDP_TRPFRX_TRPF_MASK ) ) +#define SPWTDP_TRPFRX_TRPF( _val ) \ + ( ( ( _val ) << SPWTDP_TRPFRX_TRPF_SHIFT ) & \ + SPWTDP_TRPFRX_TRPF_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTR0 Time Stamp Elapsed Time 0 Rx (TR0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TR0_TR0_SHIFT 0 +#define SPWTDP_TR0_TR0_MASK 0xffffffffU +#define SPWTDP_TR0_TR0_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_TR0_TR0_MASK ) >> \ + SPWTDP_TR0_TR0_SHIFT ) +#define SPWTDP_TR0_TR0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_TR0_TR0_MASK ) | \ + ( ( ( _val ) << SPWTDP_TR0_TR0_SHIFT ) & \ + SPWTDP_TR0_TR0_MASK ) ) +#define SPWTDP_TR0_TR0( _val ) \ + ( ( ( _val ) << SPWTDP_TR0_TR0_SHIFT ) & \ + SPWTDP_TR0_TR0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTR1 Time Stamp Elapsed Time 1 Rx (TR1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TR1_TR1_SHIFT 0 +#define SPWTDP_TR1_TR1_MASK 0xffffffffU +#define SPWTDP_TR1_TR1_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_TR1_TR1_MASK ) >> \ + SPWTDP_TR1_TR1_SHIFT ) +#define SPWTDP_TR1_TR1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_TR1_TR1_MASK ) | \ + ( ( ( _val ) << SPWTDP_TR1_TR1_SHIFT ) & \ + SPWTDP_TR1_TR1_MASK ) ) +#define SPWTDP_TR1_TR1( _val ) \ + ( ( ( _val ) << SPWTDP_TR1_TR1_SHIFT ) & \ + SPWTDP_TR1_TR1_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTR2 Time Stamp Elapsed Time 2 Rx (TR2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TR2_TR2_SHIFT 0 +#define SPWTDP_TR2_TR2_MASK 0xffffffffU +#define SPWTDP_TR2_TR2_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_TR2_TR2_MASK ) >> \ + SPWTDP_TR2_TR2_SHIFT ) +#define SPWTDP_TR2_TR2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_TR2_TR2_MASK ) | \ + ( ( ( _val ) << SPWTDP_TR2_TR2_SHIFT ) & \ + SPWTDP_TR2_TR2_MASK ) ) +#define SPWTDP_TR2_TR2( _val ) \ + ( ( ( _val ) << SPWTDP_TR2_TR2_SHIFT ) & \ + SPWTDP_TR2_TR2_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTR3 Time Stamp Elapsed Time 3 Rx (TR3) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TR3_TR3_SHIFT 0 +#define SPWTDP_TR3_TR3_MASK 0xffffffffU +#define SPWTDP_TR3_TR3_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_TR3_TR3_MASK ) >> \ + SPWTDP_TR3_TR3_SHIFT ) +#define SPWTDP_TR3_TR3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_TR3_TR3_MASK ) | \ + ( ( ( _val ) << SPWTDP_TR3_TR3_SHIFT ) & \ + SPWTDP_TR3_TR3_MASK ) ) +#define SPWTDP_TR3_TR3( _val ) \ + ( ( ( _val ) << SPWTDP_TR3_TR3_SHIFT ) & \ + SPWTDP_TR3_TR3_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTR4 Time Stamp Elapsed Time 4 Rx (TR4) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TR4_TR4_SHIFT 24 +#define SPWTDP_TR4_TR4_MASK 0xff000000U +#define SPWTDP_TR4_TR4_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_TR4_TR4_MASK ) >> \ + SPWTDP_TR4_TR4_SHIFT ) +#define SPWTDP_TR4_TR4_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_TR4_TR4_MASK ) | \ + ( ( ( _val ) << SPWTDP_TR4_TR4_SHIFT ) & \ + SPWTDP_TR4_TR4_MASK ) ) +#define SPWTDP_TR4_TR4( _val ) \ + ( ( ( _val ) << SPWTDP_TR4_TR4_SHIFT ) & \ + SPWTDP_TR4_TR4_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTTPFTX \ + * Time-Stamp SpaceWire Time-Code and Preamble Field Tx (TTPFTX) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TTPFTX_TSTC_SHIFT 24 +#define SPWTDP_TTPFTX_TSTC_MASK 0xff000000U +#define SPWTDP_TTPFTX_TSTC_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_TTPFTX_TSTC_MASK ) >> \ + SPWTDP_TTPFTX_TSTC_SHIFT ) +#define SPWTDP_TTPFTX_TSTC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_TTPFTX_TSTC_MASK ) | \ + ( ( ( _val ) << SPWTDP_TTPFTX_TSTC_SHIFT ) & \ + SPWTDP_TTPFTX_TSTC_MASK ) ) +#define SPWTDP_TTPFTX_TSTC( _val ) \ + ( ( ( _val ) << SPWTDP_TTPFTX_TSTC_SHIFT ) & \ + SPWTDP_TTPFTX_TSTC_MASK ) + +#define SPWTDP_TTPFTX_TTPF_SHIFT 0 +#define SPWTDP_TTPFTX_TTPF_MASK 0xffffU +#define SPWTDP_TTPFTX_TTPF_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_TTPFTX_TTPF_MASK ) >> \ + SPWTDP_TTPFTX_TTPF_SHIFT ) +#define SPWTDP_TTPFTX_TTPF_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_TTPFTX_TTPF_MASK ) | \ + ( ( ( _val ) << SPWTDP_TTPFTX_TTPF_SHIFT ) & \ + SPWTDP_TTPFTX_TTPF_MASK ) ) +#define SPWTDP_TTPFTX_TTPF( _val ) \ + ( ( ( _val ) << SPWTDP_TTPFTX_TTPF_SHIFT ) & \ + SPWTDP_TTPFTX_TTPF_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTT0 Time Stamp Elapsed Time 0 Tx (TT0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TT0_TT0_SHIFT 0 +#define SPWTDP_TT0_TT0_MASK 0xffffffffU +#define SPWTDP_TT0_TT0_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_TT0_TT0_MASK ) >> \ + SPWTDP_TT0_TT0_SHIFT ) +#define SPWTDP_TT0_TT0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_TT0_TT0_MASK ) | \ + ( ( ( _val ) << SPWTDP_TT0_TT0_SHIFT ) & \ + SPWTDP_TT0_TT0_MASK ) ) +#define SPWTDP_TT0_TT0( _val ) \ + ( ( ( _val ) << SPWTDP_TT0_TT0_SHIFT ) & \ + SPWTDP_TT0_TT0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTT1 Time Stamp Elapsed Time 1 Tx (TT1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TT1_TT1_SHIFT 0 +#define SPWTDP_TT1_TT1_MASK 0xffffffffU +#define SPWTDP_TT1_TT1_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_TT1_TT1_MASK ) >> \ + SPWTDP_TT1_TT1_SHIFT ) +#define SPWTDP_TT1_TT1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_TT1_TT1_MASK ) | \ + ( ( ( _val ) << SPWTDP_TT1_TT1_SHIFT ) & \ + SPWTDP_TT1_TT1_MASK ) ) +#define SPWTDP_TT1_TT1( _val ) \ + ( ( ( _val ) << SPWTDP_TT1_TT1_SHIFT ) & \ + SPWTDP_TT1_TT1_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTT2 Time Stamp Elapsed Time 2 Tx (TT2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TT2_TT2_SHIFT 0 +#define SPWTDP_TT2_TT2_MASK 0xffffffffU +#define SPWTDP_TT2_TT2_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_TT2_TT2_MASK ) >> \ + SPWTDP_TT2_TT2_SHIFT ) +#define SPWTDP_TT2_TT2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_TT2_TT2_MASK ) | \ + ( ( ( _val ) << SPWTDP_TT2_TT2_SHIFT ) & \ + SPWTDP_TT2_TT2_MASK ) ) +#define SPWTDP_TT2_TT2( _val ) \ + ( ( ( _val ) << SPWTDP_TT2_TT2_SHIFT ) & \ + SPWTDP_TT2_TT2_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTT3 Time Stamp Elapsed Time 3 Tx (TT3) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TT3_TT3_SHIFT 0 +#define SPWTDP_TT3_TT3_MASK 0xffffffffU +#define SPWTDP_TT3_TT3_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_TT3_TT3_MASK ) >> \ + SPWTDP_TT3_TT3_SHIFT ) +#define SPWTDP_TT3_TT3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_TT3_TT3_MASK ) | \ + ( ( ( _val ) << SPWTDP_TT3_TT3_SHIFT ) & \ + SPWTDP_TT3_TT3_MASK ) ) +#define SPWTDP_TT3_TT3( _val ) \ + ( ( ( _val ) << SPWTDP_TT3_TT3_SHIFT ) & \ + SPWTDP_TT3_TT3_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTT4 Time Stamp Elapsed Time 4 Tx (TT4) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TT4_TT4_SHIFT 24 +#define SPWTDP_TT4_TT4_MASK 0xff000000U +#define SPWTDP_TT4_TT4_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_TT4_TT4_MASK ) >> \ + SPWTDP_TT4_TT4_SHIFT ) +#define SPWTDP_TT4_TT4_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_TT4_TT4_MASK ) | \ + ( ( ( _val ) << SPWTDP_TT4_TT4_SHIFT ) & \ + SPWTDP_TT4_TT4_MASK ) ) +#define SPWTDP_TT4_TT4( _val ) \ + ( ( ( _val ) << SPWTDP_TT4_TT4_SHIFT ) & \ + SPWTDP_TT4_TT4_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPLPF Latency Preamble Field (LPF) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_LPF_LPF_SHIFT 0 +#define SPWTDP_LPF_LPF_MASK 0xffffU +#define SPWTDP_LPF_LPF_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_LPF_LPF_MASK ) >> \ + SPWTDP_LPF_LPF_SHIFT ) +#define SPWTDP_LPF_LPF_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_LPF_LPF_MASK ) | \ + ( ( ( _val ) << SPWTDP_LPF_LPF_SHIFT ) & \ + SPWTDP_LPF_LPF_MASK ) ) +#define SPWTDP_LPF_LPF( _val ) \ + ( ( ( _val ) << SPWTDP_LPF_LPF_SHIFT ) & \ + SPWTDP_LPF_LPF_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPIE Interrupt Enable (IE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_IE_NCTCE 0x80000U + +#define SPWTDP_IE_SETE 0x400U + +#define SPWTDP_IE_EDIE3 0x200U + +#define SPWTDP_IE_EDIE2 0x100U + +#define SPWTDP_IE_EDIE1 0x80U + +#define SPWTDP_IE_EDIE0 0x40U + +#define SPWTDP_IE_DITE 0x20U + +#define SPWTDP_IE_DIRE 0x10U + +#define SPWTDP_IE_TTE 0x8U + +#define SPWTDP_IE_TME 0x4U + +#define SPWTDP_IE_TRE 0x2U + +#define SPWTDP_IE_SE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDC Delay Count (DC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DC_DC_SHIFT 0 +#define SPWTDP_DC_DC_MASK 0x7fffU +#define SPWTDP_DC_DC_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_DC_DC_MASK ) >> \ + SPWTDP_DC_DC_SHIFT ) +#define SPWTDP_DC_DC_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_DC_DC_MASK ) | \ + ( ( ( _val ) << SPWTDP_DC_DC_SHIFT ) & \ + SPWTDP_DC_DC_MASK ) ) +#define SPWTDP_DC_DC( _val ) \ + ( ( ( _val ) << SPWTDP_DC_DC_SHIFT ) & \ + SPWTDP_DC_DC_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDS Disable Sync (DS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DS_EN 0x80000000U + +#define SPWTDP_DS_CD_SHIFT 0 +#define SPWTDP_DS_CD_MASK 0xffffffU +#define SPWTDP_DS_CD_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_DS_CD_MASK ) >> \ + SPWTDP_DS_CD_SHIFT ) +#define SPWTDP_DS_CD_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_DS_CD_MASK ) | \ + ( ( ( _val ) << SPWTDP_DS_CD_SHIFT ) & \ + SPWTDP_DS_CD_MASK ) ) +#define SPWTDP_DS_CD( _val ) \ + ( ( ( _val ) << SPWTDP_DS_CD_SHIFT ) & \ + SPWTDP_DS_CD_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPEDM0 External Datation 0 Mask (EDM0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_EDM0_EDM0_SHIFT 0 +#define SPWTDP_EDM0_EDM0_MASK 0xffffffffU +#define SPWTDP_EDM0_EDM0_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_EDM0_EDM0_MASK ) >> \ + SPWTDP_EDM0_EDM0_SHIFT ) +#define SPWTDP_EDM0_EDM0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_EDM0_EDM0_MASK ) | \ + ( ( ( _val ) << SPWTDP_EDM0_EDM0_SHIFT ) & \ + SPWTDP_EDM0_EDM0_MASK ) ) +#define SPWTDP_EDM0_EDM0( _val ) \ + ( ( ( _val ) << SPWTDP_EDM0_EDM0_SHIFT ) & \ + SPWTDP_EDM0_EDM0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPEDPF0 \ + * External Datation 0 Preamble Field (EDPF0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_EDPF0_EDPF0_SHIFT 0 +#define SPWTDP_EDPF0_EDPF0_MASK 0xffffU +#define SPWTDP_EDPF0_EDPF0_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_EDPF0_EDPF0_MASK ) >> \ + SPWTDP_EDPF0_EDPF0_SHIFT ) +#define SPWTDP_EDPF0_EDPF0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_EDPF0_EDPF0_MASK ) | \ + ( ( ( _val ) << SPWTDP_EDPF0_EDPF0_SHIFT ) & \ + SPWTDP_EDPF0_EDPF0_MASK ) ) +#define SPWTDP_EDPF0_EDPF0( _val ) \ + ( ( ( _val ) << SPWTDP_EDPF0_EDPF0_SHIFT ) & \ + SPWTDP_EDPF0_EDPF0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET0 \ + * External Datation 0 Elapsed Time 0 (ED0ET0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_ED0ET0_ED0ET0_SHIFT 0 +#define SPWTDP_ED0ET0_ED0ET0_MASK 0xffffffffU +#define SPWTDP_ED0ET0_ED0ET0_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_ED0ET0_ED0ET0_MASK ) >> \ + SPWTDP_ED0ET0_ED0ET0_SHIFT ) +#define SPWTDP_ED0ET0_ED0ET0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_ED0ET0_ED0ET0_MASK ) | \ + ( ( ( _val ) << SPWTDP_ED0ET0_ED0ET0_SHIFT ) & \ + SPWTDP_ED0ET0_ED0ET0_MASK ) ) +#define SPWTDP_ED0ET0_ED0ET0( _val ) \ + ( ( ( _val ) << SPWTDP_ED0ET0_ED0ET0_SHIFT ) & \ + SPWTDP_ED0ET0_ED0ET0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET1 \ + * External Datation 0 Elapsed Time 1 (ED0ET1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_ED0ET1_ED0ET1_SHIFT 0 +#define SPWTDP_ED0ET1_ED0ET1_MASK 0xffffffffU +#define SPWTDP_ED0ET1_ED0ET1_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_ED0ET1_ED0ET1_MASK ) >> \ + SPWTDP_ED0ET1_ED0ET1_SHIFT ) +#define SPWTDP_ED0ET1_ED0ET1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_ED0ET1_ED0ET1_MASK ) | \ + ( ( ( _val ) << SPWTDP_ED0ET1_ED0ET1_SHIFT ) & \ + SPWTDP_ED0ET1_ED0ET1_MASK ) ) +#define SPWTDP_ED0ET1_ED0ET1( _val ) \ + ( ( ( _val ) << SPWTDP_ED0ET1_ED0ET1_SHIFT ) & \ + SPWTDP_ED0ET1_ED0ET1_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET2 \ + * External Datation 0 Elapsed Time 2 (ED0ET2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_ED0ET2_ED0ET2_SHIFT 0 +#define SPWTDP_ED0ET2_ED0ET2_MASK 0xffffffffU +#define SPWTDP_ED0ET2_ED0ET2_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_ED0ET2_ED0ET2_MASK ) >> \ + SPWTDP_ED0ET2_ED0ET2_SHIFT ) +#define SPWTDP_ED0ET2_ED0ET2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_ED0ET2_ED0ET2_MASK ) | \ + ( ( ( _val ) << SPWTDP_ED0ET2_ED0ET2_SHIFT ) & \ + SPWTDP_ED0ET2_ED0ET2_MASK ) ) +#define SPWTDP_ED0ET2_ED0ET2( _val ) \ + ( ( ( _val ) << SPWTDP_ED0ET2_ED0ET2_SHIFT ) & \ + SPWTDP_ED0ET2_ED0ET2_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET3 \ + * External Datation 0 Elapsed Time 3 (ED0ET3) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_ED0ET3_ED0ET3_SHIFT 0 +#define SPWTDP_ED0ET3_ED0ET3_MASK 0xffffffffU +#define SPWTDP_ED0ET3_ED0ET3_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_ED0ET3_ED0ET3_MASK ) >> \ + SPWTDP_ED0ET3_ED0ET3_SHIFT ) +#define SPWTDP_ED0ET3_ED0ET3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_ED0ET3_ED0ET3_MASK ) | \ + ( ( ( _val ) << SPWTDP_ED0ET3_ED0ET3_SHIFT ) & \ + SPWTDP_ED0ET3_ED0ET3_MASK ) ) +#define SPWTDP_ED0ET3_ED0ET3( _val ) \ + ( ( ( _val ) << SPWTDP_ED0ET3_ED0ET3_SHIFT ) & \ + SPWTDP_ED0ET3_ED0ET3_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET4 \ + * External Datation 0 Elapsed Time 4 (ED0ET4) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_ED0ET4_ED0ET4_SHIFT 24 +#define SPWTDP_ED0ET4_ED0ET4_MASK 0xff000000U +#define SPWTDP_ED0ET4_ED0ET4_GET( _reg ) \ + ( ( ( _reg ) & SPWTDP_ED0ET4_ED0ET4_MASK ) >> \ + SPWTDP_ED0ET4_ED0ET4_SHIFT ) +#define SPWTDP_ED0ET4_ED0ET4_SET( _reg, _val ) \ + ( ( ( _reg ) & ~SPWTDP_ED0ET4_ED0ET4_MASK ) | \ + ( ( ( _val ) << SPWTDP_ED0ET4_ED0ET4_SHIFT ) & \ + SPWTDP_ED0ET4_ED0ET4_MASK ) ) +#define SPWTDP_ED0ET4_ED0ET4( _val ) \ + ( ( ( _val ) << SPWTDP_ED0ET4_ED0ET4_SHIFT ) & \ + SPWTDP_ED0ET4_ED0ET4_MASK ) + +/** @} */ + +/** + * @brief This structure defines the SPWTDP register block memory map. + */ +typedef struct spwtdp { + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCONF0. + */ + uint32_t conf0; + + uint32_t reserved_4_c[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCONF3. + */ + uint32_t conf3; + + uint32_t reserved_10_20[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET0. + */ + uint32_t cet0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET1. + */ + uint32_t cet1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET2. + */ + uint32_t cet2; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET3. + */ + uint32_t cet3; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET4. + */ + uint32_t cet4; + + uint32_t reserved_38_40[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDPF. + */ + uint32_t dpf; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET0. + */ + uint32_t det0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET1. + */ + uint32_t det1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET2. + */ + uint32_t det2; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET3. + */ + uint32_t det3; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET4. + */ + uint32_t det4; + + uint32_t reserved_58_60[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTRPFRX. + */ + uint32_t trpfrx; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR0. + */ + uint32_t tr0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR1. + */ + uint32_t tr1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR2. + */ + uint32_t tr2; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR3. + */ + uint32_t tr3; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR4. + */ + uint32_t tr4; + + uint32_t reserved_78_80[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTTPFTX. + */ + uint32_t ttpftx; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT0. + */ + uint32_t tt0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT1. + */ + uint32_t tt1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT2. + */ + uint32_t tt2; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT3. + */ + uint32_t tt3; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT4. + */ + uint32_t tt4; + + uint32_t reserved_98_a0[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPLPF. + */ + uint32_t lpf; + + uint32_t reserved_a4_c0[ 7 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPIE. + */ + uint32_t ie; + + uint32_t reserved_c4_c8; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDC. + */ + uint32_t dc; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDS. + */ + uint32_t ds; + + uint32_t reserved_d0_100[ 12 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPEDM0. + */ + uint32_t edm0; + + uint32_t reserved_104_110[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPEDPF0. + */ + uint32_t edpf0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET0. + */ + uint32_t ed0et0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET1. + */ + uint32_t ed0et1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET2. + */ + uint32_t ed0et2; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET3. + */ + uint32_t ed0et3; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET4. + */ + uint32_t ed0et4; +} spwtdp; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_SPWTDP_REGS_H */ diff --git a/bsps/include/grlib/spwtdp.h b/bsps/include/grlib/spwtdp.h index b2fa29889f..c9870c4edd 100644 --- a/bsps/include/grlib/spwtdp.h +++ b/bsps/include/grlib/spwtdp.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* SPWTDP - SpaceWire Time Distribution Protocol. The driver provides * device discovery and interrupt management. * * COPYRIGHT (c) 2017. * Cobham Gaisler AB * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * */ diff --git a/bsps/include/grlib/tlib.h b/bsps/include/grlib/tlib.h index debb8c8215..b2e8984489 100644 --- a/bsps/include/grlib/tlib.h +++ b/bsps/include/grlib/tlib.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * Timer Library (TLIB) * @@ -11,9 +13,26 @@ * COPYRIGHT (c) 2011. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __TLIB_H__ diff --git a/bsps/include/libchip/disp_hcms29xx.h b/bsps/include/libchip/disp_hcms29xx.h index a7053177c6..adb47dd9d8 100644 --- a/bsps/include/libchip/disp_hcms29xx.h +++ b/bsps/include/libchip/disp_hcms29xx.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * Display driver for HCMS29xx * @@ -6,11 +8,28 @@ */ /* - * Copyright (c) 2008 embedded brains GmbH. All rights reserved. + * Copyright (c) 2008 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _DISP_HCMS29XX_H diff --git a/bsps/include/libchip/greth.h b/bsps/include/libchip/greth.h deleted file mode 100644 index c6e000dbd3..0000000000 --- a/bsps/include/libchip/greth.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Gaisler Research ethernet MAC driver - * adapted from Opencores driver by Marko Isomaki - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#ifndef _GR_ETH_ -#define _GR_ETH_ - - -/* Configuration Information */ - -typedef struct { - void *base_address; - rtems_vector_number vector; - uint32_t txd_count; - uint32_t rxd_count; -} greth_configuration_t; - -/* Ethernet configuration registers */ - -typedef struct _greth_regs { - volatile uint32_t ctrl; /* Ctrl Register */ - volatile uint32_t status; /* Status Register */ - volatile uint32_t mac_addr_msb; /* Bit 47-32 of MAC address */ - volatile uint32_t mac_addr_lsb; /* Bit 31-0 of MAC address */ - volatile uint32_t mdio_ctrl; /* MDIO control and status */ - volatile uint32_t txdesc; /* Transmit descriptor pointer */ - volatile uint32_t rxdesc; /* Receive descriptor pointer */ -} greth_regs; - -#define GRETH_TOTAL_BD 128 -#define GRETH_MAXBUF_LEN 1520 - -/* Tx BD */ -#define GRETH_TXD_ENABLE 0x0800 /* Tx BD Enable */ -#define GRETH_TXD_WRAP 0x1000 /* Tx BD Wrap (last BD) */ -#define GRETH_TXD_IRQ 0x2000 /* Tx BD IRQ Enable */ -#define GRETH_TXD_MORE 0x20000 /* Tx BD More (more descs for packet) */ -#define GRETH_TXD_IPCS 0x40000 /* Tx BD insert ip chksum */ -#define GRETH_TXD_TCPCS 0x80000 /* Tx BD insert tcp chksum */ -#define GRETH_TXD_UDPCS 0x100000 /* Tx BD insert udp chksum */ - -#define GRETH_TXD_UNDERRUN 0x4000 /* Tx BD Underrun Status */ -#define GRETH_TXD_RETLIM 0x8000 /* Tx BD Retransmission Limit Status */ -#define GRETH_TXD_LATECOL 0x10000 /* Tx BD Late Collision */ - -#define GRETH_TXD_STATS (GRETH_TXD_UNDERRUN | \ - GRETH_TXD_RETLIM | \ - GRETH_TXD_LATECOL) - -#define GRETH_TXD_CS (GRETH_TXD_IPCS | \ - GRETH_TXD_TCPCS | \ - GRETH_TXD_UDPCS) - -/* Rx BD */ -#define GRETH_RXD_ENABLE 0x0800 /* Rx BD Enable */ -#define GRETH_RXD_WRAP 0x1000 /* Rx BD Wrap (last BD) */ -#define GRETH_RXD_IRQ 0x2000 /* Rx BD IRQ Enable */ - -#define GRETH_RXD_DRIBBLE 0x4000 /* Rx BD Dribble Nibble Status */ -#define GRETH_RXD_TOOLONG 0x8000 /* Rx BD Too Long Status */ -#define GRETH_RXD_CRCERR 0x10000 /* Rx BD CRC Error Status */ -#define GRETH_RXD_OVERRUN 0x20000 /* Rx BD Overrun Status */ -#define GRETH_RXD_LENERR 0x40000 /* Rx BD Length Error */ -#define GRETH_RXD_ID 0x40000 /* Rx BD IP Detected */ -#define GRETH_RXD_IR 0x40000 /* Rx BD IP Chksum Error */ -#define GRETH_RXD_UD 0x40000 /* Rx BD UDP Detected*/ -#define GRETH_RXD_UR 0x40000 /* Rx BD UDP Chksum Error */ -#define GRETH_RXD_TD 0x40000 /* Rx BD TCP Detected */ -#define GRETH_RXD_TR 0x40000 /* Rx BD TCP Chksum Error */ - - -#define GRETH_RXD_STATS (GRETH_RXD_OVERRUN | \ - GRETH_RXD_DRIBBLE | \ - GRETH_RXD_TOOLONG | \ - GRETH_RXD_CRCERR) - -/* CTRL Register */ -#define GRETH_CTRL_TXEN 0x00000001 /* Transmit Enable */ -#define GRETH_CTRL_RXEN 0x00000002 /* Receive Enable */ -#define GRETH_CTRL_TXIRQ 0x00000004 /* Transmit Enable */ -#define GRETH_CTRL_RXIRQ 0x00000008 /* Receive Enable */ -#define GRETH_CTRL_FULLD 0x00000010 /* Full Duplex */ -#define GRETH_CTRL_PRO 0x00000020 /* Promiscuous (receive all) */ -#define GRETH_CTRL_RST 0x00000040 /* Reset MAC */ - -/* Status Register */ -#define GRETH_STATUS_RXERR 0x00000001 /* Receive Error */ -#define GRETH_STATUS_TXERR 0x00000002 /* Transmit Error IRQ */ -#define GRETH_STATUS_RXIRQ 0x00000004 /* Receive Frame IRQ */ -#define GRETH_STATUS_TXIRQ 0x00000008 /* Transmit Error IRQ */ -#define GRETH_STATUS_RXAHBERR 0x00000010 /* Receiver AHB Error */ -#define GRETH_STATUS_TXAHBERR 0x00000020 /* Transmitter AHB Error */ - -/* MDIO Control */ -#define GRETH_MDIO_WRITE 0x00000001 /* MDIO Write */ -#define GRETH_MDIO_READ 0x00000002 /* MDIO Read */ -#define GRETH_MDIO_LINKFAIL 0x00000004 /* MDIO Link failed */ -#define GRETH_MDIO_BUSY 0x00000008 /* MDIO Link Busy */ -#define GRETH_MDIO_REGADR 0x000007C0 /* Register Address */ -#define GRETH_MDIO_PHYADR 0x0000F800 /* PHY address */ -#define GRETH_MDIO_DATA 0xFFFF0000 /* MDIO DATA */ - - -/* MII registers */ -#define GRETH_MII_EXTADV_1000FD 0x00000200 -#define GRETH_MII_EXTADV_1000HD 0x00000100 -#define GRETH_MII_EXTPRT_1000FD 0x00000800 -#define GRETH_MII_EXTPRT_1000HD 0x00000400 - -#define GRETH_MII_100T4 0x00000200 -#define GRETH_MII_100TXFD 0x00000100 -#define GRETH_MII_100TXHD 0x00000080 -#define GRETH_MII_10FD 0x00000040 -#define GRETH_MII_10HD 0x00000020 - - - -/* Attach routine */ - -int rtems_greth_driver_attach ( - struct rtems_bsdnet_ifconfig *config, - greth_configuration_t *chip -); - -/* PHY data */ -struct phy_device_info -{ - int vendor; - int device; - int rev; - - int adv; - int part; - - int extadv; - int extpart; -}; - -/* -#ifdef CPU_U32_FIX -void ipalign(struct mbuf *m); -#endif - -*/ -#endif - diff --git a/bsps/include/libchip/i2c-sc620.h b/bsps/include/libchip/i2c-sc620.h index e8326de881..f232396dfe 100644 --- a/bsps/include/libchip/i2c-sc620.h +++ b/bsps/include/libchip/i2c-sc620.h @@ -1,9 +1,28 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef I2C_SC620_H diff --git a/bsps/include/libchip/icm7170.h b/bsps/include/libchip/icm7170.h index 6b95c905a4..d0985c43f6 100644 --- a/bsps/include/libchip/icm7170.h +++ b/bsps/include/libchip/icm7170.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * This file contains the definitions for the following real-time clocks: * @@ -6,9 +8,26 @@ * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __LIBCHIP_ICM7170_h diff --git a/bsps/include/libchip/m48t08.h b/bsps/include/libchip/m48t08.h index 3c46d384d5..3effafe49f 100644 --- a/bsps/include/libchip/m48t08.h +++ b/bsps/include/libchip/m48t08.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * This file contains the definitions for the following real-time clocks: * @@ -8,9 +10,26 @@ * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __LIBCHIP_M48T08_h diff --git a/bsps/include/libchip/mc146818a.h b/bsps/include/libchip/mc146818a.h index 4eb5af04d7..d12a320fd2 100644 --- a/bsps/include/libchip/mc146818a.h +++ b/bsps/include/libchip/mc146818a.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * This file contains the definitions for the following real-time clocks: * @@ -6,9 +8,26 @@ * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __LIBCHIP_MC146818A_h diff --git a/bsps/include/libchip/mc68681.h b/bsps/include/libchip/mc68681.h index e498a41b30..c4bd890e0a 100644 --- a/bsps/include/libchip/mc68681.h +++ b/bsps/include/libchip/mc68681.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _MC68681_H_ diff --git a/bsps/include/libchip/mcp7940m-rtc.h b/bsps/include/libchip/mcp7940m-rtc.h new file mode 100644 index 0000000000..266400dfba --- /dev/null +++ b/bsps/include/libchip/mcp7940m-rtc.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBCHIP_MCP7940M_RTC_H +#define LIBCHIP_MCP7940M_RTC_H + +#include <rtems.h> +#include <rtems/thread.h> +#include <libchip/rtc.h> +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +extern const rtc_fns rtc_mcp7940m_fns; +bool rtc_mcp7940m_probe(int minor); + +/* + * It is expected, that the RTC can be accessed as a raw file. A pointer to a + * constant string with the name of that device has to be passed to the table + * initializer. + * + * The MCP7940M uses an EEPROM-like interface. So you could for example use the + * following initialization: + * + * Define a context for the RTC somewhere: + * + * static struct mcp7940m_rtc rtc_ctx = + * MCP7940M_RTC_INITIALIZER("/dev/i2c-1", 0x6F, true); + * + * Then you can use the following for the RTC_Table: + * + * MCP7940M_RTC_TBL_ENTRY("/dev/rtc", &rtc_ctx) + */ + +struct mcp7940m_rtc { + /** Just initialize with RTEMS_MUTEX_INITIALIZER('mcp7940'). */ + rtems_mutex mutex; + + /** The path of the I2C bus device. */ + const char *i2c_bus_path; + + /** I2C address. */ + uint8_t i2c_addr; + + /** True if a crystal should be used. False if an oscillator is connected. */ + bool crystal; + + /** Whether the RTC has already been initialized. Used internally. */ + bool initialized; +}; + +#define MCP7940M_RTC_INITIALIZER(i2c_path, i2c_address, has_crystal) { \ + .mutex = RTEMS_MUTEX_INITIALIZER("mcp7940m"), \ + .i2c_bus_path = i2c_path, \ + .i2c_addr = i2c_address, \ + .crystal = has_crystal, \ + .initialized = false, \ + } + +#define MCP7940M_RTC_TBL_ENTRY(dev_name, mcp7940m_rtc_ctx) \ + { \ + .sDeviceName = dev_name, \ + .deviceType = RTC_CUSTOM, \ + .pDeviceFns = &rtc_mcp7940m_fns, \ + .deviceProbe = rtc_mcp7940m_probe, \ + .pDeviceParams = (void *)mcp7940m_rtc_ctx, \ + .ulCtrlPort1 = 0, \ + .ulDataPort = 0, \ + .getRegister = NULL, \ + .setRegister = NULL, \ + } + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCHIP_MCP7940M_RTC_H */ diff --git a/bsps/include/libchip/rtc.h b/bsps/include/libchip/rtc.h index 49dd51c2e2..02bf1cad8f 100644 --- a/bsps/include/libchip/rtc.h +++ b/bsps/include/libchip/rtc.h @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * This file contains the Real-Time Clock definitions. * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __LIBCHIP_RTC_h diff --git a/bsps/include/libchip/serial.h b/bsps/include/libchip/serial.h index 49a7bebdca..eef072eb6a 100644 --- a/bsps/include/libchip/serial.h +++ b/bsps/include/libchip/serial.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -13,9 +15,26 @@ * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __LIBCHIP_SERIAL_h diff --git a/bsps/include/libchip/spi-flash-m25p40.h b/bsps/include/libchip/spi-flash-m25p40.h index fdd11f8ecf..c64109515c 100644 --- a/bsps/include/libchip/spi-flash-m25p40.h +++ b/bsps/include/libchip/spi-flash-m25p40.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * SPI driver for M25P40 like spi flash device * @@ -6,11 +8,28 @@ */ /* - * Copyright (c) 2007 embedded brains GmbH. All rights reserved. + * Copyright (c) 2007 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _LIBCHIP_SPI_FLASH_M25P40_H diff --git a/bsps/include/libchip/spi-fram-fm25l256.h b/bsps/include/libchip/spi-fram-fm25l256.h index a2d312d268..4251edb556 100644 --- a/bsps/include/libchip/spi-fram-fm25l256.h +++ b/bsps/include/libchip/spi-fram-fm25l256.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * SPI driver for FM25L256 like spi fram device * @@ -6,11 +8,28 @@ */ /* - * Copyright (c) 2008 embedded brains GmbH. All rights reserved. + * Copyright (c) 2008 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _LIBCHIP_SPI_FRAM_FM25L256_H diff --git a/bsps/include/libchip/spi-memdrv.h b/bsps/include/libchip/spi-memdrv.h index 04feccc3a3..d2c6a1edc1 100644 --- a/bsps/include/libchip/spi-memdrv.h +++ b/bsps/include/libchip/spi-memdrv.h @@ -1,13 +1,32 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * SPI driver for spi memory devices */ /* - * Copyright (c) 2008 embedded brains GmbH. All rights reserved. + * Copyright (c) 2008 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _LIBCHIP_SPI_MEMDRV_H diff --git a/bsps/include/libchip/spi-sd-card.h b/bsps/include/libchip/spi-sd-card.h index 4480823271..227ae7d58a 100644 --- a/bsps/include/libchip/spi-sd-card.h +++ b/bsps/include/libchip/spi-sd-card.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -5,10 +7,27 @@ */ /* - * Copyright (c) 2008 embedded brains GmbH. All rights reserved. - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Copyright (c) 2008 embedded brains GmbH & Co. KG + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBI2C_SD_CARD_H diff --git a/bsps/include/mpci.h b/bsps/include/mpci.h index cc7c5826de..0aeb7bb081 100644 --- a/bsps/include/mpci.h +++ b/bsps/include/mpci.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* mpci.h * * This include file contains all the renaming necessary to @@ -7,9 +9,26 @@ * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SHM_MPCI_h diff --git a/bsps/include/peripheral_maps/xilinx_zynqmp.h b/bsps/include/peripheral_maps/xilinx_zynqmp.h new file mode 100644 index 0000000000..9613dcead6 --- /dev/null +++ b/bsps/include/peripheral_maps/xilinx_zynqmp.h @@ -0,0 +1,118 @@ +/** + * @file + * @ingroup RTEMSBSPsShared + * @brief Xilinx Zynq Ultrascale+ MPSoC Peripheral memory map. + */ + +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2023 Reflex Aerospace GmbH + * + * Written by Philip Kirkpatrick <p.kirkpatrick@reflexaerospace.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_SHARED_PERIPHERAL_MAPS_ZYNQMP +#define LIBBSP_SHARED_PERIPHERAL_MAPS_ZYNQMP + +/* Data derived from https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/PS-I/O-Peripherals-Registers */ + +/* LPD IO Peripherals */ +#define ZYNQMP_UART0 (0xFF000000) +#define ZYNQMP_UART1 (0xFF010000) +#define ZYNQMP_I2C0 (0xFF020000) +#define ZYNQMP_I2C1 (0xFF030000) +#define ZYNQMP_SPI0 (0xFF040000) +#define ZYNQMP_SPI1 (0xFF050000) +#define ZYNQMP_CAN0 (0xFF060000) +#define ZYNQMP_CAN1 (0xFF070000) +#define ZYNQMP_GPIO (0xFF0A0000) +#define ZYNQMP_GEM0 (0xFF0B0000) +#define ZYNQMP_GEM1 (0xFF0C0000) +#define ZYNQMP_GEM2 (0xFF0D0000) +#define ZYNQMP_GEM3 (0xFF0E0000) +#define ZYNQMP_QSPI (0xFF0F0000) +#define ZYNQMP_NAND (0xFF100000) +#define ZYNQMP_SD0 (0xFF160000) +#define ZYNQMP_SD1 (0xFF170000) +#define ZYNQMP_IPI_MSG (0xFF990000) +#define ZYNQMP_USB0 (0xFF9D0000) +#define ZYNQMP_USB1 (0xFF9E0000) +#define ZYNQMP_AMS (0xFFA50000) +#define ZYNQMP_PSSYSMON (0xFFA50800) +#define ZYNQMP_PLSYSMON (0xFFA50C00) +#define ZYNQMP_CSU_SWDT (0xFFCB0000) + +/* FPD IO Peripherals */ +#define ZYNQMP_SATA (0xFD0C0000) +#define ZYNQMP_PCIE (0xFD0E0000) +#define ZYNQMP_PCIE_IN (0xFD0E0800) +#define ZYNQMP_PCIE_EG (0xFD0E0C00) +#define ZYNQMP_PCIE_DMA (0xFD0F0000) +#define ZYNQMP_SIOU (0xFD3D0000) +#define ZYNQMP_GTR (0xFD400000) +#define ZYNQMP_PCIE_ATTR (0xFD480000) +#define ZYNQMP_DP (0xFD4A0000) +#define ZYNQMP_GPU (0xFD4B0000) +#define ZYNQMP_DP_DMA (0xFD4C0000) + +/* LPD System Registers */ +#define ZYNQMP_IPI (0xFF300000) +#define ZYNQMP_TTC0 (0xFF110000) +#define ZYNQMP_TTC1 (0xFF120000) +#define ZYNQMP_TTC2 (0xFF130000) +#define ZYNQMP_TTC3 (0xFF140000) +#define ZYNQMP_LPD_SWDT (0xFF150000) +#define ZYNQMP_XPPU (0xFF980000) +#define ZYNQMP_XPPU_SINK (0xFF9C0000) +#define ZYNQMP_PL_LPD (0xFF9B0000) +#define ZYNQMP_OCM (0xFFA00000) +#define ZYNQMP_LPD_FPD (0xFFA10000) +#define ZYNQMP_RTC (0xFFA60000) +#define ZYNQMP_OCM_XMPU (0xFFA70000) +#define ZYNQMP_LPD_DMA (0xFFA80000) +#define ZYNQMP_CSU_DMA (0xFFC80000) +#define ZYNQMP_CSU (0xFFCA0000) +#define ZYNQMP_BBRAM (0xFFCD0000) + +/* System Interrupt Table */ + +/* SPIs */ +#define ZYNQMP_IRQ_UART_0 53 +#define ZYNQMP_IRQ_UART_1 54 + +#define ZYNQMP_IRQ_TTC_0_0 68 +#define ZYNQMP_IRQ_TTC_0_1 69 +#define ZYNQMP_IRQ_TTC_0_2 70 +#define ZYNQMP_IRQ_TTC_1_0 71 +#define ZYNQMP_IRQ_TTC_1_1 72 +#define ZYNQMP_IRQ_TTC_1_2 73 +#define ZYNQMP_IRQ_TTC_2_0 74 +#define ZYNQMP_IRQ_TTC_2_1 75 +#define ZYNQMP_IRQ_TTC_2_2 76 +#define ZYNQMP_IRQ_TTC_3_0 77 +#define ZYNQMP_IRQ_TTC_3_1 78 +#define ZYNQMP_IRQ_TTC_3_2 79 + +#endif /* LIBBSP_SHARED_PERIPHERAL_MAPS_ZYNQMP */ diff --git a/bsps/include/rtems/umon.h b/bsps/include/rtems/umon.h index d25a7818dd..7b502ebd4a 100644 --- a/bsps/include/rtems/umon.h +++ b/bsps/include/rtems/umon.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * umon.h - RTEMS specific interface to MicroMonitor. * @@ -7,9 +9,26 @@ * Modified by Fernando Nicodemos <fgnicodemos@terra.com.br> * from NCB - Sistemas Embarcados Ltda. (Brazil) * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __rtems_umon_h diff --git a/bsps/include/rtems/zilog/z8036.h b/bsps/include/rtems/zilog/z8036.h index fea1493905..61fae1ad4b 100644 --- a/bsps/include/rtems/zilog/z8036.h +++ b/bsps/include/rtems/zilog/z8036.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -14,9 +16,26 @@ * COPYRIGHT (c) 1989-2011. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RTEMS_ZILOG_Z8036_H diff --git a/bsps/include/rtems/zilog/z8530.h b/bsps/include/rtems/zilog/z8530.h index 161b9a022c..c8460830f0 100644 --- a/bsps/include/rtems/zilog/z8530.h +++ b/bsps/include/rtems/zilog/z8530.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -11,9 +13,26 @@ * COPYRIGHT (c) 1989-2011. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RTEMS_ZILOG_Z8530_H diff --git a/bsps/include/shm_driver.h b/bsps/include/shm_driver.h index f81945b3d8..3517dbc6cf 100644 --- a/bsps/include/shm_driver.h +++ b/bsps/include/shm_driver.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* shm_driver.h * * This include file contains all the constants, structures, @@ -9,9 +11,26 @@ * COPYRIGHT (c) 1989-2007. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SHM_h diff --git a/bsps/include/xil/arm/ARMv8/32bit/xil_cache.h b/bsps/include/xil/arm/ARMv8/32bit/xil_cache.h new file mode 100644 index 0000000000..b878d05299 --- /dev/null +++ b/bsps/include/xil/arm/ARMv8/32bit/xil_cache.h @@ -0,0 +1,75 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* @addtogroup a53_64_cache_apis Cortex A53 64bit Processor Cache Functions +* +* Cache functions provide access to cache related operations such as flush +* and invalidate for instruction and data caches. It gives option to perform +* the cache operations on a single cacheline, a range of memory and an entire +* cache. +* +* @{ +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +* </pre> +* +******************************************************************************/ +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + *@cond nocomments + */ + +/************************** Constant Definitions *****************************/ +#define L1_DATA_PREFETCH_CONTROL_MASK 0xE000 +#define L1_DATA_PREFETCH_CONTROL_SHIFT 13 + +/** + *@endcond + */ + +/***************** Macros (Inline Functions) Definitions *********************/ +#define Xil_DCacheFlushRange Xil_DCacheInvalidateRange + +/************************** Function Prototypes ******************************/ +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len); +void Xil_DCacheInvalidateLine(INTPTR adr); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushLine(INTPTR adr); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len); +void Xil_ICacheInvalidateLine(INTPTR adr); +void Xil_ConfigureL1Prefetch(u8 num); +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup a53_64_cache_apis". +*/ diff --git a/bsps/include/xil/arm/ARMv8/32bit/xil_exception.h b/bsps/include/xil/arm/ARMv8/32bit/xil_exception.h new file mode 100644 index 0000000000..144d8423df --- /dev/null +++ b/bsps/include/xil/arm/ARMv8/32bit/xil_exception.h @@ -0,0 +1,408 @@ +/****************************************************************************** +* Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +* @addtogroup arm_exception_apis ARM Processor Exception Handling +* @{ +* ARM processors specific exception related APIs for cortex A53,A9 and R5 can +* utilized for enabling/disabling IRQ, registering/removing handler for +* exceptions or initializing exception vector table with null handler. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.2 pkp 28/05/15 First release +* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors +* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler. +* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler. +* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and +* Xil_ExceptionDisableMask macros to support legacy +* examples for Cortexa72 EL3 exception level. +* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and +* Xil_DisableNestedInterrupts macros for ARMv8. +* For Cortexa72, these macro's would not be supported +* at EL3, as Cortexa72 is using GIC-500(GICv3), which +* triggeres only FIQ at EL3. Fix for CR#1062506 +* 7.6 mus 09/17/21 Updated flag checking to fix warning reported with +* -Wundef compiler option CR#1110261 +* 7.7 mus 01/31/22 Few of the #defines in xil_exception.h in are treated +* in different way based on "versal" flag. In existing +* flow, this flag is defined only in xparameters.h and +* BSP compiler flags, it is not defined in application +* compiler flags. So, including xil_exception.h in +* application source file, without including +* xparameters.h results in incorrect behavior. +* Including xparameters.h in xil_exception.h to avoid +* such issues. It fixes CR#1120498. +* 7.7 sk 03/02/22 Define XExc_VectorTableEntry structure to fix +* misra_c_2012_rule_5_6 violation. +* 7.7 sk 03/02/22 Add XExc_VectorTable as extern to fix misra_c_2012_ +* rule_8_4 violation. +* </pre> +* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "bspconfig.h" +#include "xparameters.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0U +#if defined (__aarch64__) +#define XIL_EXCEPTION_ID_SYNC_INT 1U +#define XIL_EXCEPTION_ID_IRQ_INT 2U +#define XIL_EXCEPTION_ID_FIQ_INT 3U +#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U +#define XIL_EXCEPTION_ID_LAST 5U +#else +#define XIL_EXCEPTION_ID_RESET 0U +#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U +#define XIL_EXCEPTION_ID_SWI_INT 2U +#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U +#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U +#define XIL_EXCEPTION_ID_IRQ_INT 5U +#define XIL_EXCEPTION_ID_FIQ_INT 6U +#define XIL_EXCEPTION_ID_LAST 6U +#endif + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#if defined (versal) && !defined(ARMR5) && EL3 +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT +#else +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT +#endif + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +extern XExc_VectorTableEntry XExc_VectorTable[]; + +/** +*@endcond +*/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* @brief Enable Exceptions. +* +* @param Mask: Value for enabling the exceptions. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* +******************************************************************************/ +#if defined (versal) && !defined(ARMR5) && EL3 +/* + * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports + * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ + * ignoring argument passed by user. + */ +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL)) +#elif defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionEnableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \ + } +#endif +/****************************************************************************/ +/** +* @brief Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#if defined (versal) && !defined(ARMR5) && EL3 +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ) +#else +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) +#endif + +/****************************************************************************/ +/** +* @brief Disable Exceptions. +* +* @param Mask: Value for disabling the exceptions. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask) +* +******************************************************************************/ +#if defined (versal) && !defined(ARMR5) && EL3 +/* + * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports + * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ + * ignoring argument passed by user. + */ +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL)) +#elif defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionDisableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \ + } +#endif +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + +#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) ) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I bit in DAIF.This +* macro is defined for Cortex-A53 64 bit mode BSP configured to run +* at EL3.. However,it is not defined for Versal Cortex-A72 BSP +* configured to run at EL3. Reason is, Cortex-A72 is coupled +* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3. +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I bit +* is set as 1). To allow nesting of interrupts, this macro should be +* used. It clears the I bit. Once that bit is cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I +* bit, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs X1, ELR_EL3"); \ + __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \ + __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I bit in DAIF. This +* macro is defined for Cortex-A53 64 bit mode BSP configured to run +* at EL3. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ mode and +* hence sets back the I bit. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \ + __asm__ __volatile__ ("msr ELR_EL3, X1"); \ + __asm__ __volatile__ ("msr SPSR_EL3, X2"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1)) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I bit in DAIF.This +* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit +* BSP configured to run at EL1 NON SECURE +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I bit +* is set as 1). To allow nesting of interrupts, this macro should be +* used. It clears the I bit. Once that bit is cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I +* bit, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs X1, ELR_EL1"); \ + __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \ + __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I bit in DAIF. This +* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit +* BSP configured to run at EL1 NON SECURE +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ mode and +* hence sets back the I bit. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \ + __asm__ __volatile__ ("msr ELR_EL1, X1"); \ + __asm__ __volatile__ ("msr SPSR_EL1, X2"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +#elif (!defined (__aarch64__) && !defined (ARMA53_32)) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This +* API is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I and F +* are 1). To allow nesting of interrupts, this macro should be +* used. It clears the I and F bits by changing the ARM mode to +* system mode. Once these bits are cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I and +* F bits, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("mrs lr, spsr"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I and F bits. This API +* is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ/FIQ mode and +* hence sets back the I and F bits. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr spsr_cxsf, lr"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + +#endif +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); +extern void Xil_GetExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler *Handler, void **Data); + +extern void Xil_ExceptionInit(void); +#if defined (__aarch64__) +void Xil_SyncAbortHandler(void *CallBackRef); +void Xil_SErrorAbortHandler(void *CallBackRef); +#else +extern void Xil_DataAbortHandler(void *CallBackRef); +extern void Xil_PrefetchAbortHandler(void *CallBackRef); +extern void Xil_UndefinedExceptionHandler(void *CallBackRef); +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ +/** +* @} End of "addtogroup arm_exception_apis". +*/ diff --git a/bsps/include/xil/arm/ARMv8/32bit/xil_system.h b/bsps/include/xil/arm/ARMv8/32bit/xil_system.h new file mode 100644 index 0000000000..7269e5c8d9 --- /dev/null +++ b/bsps/include/xil/arm/ARMv8/32bit/xil_system.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * COPYRIGHT (c) 2023. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_SHARED_XIL_SYSTEM_H +#define LIBBSP_SHARED_XIL_SYSTEM_H + +/* + * This file defines anything necessary for the Xilinx support infrastructure to + * function properly on a particular platform. + */ + +#endif diff --git a/bsps/include/xil/arm/ARMv8/32bit/xpseudo_asm.h b/bsps/include/xil/arm/ARMv8/32bit/xpseudo_asm.h new file mode 100644 index 0000000000..41c9c9c944 --- /dev/null +++ b/bsps/include/xil/arm/ARMv8/32bit/xpseudo_asm.h @@ -0,0 +1,53 @@ +/****************************************************************************** +* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* @addtogroup a53_32_specific Cortex A53 32bit Processor Specific Include Files +* +* The xpseudo_asm.h includes xreg_cortexa53.h and xpseudo_asm_gcc.h. +* The xreg_cortexa53.h file contains definitions for inline assembler code. +* It provides inline definitions for Cortex A53 GPRs, SPRs, co-processor +* registers and floating point registers. +* +* The xpseudo_asm_gcc.h contains the definitions for the most often used inline +* assembler instructions, available as macros. These can be very useful for +* tasks such as setting or getting special purpose registers, synchronization, +* or cache manipulation etc. These inline assembler instructions can be used +* from drivers and user applications written in C. +* +* @{ +* +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 5.2 pkp 28/05/15 First release +* </pre> +* +******************************************************************************/ +#ifndef XPSEUDO_ASM_H +#define XPSEUDO_ASM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xreg_cortexa53.h" +#include "xpseudo_asm_gcc.h" + +#ifdef __cplusplus +} +#endif + +#endif /* XPSEUDO_ASM_H */ +/** +* @} End of "addtogroup a53_32_specific". +*/ diff --git a/bsps/include/xil/arm/ARMv8/32bit/xreg_cortexa53.h b/bsps/include/xil/arm/ARMv8/32bit/xreg_cortexa53.h new file mode 100644 index 0000000000..e811686fe5 --- /dev/null +++ b/bsps/include/xil/arm/ARMv8/32bit/xreg_cortexa53.h @@ -0,0 +1,394 @@ +/****************************************************************************** +* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xreg_cortexa53.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU. +* +* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.2 pkp 28/05/15 First release +* </pre> +* +******************************************************************************/ +#ifndef XREG_CORTEXA53_H +#define XREG_CORTEXA53_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + *@cond nocomments + */ + +/* GPRs */ +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr + +/* Coprocessor number defines */ +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 + +/* Coprocessor control register defines */ +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_THUMB_MODE 0x20 +#define XREG_CPSR_MODE_BITS 0x1F +#define XREG_CPSR_SYSTEM_MODE 0x1F +#define XREG_CPSR_UNDEFINED_MODE 0x1B +#define XREG_CPSR_DATA_ABORT_MODE 0x17 +#define XREG_CPSR_SVC_MODE 0x13 +#define XREG_CPSR_IRQ_MODE 0x12 +#define XREG_CPSR_FIQ_MODE 0x11 +#define XREG_CPSR_USER_MODE 0x10 + +#define XREG_CPSR_IRQ_ENABLE 0x80 +#define XREG_CPSR_FIQ_ENABLE 0x40 + +#define XREG_CPSR_N_BIT 0x80000000 +#define XREG_CPSR_Z_BIT 0x40000000 +#define XREG_CPSR_C_BIT 0x20000000 +#define XREG_CPSR_V_BIT 0x10000000 + + +/* CP15 defines */ + +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" + +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" + +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" + +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" + +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" + +#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0" +#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1" +#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2" +#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3" + + +/* XREG_CP15_CONTROL bit defines */ +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U + + +/* C2 Register Defines */ +#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0" +#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1" +#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2" + +/* C3 Register Defines */ +#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0" + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" + +#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0" +#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6" + +#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0" + +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex A53. + */ +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" + +#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0" +#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1" +#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2" +#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3" + +#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4" +#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5" +#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6" +#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex A53. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" + +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" + +/* C8 Register Defines */ +#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0" +#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1" +#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2" +#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3" + +#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0" +#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1" +#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2" + +#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0" +#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1" +#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2" + +#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0" +#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1" +#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2" +#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3" + +/* C9 Register Defines */ +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" + +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" + +/* C10 Register Defines */ +#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0" + +#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0" +#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1" + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0" +#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1" + +#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0" +#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1" + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0" +#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0" + +#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2" +#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4" + +#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2" + +#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2" + +#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2" + +/* MPE register definitions */ +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24) +#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (1<<23) +#define XREG_FPSID_ARCH_BIT (16) +#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8) +#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4) +#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0) +#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (1 << 31) +#define XREG_FPSCR_Z_BIT (1 << 30) +#define XREG_FPSCR_C_BIT (1 << 29) +#define XREG_FPSCR_V_BIT (1 << 28) +#define XREG_FPSCR_QC (1 << 27) +#define XREG_FPSCR_AHP (1 << 26) +#define XREG_FPSCR_DEFAULT_NAN (1 << 25) +#define XREG_FPSCR_FLUSHTOZERO (1 << 24) +#define XREG_FPSCR_ROUND_NEAREST (0 << 22) +#define XREG_FPSCR_ROUND_PLUSINF (1 << 22) +#define XREG_FPSCR_ROUND_MINUSINF (2 << 22) +#define XREG_FPSCR_ROUND_TOZERO (3 << 22) +#define XREG_FPSCR_RMODE_BIT (22) +#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20) +#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16) +#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (1 << 7) +#define XREG_FPSCR_IXC (1 << 4) +#define XREG_FPSCR_UFC (1 << 3) +#define XREG_FPSCR_OFC (1 << 2) +#define XREG_FPSCR_DZC (1 << 1) +#define XREG_FPSCR_IOC (1 << 0) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28) +#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24) +#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20) +#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16) +#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12) +#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8) +#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4) +#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0) +#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (1 << 31) +#define XREG_FPEXC_EN (1 << 30) +#define XREG_FPEXC_DEX (1 << 29) + + +#define XREG_CONTROL_DCACHE_BIT (0X00000001U<<2U) +#define XREG_CONTROL_ICACHE_BIT (0X00000001U<<12U) + +/** + *@endcond + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXA53_H */ diff --git a/bsps/include/xil/arm/ARMv8/64bit/xil_cache.h b/bsps/include/xil/arm/ARMv8/64bit/xil_cache.h new file mode 100644 index 0000000000..b878d05299 --- /dev/null +++ b/bsps/include/xil/arm/ARMv8/64bit/xil_cache.h @@ -0,0 +1,75 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* @addtogroup a53_64_cache_apis Cortex A53 64bit Processor Cache Functions +* +* Cache functions provide access to cache related operations such as flush +* and invalidate for instruction and data caches. It gives option to perform +* the cache operations on a single cacheline, a range of memory and an entire +* cache. +* +* @{ +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +* </pre> +* +******************************************************************************/ +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + *@cond nocomments + */ + +/************************** Constant Definitions *****************************/ +#define L1_DATA_PREFETCH_CONTROL_MASK 0xE000 +#define L1_DATA_PREFETCH_CONTROL_SHIFT 13 + +/** + *@endcond + */ + +/***************** Macros (Inline Functions) Definitions *********************/ +#define Xil_DCacheFlushRange Xil_DCacheInvalidateRange + +/************************** Function Prototypes ******************************/ +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len); +void Xil_DCacheInvalidateLine(INTPTR adr); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushLine(INTPTR adr); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len); +void Xil_ICacheInvalidateLine(INTPTR adr); +void Xil_ConfigureL1Prefetch(u8 num); +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup a53_64_cache_apis". +*/ diff --git a/bsps/include/xil/arm/ARMv8/64bit/xil_exception.h b/bsps/include/xil/arm/ARMv8/64bit/xil_exception.h new file mode 100644 index 0000000000..144d8423df --- /dev/null +++ b/bsps/include/xil/arm/ARMv8/64bit/xil_exception.h @@ -0,0 +1,408 @@ +/****************************************************************************** +* Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +* @addtogroup arm_exception_apis ARM Processor Exception Handling +* @{ +* ARM processors specific exception related APIs for cortex A53,A9 and R5 can +* utilized for enabling/disabling IRQ, registering/removing handler for +* exceptions or initializing exception vector table with null handler. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.2 pkp 28/05/15 First release +* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors +* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler. +* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler. +* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and +* Xil_ExceptionDisableMask macros to support legacy +* examples for Cortexa72 EL3 exception level. +* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and +* Xil_DisableNestedInterrupts macros for ARMv8. +* For Cortexa72, these macro's would not be supported +* at EL3, as Cortexa72 is using GIC-500(GICv3), which +* triggeres only FIQ at EL3. Fix for CR#1062506 +* 7.6 mus 09/17/21 Updated flag checking to fix warning reported with +* -Wundef compiler option CR#1110261 +* 7.7 mus 01/31/22 Few of the #defines in xil_exception.h in are treated +* in different way based on "versal" flag. In existing +* flow, this flag is defined only in xparameters.h and +* BSP compiler flags, it is not defined in application +* compiler flags. So, including xil_exception.h in +* application source file, without including +* xparameters.h results in incorrect behavior. +* Including xparameters.h in xil_exception.h to avoid +* such issues. It fixes CR#1120498. +* 7.7 sk 03/02/22 Define XExc_VectorTableEntry structure to fix +* misra_c_2012_rule_5_6 violation. +* 7.7 sk 03/02/22 Add XExc_VectorTable as extern to fix misra_c_2012_ +* rule_8_4 violation. +* </pre> +* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "bspconfig.h" +#include "xparameters.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0U +#if defined (__aarch64__) +#define XIL_EXCEPTION_ID_SYNC_INT 1U +#define XIL_EXCEPTION_ID_IRQ_INT 2U +#define XIL_EXCEPTION_ID_FIQ_INT 3U +#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U +#define XIL_EXCEPTION_ID_LAST 5U +#else +#define XIL_EXCEPTION_ID_RESET 0U +#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U +#define XIL_EXCEPTION_ID_SWI_INT 2U +#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U +#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U +#define XIL_EXCEPTION_ID_IRQ_INT 5U +#define XIL_EXCEPTION_ID_FIQ_INT 6U +#define XIL_EXCEPTION_ID_LAST 6U +#endif + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#if defined (versal) && !defined(ARMR5) && EL3 +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT +#else +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT +#endif + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +extern XExc_VectorTableEntry XExc_VectorTable[]; + +/** +*@endcond +*/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* @brief Enable Exceptions. +* +* @param Mask: Value for enabling the exceptions. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* +******************************************************************************/ +#if defined (versal) && !defined(ARMR5) && EL3 +/* + * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports + * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ + * ignoring argument passed by user. + */ +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL)) +#elif defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionEnableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \ + } +#endif +/****************************************************************************/ +/** +* @brief Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#if defined (versal) && !defined(ARMR5) && EL3 +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ) +#else +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) +#endif + +/****************************************************************************/ +/** +* @brief Disable Exceptions. +* +* @param Mask: Value for disabling the exceptions. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask) +* +******************************************************************************/ +#if defined (versal) && !defined(ARMR5) && EL3 +/* + * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports + * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ + * ignoring argument passed by user. + */ +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL)) +#elif defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionDisableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \ + } +#endif +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + +#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) ) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I bit in DAIF.This +* macro is defined for Cortex-A53 64 bit mode BSP configured to run +* at EL3.. However,it is not defined for Versal Cortex-A72 BSP +* configured to run at EL3. Reason is, Cortex-A72 is coupled +* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3. +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I bit +* is set as 1). To allow nesting of interrupts, this macro should be +* used. It clears the I bit. Once that bit is cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I +* bit, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs X1, ELR_EL3"); \ + __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \ + __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I bit in DAIF. This +* macro is defined for Cortex-A53 64 bit mode BSP configured to run +* at EL3. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ mode and +* hence sets back the I bit. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \ + __asm__ __volatile__ ("msr ELR_EL3, X1"); \ + __asm__ __volatile__ ("msr SPSR_EL3, X2"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1)) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I bit in DAIF.This +* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit +* BSP configured to run at EL1 NON SECURE +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I bit +* is set as 1). To allow nesting of interrupts, this macro should be +* used. It clears the I bit. Once that bit is cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I +* bit, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs X1, ELR_EL1"); \ + __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \ + __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I bit in DAIF. This +* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit +* BSP configured to run at EL1 NON SECURE +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ mode and +* hence sets back the I bit. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \ + __asm__ __volatile__ ("msr ELR_EL1, X1"); \ + __asm__ __volatile__ ("msr SPSR_EL1, X2"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +#elif (!defined (__aarch64__) && !defined (ARMA53_32)) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This +* API is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I and F +* are 1). To allow nesting of interrupts, this macro should be +* used. It clears the I and F bits by changing the ARM mode to +* system mode. Once these bits are cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I and +* F bits, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("mrs lr, spsr"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I and F bits. This API +* is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ/FIQ mode and +* hence sets back the I and F bits. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr spsr_cxsf, lr"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + +#endif +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); +extern void Xil_GetExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler *Handler, void **Data); + +extern void Xil_ExceptionInit(void); +#if defined (__aarch64__) +void Xil_SyncAbortHandler(void *CallBackRef); +void Xil_SErrorAbortHandler(void *CallBackRef); +#else +extern void Xil_DataAbortHandler(void *CallBackRef); +extern void Xil_PrefetchAbortHandler(void *CallBackRef); +extern void Xil_UndefinedExceptionHandler(void *CallBackRef); +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ +/** +* @} End of "addtogroup arm_exception_apis". +*/ diff --git a/bsps/include/xil/arm/ARMv8/64bit/xil_system.h b/bsps/include/xil/arm/ARMv8/64bit/xil_system.h new file mode 100644 index 0000000000..7269e5c8d9 --- /dev/null +++ b/bsps/include/xil/arm/ARMv8/64bit/xil_system.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * COPYRIGHT (c) 2023. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_SHARED_XIL_SYSTEM_H +#define LIBBSP_SHARED_XIL_SYSTEM_H + +/* + * This file defines anything necessary for the Xilinx support infrastructure to + * function properly on a particular platform. + */ + +#endif diff --git a/bsps/include/xil/arm/ARMv8/64bit/xpseudo_asm.h b/bsps/include/xil/arm/ARMv8/64bit/xpseudo_asm.h new file mode 100644 index 0000000000..3c79b0b991 --- /dev/null +++ b/bsps/include/xil/arm/ARMv8/64bit/xpseudo_asm.h @@ -0,0 +1,56 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* @addtogroup a53_64_specific Cortex A53 64bit Processor Specific Include Files +* +* The xpseudo_asm.h includes xreg_cortexa53.h and xpseudo_asm_gcc.h. +* The xreg_cortexa53.h file contains definitions for inline assembler code. +* It provides inline definitions for Cortex A53 GPRs, SPRs and floating point +* registers. +* +* The xpseudo_asm_gcc.h contains the definitions for the most often used inline +* assembler instructions, available as macros. These can be very useful for +* tasks such as setting or getting special purpose registers, synchronization, +* or cache manipulation etc. These inline assembler instructions can be used +* from drivers and user applications written in C. +* +* @{ +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +* </pre> +* +******************************************************************************/ +#ifndef XPSEUDO_ASM_H +#define XPSEUDO_ASM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xreg_cortexa53.h" +#ifdef __clang__ +#include "xpseudo_asm_armclang.h" +#else +#include "xpseudo_asm_gcc.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* XPSEUDO_ASM_H */ +/** +* @} End of "addtogroup a53_64_specific". +*/ diff --git a/bsps/include/xil/arm/ARMv8/64bit/xreg_cortexa53.h b/bsps/include/xil/arm/ARMv8/64bit/xreg_cortexa53.h new file mode 100644 index 0000000000..b8ea1eac72 --- /dev/null +++ b/bsps/include/xil/arm/ARMv8/64bit/xreg_cortexa53.h @@ -0,0 +1,163 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xreg_cortexa53.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU compiler. +* +* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +* </pre> +* +******************************************************************************/ +#ifndef XREG_CORTEXA53_H +#define XREG_CORTEXA53_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + *@cond nocomments + */ + +/* GPRs */ +#define XREG_GPR0 x0 +#define XREG_GPR1 x1 +#define XREG_GPR2 x2 +#define XREG_GPR3 x3 +#define XREG_GPR4 x4 +#define XREG_GPR5 x5 +#define XREG_GPR6 x6 +#define XREG_GPR7 x7 +#define XREG_GPR8 x8 +#define XREG_GPR9 x9 +#define XREG_GPR10 x10 +#define XREG_GPR11 x11 +#define XREG_GPR12 x12 +#define XREG_GPR13 x13 +#define XREG_GPR14 x14 +#define XREG_GPR15 x15 +#define XREG_GPR16 x16 +#define XREG_GPR17 x17 +#define XREG_GPR18 x18 +#define XREG_GPR19 x19 +#define XREG_GPR20 x20 +#define XREG_GPR21 x21 +#define XREG_GPR22 x22 +#define XREG_GPR23 x23 +#define XREG_GPR24 x24 +#define XREG_GPR25 x25 +#define XREG_GPR26 x26 +#define XREG_GPR27 x27 +#define XREG_GPR28 x28 +#define XREG_GPR29 x29 +#define XREG_GPR30 x30 +#define XREG_CPSR cpsr + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_MODE_BITS 0x1FU +#define XREG_CPSR_EL3h_MODE 0xDU +#define XREG_CPSR_EL3t_MODE 0xCU +#define XREG_CPSR_EL2h_MODE 0x9U +#define XREG_CPSR_EL2t_MODE 0x8U +#define XREG_CPSR_EL1h_MODE 0x5U +#define XREG_CPSR_EL1t_MODE 0x4U +#define XREG_CPSR_EL0t_MODE 0x0U + +#define XREG_CPSR_IRQ_ENABLE 0x80U +#define XREG_CPSR_FIQ_ENABLE 0x40U + +#define XREG_CPSR_N_BIT 0x80000000U +#define XREG_CPSR_Z_BIT 0x40000000U +#define XREG_CPSR_C_BIT 0x20000000U +#define XREG_CPSR_V_BIT 0x10000000U + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24U) +#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (0X00000001U<<23U) +#define XREG_FPSID_ARCH_BIT (16U) +#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8U) +#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4U) +#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0U) +#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (0X00000001U << 31U) +#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) +#define XREG_FPSCR_C_BIT (0X00000001U << 29U) +#define XREG_FPSCR_V_BIT (0X00000001U << 28U) +#define XREG_FPSCR_QC (0X00000001U << 27U) +#define XREG_FPSCR_AHP (0X00000001U << 26U) +#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) +#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) +#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) +#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) +#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) +#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) +#define XREG_FPSCR_RMODE_BIT (22U) +#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20U) +#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16U) +#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (0X00000001U << 7U) +#define XREG_FPSCR_IXC (0X00000001U << 4U) +#define XREG_FPSCR_UFC (0X00000001U << 3U) +#define XREG_FPSCR_OFC (0X00000001U << 2U) +#define XREG_FPSCR_DZC (0X00000001U << 1U) +#define XREG_FPSCR_IOC (0X00000001U << 0U) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28U) +#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24U) +#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20U) +#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16U) +#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (0X00000012U) +#define XREG_MVFR0_EXEC_TRAP_MASK (0X0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8U) +#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4U) +#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0U) +#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (0X00000001U << 31U) +#define XREG_FPEXC_EN (0X00000001U << 30U) +#define XREG_FPEXC_DEX (0X00000001U << 29U) + + +#define XREG_CONTROL_DCACHE_BIT (0X00000001U<<2U) +#define XREG_CONTROL_ICACHE_BIT (0X00000001U<<12U) + +/** + *@endcond + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXA53_H */ diff --git a/bsps/include/xil/arm/cortexa9/xil_cache.h b/bsps/include/xil/arm/cortexa9/xil_cache.h new file mode 100644 index 0000000000..75cd6f6a8b --- /dev/null +++ b/bsps/include/xil/arm/cortexa9/xil_cache.h @@ -0,0 +1,105 @@ +/****************************************************************************** +* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions +* +* Cache functions provide access to cache related operations such as flush +* and invalidate for instruction and data caches. It gives option to perform +* the cache operations on a single cacheline, a range of memory and an entire +* cache. +* +* @{ +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a ecm 01/29/10 First release +* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance +* APIs. +* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain. +* </pre> +* +******************************************************************************/ + +/** +*@cond nocomments +*/ + +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __GNUC__ + +#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)); + +#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_SW :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)); + +#elif defined (__ICCARM__) + +#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)); + +#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \ + XREG_CP15_INVAL_DC_LINE_SW :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)); + +#endif + +/** +*@endcond +*/ + +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushRange(INTPTR adr, u32 len); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len); + +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup a9_cache_apis". +*/ diff --git a/bsps/include/xil/arm/cortexa9/xil_exception.h b/bsps/include/xil/arm/cortexa9/xil_exception.h new file mode 100644 index 0000000000..144d8423df --- /dev/null +++ b/bsps/include/xil/arm/cortexa9/xil_exception.h @@ -0,0 +1,408 @@ +/****************************************************************************** +* Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +* @addtogroup arm_exception_apis ARM Processor Exception Handling +* @{ +* ARM processors specific exception related APIs for cortex A53,A9 and R5 can +* utilized for enabling/disabling IRQ, registering/removing handler for +* exceptions or initializing exception vector table with null handler. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.2 pkp 28/05/15 First release +* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors +* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler. +* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler. +* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and +* Xil_ExceptionDisableMask macros to support legacy +* examples for Cortexa72 EL3 exception level. +* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and +* Xil_DisableNestedInterrupts macros for ARMv8. +* For Cortexa72, these macro's would not be supported +* at EL3, as Cortexa72 is using GIC-500(GICv3), which +* triggeres only FIQ at EL3. Fix for CR#1062506 +* 7.6 mus 09/17/21 Updated flag checking to fix warning reported with +* -Wundef compiler option CR#1110261 +* 7.7 mus 01/31/22 Few of the #defines in xil_exception.h in are treated +* in different way based on "versal" flag. In existing +* flow, this flag is defined only in xparameters.h and +* BSP compiler flags, it is not defined in application +* compiler flags. So, including xil_exception.h in +* application source file, without including +* xparameters.h results in incorrect behavior. +* Including xparameters.h in xil_exception.h to avoid +* such issues. It fixes CR#1120498. +* 7.7 sk 03/02/22 Define XExc_VectorTableEntry structure to fix +* misra_c_2012_rule_5_6 violation. +* 7.7 sk 03/02/22 Add XExc_VectorTable as extern to fix misra_c_2012_ +* rule_8_4 violation. +* </pre> +* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "bspconfig.h" +#include "xparameters.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0U +#if defined (__aarch64__) +#define XIL_EXCEPTION_ID_SYNC_INT 1U +#define XIL_EXCEPTION_ID_IRQ_INT 2U +#define XIL_EXCEPTION_ID_FIQ_INT 3U +#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U +#define XIL_EXCEPTION_ID_LAST 5U +#else +#define XIL_EXCEPTION_ID_RESET 0U +#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U +#define XIL_EXCEPTION_ID_SWI_INT 2U +#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U +#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U +#define XIL_EXCEPTION_ID_IRQ_INT 5U +#define XIL_EXCEPTION_ID_FIQ_INT 6U +#define XIL_EXCEPTION_ID_LAST 6U +#endif + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#if defined (versal) && !defined(ARMR5) && EL3 +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT +#else +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT +#endif + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +extern XExc_VectorTableEntry XExc_VectorTable[]; + +/** +*@endcond +*/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* @brief Enable Exceptions. +* +* @param Mask: Value for enabling the exceptions. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* +******************************************************************************/ +#if defined (versal) && !defined(ARMR5) && EL3 +/* + * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports + * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ + * ignoring argument passed by user. + */ +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL)) +#elif defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionEnableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \ + } +#endif +/****************************************************************************/ +/** +* @brief Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#if defined (versal) && !defined(ARMR5) && EL3 +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ) +#else +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) +#endif + +/****************************************************************************/ +/** +* @brief Disable Exceptions. +* +* @param Mask: Value for disabling the exceptions. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask) +* +******************************************************************************/ +#if defined (versal) && !defined(ARMR5) && EL3 +/* + * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports + * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ + * ignoring argument passed by user. + */ +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL)) +#elif defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionDisableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \ + } +#endif +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + +#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) ) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I bit in DAIF.This +* macro is defined for Cortex-A53 64 bit mode BSP configured to run +* at EL3.. However,it is not defined for Versal Cortex-A72 BSP +* configured to run at EL3. Reason is, Cortex-A72 is coupled +* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3. +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I bit +* is set as 1). To allow nesting of interrupts, this macro should be +* used. It clears the I bit. Once that bit is cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I +* bit, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs X1, ELR_EL3"); \ + __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \ + __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I bit in DAIF. This +* macro is defined for Cortex-A53 64 bit mode BSP configured to run +* at EL3. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ mode and +* hence sets back the I bit. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \ + __asm__ __volatile__ ("msr ELR_EL3, X1"); \ + __asm__ __volatile__ ("msr SPSR_EL3, X2"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1)) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I bit in DAIF.This +* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit +* BSP configured to run at EL1 NON SECURE +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I bit +* is set as 1). To allow nesting of interrupts, this macro should be +* used. It clears the I bit. Once that bit is cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I +* bit, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs X1, ELR_EL1"); \ + __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \ + __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I bit in DAIF. This +* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit +* BSP configured to run at EL1 NON SECURE +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ mode and +* hence sets back the I bit. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \ + __asm__ __volatile__ ("msr ELR_EL1, X1"); \ + __asm__ __volatile__ ("msr SPSR_EL1, X2"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +#elif (!defined (__aarch64__) && !defined (ARMA53_32)) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This +* API is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I and F +* are 1). To allow nesting of interrupts, this macro should be +* used. It clears the I and F bits by changing the ARM mode to +* system mode. Once these bits are cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I and +* F bits, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("mrs lr, spsr"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I and F bits. This API +* is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ/FIQ mode and +* hence sets back the I and F bits. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr spsr_cxsf, lr"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + +#endif +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); +extern void Xil_GetExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler *Handler, void **Data); + +extern void Xil_ExceptionInit(void); +#if defined (__aarch64__) +void Xil_SyncAbortHandler(void *CallBackRef); +void Xil_SErrorAbortHandler(void *CallBackRef); +#else +extern void Xil_DataAbortHandler(void *CallBackRef); +extern void Xil_PrefetchAbortHandler(void *CallBackRef); +extern void Xil_UndefinedExceptionHandler(void *CallBackRef); +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ +/** +* @} End of "addtogroup arm_exception_apis". +*/ diff --git a/bsps/include/xil/arm/cortexa9/xil_system.h b/bsps/include/xil/arm/cortexa9/xil_system.h new file mode 100644 index 0000000000..88d5b9aa6e --- /dev/null +++ b/bsps/include/xil/arm/cortexa9/xil_system.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * COPYRIGHT (c) 2023. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_SHARED_XIL_SYSTEM_H +#define LIBBSP_SHARED_XIL_SYSTEM_H + +/* + * This file defines anything necessary for the Xilinx support infrastructure to + * function properly on a particular platform. + */ +#define ARMA9 + +#endif diff --git a/bsps/include/xil/arm/cortexa9/xpseudo_asm.h b/bsps/include/xil/arm/cortexa9/xpseudo_asm.h new file mode 100644 index 0000000000..6d07851fa6 --- /dev/null +++ b/bsps/include/xil/arm/cortexa9/xpseudo_asm.h @@ -0,0 +1,60 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* @addtogroup a9_specific Cortex A9 Processor Specific Include Files +* +* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h. +* +* The xreg_cortexa9.h file contains definitions for inline assembler code. +* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers, +* co-processor registers and Debug registers. +* +* The xpseudo_asm_gcc.h contains the definitions for the most often used inline +* assembler instructions, available as macros. These can be very useful for +* tasks such as setting or getting special purpose registers, synchronization, +* or cache manipulation etc. These inline assembler instructions can be used +* from drivers and user applications written in C. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a ecm 10/18/09 First release +* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction. +* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain. +* </pre> +* +******************************************************************************/ +#ifndef XPSEUDO_ASM_H +#define XPSEUDO_ASM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xreg_cortexa9.h" +#ifdef __GNUC__ + #include "xpseudo_asm_gcc.h" +#elif defined (__ICCARM__) + #include "xpseudo_asm_iccarm.h" +#else + #include "xpseudo_asm_rvct.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* XPSEUDO_ASM_H */ +/** +* @} End of "addtogroup a9_specific". +*/ diff --git a/bsps/include/xil/arm/cortexa9/xreg_cortexa9.h b/bsps/include/xil/arm/cortexa9/xreg_cortexa9.h new file mode 100644 index 0000000000..2a4fff23f0 --- /dev/null +++ b/bsps/include/xil/arm/cortexa9/xreg_cortexa9.h @@ -0,0 +1,573 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xreg_cortexa9.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU, ARMCC compiler. +* +* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 1.00a ecm/sdm 10/20/09 First release +* </pre> +* +******************************************************************************/ +#ifndef XREG_CORTEXA9_H +#define XREG_CORTEXA9_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + *@cond nocomments + */ + +/* GPRs */ +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr + +/* Coprocessor number defines */ +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 + +/* Coprocessor control register defines */ +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_THUMB_MODE 0x20 +#define XREG_CPSR_MODE_BITS 0x1F +#define XREG_CPSR_SYSTEM_MODE 0x1F +#define XREG_CPSR_UNDEFINED_MODE 0x1B +#define XREG_CPSR_DATA_ABORT_MODE 0x17 +#define XREG_CPSR_SVC_MODE 0x13 +#define XREG_CPSR_IRQ_MODE 0x12 +#define XREG_CPSR_FIQ_MODE 0x11 +#define XREG_CPSR_USER_MODE 0x10 + +#define XREG_CPSR_IRQ_ENABLE 0x80 +#define XREG_CPSR_FIQ_ENABLE 0x40 + +#define XREG_CPSR_N_BIT 0x80000000 +#define XREG_CPSR_Z_BIT 0x40000000 +#define XREG_CPSR_C_BIT 0x20000000 +#define XREG_CPSR_V_BIT 0x10000000 + + +/* CP15 defines */ +#if defined (__GNUC__) || defined (__ICCARM__) +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" + +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" + +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" + +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" + +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" + +#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0" +#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1" +#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2" +#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3" + +#else /* RVCT */ +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0" +#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1" +#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2" +#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3" +#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5" + +#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0" +#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1" +#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2" +#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4" +#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5" +#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6" +#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7" + +#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0" +#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1" +#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2" +#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3" +#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4" + +#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0" +#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1" +#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7" + +#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0" +#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1" +#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2" + +#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0" +#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1" +#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2" +#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3" +#endif + +/* XREG_CP15_CONTROL bit defines */ +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U + +#if defined (__GNUC__) || defined (__ICCARM__) +/* C2 Register Defines */ +#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0" +#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1" +#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2" + +/* C3 Register Defines */ +#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0" + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" + +#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0" +#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6" + +#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0" + +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex A9. + */ +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" + +#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0" +#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1" +#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2" +#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3" + +#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4" +#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5" +#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6" +#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex A9. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" + +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" + +/* C8 Register Defines */ +#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0" +#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1" +#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2" +#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3" + +#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0" +#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1" +#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2" + +#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0" +#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1" +#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2" + +#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0" +#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1" +#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2" +#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3" + +/* C9 Register Defines */ +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" + +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" + +/* C10 Register Defines */ +#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0" + +#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0" +#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1" + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0" +#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1" + +#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0" +#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1" + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0" +#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0" + +#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2" +#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4" + +#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2" + +#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2" + +#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2" + +#else +/* C2 Register Defines */ +#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0" +#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1" +#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2" + +/* C3 Register Defines */ +#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0" + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0" +#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0" +#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "cp15:0:c7:c0:4" + +#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0" +#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6" + +#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0" + +#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex A9. + */ +#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1" +#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2" + +#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0" +#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1" +#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2" +#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3" + +#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4" +#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5" +#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6" +#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1" +#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex A9. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4" +#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1" + +#define XREG_CP15_NOP2 "cp15:0:c7:c13:1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2" + +/* C8 Register Defines */ +#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0" +#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1" +#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2" +#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3" + +#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0" +#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1" +#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2" + +#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0" +#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1" +#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2" + +#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0" +#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1" +#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2" +#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3" + +/* C9 Register Defines */ +#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0" +#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1" +#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2" +#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3" +#define XREG_CP15_SW_INC "cp15:0:c9:c12:4" +#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0" +#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1" +#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2" + +#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0" +#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1" +#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2" + +/* C10 Register Defines */ +#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0" + +#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0" +#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1" + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0" +#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1" + +#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0" +#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1" + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1" +#define USER_RW_THREAD_PID "cp15:0:c13:c0:2" +#define USER_RO_THREAD_PID "cp15:0:c13:c0:3" +#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0" +#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0" + +#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2" +#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4" + +#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2" + +#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2" + +#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2" +#endif + + +/* MPE register definitions */ +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24) +#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (1<<23) +#define XREG_FPSID_ARCH_BIT (16) +#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8) +#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4) +#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0) +#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (1 << 31) +#define XREG_FPSCR_Z_BIT (1 << 30) +#define XREG_FPSCR_C_BIT (1 << 29) +#define XREG_FPSCR_V_BIT (1 << 28) +#define XREG_FPSCR_QC (1 << 27) +#define XREG_FPSCR_AHP (1 << 26) +#define XREG_FPSCR_DEFAULT_NAN (1 << 25) +#define XREG_FPSCR_FLUSHTOZERO (1 << 24) +#define XREG_FPSCR_ROUND_NEAREST (0 << 22) +#define XREG_FPSCR_ROUND_PLUSINF (1 << 22) +#define XREG_FPSCR_ROUND_MINUSINF (2 << 22) +#define XREG_FPSCR_ROUND_TOZERO (3 << 22) +#define XREG_FPSCR_RMODE_BIT (22) +#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20) +#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16) +#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (1 << 7) +#define XREG_FPSCR_IXC (1 << 4) +#define XREG_FPSCR_UFC (1 << 3) +#define XREG_FPSCR_OFC (1 << 2) +#define XREG_FPSCR_DZC (1 << 1) +#define XREG_FPSCR_IOC (1 << 0) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28) +#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24) +#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20) +#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16) +#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12) +#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8) +#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4) +#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0) +#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (1 << 31) +#define XREG_FPEXC_EN (1 << 30) +#define XREG_FPEXC_DEX (1 << 29) + + +/** + *@endcond + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXA9_H */ diff --git a/bsps/include/xil/arm/cortexr5/xil_cache.h b/bsps/include/xil/arm/cortexr5/xil_cache.h new file mode 100644 index 0000000000..fcc74504db --- /dev/null +++ b/bsps/include/xil/arm/cortexr5/xil_cache.h @@ -0,0 +1,95 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* @addtogroup r5_cache_apis Cortex R5 Processor Cache Functions +* +* Cache functions provide access to cache related operations such as flush +* and invalidate for instruction and data caches. It gives option to perform +* the cache operations on a single cacheline, a range of memory and an entire +* cache. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 5.00 pkp 02/20/14 First release +* 6.2 mus 01/27/17 Updated to support IAR compiler +* </pre> +* +******************************************************************************/ +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + *@cond nocomments + */ + +#if defined (__GNUC__) +#define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) + +#define asm_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) + +#define asm_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) + +#define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) +#elif defined (__ICCARM__) +#define asm_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) + +#define asm_clean_inval_dc_line_sw(param) __asm volatile("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) + +#define asm_clean_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) + +#define asm_inval_ic_line_mva_pou(param) __asm volatile("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) +#endif + +/** + *@endcond + */ + +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushRange(INTPTR adr, u32 len); +void Xil_DCacheInvalidateLine(INTPTR adr); +void Xil_DCacheFlushLine(INTPTR adr); +void Xil_DCacheStoreLine(INTPTR adr); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len); +void Xil_ICacheInvalidateLine(INTPTR adr); + +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup r5_cache_apis". +*/ diff --git a/bsps/include/xil/arm/cortexr5/xil_exception.h b/bsps/include/xil/arm/cortexr5/xil_exception.h new file mode 100644 index 0000000000..144d8423df --- /dev/null +++ b/bsps/include/xil/arm/cortexr5/xil_exception.h @@ -0,0 +1,408 @@ +/****************************************************************************** +* Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +* @addtogroup arm_exception_apis ARM Processor Exception Handling +* @{ +* ARM processors specific exception related APIs for cortex A53,A9 and R5 can +* utilized for enabling/disabling IRQ, registering/removing handler for +* exceptions or initializing exception vector table with null handler. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.2 pkp 28/05/15 First release +* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors +* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler. +* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler. +* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and +* Xil_ExceptionDisableMask macros to support legacy +* examples for Cortexa72 EL3 exception level. +* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and +* Xil_DisableNestedInterrupts macros for ARMv8. +* For Cortexa72, these macro's would not be supported +* at EL3, as Cortexa72 is using GIC-500(GICv3), which +* triggeres only FIQ at EL3. Fix for CR#1062506 +* 7.6 mus 09/17/21 Updated flag checking to fix warning reported with +* -Wundef compiler option CR#1110261 +* 7.7 mus 01/31/22 Few of the #defines in xil_exception.h in are treated +* in different way based on "versal" flag. In existing +* flow, this flag is defined only in xparameters.h and +* BSP compiler flags, it is not defined in application +* compiler flags. So, including xil_exception.h in +* application source file, without including +* xparameters.h results in incorrect behavior. +* Including xparameters.h in xil_exception.h to avoid +* such issues. It fixes CR#1120498. +* 7.7 sk 03/02/22 Define XExc_VectorTableEntry structure to fix +* misra_c_2012_rule_5_6 violation. +* 7.7 sk 03/02/22 Add XExc_VectorTable as extern to fix misra_c_2012_ +* rule_8_4 violation. +* </pre> +* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "bspconfig.h" +#include "xparameters.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0U +#if defined (__aarch64__) +#define XIL_EXCEPTION_ID_SYNC_INT 1U +#define XIL_EXCEPTION_ID_IRQ_INT 2U +#define XIL_EXCEPTION_ID_FIQ_INT 3U +#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U +#define XIL_EXCEPTION_ID_LAST 5U +#else +#define XIL_EXCEPTION_ID_RESET 0U +#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U +#define XIL_EXCEPTION_ID_SWI_INT 2U +#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U +#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U +#define XIL_EXCEPTION_ID_IRQ_INT 5U +#define XIL_EXCEPTION_ID_FIQ_INT 6U +#define XIL_EXCEPTION_ID_LAST 6U +#endif + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#if defined (versal) && !defined(ARMR5) && EL3 +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT +#else +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT +#endif + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +extern XExc_VectorTableEntry XExc_VectorTable[]; + +/** +*@endcond +*/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* @brief Enable Exceptions. +* +* @param Mask: Value for enabling the exceptions. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* +******************************************************************************/ +#if defined (versal) && !defined(ARMR5) && EL3 +/* + * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports + * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ + * ignoring argument passed by user. + */ +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL)) +#elif defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionEnableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \ + } +#endif +/****************************************************************************/ +/** +* @brief Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#if defined (versal) && !defined(ARMR5) && EL3 +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ) +#else +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) +#endif + +/****************************************************************************/ +/** +* @brief Disable Exceptions. +* +* @param Mask: Value for disabling the exceptions. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask) +* +******************************************************************************/ +#if defined (versal) && !defined(ARMR5) && EL3 +/* + * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports + * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ + * ignoring argument passed by user. + */ +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL)) +#elif defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionDisableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \ + } +#endif +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + +#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) ) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I bit in DAIF.This +* macro is defined for Cortex-A53 64 bit mode BSP configured to run +* at EL3.. However,it is not defined for Versal Cortex-A72 BSP +* configured to run at EL3. Reason is, Cortex-A72 is coupled +* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3. +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I bit +* is set as 1). To allow nesting of interrupts, this macro should be +* used. It clears the I bit. Once that bit is cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I +* bit, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs X1, ELR_EL3"); \ + __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \ + __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I bit in DAIF. This +* macro is defined for Cortex-A53 64 bit mode BSP configured to run +* at EL3. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ mode and +* hence sets back the I bit. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \ + __asm__ __volatile__ ("msr ELR_EL3, X1"); \ + __asm__ __volatile__ ("msr SPSR_EL3, X2"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1)) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I bit in DAIF.This +* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit +* BSP configured to run at EL1 NON SECURE +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I bit +* is set as 1). To allow nesting of interrupts, this macro should be +* used. It clears the I bit. Once that bit is cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I +* bit, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs X1, ELR_EL1"); \ + __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \ + __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I bit in DAIF. This +* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit +* BSP configured to run at EL1 NON SECURE +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ mode and +* hence sets back the I bit. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \ + __asm__ __volatile__ ("msr ELR_EL1, X1"); \ + __asm__ __volatile__ ("msr SPSR_EL1, X2"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +#elif (!defined (__aarch64__) && !defined (ARMA53_32)) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This +* API is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I and F +* are 1). To allow nesting of interrupts, this macro should be +* used. It clears the I and F bits by changing the ARM mode to +* system mode. Once these bits are cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I and +* F bits, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("mrs lr, spsr"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I and F bits. This API +* is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ/FIQ mode and +* hence sets back the I and F bits. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr spsr_cxsf, lr"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + +#endif +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); +extern void Xil_GetExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler *Handler, void **Data); + +extern void Xil_ExceptionInit(void); +#if defined (__aarch64__) +void Xil_SyncAbortHandler(void *CallBackRef); +void Xil_SErrorAbortHandler(void *CallBackRef); +#else +extern void Xil_DataAbortHandler(void *CallBackRef); +extern void Xil_PrefetchAbortHandler(void *CallBackRef); +extern void Xil_UndefinedExceptionHandler(void *CallBackRef); +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ +/** +* @} End of "addtogroup arm_exception_apis". +*/ diff --git a/bsps/include/xil/arm/cortexr5/xil_mpu.h b/bsps/include/xil/arm/cortexr5/xil_mpu.h new file mode 100644 index 0000000000..af3d52d795 --- /dev/null +++ b/bsps/include/xil/arm/cortexr5/xil_mpu.h @@ -0,0 +1,117 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xil_mmu.h +* +* @addtogroup r5_mpu_apis Cortex R5 Processor MPU specific APIs +* +* MPU functions provides access to MPU operations such as enable MPU, disable +* MPU and set attribute for section of memory. +* Boot code invokes Init_MPU function to configure the MPU. A total of 10 MPU +* regions are allocated with another 6 being free for users. Overview of the +* memory attributes for different MPU regions is as given below, +* +*| | Memory Range | Attributes of MPURegion | +*|-----------------------|-------------------------|-----------------------------| +*| DDR | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable | +*| PL | 0x80000000 - 0xBFFFFFFF | Strongly Ordered | +*| QSPI | 0xC0000000 - 0xDFFFFFFF | Device Memory | +*| PCIe | 0xE0000000 - 0xEFFFFFFF | Device Memory | +*| STM_CORESIGHT | 0xF8000000 - 0xF8FFFFFF | Device Memory | +*| RPU_R5_GIC | 0xF9000000 - 0xF90FFFFF | Device memory | +*| FPS | 0xFD000000 - 0xFDFFFFFF | Device Memory | +*| LPS | 0xFE000000 - 0xFFFFFFFF | Device Memory | +*| OCM | 0xFFFC0000 - 0xFFFFFFFF | Normal write-back Cacheable | +* +* +* @note +* For a system where DDR is less than 2GB, region after DDR and before PL is +* marked as undefined in translation table. Memory range 0xFE000000-0xFEFFFFFF is +* allocated for upper LPS slaves, where as memory region 0xFF000000-0xFFFFFFFF is +* allocated for lower LPS slaves. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 5.00 pkp 02/10/14 Initial version +* 6.4 asa 08/16/17 Added many APIs for MPU access to make MPU usage +* user-friendly. The APIs added are: Xil_UpdateMPUConfig, +* Xil_GetMPUConfig, Xil_GetNumOfFreeRegions, +* Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum, +* Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and +* Xil_InitializeExistingMPURegConfig. +* Added a new array of structure of type XMpuConfig to +* represent the MPU configuration table. +* 7.7 sk 01/10/22 Modify Xil_SetTlbAttributes function argument name to fix +* misra_c_2012_rule_8_3 violation. +* </pre> +* + +* +* +******************************************************************************/ +/** + *@cond nocomments + */ + +#ifndef XIL_MPU_H +#define XIL_MPU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +#include "xil_types.h" +/***************************** Include Files *********************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ +#define MPU_REG_DISABLED 0U +#define MPU_REG_ENABLED 1U +#define MAX_POSSIBLE_MPU_REGS 16U +/**************************** Type Definitions *******************************/ +struct XMpuConfig{ + u32 RegionStatus; /* Enabled or disabled */ + INTPTR BaseAddress;/* MPU region base address */ + u64 Size; /* MPU region size address */ + u32 Attribute; /* MPU region size attribute */ +}; + +typedef struct XMpuConfig XMpu_Config[MAX_POSSIBLE_MPU_REGS]; + +extern XMpu_Config Mpu_Config; +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +/** + *@endcond + */ + +void Xil_SetTlbAttributes(INTPTR addr, u32 attrib); +void Xil_EnableMPU(void); +void Xil_DisableMPU(void); +u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib); +u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib); +void Xil_GetMPUConfig (XMpu_Config mpuconfig); +u32 Xil_GetNumOfFreeRegions (void); +u32 Xil_GetNextMPURegion(void); +u32 Xil_DisableMPURegionByRegNum (u32 reg_num); +u16 Xil_GetMPUFreeRegMask (void); +u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib); +void* Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MPU_H */ +/** +* @} End of "addtogroup r5_mpu_apis". +*/ diff --git a/bsps/include/xil/arm/cortexr5/xil_system.h b/bsps/include/xil/arm/cortexr5/xil_system.h new file mode 100644 index 0000000000..4274d6916a --- /dev/null +++ b/bsps/include/xil/arm/cortexr5/xil_system.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * COPYRIGHT (c) 2023. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_SHARED_XIL_SYSTEM_H +#define LIBBSP_SHARED_XIL_SYSTEM_H + +/* + * This file defines anything necessary for the Xilinx support infrastructure to + * function properly + */ +#define ARMR5 + +#endif diff --git a/bsps/include/xil/arm/cortexr5/xpseudo_asm.h b/bsps/include/xil/arm/cortexr5/xpseudo_asm.h new file mode 100644 index 0000000000..46b704539c --- /dev/null +++ b/bsps/include/xil/arm/cortexr5/xpseudo_asm.h @@ -0,0 +1,60 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* @addtogroup r5_specific Cortex R5 Processor Specific Include Files +* +* The xpseudo_asm.h includes xreg_cortexr5.h and xpseudo_asm_gcc.h. +* +* The xreg_cortexr5.h file contains definitions for inline assembler code. +* It provides inline definitions for Cortex R5 GPRs, SPRs,co-processor +* registers and Debug register +* +* The xpseudo_asm_gcc.h contains the definitions for the most often used +* inline assembler instructions, available as macros. These can be very +* useful for tasks such as setting or getting special purpose registers, +* synchronization,or cache manipulation. These inline assembler instructions +* can be used from drivers and user applications written in C. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 5.00 pkp 02/10/14 Initial version +* 6.2 mus 01/27/17 Updated to support IAR compiler +* 7.3 dp 06/25/20 Initial version for armclang +* </pre> +* +******************************************************************************/ +#ifndef XPSEUDO_ASM_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xreg_cortexr5.h" +#if defined (__clang__) +#include "xpseudo_asm_armclang.h" +#elif defined (__GNUC__) +#include "xpseudo_asm_gcc.h" +#elif defined (__ICCARM__) +#include "xpseudo_asm_iccarm.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* XPSEUDO_ASM_H */ +/** +* @} End of "addtogroup r5_specific". +*/ diff --git a/bsps/include/xil/arm/cortexr5/xreg_cortexr5.h b/bsps/include/xil/arm/cortexr5/xreg_cortexr5.h new file mode 100644 index 0000000000..8034672636 --- /dev/null +++ b/bsps/include/xil/arm/cortexr5/xreg_cortexr5.h @@ -0,0 +1,429 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xreg_cortexr5.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU, IAR, ARMCC compiler. +* +* All of the ARM Cortex R5 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.00 pkp 02/10/14 Initial version +* 7.7 sk 01/10/22 Update PRIV_RW_USER_RW macro from unsigned to unsigned +* long to fix misra_c_2012_rule_12_2 violation. +* </pre> +* +******************************************************************************/ +/** + *@cond nocomments + */ + +#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */ +#define XREG_CORTEXR5_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* GPRs */ +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr + +/* Coprocessor number defines */ +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 + +/* Coprocessor control register defines */ +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_THUMB_MODE 0x20U +#define XREG_CPSR_MODE_BITS 0x1FU +#define XREG_CPSR_SYSTEM_MODE 0x1FU +#define XREG_CPSR_UNDEFINED_MODE 0x1BU +#define XREG_CPSR_DATA_ABORT_MODE 0x17U +#define XREG_CPSR_SVC_MODE 0x13U +#define XREG_CPSR_IRQ_MODE 0x12U +#define XREG_CPSR_FIQ_MODE 0x11U +#define XREG_CPSR_USER_MODE 0x10U + +#define XREG_CPSR_IRQ_ENABLE 0x80U +#define XREG_CPSR_FIQ_ENABLE 0x40U + +#define XREG_CPSR_N_BIT 0x80000000U +#define XREG_CPSR_Z_BIT 0x40000000U +#define XREG_CPSR_C_BIT 0x20000000U +#define XREG_CPSR_V_BIT 0x10000000U + +/*MPU region definitions*/ +#define REGION_32B 0x00000004U +#define REGION_64B 0x00000005U +#define REGION_128B 0x00000006U +#define REGION_256B 0x00000007U +#define REGION_512B 0x00000008U +#define REGION_1K 0x00000009U +#define REGION_2K 0x0000000AU +#define REGION_4K 0x0000000BU +#define REGION_8K 0x0000000CU +#define REGION_16K 0x0000000DU +#define REGION_32K 0x0000000EU +#define REGION_64K 0x0000000FU +#define REGION_128K 0x00000010U +#define REGION_256K 0x00000011U +#define REGION_512K 0x00000012U +#define REGION_1M 0x00000013U +#define REGION_2M 0x00000014U +#define REGION_4M 0x00000015U +#define REGION_8M 0x00000016U +#define REGION_16M 0x00000017U +#define REGION_32M 0x00000018U +#define REGION_64M 0x00000019U +#define REGION_128M 0x0000001AU +#define REGION_256M 0x0000001BU +#define REGION_512M 0x0000001CU +#define REGION_1G 0x0000001DU +#define REGION_2G 0x0000001EU +#define REGION_4G 0x0000001FU + +#define REGION_EN 0x00000001U + + + +#define SHAREABLE 0x00000004U /*shareable */ +#define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/ + +#define DEVICE_SHARED 0x00000001U /*device, shareable*/ +#define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/ + +#define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/ +#define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/ + +#define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/ +#define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/ + +#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/ +#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/ + +#define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/ +#define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/ + +/* inner and outer cache policies can be combined for different combinations */ + +#define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/ +#define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/ +#define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/ +#define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/ + +#define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/ +#define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/ +#define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/ +#define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/ + +#define NO_ACCESS (0x00000000U<<8U) /*No access*/ +#define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/ +#define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/ +#define PRIV_RW_USER_RW (0x00000003UL<<8U) /*Full Access*/ +#define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/ +#define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/ + +#define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/ + + +/* CP15 defines */ + +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" + +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" + +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" +#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5" + +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" + +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" + + +/* XREG_CP15_CONTROL bit defines */ +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U +/* C2 Register Defines */ +/* Not Used */ + +/* C3 Register Defines */ +/* Not Used */ + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" + +#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0" +#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2" +#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4" + +#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" + +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex R5. + */ +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" +#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" + + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" + +#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0" +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex R5. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" + +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" + +/* C8 Register Defines */ +/* Not Used */ + + +/* C9 Register Defines */ + +#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1" +#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0" +#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0" + +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" + +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" + +/* C10 Register Defines */ +/* Not used */ + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +/* Not used */ + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0" + + + + +/* MPE register definitions */ +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24U) +#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (0X00000001U << 23U) +#define XREG_FPSID_ARCH_BIT (16U) +#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8U) +#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4U) +#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0U) +#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (0X00000001U << 31U) +#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) +#define XREG_FPSCR_C_BIT (0X00000001U << 29U) +#define XREG_FPSCR_V_BIT (0X00000001U << 28U) +#define XREG_FPSCR_QC (0X00000001U << 27U) +#define XREG_FPSCR_AHP (0X00000001U << 26U) +#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) +#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) +#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) +#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) +#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) +#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) +#define XREG_FPSCR_RMODE_BIT (22U) +#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20U) +#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16U) +#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (0X00000001U << 7U) +#define XREG_FPSCR_IXC (0X00000001U << 4U) +#define XREG_FPSCR_UFC (0X00000001U << 3U) +#define XREG_FPSCR_OFC (0X00000001U << 2U) +#define XREG_FPSCR_DZC (0X00000001U << 1U) +#define XREG_FPSCR_IOC (0X00000001U << 0U) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28U) +#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24U) +#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20U) +#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16U) +#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12U) +#define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8U) +#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4U) +#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0U) +#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (0X00000001U << 31U) +#define XREG_FPEXC_EN (0X00000001U << 30U) +#define XREG_FPEXC_DEX (0X00000001U << 29U) + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXR5_H */ + +/** + *@endcond + */ diff --git a/bsps/include/xil/bspconfig.h b/bsps/include/xil/bspconfig.h new file mode 100644 index 0000000000..55a8df3add --- /dev/null +++ b/bsps/include/xil/bspconfig.h @@ -0,0 +1 @@ +/* Intentional blank stub file for Xilinx driver compatibility. */ diff --git a/bsps/include/xil/microblaze/xil_cache.h b/bsps/include/xil/microblaze/xil_cache.h new file mode 100644 index 0000000000..d279665751 --- /dev/null +++ b/bsps/include/xil/microblaze/xil_cache.h @@ -0,0 +1,392 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* @addtogroup microblaze_cache_apis Microblaze Cache APIs +* @{ +* +* +* The xil_cache.h file contains cache related driver functions (or macros) +* that can be used to access the device. The user should refer to the +* hardware device specification for more details of the device operation. +* The functions in this header file can be used across all Xilinx supported +* processors. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00 hbm 07/28/09 Initial release +* 3.02a sdm 10/24/11 Updated the file to include xparameters.h so that +* the correct cache flush routines are used based on +* whether the write-back or write-through caches are +* used (cr #630532). +* 3.10a asa 05/04/13 This version of MicroBlaze BSP adds support for system +* cache/L2 cache. The existing/old APIs/macros in this +* file are renamed to imply that they deal with L1 cache. +* New macros/APIs are added to address similar features for +* L2 cache. Users can include this file in their application +* to use the various cache related APIs. These changes are +* done for implementing PR #697214. +* +* </pre> +* +* +******************************************************************************/ + +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#if defined XENV_VXWORKS +/* VxWorks environment */ +#error "Unknown processor / architecture. Must be PPC for VxWorks." +#else +/* standalone environment */ + +#include "mb_interface.h" +#include "xil_types.h" +#include "xparameters.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/** +* +* @brief Invalidate the entire L1 data cache. If the cacheline is modified +* (dirty), the modified contents are lost. +* +* +* @return None. +* +* @note Processor must be in real mode. +****************************************************************************/ +#define Xil_L1DCacheInvalidate() microblaze_invalidate_dcache() + +/****************************************************************************/ +/** +* +* @brief Invalidate the entire L2 data cache. If the cacheline is modified +* (dirty),the modified contents are lost. +* +* @return None. +* +* @note Processor must be in real mode. +****************************************************************************/ +#define Xil_L2CacheInvalidate() microblaze_invalidate_cache_ext() + +/****************************************************************************/ +/** +* +* @brief Invalidate the L1 data cache for the given address range. +* If the bytes specified by the address (Addr) are cached by the L1 +* data cache, the cacheline containing that byte is invalidated.If +* the cacheline is modified (dirty), the modified contents are lost. +* +* @param Addr is address of range to be invalidated. +* @param Len is the length in bytes to be invalidated. +* +* @return None. +* +* @note Processor must be in real mode. +****************************************************************************/ +#define Xil_L1DCacheInvalidateRange(Addr, Len) \ + microblaze_invalidate_dcache_range((Addr), (Len)) + +/****************************************************************************/ +/** +* +* @brief Invalidate the L1 data cache for the given address range. +* If the bytes specified by the address (Addr) are cached by the +* L1 data cache, the cacheline containing that byte is invalidated. +* If the cacheline is modified (dirty), the modified contents are lost. +* +* @param Addr: address of range to be invalidated. +* @param Len: length in bytes to be invalidated. +* +* @return None. +* +* @note Processor must be in real mode. +****************************************************************************/ +#define Xil_L2CacheInvalidateRange(Addr, Len) \ + microblaze_invalidate_cache_ext_range((Addr), (Len)) + +/****************************************************************************/ +/** +* @brief Flush the L1 data cache for the given address range. +* If the bytes specified by the address (Addr) are cached by the +* data cache, and is modified (dirty), the cacheline will be written +* to system memory.The cacheline will also be invalidated. +* +* @param Addr: the starting address of the range to be flushed. +* @param Len: length in byte to be flushed. +* +* @return None. +* +****************************************************************************/ +#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) +# define Xil_L1DCacheFlushRange(Addr, Len) \ + microblaze_flush_dcache_range((Addr), (Len)) +#else +# define Xil_L1DCacheFlushRange(Addr, Len) \ + microblaze_invalidate_dcache_range((Addr), (Len)) +#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */ + +/****************************************************************************/ +/** +* @brief Flush the L2 data cache for the given address range. +* If the bytes specified by the address (Addr) are cached by the +* data cache, and is modified (dirty), the cacheline will be +* written to system memory. The cacheline will also be invalidated. +* +* @param Addr: the starting address of the range to be flushed. +* @param Len: length in byte to be flushed. +* +* @return None. +* +****************************************************************************/ +#define Xil_L2CacheFlushRange(Addr, Len) \ + microblaze_flush_cache_ext_range((Addr), (Len)) + +/****************************************************************************/ +/** +* @brief Flush the entire L1 data cache. If any cacheline is dirty, the +* cacheline will be written to system memory. The entire data cache +* will be invalidated. +* +* @return None. +* +****************************************************************************/ +#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) +# define Xil_L1DCacheFlush() microblaze_flush_dcache() +#else +# define Xil_L1DCacheFlush() microblaze_invalidate_dcache() +#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */ + +/****************************************************************************/ +/** +* @brief Flush the entire L2 data cache. If any cacheline is dirty, the +* cacheline will be written to system memory. The entire data cache +* will be invalidated. +* +* @return None. +* +****************************************************************************/ +#define Xil_L2CacheFlush() microblaze_flush_cache_ext() + +/****************************************************************************/ +/** +* +* @brief Invalidate the instruction cache for the given address range. +* +* @param Addr is address of ragne to be invalidated. +* @param Len is the length in bytes to be invalidated. +* +* @return None. +* +****************************************************************************/ +#define Xil_L1ICacheInvalidateRange(Addr, Len) \ + microblaze_invalidate_icache_range((Addr), (Len)) + +/****************************************************************************/ +/** +* +* @brief Invalidate the entire instruction cache. +* +* @return None. +* +****************************************************************************/ +#define Xil_L1ICacheInvalidate() \ + microblaze_invalidate_icache() + + +/****************************************************************************/ +/** +* +* @brief Enable the L1 data cache. +* +* @return None. +* +* @note This is processor specific. +* +****************************************************************************/ +#define Xil_L1DCacheEnable() \ + microblaze_enable_dcache() + +/****************************************************************************/ +/** +* +* @brief Disable the L1 data cache. +* +* @return None. +* +* @note This is processor specific. +* +****************************************************************************/ +#define Xil_L1DCacheDisable() \ + microblaze_disable_dcache() + +/****************************************************************************/ +/** +* +* @brief Enable the instruction cache. +* +* @return None. +* +* @note This is processor specific. +* +****************************************************************************/ +#define Xil_L1ICacheEnable() \ + microblaze_enable_icache() + +/****************************************************************************/ +/** +* +* @brief Disable the L1 Instruction cache. +* +* @return None. +* +* @note This is processor specific. +* +****************************************************************************/ +#define Xil_L1ICacheDisable() \ + microblaze_disable_icache() + +/****************************************************************************/ +/** +* +* @brief Enable the data cache. +* +* @return None. +* +****************************************************************************/ +#define Xil_DCacheEnable() Xil_L1DCacheEnable() + +/****************************************************************************/ +/** +* +* @brief Enable the instruction cache. +* +* @return None. +* +* +****************************************************************************/ +#define Xil_ICacheEnable() Xil_L1ICacheEnable() + +/****************************************************************************/ +/** +* +* @brief Invalidate the entire Data cache. +* +* @return None. +* +****************************************************************************/ +#define Xil_DCacheInvalidate() \ + Xil_L2CacheInvalidate(); \ + Xil_L1DCacheInvalidate(); + + +/****************************************************************************/ +/** +* +* @brief Invalidate the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the +* Data cache, the cacheline containing that byte is invalidated. +* If the cacheline is modified (dirty), the modified contents are +* lost and are NOT written to system memory before the line is +* invalidated. +* +* @param Addr: Start address of range to be invalidated. +* @param Len: Length of range to be invalidated in bytes. +* +* @return None. +* +****************************************************************************/ +#define Xil_DCacheInvalidateRange(Addr, Len) \ + Xil_L2CacheInvalidateRange((Addr), (Len)); \ + Xil_L1DCacheInvalidateRange((Addr), (Len)); + + +/****************************************************************************/ +/** +* +* @brief Flush the entire Data cache. +* +* @return None. +* +****************************************************************************/ +#define Xil_DCacheFlush() \ + Xil_L2CacheFlush(); \ + Xil_L1DCacheFlush(); + +/****************************************************************************/ +/** +* @brief Flush the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the +* Data cache, the cacheline containing that byte is invalidated. +* If the cacheline is modified (dirty), the written to system +* memory first before the before the line is invalidated. +* +* @param Addr: Start address of range to be flushed. +* @param Len: Length of range to be flushed in bytes. +* +* @return None. +* +****************************************************************************/ +#define Xil_DCacheFlushRange(Addr, Len) \ + Xil_L2CacheFlushRange((Addr), (Len)); \ + Xil_L1DCacheFlushRange((Addr), (Len)); + + +/****************************************************************************/ +/** +* @brief Invalidate the entire instruction cache. +* +* @return None. +* +****************************************************************************/ +#define Xil_ICacheInvalidate() \ + Xil_L2CacheInvalidate(); \ + Xil_L1ICacheInvalidate(); + + +/****************************************************************************/ +/** +* @brief Invalidate the instruction cache for the given address range. +* If the bytes specified by the address (adr) are cached by the +* Data cache, the cacheline containing that byte is invalidated. +* If the cacheline is modified (dirty), the modified contents are +* lost and are NOT written to system memory before the line is +* invalidated. +* +* @param Addr: Start address of ragne to be invalidated. +* @param Len: Length of range to be invalidated in bytes. +* +* @return None. +* +****************************************************************************/ +#define Xil_ICacheInvalidateRange(Addr, Len) \ + Xil_L2CacheInvalidateRange((Addr), (Len)); \ + Xil_L1ICacheInvalidateRange((Addr), (Len)); + +void Xil_DCacheDisable(void); +void Xil_ICacheDisable(void); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif +/** +* @} End of "addtogroup microblaze_cache_apis". +*/ diff --git a/bsps/include/xil/microblaze/xil_exception.h b/bsps/include/xil/microblaze/xil_exception.h new file mode 100644 index 0000000000..571acd9624 --- /dev/null +++ b/bsps/include/xil/microblaze/xil_exception.h @@ -0,0 +1,112 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* @addtogroup microblaze_exception_apis Microblaze Exception APIs +* @{ +* +* The xil_exception.h file, available in the <install-directory>/src/microblaze folder, +* contains Microblaze specific exception related APIs and macros. Application programs +* can use these APIs for various exception related operations. For example, enable exception, +* disable exception, register exception hander. +* +* @note To use exception related functions, xil_exception.h must be added in source code +* +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00 hbm 07/28/09 Initial release +* +* </pre> +* +******************************************************************************/ + +/** + *@cond nocomments + */ +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* + * These constants are specific to Microblaze processor. + */ + +#define XIL_EXCEPTION_ID_FIRST 0U +#define XIL_EXCEPTION_ID_FSL 0U +#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS 1U +#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE 2U +#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION 3U +#define XIL_EXCEPTION_ID_IPLB_EXCEPTION 3U +#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION 4U +#define XIL_EXCEPTION_ID_DPLB_EXCEPTION 4U +#define XIL_EXCEPTION_ID_DIV_BY_ZERO 5U +#define XIL_EXCEPTION_ID_FPU 6U +#define XIL_EXCEPTION_ID_STACK_VIOLATION 7U +#define XIL_EXCEPTION_ID_MMU 7U +#define XIL_EXCEPTION_ID_LAST XIL_EXCEPTION_ID_MMU + +/* + * XIL_EXCEPTION_ID_INT is defined for all processors, but with different value. + */ +#define XIL_EXCEPTION_ID_INT 16U /** + * exception ID for interrupt + */ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *Data); + +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Id); + +extern void Xil_ExceptionInit(void); +extern void Xil_ExceptionEnable(void); +extern void Xil_ExceptionDisable(void); + +#ifdef __cplusplus +} +#endif + +#endif + +/** + *@endcond + */ + +/** +* @} End of "addtogroup microblaze_exception_apis". +*/ diff --git a/bsps/include/xil/microblaze/xil_system.h b/bsps/include/xil/microblaze/xil_system.h new file mode 100644 index 0000000000..7269e5c8d9 --- /dev/null +++ b/bsps/include/xil/microblaze/xil_system.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * COPYRIGHT (c) 2023. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_SHARED_XIL_SYSTEM_H +#define LIBBSP_SHARED_XIL_SYSTEM_H + +/* + * This file defines anything necessary for the Xilinx support infrastructure to + * function properly on a particular platform. + */ + +#endif diff --git a/bsps/include/xil/sleep.h b/bsps/include/xil/sleep.h new file mode 100644 index 0000000000..5cab0b5a1b --- /dev/null +++ b/bsps/include/xil/sleep.h @@ -0,0 +1 @@ +#include <sys/unistd.h> diff --git a/bsps/include/xil/xbasic_types.h b/bsps/include/xil/xbasic_types.h new file mode 100644 index 0000000000..99b137503e --- /dev/null +++ b/bsps/include/xil/xbasic_types.h @@ -0,0 +1,113 @@ +/****************************************************************************** +* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xbasic_types.h +* +* +* @note Dummy File for backwards compatibility +* + +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility +* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8 +* 7.0 aru 02/06/19 Included stdint.h and stddef.h +* </pre> +* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XBASIC_TYPES_H /* prevent circular inclusions */ +#define XBASIC_TYPES_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> +#include <stddef.h> + +/** @name Legacy types + * Deprecated legacy types. + * @{ + */ +typedef uint8_t Xuint8; /**< unsigned 8-bit */ +typedef char Xint8; /**< signed 8-bit */ +typedef uint16_t Xuint16; /**< unsigned 16-bit */ +typedef short Xint16; /**< signed 16-bit */ +typedef uint32_t Xuint32; /**< unsigned 32-bit */ +typedef long Xint32; /**< signed 32-bit */ +typedef float Xfloat32; /**< 32-bit floating point */ +typedef double Xfloat64; /**< 64-bit double precision FP */ +typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */ + +#if !defined __XUINT64__ +typedef struct +{ + Xuint32 Upper; + Xuint32 Lower; +} Xuint64; +#endif + +/** @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XIL_TYPES_H +typedef Xuint32 u32; +typedef Xuint16 u16; +typedef Xuint8 u8; +#endif +#else +#include <linux/types.h> +#endif + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +/* + * Xilinx NULL, TRUE and FALSE legacy support. Deprecated. + * Please use NULL, TRUE and FALSE + */ +#define XNULL NULL +#define XTRUE TRUE +#define XFALSE FALSE + +/* + * This file is deprecated and users + * should use xil_types.h and xil_assert.h\n\r + */ +#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert. +#warning Please refer the Standalone BSP UG647 for further details + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + +/** + *@endcond + */ diff --git a/bsps/include/xil/xdebug.h b/bsps/include/xil/xdebug.h new file mode 100644 index 0000000000..416a2f2cb3 --- /dev/null +++ b/bsps/include/xil/xdebug.h @@ -0,0 +1,2 @@ +/* Minimal stub file for Xilinx driver compatibility. */ +#define xdbg_printf(...) diff --git a/bsps/include/xil/xil_assert.h b/bsps/include/xil/xil_assert.h new file mode 100644 index 0000000000..e8b87b59f2 --- /dev/null +++ b/bsps/include/xil/xil_assert.h @@ -0,0 +1,176 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_assert.h +* +* @addtogroup common_assert_apis Assert APIs and Macros +* +* The xil_assert.h file contains assert related functions and macros. +* Assert APIs/Macros specifies that a application program satisfies certain +* conditions at particular points in its execution. These function can be +* used by application programs to ensure that, application code is satisfying +* certain conditions. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 07/14/09 First release +* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable +* </pre> +* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XIL_ASSERT_H /* prevent circular inclusions */ +#define XIL_ASSERT_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + +#define XIL_ASSERT_NONE 0U +#define XIL_ASSERT_OCCURRED 1U +#define XNULL NULL + +extern u32 Xil_AssertStatus; +extern s32 Xil_AssertWait; +extern void Xil_Assert(const char8 *File, s32 Line); +/** + *@endcond + */ +void XNullHandler(void *NullParameter); + +/** + * This data type defines a callback to be invoked when an + * assert occurs. The callback is invoked only when asserts are enabled + */ +typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); + +/***************** Macros (Inline Functions) Definitions *********************/ + +#ifndef NDEBUG + +/*****************************************************************************/ +/** +* @brief This assert macro is to be used for void functions. This in +* conjunction with the Xil_AssertWait boolean can be used to +* accommodate tests so that asserts which fail allow execution to +* continue. +* +* @param Expression: expression to be evaluated. If it evaluates to +* false, the assert occurs. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertVoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ + } \ +} + +/*****************************************************************************/ +/** +* @brief This assert macro is to be used for functions that do return a +* value. This in conjunction with the Xil_AssertWait boolean can be +* used to accommodate tests so that asserts which fail allow execution +* to continue. +* +* @param Expression: expression to be evaluated. If it evaluates to false, +* the assert occurs. +* +* @return Returns 0 unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertNonvoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ + } \ +} + +/*****************************************************************************/ +/** +* @brief Always assert. This assert macro is to be used for void functions. +* Use for instances where an assert should always occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertVoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ +} + +/*****************************************************************************/ +/** +* @brief Always assert. This assert macro is to be used for functions that +* do return a value. Use for instances where an assert should always +* occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertNonvoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ +} + + +#else + +#define Xil_AssertVoid(Expression) +#define Xil_AssertVoidAlways() +#define Xil_AssertNonvoid(Expression) +#define Xil_AssertNonvoidAlways() + +#endif + +/************************** Function Prototypes ******************************/ + +void Xil_AssertSetCallback(Xil_AssertCallback Routine); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_assert_apis". +*/ diff --git a/bsps/include/xil/xil_io.h b/bsps/include/xil/xil_io.h new file mode 100644 index 0000000000..853ef6bc76 --- /dev/null +++ b/bsps/include/xil/xil_io.h @@ -0,0 +1,412 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* @addtogroup common_io_interfacing_apis Register IO interfacing APIs +* +* The xil_io.h file contains the interface for the general I/O component, which +* encapsulates the Input/Output functions for the processors that do not +* require any special I/O handling. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for +* ARM processors +* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for +* CR-1049218 +* 7.30 kpt 09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to +* xil_io.h and made them as static inline +* am 10/13/20 Changed the return type of Xil_SecureOut32 function +* from u32 to int +* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur +* when -Werror=conversion compiler flag is enabled +* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739. +* +* </pre> +******************************************************************************/ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_printf.h" +#include "xstatus.h" + +#if defined (__MICROBLAZE__) +#include "mb_interface.h" +#else +#include "xpseudo_asm.h" +#endif + +/************************** Function Prototypes ******************************/ +#ifdef ENABLE_SAFETY +extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal); +#endif + +/***************** Macros (Inline Functions) Definitions *********************/ +#if defined __GNUC__ +#if defined (__MICROBLAZE__) +# define INST_SYNC mbar(0) +# define DATA_SYNC mbar(1) +# else +# define SYNCHRONIZE_IO dmb() +# define INST_SYNC isb() +# define DATA_SYNC dsb() +# endif +#else +# define SYNCHRONIZE_IO +# define INST_SYNC +# define DATA_SYNC +# define INST_SYNC +# define DATA_SYNC +#endif + +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__) +#define INLINE inline +#else +#define INLINE __inline +#endif + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading +* from the specified address and returning the 8 bit Value read from +* that address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 8 bit Value read from the specified input address. + +* +******************************************************************************/ +static INLINE u8 Xil_In8(UINTPTR Addr) +{ + return *(volatile u8 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading from +* the specified address and returning the 16 bit Value read from that +* address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 16 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u16 Xil_In16(UINTPTR Addr) +{ + return *(volatile u16 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by +* reading from the specified address and returning the 32 bit Value +* read from that address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 32 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u32 Xil_In32(UINTPTR Addr) +{ + return *(volatile u32 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading the +* 64 bit Value read from that address. +* +* +* @param Addr: contains the address to perform the input operation +* +* @return The 64 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u64 Xil_In64(UINTPTR Addr) +{ + return *(volatile u64 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for an memory location by +* writing the 8 bit Value to the the specified address. +* +* @param Addr: contains the address to perform the output operation +* @param Value: contains the 8 bit Value to be written at the specified +* address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out8(UINTPTR Addr, u8 Value) +{ + /* write 8 bit value to specified address */ + volatile u8 *LocalAddr = (volatile u8 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 16 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains the Value to be written at the specified address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out16(UINTPTR Addr, u16 Value) +{ + /* write 16 bit value to specified address */ + volatile u16 *LocalAddr = (volatile u16 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 32 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains the 32 bit Value to be written at the specified +* address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out32(UINTPTR Addr, u32 Value) +{ + /* write 32 bit value to specified address */ +#ifndef ENABLE_SAFETY + volatile u32 *LocalAddr = (volatile u32 *)Addr; + *LocalAddr = Value; +#else + XStl_RegUpdate(Addr, Value); +#endif +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 64 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains 64 bit Value to be written at the specified address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out64(UINTPTR Addr, u64 Value) +{ + /* write 64 bit value to specified address */ + volatile u64 *LocalAddr = (volatile u64 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** + * + * @brief Performs an output operation for a memory location by writing the + * 32 bit Value to the the specified address and then reading it + * back to verify the value written in the register. + * + * @param Addr contains the address to perform the output operation + * @param Value contains 32 bit Value to be written at the specified address + * + * @return Returns Status + * - XST_SUCCESS on success + * - XST_FAILURE on failure + * + *****************************************************************************/ +static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value) +{ + int Status = XST_FAILURE; + u32 ReadReg; + u32 ReadRegTemp; + + /* writing 32 bit value to specified address */ + Xil_Out32(Addr, Value); + + /* verify value written to specified address with multiple reads */ + ReadReg = Xil_In32(Addr); + ReadRegTemp = Xil_In32(Addr); + + if( (ReadReg == Value) && (ReadRegTemp == Value) ) { + Status = XST_SUCCESS; + } + + return Status; +} + +/*****************************************************************************/ +/** +* +* @brief Perform a 16-bit endian conversion. +* +* @param Data: 16 bit value to be converted +* +* @return 16 bit Data with converted endianness +* +******************************************************************************/ +static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data) +{ + return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); +} + +/*****************************************************************************/ +/** +* +* @brief Perform a 32-bit endian conversion. +* +* @param Data: 32 bit value to be converted +* +* @return 32 bit data with converted endianness +* +******************************************************************************/ +static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data) +{ + u16 LoWord; + u16 HiWord; + + /* get each of the half words from the 32 bit word */ + + LoWord = (u16) (Data & 0x0000FFFFU); + HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); + + /* byte swap each of the 16 bit half words */ + + LoWord = (u16)(((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); + HiWord = (u16)(((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); + + /* swap the half words before returning the value */ + + return ((((u32)LoWord) << (u32)16U) | (u32)HiWord); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +# define Xil_In16LE Xil_In16 +# define Xil_In32LE Xil_In32 +# define Xil_Out16LE Xil_Out16 +# define Xil_Out32LE Xil_Out32 +# define Xil_Htons Xil_EndianSwap16 +# define Xil_Htonl Xil_EndianSwap32 +# define Xil_Ntohs Xil_EndianSwap16 +# define Xil_Ntohl Xil_EndianSwap32 +# else +# define Xil_In16BE Xil_In16 +# define Xil_In32BE Xil_In32 +# define Xil_Out16BE Xil_Out16 +# define Xil_Out32BE Xil_Out32 +# define Xil_Htons(Data) (Data) +# define Xil_Htonl(Data) (Data) +# define Xil_Ntohs(Data) (Data) +# define Xil_Ntohl(Data) (Data) +#endif +#else +# define Xil_In16LE Xil_In16 +# define Xil_In32LE Xil_In32 +# define Xil_Out16LE Xil_Out16 +# define Xil_Out32LE Xil_Out32 +# define Xil_Htons Xil_EndianSwap16 +# define Xil_Htonl Xil_EndianSwap32 +# define Xil_Ntohs Xil_EndianSwap16 +# define Xil_Ntohl Xil_EndianSwap32 +#endif + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE u16 Xil_In16BE(UINTPTR Addr) +#else +static INLINE u16 Xil_In16LE(UINTPTR Addr) +#endif +#else +static INLINE u16 Xil_In16BE(UINTPTR Addr) +#endif +{ + u16 value = Xil_In16(Addr); + return Xil_EndianSwap16(value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE u32 Xil_In32BE(UINTPTR Addr) +#else +static INLINE u32 Xil_In32LE(UINTPTR Addr) +#endif +#else +static INLINE u32 Xil_In32BE(UINTPTR Addr) +#endif +{ + u32 value = Xil_In32(Addr); + return Xil_EndianSwap32(value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) +#else +static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value) +#endif +#else +static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) +#endif +{ + Value = Xil_EndianSwap16(Value); + Xil_Out16(Addr, Value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) +#else +static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value) +#endif +#else +static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) +#endif +{ + Value = Xil_EndianSwap32(Value); + Xil_Out32(Addr, Value); +} + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_io_interfacing_apis". +*/ diff --git a/bsps/include/xil/xil_mem.h b/bsps/include/xil/xil_mem.h new file mode 100644 index 0000000000..d6bc637a94 --- /dev/null +++ b/bsps/include/xil/xil_mem.h @@ -0,0 +1,47 @@ +/******************************************************************************/ +/** +* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* @file xil_mem.h +* +* @addtogroup common_mem_operation_api Customized APIs for Memory Operations +* +* The xil_mem.h file contains prototype for functions related +* to memory operations. These APIs are applicable for all processors supported +* by Xilinx. +* +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 6.1 nsk 11/07/16 First release. +* 7.0 mus 01/07/19 Add cpp extern macro +* +* </pre> +* +*****************************************************************************/ +#ifndef XIL_MEM_H /* prevent circular inclusions */ +#define XIL_MEM_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Function Prototypes *****************************/ + +void Xil_MemCpy(void* dst, const void* src, u32 cnt); + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_MEM_H */ +/** +* @} End of "addtogroup common_mem_operation_api". +*/
\ No newline at end of file diff --git a/bsps/include/xil/xil_printf.h b/bsps/include/xil/xil_printf.h new file mode 100644 index 0000000000..462b7c50db --- /dev/null +++ b/bsps/include/xil/xil_printf.h @@ -0,0 +1,44 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef XIL_PRINTF_H +#define XIL_PRINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdio.h> + +#define xil_printf(args...) printf(args) +#define print(args...) printf(args) + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_PRINTF_H */ diff --git a/bsps/include/xil/xil_smc.h b/bsps/include/xil/xil_smc.h new file mode 100644 index 0000000000..55a8df3add --- /dev/null +++ b/bsps/include/xil/xil_smc.h @@ -0,0 +1 @@ +/* Intentional blank stub file for Xilinx driver compatibility. */ diff --git a/bsps/include/xil/xil_types.h b/bsps/include/xil/xil_types.h new file mode 100644 index 0000000000..1d18bfbbca --- /dev/null +++ b/bsps/include/xil/xil_types.h @@ -0,0 +1,203 @@ +/****************************************************************************** +* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_types.h +* +* @addtogroup common_types Basic Data types for Xilinx® Software IP +* +* The xil_types.h file contains basic types for Xilinx software IP. These data types +* are applicable for all processors supported by Xilinx. +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 07/14/09 First release +* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros +* 5.00 pkp 05/29/14 Made changes for 64 bit architecture +* srt 07/14/14 Use standard definitions from stdint.h and stddef.h +* Define LONG and ULONG datatypes and mask values +* 7.00 mus 01/07/19 Add cpp extern macro +* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it +* is 64-bit processor +* </pre> +* +******************************************************************************/ + +/** + *@cond nocomments + */ +#ifndef XIL_TYPES_H /* prevent circular inclusions */ +#define XIL_TYPES_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> +#include <stddef.h> + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be + assigend to "IsReady" member of driver + instance to indicate that driver + instance is initialized and ready to use. */ +#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to + "IsStarted" member of driver instance + to indicate that driver instance is + started and it can be enabled. */ + +/* @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XBASIC_TYPES_H +/* + * guarded against xbasic_types.h. + */ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +/** @}*/ +#define __XUINT64__ +typedef struct +{ + u32 Upper; + u32 Lower; +} Xuint64; + + +/*****************************************************************************/ +/** +* @brief Return the most significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The upper 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_MSW(x) ((x).Upper) + +/*****************************************************************************/ +/** +* @brief Return the least significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The lower 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_LSW(x) ((x).Lower) + +#endif /* XBASIC_TYPES_H */ + +/* + * xbasic_types.h does not typedef s* or u64 + */ +/** @{ */ +typedef char char8; +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; +typedef uint64_t u64; +typedef int sint32; + +typedef intptr_t INTPTR; +typedef uintptr_t UINTPTR; +typedef ptrdiff_t PTRDIFF; +/** @}*/ +#if !defined(LONG) || !defined(ULONG) +typedef long LONG; +typedef unsigned long ULONG; +#endif + +#define ULONG64_HI_MASK 0xFFFFFFFF00000000U +#define ULONG64_LO_MASK ~ULONG64_HI_MASK + +#else +#include <linux/types.h> +#endif + +/** @{ */ +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines an exception handler for a processor. + * The argument points to the instance of the component + */ +typedef void (*XExceptionHandler) (void *InstancePtr); + +/** + * @brief Returns 32-63 bits of a number. + * @param n : Number being accessed. + * @return Bits 32-63 of number. + * + * @note A basic shift-right of a 64- or 32-bit quantity. + * Use this to suppress the "right shift count >= width of type" + * warning when that quantity is 32-bits. + */ +#if defined (__aarch64__) || defined (__arch64__) +#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16)) +#else +#define UPPER_32_BITS(n) 0U +#endif +/** + * @brief Returns 0-31 bits of a number + * @param n : Number being accessed. + * @return Bits 0-31 of number + */ +#define LOWER_32_BITS(n) ((u32)(n)) + + + + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** + *@endcond + */ +/** +* @} End of "addtogroup common_types". +*/ diff --git a/bsps/include/xil/xparameters.h b/bsps/include/xil/xparameters.h new file mode 100644 index 0000000000..9d4d95eacb --- /dev/null +++ b/bsps/include/xil/xparameters.h @@ -0,0 +1,44 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef XPARAMETERS_H +#define XPARAMETERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <bspopts.h> + +#define EL3 1 +#define EL1_NONSECURE 0 + +#ifdef __cplusplus +} +#endif + +#endif /* XPARAMETERS_H */ diff --git a/bsps/include/xil/xpseudo_asm_gcc.h b/bsps/include/xil/xpseudo_asm_gcc.h new file mode 100644 index 0000000000..d986349072 --- /dev/null +++ b/bsps/include/xil/xpseudo_asm_gcc.h @@ -0,0 +1,240 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_gcc.h +* +* This header file contains macros for using inline assembler code. It is +* written specifically for the GNU compiler. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.00 pkp 05/21/14 First release +* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors +* 7.2 asa 04/03/20 Renamed the str macro to strw. +* 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors +* </pre> +* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_GCC_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +#if defined (__aarch64__) +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval = 0U; \ + asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) + +#define cpsiei() //__asm__ __volatile__("cpsie i\n") +#define cpsidi() //__asm__ __volatile__("cpsid i\n") + +#define cpsief() //__asm__ __volatile__("cpsie f\n") +#define cpsidf() //__asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) /*__asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + )*/ + +#define mfgpr(rn) /*({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + })*/ + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb sy") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__("dsb sy") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__("dmb sy") + + +/* Memory Operations */ +#define ldr(adr) ({u64 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define mfelrel3() ({u64 rval = 0U; \ + asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\ + rval;\ + }) + +#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v)) + +#else + +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval = 0U; \ + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__(\ + "msr cpsr,%0\n"\ + : : "r" (v) : "cc" \ + ) + +#define cpsiei() __asm__ __volatile__("cpsie i\n") +#define cpsidi() __asm__ __volatile__("cpsid i\n") + +#define cpsief() __asm__ __volatile__("cpsie f\n") +#define cpsidf() __asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) __asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) + +#define mfgpr(rn) ({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb" : : : "memory") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") + + +/* Memory Operations */ +#define ldr(adr) ({u32 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#endif + +#define ldrb(adr) ({u8 rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define strw(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +/* Count leading zeroes (clz) */ +#define clz(arg) ({u8 rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) + +#if defined (__aarch64__) +#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) +#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) + +#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) +#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) +#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) +/* CP15 operations */ +#define mfcp(reg) ({u64 rval = 0U;\ + __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) + +#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) + +#else +/* CP15 operations */ +#define mtcp(rn, v) __asm__ __volatile__(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); + +#define mfcp(rn) ({u32 rval = 0U; \ + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) +#endif + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +/** + *@endcond + */ + +#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/bsps/include/xil/xstatus.h b/bsps/include/xil/xstatus.h new file mode 100644 index 0000000000..1e9e6fbffc --- /dev/null +++ b/bsps/include/xil/xstatus.h @@ -0,0 +1,522 @@ +/****************************************************************************** +* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* @addtogroup common_status_codes Xilinx software status codes +* +* The xstatus.h file contains the Xilinx software status codes.These codes are +* used throughout the Xilinx device drivers. +* +* @{ +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ +/** +@name Common Status Codes for All Device Drivers +@{ +*/ +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /*!< An error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /*!< An error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /*!< The device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /*!< There was no data available */ +#define XST_REGISTER_ERROR 14L /*!< A register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /*!< The device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */ +#define XST_NO_CALLBACK 18L /*!< A callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /*!< Device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /*!< Device is busy */ +#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /*!< Used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /*!< Used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /*!< Driver defined error */ +#define XST_RECV_ERROR 27L /*!< Generic receive error */ +#define XST_SEND_ERROR 28L /*!< Generic transmit error */ +#define XST_NOT_ENABLED 29L /*!< A requested service is not + available because it has not + been enabled */ +#define XST_NO_ACCESS 30L /* Generic access error */ +#define XST_TIMEOUT 31L /*!< Event timeout occurred */ + +/** @} */ +/***************** Utility Component statuses 401 - 500 *********************/ +/** +@name Utility Component Status Codes 401 - 500 +@{ +*/ +#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */ + +/** @} */ +/***************** Common Components statuses 501 - 1000 *********************/ +/** +@name Packet Fifo Status Codes 501 - 510 +@{ +*/ +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting + * empty and full simultaneously + */ +/** @} */ +/** +@name DMA Status Codes 511 - 530 +@{ +*/ +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer descriptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been + put into the scatter gather + list to be committed */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor + error */ +/** @} */ +/** +@name IPIF Status Codes Codes 531 - 550 +@{ +*/ +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /*!< Generic ipif error */ +/** @} */ + +/****************** Device specific statuses 1001 - 4095 *********************/ +/** +@name Ethernet Status Codes 1001 - 1050 +@{ +*/ +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */ +#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late + * collision on polled send */ +/** @} */ +/** +@name UART Status Codes 1051 - 1075 +@{ +*/ +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + +/** @} */ +/** +@name IIC Status Codes 1076 - 1100 +@{ +*/ +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */ +#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */ +#define XST_IIC_ARB_LOST 1089 /*!< Arbitration lost for master */ +/** @} */ +/** +@name ATMC Status Codes 1101 - 1125 +@{ +*/ +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ +/** @} */ +/** +@name Flash Status Codes 1126 - 1150 +@{ +*/ +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */ +/** @} */ +/** +@name SPI Status Codes 1151 - 1175 +@{ +*/ +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */ +#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the + device for status */ +/** @} */ +/** +@name OPB Arbiter Status Codes 1176 - 1200 +@{ +*/ +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ +/** @} */ +/** +@name INTC Status Codes 1201 - 1225 +@{ +*/ +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */ +/** @} */ +/** +@name TmrCtr Status Codes 1226 - 1250 +@{ +*/ +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */ +/** @} */ +/** +@name WdtTb Status Codes 1251 - 1275 +@{ +*/ +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L +/** @} */ +/** +@name PlbArb status Codes 1276 - 1300 +@{ +*/ +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L +/** @} */ +/** +@name Plb2Opb Status Codes 1301 - 1325 +@{ +*/ +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L +/** @} */ +/** +@name Opb2Plb Status 1326 - 1350 +@{ +*/ +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L +/** @} */ +/** +@name SysAce Status Codes 1351 - 1360 +@{ +*/ +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */ +/** @} */ +/** +@name PCI Bridge Status Codes 1361 - 1375 +@{ +*/ +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L +/** @} */ +/** +@name FlexRay Constants 1400 - 1409 +@{ +*/ +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 +/** @} */ +/** +@name USB constants 1410 - 1420 +@{ +*/ +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 +/** @} */ +/** +@name HWICAP constants 1421 - 1429 +@{ +*/ +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + +/** @} */ +/** +@name AXI VDMA constants 1430 - 1440 +@{ +*/ +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 +/** @} */ +/** +@name NAND Flash Status Codes 1441 - 1459 +@{ +*/ +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /*!< Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /*!< Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /*!< Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected + */ +/** @} */ + +/**************************** Type Definitions *******************************/ + +typedef s32 XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + +/** + *@endcond + */ + +/** +* @} End of "addtogroup common_status_codes". +*/ |