1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
|
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGRLIBAHBTRACE
*
* @brief This header file defines the AHBTRACE register block interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/ahbtrace-header */
#ifndef _GRLIB_AHBTRACE_REGS_H
#define _GRLIB_AHBTRACE_REGS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/ahbtrace */
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACE AHBTRACE
*
* @ingroup RTEMSDeviceGRLIB
*
* @brief This group contains the AHBTRACE interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACECTRL Trace buffer control register (CTRL)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBTRACE_CTRL_DCNT_SHIFT 16
#define AHBTRACE_CTRL_DCNT_MASK 0x7f0000U
#define AHBTRACE_CTRL_DCNT_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_CTRL_DCNT_MASK ) >> \
AHBTRACE_CTRL_DCNT_SHIFT )
#define AHBTRACE_CTRL_DCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_CTRL_DCNT_MASK ) | \
( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & \
AHBTRACE_CTRL_DCNT_MASK ) )
#define AHBTRACE_CTRL_DCNT( _val ) \
( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & \
AHBTRACE_CTRL_DCNT_MASK )
#define AHBTRACE_CTRL_PF 0x100U
#define AHBTRACE_CTRL_BW_SHIFT 6
#define AHBTRACE_CTRL_BW_MASK 0xc0U
#define AHBTRACE_CTRL_BW_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_CTRL_BW_MASK ) >> \
AHBTRACE_CTRL_BW_SHIFT )
#define AHBTRACE_CTRL_BW_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_CTRL_BW_MASK ) | \
( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & \
AHBTRACE_CTRL_BW_MASK ) )
#define AHBTRACE_CTRL_BW( _val ) \
( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & \
AHBTRACE_CTRL_BW_MASK )
#define AHBTRACE_CTRL_RF 0x20U
#define AHBTRACE_CTRL_AF 0x10U
#define AHBTRACE_CTRL_FR 0x8U
#define AHBTRACE_CTRL_FW 0x4U
#define AHBTRACE_CTRL_DM 0x2U
#define AHBTRACE_CTRL_EN 0x1U
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACEINDEX Trace buffer index register (INDEX)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBTRACE_INDEX_INDEX_SHIFT 4
#define AHBTRACE_INDEX_INDEX_MASK 0x7f0U
#define AHBTRACE_INDEX_INDEX_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_INDEX_INDEX_MASK ) >> \
AHBTRACE_INDEX_INDEX_SHIFT )
#define AHBTRACE_INDEX_INDEX_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_INDEX_INDEX_MASK ) | \
( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & \
AHBTRACE_INDEX_INDEX_MASK ) )
#define AHBTRACE_INDEX_INDEX( _val ) \
( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & \
AHBTRACE_INDEX_INDEX_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACETIMETAG \
* Trace buffer time tag register (TIMETAG)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBTRACE_TIMETAG_TIMETAG_SHIFT 0
#define AHBTRACE_TIMETAG_TIMETAG_MASK 0xffffffffU
#define AHBTRACE_TIMETAG_TIMETAG_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_TIMETAG_TIMETAG_MASK ) >> \
AHBTRACE_TIMETAG_TIMETAG_SHIFT )
#define AHBTRACE_TIMETAG_TIMETAG_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_TIMETAG_TIMETAG_MASK ) | \
( ( ( _val ) << AHBTRACE_TIMETAG_TIMETAG_SHIFT ) & \
AHBTRACE_TIMETAG_TIMETAG_MASK ) )
#define AHBTRACE_TIMETAG_TIMETAG( _val ) \
( ( ( _val ) << AHBTRACE_TIMETAG_TIMETAG_SHIFT ) & \
AHBTRACE_TIMETAG_TIMETAG_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACEMSFILT \
* Trace buffer master/slave filter register (MSFILT)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBTRACE_MSFILT_SMASK_15_0_SHIFT 16
#define AHBTRACE_MSFILT_SMASK_15_0_MASK 0xffff0000U
#define AHBTRACE_MSFILT_SMASK_15_0_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_MSFILT_SMASK_15_0_MASK ) >> \
AHBTRACE_MSFILT_SMASK_15_0_SHIFT )
#define AHBTRACE_MSFILT_SMASK_15_0_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_MSFILT_SMASK_15_0_MASK ) | \
( ( ( _val ) << AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) & \
AHBTRACE_MSFILT_SMASK_15_0_MASK ) )
#define AHBTRACE_MSFILT_SMASK_15_0( _val ) \
( ( ( _val ) << AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) & \
AHBTRACE_MSFILT_SMASK_15_0_MASK )
#define AHBTRACE_MSFILT_MMASK_15_0_SHIFT 0
#define AHBTRACE_MSFILT_MMASK_15_0_MASK 0xffffU
#define AHBTRACE_MSFILT_MMASK_15_0_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_MSFILT_MMASK_15_0_MASK ) >> \
AHBTRACE_MSFILT_MMASK_15_0_SHIFT )
#define AHBTRACE_MSFILT_MMASK_15_0_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_MSFILT_MMASK_15_0_MASK ) | \
( ( ( _val ) << AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) & \
AHBTRACE_MSFILT_MMASK_15_0_MASK ) )
#define AHBTRACE_MSFILT_MMASK_15_0( _val ) \
( ( ( _val ) << AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) & \
AHBTRACE_MSFILT_MMASK_15_0_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACETBBA \
* Trace buffer break address registers (TBBA)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBTRACE_TBBA_BADDR_31_2_SHIFT 2
#define AHBTRACE_TBBA_BADDR_31_2_MASK 0xfffffffcU
#define AHBTRACE_TBBA_BADDR_31_2_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_TBBA_BADDR_31_2_MASK ) >> \
AHBTRACE_TBBA_BADDR_31_2_SHIFT )
#define AHBTRACE_TBBA_BADDR_31_2_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_TBBA_BADDR_31_2_MASK ) | \
( ( ( _val ) << AHBTRACE_TBBA_BADDR_31_2_SHIFT ) & \
AHBTRACE_TBBA_BADDR_31_2_MASK ) )
#define AHBTRACE_TBBA_BADDR_31_2( _val ) \
( ( ( _val ) << AHBTRACE_TBBA_BADDR_31_2_SHIFT ) & \
AHBTRACE_TBBA_BADDR_31_2_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACETBBM \
* Trace buffer break mask registers (TBBM)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBTRACE_TBBM_BMASK_31_2_SHIFT 2
#define AHBTRACE_TBBM_BMASK_31_2_MASK 0xfffffffcU
#define AHBTRACE_TBBM_BMASK_31_2_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_TBBM_BMASK_31_2_MASK ) >> \
AHBTRACE_TBBM_BMASK_31_2_SHIFT )
#define AHBTRACE_TBBM_BMASK_31_2_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_TBBM_BMASK_31_2_MASK ) | \
( ( ( _val ) << AHBTRACE_TBBM_BMASK_31_2_SHIFT ) & \
AHBTRACE_TBBM_BMASK_31_2_MASK ) )
#define AHBTRACE_TBBM_BMASK_31_2( _val ) \
( ( ( _val ) << AHBTRACE_TBBM_BMASK_31_2_SHIFT ) & \
AHBTRACE_TBBM_BMASK_31_2_MASK )
#define AHBTRACE_TBBM_LD 0x2U
#define AHBTRACE_TBBM_ST 0x1U
/** @} */
/**
* @brief This structure defines the AHBTRACE register block memory map.
*/
typedef struct ahbtrace {
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACECTRL.
*/
uint32_t ctrl;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACEINDEX.
*/
uint32_t index;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACETIMETAG.
*/
uint32_t timetag;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACEMSFILT.
*/
uint32_t msfilt;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBA.
*/
uint32_t tbba_0;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBM.
*/
uint32_t tbbm_0;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBA.
*/
uint32_t tbba_1;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBM.
*/
uint32_t tbbm_1;
} ahbtrace;
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_AHBTRACE_REGS_H */
|
