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* Update company nameSebastian Huber2023-05-2046-47/+47
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* spec: add riscv kendrytek210 variant build optionsAlan Cudmore2023-03-288-1/+68
| | | | | | | | | This patch includes the spec/build options for the riscv kendrytek210 BSP variant. It includes options to allow the frdme310arty console UART to be used on multiple BSPS, device tree options, memory options, and other required options for the variant. Updates #4876
* bsps/riscv: Use medany cmodel for 64-bit variantsSebastian Huber2023-03-021-0/+4
| | | | Updates #4775.
* build: Use enabled by for defaultsSebastian Huber2023-01-1711-121/+96
| | | | | | | | | | | | | | Merge the "default" and "default-by-variant" attributes. Use an "enabled-by" expression to select the default value based on the enabled set. This makes it possible to select default values depending on other options. For example you could choose memory settings based on whether RTEMS_SMP is enabled or disabled. The change was tested by comparing the output of ./waf bspdefaults before and after the change.
* build: Replace variant patterns with a listSebastian Huber2023-01-177-10/+13
| | | | | | | | | | | Replace the variant patterns in the default-by-variant list with an explicit list of matching BSPs. The change was tested by comparing the output of ./waf bspdefaults before and after the change.
* build: Format build itemsSebastian Huber2023-01-172-8/+8
| | | | | Use yaml.dump(data, default_flow_style=False, allow_unicode=True) with a custom representer for integer default values to format all build items.
* riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORTSebastian Huber2023-01-121-2/+2
| | | | | | | | Low-end configurations may want to have the HTIF support removed. Enable the option by default. Fix formatting. Fix node validity checks. Updates #4779.
* spec/build/riscv: Start all riscv/riscv BSPs at 0x80000000Hesham Almatary2022-12-231-6/+0
| | | | | | | To follow other RISC-V-based OSes conventions. Delete generic BSPs that start at 0x70000000 as BSPs are now medany by default. Updates #4775
* spec/build/riscv: Default rv64* BSPs to medany cmodelHesham Almatary2022-12-234-68/+2
| | | | | | | | | | | | | | | Currently generic RISC-V BSPs (riscv/riscv) that start with rv64 and not rv64*_medany will start at 0x70000000. This adds high maintenance overhead and deviates from almost all other RISC-V-based OSes and baremetal programs that start at 0x80000000. Further, testing now has to account for an extra parameter (medany or not) that doubles the number of BSPs need to be tested. This commit defaults all RV64 BSPs to use medany code model to allow starting all BSPs at 0x80000000. BSPs that require different code models and/or start addresses are custom and need to add their own entries. Updates #4775
* bsps/riscv: RISCV_MAXIMUM_EXTERNAL_INTERRUPTSSebastian Huber2022-11-101-2/+2
| | | | | Increase RISCV_MAXIMUM_EXTERNAL_INTERRUPTS to 128 to support recent Qemu versions by default.
* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-208-3/+64
| | | | | | | | The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
* bsp/riscv: Add NOEL-V BSPMartin Aberg2022-09-0611-0/+276
| | | | | | | | | | | | | | | | | | | | Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the following NOEL-V FPGA example design ranges available from Cobham Gaisler. Follow the links for free bit-streams, DTS/DTB, user's manuals and quick-start guides: - NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7) - NOEL-PF-EX (https://www.gaisler.com/NOEL-PF) - NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU) Uses the shared GRLIB APBUART console driver "apbuart_termios.c". APBUART devices are probed using device tree. Closes #4225.
* bsp/riscv: Work area size based on /memory node in fdtDaniel Cederman2022-09-061-0/+1
| | | | | Uses the first entry in the /memory node to determine the end of the work area. Falls back on linker symbol if unable to parse the node.
* spec/bsps: Do not install tm27.hChris Johns2022-08-222-2/+0
| | | | Updates #4705
* build: Move RISCV_MAXIMUM_EXTERNAL_INTERRUPTSSebastian Huber2022-07-264-19/+3
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* bsps/riscv: Sort .noinit* sectionsSebastian Huber2022-07-201-1/+1
| | | | | | | | Sort the .noinit* input sections by name first, then by alignment if two sections have the same name. This allows the placement of begin/end symbols to initialize some areas with a special value. Update #4678.
* build: Add cppflags, cflags, cxxflags to groupsSebastian Huber2022-07-043-0/+9
| | | | | | | Propagate the group defined cppflags, cflags, and cxxflags from parent groups to child items through the build item context. Update #4670.
* bsps/riscv: Support .riscv.attributesSebastian Huber2022-02-251-1/+1
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* bsps: Default to CPU counter benchmark timerSebastian Huber2022-01-151-1/+1
| | | | | | Most BSPs which used the stubbed benachmark timer provide a CPU counter. All BSPs provide at least a stub CPU counter. Simply use the benchmark timer implementation using the CPU counter.
* build: Use common objects item for get memorySebastian Huber2021-11-304-2/+4
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* build: Merge default-by-family into by-variantSebastian Huber2021-08-189-9/+0
| | | | | | | Prefix the BSP family name with "bsps/" to make it distinct to the BSP variant names. Update #4468.
* bsps: Move optfdt* files to shared parent directorypranav2021-08-095-69/+4
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* build: Use BSP family for optionsChris Johns2021-07-1513-0/+13
| | | | | | | - Optionally add support for 'default-by-family' to allow option to be set by a family and so all related BSPs Close #4468
* bsps/riscv: Support RTEMS_NOINIT in linkcmdsSebastian Huber2021-05-031-0/+7
| | | | Update #3866.
* spec: Remove residue bsps spec filesVijay Kumar Banerjee2021-04-071-18/+0
| | | | Update #3850
* spec: Remove RTEMS_NETWORKING optionsVijay Kumar Banerjee2021-04-071-2/+0
| | | | Update #3850
* bsps: Add default rtems_get_target_hash()Sebastian Huber2021-02-262-0/+2
| | | | Update #4267.
* bsps: Add missing DWARF 5 sectionsSebastian Huber2021-01-261-3/+5
| | | | Sort alphabetically.
* bsps: Support DWARF 5 sectionsSebastian Huber2021-01-251-8/+12
| | | | GCC 11 uses DWARF 5 by default.
* Add correct link address for griscv waf buildJiri Gaisler2020-11-092-0/+6
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* Add networking support for griscv bspJiri Gaisler2020-11-092-0/+20
| | | | | | | * Only GRETH device supported for now * Fix endian problem in GRETH driver * Remove SPARC assembly from greth.c * Builds with both autoconf and waf
* build: Alternative build system based on wafSebastian Huber2020-09-1442-0/+1338
Update #3818.
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