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* Update company nameSebastian Huber2023-05-201-1/+1
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* build: Use enabled by for defaultsSebastian Huber2023-01-171-10/+9
| | | | | | | | | | | | | | Merge the "default" and "default-by-variant" attributes. Use an "enabled-by" expression to select the default value based on the enabled set. This makes it possible to select default values depending on other options. For example you could choose memory settings based on whether RTEMS_SMP is enabled or disabled. The change was tested by comparing the output of ./waf bspdefaults before and after the change.
* build: Replace variant patterns with a listSebastian Huber2023-01-171-2/+6
| | | | | | | | | | | Replace the variant patterns in the default-by-variant list with an explicit list of matching BSPs. The change was tested by comparing the output of ./waf bspdefaults before and after the change.
* build: Format build itemsSebastian Huber2023-01-171-4/+4
| | | | | Use yaml.dump(data, default_flow_style=False, allow_unicode=True) with a custom representer for integer default values to format all build items.
* spec/build/riscv: Start all riscv/riscv BSPs at 0x80000000Hesham Almatary2022-12-231-6/+0
| | | | | | | To follow other RISC-V-based OSes conventions. Delete generic BSPs that start at 0x70000000 as BSPs are now medany by default. Updates #4775
* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-201-1/+4
| | | | | | | | The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
* bsp/riscv: Add NOEL-V BSPMartin Aberg2022-09-061-0/+3
| | | | | | | | | | | | | | | | | | | | Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the following NOEL-V FPGA example design ranges available from Cobham Gaisler. Follow the links for free bit-streams, DTS/DTB, user's manuals and quick-start guides: - NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7) - NOEL-PF-EX (https://www.gaisler.com/NOEL-PF) - NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU) Uses the shared GRLIB APBUART console driver "apbuart_termios.c". APBUART devices are probed using device tree. Closes #4225.
* build: Merge default-by-family into by-variantSebastian Huber2021-08-181-1/+0
| | | | | | | Prefix the BSP family name with "bsps/" to make it distinct to the BSP variant names. Update #4468.
* build: Use BSP family for optionsChris Johns2021-07-151-0/+1
| | | | | | | - Optionally add support for 'default-by-family' to allow option to be set by a family and so all related BSPs Close #4468
* Add correct link address for griscv waf buildJiri Gaisler2020-11-091-0/+3
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* build: Alternative build system based on wafSebastian Huber2020-09-141-0/+24
Update #3818.
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