| Commit message (Collapse) | Author | Age | Files | Lines |
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Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new
BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR. Move the kernel I/O support to a
shared file.
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Update #4982.
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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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Updates #4705
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Most BSPs which used the stubbed benachmark timer provide a CPU counter.
All BSPs provide at least a stub CPU counter. Simply use the benchmark
timer implementation using the CPU counter.
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ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
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Updates #4321
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Updates #4320
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Update #4267.
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Use the Python sorted() function to sort the "source" lists.
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This avoids a function call overhead in the interrupt dispatching.
Update #4202.
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Update #4202.
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Currently, zynq-uart code is always built and has some requirements for
BSPs that use it. Instead of making all BSPs satisfy that requirement or
working around it by setting defaults, this moves the zynq-uart code
into its own spec build object so it can be included if needed.
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This adds a BSP family that runs on the Xilinx Ultrascale+ MPSOC
(ZynqMP) family of chips. It is configured to be usable on the Qemu
ZCU102 machine definition and should be almost trivially portable to
ZynqMP development boards and custom hardware. It is also configured to
be usable with libbsd.
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This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64
code.
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This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to
accomodate use by AArch64 BSPs.
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This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
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Update #3818.
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