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* doxygen: score: Add RISC-V CPU architecture groupAndreas Dachsberger2019-04-024-1/+26
| | | | Update #3706.
* score: Rename ScoreCPU Doxygen groupSebastian Huber2019-03-261-1/+1
| | | | Update #3706.
* Remove superfluous <rtems/system.h> includesSebastian Huber2019-03-141-1/+0
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* Remove explicit file names from @fileSebastian Huber2019-02-283-3/+3
| | | | | | This makes the @file documentation independent of the actual file name. Update #3707.
* riscv: Fix misaligned access in context validateSebastian Huber2019-02-021-1/+1
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* riscv: add griscv bspJiri Gaisler2019-01-221-4/+1
| | | | Update #3678.
* grlib: use cpu-independent routines for uncached accessJiri Gaisler2019-01-223-0/+83
| | | | Update #3678.
* riscv: Enable robust thread dispatchSebastian Huber2019-01-091-0/+3
| | | | | | | It must be enabled, since the context switch code does not save/restore the interrupt status. Update #3433.
* build: Include header.am in cpukit/Makefile.amSebastian Huber2018-10-102-14/+7
| | | | | Include all cpukit/*/header.am files in cpukit/Makefile.am. This gets rid of all subtree Makefile.am and the sudirs hack.
* build: Merge score/cpu/*/Makefile.amSebastian Huber2018-10-101-12/+0
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* build: Remove specialized CPPFLAGSSebastian Huber2018-10-091-1/+0
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* score: Remove CPU_PROVIDES_IDLE_THREAD_BODYSebastian Huber2018-10-051-1/+0
| | | | | | | Remove the CPU_PROVIDES_IDLE_THREAD_BODY option to avoid unnecessary conditional compilation. Close #3539.
* score: Remove CPU_PARTITION_ALIGNMENTSebastian Huber2018-08-021-2/+0
| | | | | | | | | | | | | | Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment requirement is defined by the use of Chain_Node (consisting of two pointers) to manage the free chain of partitions. It seems that previously the condition CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node) was true on all CPU ports. Now, we need an additional check. Update #3482.
* riscv: Fix CPU_ALIGNMENTSebastian Huber2018-08-021-1/+3
| | | | Update #3433.
* riscv: Rework CPU counter supportSebastian Huber2018-07-274-5/+91
| | | | Update #3433.
* riscv: Add CLINT and PLIC supportSebastian Huber2018-07-251-5/+45
| | | | | | The CLINT and PLIC need some per-processor state. Update #3433.
* riscv: Use wfi instruction for idle taskSebastian Huber2018-07-252-12/+3
| | | | Update #3433.
* riscv: Rework exception handlingSebastian Huber2018-07-256-144/+54
| | | | | | | | | | | Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() functions. Applications can install an exception handler via the fatal error handler to handle synchronous exceptions. Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must be provided by the BSP. Update #3433.
* riscv: New CPU_Exception_frameSebastian Huber2018-07-254-64/+203
| | | | | | | Use the CPU_Interrupt_frame for the volatile context. Add non-volatile registers and extra state on top of it. Update #3433.
* riscv: Add exception codesSebastian Huber2018-07-251-0/+39
| | | | Update #3433.
* score: Add _CPU_Instruction_illegal()Sebastian Huber2018-07-231-0/+5
| | | | | | | | On some architectures/simulators it is difficult to provoke an exception with misaligned or illegal data loads. Use an illegal instruction instead. Update #3433.
* score: Add _CPU_Instruction_no_operation()Sebastian Huber2018-07-201-0/+5
| | | | | This helps to reduce the use of architecture-specific defines throughout the code base.
* score: Move context validation declarationsSebastian Huber2018-07-202-4/+4
| | | | | | | The context validation support functions _CPU_Context_validate() and _CPU_Context_volatile_clobber() are used only by one test program (spcontext01). Move the function declarations to the CPU port implementation header file.
* score: Remove obsolete CPU port definesSebastian Huber2018-07-201-4/+0
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* riscv: Add LADDR assembler defineSebastian Huber2018-07-062-2/+12
| | | | | | | An address must be loaded to a register according to the code model. Add LADDR define for use in assembler code. Update #3433.
* riscv: Implement CPU counterSebastian Huber2018-07-062-2/+16
| | | | Update #3433.
* riscv: Clear reservationsSebastian Huber2018-07-055-6/+25
| | | | | | | See also RISC-V User-Level ISA V2.3, comment in section 8.2 "Load-Reserved/Store-Conditional Instructions". Update #3433.
* riscv: Fix fcsr initializationSebastian Huber2018-07-022-1/+19
| | | | Update #3433.
* riscv: Fix SMP context switch supportSebastian Huber2018-06-291-2/+2
| | | | Update #3433.
* riscv: Add SMP context switch supportSebastian Huber2018-06-291-0/+47
| | | | Update #3433.
* riscv: Add floating-point supportSebastian Huber2018-06-298-50/+538
| | | | Update #3433.
* riscv: Fix global constructionSebastian Huber2018-06-291-4/+5
| | | | Update #3433.
* riscv: Add TLS supportSebastian Huber2018-06-292-0/+9
| | | | Update #3433.
* riscv: Remove dead codeSebastian Huber2018-06-291-41/+1
| | | | Update #3433.
* riscv: Optimize context switch and interruptsSebastian Huber2018-06-296-174/+255
| | | | | | | | Save/restore non-volatile registers in _CPU_Context_switch(). Save/restore volatile registers in _ISR_Handler(). Update #3433.
* riscv: Fix _CPU_Context_Initialize() prototypeSebastian Huber2018-06-292-12/+12
| | | | Update #3433.
* riscv: Fix interrupt save/restoreSebastian Huber2018-06-291-1/+1
| | | | Update #3433.
* riscv: Implement _CPU_Context_validate()Sebastian Huber2018-06-292-160/+168
| | | | Update #3433.
* riscv: Make some CPU port defines visible to asmSebastian Huber2018-06-292-37/+49
| | | | | | Move SREG and LREG assembler defines to <rtems/score/asm.h>. Update #3433.
* riscv: Implement _CPU_Context_volatile_clobber()Sebastian Huber2018-06-292-16/+16
| | | | Update #3433.
* riscv: Remove mstatus from thread contextSebastian Huber2018-06-294-27/+14
| | | | | | | | | | The mstatus register contains no thread-specific state which must be saved/restored during a context switch. Machine interrupts (MIE) must be enabled during a context switch. Create separate CPU_Interrupt_frame structure. Update #3433.
* riscv: Remove x8 initializationSebastian Huber2018-06-291-2/+0
| | | | | | | | | | The RISC-V psABI https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md does not mention that this is a frame pointer. Update #3433.
* riscv: Properly align the thread stackSebastian Huber2018-06-291-3/+7
| | | | Update #3433.
* riscv: Do not clear thread contextSebastian Huber2018-06-291-5/+2
| | | | | | | | Do not clear the complete thread context. Initialize only the necessary members. The Context_Control::is_executing member must be preserved across _CPU_Context_Initialize() calls. Update #3433.
* riscv: Fix CPU_STACK_ALIGNMENTSebastian Huber2018-06-291-1/+2
| | | | | | | | | | According to the RISC-V psABI https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md the stack alignment is 128 bits (16 bytes). Update #3433.
* riscv: Remove RISCV_GCC_RED_ZONE_SIZESebastian Huber2018-06-292-5/+1
| | | | | | | | | | | The current ABI says that there is no stack red zone: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md "Procedures must not rely upon the persistence of stack-allocated data whose addresses lie below the stack pointer." Update #3433.
* riscv: Enable interrupts during dispatch after ISRSebastian Huber2018-06-295-55/+91
| | | | | | | | The code sequence is derived from the ARM code (see _ARMV4_Exception_interrupt). Update #2751. Update #3433.
* riscv: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2018-06-282-0/+23
| | | | Update #3433.
* riscv: Avoid namespace pollutionSebastian Huber2018-06-283-10/+4
| | | | | | | Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h> (which is visible via <rtems.h> for example). Update #3433.
* riscv: Optimize and fix interrupt disable/enableSebastian Huber2018-06-281-15/+16
| | | | | | | | | Use the atomic read and clear operation to disable interrupts. Do not write the complete mstatus. Instead, set only the MIE bit depending on the level parameter. Update #3433.
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