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* doxygen: score: Add RISC-V CPU architecture groupAndreas Dachsberger2019-04-024-1/+26
* score: Rename ScoreCPU Doxygen groupSebastian Huber2019-03-261-1/+1
* Remove superfluous <rtems/system.h> includesSebastian Huber2019-03-141-1/+0
* Remove explicit file names from @fileSebastian Huber2019-02-283-3/+3
* riscv: Fix misaligned access in context validateSebastian Huber2019-02-021-1/+1
* riscv: add griscv bspJiri Gaisler2019-01-221-4/+1
* grlib: use cpu-independent routines for uncached accessJiri Gaisler2019-01-223-0/+83
* riscv: Enable robust thread dispatchSebastian Huber2019-01-091-0/+3
* build: Include header.am in cpukit/Makefile.amSebastian Huber2018-10-102-14/+7
* build: Merge score/cpu/*/Makefile.amSebastian Huber2018-10-101-12/+0
* build: Remove specialized CPPFLAGSSebastian Huber2018-10-091-1/+0
* score: Remove CPU_PROVIDES_IDLE_THREAD_BODYSebastian Huber2018-10-051-1/+0
* score: Remove CPU_PARTITION_ALIGNMENTSebastian Huber2018-08-021-2/+0
* riscv: Fix CPU_ALIGNMENTSebastian Huber2018-08-021-1/+3
* riscv: Rework CPU counter supportSebastian Huber2018-07-274-5/+91
* riscv: Add CLINT and PLIC supportSebastian Huber2018-07-251-5/+45
* riscv: Use wfi instruction for idle taskSebastian Huber2018-07-252-12/+3
* riscv: Rework exception handlingSebastian Huber2018-07-256-144/+54
* riscv: New CPU_Exception_frameSebastian Huber2018-07-254-64/+203
* riscv: Add exception codesSebastian Huber2018-07-251-0/+39
* score: Add _CPU_Instruction_illegal()Sebastian Huber2018-07-231-0/+5
* score: Add _CPU_Instruction_no_operation()Sebastian Huber2018-07-201-0/+5
* score: Move context validation declarationsSebastian Huber2018-07-202-4/+4
* score: Remove obsolete CPU port definesSebastian Huber2018-07-201-4/+0
* riscv: Add LADDR assembler defineSebastian Huber2018-07-062-2/+12
* riscv: Implement CPU counterSebastian Huber2018-07-062-2/+16
* riscv: Clear reservationsSebastian Huber2018-07-055-6/+25
* riscv: Fix fcsr initializationSebastian Huber2018-07-022-1/+19
* riscv: Fix SMP context switch supportSebastian Huber2018-06-291-2/+2
* riscv: Add SMP context switch supportSebastian Huber2018-06-291-0/+47
* riscv: Add floating-point supportSebastian Huber2018-06-298-50/+538
* riscv: Fix global constructionSebastian Huber2018-06-291-4/+5
* riscv: Add TLS supportSebastian Huber2018-06-292-0/+9
* riscv: Remove dead codeSebastian Huber2018-06-291-41/+1
* riscv: Optimize context switch and interruptsSebastian Huber2018-06-296-174/+255
* riscv: Fix _CPU_Context_Initialize() prototypeSebastian Huber2018-06-292-12/+12
* riscv: Fix interrupt save/restoreSebastian Huber2018-06-291-1/+1
* riscv: Implement _CPU_Context_validate()Sebastian Huber2018-06-292-160/+168
* riscv: Make some CPU port defines visible to asmSebastian Huber2018-06-292-37/+49
* riscv: Implement _CPU_Context_volatile_clobber()Sebastian Huber2018-06-292-16/+16
* riscv: Remove mstatus from thread contextSebastian Huber2018-06-294-27/+14
* riscv: Remove x8 initializationSebastian Huber2018-06-291-2/+0
* riscv: Properly align the thread stackSebastian Huber2018-06-291-3/+7
* riscv: Do not clear thread contextSebastian Huber2018-06-291-5/+2
* riscv: Fix CPU_STACK_ALIGNMENTSebastian Huber2018-06-291-1/+2
* riscv: Remove RISCV_GCC_RED_ZONE_SIZESebastian Huber2018-06-292-5/+1
* riscv: Enable interrupts during dispatch after ISRSebastian Huber2018-06-295-55/+91
* riscv: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2018-06-282-0/+23
* riscv: Avoid namespace pollutionSebastian Huber2018-06-283-10/+4
* riscv: Optimize and fix interrupt disable/enableSebastian Huber2018-06-281-15/+16
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