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* score: Canonicalize _CPU_Fatal_halt()Sebastian Huber2021-07-282-2/+2
* score: Remove processor event broadcast/receiveSebastian Huber2021-07-281-10/+0
* score: Remove _CPU_Initialize_vectors()Sebastian Huber2021-06-241-2/+0
* score: Add _CPU_Context_switch_no_return()Sebastian Huber2021-05-181-0/+5
* rtems: Improve RTEMS_NO_RETURN attributeSebastian Huber2020-10-101-4/+2
* score: Add CPU_USE_LIBC_INIT_FINI_ARRAYKinsey Moore2020-06-301-0/+2
* riscv: preliminarily support for libdlHesham Almatary2019-11-121-0/+144
* doxygen: score: Add RISC-V CPU architecture groupAndreas Dachsberger2019-04-023-0/+25
* Remove superfluous <rtems/system.h> includesSebastian Huber2019-03-141-1/+0
* Remove explicit file names from @fileSebastian Huber2019-02-283-3/+3
* riscv: add griscv bspJiri Gaisler2019-01-221-4/+1
* grlib: use cpu-independent routines for uncached accessJiri Gaisler2019-01-222-0/+81
* riscv: Enable robust thread dispatchSebastian Huber2019-01-091-0/+3
* score: Remove CPU_PROVIDES_IDLE_THREAD_BODYSebastian Huber2018-10-051-1/+0
* score: Remove CPU_PARTITION_ALIGNMENTSebastian Huber2018-08-021-2/+0
* riscv: Fix CPU_ALIGNMENTSebastian Huber2018-08-021-1/+3
* riscv: Rework CPU counter supportSebastian Huber2018-07-272-5/+41
* riscv: Add CLINT and PLIC supportSebastian Huber2018-07-251-5/+45
* riscv: Use wfi instruction for idle taskSebastian Huber2018-07-251-10/+0
* riscv: Rework exception handlingSebastian Huber2018-07-252-30/+7
* riscv: New CPU_Exception_frameSebastian Huber2018-07-252-55/+121
* riscv: Add exception codesSebastian Huber2018-07-251-0/+39
* score: Add _CPU_Instruction_illegal()Sebastian Huber2018-07-231-0/+5
* score: Add _CPU_Instruction_no_operation()Sebastian Huber2018-07-201-0/+5
* score: Move context validation declarationsSebastian Huber2018-07-202-4/+4
* score: Remove obsolete CPU port definesSebastian Huber2018-07-201-4/+0
* riscv: Add LADDR assembler defineSebastian Huber2018-07-061-1/+11
* riscv: Implement CPU counterSebastian Huber2018-07-061-1/+16
* riscv: Clear reservationsSebastian Huber2018-07-053-6/+21
* riscv: Fix fcsr initializationSebastian Huber2018-07-021-0/+9
* riscv: Add floating-point supportSebastian Huber2018-06-293-40/+184
* riscv: Remove dead codeSebastian Huber2018-06-291-41/+1
* riscv: Optimize context switch and interruptsSebastian Huber2018-06-292-17/+123
* riscv: Fix _CPU_Context_Initialize() prototypeSebastian Huber2018-06-291-6/+6
* riscv: Implement _CPU_Context_validate()Sebastian Huber2018-06-291-6/+1
* riscv: Make some CPU port defines visible to asmSebastian Huber2018-06-292-37/+49
* riscv: Implement _CPU_Context_volatile_clobber()Sebastian Huber2018-06-291-4/+1
* riscv: Remove mstatus from thread contextSebastian Huber2018-06-292-11/+14
* riscv: Fix CPU_STACK_ALIGNMENTSebastian Huber2018-06-291-1/+2
* riscv: Remove RISCV_GCC_RED_ZONE_SIZESebastian Huber2018-06-291-3/+0
* riscv: Enable interrupts during dispatch after ISRSebastian Huber2018-06-292-0/+6
* riscv: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2018-06-282-0/+23
* riscv: Avoid namespace pollutionSebastian Huber2018-06-281-7/+1
* riscv: Optimize and fix interrupt disable/enableSebastian Huber2018-06-281-15/+16
* riscv: Add dummy SMP supportSebastian Huber2018-06-282-125/+27
* riscv: Implement ISR set/get levelSebastian Huber2018-06-281-2/+13
* Rework initialization and interrupt stack supportSebastian Huber2018-06-271-15/+0
* score: Add CPU_INTERRUPT_STACK_ALIGNMENTSebastian Huber2018-06-271-0/+5
* Add _CPU_Counter_frequency()Sebastian Huber2018-06-151-0/+2
* Remove register keyword from public header filesSebastian Huber2018-04-161-1/+1
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