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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-06 11:07:20 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-06 13:46:46 +0200 |
commit | bca36d986b24b0720ce19b618bbe592baed6cb95 (patch) | |
tree | a1cb260164decf4d98def37505203269920cf985 /cpukit/score/cpu/riscv/include | |
parent | riscv: Implement CPU counter (diff) | |
download | rtems-bca36d986b24b0720ce19b618bbe592baed6cb95.tar.bz2 |
riscv: Add LADDR assembler define
An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.
Update #3433.
Diffstat (limited to 'cpukit/score/cpu/riscv/include')
-rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/asm.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/asm.h b/cpukit/score/cpu/riscv/include/rtems/asm.h index c3be827be0..c4abc76a27 100644 --- a/cpukit/score/cpu/riscv/include/rtems/asm.h +++ b/cpukit/score/cpu/riscv/include/rtems/asm.h @@ -131,6 +131,16 @@ #endif /* __riscv_xlen */ +#ifdef __riscv_cmodel_medany + +#define LADDR lla + +#else /* !__riscv_cmodel_medany */ + +#define LADDR la + +#endif /* __riscv_cmodel_medany */ + #if __riscv_flen == 32 #define FLREG flw @@ -167,7 +177,7 @@ #ifdef RTEMS_SMP csrr \REG, mscratch #else - la \REG, _Per_CPU_Information + LADDR \REG, _Per_CPU_Information #endif .endm |