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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-26 08:53:28 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-29 10:04:32 +0200 |
| commit | 9704d86f86c5a800a06dd814538df4cd83367fc5 (patch) | |
| tree | 9b69dc883eea50e0a5987e27590b4f4710a64c07 /cpukit/score/cpu/riscv/include | |
| parent | riscv: Add _CPU_Get_current_per_CPU_control() (diff) | |
| download | rtems-9704d86f86c5a800a06dd814538df4cd83367fc5.tar.bz2 | |
riscv: Enable interrupts during dispatch after ISR
The code sequence is derived from the ARM code
(see _ARMV4_Exception_interrupt).
Update #2751.
Update #3433.
Diffstat (limited to 'cpukit/score/cpu/riscv/include')
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 4 |
2 files changed, 6 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 30adbbca38..4d9f828086 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -3,6 +3,7 @@ */ /* + * Copyright (c) 2018 embedded brains GmbH * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> @@ -75,6 +76,7 @@ typedef struct { unsigned long mstatus; unsigned long mcause; unsigned long mepc; + uint32_t isr_dispatch_disable; #ifdef RTEMS_SMP volatile bool is_executing; #endif diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index 1370e656dd..6279c7c22e 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -38,10 +38,14 @@ #if __riscv_xlen == 32 +#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 140 + #define CPU_INTERRUPT_FRAME_SIZE 144 #elif __riscv_xlen == 64 +#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 280 + #define CPU_INTERRUPT_FRAME_SIZE 288 #endif /* __riscv_xlen */ |