diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-19 12:11:19 +0200 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-25 10:07:43 +0200 |
commit | 8db3f0e878b7f008ad05716f501220509662e2c4 (patch) | |
tree | d55db59defa95096a3ef156427822a9f8744ab58 /cpukit/score/cpu/riscv/include | |
parent | riscv: New CPU_Exception_frame (diff) | |
download | rtems-8db3f0e878b7f008ad05716f501220509662e2c4.tar.bz2 |
riscv: Rework exception handling
Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.
Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.
Update #3433.
Diffstat (limited to 'cpukit/score/cpu/riscv/include')
-rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 30 | ||||
-rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 7 |
2 files changed, 7 insertions, 30 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 5553fa9d05..724385cd75 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -361,36 +361,6 @@ void _CPU_Initialize( ); /* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - unsigned long vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* * _CPU_Thread_Idle_body * * This routine is the CPU dependent IDLE thread body. diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index cb60a528de..313b671da0 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -289,6 +289,13 @@ typedef struct { } CPU_Per_CPU_control; #endif +struct Per_CPU_Control; + +void _RISCV_Interrupt_dispatch( + uintptr_t mcause, + struct Per_CPU_Control *cpu_self +); + static inline uint32_t _RISCV_Read_FCSR( void ) { uint32_t fcsr; |