| Commit message (Collapse) | Author | Age | Files | Lines |
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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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Update #3835.
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Updates #3053.
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Update #4214.
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Use the following variant which was already used by most source files:
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
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The fatal is internal indicator is redundant since the fatal source and
error code uniquely identify a fatal error. Keep the fatal user
extension is internal parameter for backward compatibility and set it to
false always.
Update #2825.
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Rename _Internal_error_Occurred() into _Terminate().
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Tested and implemented on ARM, m68k, PowerPC and SPARC. Other
architectures need more work.
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Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
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* nios2-mpu-configuration.c, nios2-mpu-descriptor.c,
nios2-mpu-disable-protected.c, nios2-mpu-reset.c: New files.
* Makefile.am: Reflect changes above.
* rtems/score/nios2-utility.h, nios2-context-initialize.c: Added
support for the memory protection unit (MPU).
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* rtems/score/nios2-utility.h: Avoid redefines with Altera HAL.
Declare _Nios2_ISR_Set_level().
* nios2-context-initialize.c: Use _Nios2_ISR_Set_level().
* nios2-isr-set-level.c: Define _Nios2_ISR_Set_level().
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* cpu.c, cpu_asm.S: Removed files.
* nios2-context-initialize.c, nios2-context-switch.S,
nios2-fatal-halt.c, nios2-initialize-vectors.c, nios2-initialize.c,
nios2-isr-get-level.c, nios2-isr-install-raw-handler.c,
nios2-isr-install-vector.c, nios2-isr-is-in-progress.c,
nios2-isr-set-level.c, nios2-thread-dispatch-disabled.c,
rtems/score/nios2-utility.h: New files.
* Makefile.am, preinstall.am: Reflect changes above.
* irq.c: Update due to API changes.
* rtems/score/cpu.h: New functions _CPU_Initialize_vectors(),
_CPU_ISR_Set_level(), and _CPU_Fatal_halt() (instead of macros).
Support for external interrupt controller (EIC). Documentation
changes.
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