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* score: Add _CPU_Get_TLS_thread_pointer()Sebastian Huber2023-09-151-0/+7
| | | | | | | | Add _CPU_Get_TLS_thread_pointer() to get the thread pointer which is used to get the address of thread-local storage objects associated with a thread. Update #4920.
* microblaze: Add libdl supportAlex White2023-08-301-0/+83
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* score: Remove CPU port specific cpuatomic.hSebastian Huber2023-06-121-41/+0
| | | | | All CPU ports used the same <rtems/score/cpustdatomic.h> header file to provide the atomic operations. Remove the header file indirection.
* score: Add CPU_THREAD_LOCAL_STORAGE_VARIANTSebastian Huber2022-10-144-5/+11
| | | | Update #3835.
* Do not use RTEMS_INLINE_ROUTINESebastian Huber2022-09-192-4/+4
| | | | | | | Directly use "static inline" which is available in C99 and later. This brings the RTEMS implementation closer to standard C. Close #3935.
* score: Remove _CPU_Counter_difference()Sebastian Huber2022-09-091-8/+0
| | | | | | | All CPU ports used the same _CPU_Counter_difference() implementation. Remove this CPU port interface and mandate a monotonically increasing CPU counter. Close #3456.
* score: Add _CPU_Use_thread_local_storage()Sebastian Huber2022-07-041-0/+11
| | | | | | | | | | | | At some point during system initialization, the idle threads are created. Afterwards, the boot processor basically executes within the context of an idle thread with thread dispatching disabled. On some architectures, the thread-local storage area of the associated thread must be set in dedicated processor registers. Add the new CPU port function to do this: void _CPU_Use_thread_local_storage( const Context_Control *context ) Close #4672.
* cpukit/microblaze: Add file headers and licensesRyan Long2022-05-042-0/+70
| | | | | These files had no file header, copyright, or license. Based on git history, added appropriate copyright and license.
* cpukit/libdebugger: Add MicroBlaze supportKinsey Moore2022-02-231-0/+24
| | | | | | | | | | | | Add MicroBlaze support for libdebugger. This uses only software break type instructions to provide self-hosted GDB debugging support for applications since internal control of debug hardware is not possible. Also of note, this implementation for MicroBlaze would typically use the brki instruction for software break, but instead uses an illegal opcode to manage software breaks as exceptions. This is due to poor interaction with the debug hardware where the debug hardware will intercept software breaks instead of allowing the software break vector to execute.
* microblaze: Decouple exceptions from interruptsKinsey Moore2022-02-232-8/+8
| | | | | | | | Exception handling should be enabled at all times during execution to ensure that exceptions are not ignored which would cause further problems. This separates use of the exception enable bit from use of the interrupt enable bit in the machine status register so that they can be manipulated independently.
* cpukit/microblaze: Simplify dispatch assemblyKinsey Moore2022-02-041-45/+3
| | | | | | The dispatch code was unnecessarily saving and restoring an extra interrupt frame. This avoids the extra frame and folds the dispatch call into a fallthrough to the interrupt frame restoration code.
* cpukit/microblaze: Clarify interrupt frame usageKinsey Moore2022-02-042-5/+14
| | | | | | Avoid use of magic numbers in favor of named constants and add MSR to the interrupt frame so that thread dispatch can occur on exceptions as well.
* cpukit/microblaze: Add exception extensionsKinsey Moore2022-02-043-0/+388
| | | | | Add the functions necessary to support RTEMS_EXCEPTION_EXTENSIONS and mark this functionality as available on MicroBlaze.
* cpukit/microblaze: Add debug vector and handlerKinsey Moore2022-02-042-0/+35
| | | | | | This patch adds a vector for debug events along with a hook similar to the exception framework. The debug vector generates an exception frame for use by libdebugger.
* cpukit/microblaze: Add exception frameworkKinsey Moore2022-02-043-17/+187
| | | | | | | | | | | This patch updates the CPU_Exception_frame to include all necessary registers, combines hardware snd software exception handlers into a shared vector, provides an architecture-specific hook for taking control of exception handling, and moves exception handling over to actually using the CPU_Exception_frame instead of a minimal interrupt stack frame. As the significant contents of _exception_handler.S have been entirely rewritten, the copyright information on this file has been updated to reflect that.
* microblaze: Add support for libbsd networkingAlex White2022-02-012-4/+1
| | | | | This includes fixes and improvements necessary to get libbsd networking running.
* microblaze: Rework for RTEMS 6Alex White2021-10-1312-1490/+963
| | | | | This reworks the existing MicroBlaze architecture port and BSP to achieve basic functionality using the latest RTEMS APIs.
* bsps: Add MicroBlaze FPGA BSPHesham ALMatary2021-10-135-79/+238
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* score: Add MicroBlaze portJoel Sherrill2021-10-134-0/+1626