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* bsps/m68k/genmcf548x/README: Manual cleanup of embedded brains File HeadersJoel Sherrill2022-03-101-7/+1
| | | | Updates #4625.
* bsp/altera-cyclone-v: fix the creation of reserved memory regionsMarcus Ritter2022-03-091-1/+1
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* bsp/leon3: Fix warningSebastian Huber2022-03-081-1/+1
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* bsp/leon3: Include missing header fileSebastian Huber2022-03-082-0/+2
| | | | | The <leon.h> include was removed from <bsp.h> in commit 1577a48369fae5e024baa2119b26d25de0f43946.
* powerpc: Use .machine any for some inline asmSebastian Huber2022-02-268-14/+91
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* riscv: Use zicsr architecture extensionSebastian Huber2022-02-252-1/+8
| | | | | | | | | | This is required for ISA 2.0 support, see chapter "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0 in RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
* bsps/riscv: Add missing includeSebastian Huber2022-02-251-0/+1
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* bsps/powerpc: Do no use Newlib internalsSebastian Huber2022-02-255-5/+10
| | | | The struct _reent::__sdidinit member was renamed in a recent Newlib.
* microblaze: Decouple exceptions from interruptsKinsey Moore2022-02-231-0/+3
| | | | | | | | Exception handling should be enabled at all times during execution to ensure that exceptions are not ignored which would cause further problems. This separates use of the exception enable bit from use of the interrupt enable bit in the machine status register so that they can be manipulated independently.
* bsp/imxrt: Enforce alignment for devicetreeChristian Mauderer2022-02-213-3/+3
| | | | | | A device tree binary has to be 8 byte aligned in memory. This is checked since RTEMS commit 34052ef78cf8724dee73e9279b2c6bff8cfed234 "libfdt: Add FDT alignment check to fdt_check_header()".
* bsp/arm/zynq: Cadence I2C has moved, update to the new pathChris Johns2022-02-171-1/+2
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* bsp/atsam: Improve UART / USART tx performanceChristian Mauderer2022-02-111-4/+5
| | | | | | | | | | | | | Put the next character into the send buffer if the buffer is empty and not when the last character has been sent out to the line. This improves the performance slightly. Before that patch, the receive path was faster than the transmit path. Therefore a simple echo could drop characters on a busy connection. With this patch sending and receiving has about the same performance so that no characters are lost. Fixes #4610
* bsp/atsam/i2c: Add error return and fix edge casesChristian Mauderer2022-02-102-59/+47
| | | | | | | | | | The driver didn't return with an error on (for example) a NACK on the bus. This adds the expected error return. Due to the new case that a transfer can be interrupted on an error, there were some new edge cases. This patch therefore also fixes these edge cases by removing the transfer_state that more or less duplicated the interrupt states. Fixes #4592
* bsp/atsam/i2c: Simplify driverChristian Mauderer2022-02-102-69/+45
| | | | | | | | | | Do some clean ups. Remove superfluous variables. Eliminate some overly complex logic (information about transfer and remaining bytes has been tracked redundantly in multiple variables). This patch doesn't change the behavior of the driver. Update #4592
* cpukit/microblaze: Clarify interrupt frame usageKinsey Moore2022-02-041-1/+3
| | | | | | Avoid use of magic numbers in favor of named constants and add MSR to the interrupt frame so that thread dispatch can occur on exceptions as well.
* cpukit/microblaze: Add debug vector and handlerKinsey Moore2022-02-042-1/+112
| | | | | | This patch adds a vector for debug events along with a hook similar to the exception framework. The debug vector generates an exception frame for use by libdebugger.
* cpukit/microblaze: Add exception frameworkKinsey Moore2022-02-043-92/+96
| | | | | | | | | | | This patch updates the CPU_Exception_frame to include all necessary registers, combines hardware snd software exception handlers into a shared vector, provides an architecture-specific hook for taking control of exception handling, and moves exception handling over to actually using the CPU_Exception_frame instead of a minimal interrupt stack frame. As the significant contents of _exception_handler.S have been entirely rewritten, the copyright information on this file has been updated to reflect that.
* microblaze: Add support for libbsd networkingAlex White2022-02-0110-6/+123
| | | | | This includes fixes and improvements necessary to get libbsd networking running.
* microblaze: Add support for libbsd.Jennifer Averett2022-02-014-0/+1438
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* bsps: Avoid use of memcpy() in bsp_fdt_copy()Sebastian Huber2022-01-191-1/+1
| | | | | The memcpy() function may be not loaded at the time bsp_fdt_copy() is called.
* bsp/atsam: Optionally use DMA for UART RxChristian Mauderer2022-01-182-5/+190
| | | | | | | | | | | | If the system is busy with other interrupts and the UART is set to a fast baud rate, it's possible to loose UART interrupts and therefore characters. This allows to optionally enable a DMA for the UARTs so that a number of lost interrupts can be tolerated. The number of DMAs on this chip is limited and not not all applications need that feature. Therefore the DMA is disabled by default. Close #4578
* bsp/atsam: Merge USART and UART driverChristian Mauderer2022-01-181-225/+60
| | | | | | | | | | If no extended features of the USART are used and if the comparison feature of the UART is not used, the two modules are compatible. The drivers were nearly identical except for some names of the defines. This patch merges the two drivers into one. Update #4578
* bsps: Default to CPU counter benchmark timerSebastian Huber2022-01-151-30/+0
| | | | | | Most BSPs which used the stubbed benachmark timer provide a CPU counter. All BSPs provide at least a stub CPU counter. Simply use the benchmark timer implementation using the CPU counter.
* aarch64: always boot into EL1NSGedare Bloom2022-01-123-32/+32
| | | | | | | | | | | Always start the executive in Exception Level 1, Non-Secure mode. If we boot in EL3 Secure with GICv3 then we have to initialize the distributor and redistributor to set up G1NS interrupts early in the boot sequence before stepping down from EL3S to EL1NS. Now there is no need to distinguish between secure and non-secure world execution after the primary core boots, so get rid of the AARCH64_IS_NONSECURE configuration option.
* arm/gicv3: refactor DIST initialization to helperGedare Bloom2022-01-121-31/+29
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* bsps/aarch64: refactor register init and hooksGedare Bloom2022-01-122-45/+48
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* Fix device tree blob alignmentSebastian Huber2022-01-111-4/+4
| | | | A device tree blob must be aligned on an 8-byte boundary.
* bsp/qoriq: Implement Interrupt Manager directivesSebastian Huber2022-01-111-24/+77
| | | | Update #3269.
* bsp/mrm332: Fix TLS support in linker command fileSebastian Huber2021-12-221-10/+6
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* Remove powerpc/haleakala boardJoel Sherrill2021-12-1713-1841/+0
| | | | Closes #4302.
* bsp/leon3: Do not invalidate cache in SMP startSebastian Huber2021-12-131-1/+1
| | | | | Since the trap table is now statically initialized, there is no need to invalidate the instruction cache.
* bsp/leon3: Use interrupt entry for tm27 supportSebastian Huber2021-12-131-20/+57
| | | | | | | | | | Using rtems_interrupt_entry_install() instead of rtems_interrupt_handler_install() avoids a dependency on the dynamic memory allocation. Use Interrupt Manager directives instead of a BSP-specific API. Use inline functions. In SMP configurations, set an affinity to all online processors and raise the interrupt on the current processor.
* bsp/leon3: Use interrupt entry for the SMP supportSebastian Huber2021-12-131-4/+9
| | | | | | Using rtems_interrupt_entry_install() instead of rtems_interrupt_handler_install() avoids a dependency on the dynamic memory allocation.
* bsp/leon3: Use interrupt entry for Clock DriverSebastian Huber2021-12-131-4/+10
| | | | | | Using rtems_interrupt_entry_install() instead of rtems_interrupt_handler_install() avoids a dependency on the dynamic memory allocation.
* bsps/aarch64: Support .noinit linker sectionSebastian Huber2021-12-131-0/+7
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* bsps/aarch64: Remove erroneous cache featureKinsey Moore2021-12-121-2/+0
| | | | | | | | | | The AArch64 cache implementation does not define rtems_cache_disable_data(), but declares that it does via CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA. The existing implementation of _CPU_cache_disable_data() is sufficient to enable this functionality without the erroneous cache feature flag. Closes #4569
* libc: Optimize malloc() initializationSebastian Huber2021-11-302-0/+98
| | | | | | | | | | | | | | | | The BSPs provide memory for the separate C Program Heap initialization via _Memory_Get(). Most BSPs provide exactly one memory area. Only two BSPs provide more than one memory area (arm/altera-cyclone-v and bsps/powerpc/mpc55xxevb). Only if more than one memory area is provided, there is a need to use _Heap_Extend(). Provide two implementations to initialize the separate C Program Heap and let the BSP select one of the implementations based on the number of provided memory areas. This gets rid of a dependency on _Heap_Extend(). It also avoids dead code sections for most BSPs. Change licence to BSD-2-Clause according to file history. Update #3053.
* score: Optimize Workspace Handler initializationSebastian Huber2021-11-302-0/+92
| | | | | | | | | | | | The BSPs provide memory for the workspace initialization via _Memory_Get(). Most BSPs provide exactly one memory area. Only two BSPs provide more than one memory area (arm/altera-cyclone-v and bsps/powerpc/mpc55xxevb). Only if more than one memory area is provided, there is a need to use _Heap_Extend(). Provide two implementations to initialize the workspace handler and let the BSP select one of the implementations based on the number of provided memory areas. This gets rid of a dependency on _Heap_Extend(). It also avoids dead code sections for most BSPs.
* bsp_specs: Delete last remnants of these.Joel Sherrill2021-11-2985-0/+0
| | | | Updates #3937.
* bsps/aarch64: Restore interrupt nestingKinsey Moore2021-11-101-1/+3
| | | | | Fixing the debug mask flag broke nested interrupts. This restores that functionality.
* cpukit/aarch64: Add libdebugger supportKinsey Moore2021-11-011-0/+11
| | | | | | This adds support for libdebugger under AArch64 using software breakpoints and the single-step execution mode present in all AArch64 CPUs.
* bsps/aarch64: Mask debug events from startupKinsey Moore2021-11-011-2/+2
| | | | | | Debug events should be masked at least until after the first context switch and should usually be masked until a debugger is attached for application debugging.
* bsps/aarch64: Set interrupt level correctlyKinsey Moore2021-11-011-1/+1
| | | | | | The existing code is functional but inccorrect and blindly modifies the other masking bits. It is important to preserve those other bits since they control masking of important system events.
* bsps/aarch64: Add missing MMU map recursion checkKinsey Moore2021-11-011-0/+9
| | | | | | | Certain input parameters for MMU mapping operations could cause an infinite recursion if block end boundaries didn't align to 4k. This ensures that recursion descent does not exceed 2 levels and instead rounds up to the nearest 4k block if necessary.
* aarch64: Break out MMU definitionsKinsey Moore2021-11-015-39/+121
| | | | | | This moves the AArch64 MMU memory type definitions into cpukit for use by libdebugger since remapping of memory is required to insert software breakpoints.
* microblaze: Rework for RTEMS 6Alex White2021-10-1324-0/+2171
| | | | | This reworks the existing MicroBlaze architecture port and BSP to achieve basic functionality using the latest RTEMS APIs.
* bsp/imx: Add cs_change support to SPIChristian Mauderer2021-10-061-4/+6
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* cpukit: Add AArch64 SMP SupportKinsey Moore2021-09-217-26/+165
| | | | This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
* bsps/gicv2: Allow BSPs to define IRQ attributesKinsey Moore2021-09-213-34/+180
| | | | | | | ARM's GICv2 is configurable and its attributes vary between implementations including omission of specific interrupts. This allows BSPs to accomodate those varying implementations with customized attribute sets.
* bsps/zynqmp: Use correct number of interruptsKinsey Moore2021-09-211-1/+1
| | | | | GICv2 can support up to 1024 interrupts, but ZynqMP hardware is only configured for 192 interrupts.
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