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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-02-25 17:45:06 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-02-25 20:38:20 +0100 |
| commit | faaffbd913c0e4e39444b2b4b0e0bfb93cc1a0a2 (patch) | |
| tree | 22e840b74ab2f28e275ade935d98116e40e3df19 /bsps | |
| parent | bsps/riscv: Add missing include (diff) | |
| download | rtems-faaffbd913c0e4e39444b2b4b0e0bfb93cc1a0a2.tar.bz2 | |
riscv: Use zicsr architecture extension
This is required for ISA 2.0 support, see chapter
"Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
in
RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
Diffstat (limited to 'bsps')
| -rw-r--r-- | bsps/riscv/griscv/clock/clockdrv.c | 8 | ||||
| -rw-r--r-- | bsps/riscv/shared/start/start.S | 1 |
2 files changed, 8 insertions, 1 deletions
diff --git a/bsps/riscv/griscv/clock/clockdrv.c b/bsps/riscv/griscv/clock/clockdrv.c index 4cf15fe4f8..a5b7b15760 100644 --- a/bsps/riscv/griscv/clock/clockdrv.c +++ b/bsps/riscv/griscv/clock/clockdrv.c @@ -187,7 +187,13 @@ CPU_Counter_ticks _CPU_Counter_read( void ) { unsigned long timec; - __asm__ volatile ( "csrr %0, time" : "=&r" ( timec ) ); + __asm__ volatile ( + ".option push\n" + ".option arch, +zicsr\n" + "csrr %0, time\n" + ".option pop" : + "=&r" ( timec ) + ); return timec; } diff --git a/bsps/riscv/shared/start/start.S b/bsps/riscv/shared/start/start.S index 04a62a26ce..3702f8ac2f 100644 --- a/bsps/riscv/shared/start/start.S +++ b/bsps/riscv/shared/start/start.S @@ -39,6 +39,7 @@ PUBLIC(_start) .section .bsp_start_text, "wax", @progbits .align 2 + .option arch, +zicsr TYPE_FUNC(_start) SYM(_start): |