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| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2021-12-10 09:45:54 -0600 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2021-12-12 12:04:02 -0600 |
| commit | 68b0db358c81a7f770a44ceb819197bdc320bc99 (patch) | |
| tree | 7fa12f267aada7b05d165df6ee425a7e2d3a8e35 /bsps | |
| parent | Avoid ISR_LOCK_MEMBER() since it confuses Doxygen (diff) | |
| download | rtems-68b0db358c81a7f770a44ceb819197bdc320bc99.tar.bz2 | |
bsps/aarch64: Remove erroneous cache feature
The AArch64 cache implementation does not define
rtems_cache_disable_data(), but declares that it does via
CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA. The existing implementation of
_CPU_cache_disable_data() is sufficient to enable this functionality
without the erroneous cache feature flag.
Closes #4569
Diffstat (limited to 'bsps')
| -rw-r--r-- | bsps/aarch64/shared/cache/cache.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/bsps/aarch64/shared/cache/cache.c b/bsps/aarch64/shared/cache/cache.c index 9e7446a077..fc1766c2b9 100644 --- a/bsps/aarch64/shared/cache/cache.c +++ b/bsps/aarch64/shared/cache/cache.c @@ -47,8 +47,6 @@ #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS -#define CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA - #define AARCH64_CACHE_L1_CPU_DATA_ALIGNMENT ( (size_t) 64 ) #define AARCH64_CACHE_PREPARE_MVA(mva) (const void *) \ RTEMS_ALIGN_DOWN ( (size_t) mva, AARCH64_CACHE_L1_CPU_DATA_ALIGNMENT ) |