diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-05-19 08:18:25 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-05-20 11:05:26 +0200 |
| commit | bcef89f2360b97005e490c92fe624ab9dec789e6 (patch) | |
| tree | 61a05a2699d86de26b84acf355d9d9ddaa3c4c5b /bsps/riscv/riscv | |
| parent | bsps/microblaze: Add device tree support to GPIO (diff) | |
| download | rtems-bcef89f2360b97005e490c92fe624ab9dec789e6.tar.bz2 | |
Update company name
The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
Diffstat (limited to 'bsps/riscv/riscv')
| -rw-r--r-- | bsps/riscv/riscv/clock/clockdrv.c | 2 | ||||
| -rw-r--r-- | bsps/riscv/riscv/console/console-config.c | 2 | ||||
| -rw-r--r-- | bsps/riscv/riscv/include/bsp/irq.h | 2 | ||||
| -rw-r--r-- | bsps/riscv/riscv/include/bsp/riscv.h | 2 | ||||
| -rw-r--r-- | bsps/riscv/riscv/include/dev/serial/htif.h | 2 | ||||
| -rw-r--r-- | bsps/riscv/riscv/include/tm27.h | 2 | ||||
| -rw-r--r-- | bsps/riscv/riscv/irq/irq.c | 2 | ||||
| -rw-r--r-- | bsps/riscv/riscv/start/bsp_fatal_halt.c | 2 | ||||
| -rw-r--r-- | bsps/riscv/riscv/start/bspsmp.c | 2 | ||||
| -rw-r--r-- | bsps/riscv/riscv/start/bspstart.c | 2 |
10 files changed, 10 insertions, 10 deletions
diff --git a/bsps/riscv/riscv/clock/clockdrv.c b/bsps/riscv/riscv/clock/clockdrv.c index 6d70419a5c..ebbc9d77d9 100644 --- a/bsps/riscv/riscv/clock/clockdrv.c +++ b/bsps/riscv/riscv/clock/clockdrv.c @@ -8,7 +8,7 @@ */ /* - * Copyright (c) 2018, 2023 embedded brains GmbH + * Copyright (C) 2018, 2023 embedded brains GmbH & Co. KG * COPYRIGHT (c) 2015 Hesham Alatary <hesham@alumni.york.ac.uk> * * Redistribution and use in source and binary forms, with or without diff --git a/bsps/riscv/riscv/console/console-config.c b/bsps/riscv/riscv/console/console-config.c index 72743fe9d5..df9828cf27 100644 --- a/bsps/riscv/riscv/console/console-config.c +++ b/bsps/riscv/riscv/console/console-config.c @@ -11,7 +11,7 @@ */ /* - * Copyright (C) 2018 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/riscv/riscv/include/bsp/irq.h b/bsps/riscv/riscv/include/bsp/irq.h index 93c9780111..0c0dc1a48e 100644 --- a/bsps/riscv/riscv/include/bsp/irq.h +++ b/bsps/riscv/riscv/include/bsp/irq.h @@ -9,7 +9,7 @@ */ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> diff --git a/bsps/riscv/riscv/include/bsp/riscv.h b/bsps/riscv/riscv/include/bsp/riscv.h index d294f1ae58..5f8edb650d 100644 --- a/bsps/riscv/riscv/include/bsp/riscv.h +++ b/bsps/riscv/riscv/include/bsp/riscv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/riscv/riscv/include/dev/serial/htif.h b/bsps/riscv/riscv/include/dev/serial/htif.h index 4b16d87468..48a3782e31 100644 --- a/bsps/riscv/riscv/include/dev/serial/htif.h +++ b/bsps/riscv/riscv/include/dev/serial/htif.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/riscv/riscv/include/tm27.h b/bsps/riscv/riscv/include/tm27.h index 9fe6bcd255..239e860dc8 100644 --- a/bsps/riscv/riscv/include/tm27.h +++ b/bsps/riscv/riscv/include/tm27.h @@ -10,7 +10,7 @@ */ /* - * Copyright (C) 2022 embedded brains GmbH + * Copyright (C) 2022 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c index e8d297052b..4679d5a624 100644 --- a/bsps/riscv/riscv/irq/irq.c +++ b/bsps/riscv/riscv/irq/irq.c @@ -9,7 +9,7 @@ */ /* - * Copyright (C) 2018, 2022 embedded brains GmbH + * Copyright (C) 2018, 2022 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> diff --git a/bsps/riscv/riscv/start/bsp_fatal_halt.c b/bsps/riscv/riscv/start/bsp_fatal_halt.c index e4db1f03ca..06fffad6df 100644 --- a/bsps/riscv/riscv/start/bsp_fatal_halt.c +++ b/bsps/riscv/riscv/start/bsp_fatal_halt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> diff --git a/bsps/riscv/riscv/start/bspsmp.c b/bsps/riscv/riscv/start/bspsmp.c index 34796a5120..a6884299a0 100644 --- a/bsps/riscv/riscv/start/bspsmp.c +++ b/bsps/riscv/riscv/start/bspsmp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c index fa1e978dc7..d65741b13f 100644 --- a/bsps/riscv/riscv/start/bspstart.c +++ b/bsps/riscv/riscv/start/bspstart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions |