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* aarch64: whitespace fixes in start.SGedare Bloom2021-06-241-166/+166
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* bsps/aarch64: replace boot options with asm switch codeGedare Bloom2021-06-241-7/+8
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* bsps/aarch64: add non-secure mode and versal supportGedare Bloom2021-06-241-2/+16
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* bsps/aarch64: add physical secure timerGedare Bloom2021-06-241-0/+8
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* aarch64: add support to drop EL3 to EL2Kinsey Moore2021-06-241-1/+26
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* bsps/aarch64: Advertise cache function supportKinsey Moore2021-05-271-0/+10
| | | | | Ensure that cache functions are flagged as usable by the generic cache implementation code.
* bsps/aarch64: Align MVAs consistentlyKinsey Moore2021-05-271-8/+5
| | | | | | This fixes a bug where addresses were not being aligned correctly. Addresses used in cache functions are now aligned consistently using RTEMS_ALIGN_DOWN.
* bsps/aarch64: Break out system registersKinsey Moore2021-05-271-180/+33
| | | | | Break out system register definitions and accessors so that they're usable by other parts of RTEMS.
* bsps/aarch64: Add support for EL2 startKinsey Moore2021-03-051-0/+25
| | | | | Add the stub necessary to boot on AArch64 under EL2 and drop to EL1 for normal operation.
* bsps/aarch64: RTEMS_DEBUG stack alignment faultsKinsey Moore2021-03-051-0/+8
| | | | | | Run with stack alignment faults enabled under RTEMS_DEBUG to catch any stack misalignments early. This makes it easier to track them down should they ever occur.
* bsps/aarch64: Resolve usage of SUBALIGN()Kinsey Moore2021-03-051-4/+2
| | | | | | | | Remove usage of SUBALIGN() in aarch64 linkcmds which works around a difference in behavior on AArch64 platforms. This is no longer necessary since alignment is now enforced explicitly. Closes #4178.
* bsps: Add missing DWARF 5 sectionsSebastian Huber2021-01-261-3/+5
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* bsps: Support DWARF 5 sectionsSebastian Huber2021-01-251-8/+13
| | | | GCC 11 uses DWARF 5 by default.
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-231-58/+0
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
* bsps: Fix includesSebastian Huber2020-12-221-1/+0
| | | | Update #4202.
* bsps: Remove gicvx_interrupt_dispatch()Sebastian Huber2020-12-161-5/+0
| | | | | | Avoid one level of indirection. Update #4202.
* bsps: Move ARM GICv2 driver to bsps/sharedKinsey Moore2020-12-021-1/+1
| | | | | This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64 code.
* spec/aarch64: Only apply SUBALIGN(4) to ILP32Kinsey Moore2020-11-231-2/+4
| | | | | | | The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds was previously present on LP64 builds and causes no issues within RTEMS, but causes relocation/alignment issues when building libbsd. This restricts those alignment changes to ILP32 builds.
* bsps: Add Cortex-A53 ILP32 BSP variantKinsey Moore2020-10-051-0/+16
| | | | | | This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53 emulation with interrupt support using GICv3 and clock support using the ARM GPT.
* bsps: Add Cortex-A53 LP64 basic BSPKinsey Moore2020-10-055-0/+1432
This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with interrupt support using GICv3 and clock support using the ARM GPT.
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