diff options
| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2020-10-02 09:27:54 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2020-10-05 16:11:40 -0500 |
| commit | ed9c88cea8d5c086858b71e68becfac1e228f1b6 (patch) | |
| tree | 34e0e20d2c8c698e834051134b2f48f8d637c2ed /bsps/aarch64/shared | |
| parent | bsps: Add Cortex-A53 LP64 basic BSP (diff) | |
| download | rtems-ed9c88cea8d5c086858b71e68becfac1e228f1b6.tar.bz2 | |
bsps: Add Cortex-A53 ILP32 BSP variant
This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53
emulation with interrupt support using GICv3 and clock support using
the ARM GPT.
Diffstat (limited to 'bsps/aarch64/shared')
| -rw-r--r-- | bsps/aarch64/shared/start/start.S | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/bsps/aarch64/shared/start/start.S b/bsps/aarch64/shared/start/start.S index f60e840137..f4c62b2b6c 100644 --- a/bsps/aarch64/shared/start/start.S +++ b/bsps/aarch64/shared/start/start.S @@ -101,19 +101,31 @@ _start: * Get current per-CPU control and store it in PL1 only Thread ID * Register (TPIDRPRW). */ +#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 + ldr w1, =_Per_CPU_Information +#else ldr x1, =_Per_CPU_Information +#endif add x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2 mcr p15, 0, x1, c13, c0, 4 #endif /* Calculate interrupt stack area end for current processor */ +#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 + ldr w1, =_ISR_Stack_size +#else ldr x1, =_ISR_Stack_size +#endif #ifdef RTEMS_SMP add x3, x7, #1 mul x1, x1, x3 #endif +#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 + ldr w2, =_ISR_Stack_area_begin +#else ldr x2, =_ISR_Stack_area_begin +#endif add x3, x1, x2 /* Save original DAIF value */ @@ -135,7 +147,11 @@ _start: * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1 * Exception operation (synchronous errors, IRQ, FIQ, System Errors) uses SP0 */ +#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 + ldr w1, =bsp_stack_exception_size +#else ldr x1, =bsp_stack_exception_size +#endif /* Switch to SP0 and set exception stack */ msr spsel, #0 mov sp, x3 |