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| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2021-05-18 14:49:20 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2021-05-27 14:09:00 -0500 |
| commit | 8810e08371d007e92e87fe797eb3474f41855905 (patch) | |
| tree | 91d60ea72662ed9f3c759f37714ba3af05094950 /bsps/aarch64/shared | |
| parent | bsps/aarch64: Align MVAs consistently (diff) | |
| download | rtems-8810e08371d007e92e87fe797eb3474f41855905.tar.bz2 | |
bsps/aarch64: Advertise cache function support
Ensure that cache functions are flagged as usable by the generic cache
implementation code.
Diffstat (limited to 'bsps/aarch64/shared')
| -rw-r--r-- | bsps/aarch64/shared/cache/cache.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/bsps/aarch64/shared/cache/cache.c b/bsps/aarch64/shared/cache/cache.c index 47722c21e4..9e7446a077 100644 --- a/bsps/aarch64/shared/cache/cache.c +++ b/bsps/aarch64/shared/cache/cache.c @@ -39,6 +39,16 @@ #include <bsp/utility.h> #include <rtems/score/aarch64-system-registers.h> +#define CPU_DATA_CACHE_ALIGNMENT 64 + +#define CPU_INSTRUCTION_CACHE_ALIGNMENT 64 + +#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS + +#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS + +#define CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA + #define AARCH64_CACHE_L1_CPU_DATA_ALIGNMENT ( (size_t) 64 ) #define AARCH64_CACHE_PREPARE_MVA(mva) (const void *) \ RTEMS_ALIGN_DOWN ( (size_t) mva, AARCH64_CACHE_L1_CPU_DATA_ALIGNMENT ) |