bsps: Use header file for GIC architecture support

This avoids a function call overhead in the interrupt dispatching.

Update #4202.

1 files changed, 0 insertions, 58 deletions

diff --git a/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c b/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
deleted file mode 100644
index 4c26ec3c2b..0000000000
--- a/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSBSPsAArch64Shared
- *
- * @brief AArch64-specific ARM GICv3 handlers.
- */
-
-/*
- * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
- * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <dev/irq/arm-gic-irq.h>
-#include <bsp/irq-generic.h>
-
-void arm_interrupt_handler_dispatch(rtems_vector_number vector)
-{
-  uint32_t interrupt_level = _CPU_ISR_Get_level();
-  AArch64_interrupt_enable(1);
-  bsp_interrupt_handler_dispatch(vector);
-  _CPU_ISR_Set_level(interrupt_level);
-}
-
-void arm_interrupt_facility_set_exception_handler(void)
-{
-  AArch64_set_exception_handler(
-    AARCH64_EXCEPTION_SPx_IRQ,
-    _AArch64_Exception_interrupt_no_nest
-  );
-  AArch64_set_exception_handler(
-    AARCH64_EXCEPTION_SP0_IRQ,
-    _AArch64_Exception_interrupt_nest
-  );
-}