summaryrefslogtreecommitdiffstats
path: root/cpukit/score/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'cpukit/score/cpu')
-rw-r--r--cpukit/score/cpu/aarch64/aarch64-context-validate.S159
-rw-r--r--cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S19
-rw-r--r--cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S6
-rw-r--r--cpukit/score/cpu/aarch64/cpu.c4
-rw-r--r--cpukit/score/cpu/aarch64/cpu_asm.S78
-rw-r--r--cpukit/score/cpu/aarch64/include/rtems/asm.h5
-rw-r--r--[-rwxr-xr-x]cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h0
-rw-r--r--cpukit/score/cpu/aarch64/include/rtems/score/cpu.h17
-rw-r--r--cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h67
-rw-r--r--cpukit/score/cpu/arm/headers.am14
-rw-r--r--cpukit/score/cpu/bfin/headers.am11
-rw-r--r--cpukit/score/cpu/i386/cpu.c8
-rw-r--r--cpukit/score/cpu/i386/headers.am11
-rw-r--r--cpukit/score/cpu/lm32/headers.am8
-rw-r--r--cpukit/score/cpu/m68k/headers.am11
-rw-r--r--cpukit/score/cpu/microblaze/__tls_get_addr.c54
-rw-r--r--cpukit/score/cpu/microblaze/cpu.c121
-rw-r--r--cpukit/score/cpu/microblaze/cpu_asm.S194
-rw-r--r--cpukit/score/cpu/microblaze/include/rtems/asm.h138
-rw-r--r--cpukit/score/cpu/microblaze/include/rtems/score/cpu.h305
-rw-r--r--cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h41
-rw-r--r--cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h96
-rw-r--r--cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h57
-rw-r--r--cpukit/score/cpu/microblaze/microblaze-context-switch.S107
-rw-r--r--cpukit/score/cpu/microblaze/microblaze-context-validate.S117
-rw-r--r--cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S28
-rw-r--r--cpukit/score/cpu/mips/headers.am9
-rw-r--r--cpukit/score/cpu/moxie/headers.am7
-rw-r--r--cpukit/score/cpu/nios2/headers.am10
-rw-r--r--cpukit/score/cpu/no_cpu/headers.am6
-rw-r--r--cpukit/score/cpu/or1k/headers.am8
-rw-r--r--cpukit/score/cpu/powerpc/headers.am9
-rw-r--r--cpukit/score/cpu/riscv/headers.am11
-rw-r--r--cpukit/score/cpu/sh/headers.am7
-rw-r--r--cpukit/score/cpu/sparc/headers.am11
-rw-r--r--cpukit/score/cpu/sparc64/headers.am6
-rw-r--r--cpukit/score/cpu/v850/headers.am8
-rw-r--r--cpukit/score/cpu/x86_64/headers.am9
38 files changed, 1549 insertions, 228 deletions
diff --git a/cpukit/score/cpu/aarch64/aarch64-context-validate.S b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
index 1e71bc5b3a..1daa0d6bf2 100644
--- a/cpukit/score/cpu/aarch64/aarch64-context-validate.S
+++ b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
@@ -44,35 +44,47 @@
#include <rtems/score/cpu.h>
#include <rtems/score/basedefs.h>
-/* These must be 8 byte aligned to avoid misaligned accesses */
-#define FRAME_OFFSET_X4 0x00
-#define FRAME_OFFSET_X5 0x08
-#define FRAME_OFFSET_X6 0x10
-#define FRAME_OFFSET_X7 0x18
-#define FRAME_OFFSET_X8 0x20
-#define FRAME_OFFSET_X9 0x28
-#define FRAME_OFFSET_X10 0x30
-#define FRAME_OFFSET_X11 0x38
-#define FRAME_OFFSET_LR 0x40
+/*
+ * This register size applies to X (integer) registers as well as the D (lower
+ * half floating point) registers. It does not apply to V (full size floating
+ * point) registers or W (lower half integer) registers.
+ */
+#define AARCH64_REGISTER_SIZE 8
+
+/* According to the AAPCS64, X19-X28 are callee-saved registers */
+#define FRAME_OFFSET_X19 0x00
+#define FRAME_OFFSET_X20 0x08
+#define FRAME_OFFSET_X21 0x10
+#define FRAME_OFFSET_X22 0x18
+#define FRAME_OFFSET_X23 0x20
+#define FRAME_OFFSET_X24 0x28
+#define FRAME_OFFSET_X25 0x30
+#define FRAME_OFFSET_X26 0x38
+#define FRAME_OFFSET_X27 0x40
+#define FRAME_OFFSET_X28 0x48
+#define FRAME_OFFSET_LR 0x50
#ifdef AARCH64_MULTILIB_VFP
- /* These must be 16 byte aligned to avoid misaligned accesses */
- #define FRAME_OFFSET_V8 0x50
- #define FRAME_OFFSET_V9 0x60
- #define FRAME_OFFSET_V10 0x70
- #define FRAME_OFFSET_V11 0x80
- #define FRAME_OFFSET_V12 0x90
- #define FRAME_OFFSET_V13 0xA0
- #define FRAME_OFFSET_V14 0xB0
- #define FRAME_OFFSET_V15 0xC0
+ /*
+ * According to the AAPCS64, V8-V15 are callee-saved registers, but only the
+ * bottom 8 bytes are required to be saved which correspond to D8-D15.
+ */
+ #define FRAME_OFFSET_D8 0x58
+ #define FRAME_OFFSET_D9 0x60
+ #define FRAME_OFFSET_D10 0x68
+ #define FRAME_OFFSET_D11 0x70
+ #define FRAME_OFFSET_D12 0x78
+ #define FRAME_OFFSET_D13 0x80
+ #define FRAME_OFFSET_D14 0x88
+ #define FRAME_OFFSET_D15 0x90
/*
* Force 16 byte alignment of the frame size to avoid stack pointer alignment
* exceptions.
*/
- #define FRAME_SIZE RTEMS_ALIGN_UP( FRAME_OFFSET_V15, 16 )
+ #define FRAME_SIZE RTEMS_ALIGN_UP( FRAME_OFFSET_D15 + AARCH64_REGISTER_SIZE, 16 )
#else
- #define FRAME_SIZE RTEMS_ALIGN_UP( FRAME_OFFSET_LR, 16 )
+ #define FRAME_SIZE RTEMS_ALIGN_UP( FRAME_OFFSET_LR + AARCH64_REGISTER_SIZE, 16 )
#endif
.section .text
@@ -83,25 +95,27 @@ FUNCTION_ENTRY(_CPU_Context_validate)
sub sp, sp, #FRAME_SIZE
- str x4, [sp, #FRAME_OFFSET_X4]
- str x5, [sp, #FRAME_OFFSET_X5]
- str x6, [sp, #FRAME_OFFSET_X6]
- str x7, [sp, #FRAME_OFFSET_X7]
- str x8, [sp, #FRAME_OFFSET_X8]
- str x9, [sp, #FRAME_OFFSET_X9]
- str x10, [sp, #FRAME_OFFSET_X10]
- str x11, [sp, #FRAME_OFFSET_X11]
+ str x19, [sp, #FRAME_OFFSET_X19]
+ str x20, [sp, #FRAME_OFFSET_X20]
+ str x21, [sp, #FRAME_OFFSET_X21]
+ str x22, [sp, #FRAME_OFFSET_X22]
+ str x23, [sp, #FRAME_OFFSET_X23]
+ str x24, [sp, #FRAME_OFFSET_X24]
+ str x25, [sp, #FRAME_OFFSET_X25]
+ str x26, [sp, #FRAME_OFFSET_X26]
+ str x27, [sp, #FRAME_OFFSET_X27]
+ str x28, [sp, #FRAME_OFFSET_X28]
str lr, [sp, #FRAME_OFFSET_LR]
#ifdef AARCH64_MULTILIB_VFP
- str d8, [sp, #FRAME_OFFSET_V8]
- str d9, [sp, #FRAME_OFFSET_V9]
- str d10, [sp, #FRAME_OFFSET_V10]
- str d11, [sp, #FRAME_OFFSET_V11]
- str d12, [sp, #FRAME_OFFSET_V12]
- str d13, [sp, #FRAME_OFFSET_V13]
- str d14, [sp, #FRAME_OFFSET_V14]
- str d15, [sp, #FRAME_OFFSET_V15]
+ str d8, [sp, #FRAME_OFFSET_D8]
+ str d9, [sp, #FRAME_OFFSET_D9]
+ str d10, [sp, #FRAME_OFFSET_D10]
+ str d11, [sp, #FRAME_OFFSET_D11]
+ str d12, [sp, #FRAME_OFFSET_D12]
+ str d13, [sp, #FRAME_OFFSET_D13]
+ str d14, [sp, #FRAME_OFFSET_D14]
+ str d15, [sp, #FRAME_OFFSET_D15]
#endif
/* Fill */
@@ -119,7 +133,7 @@ FUNCTION_ENTRY(_CPU_Context_validate)
#ifdef AARCH64_MULTILIB_VFP
- /* X3 contains the FPSCR */
+ /* X3 contains the FPSR */
mrs x3, FPSR
ldr x4, =0xf000001f
bic x3, x3, x4
@@ -139,6 +153,23 @@ FUNCTION_ENTRY(_CPU_Context_validate)
fill_register x10
fill_register x11
fill_register x12
+ fill_register x13
+ fill_register x14
+ fill_register x15
+ fill_register x16
+ fill_register x17
+ fill_register x18
+ fill_register x19
+ fill_register x20
+ fill_register x21
+ fill_register x22
+ fill_register x23
+ fill_register x24
+ fill_register x25
+ fill_register x26
+ fill_register x27
+ fill_register x28
+ fill_register x29
fill_register lr
#ifdef AARCH64_MULTILIB_VFP
@@ -191,7 +222,6 @@ check:
bne restore
.endm
- /* A compare involving the stack pointer is deprecated */
mov x1, sp
cmp x2, x1
bne restore
@@ -211,6 +241,23 @@ check:
check_register x10
check_register x11
check_register x12
+ check_register x13
+ check_register x14
+ check_register x15
+ check_register x16
+ check_register x17
+ check_register x18
+ check_register x19
+ check_register x20
+ check_register x21
+ check_register x22
+ check_register x23
+ check_register x24
+ check_register x25
+ check_register x26
+ check_register x27
+ check_register x28
+ check_register x29
check_register lr
#ifdef AARCH64_MULTILIB_VFP
@@ -222,25 +269,27 @@ check:
/* Restore */
restore:
- ldr x4, [sp, #FRAME_OFFSET_X4]
- ldr x5, [sp, #FRAME_OFFSET_X5]
- ldr x6, [sp, #FRAME_OFFSET_X6]
- ldr x7, [sp, #FRAME_OFFSET_X7]
- ldr x8, [sp, #FRAME_OFFSET_X8]
- ldr x9, [sp, #FRAME_OFFSET_X9]
- ldr x10, [sp, #FRAME_OFFSET_X10]
- ldr x11, [sp, #FRAME_OFFSET_X11]
+ ldr x19, [sp, #FRAME_OFFSET_X19]
+ ldr x20, [sp, #FRAME_OFFSET_X20]
+ ldr x21, [sp, #FRAME_OFFSET_X21]
+ ldr x22, [sp, #FRAME_OFFSET_X22]
+ ldr x23, [sp, #FRAME_OFFSET_X23]
+ ldr x24, [sp, #FRAME_OFFSET_X24]
+ ldr x25, [sp, #FRAME_OFFSET_X25]
+ ldr x26, [sp, #FRAME_OFFSET_X26]
+ ldr x27, [sp, #FRAME_OFFSET_X27]
+ ldr x28, [sp, #FRAME_OFFSET_X28]
ldr lr, [sp, #FRAME_OFFSET_LR]
#ifdef AARCH64_MULTILIB_VFP
- ldr d8, [sp, #FRAME_OFFSET_V8]
- ldr d9, [sp, #FRAME_OFFSET_V9]
- ldr d10, [sp, #FRAME_OFFSET_V10]
- ldr d11, [sp, #FRAME_OFFSET_V11]
- ldr d12, [sp, #FRAME_OFFSET_V12]
- ldr d13, [sp, #FRAME_OFFSET_V13]
- ldr d14, [sp, #FRAME_OFFSET_V14]
- ldr d15, [sp, #FRAME_OFFSET_V15]
+ ldr d8, [sp, #FRAME_OFFSET_D8]
+ ldr d9, [sp, #FRAME_OFFSET_D9]
+ ldr d10, [sp, #FRAME_OFFSET_D10]
+ ldr d11, [sp, #FRAME_OFFSET_D11]
+ ldr d12, [sp, #FRAME_OFFSET_D12]
+ ldr d13, [sp, #FRAME_OFFSET_D13]
+ ldr d14, [sp, #FRAME_OFFSET_D14]
+ ldr d15, [sp, #FRAME_OFFSET_D15]
#endif
add sp, sp, #FRAME_SIZE
diff --git a/cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S b/cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S
index 2be5ce69ff..73472b81ac 100644
--- a/cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S
+++ b/cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S
@@ -90,10 +90,29 @@ FUNCTION_ENTRY(_CPU_Context_volatile_clobber)
clobber_vfp_register d31
#endif /* AARCH64_MULTILIB_VFP */
+/*
+ * According to the AAPCS64, X0-X18 and X29 are caller-saved registers. X0 is
+ * already being clobbered.
+ */
clobber_register x1
clobber_register x2
clobber_register x3
+ clobber_register x4
+ clobber_register x5
+ clobber_register x6
+ clobber_register x7
+ clobber_register x8
+ clobber_register x9
+ clobber_register x10
+ clobber_register x11
clobber_register x12
+ clobber_register x13
+ clobber_register x14
+ clobber_register x15
+ clobber_register x16
+ clobber_register x17
+ clobber_register x18
+ clobber_register x29
ret
diff --git a/cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S b/cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S
index cb0954a29b..b206f5764b 100644
--- a/cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S
+++ b/cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S
@@ -47,7 +47,11 @@
.globl _AArch64_Exception_interrupt_nest
#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
- #define SELF_CPU_CONTROL_GET_REG w19
+ #ifdef RTEMS_SMP
+ #define SELF_CPU_CONTROL_GET_REG x19
+ #else
+ #define SELF_CPU_CONTROL_GET_REG w19
+ #endif
#else
#define SELF_CPU_CONTROL_GET_REG x19
#endif
diff --git a/cpukit/score/cpu/aarch64/cpu.c b/cpukit/score/cpu/aarch64/cpu.c
index d09403a349..b36f55ae17 100644
--- a/cpukit/score/cpu/aarch64/cpu.c
+++ b/cpukit/score/cpu/aarch64/cpu.c
@@ -146,7 +146,7 @@ void _CPU_Context_Initialize(
}
}
-void _CPU_ISR_Set_level( uint64_t level )
+void _CPU_ISR_Set_level( uint32_t level )
{
/* Set the mask bit if interrupts are disabled */
level = level ? AARCH64_PSTATE_I : 0;
@@ -156,7 +156,7 @@ void _CPU_ISR_Set_level( uint64_t level )
);
}
-uint64_t _CPU_ISR_Get_level( void )
+uint32_t _CPU_ISR_Get_level( void )
{
uint64_t level;
diff --git a/cpukit/score/cpu/aarch64/cpu_asm.S b/cpukit/score/cpu/aarch64/cpu_asm.S
index 9e609e06bd..2379698336 100644
--- a/cpukit/score/cpu/aarch64/cpu_asm.S
+++ b/cpukit/score/cpu/aarch64/cpu_asm.S
@@ -55,13 +55,22 @@
*
*/
+DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
+ .globl _CPU_Context_switch_no_return
+ .set _CPU_Context_switch_no_return, _CPU_Context_switch
#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
-#define reg_2 w2
+/* Sanitize inputs for ILP32 ABI */
+ mov w0, w0
+ mov w1, w1
+ #ifdef RTEMS_SMP
+ #define reg_2 x2
+ #else
+ #define reg_2 w2
+ #endif
#else
#define reg_2 x2
#endif
-DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
/* Start saving context */
GET_SELF_CPU_CONTROL reg_2
ldr w3, [x2, #PER_CPU_ISR_DISPATCH_DISABLE]
@@ -86,7 +95,30 @@ DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
str x3, [x0, #AARCH64_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE]
#ifdef RTEMS_SMP
-#error SMP not yet supported
+ /*
+ * The executing thread no longer executes on this processor. Switch
+ * the stack to the temporary interrupt stack of this processor. Mark
+ * the context of the executing thread as not executing.
+ */
+ dmb SY
+ add sp, x2, #(PER_CPU_INTERRUPT_FRAME_AREA + CPU_INTERRUPT_FRAME_SIZE)
+ mov x3, #0
+ strb w3, [x0, #AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET]
+
+.L_check_is_executing:
+
+ /* Check the is executing indicator of the heir context */
+ add x3, x1, #AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET
+ ldaxrb w4, [x3]
+ cmp x4, #0
+ bne .L_get_potential_new_heir
+
+ /* Try to update the is executing indicator of the heir context */
+ mov x4, #1
+ stlxrb w5, w4, [x3]
+ cmp x5, #0
+ bne .L_get_potential_new_heir
+ dmb SY
#endif
/* Start restoring context */
@@ -129,6 +161,46 @@ DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
*
*/
DEFINE_FUNCTION_AARCH64(_CPU_Context_restore)
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+/* Sanitize input for ILP32 ABI */
+ mov w0, w0
+#endif
+
mov x1, x0
GET_SELF_CPU_CONTROL reg_2
b .L_restore
+
+#ifdef RTEMS_SMP
+.L_get_potential_new_heir:
+
+ /* We may have a new heir */
+
+ /* Read the executing and heir */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+ ldr w4, [x2, #PER_CPU_OFFSET_EXECUTING]
+ ldr w5, [x2, #PER_CPU_OFFSET_HEIR]
+#else
+ ldr x4, [x2, #PER_CPU_OFFSET_EXECUTING]
+ ldr x5, [x2, #PER_CPU_OFFSET_HEIR]
+#endif
+
+ /*
+ * Update the executing only if necessary to avoid cache line
+ * monopolization.
+ */
+ cmp x4, x5
+ beq .L_check_is_executing
+
+ /* Calculate the heir context pointer */
+ sub x4, x1, x4
+ add x1, x5, x4
+
+ /* Update the executing */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+ str w5, [x2, #PER_CPU_OFFSET_EXECUTING]
+#else
+ str x5, [x2, #PER_CPU_OFFSET_EXECUTING]
+#endif
+
+ b .L_check_is_executing
+#endif
diff --git a/cpukit/score/cpu/aarch64/include/rtems/asm.h b/cpukit/score/cpu/aarch64/include/rtems/asm.h
index 35bf533c8a..fa53e08291 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/asm.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/asm.h
@@ -81,7 +81,12 @@
.align 8 ; .globl name ; name: ; .globl name ## _aarch64 ; name ## _aarch64:
.macro GET_SELF_CPU_CONTROL REG
+#ifdef RTEMS_SMP
+ /* Use Thread ID Register (TPIDR_EL1) */
+ mrs \REG, TPIDR_EL1
+#else
ldr \REG, =_Per_CPU_Information
+#endif
.endm
/** @} */
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h b/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h
index dc2afdeca8..dc2afdeca8 100755..100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index dacc18638e..ae7e2bdcba 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -134,9 +134,9 @@
#ifdef RTEMS_SMP
#if defined(AARCH64_MULTILIB_VFP)
- #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x70
+ #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0xb8
#else
- #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x30
+ #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x78
#endif
#endif
@@ -191,12 +191,12 @@ typedef struct {
static inline void _AARCH64_Data_memory_barrier( void )
{
- __asm__ volatile ( "dmb LD" : : : "memory" );
+ __asm__ volatile ( "dmb SY" : : : "memory" );
}
static inline void _AARCH64_Data_synchronization_barrier( void )
{
- __asm__ volatile ( "dsb LD" : : : "memory" );
+ __asm__ volatile ( "dsb SY" : : : "memory" );
}
static inline void _AARCH64_Instruction_synchronization_barrier( void )
@@ -204,9 +204,9 @@ static inline void _AARCH64_Instruction_synchronization_barrier( void )
__asm__ volatile ( "isb" : : : "memory" );
}
-void _CPU_ISR_Set_level( uint64_t level );
+void _CPU_ISR_Set_level( uint32_t level );
-uint64_t _CPU_ISR_Get_level( void );
+uint32_t _CPU_ISR_Get_level( void );
#if defined(AARCH64_DISABLE_INLINE_ISR_DISABLE_ENABLE)
uint64_t AArch64_interrupt_disable( void );
@@ -313,6 +313,11 @@ void _CPU_ISR_install_vector(
*/
void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
+RTEMS_NO_RETURN void _CPU_Context_switch_no_return(
+ Context_Control *executing,
+ Context_Control *heir
+);
+
RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
#ifdef RTEMS_SMP
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
index 0536ecd860..90fd48ad4e 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
@@ -50,7 +50,7 @@
*/
#define CPU_PER_CPU_CONTROL_SIZE 0
-#define CPU_INTERRUPT_FRAME_SIZE 240
+#define CPU_INTERRUPT_FRAME_SIZE 0x2E0
#ifndef ASM
@@ -60,6 +60,71 @@ extern "C" {
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
+typedef struct {
+ uint64_t x0;
+ uint64_t register_lr_original;
+ uint64_t register_lr;
+ uint64_t x1;
+ uint64_t x2;
+ uint64_t x3;
+ uint64_t x4;
+ uint64_t x5;
+ uint64_t x6;
+ uint64_t x7;
+ uint64_t x8;
+ uint64_t x9;
+ uint64_t x10;
+ uint64_t x11;
+ uint64_t x12;
+ uint64_t x13;
+ uint64_t x14;
+ uint64_t x15;
+ uint64_t x16;
+ uint64_t x17;
+ uint64_t x18;
+ uint64_t x19;
+ uint64_t x20;
+ uint64_t x21;
+#ifdef AARCH64_MULTILIB_VFP
+ uint128_t q0;
+ uint128_t q1;
+ uint128_t q2;
+ uint128_t q3;
+ uint128_t q4;
+ uint128_t q5;
+ uint128_t q6;
+ uint128_t q7;
+ uint128_t q8;
+ uint128_t q9;
+ uint128_t q10;
+ uint128_t q11;
+ uint128_t q12;
+ uint128_t q13;
+ uint128_t q14;
+ uint128_t q15;
+ uint128_t q16;
+ uint128_t q17;
+ uint128_t q18;
+ uint128_t q19;
+ uint128_t q20;
+ uint128_t q21;
+ uint128_t q22;
+ uint128_t q23;
+ uint128_t q24;
+ uint128_t q25;
+ uint128_t q26;
+ uint128_t q27;
+ uint128_t q28;
+ uint128_t q29;
+ uint128_t q30;
+ uint128_t q31;
+#endif /* AARCH64_MULTILIB_VFP */
+ uint64_t register_elr;
+ uint64_t register_spsr;
+ uint64_t register_fpsr;
+ uint64_t register_fpcr;
+} CPU_Interrupt_frame;
+
void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );
diff --git a/cpukit/score/cpu/arm/headers.am b/cpukit/score/cpu/arm/headers.am
deleted file mode 100644
index cb8976fdbc..0000000000
--- a/cpukit/score/cpu/arm/headers.am
+++ /dev/null
@@ -1,14 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_libcpu_HEADERS += score/cpu/arm/include/libcpu/arm-cp15.h
-include_machine_HEADERS += score/cpu/arm/include/machine/elf_machdep.h
-include_rtems_HEADERS += score/cpu/arm/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/arm/include/rtems/score/aarch32-pmsa.h
-include_rtems_score_HEADERS += score/cpu/arm/include/rtems/score/aarch32-system-registers.h
-include_rtems_score_HEADERS += score/cpu/arm/include/rtems/score/arm.h
-include_rtems_score_HEADERS += score/cpu/arm/include/rtems/score/armv4.h
-include_rtems_score_HEADERS += score/cpu/arm/include/rtems/score/armv7m.h
-include_rtems_score_HEADERS += score/cpu/arm/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/arm/include/rtems/score/cpu_asm.h
-include_rtems_score_HEADERS += score/cpu/arm/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/arm/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/arm/include/rtems/score/paravirt.h
diff --git a/cpukit/score/cpu/bfin/headers.am b/cpukit/score/cpu/bfin/headers.am
deleted file mode 100644
index e0f6cfca74..0000000000
--- a/cpukit/score/cpu/bfin/headers.am
+++ /dev/null
@@ -1,11 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_machine_HEADERS += score/cpu/bfin/include/machine/elf_machdep.h
-include_rtems_HEADERS += score/cpu/bfin/include/rtems/asm.h
-include_rtems_bfin_HEADERS += score/cpu/bfin/include/rtems/bfin/bf52x.h
-include_rtems_bfin_HEADERS += score/cpu/bfin/include/rtems/bfin/bf533.h
-include_rtems_bfin_HEADERS += score/cpu/bfin/include/rtems/bfin/bfin.h
-include_rtems_score_HEADERS += score/cpu/bfin/include/rtems/score/bfin.h
-include_rtems_score_HEADERS += score/cpu/bfin/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/bfin/include/rtems/score/cpu_asm.h
-include_rtems_score_HEADERS += score/cpu/bfin/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/bfin/include/rtems/score/cpuimpl.h
diff --git a/cpukit/score/cpu/i386/cpu.c b/cpukit/score/cpu/i386/cpu.c
index 77b7a7161c..f4e3e4d754 100644
--- a/cpukit/score/cpu/i386/cpu.c
+++ b/cpukit/score/cpu/i386/cpu.c
@@ -215,16 +215,16 @@ void _CPU_Exception_frame_print (const CPU_Exception_frame *ctx)
{
unsigned int faultAddr = 0;
printk("----------------------------------------------------------\n");
- printk("Exception %" PRIu32 " caught at PC %" PRIx32 " by thread %" PRId32 "\n",
+ printk("Exception %" PRIu32 " caught at PC %" PRIx32 " by thread %" PRIx32 "\n",
ctx->idtIndex,
ctx->eip,
_Thread_Executing->Object.id);
printk("----------------------------------------------------------\n");
printk("Processor execution context at time of the fault was :\n");
printk("----------------------------------------------------------\n");
- printk(" EAX = %" PRIx32 " EBX = %" PRIx32 " ECX = %" PRIx32 " EDX = %" PRIx32 "\n",
+ printk(" EAX = 0x%08" PRIx32 " EBX = 0x%08" PRIx32 " ECX = 0x%08" PRIx32 " EDX = 0x%08" PRIx32 "\n",
ctx->eax, ctx->ebx, ctx->ecx, ctx->edx);
- printk(" ESI = %" PRIx32 " EDI = %" PRIx32 " EBP = %" PRIx32 " ESP = %" PRIx32 "\n",
+ printk(" ESI = 0x%08" PRIx32 " EDI = 0x%08" PRIx32 " EBP = 0x%08" PRIx32 " ESP = 0x%08" PRIx32 "\n",
ctx->esi, ctx->edi, ctx->ebp, ctx->esp0);
printk("----------------------------------------------------------\n");
printk("Error code pushed by processor itself (if not 0) = %" PRIx32 "\n",
@@ -250,7 +250,7 @@ void _CPU_Exception_frame_print (const CPU_Exception_frame *ctx)
printk("Call Stack Trace of EIP:\n");
if ( fp ) {
for ( i=1; fp->up; fp=fp->up, i++ ) {
- printk("0x%08" PRIx32 " ",fp->pc);
+ printk("0x%08" PRIxPTR " ",fp->pc);
if ( ! (i&3) )
printk("\n");
}
diff --git a/cpukit/score/cpu/i386/headers.am b/cpukit/score/cpu/i386/headers.am
deleted file mode 100644
index e984232d9b..0000000000
--- a/cpukit/score/cpu/i386/headers.am
+++ /dev/null
@@ -1,11 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_machine_HEADERS += score/cpu/i386/include/machine/elf_machdep.h
-include_rtems_HEADERS += score/cpu/i386/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/i386/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/i386/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/i386/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/i386/include/rtems/score/i386.h
-include_rtems_score_HEADERS += score/cpu/i386/include/rtems/score/idtr.h
-include_rtems_score_HEADERS += score/cpu/i386/include/rtems/score/interrupts.h
-include_rtems_score_HEADERS += score/cpu/i386/include/rtems/score/paravirt.h
-include_rtems_score_HEADERS += score/cpu/i386/include/rtems/score/registers.h
diff --git a/cpukit/score/cpu/lm32/headers.am b/cpukit/score/cpu/lm32/headers.am
deleted file mode 100644
index b77dfb5ab3..0000000000
--- a/cpukit/score/cpu/lm32/headers.am
+++ /dev/null
@@ -1,8 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_machine_HEADERS += score/cpu/lm32/include/machine/elf_machdep.h
-include_rtems_HEADERS += score/cpu/lm32/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/lm32/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/lm32/include/rtems/score/cpu_asm.h
-include_rtems_score_HEADERS += score/cpu/lm32/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/lm32/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/lm32/include/rtems/score/lm32.h
diff --git a/cpukit/score/cpu/m68k/headers.am b/cpukit/score/cpu/m68k/headers.am
deleted file mode 100644
index 3fdc6fe2bd..0000000000
--- a/cpukit/score/cpu/m68k/headers.am
+++ /dev/null
@@ -1,11 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_machine_HEADERS += score/cpu/m68k/include/machine/elf_machdep.h
-include_rtems_HEADERS += score/cpu/m68k/include/rtems/asm.h
-include_rtems_m68k_HEADERS += score/cpu/m68k/include/rtems/m68k/m68302.h
-include_rtems_m68k_HEADERS += score/cpu/m68k/include/rtems/m68k/m68360.h
-include_rtems_m68k_HEADERS += score/cpu/m68k/include/rtems/m68k/qsm.h
-include_rtems_m68k_HEADERS += score/cpu/m68k/include/rtems/m68k/sim.h
-include_rtems_score_HEADERS += score/cpu/m68k/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/m68k/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/m68k/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/m68k/include/rtems/score/m68k.h
diff --git a/cpukit/score/cpu/microblaze/__tls_get_addr.c b/cpukit/score/cpu/microblaze/__tls_get_addr.c
new file mode 100644
index 0000000000..e779a63488
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/__tls_get_addr.c
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMicroBlaze
+ *
+ * @brief MicroBlaze thread-local storage implementation
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems/score/threadimpl.h>
+#include <rtems/score/tls.h>
+
+#include <assert.h>
+
+void *__tls_get_addr( const TLS_Index *ti );
+
+void *__tls_get_addr( const TLS_Index *ti )
+{
+ const Thread_Control *executing = _Thread_Get_executing();
+ void *tls_block = (char *) executing->Start.tls_area
+ + _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment );
+
+ return (char *) tls_block + ti->offset;
+}
diff --git a/cpukit/score/cpu/microblaze/cpu.c b/cpukit/score/cpu/microblaze/cpu.c
new file mode 100644
index 0000000000..de8fbfbba1
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/cpu.c
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMicroBlaze
+ *
+ * @brief MicroBlaze architecture support implementation
+ */
+
+/*
+ * Copyright (c) 2015, Hesham Almatary
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems/score/isr.h>
+#include <rtems/score/tls.h>
+#include <rtems/score/wkspace.h>
+
+void _CPU_Initialize( void )
+{
+}
+
+void _CPU_Context_Initialize(
+ Context_Control *context,
+ void *stack_area_begin,
+ size_t stack_area_size,
+ uint32_t new_level,
+ void (*entry_point)( void ),
+ bool is_fp,
+ void *tls_area
+)
+{
+ uint32_t stack = (uint32_t) stack_area_begin;
+ uint32_t stack_high = stack + stack_area_size;
+
+ memset( context, 0, sizeof(*context) ) ;
+
+ context->r1 = stack_high - 64;
+ context->r15 = (uint32_t) entry_point;
+
+ uint32_t msr;
+ _CPU_MSR_GET( msr );
+ context->rmsr = msr;
+
+ if ( tls_area != NULL ) {
+ _TLS_TCB_at_area_begin_initialize( tls_area );
+ }
+}
+
+void _CPU_Exception_frame_print( const CPU_Exception_frame *ctx )
+{
+}
+
+void _CPU_ISR_Set_level( uint32_t level )
+{
+ uint32_t microblaze_switch_reg;
+
+ _CPU_MSR_GET( microblaze_switch_reg );
+
+ if ( level == 0 ) {
+ microblaze_switch_reg |= (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE);
+ } else {
+ microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE);
+ }
+
+ _CPU_MSR_SET( microblaze_switch_reg );
+}
+
+uint32_t _CPU_ISR_Get_level( void )
+{
+ uint32_t level;
+
+ _CPU_MSR_GET( level );
+
+ /* This is unique. The MSR register contains an interrupt enable flag where
+ * most other architectures have an interrupt disable flag. */
+ return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) == 0;
+}
+
+void _CPU_ISR_install_vector(
+ uint32_t vector,
+ CPU_ISR_handler new_handler,
+ CPU_ISR_handler *old_handler
+)
+{
+ *old_handler = _ISR_Vector_table[ vector ];
+ _ISR_Vector_table[ vector ] = new_handler;
+}
+
+void *_CPU_Thread_Idle_body( uintptr_t ignored )
+{
+ while ( true ) {
+ __asm__ volatile ( "sleep" );
+ }
+}
diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S b/cpukit/score/cpu/microblaze/cpu_asm.S
new file mode 100644
index 0000000000..d095e62f69
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/cpu_asm.S
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMicroBlaze
+ *
+ * @brief MicroBlaze interrupt handler implementation
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rtems/asm.h>
+#include <rtems/score/percpu.h>
+
+ .text
+ .globl _ISR_Handler
+ .align 2
+
+_ISR_Handler:
+ /* Save stack frame */
+ swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
+ swi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
+ swi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
+ swi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
+ swi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
+ swi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
+ swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
+ swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
+ swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
+ swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
+ swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
+
+ xori r3, r5, 0xFFFF
+ beqi r3, do_exception
+
+ /* Disable dispatching */
+ lwi r3, r0, _Per_CPU_Information + 16
+ addik r3, r3, 1
+ swi r3, r0, _Per_CPU_Information + 16
+
+ swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
+
+ /* Is SP < INTERRUPT_STACK_LOW? */
+ lwi r4, r0, _Per_CPU_Information
+ rsubk r3, r4, r1
+ blei r3, switch_to_interrupt_stack
+
+ /* Is SP > INTERRUPT_STACK_HIGH? */
+ lwi r4, r0, _Per_CPU_Information + 4
+ rsubk r3, r4, r1
+ bgei r3, switch_to_interrupt_stack
+
+ bri on_interrupt_stack
+
+switch_to_interrupt_stack:
+ add r4, r0, r1
+ lwi r1, r0, _Per_CPU_Information + 4
+ addik r1, r1, -52
+ swi r4, r1, 0
+
+on_interrupt_stack:
+ /* Add 1 to ISR_NEST_LEVEL */
+ lwi r3, r0, _Per_CPU_Information + 8
+ addik r3, r3, 1
+ swi r3, r0, _Per_CPU_Information + 8
+
+ bralid r15, bsp_interrupt_dispatch
+ nop
+
+ /* Subtract 1 from ISR_NEST_LEVEL */
+ lwi r3, r0, _Per_CPU_Information + 8
+ addik r3, r3, -1
+ swi r3, r0, _Per_CPU_Information + 8
+
+ /* Is ISR_NEST_LEVEL > 0? */
+ bgti r3, after_stack_switch
+
+ /* Switch back to interrupted thread stack */
+ lwi r1, r1, 0
+
+after_stack_switch:
+ /* Subtract 1 from THREAD_DISPATCH_DISABLE_LEVEL */
+ lwi r3, r0, _Per_CPU_Information + 16
+ addik r3, r3, -1
+ swi r3, r0, _Per_CPU_Information + 16
+
+ /* Is THREAD_DISPATCH_DISABLE_LEVEL != 0? */
+ bnei r3, quick_exit
+
+ /* Is DISPATCH_NEEDED == 0? */
+ lwi r3, r0, _Per_CPU_Information + 20
+ beqi r3, quick_exit
+
+ /* Return to interrupted thread and make it do a dispatch */
+ addik r14, r0, thread_dispatch
+ rtid r14, 0
+ nop
+
+quick_exit:
+ /* Simple return from nested interrupt */
+ /* Restore registers */
+ lwi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
+ lwi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
+ lwi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
+ lwi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
+ lwi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
+ lwi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
+ lwi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
+ lwi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
+ lwi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
+ lwi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
+ lwi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
+ lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
+ lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
+
+ /* Remove stack frame */
+ addik r1, r1, 52
+
+ rtid r14, 0
+ nop
+
+thread_dispatch:
+ /* Reserve stack */
+ addik r1, r1, -52
+ /* Save scratch registers */
+ swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
+ swi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
+ swi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
+ swi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
+ swi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
+ swi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
+ swi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
+ swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
+ swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
+ swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
+ swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
+ swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
+ swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
+
+ bralid r15, _Thread_Dispatch
+ nop
+
+ /* Restore scratch registers */
+ lwi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
+ lwi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
+ lwi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
+ lwi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
+ lwi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
+ lwi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
+ lwi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
+ lwi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
+ lwi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
+ lwi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
+ lwi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
+ lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
+ lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
+ /* Free stack space */
+ addik r1, r1, 52
+
+ bri quick_exit
+
+do_exception:
+ /* exception no longer in progress */
+ mfs r3, rmsr
+ andni r3, r3, 0x200
+ mts rmsr, r3
+ addi r5, r0, 9
+ add r6, r0, r1
+
+ brai _Terminate
diff --git a/cpukit/score/cpu/microblaze/include/rtems/asm.h b/cpukit/score/cpu/microblaze/include/rtems/asm.h
new file mode 100644
index 0000000000..2e35a66294
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/include/rtems/asm.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @brief MicroBlaze assembler support
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets. It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ */
+
+/*
+ * Copyright (c) 2015, Hesham Almatary
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_ASM_H
+#define _RTEMS_ASM_H
+
+/*
+ * Indicate we are in an assembly file and get the basic CPU definitions.
+ */
+
+#ifndef ASM
+#define ASM
+#endif
+
+#include <rtems/score/cpuopts.h>
+
+#ifndef __USER_LABEL_PREFIX__
+/**
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents. If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
+ *
+ * This symbol is prefixed to all C program symbols.
+ */
+#define __USER_LABEL_PREFIX__ _
+#endif
+
+#ifndef __REGISTER_PREFIX__
+/**
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents. If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
+ *
+ * This symbol is prefixed to all register names.
+ */
+#define __REGISTER_PREFIX__
+#endif
+
+#include <rtems/concat.h>
+
+/** Use the right prefix for global labels. */
+#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+
+/** Use the right prefix for registers. */
+#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
+
+/*
+ * define macros for all of the registers on this CPU
+ *
+ * EXAMPLE: #define d0 REG (d0)
+ */
+
+/*
+ * Define macros to handle section beginning and ends.
+ */
+
+
+/** This macro is used to denote the beginning of a code declaration. */
+#define BEGIN_CODE_DCL .text
+/** This macro is used to denote the end of a code declaration. */
+#define END_CODE_DCL
+/** This macro is used to denote the beginning of a data declaration section. */
+#define BEGIN_DATA_DCL .data
+/** This macro is used to denote the end of a data declaration section. */
+#define END_DATA_DCL
+/** This macro is used to denote the beginning of a code section. */
+#define BEGIN_CODE .text
+/** This macro is used to denote the end of a code section. */
+#define END_CODE
+/** This macro is used to denote the beginning of a data section. */
+#define BEGIN_DATA
+/** This macro is used to denote the end of a data section. */
+#define END_DATA
+/** This macro is used to denote the beginning of the
+ * unitialized data section.
+ */
+#define BEGIN_BSS
+/** This macro is used to denote the end of the unitialized data section. */
+#define END_BSS
+/** This macro is used to denote the end of the assembly file. */
+#define END
+
+/**
+ * This macro is used to declare a public global symbol.
+ *
+ * @note This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
+ */
+#define PUBLIC(sym) .globl SYM (sym)
+
+/**
+ * This macro is used to prototype a public global symbol.
+ *
+ * @note This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
+ */
+#define EXTERN(sym) .globl SYM (sym)
+
+#endif
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
new file mode 100644
index 0000000000..4b11625463
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPU
+ *
+ * @brief MicroBlaze architecture support
+ */
+
+/*
+ * Copyright (c) 2015, Hesham Almatary
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_SCORE_CPU_H
+#define _RTEMS_SCORE_CPU_H
+
+#include <rtems/score/basedefs.h>
+#include <rtems/score/microblaze.h>
+
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
+#define CPU_ISR_PASSES_FRAME_POINTER FALSE
+
+#define CPU_HARDWARE_FP FALSE
+
+#define CPU_SOFTWARE_FP FALSE
+
+#define CPU_ALL_TASKS_ARE_FP FALSE
+
+#define CPU_IDLE_TASK_IS_FP FALSE
+
+#define CPU_USE_DEFERRED_FP_SWITCH FALSE
+
+#define CPU_STACK_GROWS_UP FALSE
+
+/**
+ * The maximum cache-line size is 16 words.
+ */
+#define CPU_CACHE_LINE_BYTES 64
+
+#define CPU_STRUCTURE_ALIGNMENT
+
+#define CPU_MODES_INTERRUPT_MASK 0x00000001
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup CPUContext Management
+ * This defines the minimal set of integer and processor state registers
+ * that must be saved during a voluntary context switch from one thread
+ * to another.
+ */
+typedef struct {
+ uint32_t r1;
+ uint32_t r13;
+ uint32_t r14;
+ uint32_t r15;
+ uint32_t r16;
+ uint32_t r17;
+ uint32_t r18;
+ uint32_t r19;
+ uint32_t r20;
+ uint32_t r21;
+ uint32_t r22;
+ uint32_t r23;
+ uint32_t r24;
+ uint32_t r25;
+ uint32_t r26;
+ uint32_t r27;
+ uint32_t r28;
+ uint32_t r29;
+ uint32_t r30;
+ uint32_t r31;
+ uint32_t rmsr;
+} Context_Control;
+
+/**
+ * @ingroup CPUContext Management
+ *
+ * This macro returns the stack pointer associated with @a _context.
+ *
+ * @param[in] _context is the thread context area to access
+ *
+ * @return This method returns the stack pointer.
+ */
+#define _CPU_Context_Get_SP( _context ) \
+ (_context)->r1
+
+#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
+
+#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
+
+#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
+
+#define CPU_MAXIMUM_PROCESSORS 32
+
+/**
+ * @ingroup CPUInterrupt
+ * This defines the highest interrupt vector number for this port.
+ */
+#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
+
+#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
+
+#define CPU_STACK_MINIMUM_SIZE (1024*4)
+
+#define CPU_ALIGNMENT 4
+
+#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
+
+#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
+
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
+#define MICROBLAZE_MSR_IE (1 << 1)
+#define MICROBLAZE_MSR_EE (1 << 8)
+
+#define _CPU_MSR_GET( _msr_value ) \
+ do { \
+ (_msr_value) = 0; \
+ __asm__ volatile ("mfs %0, rmsr" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
+ } while (0)
+
+#define _CPU_MSR_SET( _msr_value ) \
+{ __asm__ volatile ("mts rmsr, %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
+
+#define _CPU_ISR_Disable( _isr_cookie ) \
+ { \
+ unsigned int _new_msr; \
+ _CPU_MSR_GET(_isr_cookie); \
+ _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \
+ _CPU_MSR_SET(_new_msr); \
+ }
+
+#define _CPU_ISR_Enable( _isr_cookie ) \
+ { \
+ uint32_t _microblaze_interrupt_enable; \
+ uint32_t _microblaze_switch_reg; \
+ \
+ _microblaze_interrupt_enable = (_isr_cookie) & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \
+ _CPU_MSR_GET(_microblaze_switch_reg); \
+ _microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \
+ _microblaze_switch_reg |= _microblaze_interrupt_enable; \
+ _CPU_MSR_SET(_microblaze_switch_reg); \
+ }
+
+#define _CPU_ISR_Flash( _isr_cookie ) \
+ { \
+ unsigned int _new_msr; \
+ _CPU_MSR_SET(_isr_cookie); \
+ _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \
+ _CPU_MSR_SET(_new_msr); \
+ }
+
+void _CPU_ISR_Set_level( uint32_t level );
+
+uint32_t _CPU_ISR_Get_level( void );
+
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) != 0;
+}
+
+void _CPU_Context_Initialize(
+ Context_Control *context,
+ void *stack_area_begin,
+ size_t stack_area_size,
+ uint32_t new_level,
+ void (*entry_point)( void ),
+ bool is_fp,
+ void *tls_area
+);
+
+#define _CPU_Context_Restart_self( _the_context ) \
+ _CPU_Context_restore( (_the_context) );
+
+#define _CPU_Context_Initialize_fp( _destination ) \
+ { \
+ *(*(_destination)) = _CPU_Null_fp_context; \
+ }
+
+/* end of Context handler macros */
+
+/* Fatal Error manager macros */
+
+/* TODO */
+#define _CPU_Fatal_halt(_source, _error ) \
+ do { \
+ __asm__ volatile ( "sleep" ); \
+ for(;;) {} \
+ } while (0)
+
+/* end of Fatal Error manager macros */
+
+/* Bitfield handler macros */
+
+#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
+
+#define CPU_SIZEOF_POINTER 4
+
+#define CPU_PER_CPU_CONTROL_SIZE 0
+
+typedef struct {
+ /* TODO: enumerate registers */
+ uint32_t r[32];
+} CPU_Exception_frame;
+
+/* end of Priority handler macros */
+
+/* functions */
+
+void _CPU_Initialize( void );
+
+typedef void ( *CPU_ISR_handler )( uint32_t );
+
+void _CPU_ISR_install_vector(
+ uint32_t vector,
+ CPU_ISR_handler new_handler,
+ CPU_ISR_handler *old_handler
+);
+
+void _CPU_Context_switch(
+ Context_Control *run,
+ Context_Control *heir
+);
+
+RTEMS_NO_RETURN void _CPU_Context_restore(
+ Context_Control *new_context
+);
+
+static inline uint32_t CPU_swap_u32(
+ uint32_t value
+)
+{
+ uint32_t byte1, byte2, byte3, byte4, swapped;
+
+ byte4 = (value >> 24) & 0xff;
+ byte3 = (value >> 16) & 0xff;
+ byte2 = (value >> 8) & 0xff;
+ byte1 = value & 0xff;
+
+ swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
+ return swapped;
+}
+
+#define CPU_swap_u16( value ) \
+ (((value&0xff) << 8) | ((value >> 8)&0xff))
+
+void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
+
+typedef uint32_t CPU_Counter_ticks;
+
+uint32_t _CPU_Counter_frequency( void );
+
+CPU_Counter_ticks _CPU_Counter_read( void );
+
+static inline CPU_Counter_ticks _CPU_Counter_difference(
+ CPU_Counter_ticks second,
+ CPU_Counter_ticks first
+)
+{
+ return second - first;
+}
+
+void *_CPU_Thread_Idle_body( uintptr_t ignored );
+
+void bsp_interrupt_dispatch( uint32_t source );
+
+/** Type that can store a 32-bit integer or a pointer. */
+typedef uintptr_t CPU_Uint32ptr;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ASM */
+
+#endif /* _RTEMS_SCORE_CPU_H */
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h
new file mode 100644
index 0000000000..6dc769b95a
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPU
+ *
+ * @brief MicroBlaze atomic support
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
+#define _RTEMS_SCORE_ATOMIC_CPU_H
+
+#include <rtems/score/cpustdatomic.h>
+
+#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
new file mode 100644
index 0000000000..3d0167dd40
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPU
+ *
+ * @brief CPU Port Implementation API
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_SCORE_CPUIMPL_H
+#define _RTEMS_SCORE_CPUIMPL_H
+
+#include <rtems/score/cpu.h>
+
+/**
+ * @defgroup RTEMSScoreCPUMicroBlaze MicroBlaze
+ *
+ * @ingroup RTEMSScoreCPU
+ *
+ * @brief MicroBlaze Architecture Support
+ *
+ * @{
+ */
+
+#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_INTERRUPT_FRAME_SIZE 52
+
+#define MICROBLAZE_INTERRUPT_FRAME_R3 0
+#define MICROBLAZE_INTERRUPT_FRAME_R4 4
+#define MICROBLAZE_INTERRUPT_FRAME_R5 8
+#define MICROBLAZE_INTERRUPT_FRAME_R6 12
+#define MICROBLAZE_INTERRUPT_FRAME_R7 16
+#define MICROBLAZE_INTERRUPT_FRAME_R8 20
+#define MICROBLAZE_INTERRUPT_FRAME_R9 24
+#define MICROBLAZE_INTERRUPT_FRAME_R10 28
+#define MICROBLAZE_INTERRUPT_FRAME_R11 32
+#define MICROBLAZE_INTERRUPT_FRAME_R12 36
+#define MICROBLAZE_INTERRUPT_FRAME_R14 40
+#define MICROBLAZE_INTERRUPT_FRAME_R15 44
+#define MICROBLAZE_INTERRUPT_FRAME_R18 48
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _CPU_Context_volatile_clobber( uintptr_t pattern );
+
+void _CPU_Context_validate( uintptr_t pattern );
+
+RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+{
+ __asm__ volatile ( ".word 0x0" );
+}
+
+RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+{
+ __asm__ volatile ( "nop" );
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ASM */
+
+/** @} */
+
+#endif /* _RTEMS_SCORE_CPUIMPL_H */
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h b/cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h
new file mode 100644
index 0000000000..6310b4b17d
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPU
+ *
+ * @brief MicroBlaze architecture support
+ */
+
+/*
+ * Copyright (c) 2015, Hesham Almatary
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_SCORE_MICROBLAZE_H
+#define _RTEMS_SCORE_MICROBLAZE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CPU_MODEL_NAME "MicroBlaze"
+#define NOCPU_HAS_FPU 1
+
+/*
+ * Define the name of the CPU family.
+ */
+
+#define CPU_NAME "MicroBlaze CPU"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTEMS_SCORE_MICROBLAZE_H */
diff --git a/cpukit/score/cpu/microblaze/microblaze-context-switch.S b/cpukit/score/cpu/microblaze/microblaze-context-switch.S
new file mode 100644
index 0000000000..523e836398
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/microblaze-context-switch.S
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMicroBlaze
+ *
+ * @brief MicroBlaze context switch implementation
+ */
+
+/*
+ * Copyright (c) 2015, Hesham Almatary
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+ #include "config.h"
+#endif
+
+#include <rtems/asm.h>
+
+.text
+.align 4
+
+PUBLIC(_CPU_Context_switch)
+PUBLIC(_CPU_Context_restore)
+PUBLIC(_CPU_Context_restore_fp)
+PUBLIC(_CPU_Context_save_fp)
+
+SYM(_CPU_Context_switch):
+ swi r1, r5, 0
+ swi r13, r5, 4
+ swi r14, r5, 8
+ swi r15, r5, 12
+ swi r16, r5, 16
+ swi r17, r5, 20
+ swi r18, r5, 24
+ swi r19, r5, 28
+ swi r20, r5, 32
+ swi r21, r5, 36
+ swi r22, r5, 40
+ swi r23, r5, 44
+ swi r24, r5, 48
+ swi r25, r5, 52
+ swi r26, r5, 56
+ swi r27, r5, 60
+ swi r28, r5, 64
+ swi r29, r5, 68
+ swi r30, r5, 72
+ swi r31, r5, 76
+
+ mfs r21, rmsr
+ swi r21, r5, 80
+
+
+SYM(restore):
+ lwi r1, r6, 0
+ lwi r13, r6, 4
+ lwi r14, r6, 8
+ lwi r15, r6, 12
+ lwi r16, r6, 16
+ lwi r17, r6, 20
+ lwi r18, r6, 24
+ lwi r19, r6, 28
+ lwi r20, r6, 32
+ lwi r21, r6, 36
+ lwi r22, r6, 40
+ lwi r23, r6, 44
+ lwi r24, r6, 48
+ lwi r25, r6, 52
+ lwi r26, r6, 56
+ lwi r27, r6, 60
+ lwi r28, r6, 64
+ lwi r29, r6, 68
+ lwi r30, r6, 72
+
+ lwi r31, r6, 80
+ mts rmsr, r31
+
+ lwi r31, r6, 76
+
+ rtsd r15, 8
+
+SYM(_CPU_Context_restore):
+ add r6, r5, r0
+ brai restore
diff --git a/cpukit/score/cpu/microblaze/microblaze-context-validate.S b/cpukit/score/cpu/microblaze/microblaze-context-validate.S
new file mode 100644
index 0000000000..b12d5930f6
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/microblaze-context-validate.S
@@ -0,0 +1,117 @@
+#ifdef HAVE_CONFIG_H
+ #include "config.h"
+#endif
+
+#include <rtems/asm.h>
+
+#define FRAME_OFFSET_R19 0
+#define FRAME_OFFSET_R20 4
+#define FRAME_OFFSET_R21 8
+#define FRAME_OFFSET_R22 12
+#define FRAME_OFFSET_R23 16
+#define FRAME_OFFSET_R24 20
+#define FRAME_OFFSET_R25 24
+#define FRAME_OFFSET_R26 28
+#define FRAME_OFFSET_R27 32
+#define FRAME_OFFSET_R28 36
+#define FRAME_OFFSET_R29 40
+#define FRAME_OFFSET_R30 44
+#define FRAME_OFFSET_R31 48
+
+#define FRAME_SIZE (FRAME_OFFSET_R31 + 4)
+
+.text
+.align 4
+
+PUBLIC(_CPU_Context_validate)
+
+SYM(_CPU_Context_validate):
+
+ /* Save */
+ addik r1, r1, -FRAME_SIZE
+ swi r19, r1, FRAME_OFFSET_R19
+ swi r20, r1, FRAME_OFFSET_R20
+ swi r21, r1, FRAME_OFFSET_R21
+ swi r22, r1, FRAME_OFFSET_R22
+ swi r23, r1, FRAME_OFFSET_R23
+ swi r24, r1, FRAME_OFFSET_R24
+ swi r25, r1, FRAME_OFFSET_R25
+ swi r26, r1, FRAME_OFFSET_R26
+ swi r27, r1, FRAME_OFFSET_R27
+ swi r28, r1, FRAME_OFFSET_R28
+ swi r29, r1, FRAME_OFFSET_R29
+ swi r30, r1, FRAME_OFFSET_R30
+ swi r31, r1, FRAME_OFFSET_R31
+
+ /* Fill */
+
+ add r4, r0, r3
+
+ /* r7 contains the stack pointer */
+ add r7, r0, r1
+
+.macro fill_register reg
+ addi r4, r4, 1
+ add \reg, r0, r4
+.endm
+
+ fill_register r21
+ fill_register r22
+ fill_register r23
+ fill_register r24
+ fill_register r25
+ fill_register r26
+ fill_register r27
+ fill_register r28
+ fill_register r29
+ fill_register r30
+ fill_register r31
+
+ /* Check */
+check:
+
+.macro check_register reg
+ addi r4, r4, 1
+ cmp r6, \reg, r4
+ bnei r6, restore
+.endm
+
+ cmp r6, r7, r1
+ bnei r6, restore
+
+ add r4, r0, r3
+
+ check_register r21
+ check_register r22
+ check_register r23
+ check_register r24
+ check_register r25
+ check_register r26
+ check_register r27
+ check_register r28
+ check_register r29
+ check_register r30
+ check_register r31
+
+ brai check
+
+ /* Restore */
+restore:
+
+ lwi r19, r1, FRAME_OFFSET_R19
+ lwi r20, r1, FRAME_OFFSET_R20
+ lwi r21, r1, FRAME_OFFSET_R21
+ lwi r22, r1, FRAME_OFFSET_R22
+ lwi r23, r1, FRAME_OFFSET_R23
+ lwi r24, r1, FRAME_OFFSET_R24
+ lwi r25, r1, FRAME_OFFSET_R25
+ lwi r26, r1, FRAME_OFFSET_R26
+ lwi r27, r1, FRAME_OFFSET_R27
+ lwi r28, r1, FRAME_OFFSET_R28
+ lwi r29, r1, FRAME_OFFSET_R29
+ lwi r30, r1, FRAME_OFFSET_R30
+ lwi r31, r1, FRAME_OFFSET_R31
+
+ addik r1, r1, FRAME_SIZE
+
+ bra r15
diff --git a/cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S b/cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S
new file mode 100644
index 0000000000..fb49dc5e40
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S
@@ -0,0 +1,28 @@
+#ifdef HAVE_CONFIG_H
+ #include "config.h"
+#endif
+
+#include <rtems/asm.h>
+
+.text
+.align 4
+
+PUBLIC(_CPU_Context_volatile_clobber)
+
+SYM(_CPU_Context_volatile_clobber):
+
+.macro clobber_register reg
+ addi r5, r5, -1
+ add \reg, r0, r5
+.endm
+
+ clobber_register r3
+ clobber_register r4
+ clobber_register r6
+ clobber_register r7
+ clobber_register r8
+ clobber_register r9
+ clobber_register r10
+
+ rtsd r15, 8
+ nop
diff --git a/cpukit/score/cpu/mips/headers.am b/cpukit/score/cpu/mips/headers.am
deleted file mode 100644
index 3084000f09..0000000000
--- a/cpukit/score/cpu/mips/headers.am
+++ /dev/null
@@ -1,9 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_machine_HEADERS += score/cpu/mips/include/machine/elf_machdep.h
-include_rtems_HEADERS += score/cpu/mips/include/rtems/asm.h
-include_rtems_mips_HEADERS += score/cpu/mips/include/rtems/mips/idtcpu.h
-include_rtems_mips_HEADERS += score/cpu/mips/include/rtems/mips/iregdef.h
-include_rtems_score_HEADERS += score/cpu/mips/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/mips/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/mips/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/mips/include/rtems/score/mips.h
diff --git a/cpukit/score/cpu/moxie/headers.am b/cpukit/score/cpu/moxie/headers.am
deleted file mode 100644
index 6324166c86..0000000000
--- a/cpukit/score/cpu/moxie/headers.am
+++ /dev/null
@@ -1,7 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_machine_HEADERS += score/cpu/moxie/include/machine/elf_machdep.h
-include_rtems_HEADERS += score/cpu/moxie/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/moxie/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/moxie/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/moxie/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/moxie/include/rtems/score/moxie.h
diff --git a/cpukit/score/cpu/nios2/headers.am b/cpukit/score/cpu/nios2/headers.am
deleted file mode 100644
index 253f64d03a..0000000000
--- a/cpukit/score/cpu/nios2/headers.am
+++ /dev/null
@@ -1,10 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_machine_HEADERS += score/cpu/nios2/include/machine/elf_machdep.h
-include_rtems_HEADERS += score/cpu/nios2/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/nios2/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/nios2/include/rtems/score/cpu_asm.h
-include_rtems_score_HEADERS += score/cpu/nios2/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/nios2/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/nios2/include/rtems/score/nios2-count-zeros.h
-include_rtems_score_HEADERS += score/cpu/nios2/include/rtems/score/nios2-utility.h
-include_rtems_score_HEADERS += score/cpu/nios2/include/rtems/score/nios2.h
diff --git a/cpukit/score/cpu/no_cpu/headers.am b/cpukit/score/cpu/no_cpu/headers.am
deleted file mode 100644
index 6a8c54df42..0000000000
--- a/cpukit/score/cpu/no_cpu/headers.am
+++ /dev/null
@@ -1,6 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_rtems_HEADERS += score/cpu/no_cpu/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/no_cpu/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/no_cpu/include/rtems/score/cpu_asm.h
-include_rtems_score_HEADERS += score/cpu/no_cpu/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/no_cpu/include/rtems/score/no_cpu.h
diff --git a/cpukit/score/cpu/or1k/headers.am b/cpukit/score/cpu/or1k/headers.am
deleted file mode 100644
index e65d66464d..0000000000
--- a/cpukit/score/cpu/or1k/headers.am
+++ /dev/null
@@ -1,8 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_rtems_HEADERS += score/cpu/or1k/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/or1k/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/or1k/include/rtems/score/cpu_asm.h
-include_rtems_score_HEADERS += score/cpu/or1k/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/or1k/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/or1k/include/rtems/score/or1k-utility.h
-include_rtems_score_HEADERS += score/cpu/or1k/include/rtems/score/or1k.h
diff --git a/cpukit/score/cpu/powerpc/headers.am b/cpukit/score/cpu/powerpc/headers.am
deleted file mode 100644
index 5f016a21d1..0000000000
--- a/cpukit/score/cpu/powerpc/headers.am
+++ /dev/null
@@ -1,9 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_machine_HEADERS += score/cpu/powerpc/include/machine/elf_machdep.h
-include_rtems_HEADERS += score/cpu/powerpc/include/rtems/asm.h
-include_rtems_powerpc_HEADERS += score/cpu/powerpc/include/rtems/powerpc/registers.h
-include_rtems_score_HEADERS += score/cpu/powerpc/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/powerpc/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/powerpc/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/powerpc/include/rtems/score/paravirt.h
-include_rtems_score_HEADERS += score/cpu/powerpc/include/rtems/score/powerpc.h
diff --git a/cpukit/score/cpu/riscv/headers.am b/cpukit/score/cpu/riscv/headers.am
deleted file mode 100644
index eb863cb28c..0000000000
--- a/cpukit/score/cpu/riscv/headers.am
+++ /dev/null
@@ -1,11 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_libcpu_HEADERS += score/cpu/riscv/include/libcpu/access.h
-include_libcpu_HEADERS += score/cpu/riscv/include/libcpu/byteorder.h
-include_machine_HEADERS += score/cpu/riscv/include/machine/elf_machdep.h
-include_rtems_HEADERS += score/cpu/riscv/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/riscv/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/riscv/include/rtems/score/cpu_asm.h
-include_rtems_score_HEADERS += score/cpu/riscv/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/riscv/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/riscv/include/rtems/score/riscv-utility.h
-include_rtems_score_HEADERS += score/cpu/riscv/include/rtems/score/riscv.h
diff --git a/cpukit/score/cpu/sh/headers.am b/cpukit/score/cpu/sh/headers.am
deleted file mode 100644
index ccb3b94eb5..0000000000
--- a/cpukit/score/cpu/sh/headers.am
+++ /dev/null
@@ -1,7 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_rtems_HEADERS += score/cpu/sh/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/sh/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/sh/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/sh/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/sh/include/rtems/score/sh.h
-include_rtems_score_HEADERS += score/cpu/sh/include/rtems/score/sh_io.h
diff --git a/cpukit/score/cpu/sparc/headers.am b/cpukit/score/cpu/sparc/headers.am
deleted file mode 100644
index 25eaeaa74a..0000000000
--- a/cpukit/score/cpu/sparc/headers.am
+++ /dev/null
@@ -1,11 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_libcpu_HEADERS += score/cpu/sparc/include/libcpu/access.h
-include_libcpu_HEADERS += score/cpu/sparc/include/libcpu/byteorder.h
-include_libcpu_HEADERS += score/cpu/sparc/include/libcpu/grlib-tn-0018.h
-include_machine_HEADERS += score/cpu/sparc/include/machine/elf_machdep.h
-include_rtems_HEADERS += score/cpu/sparc/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/sparc/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/sparc/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/sparc/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/sparc/include/rtems/score/sparc.h
-include_rtems_score_HEADERS += score/cpu/sparc/include/rtems/score/sparcimpl.h
diff --git a/cpukit/score/cpu/sparc64/headers.am b/cpukit/score/cpu/sparc64/headers.am
deleted file mode 100644
index a2a1c1fb2c..0000000000
--- a/cpukit/score/cpu/sparc64/headers.am
+++ /dev/null
@@ -1,6 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_rtems_HEADERS += score/cpu/sparc64/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/sparc64/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/sparc64/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/sparc64/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/sparc64/include/rtems/score/sparc64.h
diff --git a/cpukit/score/cpu/v850/headers.am b/cpukit/score/cpu/v850/headers.am
deleted file mode 100644
index 547f128401..0000000000
--- a/cpukit/score/cpu/v850/headers.am
+++ /dev/null
@@ -1,8 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_machine_HEADERS += score/cpu/v850/include/machine/elf_machdep.h
-include_rtems_HEADERS += score/cpu/v850/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/v850/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/v850/include/rtems/score/cpu_asm.h
-include_rtems_score_HEADERS += score/cpu/v850/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/v850/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/v850/include/rtems/score/v850.h
diff --git a/cpukit/score/cpu/x86_64/headers.am b/cpukit/score/cpu/x86_64/headers.am
deleted file mode 100644
index 3ce32c3317..0000000000
--- a/cpukit/score/cpu/x86_64/headers.am
+++ /dev/null
@@ -1,9 +0,0 @@
-## This file was generated by "./boostrap -H".
-include_machine_HEADERS += score/cpu/x86_64/include/machine/elf_machdep.h
-include_rtems_HEADERS += score/cpu/x86_64/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/x86_64/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/x86_64/include/rtems/score/cpu_asm.h
-include_rtems_score_HEADERS += score/cpu/x86_64/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/x86_64/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/x86_64/include/rtems/score/idt.h
-include_rtems_score_HEADERS += score/cpu/x86_64/include/rtems/score/x86_64.h