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-rw-r--r--cpukit/score/cpu/aarch64/cpu.c44
1 files changed, 14 insertions, 30 deletions
diff --git a/cpukit/score/cpu/aarch64/cpu.c b/cpukit/score/cpu/aarch64/cpu.c
index d09403a349..207508302b 100644
--- a/cpukit/score/cpu/aarch64/cpu.c
+++ b/cpukit/score/cpu/aarch64/cpu.c
@@ -142,21 +142,27 @@ void _CPU_Context_Initialize(
the_context->thread_id = (uintptr_t) tls_area;
if ( tls_area != NULL ) {
- _TLS_TCB_at_area_begin_initialize( tls_area );
+ the_context->thread_id = (uintptr_t) _TLS_Initialize_area( tls_area );
}
}
-void _CPU_ISR_Set_level( uint64_t level )
+void _CPU_ISR_Set_level( uint32_t level )
{
/* Set the mask bit if interrupts are disabled */
- level = level ? AARCH64_PSTATE_I : 0;
- __asm__ volatile (
- "msr DAIF, %[level]\n"
- : : [level] "r" (level)
- );
+ if ( level ) {
+ __asm__ volatile (
+ "msr DAIFSet, #0x2\n"
+ : : [level] "r" (level)
+ );
+ } else {
+ __asm__ volatile (
+ "msr DAIFClr, #0x2\n"
+ : : [level] "r" (level)
+ );
+ }
}
-uint64_t _CPU_ISR_Get_level( void )
+uint32_t _CPU_ISR_Get_level( void )
{
uint64_t level;
@@ -168,28 +174,6 @@ uint64_t _CPU_ISR_Get_level( void )
return ( level & AARCH64_PSTATE_I ) != 0;
}
-void _CPU_ISR_install_vector(
- uint32_t vector,
- CPU_ISR_handler new_handler,
- CPU_ISR_handler *old_handler
-)
-{
- /* Redirection table starts at the end of the vector table */
- CPU_ISR_handler *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4);
-
- CPU_ISR_handler current_handler = table [vector];
-
- /* The current handler is now the old one */
- if (old_handler != NULL) {
- *old_handler = current_handler;
- }
-
- /* Write only if necessary to avoid writes to a maybe read-only memory */
- if (current_handler != new_handler) {
- table [vector] = new_handler;
- }
-}
-
void _CPU_Initialize( void )
{
/* Do nothing */