diff options
Diffstat (limited to 'c/src/lib/libcpu')
147 files changed, 22 insertions, 87662 deletions
diff --git a/c/src/lib/libcpu/Makefile.am b/c/src/lib/libcpu/Makefile.am index 38de255d1a..9cc2ece050 100644 --- a/c/src/lib/libcpu/Makefile.am +++ b/c/src/lib/libcpu/Makefile.am @@ -1,5 +1,3 @@ -include_libcpudir = $(includedir)/libcpu - EXTRA_DIST = EXTRA_DIST += shared/include/cache.h EXTRA_DIST += shared/src/cache_manager.c diff --git a/c/src/lib/libcpu/arm/Makefile.am b/c/src/lib/libcpu/arm/Makefile.am index 7f76673cfd..35b08e2495 100644 --- a/c/src/lib/libcpu/arm/Makefile.am +++ b/c/src/lib/libcpu/arm/Makefile.am @@ -6,17 +6,9 @@ EXTRA_DIST = noinst_PROGRAMS = -include_bspdir = $(includedir)/bsp -include_libcpudir = $(includedir)/libcpu - -include_bsp_HEADERS = -include_libcpu_HEADERS = - ## shared/include if shared -include_libcpu_HEADERS += shared/include/mmu.h - ## shared/arm920 noinst_PROGRAMS += shared/arm920.rel shared_arm920_rel_SOURCES = shared/arm920/mmu.c @@ -24,5 +16,4 @@ shared_arm920_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/src shared_arm920_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/arm/configure.ac b/c/src/lib/libcpu/arm/configure.ac index c72c34eb19..a5e3e1cc88 100644 --- a/c/src/lib/libcpu/arm/configure.ac +++ b/c/src/lib/libcpu/arm/configure.ac @@ -4,6 +4,8 @@ AC_PREREQ([2.69]) AC_INIT([rtems-c-src-lib-libcpu-arm],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([shared]) RTEMS_TOP([../../../../..],[../../..]) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP RTEMS_CANONICAL_TARGET_CPU diff --git a/c/src/lib/libcpu/arm/preinstall.am b/c/src/lib/libcpu/arm/preinstall.am deleted file mode 100644 index 31e0da295b..0000000000 --- a/c/src/lib/libcpu/arm/preinstall.am +++ /dev/null @@ -1,30 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/bsp/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp - @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) - -$(PROJECT_INCLUDE)/libcpu/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu - @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - -if shared -$(PROJECT_INCLUDE)/libcpu/mmu.h: shared/include/mmu.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h -endif diff --git a/c/src/lib/libcpu/arm/shared/include/am335x.h b/c/src/lib/libcpu/arm/shared/include/am335x.h deleted file mode 100644 index 367e97cae9..0000000000 --- a/c/src/lib/libcpu/arm/shared/include/am335x.h +++ /dev/null @@ -1,704 +0,0 @@ -/* - * Copyright (c) 2012 Claas Ziemke. All rights reserved. - * - * Claas Ziemke - * Kernerstrasse 11 - * 70182 Stuttgart - * Germany - * <claas.ziemke@gmx.net> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified by Ben Gras <beng@shrike-systems.com> to add lots - * of beagleboard/beaglebone definitions, delete lpc32xx specific - * ones, and merge with some other header files. - */ - -#if !defined(_AM335X_H_) -#define _AM335X_H_ - -/* Interrupt controller memory map */ -#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */ - -/* Interrupt controller memory map */ -#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */ - -#define AM335X_INT_EMUINT 0 - /* Emulation interrupt (EMUICINTR) */ -#define AM335X_INT_COMMTX 1 - /* CortexA8 COMMTX */ -#define AM335X_INT_COMMRX 2 - /* CortexA8 COMMRX */ -#define AM335X_INT_BENCH 3 - /* CortexA8 NPMUIRQ */ -#define AM335X_INT_ELM_IRQ 4 - /* Sinterrupt (Error location process completion) */ -#define AM335X_INT_NMI 7 - /* nmi_int */ -#define AM335X_INT_L3DEBUG 9 - /* l3_FlagMux_top_FlagOut1 */ -#define AM335X_INT_L3APPINT 10 - /* l3_FlagMux_top_FlagOut0 */ -#define AM335X_INT_PRCMINT 11 - /* irq_mpu */ -#define AM335X_INT_EDMACOMPINT 12 - /* tpcc_int_pend_po0 */ -#define AM335X_INT_EDMAMPERR 13 - /* tpcc_mpint_pend_po */ -#define AM335X_INT_EDMAERRINT 14 - /* tpcc_errint_pend_po */ -#define AM335X_INT_ADC_TSC_GENINT 16 - /* gen_intr_pend */ -#define AM335X_INT_USBSSINT 17 - /* usbss_intr_pend */ -#define AM335X_INT_USB0 18 - /* usb0_intr_pend */ -#define AM335X_INT_USB1 19 - /* usb1_intr_pend */ -#define AM335X_INT_PRUSS1_EVTOUT0 20 - /* pr1_host_intr0_intr_pend */ -#define AM335X_INT_PRUSS1_EVTOUT1 21 - /* pr1_host_intr1_intr_pend */ -#define AM335X_INT_PRUSS1_EVTOUT2 22 - /* pr1_host_intr2_intr_pend */ -#define AM335X_INT_PRUSS1_EVTOUT3 23 - /* pr1_host_intr3_intr_pend */ -#define AM335X_INT_PRUSS1_EVTOUT4 24 - /* pr1_host_intr4_intr_pend */ -#define AM335X_INT_PRUSS1_EVTOUT5 25 - /* pr1_host_intr5_intr_pend */ -#define AM335X_INT_PRUSS1_EVTOUT6 26 - /* pr1_host_intr6_intr_pend */ -#define AM335X_INT_PRUSS1_EVTOUT7 27 - /* pr1_host_intr7_intr_pend */ -#define AM335X_INT_MMCSD1INT 28 - /* MMCSD1 SINTERRUPTN */ -#define AM335X_INT_MMCSD2INT 29 - /* MMCSD2 SINTERRUPT */ -#define AM335X_INT_I2C2INT 30 - /* I2C2 POINTRPEND */ -#define AM335X_INT_eCAP0INT 31 - /* ecap_intr_intr_pend */ -#define AM335X_INT_GPIOINT2A 32 - /* GPIO 2 POINTRPEND1 */ -#define AM335X_INT_GPIOINT2B 33 - /* GPIO 2 POINTRPEND2 */ -#define AM335X_INT_USBWAKEUP 34 - /* USBSS slv0p_Swakeup */ -#define AM335X_INT_LCDCINT 36 - /* LCDC lcd_irq */ -#define AM335X_INT_GFXINT 37 - /* SGX530 THALIAIRQ */ -#define AM335X_INT_ePWM2INT 39 - /* (PWM Subsystem) epwm_intr_intr_pend */ -#define AM335X_INT_3PGSWRXTHR0 40 - /* (Ethernet) c0_rx_thresh_pend (RX_THRESH_PULSE) */ -#define AM335X_INT_3PGSWRXINT0 41 - /* CPSW (Ethernet) c0_rx_pend */ -#define AM335X_INT_3PGSWTXINT0 42 - /* CPSW (Ethernet) c0_tx_pend */ -#define AM335X_INT_3PGSWMISC0 43 - /* CPSW (Ethernet) c0_misc_pend */ -#define AM335X_INT_UART3INT 44 - /* UART3 niq */ -#define AM335X_INT_UART4INT 45 - /* UART4 niq */ -#define AM335X_INT_UART5INT 46 - /* UART5 niq */ -#define AM335X_INT_eCAP1INT 47 - /* (PWM Subsystem) ecap_intr_intr_pend */ -#define AM335X_INT_DCAN0_INT0 52 - /* DCAN0 dcan_intr0_intr_pend */ -#define AM335X_INT_DCAN0_INT1 53 - /* DCAN0 dcan_intr1_intr_pend */ -#define AM335X_INT_DCAN0_PARITY 54 - /* DCAN0 dcan_uerr_intr_pend */ -#define AM335X_INT_DCAN1_INT0 55 - /* DCAN1 dcan_intr0_intr_pend */ -#define AM335X_INT_DCAN1_INT1 56 - /* DCAN1 dcan_intr1_intr_pend */ -#define AM335X_INT_DCAN1_PARITY 57 - /* DCAN1 dcan_uerr_intr_pend */ -#define AM335X_INT_ePWM0_TZINT 58 - /* eHRPWM0 TZ interrupt (PWM epwm_tz_intr_pend Subsystem) */ -#define AM335X_INT_ePWM1_TZINT 59 - /* eHRPWM1 TZ interrupt (PWM epwm_tz_intr_pend Subsystem) */ -#define AM335X_INT_ePWM2_TZINT 60 - /* eHRPWM2 TZ interrupt (PWM epwm_tz_intr_pend Subsystem) */ -#define AM335X_INT_eCAP2INT 61 - /* eCAP2 (PWM Subsystem) ecap_intr_intr_pend */ -#define AM335X_INT_GPIOINT3A 62 - /* GPIO 3 POINTRPEND1 */ -#define AM335X_INT_GPIOINT3B 63 - /* GPIO 3 POINTRPEND2 */ -#define AM335X_INT_MMCSD0INT 64 - /* MMCSD0 SINTERRUPTN */ -#define AM335X_INT_SPI0INT 65 - /* McSPI0 SINTERRUPTN */ -#define AM335X_INT_TINT0 66 - /* Timer0 POINTR_PEND */ -#define AM335X_INT_TINT1_1MS 67 - /* DMTIMER_1ms POINTR_PEND */ -#define AM335X_INT_TINT2 68 - /* DMTIMER2 POINTR_PEND */ -#define AM335X_INT_TINT3 69 - /* DMTIMER3 POINTR_PEND */ -#define AM335X_INT_I2C0INT 70 - /* I2C0 POINTRPEND */ -#define AM335X_INT_I2C1INT 71 - /* I2C1 POINTRPEND */ -#define AM335X_INT_UART0INT 72 - /* UART0 niq */ -#define AM335X_INT_UART1INT 73 - /* UART1 niq */ -#define AM335X_INT_UART2INT 74 - /* UART2 niq */ -#define AM335X_INT_RTCINT 75 - /* RTC timer_intr_pend */ -#define AM335X_INT_RTCALARMINT 76 - /* RTC alarm_intr_pend */ -#define AM335X_INT_MBINT0 77 - /* Mailbox0 (mail_u0_irq) initiator_sinterrupt_q_n */ -#define AM335X_INT_M3_TXEV 78 - /* Wake M3 Subsystem TXEV */ -#define AM335X_INT_eQEP0INT 79 - /* eQEP0 (PWM Subsystem) eqep_intr_intr_pend */ -#define AM335X_INT_MCATXINT0 80 - /* McASP0 mcasp_x_intr_pend */ -#define AM335X_INT_MCARXINT0 81 - /* McASP0 mcasp_r_intr_pend */ -#define AM335X_INT_MCATXINT1 82 - /* McASP1 mcasp_x_intr_pend */ -#define AM335X_INT_MCARXINT1 83 - /* McASP1 mcasp_r_intr_pend */ -#define AM335X_INT_ePWM0INT 86 - /* (PWM Subsystem) epwm_intr_intr_pend */ -#define AM335X_INT_ePWM1INT 87 - /* (PWM Subsystem) epwm_intr_intr_pend */ -#define AM335X_INT_eQEP1INT 88 - /* (PWM Subsystem) eqep_intr_intr_pend */ -#define AM335X_INT_eQEP2INT 89 - /* (PWM Subsystem) eqep_intr_intr_pend */ -#define AM335X_INT_DMA_INTR_PIN2 90 - /* External DMA/Interrupt Pin2 */ -#define AM335X_INT_WDT1INT 91 - /* (Public Watchdog) WDTIMER1 PO_INT_PEND */ -#define AM335X_INT_TINT4 92 - /* DMTIMER4 POINTR_PEN */ -#define AM335X_INT_TINT5 93 - /* DMTIMER5 POINTR_PEN */ -#define AM335X_INT_TINT6 94 - /* DMTIMER6 POINTR_PEND */ -#define AM335X_INT_TINT7 95 - /* DMTIMER7 POINTR_PEND */ -#define AM335X_INT_GPIOINT0A 96 - /* GPIO 0 POINTRPEND1 */ -#define AM335X_INT_GPIOINT0B 97 - /* GPIO 0 POINTRPEND2 */ -#define AM335X_INT_GPIOINT1A 98 - /* GPIO 1 POINTRPEND1 */ -#define AM335X_INT_GPIOINT1B 99 - /* GPIO 1 POINTRPEND2 */ -#define AM335X_INT_GPMCINT 100 - /* GPMC gpmc_sinterrupt */ -#define AM335X_INT_DDRERR0 101 - /* EMIF sys_err_intr_pend */ -#define AM335X_INT_TCERRINT0 112 - /* TPTC0 tptc_erint_pend_po */ -#define AM335X_INT_TCERRINT1 113 - /* TPTC1 tptc_erint_pend_po */ -#define AM335X_INT_TCERRINT2 114 - /* TPTC2 tptc_erint_pend_po */ -#define AM335X_INT_ADC_TSC_PENINT 115 - /* ADC_TSC pen_intr_pend */ -#define AM335X_INT_SMRFLX_Sabertooth 120 - /* Smart Reflex 0 intrpen */ -#define AM335X_INT_SMRFLX_Core 121 - /* Smart Reflex 1 intrpend */ -#define AM335X_INT_DMA_INTR_PIN0 123 - /* pi_x_dma_event_intr0 (xdma_event_intr0) */ -#define AM335X_INT_DMA_INTR_PIN1 124 - /* pi_x_dma_event_intr1 (xdma_event_intr1) */ -#define AM335X_INT_SPI1INT 125 - /* McSPI1 SINTERRUPTN */ - -#define OMAP3_AM335X_NR_IRQ_VECTORS 125 - -#define AM335X_DMTIMER0_BASE 0x44E05000 - /* DMTimer0 Registers */ -#define AM335X_DMTIMER1_1MS_BASE 0x44E31000 - /* DMTimer1 1ms Registers (Accurate 1ms timer) */ -#define AM335X_DMTIMER2_BASE 0x48040000 - /* DMTimer2 Registers */ -#define AM335X_DMTIMER3_BASE 0x48042000 - /* DMTimer3 Registers */ -#define AM335X_DMTIMER4_BASE 0x48044000 - /* DMTimer4 Registers */ -#define AM335X_DMTIMER5_BASE 0x48046000 - /* DMTimer5 Registers */ -#define AM335X_DMTIMER6_BASE 0x48048000 - /* DMTimer6 Registers */ -#define AM335X_DMTIMER7_BASE 0x4804A000 - /* DMTimer7 Registers */ - -/* General-purpose timer registers - AM335x non 1MS timers have different offsets */ -#define AM335X_TIMER_TIDR 0x000 - /* IP revision code */ -#define AM335X_TIMER_TIOCP_CFG 0x010 - /* Controls params for GP timer L4 interface */ -#define AM335X_TIMER_IRQSTATUS_RAW 0x024 - /* Timer IRQSTATUS Raw Register */ -#define AM335X_TIMER_IRQSTATUS 0x028 - /* Timer IRQSTATUS Register */ -#define AM335X_TIMER_IRQENABLE_SET 0x02C - /* Timer IRQENABLE Set Register */ -#define AM335X_TIMER_IRQENABLE_CLR 0x030 - /* Timer IRQENABLE Clear Register */ -#define AM335X_TIMER_IRQWAKEEN 0x034 - /* Timer IRQ Wakeup Enable Register */ -#define AM335X_TIMER_TCLR 0x038 - /* Controls optional features */ -#define AM335X_TIMER_TCRR 0x03C - /* Internal counter value */ -#define AM335X_TIMER_TLDR 0x040 - /* Timer load value */ -#define AM335X_TIMER_TTGR 0x044 - /* Triggers counter reload */ -#define AM335X_TIMER_TWPS 0x048 - /* Indicates if Write-Posted pending */ -#define AM335X_TIMER_TMAR 0x04C - /* Value to be compared with counter */ -#define AM335X_TIMER_TCAR1 0x050 - /* First captured value of counter register */ -#define AM335X_TIMER_TSICR 0x054 - /* Control posted mode and functional SW reset */ -#define AM335X_TIMER_TCAR2 0x058 - /* Second captured value of counter register */ -#define AM335X_WDT_BASE 0x44E35000 - /* Watchdog timer */ -#define AM335X_WDT_WWPS 0x34 - /* Command posted status */ -#define AM335X_WDT_WSPR 0x48 - /* Activate/deactivate sequence */ - -/* RTC registers */ -#define AM335X_RTC_BASE 0x44E3E000 -#define AM335X_RTC_SECS 0x0 -#define AM335X_RTC_MINS 0x4 -#define AM335X_RTC_HOURS 0x8 -#define AM335X_RTC_DAYS 0xc -#define AM335X_RTC_MONTHS 0x10 -#define AM335X_RTC_YEARS 0x14 -#define AM335X_RTC_WEEKS 0x18 -#define AM335X_RTC_CTRL_REG 0x40 -#define AM335X_RTC_STATUS_REG 0x44 -#define AM335X_RTC_REV_REG 0x74 -#define AM335X_RTC_SYSCONFIG 0x78 -#define AM335X_RTC_KICK0 0x6c -#define AM335X_RTC_KICK1 0x70 -#define AM335X_RTC_OSC_CLOCK 0x54 - -#define AM335X_RTC_KICK0_KEY 0x83E70B13 -#define AM335X_RTC_KICK1_KEY 0x95A4F1E0 - -/* GPIO memory-mapped registers */ - -#define AM335X_GPIO0_BASE 0x44E07000 - /* GPIO Bank 0 base Register */ -#define AM335X_GPIO1_BASE 0x4804C000 - /* GPIO Bank 1 base Register */ -#define AM335X_GPIO2_BASE 0x481AC000 - /* GPIO Bank 2 base Register */ -#define AM335X_GPIO3_BASE 0x481AE000 - /* GPIO Bank 3 base Register */ - -#define AM335X_GPIO_REVISION 0x00 -#define AM335X_GPIO_SYSCONFIG 0x10 -#define AM335X_GPIO_EOI 0x20 -#define AM335X_GPIO_IRQSTATUS_RAW_0 0x24 -#define AM335X_GPIO_IRQSTATUS_RAW_1 0x28 -#define AM335X_GPIO_IRQSTATUS_0 0x2C -#define AM335X_GPIO_IRQSTATUS_1 0x30 -#define AM335X_GPIO_IRQSTATUS_SET_0 0x34 -#define AM335X_GPIO_IRQSTATUS_SET_1 0x38 -#define AM335X_GPIO_IRQSTATUS_CLR_0 0x3C -#define AM335X_GPIO_IRQSTATUS_CLR_1 0x40 -#define AM335X_GPIO_IRQWAKEN_0 0x44 -#define AM335X_GPIO_IRQWAKEN_1 0x48 -#define AM335X_GPIO_SYSSTATUS 0x114 -#define AM335X_GPIO_CTRL 0x130 -#define AM335X_GPIO_OE 0x134 -#define AM335X_GPIO_DATAIN 0x138 -#define AM335X_GPIO_DATAOUT 0x13C -#define AM335X_GPIO_LEVELDETECT0 0x140 -#define AM335X_GPIO_LEVELDETECT1 0x144 -#define AM335X_GPIO_RISINGDETECT 0x148 -#define AM335X_GPIO_FALLINGDETECT 0x14C -#define AM335X_GPIO_DEBOUNCENABLE 0x150 -#define AM335X_GPIO_DEBOUNCINGTIME 0x154 -#define AM335X_GPIO_CLEARDATAOUT 0x190 -#define AM335X_GPIO_SETDATAOUT 0x194 - -/* AM335X Pad Configuration Register Base */ -#define AM335X_PADCONF_BASE 0x44E10000 - -/* Memory mapped register offset for Control Module */ -#define AM335X_CONF_GPMC_AD0 0x800 -#define AM335X_CONF_GPMC_AD1 0x804 -#define AM335X_CONF_GPMC_AD2 0x808 -#define AM335X_CONF_GPMC_AD3 0x80C -#define AM335X_CONF_GPMC_AD4 0x810 -#define AM335X_CONF_GPMC_AD5 0x814 -#define AM335X_CONF_GPMC_AD6 0x818 -#define AM335X_CONF_GPMC_AD7 0x81C -#define AM335X_CONF_GPMC_AD8 0x820 -#define AM335X_CONF_GPMC_AD9 0x824 -#define AM335X_CONF_GPMC_AD10 0x828 -#define AM335X_CONF_GPMC_AD11 0x82C -#define AM335X_CONF_GPMC_AD12 0x830 -#define AM335X_CONF_GPMC_AD13 0x834 -#define AM335X_CONF_GPMC_AD14 0x838 -#define AM335X_CONF_GPMC_AD15 0x83C -#define AM335X_CONF_GPMC_A0 0x840 -#define AM335X_CONF_GPMC_A1 0x844 -#define AM335X_CONF_GPMC_A2 0x848 -#define AM335X_CONF_GPMC_A3 0x84C -#define AM335X_CONF_GPMC_A4 0x850 -#define AM335X_CONF_GPMC_A5 0x854 -#define AM335X_CONF_GPMC_A6 0x858 -#define AM335X_CONF_GPMC_A7 0x85C -#define AM335X_CONF_GPMC_A8 0x860 -#define AM335X_CONF_GPMC_A9 0x864 -#define AM335X_CONF_GPMC_A10 0x868 -#define AM335X_CONF_GPMC_A11 0x86C -#define AM335X_CONF_GPMC_WAIT0 0x870 -#define AM335X_CONF_GPMC_WPN 0x874 -#define AM335X_CONF_GPMC_BEN1 0x878 -#define AM335X_CONF_GPMC_CSN0 0x87C -#define AM335X_CONF_GPMC_CSN1 0x880 -#define AM335X_CONF_GPMC_CSN2 0x884 -#define AM335X_CONF_GPMC_CSN3 0x888 -#define AM335X_CONF_GPMC_CLK 0x88C -#define AM335X_CONF_GPMC_ADVN_ALE 0x890 -#define AM335X_CONF_GPMC_OEN_REN 0x894 -#define AM335X_CONF_GPMC_WEN 0x898 -#define AM335X_CONF_GPMC_BEN0_CLE 0x89C -#define AM335X_CONF_LCD_DATA0 0x8A0 -#define AM335X_CONF_LCD_DATA1 0x8A4 -#define AM335X_CONF_LCD_DATA2 0x8A8 -#define AM335X_CONF_LCD_DATA3 0x8AC -#define AM335X_CONF_LCD_DATA4 0x8B0 -#define AM335X_CONF_LCD_DATA5 0x8B4 -#define AM335X_CONF_LCD_DATA6 0x8B8 -#define AM335X_CONF_LCD_DATA7 0x8BC -#define AM335X_CONF_LCD_DATA8 0x8C0 -#define AM335X_CONF_LCD_DATA9 0x8C4 -#define AM335X_CONF_LCD_DATA10 0x8C8 -#define AM335X_CONF_LCD_DATA11 0x8CC -#define AM335X_CONF_LCD_DATA12 0x8D0 -#define AM335X_CONF_LCD_DATA13 0x8D4 -#define AM335X_CONF_LCD_DATA14 0x8D8 -#define AM335X_CONF_LCD_DATA15 0x8DC -#define AM335X_CONF_LCD_VSYNC 0x8E0 -#define AM335X_CONF_LCD_HSYNC 0x8E4 -#define AM335X_CONF_LCD_PCLK 0x8E8 -#define AM335X_CONF_LCD_AC_BIAS_EN 0x8EC -#define AM335X_CONF_MMC0_DAT3 0x8F0 -#define AM335X_CONF_MMC0_DAT2 0x8F4 -#define AM335X_CONF_MMC0_DAT1 0x8F8 -#define AM335X_CONF_MMC0_DAT0 0x8FC -#define AM335X_CONF_MMC0_CLK 0x900 -#define AM335X_CONF_MMC0_CMD 0x904 -#define AM335X_CONF_MII1_COL 0x908 -#define AM335X_CONF_MII1_CRS 0x90C -#define AM335X_CONF_MII1_RX_ER 0x910 -#define AM335X_CONF_MII1_TX_EN 0x914 -#define AM335X_CONF_MII1_RX_DV 0x918 -#define AM335X_CONF_MII1_TXD3 0x91C -#define AM335X_CONF_MII1_TXD2 0x920 -#define AM335X_CONF_MII1_TXD1 0x924 -#define AM335X_CONF_MII1_TXD0 0x928 -#define AM335X_CONF_MII1_TX_CLK 0x92C -#define AM335X_CONF_MII1_RX_CLK 0x930 -#define AM335X_CONF_MII1_RXD3 0x934 -#define AM335X_CONF_MII1_RXD2 0x938 -#define AM335X_CONF_MII1_RXD1 0x93C -#define AM335X_CONF_MII1_RXD0 0x940 -#define AM335X_CONF_RMII1_REF_CLK 0x944 -#define AM335X_CONF_MDIO 0x948 -#define AM335X_CONF_MDC 0x94C -#define AM335X_CONF_SPI0_SCLK 0x950 -#define AM335X_CONF_SPI0_D0 0x954 -#define AM335X_CONF_SPI0_D1 0x958 -#define AM335X_CONF_SPI0_CS0 0x95C -#define AM335X_CONF_SPI0_CS1 0x960 -#define AM335X_CONF_ECAP0_IN_PWM0_OUT 0x964 -#define AM335X_CONF_UART0_CTSN 0x968 -#define AM335X_CONF_UART0_RTSN 0x96C -#define AM335X_CONF_UART0_RXD 0x970 -#define AM335X_CONF_UART0_TXD 0x974 -#define AM335X_CONF_UART1_CTSN 0x978 -#define AM335X_CONF_UART1_RTSN 0x97C -#define AM335X_CONF_UART1_RXD 0x980 -#define AM335X_CONF_UART1_TXD 0x984 -#define AM335X_CONF_I2C0_SDA 0x988 -#define AM335X_CONF_I2C0_SCL 0x98C -#define AM335X_CONF_MCASP0_ACLKX 0x990 -#define AM335X_CONF_MCASP0_FSX 0x994 -#define AM335X_CONF_MCASP0_AXR0 0x998 -#define AM335X_CONF_MCASP0_AHCLKR 0x99C -#define AM335X_CONF_MCASP0_ACLKR 0x9A0 -#define AM335X_CONF_MCASP0_FSR 0x9A4 -#define AM335X_CONF_MCASP0_AXR1 0x9A8 -#define AM335X_CONF_MCASP0_AHCLKX 0x9AC -#define AM335X_CONF_XDMA_EVENT_INTR0 0x9B0 -#define AM335X_CONF_XDMA_EVENT_INTR1 0x9B4 -#define AM335X_CONF_WARMRSTN 0x9B8 -#define AM335X_CONF_NNMI 0x9C0 -#define AM335X_CONF_TMS 0x9D0 -#define AM335X_CONF_TDI 0x9D4 -#define AM335X_CONF_TDO 0x9D8 -#define AM335X_CONF_TCK 0x9DC -#define AM335X_CONF_TRSTN 0x9E0 -#define AM335X_CONF_EMU0 0x9E4 -#define AM335X_CONF_EMU1 0x9E8 -#define AM335X_CONF_RTC_PWRONRSTN 0x9F8 -#define AM335X_CONF_PMIC_POWER_EN 0x9FC -#define AM335X_CONF_EXT_WAKEUP 0xA00 -#define AM335X_CONF_RTC_KALDO_ENN 0xA04 -#define AM335X_CONF_USB0_DRVVBUS 0xA1C -#define AM335X_CONF_USB1_DRVVBUS 0xA34 - -/* Registers for PWM Subsystem */ -#define AM335X_PWMSS_CTRL (0x664) -#define AM335X_CM_PER_EPWMSS0_CLKCTRL (0xD4) -#define AM335X_CM_PER_EPWMSS1_CLKCTRL (0xCC) -#define AM335X_CM_PER_EPWMSS2_CLKCTRL (0xD8) -#define AM335X_CONTROL_MODULE (0x44e10000) -#define AM335X_CM_PER_ADDR (0x44e00000) -#define AM335X_PWMSS_CLKSTATUS (0xC) -#define AM335X_PWMSS0_MMAP_ADDR 0x48300000 -#define AM335X_PWMSS1_MMAP_ADDR 0x48302000 -#define AM335X_PWMSS2_MMAP_ADDR 0x48304000 -#define AM335X_PWMSS_MMAP_LEN 0x1000 -#define AM335X_PWMSS_IDVER 0x0 -#define AM335X_PWMSS_SYSCONFIG 0x4 -#define AM335X_PWMSS_CLKCONFIG 0x8 -#define AM335X_PWMSS_CLK_EN_ACK 0x100 -#define AM335X_EPWM_TBCTL 0x0 -#define AM335X_EPWM_TBSTS 0x2 -#define AM335X_EPWM_TBPHSHR 0x4 -#define AM335X_EPWM_TBPHS 0x6 -#define AM335X_EPWM_TBCNT 0x8 -#define AM335X_EPWM_TBPRD 0xA -#define AM335X_EPWM_CMPCTL 0xE -#define AM335X_EPWM_CMPAHR 0x10 -#define AM335X_EPWM_CMPA 0x12 -#define AM335X_EPWM_CMPB 0x14 -#define AM335X_EPWM_AQCTLA 0x16 -#define AM335X_EPWM_AQCTLB 0x18 -#define AM335X_EPWM_AQSFRC 0x1A -#define AM335X_EPWM_AQCSFRC 0x1C -#define AM335X_EPWM_DBCTL 0x1E -#define AM335X_EPWM_DBRED 0x20 -#define AM335X_EPWM_DBFED 0x22 -#define AM335X_TBCTL_CTRMODE_UP 0x0 -#define AM335X_TBCTL_CTRMODE_DOWN 0x1 -#define AM335X_TBCTL_CTRMODE_UPDOWN 0x2 -#define AM335X_TBCTL_CTRMODE_FREEZE 0x3 -#define AM335X_EPWM_AQCTLA_ZRO_XALOW (0x0001u) -#define AM335X_EPWM_AQCTLA_ZRO_XAHIGH (0x0002u) -#define AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE (0x0003u) -#define AM335X_EPWM_AQCTLA_CAU_SHIFT (0x0004u) -#define AM335X_EPWM_AQCTLA_ZRO_XBLOW (0x0001u) -#define AM335X_EPWM_AQCTLB_ZRO_XBHIGH (0x0002u) -#define AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE (0x0003u) -#define AM335X_EPWM_AQCTLB_CBU_SHIFT (0x0008u) -#define AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE (0x0003u) -#define AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN (0x00000001u) -#define AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN (0x00000002u) -#define AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN (0x00000004u) -#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE (0x2u) -#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE (0x2u) -#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE (0x2u) -#define AM335X_TBCTL_CLKDIV_MASK (3 << 10) -#define AM335X_TBCTL_HSPCLKDIV_MASK (3 << 7) -#define AM335X_EPWM_TBCTL_CLKDIV (0x1C00u) -#define AM335X_EPWM_TBCTL_CLKDIV_SHIFT (0x000Au) -#define AM335X_EPWM_TBCTL_HSPCLKDIV (0x0380u) -#define AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT (0x0007u) -#define AM335X_EPWM_TBCTL_PRDLD (0x0008u) -#define AM335X_EPWM_PRD_LOAD_SHADOW_MASK AM335X_EPWM_TBCTL_PRDLD -#define AM335X_EPWM_SHADOW_WRITE_ENABLE 0x0 -#define AM335X_EPWM_SHADOW_WRITE_DISABLE 0x1 -#define AM335X_EPWM_TBCTL_PRDLD_SHIFT (0x0003u) -#define AM335X_EPWM_TBCTL_CTRMODE (0x0003u) -#define AM335X_EPWM_COUNTER_MODE_MASK AM335X_EPWM_TBCTL_CTRMODE -#define AM335X_TBCTL_FREERUN (2 << 14) -#define AM335X_TBCTL_CTRMODE_SHIFT (0x0000u) -#define AM335X_EPWM_COUNT_UP (AM335X_TBCTL_CTRMODE_UP << \ - AM335X_TBCTL_CTRMODE_SHIFT) - -#define AM335X_EPWM_REGS (0x00000200) -#define AM335X_EPWM_0_REGS (AM335X_PWMSS0_MMAP_ADDR + AM335X_EPWM_REGS) -#define AM335X_EPWM_1_REGS (AM335X_PWMSS1_MMAP_ADDR + AM335X_EPWM_REGS) -#define AM335X_EPWM_2_REGS (AM335X_PWMSS2_MMAP_ADDR + AM335X_EPWM_REGS) - -#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE (0x00000003u) -#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC (0x0u) -#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT (0x00000010u) -#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST (0x00030000u) - -#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE (0x00000003u) -#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST (0x00030000u) -#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC (0x0u) -#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT (0x00000010u) - -#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE (0x00000003u) -#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC (0x0u) -#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT (0x00000010u) -#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST (0x00030000u) - - - -/* I2C registers */ -#define AM335X_I2C0_BASE 0x44e0b000 - /* I2C0 base address */ -#define AM335X_I2C1_BASE 0x4802a000 - /* I2C1 base address */ -#define AM335X_I2C2_BASE 0x4819c000 - /* I2C2 base address */ -#define AM335X_I2C_REVNB_LO 0x00 - /* Module Revision Register (low bytes) */ -#define AM335X_I2C_REVNB_HI 0x04 - /* Module Revision Register (high bytes) */ -#define AM335X_I2C_SYSC 0x10 - /* System Configuration Register */ -#define AM335X_I2C_IRQSTATUS_RAW 0x24 - /* I2C Status Raw Register */ -#define AM335X_I2C_IRQSTATUS 0x28 - /* I2C Status Register */ -#define AM335X_I2C_IRQENABLE_SET 0x2c - /* I2C Interrupt Enable Set Register */ -#define AM335X_I2C_IRQENABLE_CLR 0x30 - /* I2C Interrupt Enable Clear Register */ -#define AM335X_I2C_WE 0x34 - /* I2C Wakeup Enable Register */ -#define AM335X_I2C_DMARXENABLE_SET 0x38 - /* Receive DMA Enable Set Register */ -#define AM335X_I2C_DMATXENABLE_SET 0x3c - /* Transmit DMA Enable Set Register */ -#define AM335X_I2C_DMARXENABLE_CLR 0x40 - /* Receive DMA Enable Clear Register */ -#define AM335X_I2C_DMATXENABLE_CLR 0x44 - /* Transmit DMA Enable Clear Register */ -#define AM335X_I2C_DMARXWAKE_EN 0x48 - /* Receive DMA Wakeup Register */ -#define AM335X_I2C_DMATXWAKE_EN 0x4c - /* Transmit DMA Wakeup Register */ -#define AM335X_I2C_SYSS 0x90 - /* System Status Register */ -#define AM335X_I2C_BUF 0x94 - /* Buffer Configuration Register */ -#define AM335X_I2C_CNT 0x98 - /* Data Counter Register */ -#define AM335X_I2C_DATA 0x9c - /* Data Access Register */ -#define AM335X_I2C_CON 0xa4 - /* I2C Configuration Register */ -#define AM335X_I2C_OA 0xa8 - /* I2C Own Address Register */ -#define AM335X_I2C_SA 0xac - /* I2C Slave Address Register */ -#define AM335X_I2C_PSC 0xb0 - /* I2C Clock Prescaler Register */ -#define AM335X_I2C_SCLL 0xb4 - /* I2C SCL Low Time Register */ -#define AM335X_I2C_SCLH 0xb8 - /* I2C SCL High Time Register */ -#define AM335X_I2C_SYSTEST 0xbc - /* System Test Register */ -#define AM335X_I2C_BUFSTAT 0xc0 - /* I2C Buffer Status Register */ -#define AM335X_I2C_OA1 0xc4 - /* I2C Own Address 1 Register */ -#define AM335X_I2C_OA2 0xc8 - /* I2C Own Address 2 Register */ -#define AM335X_I2C_OA3 0xcc - /* I2C Own Address 3 Register */ -#define AM335X_I2C_ACTOA 0xd0 - /* Active Own Address Register */ -#define AM335X_I2C_SBLOCK 0xd4 - /* I2C Clock Blocking Enable Register */ - -#define AM335X_CM_PER_L4LS_CLKSTCTRL (0x0) -#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u) -#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL (0x00000003u) -#define AM335X_CM_PER_L4LS_CLKCTRL (0x60) -#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE (0x2u) -#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE (0x00000003u) -#define AM335X_CM_PER_I2C1_CLKCTRL (0x48) -#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE_ENABLE (0x2u) -#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE (0x00000003u) -#define AM335X_CM_PER_I2C2_CLKCTRL (0x44) -#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE_ENABLE (0x2u) -#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE (0x00000003u) -#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u) -#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK (0x01000000u) -#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE (0x00000003u) -#define AM335X_I2C_CON_XSA (0x00000100u) -#define AM335X_I2C_CFG_10BIT_SLAVE_ADDR AM335X_I2C_CON_XSA -#define AM335X_I2C_CON_XSA_SHIFT (0x00000008u) -#define AM335X_I2C_CFG_7BIT_SLAVE_ADDR (0 << AM335X_I2C_CON_XSA_SHIFT) -#define AM335X_I2C_CON_I2C_EN (0x00008000u) -#define AM335X_I2C_CON_TRX (0x00000200u) -#define AM335X_I2C_CON_MST (0x00000400u) -#define AM335X_I2C_CON_STB (0x00000800u) -#define AM335X_I2C_SYSC_AUTOIDLE (0x00000001u) - -/*I2C0 module clock registers*/ - -#define AM335X_CM_WKUP_CONTROL_CLKCTRL (0x4) -#define AM335X_CM_WKUP_CLKSTCTRL (0x0) -#define AM335X_CM_WKUP_I2C0_CLKCTRL (0xb8) -#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE_ENABLE (0x2u) -#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE (0x00000003u) -#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC (0x0u) -#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT (0x00000010u) -#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST (0x00030000u) -#define AM335X_CM_WKUP_CLKSTCTRL_CLKACTIVITY_I2C0_GFCLK (0x00000800u) -#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_FUNC (0x0u) -#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_SHIFT (0x00000010u) -#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST (0x00030000u) -#define AM335X_SOC_CM_WKUP_REGS (AM335X_CM_PER_ADDR + 0x400) - -/* I2C status Register */ -#define AM335X_I2C_IRQSTATUS_NACK (1 << 1) -#define AM335X_I2C_IRQSTATUS_ROVR (1 << 11) -#define AM335X_I2C_IRQSTATUS_AL (1<<0) -#define AM335X_I2C_IRQSTATUS_ARDY (1 << 2) -#define AM335X_I2C_IRQSTATUS_RRDY (1 << 3) -#define AM335X_I2C_IRQSTATUS_XRDY (1 << 4) -#define AM335X_I2C_IRQSTATUS_XUDF (1 << 10) -#define AM335X_I2C_BUF_TXFIFO_CLR (0x00000040u) -#define AM335X_I2C_BUF_RXFIFO_CLR (0x00004000u) -#define AM335X_I2C_IRQSTATUS_AAS (1 << 9) -#define AM335X_I2C_IRQSTATUS_BF (1 << 8) -#define AM335X_I2C_IRQSTATUS_STC (1 << 6) -#define AM335X_I2C_IRQSTATUS_GC (1 << 5) -#define AM335X_I2C_IRQSTATUS_XDR (1 << 14) -#define AM335X_I2C_IRQSTATUS_RDR (1 << 13) - -#define AM335X_I2C_INT_RECV_READY AM335X_I2C_IRQSTATUS_RRDY -#define AM335X_I2C_CON_STOP (0x00000002u) -#define AM335X_I2C_CON_START (0x00000001u) -#define AM335X_I2C_CFG_MST_RX AM335X_I2C_CON_MST -#define AM335X_I2C_CFG_MST_TX (AM335X_I2C_CON_TRX | AM335X_I2C_CON_MST) -#define AM335X_I2C_IRQSTATUS_RAW_BB (0x00001000u) -#define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x00000020u) -#define AM335X_I2C_INT_STOP_CONDITION AM335X_I2C_IRQSTATUS_BF - -#endif diff --git a/c/src/lib/libcpu/arm/shared/include/mmu.h b/c/src/lib/libcpu/arm/shared/include/mmu.h deleted file mode 100644 index b82e838695..0000000000 --- a/c/src/lib/libcpu/arm/shared/include/mmu.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * ARM MMU header file - */ - -/* - * Copyright (c) 2004 by Cogent Computer Systems - * Written by Jay Monkman <jtm@lopingdog.com> - */ - -#ifndef __LIBCPU_MMU_H__ -#define __LIBCPU_MMU_H__ - -#include <stdint.h> - -#define MMU_SECT_SIZE 0x100000 - -#define MMU_CACHE_NONE 0x0 -#define MMU_CACHE_BUFFERED 0x1 -#define MMU_CACHE_WTHROUGH 0x2 -#define MMU_CACHE_WBACK 0x3 - -typedef struct { - uint32_t paddr; - uint32_t vaddr; - uint32_t size; /* in MB */ - uint8_t cache_flags; -} mmu_sect_map_t; - -void mmu_init(mmu_sect_map_t *map); -void mmu_set_cpu_async_mode(void); - -#endif /* __MMU_H__ */ diff --git a/c/src/lib/libcpu/arm/shared/include/omap3.h b/c/src/lib/libcpu/arm/shared/include/omap3.h deleted file mode 100644 index 0cc43d6383..0000000000 --- a/c/src/lib/libcpu/arm/shared/include/omap3.h +++ /dev/null @@ -1,384 +0,0 @@ -/* - * Copyright (c) 2012 Claas Ziemke. All rights reserved. - * - * Claas Ziemke - * Kernerstrasse 11 - * 70182 Stuttgart - * Germany - * <claas.ziemke@gmx.net> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified by Ben Gras <beng@shrike-systems.com> to add lots - * of beagleboard/beaglebone definitions, delete lpc32xx specific - * ones, and merge with some other header files. - */ - -/* Interrupt controller memory map */ -#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */ - -/* Interrupt controller memory map */ -#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */ - -/* Interrupt controller registers */ -#define OMAP3_INTCPS_REVISION 0x000 /* IP revision code */ -#define OMAP3_INTCPS_SYSCONFIG 0x010 /* Controls params */ -#define OMAP3_INTCPS_SYSSTATUS 0x014 /* Status */ -#define OMAP3_INTCPS_SIR_IRQ 0x040 /* Active IRQ number */ -#define OMAP3_INTCPS_SIR_FIQ 0x044 /* Active FIQ number */ -#define OMAP3_INTCPS_CONTROL 0x048 /* New int agreement bits */ -#define OMAP3_INTCPS_PROTECTION 0x04C /* Protection for other regs */ -#define OMAP3_INTCPS_IDLE 0x050 /* Clock auto-idle/gating */ -#define OMAP3_INTCPS_IRQ_PRIORITY 0x060 /* Active IRQ priority level */ -#define OMAP3_INTCPS_FIQ_PRIORITY 0x064 /* Active FIQ priority level */ -#define OMAP3_INTCPS_THRESHOLD 0x068 /* Priority threshold */ -#define OMAP3_INTCPS_ITR0 0x080 /* Raw pre-masking interrupt status */ -#define OMAP3_INTCPS_MIR0 0x084 /* Interrupt mask */ -#define OMAP3_INTCPS_MIR1 0x0A4 /* Interrupt mask */ -#define OMAP3_INTCPS_MIR2 0x0C4 /* Interrupt mask */ -#define OMAP3_INTCPS_MIR3 0x0E4 /* Interrupt mask */ -#define OMAP3_INTCPS_MIR_CLEAR0 0x088 /* Clear interrupt mask bits */ -#define OMAP3_INTCPS_MIR_SET0 0x08C /* Set interrupt mask bits */ -#define OMAP3_INTCPS_ISR_SET0 0x090 /* Set software int bits */ -#define OMAP3_INTCPS_ISR_CLEAR0 0x094 /* Clear software int bits */ -#define OMAP3_INTCPS_PENDING_IRQ0 0x098 /* IRQ status post-masking */ -#define OMAP3_INTCPS_PENDING_IRQ1 0x0b8 /* IRQ status post-masking */ -#define OMAP3_INTCPS_PENDING_IRQ2 0x0d8 /* IRQ status post-masking */ -#define OMAP3_INTCPS_PENDING_IRQ3 0x0f8 /* IRQ status post-masking */ -#define OMAP3_INTCPS_PENDING_FIQ0 0x09C /* FIQ status post-masking */ -#define OMAP3_INTCPS_ILR0 0x100 /* Priority for interrupts */ - -/* SYSCONFIG */ -#define OMAP3_SYSCONFIG_AUTOIDLE 0x01 /* SYSCONFIG.AUTOIDLE bit */ - -#define OMAP3_INTR_ITR(base,n) \ - (base + OMAP3_INTCPS_ITR0 + 0x20 * (n)) -#define OMAP3_INTR_MIR(base,n) \ - (base + OMAP3_INTCPS_MIR0 + 0x20 * (n)) -#define OMAP3_INTR_MIR_CLEAR(base,n) \ - (base + OMAP3_INTCPS_MIR_CLEAR0 + 0x20 * (n)) -#define OMAP3_INTR_MIR_SET(base,n) \ - (base + OMAP3_INTCPS_MIR_SET0 + 0x20 * (n)) -#define OMAP3_INTR_ISR_SET(base,n) \ - (base + OMAP3_INTCPS_ISR_SET0 + 0x20 * (n)) -#define OMAP3_INTR_ISR_CLEAR(base,n) \ - (base + OMAP3_INTCPS_ISR_CLEAR0 + 0x20 * (n)) -#define OMAP3_INTR_PENDING_IRQ(base,n) \ - (base + OMAP3_INTCPS_PENDING_IRQ0 + 0x20 * (n)) -#define OMAP3_INTR_PENDING_FIQ(base,n) \ - (base + OMAP3_INTCPS_PENDING_FIQ0 + 0x20 * (n)) -#define OMAP3_INTR_ILR(base,m) \ - (base + OMAP3_INTCPS_ILR0 + 0x4 * (m)) - -#define OMAP3_INTR_SPURIOUSIRQ_MASK (0x1FFFFFF << 7) /* Spurious IRQ mask for SIR_IRQ */ -#define OMAP3_INTR_ACTIVEIRQ_MASK 0x7F /* Active IRQ mask for SIR_IRQ */ -#define OMAP3_INTR_NEWIRQAGR 0x1 /* New IRQ Generation */ - -#define OMAP3_DM337X_NR_IRQ_VECTORS 96 - -/* Interrupt mappings */ -#define OMAP3_MCBSP2_ST_IRQ 4 /* Sidestone McBSP2 overflow */ -#define OMAP3_MCBSP3_ST_IRQ 5 /* Sidestone McBSP3 overflow */ -#define OMAP3_SYS_NIRQ 7 /* External source (active low) */ -#define OMAP3_SMX_DBG_IRQ 9 /* L3 interconnect error for debug */ -#define OMAP3_SMX_APP_IRQ 10 /* L3 interconnect error for application */ -#define OMAP3_PRCM_IRQ 11 /* PRCM module */ -#define OMAP3_SDMA0_IRQ 12 /* System DMA request 0 */ -#define OMAP3_SDMA1_IRQ 13 /* System DMA request 1 */ -#define OMAP3_SDMA2_IRQ 14 /* System DMA request 2 */ -#define OMAP3_SDMA3_IRQ 15 /* System DMA request 3 */ -#define OMAP3_MCBSP1_IRQ 16 /* McBSP module 1 */ -#define OMAP3_MCBSP2_IRQ 17 /* McBSP module 2 */ -#define OMAP3_GPMC_IRQ 20 /* General-purpose memory controller */ -#define OMAP3_SGX_IRQ 21 /* 2D/3D graphics module */ -#define OMAP3_MCBSP3_IRQ 22 /* McBSP module 3 */ -#define OMAP3_MCBSP4_IRQ 23 /* McBSP module 4 */ -#define OMAP3_CAM0_IRQ 24 /* Camera interface request 0 */ -#define OMAP3_DSS_IRQ 25 /* Display subsystem module */ -#define OMAP3_MAIL_U0_IRQ 26 /* Mailbox user 0 request */ -#define OMAP3_MCBSP5_IRQ 27 /* McBSP module 5 */ -#define OMAP3_IVA2_MMU_IRQ 28 /* IVA2 MMU */ -#define OMAP3_GPIO1_IRQ 29 /* GPIO module 1 */ -#define OMAP3_GPIO2_IRQ 30 /* GPIO module 2 */ -#define OMAP3_GPIO3_IRQ 31 /* GPIO module 3 */ -#define OMAP3_GPIO4_IRQ 32 /* GPIO module 4 */ -#define OMAP3_GPIO5_IRQ 33 /* GPIO module 5 */ -#define OMAP3_GPIO6_IRQ 34 /* GPIO module 6 */ -#define OMAP3_WDT3_IRQ 36 /* Watchdog timer module 3 overflow */ -#define OMAP3_GPT1_IRQ 37 /* General-purpose timer module 1 */ -#define OMAP3_GPT2_IRQ 38 /* General-purpose timer module 2 */ -#define OMAP3_GPT3_IRQ 39 /* General-purpose timer module 3 */ -#define OMAP3_GPT4_IRQ 40 /* General-purpose timer module 4 */ -#define OMAP3_GPT5_IRQ 41 /* General-purpose timer module 5 */ -#define OMAP3_GPT6_IRQ 42 /* General-purpose timer module 6 */ -#define OMAP3_GPT7_IRQ 43 /* General-purpose timer module 7 */ -#define OMAP3_GPT8_IRQ 44 /* General-purpose timer module 8 */ -#define OMAP3_GPT9_IRQ 45 /* General-purpose timer module 9 */ -#define OMAP3_GPT10_IRQ 46 /* General-purpose timer module 10 */ -#define OMAP3_GPT11_IRQ 47 /* General-purpose timer module 11 */ -#define OMAP3_SPI4_IRQ 48 /* McSPI module 4 */ -#define OMAP3_MCBSP4_TX_IRQ 54 /* McBSP module 4 transmit */ -#define OMAP3_MCBSP4_RX_IRQ 55 /* McBSP module 4 receive */ -#define OMAP3_I2C1_IRQ 56 /* I2C module 1 */ -#define OMAP3_I2C2_IRQ 57 /* I2C module 2 */ -#define OMAP3_HDQ_IRQ 58 /* HDQ/1-Wire */ -#define OMAP3_MCBSP1_TX_IRQ 59 /* McBSP module 1 transmit */ -#define OMAP3_MCBSP1_RX_IRQ 60 /* McBSP module 1 receive */ -#define OMAP3_I2C3_IRQ 61 /* I2C module 3 */ -#define OMAP3_MCBSP2_TX_IRQ 62 /* McBSP module 2 transmit */ -#define OMAP3_MCBSP2_RX_IRQ 63 /* McBSP module 2 receive */ -#define OMAP3_SPI1_IRQ 65 /* McSPI module 1 */ -#define OMAP3_SPI2_IRQ 66 /* McSPI module 2 */ -#define OMAP3_UART1_IRQ 72 /* UART module 1 */ -#define OMAP3_UART2_IRQ 73 /* UART module 2 */ -#define OMAP3_UART3_IRQ 74 /* UART module 3 */ -#define OMAP3_PBIAS_IRQ 75 /* Merged interrupt for PBIASlite 1/2 */ -#define OMAP3_OHCI_IRQ 76 /* OHCI HSUSB MP Host Interrupt */ -#define OMAP3_EHCI_IRQ 77 /* EHCI HSUSB MP Host Interrupt */ -#define OMAP3_TLL_IRQ 78 /* HSUSB MP TLL Interrupt */ -#define OMAP3_MCBSP5_TX_IRQ 81 /* McBSP module 5 transmit */ -#define OMAP3_MCBSP5_RX_IRQ 82 /* McBSP module 5 receive */ -#define OMAP3_MMC1_IRQ 83 /* MMC/SD module 1 */ -#define OMAP3_MMC2_IRQ 86 /* MMC/SD module 2 */ -#define OMAP3_ICR_IRQ 87 /* MPU ICR */ -#define OMAP3_D2DFRINT_IRQ 88 /* 3G coproc (in stacked modem config) */ -#define OMAP3_MCBSP3_TX_IRQ 89 /* McBSP module 3 transmit */ -#define OMAP3_MCBSP3_RX_IRQ 90 /* McBSP module 3 receive */ -#define OMAP3_SPI3_IRQ 91 /* McSPI module 3 */ -#define OMAP3_HSUSB_MC_IRQ 92 /* High-speed USB OTG */ -#define OMAP3_HSUSB_DMA_IRQ 93 /* High-speed USB OTG DMA */ -#define OMAP3_MMC3_IRQ 94 /* MMC/SD module 3 */ - -/* General-purpose timer register map */ -#define OMAP3_GPTIMER1_BASE 0x48318000 - /* GPTIMER1 physical address */ -#define OMAP3_GPTIMER2_BASE 0x49032000 - /* GPTIMER2 physical address */ -#define OMAP3_GPTIMER3_BASE 0x49034000 - /* GPTIMER3 physical address */ -#define OMAP3_GPTIMER4_BASE 0x49036000 - /* GPTIMER4 physical address */ -#define OMAP3_GPTIMER5_BASE 0x49038000 - /* GPTIMER5 physical address */ -#define OMAP3_GPTIMER6_BASE 0x4903A000 - /* GPTIMER6 physical address */ -#define OMAP3_GPTIMER7_BASE 0x4903C000 - /* GPTIMER7 physical address */ -#define OMAP3_GPTIMER8_BASE 0x4903E000 - /* GPTIMER8 physical address */ -#define OMAP3_GPTIMER9_BASE 0x49040000 - /* GPTIMER9 physical address */ -#define OMAP3_GPTIMER10_BASE 0x48086000 - /* GPTIMER10 physical address */ -#define OMAP3_GPTIMER11_BASE 0x48088000 - /* GPTIMER11 physical address */ - - -/* General-purpose timer registers */ -#define OMAP3_TIMER_TIDR 0x000 - /* IP revision code */ -#define OMAP3_TIMER_TIOCP_CFG 0x010 - /* Controls params for GP timer L4 iface */ -#define OMAP3_TIMER_TISTAT 0x014 - /* Status (excl. interrupt status) */ -#define OMAP3_TIMER_TISR 0x018 - /* Pending interrupt status */ -#define OMAP3_TIMER_TIER 0x01C - /* Interrupt enable */ -#define OMAP3_TIMER_TWER 0x020 - /* Wakeup enable */ -#define OMAP3_TIMER_TCLR 0x024 - /* Controls optional features */ -#define OMAP3_TIMER_TCRR 0x028 - /* Internal counter value */ -#define OMAP3_TIMER_TLDR 0x02C - /* Timer load value */ -#define OMAP3_TIMER_TTGR 0x030 - /* Triggers counter reload */ -#define OMAP3_TIMER_TWPS 0x034 - /* Indicates if Write-Posted pending */ -#define OMAP3_TIMER_TMAR 0x038 - /* Value to be compared with counter */ -#define OMAP3_TIMER_TCAR1 0x03C - /* First captured value of counter reg */ -#define OMAP3_TIMER_TSICR 0x040 - /* Control posted mode and functional SW rst */ -#define OMAP3_TIMER_TCAR2 0x044 - /* Second captured value of counter register */ -#define OMAP3_TIMER_TPIR 0x048 - /* Positive increment (1 ms tick) */ -#define OMAP3_TIMER_TNIR 0x04C - /* Negative increment (1 ms tick) */ -#define OMAP3_TIMER_TCVR 0x050 - /* Defines TCRR is sub/over-period (1 ms tick) */ -#define OMAP3_TIMER_TOCR 0x054 - /* Masks tick interrupt */ -#define OMAP3_TIMER_TOWR 0x058 - /* Number of masked overflow interrupts */ - -/* Interrupt status register fields */ -#define OMAP3_TISR_MAT_IT_FLAG (1 << 0) /* Pending match interrupt status */ -#define OMAP3_TISR_OVF_IT_FLAG (1 << 1) /* Pending overflow interrupt status */ -#define OMAP3_TISR_TCAR_IT_FLAG (1 << 2) /* Pending capture interrupt status */ - -/* Interrupt enable register fields */ -#define OMAP3_TIER_MAT_IT_ENA (1 << 0) /* Enable match interrupt */ -#define OMAP3_TIER_OVF_IT_ENA (1 << 1) /* Enable overflow interrupt */ -#define OMAP3_TIER_TCAR_IT_ENA (1 << 2) /* Enable capture interrupt */ - -/* Timer control fields */ -#define OMAP3_TCLR_ST (1 << 0) /* Start/stop timer */ -#define OMAP3_TCLR_AR (1 << 1) /* Autoreload or one-shot mode */ -#define OMAP3_TCLR_PRE (1 << 5) /* Prescaler on */ -#define OMAP3_TCLR_PTV (1 << 1) /* looks like "bleed" from Minix */ -#define OMAP3_TCLR_OVF_TRG (1 << 10) /* Overflow trigger */ - - -#define OMAP3_CM_CLKSEL_GFX 0x48004b40 -#define OMAP3_CM_CLKEN_PLL 0x48004d00 -#define OMAP3_CM_FCLKEN1_CORE 0x48004A00 -#define OMAP3_CM_CLKSEL_CORE 0x48004A40 /* GPT10 src clock sel. */ -#define OMAP3_CM_FCLKEN_PER 0x48005000 -#define OMAP3_CM_CLKSEL_PER 0x48005040 -#define OMAP3_CM_CLKSEL_WKUP 0x48004c40 /* GPT1 source clock selection */ - - -#define CM_MODULEMODE_MASK (0x3 << 0) -#define CM_MODULEMODE_ENABLE (0x2 << 0) -#define CM_MODULEMODE_DISABLED (0x0 << 0) - -#define CM_CLKCTRL_IDLEST (0x3 << 16) -#define CM_CLKCTRL_IDLEST_FUNC (0x0 << 16) -#define CM_CLKCTRL_IDLEST_TRANS (0x1 << 16) -#define CM_CLKCTRL_IDLEST_IDLE (0x2 << 16) -#define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16) - -#define CM_WKUP_BASE 0x44E00400 /* Clock Module Wakeup Registers */ - -#define CM_WKUP_TIMER1_CLKCTRL (CM_WKUP_BASE + 0xC4) - /* This register manages the TIMER1 clocks. [Memory Mapped] */ - -#define CM_PER_BASE 0x44E00000 /* Clock Module Peripheral Registers */ -#define CM_PER_TIMER7_CLKCTRL (CM_PER_BASE + 0x7C) - /* This register manages the TIMER7 clocks. [Memory Mapped] */ - -/* CM_DPLL registers */ - -#define CM_DPLL_BASE 0x44E00500 /* Clock Module PLL Registers */ - -#define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28) - -#define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0) -#define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0) - /* Select CLK_M_OSC clock */ -#define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0) - /* Select CLK_32KHZ clock */ -#define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0) - /* Select TCLKIN clock */ -#define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0) - /* Select CLK_RC32K clock */ -#define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0) - /* Selects the CLK_32768 from 32KHz Crystal Osc */ - -#define CLKSEL_TIMER7_CLK (CM_DPLL_BASE + 0x04) -#define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0) -#define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0) /* Select TCLKIN clock */ -#define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_M_OSC clock */ -#define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */ -#define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */ - -/*RTC CLOCK BASE & Registers*/ -#define CM_RTC_BASE 0x44E00800 -#define CM_RTC_RTC_CLKCTRL 0x0 -#define CM_RTC_CLKSTCTRL 0x4 - - -#define OMAP3_CLKSEL_GPT1 (1 << 0) -#define OMAP3_CLKSEL_GPT10 (1 << 6) -#define OMAP3_CLKSEL_GPT11 (1 << 7) - -#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 - -#define ARM_TTBR_ADDR_MASK (0xffffc000) -#define ARM_TTBR_OUTER_NC (0x0 << 3) /* Non-cacheable*/ -#define ARM_TTBR_OUTER_WBWA (0x1 << 3) /* Outer Write-Back */ -#define ARM_TTBR_OUTER_WT (0x2 << 3) /* Outer Write-Through */ -#define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back */ -#define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA - -/* cpu control flags */ -/* CPU control register (CP15 register 1) */ -#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ -#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ -#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ -#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ -#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ -#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ -#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ -#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ -#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ -#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ -#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ -#define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */ -#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ -#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ -#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ -#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ -#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ -#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ -#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ -#define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */ -#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ -#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ -#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ -#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */ -#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */ -#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ - -#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE - -/* VM bits */ - -/* Big page (1MB section) specific flags. */ -#define ARM_VM_SECTION (1 << 1) - /* 1MB section */ -#define ARM_VM_SECTION_PRESENT (1 << 1) - /* Section is present */ -#define ARM_VM_SECTION_B (1 << 2) - /* B Bit */ -#define ARM_VM_SECTION_C (1 << 3) - /* C Bit */ -#define ARM_VM_SECTION_DOMAIN (0xF << 5) - /* Domain Number */ -#define ARM_VM_SECTION_SUPER (0x1 << 10) - /* Super access only AP[1:0] */ -#define ARM_VM_SECTION_USER (0x3 << 10) - /* Super/User access AP[1:0] */ -#define ARM_VM_SECTION_TEX0 (1 << 12) - /* TEX[0] */ -#define ARM_VM_SECTION_TEX1 (1 << 13) - /* TEX[1] */ -#define ARM_VM_SECTION_TEX2 (1 << 14) - /* TEX[2] */ -#define ARM_VM_SECTION_RO (1 << 15) - /* Read only access AP[2] */ -#define ARM_VM_SECTION_SHAREABLE (1 << 16) - /* Shareable */ -#define ARM_VM_SECTION_NOTGLOBAL (1 << 17) - /* Not Global */ - -#define ARM_VM_SECTION_WB \ - (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B ) -/* inner and outer write-back, write-allocate */ -#define ARM_VM_SECTION_WT \ - (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C ) -/* inner and outer write-through, no write-allocate */ -#define ARM_VM_SECTION_WTWB \ - (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C ) -/* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */ - -/* shareable device */ -#define ARM_VM_SECTION_CACHED ARM_VM_SECTION_WTWB -#define ARM_VM_SECTION_DEVICE (ARM_VM_SECTION_B) diff --git a/c/src/lib/libcpu/arm/shared/include/omap_timer.h b/c/src/lib/libcpu/arm/shared/include/omap_timer.h deleted file mode 100644 index ef8787a571..0000000000 --- a/c/src/lib/libcpu/arm/shared/include/omap_timer.h +++ /dev/null @@ -1,39 +0,0 @@ -/** - * @file - * - * @brief Clock driver configuration. - */ - -#include <stdint.h> - -typedef struct omap_timer_registers -{ - uint32_t TIDR; - uint32_t TIOCP_CFG; - uint32_t TISTAT; - uint32_t TISR; - uint32_t TIER; - uint32_t TWER; - uint32_t TCLR; - uint32_t TCRR; - uint32_t TLDR; - uint32_t TTGR; - uint32_t TWPS; - uint32_t TMAR; - uint32_t TCAR1; - uint32_t TSICR; - uint32_t TCAR2; - uint32_t TPIR; - uint32_t TNIR; - uint32_t TCVR; - uint32_t TOCR; - uint32_t TOWR; - -} omap_timer_registers_t; - -typedef struct omap_timer -{ - uint32_t base; - int irq_nr; - struct omap_timer_registers *regs; -} omap_timer_t; diff --git a/c/src/lib/libcpu/bfin/Makefile.am b/c/src/lib/libcpu/bfin/Makefile.am index 1dc90d481b..5f981657f7 100644 --- a/c/src/lib/libcpu/bfin/Makefile.am +++ b/c/src/lib/libcpu/bfin/Makefile.am @@ -6,21 +6,12 @@ EXTRA_DIST = noinst_PROGRAMS = -include_bspdir = $(includedir)/bsp -include_libcpudir = $(includedir)/libcpu - -include_bsp_HEADERS = -include_libcpu_HEADERS = - ############ # Start of bf52x files if bf52x -include_HEADERS = bf52x/include/bf52x.h - ## INTERRUPT -include_bsp_HEADERS += bf52x/interrupt/interrupt.h noinst_PROGRAMS += bf52x/interrupt.rel bf52x_interrupt_rel_SOURCES = bf52x/interrupt/interrupt.c \ bf52x/interrupt/interrupt.h @@ -31,33 +22,12 @@ endif # endof bf52x ############ -include_libcpu_HEADERS += include/bf533.h -include_libcpu_HEADERS += include/bf537.h -include_libcpu_HEADERS += include/cecRegs.h -include_libcpu_HEADERS += include/memoryRegs.h -include_libcpu_HEADERS += include/mmuRegs.h -include_libcpu_HEADERS += include/sicRegs.h -include_libcpu_HEADERS += include/ebiuRegs.h -include_libcpu_HEADERS += include/ppiRegs.h -include_libcpu_HEADERS += include/coreTimerRegs.h -include_libcpu_HEADERS += include/wdogRegs.h -include_libcpu_HEADERS += include/timerRegs.h -include_libcpu_HEADERS += include/dmaRegs.h -include_libcpu_HEADERS += include/ethernetRegs.h -include_libcpu_HEADERS += include/uartRegs.h -include_libcpu_HEADERS += include/sportRegs.h -include_libcpu_HEADERS += include/twiRegs.h -include_libcpu_HEADERS += include/spiRegs.h -include_libcpu_HEADERS += include/rtcRegs.h -include_libcpu_HEADERS += include/gpioRegs.h - noinst_PROGRAMS += cache.rel cache_rel_SOURCES = cache/cache.c \ ../shared/src/cache_manager.c cache/cache_.h cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/cache cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -include_libcpu_HEADERS += mmu/mmu.h noinst_PROGRAMS += mmu.rel mmu_rel_SOURCES = mmu/mmu.c mmu_rel_CPPFLAGS = $(AM_CPPFLAGS) @@ -66,7 +36,6 @@ mmu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) if bf52x else -include_libcpu_HEADERS += interrupt/interrupt.h noinst_PROGRAMS += interrupt.rel interrupt_rel_SOURCES = interrupt/interrupt.c interrupt_rel_CPPFLAGS = $(AM_CPPFLAGS) @@ -84,25 +53,21 @@ rtc_rel_SOURCES = clock/rtc.c clock/rtc.h rtc_rel_CPPFLAGS = $(AM_CPPFLAGS) rtc_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -include_libcpu_HEADERS += serial/uart.h noinst_PROGRAMS += uart.rel uart_rel_SOURCES = serial/uart.c uart_rel_CPPFLAGS = $(AM_CPPFLAGS) uart_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -include_libcpu_HEADERS += serial/sport.h noinst_PROGRAMS += sport.rel sport_rel_SOURCES = serial/sport.c sport_rel_CPPFLAGS = $(AM_CPPFLAGS) sport_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -include_libcpu_HEADERS += serial/spi.h noinst_PROGRAMS += spi.rel spi_rel_SOURCES = serial/spi.c spi_rel_CPPFLAGS = $(AM_CPPFLAGS) spi_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -include_libcpu_HEADERS += serial/twi.h noinst_PROGRAMS += twi.rel twi_rel_SOURCES = serial/twi.c twi_rel_CPPFLAGS = $(AM_CPPFLAGS) @@ -115,7 +80,6 @@ timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) if HAS_NETWORKING ## network -include_libcpu_HEADERS += network/ethernet.h network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ noinst_PROGRAMS += network.rel network_rel_SOURCES = network/ethernet.c @@ -123,5 +87,4 @@ network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS) network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h b/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h deleted file mode 100644 index 6c3d087c79..0000000000 --- a/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - *@file bf52x.h - * - *@brief - * - This file provides the register address for the 52X model. The file is - * based on the 533 implementation with some addition to support 52X range of - * processors. - * - * Target: TLL6527v1-0 - * Compiler: - * - * COPYRIGHT (c) 2010 by ECE Northeastern University. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license - * - * @author Rohan Kangralkar, ECE, Northeastern University - * (kangralkar.r@husky.neu.edu) - * - * LastChange: - */ - -#ifndef _BF52X_H_ -#define _BF52X_H_ - -/* register (or register block) addresses */ - -#define SIC_BASE_ADDRESS 0xffc00100 -#define WDOG_BASE_ADDRESS 0xffc00200 -#define RTC_BASE_ADDRESS 0xffc00300 -#define UART0_BASE_ADDRESS 0xffc00400 -#define UART1_BASE_ADDRESS 0xffc02000 -#define SPI_BASE_ADDRESS 0xffc00500 -#define TIMER_BASE_ADDRESS 0xffc00600 -#define TIMER_CHANNELS 3 -#define TIMER_PITCH 0x10 -#define TIMER0_BASE_ADDRESS 0xffc00600 -#define TIMER1_BASE_ADDRESS 0xffc00610 -#define TIMER2_BASE_ADDRESS 0xffc00620 -#define TIMER_ENABLE 0xffc00640 -#define TIMER_DISABLE 0xffc00644 -#define TIMER_STATUS 0xffc00648 -#define PORTFIO_BASE_ADDRESS 0xffc00700 -#define SPORT0_BASE_ADDRESS 0xffc00800 -#define SPORT1_BASE_ADDRESS 0xffc00900 -#define EBIU_BASE_ADDRESS 0xffc00a00 -#define DMA_TC_PER 0xffc00b0c -#define DMA_TC_CNT 0xffc00b10 -#define DMA_BASE_ADDRESS 0xffc00c00 -#define DMA_CHANNELS 8 -#define DMA_PITCH 0x40 -#define DMA0_BASE_ADDRESS 0xffc00c00 -#define DMA1_BASE_ADDRESS 0xffc00c40 -#define DMA2_BASE_ADDRESS 0xffc00c80 -#define DMA3_BASE_ADDRESS 0xffc00cc0 -#define DMA4_BASE_ADDRESS 0xffc00d00 -#define DMA5_BASE_ADDRESS 0xffc00d40 -#define DMA6_BASE_ADDRESS 0xffc00d80 -#define DMA7_BASE_ADDRESS 0xffc00dc0 -#define DMA8_BASE_ADDRESS 0xffc00e00 -#define DMA9_BASE_ADDRESS 0xffc00e40 -#define DMA10_BASE_ADDRESS 0xffc00e80 -#define DMA11_BASE_ADDRESS 0xffc00ec0 -#define MDMA_BASE_ADDRESS 0xffc00e00 -#define MDMA_CHANNELS 2 -#define MDMA_D_S 0x40 -#define MDMA_PITCH 0x80 -#define MDMA0D_BASE_ADDRESS 0xffc00e00 -#define MDMA0S_BASE_ADDRESS 0xffc00e40 -#define MDMA1D_BASE_ADDRESS 0xffc00e80 -#define MDMA1S_BASE_ADDRESS 0xffc00ec0 -#define PPI_BASE_ADDRESS 0xffc01000 - - -/* register fields */ - -#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800 -#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11 -#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700 -#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8 -#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0 -#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4 -#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f -#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0 - -#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800 -#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11 -#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700 -#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8 -#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0 -#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4 -#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f -#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0 - -#define TIMER_ENABLE_TIMEN2 0x0004 -#define TIMER_ENABLE_TIMEN1 0x0002 -#define TIMER_ENABLE_TIMEN0 0x0001 - -#define TIMER_DISABLE_TIMDIS2 0x0004 -#define TIMER_DISABLE_TIMDIS1 0x0002 -#define TIMER_DISABLE_TIMDIS0 0x0001 - -#define TIMER_STATUS_TRUN2 0x00004000 -#define TIMER_STATUS_TRUN1 0x00002000 -#define TIMER_STATUS_TRUN0 0x00001000 -#define TIMER_STATUS_TOVF_ERR2 0x00000040 -#define TIMER_STATUS_TOVF_ERR1 0x00000020 -#define TIMER_STATUS_TOVF_ERR0 0x00000010 -#define TIMER_STATUS_TIMIL2 0x00000004 -#define TIMER_STATUS_TIMIL1 0x00000002 -#define TIMER_STATUS_TIMIL0 0x00000001 - -/* Core Event Controller vectors */ - -#define CEC_EMULATION_VECTOR 0 -#define CEC_RESET_VECTOR 1 -#define CEC_NMI_VECTOR 2 -#define CEC_EXCEPTIONS_VECTOR 3 -#define CEC_HARDWARE_ERROR_VECTOR 5 -#define CEC_CORE_TIMER_VECTOR 6 -#define CEC_INTERRUPT_BASE_VECTOR 7 -#define CEC_INTERRUPT_COUNT 9 - - -/* System Interrupt Controller vectors */ - -#define SIC_IAR_COUNT 8 - -#endif /* _BF52X_H_ */ - diff --git a/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h b/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h deleted file mode 100644 index 7a98775dd5..0000000000 --- a/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h +++ /dev/null @@ -1,144 +0,0 @@ -/** - *@file interrupt.h - * - *@brief - * - This file implements interrupt dispatcher. The init code is taken from - * the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR - * registers some portion is written twice. - * - * Target: TLL6527v1-0 - * Compiler: - * - * COPYRIGHT (c) 2010 by ECE Northeastern University. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license - * - * @author Rohan Kangralkar, ECE, Northeastern University - * (kangralkar.r@husky.neu.edu) - * - * LastChange: - */ - -#ifndef _BFIN_INTERRUPT_H_ -#define _BFIN_INTERRUPT_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** The type of interrupts handled by the SIC - */ -typedef enum { - IRQ_PLL_WAKEUP_INTERRUPT, /* 0 */ - IRQ_DMA_ERROR_0, /* 1 */ - IRQ_DMAR0_BLOCK_INTERRUPT, /* 2 */ - IRQ_DMAR1_BLOCK_INTERRUPT, /* 3 */ - IRQ_DMAR0_OVERFLOW_ERROR, /* 4 */ - IRQ_DMAR1_OVERFLOW_ERROR, /* 5 */ - IRQ_PPI_STATUS, /* 6 */ - IRQ_MAC_STATUS, /* 7 */ - IRQ_SPORT0_STATUS, /* 8 */ - IRQ_SPORT1_STATUS, /* 9 */ - IRQ_RESERVED_10, /* 10 */ - IRQ_RESERVED_11, /* 11 */ - IRQ_UART0_STATUS, /* 12 */ - IRQ_UART1_STATUS, /* 13 */ - IRQ_REAL_TIME_CLOCK, /* 14 */ - IRQ_DMA0_PPI_NFC, /* 15 */ - IRQ_DMA3_SPORT0_RX, /* 16 */ - IRQ_DMA4_SPORT0_TX, /* 17 */ - IRQ_DMA5_SPORT1_RX, /* 18 */ - IRQ_DMA6_SPORT1_TX, /* 19 */ - IRQ_TWI_INTERRUPT, /* 20 */ - IRQ_DMA7_SPI, /* 21 */ - IRQ_DMA8_UART0_RX, /* 22 */ - IRQ_DMA9_UART0_TX, /* 23 */ - IRQ_DMA10_UART1_RX, /* 24 */ - IRQ_DMA11_UART1_TX, /* 25 */ - IRQ_OTP, /* 26 */ - IRQ_GP_COUNTER, /* 27 */ - IRQ_DMA1_MAC_RX_HOSTDP, /* 28 */ - IRQ_PORT_H_INTERRUPT_A, /* 29 */ - IRQ_DMA2_MAC_TX_NFC, /* 30 */ - IRQ_PORT_H_INTERRUPT_B, /* 31 */ - SIC_ISR0_MAX, /* 32 ***/ - IRQ_TIMER0 = SIC_ISR0_MAX, /* 32 */ - IRQ_TIMER1, /* 33 */ - IRQ_TIMER2, /* 34 */ - IRQ_TIMER3, /* 35 */ - IRQ_TIMER4, /* 36 */ - IRQ_TIMER5, /* 37 */ - IRQ_TIMER6, /* 38 */ - IRQ_TIMER7, /* 39 */ - IRQ_PORT_G_INTERRUPT_A, /* 40 */ - IRQ_PORT_G_INTERRUPT_B, /* 41 */ - IRQ_MDMA0_STREAM_0_INTERRUPT, /* 42 */ - IRQ_MDMA1_STREAM_0_INTERRUPT, /* 43 */ - IRQ_SOFTWARE_WATCHDOG_INTERRUPT, /* 44 */ - IRQ_PORT_F_INTERRUPT_A, /* 45 */ - IRQ_PORT_F_INTERRUPT_B, /* 46 */ - IRQ_SPI_STATUS, /* 47 */ - IRQ_NFC_STATUS, /* 48 */ - IRQ_HOSTDP_STATUS, /* 49 */ - IRQ_HOREAD_DONE_INTERRUPT, /* 50 */ - IRQ_RESERVED_19, /* 51 */ - IRQ_USB_INT0_INTERRUPT, /* 52 */ - IRQ_USB_INT1_INTERRUPT, /* 53 */ - IRQ_USB_INT2_INTERRUPT, /* 54 */ - IRQ_USB_DMAINT, /* 55 */ - IRQ_MAX, /* 56 */ -} e_isr_t; - - - - -/* source is the source to the SIC (the bit number in SIC_ISR). isr is - the function that will be called when the interrupt is active. */ -typedef struct bfin_isr_s { -#if INTERRUPT_USE_TABLE - e_isr_t source; - void (*pFunc)(void *arg); - void *pArg; - int priority; /** not used */ -#else - int source; - void (*isr)(void *arg); - void *_arg; - /* the following are for internal use only */ - uint32_t mask0; - uint32_t mask1; - uint32_t vector; - struct bfin_isr_s *next; -#endif -} bfin_isr_t; - -/** - * This routine registers a new ISR. It will write a new entry to the IVT table - * @param isr contains a callback function and source - * @return rtems status code - */ -rtems_status_code bfin_interrupt_register(bfin_isr_t *isr); - -/** - * This function unregisters a registered interrupt handler. - * @param isr - */ -rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr); - -/** - * blackfin interrupt initialization routine. It initializes the bfin ISR - * dispatcher. It will also create SIC CEC map which will be used for - * identifying the ISR. - */ -void bfin_interrupt_init(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* _BFIN_INTERRUPT_H_ */ - diff --git a/c/src/lib/libcpu/bfin/configure.ac b/c/src/lib/libcpu/bfin/configure.ac index 7888b083ea..4330957698 100644 --- a/c/src/lib/libcpu/bfin/configure.ac +++ b/c/src/lib/libcpu/bfin/configure.ac @@ -3,6 +3,8 @@ AC_PREREQ([2.69]) AC_INIT([rtems-c-src-lib-libcpu-bfin],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) RTEMS_TOP([../../../../..],[../../..]) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP RTEMS_CANONICAL_TARGET_CPU diff --git a/c/src/lib/libcpu/bfin/include/bf533.h b/c/src/lib/libcpu/bfin/include/bf533.h deleted file mode 100644 index 78cfaa0125..0000000000 --- a/c/src/lib/libcpu/bfin/include/bf533.h +++ /dev/null @@ -1,135 +0,0 @@ -/* Blackfin BF533 Definitions - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _bf533_h_ -#define _bf533_h_ - -/* register (or register block) addresses */ - -#define SIC_BASE_ADDRESS 0xffc00100 -#define WDOG_BASE_ADDRESS 0xffc00200 -#define RTC_BASE_ADDRESS 0xffc00300 -#define UART0_BASE_ADDRESS 0xffc00400 -#define SPI_BASE_ADDRESS 0xffc00500 -#define TIMER_BASE_ADDRESS 0xffc00600 -#define TIMER_CHANNELS 3 -#define TIMER_PITCH 0x10 -#define TIMER0_BASE_ADDRESS 0xffc00600 -#define TIMER1_BASE_ADDRESS 0xffc00610 -#define TIMER2_BASE_ADDRESS 0xffc00620 -#define TIMER_ENABLE 0xffc00640 -#define TIMER_DISABLE 0xffc00644 -#define TIMER_STATUS 0xffc00648 -#define PORTFIO_BASE_ADDRESS 0xffc00700 -#define SPORT0_BASE_ADDRESS 0xffc00800 -#define SPORT1_BASE_ADDRESS 0xffc00900 -#define EBIU_BASE_ADDRESS 0xffc00a00 -#define DMA_TC_PER 0xffc00b0c -#define DMA_TC_CNT 0xffc00b10 -#define DMA_BASE_ADDRESS 0xffc00c00 -#define DMA_CHANNELS 8 -#define DMA_PITCH 0x40 -#define DMA0_BASE_ADDRESS 0xffc00c00 -#define DMA1_BASE_ADDRESS 0xffc00c40 -#define DMA2_BASE_ADDRESS 0xffc00c80 -#define DMA3_BASE_ADDRESS 0xffc00cc0 -#define DMA4_BASE_ADDRESS 0xffc00d00 -#define DMA5_BASE_ADDRESS 0xffc00d40 -#define DMA6_BASE_ADDRESS 0xffc00d80 -#define DMA7_BASE_ADDRESS 0xffc00dc0 -#define MDMA_BASE_ADDRESS 0xffc00e00 -#define MDMA_CHANNELS 2 -#define MDMA_D_S 0x40 -#define MDMA_PITCH 0x80 -#define MDMA0D_BASE_ADDRESS 0xffc00e00 -#define MDMA0S_BASE_ADDRESS 0xffc00e40 -#define MDMA1D_BASE_ADDRESS 0xffc00e80 -#define MDMA1S_BASE_ADDRESS 0xffc00ec0 -#define PPI_BASE_ADDRESS 0xffc01000 - - -/* register fields */ - -#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800 -#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11 -#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700 -#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8 -#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0 -#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4 -#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f -#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0 - -#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800 -#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11 -#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700 -#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8 -#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0 -#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4 -#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f -#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0 - -#define TIMER_ENABLE_TIMEN2 0x0004 -#define TIMER_ENABLE_TIMEN1 0x0002 -#define TIMER_ENABLE_TIMEN0 0x0001 - -#define TIMER_DISABLE_TIMDIS2 0x0004 -#define TIMER_DISABLE_TIMDIS1 0x0002 -#define TIMER_DISABLE_TIMDIS0 0x0001 - -#define TIMER_STATUS_TRUN2 0x00004000 -#define TIMER_STATUS_TRUN1 0x00002000 -#define TIMER_STATUS_TRUN0 0x00001000 -#define TIMER_STATUS_TOVF_ERR2 0x00000040 -#define TIMER_STATUS_TOVF_ERR1 0x00000020 -#define TIMER_STATUS_TOVF_ERR0 0x00000010 -#define TIMER_STATUS_TIMIL2 0x00000004 -#define TIMER_STATUS_TIMIL1 0x00000002 -#define TIMER_STATUS_TIMIL0 0x00000001 - -/* Core Event Controller vectors */ - -#define CEC_EMULATION_VECTOR 0 -#define CEC_RESET_VECTOR 1 -#define CEC_NMI_VECTOR 2 -#define CEC_EXCEPTIONS_VECTOR 3 -#define CEC_HARDWARE_ERROR_VECTOR 5 -#define CEC_CORE_TIMER_VECTOR 6 -#define CEC_INTERRUPT_BASE_VECTOR 7 -#define CEC_INTERRUPT_COUNT 9 - - -/* System Interrupt Controller vectors */ - -#define SIC_IAR_COUNT 3 - -#define SIC_PLL_WAKEUP_VECTOR 0 -#define SIC_DMA_ERROR_VECTOR 1 -#define SIC_PPI_ERROR_VECTOR 2 -#define SIC_SPORT0_ERROR_VECTOR 3 -#define SIC_SPORT1_ERROR_VECTOR 4 -#define SIC_SPI_ERROR_VECTOR 5 -#define SIC_UART0_ERROR_VECTOR 6 -#define SIC_RTC_VECTOR 7 -#define SIC_DMA0_PPI_VECTOR 8 -#define SIC_DMA1_SPORT0_RX_VECTOR 9 -#define SIC_DMA2_SPORT0_TX_VECTOR 10 -#define SIC_DMA3_SPORT1_RX_VECTOR 11 -#define SIC_DMA4_SPORT1_TX_VECTOR 12 -#define SIC_DMA5_SPI_VECTOR 13 -#define SIC_DMA6_UART0_RX_VECTOR 14 -#define SIC_DMA7_UART0_TX_VECTOR 15 -#define SIC_TIMER0_VECTOR 16 -#define SIC_TIMER1_VECTOR 17 -#define SIC_TIMER2_VECTOR 18 -#define SIC_MDMA0_VECTOR 21 -#define SIC_MDMA1_VECTOR 22 -#define SIC_WATCHDOG_VECTOR 23 - -#endif /* _bf533_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/bf537.h b/c/src/lib/libcpu/bfin/include/bf537.h deleted file mode 100644 index 8ed235205f..0000000000 --- a/c/src/lib/libcpu/bfin/include/bf537.h +++ /dev/null @@ -1,225 +0,0 @@ -/* Blackfin BF537 Definitions - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _bf537_h_ -#define _bf537_h_ - -/* register (or register block) addresses */ - -#define SIC_BASE_ADDRESS 0xffc00100 -#define WDOG_BASE_ADDRESS 0xffc00200 -#define RTC_BASE_ADDRESS 0xffc00300 -#define UART0_BASE_ADDRESS 0xffc00400 -#define SPI_BASE_ADDRESS 0xffc00500 -#define TIMER_BASE_ADDRESS 0xffc00600 -#define TIMER_CHANNELS 8 -#define TIMER_PITCH 0x10 -#define TIMER0_BASE_ADDRESS 0xffc00600 -#define TIMER1_BASE_ADDRESS 0xffc00610 -#define TIMER2_BASE_ADDRESS 0xffc00620 -#define TIMER3_BASE_ADDRESS 0xffc00630 -#define TIMER4_BASE_ADDRESS 0xffc00640 -#define TIMER5_BASE_ADDRESS 0xffc00650 -#define TIMER6_BASE_ADDRESS 0xffc00660 -#define TIMER7_BASE_ADDRESS 0xffc00670 -#define TIMER_ENABLE 0xffc00680 -#define TIMER_DISABLE 0xffc00684 -#define TIMER_STATUS 0xffc00688 -#define PORTFIO_BASE_ADDRESS 0xffc00700 -#define SPORT0_BASE_ADDRESS 0xffc00800 -#define SPORT1_BASE_ADDRESS 0xffc00900 -#define EBIU_BASE_ADDRESS 0xffc00a00 -#define DMA_TC_PER 0xffc00b0c -#define DMA_TC_CNT 0xffc00b10 -#define DMA_BASE_ADDRESS 0xffc00c00 -#define DMA_CHANNELS 12 -#define DMA_PITCH 0x40 -#define DMA0_BASE_ADDRESS 0xffc00c00 -#define DMA1_BASE_ADDRESS 0xffc00c40 -#define DMA2_BASE_ADDRESS 0xffc00c80 -#define DMA3_BASE_ADDRESS 0xffc00cc0 -#define DMA4_BASE_ADDRESS 0xffc00d00 -#define DMA5_BASE_ADDRESS 0xffc00d40 -#define DMA6_BASE_ADDRESS 0xffc00d80 -#define DMA7_BASE_ADDRESS 0xffc00dc0 -#define DMA8_BASE_ADDRESS 0xffc00e00 -#define DMA9_BASE_ADDRESS 0xffc00e40 -#define DMA10_BASE_ADDRESS 0xffc00e80 -#define DMA11_BASE_ADDRESS 0xffc00ec0 -#define MDMA_BASE_ADDRESS 0xffc00f00 -#define MDMA_CHANNELS 2 -#define MDMA_D_S 0x40 -#define MDMA_PITCH 0x80 -#define MDMA0D_BASE_ADDRESS 0xffc00f00 -#define MDMA0S_BASE_ADDRESS 0xffc00f40 -#define MDMA1D_BASE_ADDRESS 0xffc00f80 -#define MDMA1S_BASE_ADDRESS 0xffc00fc0 -#define PPI_BASE_ADDRESS 0xffc01000 -#define TWI_BASE_ADDRESS 0xffc01400 -#define PORTGIO_BASE_ADDRESS 0xffc01500 -#define PORTHIO_BASE_ADDRESS 0xffc01700 -#define UART1_BASE_ADDRESS 0xffc02000 -#define CAN_BASE_ADDRESS 0xffc02a00 -#define CAN_AM_BASE_ADDRESS 0xffc02b00 -#define CAN_MB_BASE_ADDRESS 0xffc02c00 -#define EMAC_BASE_ADDRESS 0xffc03000 -#define PORTF_FER 0xffc03200 -#define PORTG_FER 0xffc03204 -#define PORTH_FER 0xffc03208 -#define PORT_MUX 0xffc0320c -#define HMDMA0_BASE_ADDRESS 0xffc03300 -#define HMDMA1_BASE_ADDRESS 0xffc03340 - - -/* register fields */ - -#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800 -#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11 -#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700 -#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8 -#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0 -#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4 -#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f -#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0 - -#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800 -#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11 -#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700 -#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8 -#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0 -#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4 -#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f -#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0 - -#define TIMER_ENABLE_TIMEN7 0x0080 -#define TIMER_ENABLE_TIMEN6 0x0040 -#define TIMER_ENABLE_TIMEN5 0x0020 -#define TIMER_ENABLE_TIMEN4 0x0010 -#define TIMER_ENABLE_TIMEN3 0x0008 -#define TIMER_ENABLE_TIMEN2 0x0004 -#define TIMER_ENABLE_TIMEN1 0x0002 -#define TIMER_ENABLE_TIMEN0 0x0001 - -#define TIMER_DISABLE_TIMDIS7 0x0080 -#define TIMER_DISABLE_TIMDIS6 0x0040 -#define TIMER_DISABLE_TIMDIS5 0x0020 -#define TIMER_DISABLE_TIMDIS4 0x0010 -#define TIMER_DISABLE_TIMDIS3 0x0008 -#define TIMER_DISABLE_TIMDIS2 0x0004 -#define TIMER_DISABLE_TIMDIS1 0x0002 -#define TIMER_DISABLE_TIMDIS0 0x0001 - -#define TIMER_STATUS_TRUN7 0x80000000 -#define TIMER_STATUS_TRUN6 0x40000000 -#define TIMER_STATUS_TRUN5 0x20000000 -#define TIMER_STATUS_TRUN4 0x10000000 -#define TIMER_STATUS_TOVF_ERR7 0x00800000 -#define TIMER_STATUS_TOVF_ERR6 0x00400000 -#define TIMER_STATUS_TOVF_ERR5 0x00200000 -#define TIMER_STATUS_TOVF_ERR4 0x00100000 -#define TIMER_STATUS_TIMIL7 0x00080000 -#define TIMER_STATUS_TIMIL6 0x00040000 -#define TIMER_STATUS_TIMIL5 0x00020000 -#define TIMER_STATUS_TIMIL4 0x00010000 -#define TIMER_STATUS_TRUN3 0x00008000 -#define TIMER_STATUS_TRUN2 0x00004000 -#define TIMER_STATUS_TRUN1 0x00002000 -#define TIMER_STATUS_TRUN0 0x00001000 -#define TIMER_STATUS_TOVF_ERR3 0x00000080 -#define TIMER_STATUS_TOVF_ERR2 0x00000040 -#define TIMER_STATUS_TOVF_ERR1 0x00000020 -#define TIMER_STATUS_TOVF_ERR0 0x00000010 -#define TIMER_STATUS_TIMIL3 0x00000008 -#define TIMER_STATUS_TIMIL2 0x00000004 -#define TIMER_STATUS_TIMIL1 0x00000002 -#define TIMER_STATUS_TIMIL0 0x00000001 - -#define PORT_MUX_PGTE 0x0800 -#define PORT_MUX_PGRE 0x0400 -#define PORT_MUX_PGSE 0x0200 -#define PORT_MUX_PFFE 0x0100 -#define PORT_MUX_PFS4E 0x0080 -#define PORT_MUX_PFS5E 0x0040 -#define PORT_MUX_PFS6E 0x0020 -#define PORT_MUX_PFTE 0x0010 -#define PORT_MUX_PFDE 0x0008 -#define PORT_MUX_PJCE_MASK 0x0006 -#define PORT_MUX_PJCE_DR0SEC_DTOSEC 0x0000 -#define PORT_MUX_PJCE_CANRX_CANTX 0x0002 -#define PORT_MUX_PJCE_SPISSEL7 0x0004 -#define PORT_MUX_PJSE 0x0001 - - -/* Core Event Controller vectors */ - -#define CEC_EMULATION_VECTOR 0 -#define CEC_RESET_VECTOR 1 -#define CEC_NMI_VECTOR 2 -#define CEC_EXCEPTIONS_VECTOR 3 -#define CEC_HARDWARE_ERROR_VECTOR 5 -#define CEC_CORE_TIMER_VECTOR 6 -#define CEC_INTERRUPT_BASE_VECTOR 7 -#define CEC_INTERRUPT_COUNT 9 - - -/* System Interrupt Controller vectors */ - -#define SIC_IAR_COUNT 4 - -#define SIC_PLL_WAKEUP_VECTOR 0 -#define SIC_DMA_ERROR_VECTOR 1 -#define SIC_DMAR0_BLOCK_DONE_VECTOR 1 -#define SIC_DMAR1_BLOCK_DONE_VECTOR 1 -#define SIC_DMAR0_OVERFLOW_VECTOR 1 -#define SIC_DMAR1_OVERFLOW_VECTOR 1 -#define SIC_CAN_ERROR_VECTOR 2 -#define SIC_MAC_ERROR_VECTOR 2 -#define SIC_SPORT0_ERROR_VECTOR 2 -#define SIC_SPORT1_ERROR_VECTOR 2 -#define SIC_PPI_ERROR_VECTOR 2 -#define SIC_SPI_ERROR_VECTOR 2 -#define SIC_UART0_ERROR_VECTOR 2 -#define SIC_UART1_ERROR_VECTOR 2 -#define SIC_RTC_VECTOR 3 -#define SIC_DMA0_PPI_VECTOR 4 -#define SIC_DMA3_SPORT0_RX_VECTOR 5 -#define SIC_DMA4_SPORT0_TX_VECTOR 6 -#define SIC_DMA5_SPORT1_RX_VECTOR 7 -#define SIC_DMA5_SPORT1_TX_VECTOR 8 -#define SIC_TWI_VECTOR 9 -#define SIC_DMA7_SPI_VECTOR 10 -#define SIC_DMA8_UART0_RX_VECTOR 11 -#define SIC_DMA9_UART0_TX_VECTOR 12 -#define SIC_DMA10_UART1_RX_VECTOR 13 -#define SIC_DMA11_UART1_TX_VECTOR 14 -#define SIC_CAN_RX_VECTOR 15 -#define SIC_CAN_TX_VECTOR 16 -#define SIC_DMA1_MAC_RX_VECTOR 17 -#define SIC_PORTH_IRQ_A_VECTOR 17 -#define SIC_DMA2_MAC_TX_VECTOR 18 -#define SIC_PORTH_IRQ_B_VECTOR 18 -#define SIC_TIMER0_VECTOR 19 -#define SIC_TIMER1_VECTOR 20 -#define SIC_TIMER2_VECTOR 21 -#define SIC_TIMER3_VECTOR 22 -#define SIC_TIMER4_VECTOR 23 -#define SIC_TIMER5_VECTOR 24 -#define SIC_TIMER6_VECTOR 25 -#define SIC_TIMER7_VECTOR 26 -#define SIC_PORTF_IRQ_A_VECTOR 27 -#define SIC_PORTG_IRQ_A_VECTOR 27 -#define SIC_PORTG_IRQ_B_VECTOR 28 -#define SIC_MDMA0_VECTOR 29 -#define SIC_MDMA1_VECTOR 30 -#define SIC_WATCHDOG_VECTOR 31 -#define SIC_PORTF_IRQ_B_VECTOR 31 - - -#endif /* _bf537_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/cecRegs.h b/c/src/lib/libcpu/bfin/include/cecRegs.h deleted file mode 100644 index 89564c6f70..0000000000 --- a/c/src/lib/libcpu/bfin/include/cecRegs.h +++ /dev/null @@ -1,46 +0,0 @@ -/* Blackfin Core Event Controller Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _cecRegs_h_ -#define _cecRegs_h_ - -/* register addresses */ -#define CEC_EVT_BASE 0xffe02000 -#define CEC_EVT_COUNT 16 -#define CEC_EVT_PITCH 0x04 -#define CEC_EVT0 0xffe02000 -#define CEC_EVT1 0xffe02004 -#define CEC_EVT2 0xffe02008 -#define CEC_EVT3 0xffe0200c -#define CEC_EVT4 0xffe02010 -#define CEC_EVT5 0xffe02014 -#define CEC_EVT6 0xffe02018 -#define CEC_EVT7 0xffe0201c -#define CEC_EVT8 0xffe02020 -#define CEC_EVT9 0xffe02024 -#define CEC_EVT10 0xffe02028 -#define CEC_EVT11 0xffe0202c -#define CEC_EVT12 0xffe02030 -#define CEC_EVT13 0xffe02034 -#define CEC_EVT14 0xffe02038 -#define CEC_EVT15 0xffe0203c -#define CEC_IMASK 0xffe02104 -#define CEC_IPEND 0xffe02108 -#define CEC_ILAT 0xffe0210c -#define CEC_IPRIO 0xffe02110 - - -/* register fields */ - -#define CEC_IPRIO_IPRIO_MARK_MASK 0x0000000f -#define CEC_IPRIO_IPRIO_MARK_SHIFT 0 - - -#endif /* _cecRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/coreTimerRegs.h b/c/src/lib/libcpu/bfin/include/coreTimerRegs.h deleted file mode 100644 index c5b257783c..0000000000 --- a/c/src/lib/libcpu/bfin/include/coreTimerRegs.h +++ /dev/null @@ -1,29 +0,0 @@ -/* Blackfin Core Timer Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _coreTimerRegs_h_ -#define _coreTimerRegs_h_ - -/* register addresses */ - -#define TCNTL 0xffe03000 -#define TPERIOD 0xffe03004 -#define TSCALE 0xffe03008 -#define TCOUNT 0xffe0300c - - -/* register fields */ - -#define TCNTL_TINT 0x00000008 -#define TCNTL_TAUTORLD 0x00000004 -#define TCNTL_TMREN 0x00000002 -#define TCNTL_TMPWR 0x00000001 - -#endif /* _coreTimerRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/dmaRegs.h b/c/src/lib/libcpu/bfin/include/dmaRegs.h deleted file mode 100644 index 7c895b7cab..0000000000 --- a/c/src/lib/libcpu/bfin/include/dmaRegs.h +++ /dev/null @@ -1,97 +0,0 @@ -/* Blackfin DMA Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _dmaRegs_h_ -#define _dmaRegs_h_ - - -/* register addresses */ - -#define DMA_NEXT_DESC_PTR_OFFSET 0x0000 -#define DMA_START_ADDR_OFFSET 0x0004 -#define DMA_CONFIG_OFFSET 0x0008 -#define DMA_X_COUNT_OFFSET 0x0010 -#define DMA_X_MODIFY_OFFSET 0x0014 -#define DMA_Y_COUNT_OFFSET 0x0018 -#define DMA_Y_MODIFY_OFFSET 0x001c -#define DMA_CURR_DESC_PTR_OFFSET 0x0020 -#define DMA_CURR_ADDR_OFFSET 0x0024 -#define DMA_IRQ_STATUS_OFFSET 0x0028 -#define DMA_PERIPHERAL_MAP_OFFSET 0x002c -#define DMA_CURR_X_COUNT_OFFSET 0x0030 -#define DMA_CURR_Y_COUNT_OFFSET 0x0038 - -#define HMDMA_CONTROL_OFFSET 0x0000 -#define HMDMA_ECINIT_OFFSET 0x0004 -#define HMDMA_BCINIT_OFFSET 0x0008 -#define HMDMA_ECURGENT_OFFSET 0x000c -#define HMDMA_ECOVERFLOW_OFFSET 0x0010 -#define HMDMA_ECOUNT_OFFSET 0x0014 -#define HMDMA_BCOUNT_OFFSET 0x0018 - - -/* register fields */ - -#define DMA_CONFIG_FLOW_MASK 0x7000 -#define DMA_CONFIG_FLOW_STOP 0x0000 -#define DMA_CONFIG_FLOW_AUTOBUFFER 0x1000 -#define DMA_CONFIG_FLOW_DESC_ARRAY 0x4000 -#define DMA_CONFIG_FLOW_DESC_SMALL 0x6000 -#define DMA_CONFIG_FLOW_DESC_LARGE 0x7000 -#define DMA_CONFIG_NDSIZE_MASK 0x0f00 -#define DMA_CONFIG_NDSIZE_SHIFT 8 -#define DMA_CONFIG_DI_EN 0x0080 -#define DMA_CONFIG_DI_SEL 0x0040 -#define DMA_CONFIG_SYNC 0x0020 -#define DMA_CONFIG_DMA2D 0x0010 -#define DMA_CONFIG_WDSIZE_MASK 0x000c -#define DMA_CONFIG_WDSIZE_8 0x0000 -#define DMA_CONFIG_WDSIZE_16 0x0004 -#define DMA_CONFIG_WDSIZE_32 0x0008 -#define DMA_CONFIG_WNR 0x0002 -#define DMA_CONFIG_DMAEN 0x0001 - -#define DMA_IRQ_STATUS_DMA_RUN 0x0008 -#define DMA_IRQ_STATUS_DFETCH 0x0004 -#define DMA_IRQ_STATUS_DMA_ERR 0x0002 -#define DMA_IRQ_STATUS_DMA_DONE 0x0001 - -#define DMA_PERIPHERAL_MAP_PMAP_MASK 0xf000 -#define DMA_PERIPHERAL_MAP_PMAP_PPI 0x0000 -#define DMA_PERIPHERAL_MAP_PMAP_ETHRX 0x1000 -#define DMA_PERIPHERAL_MAP_PMAP_ETHTX 0x2000 -#define DMA_PERIPHERAL_MAP_PMAP_SPORT0RX 0x3000 -#define DMA_PERIPHERAL_MAP_PMAP_SPORT0TX 0x4000 -#define DMA_PERIPHERAL_MAP_PMAP_SPORT1RX 0x5000 -#define DMA_PERIPHERAL_MAP_PMAP_SPORT1TX 0x6000 -#define DMA_PERIPHERAL_MAP_PMAP_SPI 0x7000 -#define DMA_PERIPHERAL_MAP_PMAP_UART0RX 0x8000 -#define DMA_PERIPHERAL_MAP_PMAP_UART0TX 0x9000 -#define DMA_PERIPHERAL_MAP_PMAP_UART1RX 0xa000 -#define DMA_PERIPHERAL_MAP_PMAP_UART1TX 0xb000 -#define DMA_PERIPHERAL_MAP_CTYPE 0x0040 - -#define HMDMA_CONTROL_BDI 0x8000 -#define HMDMA_CONTROL_OI 0x4000 -#define HMDMA_CONTROL_PS 0x2000 -#define HMDMA_CONTROL_RBC 0x1000 -#define HMDMA_CONTROL_DRQ_MASK 0x0300 -#define HMDMA_CONTROL_DRQ_NONE 0x0000 -#define HMDMA_CONTROL_DRQ_SINGLE 0x0100 -#define HMDMA_CONTROL_DRQ_MULTIPLE 0x0200 -#define HMDMA_CONTROL_DRQ_URGENT_MULTIPLE 0x0300 -#define HMDMA_CONTROL_MBDI 0x0040 -#define HMDMA_CONTROL_BDIE 0x0020 -#define HMDMA_CONTROL_OIE 0x0010 -#define HMDMA_CONTROL_UTE 0x0008 -#define HMDMA_CONTROL_REP 0x0002 -#define HMDMA_CONTROL_HMDMAEN 0x0001 - -#endif /* _dmaRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/ebiuRegs.h b/c/src/lib/libcpu/bfin/include/ebiuRegs.h deleted file mode 100644 index 1a07ff6985..0000000000 --- a/c/src/lib/libcpu/bfin/include/ebiuRegs.h +++ /dev/null @@ -1,133 +0,0 @@ -/* Blackfin External Peripheral Interface Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _ebiuRegs_h_ -#define _ebiuRegs_h_ - -/* register addresses */ - -#define EBIU_AMGCTL (EBIU_BASE_ADDRESS + 0x0000) -#define EBIU_AMBCTL0 (EBIU_BASE_ADDRESS + 0x0004) -#define EBIU_AMBCTL1 (EBIU_BASE_ADDRESS + 0x0008) -#define EBIU_SDGCTL (EBIU_BASE_ADDRESS + 0x0010) -#define EBIU_SDBCTL (EBIU_BASE_ADDRESS + 0x0014) -#define EBIU_SDRRC (EBIU_BASE_ADDRESS + 0x0018) -#define EBIU_SDSTAT (EBIU_BASE_ADDRESS + 0x001c) - -/* register fields */ - -#define EBIU_AMGCTL_CDPRIO 0x0100 -#define EBIU_AMGCTL_AMBEN_MASK 0x000e -#define EBIU_AMGCTL_AMBEN_SHIFT 1 -#define EBIU_AMGCTL_AMCKEN 0x0001 - -#define EBIU_AMBCTL0_B1WAT_MASK 0xf0000000 -#define EBIU_AMBCTL0_B1WAT_SHIFT 28 -#define EBIU_AMBCTL0_B1RAT_MASK 0x0f000000 -#define EBIU_AMBCTL0_B1RAT_SHIFT 24 -#define EBIU_AMBCTL0_B1HT_MASK 0x00c00000 -#define EBIU_AMBCTL0_B1HT_SHIFT 22 -#define EBIU_AMBCTL0_B1ST_MASK 0x00300000 -#define EBIU_AMBCTL0_B1ST_SHIFT 20 -#define EBIU_AMBCTL0_B1TT_MASK 0x000c0000 -#define EBIU_AMBCTL0_B1TT_SHIFT 18 -#define EBIU_AMBCTL0_B1RDYPOL 0x00020000 -#define EBIU_AMBCTL0_B1RDYEN 0x00010000 -#define EBIU_AMBCTL0_B0WAT_MASK 0x0000f000 -#define EBIU_AMBCTL0_B0WAT_SHIFT 12 -#define EBIU_AMBCTL0_B0RAT_MASK 0x00000f00 -#define EBIU_AMBCTL0_B0RAT_SHIFT 8 -#define EBIU_AMBCTL0_B0HT_MASK 0x000000c0 -#define EBIU_AMBCTL0_B0HT_SHIFT 6 -#define EBIU_AMBCTL0_B0ST_MASK 0x00000030 -#define EBIU_AMBCTL0_B0ST_SHIFT 4 -#define EBIU_AMBCTL0_B0TT_MASK 0x0000000c -#define EBIU_AMBCTL0_B0TT_SHIFT 2 -#define EBIU_AMBCTL0_B0RDYPOL 0x00000002 -#define EBIU_AMBCTL0_B0RDYEN 0x00000001 - -#define EBIU_AMBCTL1_B3WAT_MASK 0xf0000000 -#define EBIU_AMBCTL1_B3WAT_SHIFT 28 -#define EBIU_AMBCTL1_B3RAT_MASK 0x0f000000 -#define EBIU_AMBCTL1_B3RAT_SHIFT 24 -#define EBIU_AMBCTL1_B3HT_MASK 0x00c00000 -#define EBIU_AMBCTL1_B3HT_SHIFT 22 -#define EBIU_AMBCTL1_B3ST_MASK 0x00300000 -#define EBIU_AMBCTL1_B3ST_SHIFT 20 -#define EBIU_AMBCTL1_B3TT_MASK 0x000c0000 -#define EBIU_AMBCTL1_B3TT_SHIFT 18 -#define EBIU_AMBCTL1_B3RDYPOL 0x00020000 -#define EBIU_AMBCTL1_B3RDYEN 0x00010000 -#define EBIU_AMBCTL1_B2WAT_MASK 0x0000f000 -#define EBIU_AMBCTL1_B2WAT_SHIFT 12 -#define EBIU_AMBCTL1_B2RAT_MASK 0x00000f00 -#define EBIU_AMBCTL1_B2RAT_SHIFT 8 -#define EBIU_AMBCTL1_B2HT_MASK 0x000000c0 -#define EBIU_AMBCTL1_B2HT_SHIFT 6 -#define EBIU_AMBCTL1_B2ST_MASK 0x00000030 -#define EBIU_AMBCTL1_B2ST_SHIFT 4 -#define EBIU_AMBCTL1_B2TT_MASK 0x0000000c -#define EBIU_AMBCTL1_B2TT_SHIFT 2 -#define EBIU_AMBCTL1_B2RDYPOL 0x00000002 -#define EBIU_AMBCTL1_B2RDYEN 0x00000001 - -#define EBIU_SDGCTL_CDDBG 0x40000000 -#define EBIU_SDGCTL_TCSR 0x20000000 -#define EBIU_SDGCTL_EMREN 0x10000000 -#define EBIU_SDGCTL_FBBRW 0x04000000 -#define EBIU_SDGCTL_EBUFE 0x02000000 -#define EBIU_SDGCTL_SRFS 0x01000000 -#define EBIU_SDGCTL_PSSE 0x00800000 -#define EBIU_SDGCTL_PSM 0x00400000 -#define EBIU_SDGCTL_PUPSD 0x00200000 -#define EBIU_SDGCTL_TWR_MASK 0x00180000 -#define EBIU_SDGCTL_TWR_SHIFT 19 -#define EBIU_SDGCTL_TRCD_MASK 0x00038000 -#define EBIU_SDGCTL_TRCD_SHIFT 15 -#define EBIU_SDGCTL_TRP_MASK 0x00003800 -#define EBIU_SDGCTL_TRP_SHIFT 11 -#define EBIU_SDGCTL_TRAS_MASK 0x000003c0 -#define EBIU_SDGCTL_TRAS_SHIFT 6 -#define EBIU_SDGCTL_PASR_MASK 0x00000030 -#define EBIU_SDGCTL_PASR_ALL 0x00000000 -#define EBIU_SDGCTL_PASR_0_1 0x00000010 -#define EBIU_SDGCTL_PASR_0 0x00000020 -#define EBIU_SDGCTL_CL_MASK 0x0000000c -#define EBIU_SDGCTL_CL_SHIFT 2 -#define EBIU_SDGCTL_SCTLE 0x00000001 - -#define EBIU_SDBCTL_EBCAW_MASK 0x0030 -#define EBIU_SDBCTL_SHIFT 4 -#define EBIU_SDBCTL_EBCAW_8 0x0000 -#define EBIU_SDBCTL_EBCAW_9 0x0010 -#define EBIU_SDBCTL_EBCAW_10 0x0020 -#define EBIU_SDBCTL_EBCAW_11 0x0030 -#define EBIU_SDBCTL_EBSZ_MASK 0x000e -#define EBIU_SDBCTL_EBSZ_SHIFT 1 -#define EBIU_SDBCTL_EBSZ_16M 0x0000 -#define EBIU_SDBCTL_EBSZ_32M 0x0002 -#define EBIU_SDBCTL_EBSZ_64M 0x0004 -#define EBIU_SDBCTL_EBSZ_128M 0x0006 -#define EBIU_SDBCTL_EBSZ_256M 0x0008 -#define EBIU_SDBCTL_EBSZ_512M 0x000a -#define EBIU_SDBCTL_EBE 0x0001 - -#define EBIU_SDRRC_RDIV_MASK 0x0fff -#define EBIU_SDRRC_RDIV_SHIFT 0 - -#define EBIU_SDSTAT_BGSTAT 0x0020 -#define EBIU_SDSTAT_SDEASE 0x0010 -#define EBIU_SDSTAT_SDRS 0x0008 -#define EBIU_SDSTAT_SDPUA 0x0004 -#define EBIU_SDSTAT_SDSRA 0x0002 -#define EBIU_SDSTAT_SDCI 0x0001 - - -#endif /* _ebiuRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/ethernetRegs.h b/c/src/lib/libcpu/bfin/include/ethernetRegs.h deleted file mode 100644 index 7bf85c576b..0000000000 --- a/c/src/lib/libcpu/bfin/include/ethernetRegs.h +++ /dev/null @@ -1,419 +0,0 @@ -/* Blackfin Ethernet Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _ethernetRegs_h_ -#define _ethernetRegs_h_ - -/* register addresses */ - -#define EMAC_OPMODE_OFFSET 0x0000 -#define EMAC_ADDRLO_OFFSET 0x0004 -#define EMAC_ADDRHI_OFFSET 0x0008 -#define EMAC_HASHLO_OFFSET 0x000c -#define EMAC_HASHHI_OFFSET 0x0010 -#define EMAC_STAADD_OFFSET 0x0014 -#define EMAC_STADAT_OFFSET 0x0018 -#define EMAC_FLC_OFFSET 0x001c -#define EMAC_VLAN1_OFFSET 0x0020 -#define EMAC_VLAN2_OFFSET 0x0024 -#define EMAC_WKUP_CTL_OFFSET 0x002c -#define EMAC_WKUP_FFMSK0_OFFSET 0x0030 -#define EMAC_WKUP_FFMSK1_OFFSET 0x0034 -#define EMAC_WKUP_FFMSK2_OFFSET 0x0038 -#define EMAC_WKUP_FFMSK3_OFFSET 0x003c -#define EMAC_WKUP_FFCMD_OFFSET 0x0040 -#define EMAC_WKUP_FFOFF_OFFSET 0x0044 -#define EMAC_WKUP_FFCRC01_OFFSET 0x0048 -#define EMAC_WKUP_FFCRC23_OFFSET 0x004c -#define EMAC_SYSCTL_OFFSET 0x0060 -#define EMAC_SYSTAT_OFFSET 0x0064 -#define EMAC_RX_STAT_OFFSET 0x0068 -#define EMAC_RX_STKY_OFFSET 0x006c -#define EMAC_RX_IRQE_OFFSET 0x0070 -#define EMAC_TX_STAT_OFFSET 0x0074 -#define EMAC_TX_STKY_OFFSET 0x0078 -#define EMAC_TX_IRQE_OFFSET 0x007c -#define EMAC_MMC_CTL_OFFSET 0x0080 -#define EMAC_MMC_RIRQS_OFFSET 0x0084 -#define EMAC_MMC_RIRQE_OFFSET 0x0088 -#define EMAC_MMC_TIRQS_OFFSET 0x008c -#define EMAC_MMC_TIRQE_OFFSET 0x0090 - -#define EMAC_RXC_OK_OFFSET 0x0100 -#define EMAC_RXC_FCS_OFFSET 0x0104 -#define EMAC_RXC_ALIGN_OFFSET 0x0108 -#define EMAC_RXC_OCTET_OFFSET 0x010c -#define EMAC_RXC_DMAOVF_OFFSET 0x0110 -#define EMAC_RXC_UNICST_OFFSET 0x0114 -#define EMAC_RXC_MULTI_OFFSET 0x0118 -#define EMAC_RXC_BROAD_OFFSET 0x011c -#define EMAC_RXC_LNERRI_OFFSET 0x0120 -#define EMAC_RXC_LNERRO_OFFSET 0x0124 -#define EMAC_RXC_LONG_OFFSET 0x0128 -#define EMAC_RXC_MACCTL_OFFSET 0x012c -#define EMAC_RXC_OPCODE_OFFSET 0x0130 -#define EMAC_RXC_PAUSE_OFFSET 0x0134 -#define EMAC_RXC_ALLFRM_OFFSET 0x0138 -#define EMAC_RXC_ALLOCT_OFFSET 0x013c -#define EMAC_RXC_TYPED_OFFSET 0x0140 -#define EMAC_RXC_SHORT_OFFSET 0x0144 -#define EMAC_RXC_EQ64_OFFSET 0x0148 -#define EMAC_RXC_LT128_OFFSET 0x014c -#define EMAC_RXC_LT256_OFFSET 0x0150 -#define EMAC_RXC_LT512_OFFSET 0x0154 -#define EMAC_RXC_LT1024_OFFSET 0x0158 -#define EMAC_RXC_GE1024_OFFSET 0x015c - -#define EMAC_TXC_OK_OFFSET 0x0180 -#define EMAC_TXC_1COL_OFFSET 0x0184 -#define EMAC_TXC_GT1COL_OFFSET 0x0188 -#define EMAC_TXC_OCTET_OFFSET 0x018c -#define EMAC_TXC_DEFER_OFFSET 0x0190 -#define EMAC_TXC_LATECL_OFFSET 0x0194 -#define EMAC_TXC_XS_COL_OFFSET 0x0198 -#define EMAC_TXC_DMAUND_OFFSET 0x019c -#define EMAC_TXC_CRSERR_OFFSET 0x01a0 -#define EMAC_TXC_UNICST_OFFSET 0x01a4 -#define EMAC_TXC_MULTI_OFFSET 0x01a8 -#define EMAC_TXC_BROAD_OFFSET 0x01ac -#define EMAC_TXC_ES_DFR_OFFSET 0x01b0 -#define EMAC_TXC_MACCTL_OFFSET 0x01b4 -#define EMAC_TXC_ALLFRM_OFFSET 0x01b8 -#define EMAC_TXC_ALLOCT_OFFSET 0x01bc -#define EMAC_TXC_EQ64_OFFSET 0x01c0 -#define EMAC_TXC_LT128_OFFSET 0x01c4 -#define EMAC_TXC_LT256_OFFSET 0x01c8 -#define EMAC_TXC_LT512_OFFSET 0x01cc -#define EMAC_TXC_LT1024_OFFSET 0x01d0 -#define EMAC_TXC_GE1024_OFFSET 0x01d4 -#define EMAC_TXC_ABORT_OFFSET 0x01d8 - - -/* register fields */ - -#define EMAC_OPMODE_DRO 0x10000000 -#define EMAC_OPMODE_LB 0x08000000 -#define EMAC_OPMODE_FDMODE 0x04000000 -#define EMAC_OPMODE_RMII_10 0x02000000 -#define EMAC_OPMODE_RMII 0x01000000 -#define EMAC_OPMODE_LCTRE 0x00800000 -#define EMAC_OPMODE_DRTY 0x00400000 -#define EMAC_OPMODE_BOLMT_MASK 0x00300000 -#define EMAC_OPMODE_BOLMT_1023 0x00000000 -#define EMAC_OPMODE_BOLMT_255 0x00100000 -#define EMAC_OPMODE_BOLMT_15 0x00200000 -#define EMAC_OPMODE_BOLMT_1 0x00300000 -#define EMAC_OPMODE_DC 0x00080000 -#define EMAC_OPMODE_DTXCRC 0x00040000 -#define EMAC_OPMODE_DTXPAD 0x00020000 -#define EMAC_OPMODE_TE 0x00010000 -#define EMAC_OPMODE_RAF 0x00001000 -#define EMAC_OPMODE_PSF 0x00000800 -#define EMAC_OPMODE_PBF 0x00000400 -#define EMAC_OPMODE_DBF 0x00000200 -#define EMAC_OPMODE_IFE 0x00000100 -#define EMAC_OPMODE_PR 0x00000080 -#define EMAC_OPMODE_PAM 0x00000040 -#define EMAC_OPMODE_HM 0x00000020 -#define EMAC_OPMODE_HU 0x00000010 -#define EMAC_OPMODE_ASTP 0x00000002 -#define EMAC_OPMODE_RE 0x00000001 - -#define EMAC_STAADD_PHYAD_MASK 0x0000f800 -#define EMAC_STAADD_PHYAD_SHIFT 11 -#define EMAC_STAADD_REGAD_MASK 0x000007c0 -#define EMAC_STAADD_REGAD_SHIFT 6 -#define EMAC_STAADD_STAIE 0x00000008 -#define EMAC_STAADD_STADISPRE 0x00000004 -#define EMAC_STAADD_STAOP 0x00000002 -#define EMAC_STAADD_STABUSY 0x00000001 - -#define EMAC_FLC_FLCPAUSE_MASK 0xffff0000 -#define EMAC_FLC_FLCPAUSE_SHIFT 16 -#define EMAC_FLC_BKPRSEN 0x00000008 -#define EMAC_FLC_PCF 0x00000004 -#define EMAC_FLC_FLCE 0x00000002 -#define EMAC_FLC_FLCBUSY 0x00000001 - -#define EMAC_WKUP_CTL_RWKS_MASK 0x00000f00 -#define EMAC_WKUP_CTL_RWKS_SHIFT 8 -#define EMAC_WKUP_CTL_MPKS 0x00000020 -#define EMAC_WKUP_CTL_GUWKE 0x00000008 -#define EMAC_WKUP_CTL_RWKE 0x00000004 -#define EMAC_WKUP_CTL_MPKE 0x00000002 -#define EMAC_WKUP_CTL_CAPWKFRM 0x00000001 - -#define EMAC_WKUP_FFCMD_3_TYPE 0x08000000 -#define EMAC_WKUP_FFCMD_3_EN 0x01000000 -#define EMAC_WKUP_FFCMD_2_TYPE 0x00080000 -#define EMAC_WKUP_FFCMD_2_EN 0x00010000 -#define EMAC_WKUP_FFCMD_1_TYPE 0x00000800 -#define EMAC_WKUP_FFCMD_1_EN 0x00000100 -#define EMAC_WKUP_FFCMD_0_TYPE 0x00000008 -#define EMAC_WKUP_FFCMD_0_EN 0x00000001 - -#define EMAC_WKUP_FFOFF_3_MASK 0xff000000 -#define EMAC_WKUP_FFOFF_3_SHIFT 24 -#define EMAC_WKUP_FFOFF_2_MASK 0x00ff0000 -#define EMAC_WKUP_FFOFF_2_SHIFT 16 -#define EMAC_WKUP_FFOFF_1_MASK 0x0000ff00 -#define EMAC_WKUP_FFOFF_1_SHIFT 8 -#define EMAC_WKUP_FFOFF_0_MASK 0x000000ff -#define EMAC_WKUP_FFOFF_0_SHIFT 0 - -#define EMAC_WKUP_FFCRC01_1_MASK 0xffff0000 -#define EMAC_WKUP_FFCRC01_1_SHIFT 16 -#define EMAC_WKUP_FFCRC01_0_MASK 0x0000ffff -#define EMAC_WKUP_FFCRC01_0_SHIFT 0 - -#define EMAC_WKUP_FFCRC23_3_MASK 0xffff0000 -#define EMAC_WKUP_FFCRC23_3_SHIFT 16 -#define EMAC_WKUP_FFCRC23_2_MASK 0x0000ffff -#define EMAC_WKUP_FFCRC23_2_SHIFT 0 - -#define EMAC_SYSCTL_MDCDIV_MASK 0x00003f00 -#define EMAC_SYSCTL_MDCDIV_SHIFT 8 -#define EMAC_SYSCTL_TXDWA 0x00000010 -#define EMAC_SYSCTL_RXCKS 0x00000004 -#define EMAC_SYSCTL_RXDWA 0x00000002 -#define EMAC_SYSCTL_PHYIE 0x00000001 - -#define EMAC_SYSTAT_STMDONE 0x00000080 -#define EMAC_SYSTAT_TXDMAERR 0x00000040 -#define EMAC_SYSTAT_RXDMAERR 0x00000020 -#define EMAC_SYSTAT_WAKEDET 0x00000010 -#define EMAC_SYSTAT_TXFSINT 0x00000008 -#define EMAC_SYSTAT_RXFSINT 0x00000004 -#define EMAC_SYSTAT_MMCINT 0x00000002 -#define EMAC_SYSTAT_PHYINT 0x00000001 - -#define EMAC_RX_STAT_RX_ACCEPT 0x80000000 -#define EMAC_RX_STAT_RX_VLAN2 0x40000000 -#define EMAC_RX_STAT_RX_VLAN1 0x20000000 -#define EMAC_RX_STAT_RX_TYPE 0x10000000 -#define EMAC_RX_STAT_RX_UCTL 0x08000000 -#define EMAC_RX_STAT_RX_CTL 0x04000000 -#define EMAC_RX_STAT_RX_BROAD_MULTI_MASK 0x03000000 -#define EMAC_RX_STAT_RX_BROAD_MULTI_ILLEGAL 0x03000000 -#define EMAC_RX_STAT_RX_BROAD_MULTI_BROADCAST 0x02000000 -#define EMAC_RX_STAT_RX_BROAD_MULTI_GROUP 0x01000000 -#define EMAC_RX_STAT_RX_BROAD_MULTI_UNICAST 0x00000000 -#define EMAC_RX_STAT_RX_RANGE 0x00800000 -#define EMAC_RX_STAT_RX_LATE 0x00400000 -#define EMAC_RX_STAT_RX_PHY 0x00200000 -#define EMAC_RX_STAT_RX_DMAO 0x00100000 -#define EMAC_RX_STAT_RX_ADDR 0x00080000 -#define EMAC_RX_STAT_RX_FRAG 0x00040000 -#define EMAC_RX_STAT_RX_LEN 0x00020000 -#define EMAC_RX_STAT_RX_CRC 0x00010000 -#define EMAC_RX_STAT_RX_ALIGN 0x00008000 -#define EMAC_RX_STAT_RX_LONG 0x00004000 -#define EMAC_RX_STAT_RX_OK 0x00002000 -#define EMAC_RX_STAT_RX_COMP 0x00001000 -#define EMAC_RX_STAT_RX_FRLEN_MASK 0x000007ff -#define EMAC_RX_STAT_RX_FRLEN_SHIFT 0 - -#define EMAC_RX_STKY_RX_ACCEPT 0x80000000 -#define EMAC_RX_STKY_RX_VLAN2 0x40000000 -#define EMAC_RX_STKY_RX_VLAN1 0x20000000 -#define EMAC_RX_STKY_RX_TYPE 0x10000000 -#define EMAC_RX_STKY_RX_UCTL 0x08000000 -#define EMAC_RX_STKY_RX_CTL 0x04000000 -#define EMAC_RX_STKY_RX_BROAD 0x02000000 -#define EMAC_RX_STKY_RX_MULTI 0x01000000 -#define EMAC_RX_STKY_RX_RANGE 0x00800000 -#define EMAC_RX_STKY_RX_LATE 0x00400000 -#define EMAC_RX_STKY_RX_PHY 0x00200000 -#define EMAC_RX_STKY_RX_DMAO 0x00100000 -#define EMAC_RX_STKY_RX_ADDR 0x00080000 -#define EMAC_RX_STKY_RX_FRAG 0x00040000 -#define EMAC_RX_STKY_RX_LEN 0x00020000 -#define EMAC_RX_STKY_RX_CRC 0x00010000 -#define EMAC_RX_STKY_RX_ALIGN 0x00008000 -#define EMAC_RX_STKY_RX_LONG 0x00004000 -#define EMAC_RX_STKY_RX_OK 0x00002000 -#define EMAC_RX_STKY_RX_COMP 0x00001000 - -#define EMAC_RX_IRQE_RX_ACCEPT 0x80000000 -#define EMAC_RX_IRQE_RX_VLAN2 0x40000000 -#define EMAC_RX_IRQE_RX_VLAN1 0x20000000 -#define EMAC_RX_IRQE_RX_TYPE 0x10000000 -#define EMAC_RX_IRQE_RX_UCTL 0x08000000 -#define EMAC_RX_IRQE_RX_CTL 0x04000000 -#define EMAC_RX_IRQE_RX_BROAD 0x02000000 -#define EMAC_RX_IRQE_RX_MULTI 0x01000000 -#define EMAC_RX_IRQE_RX_RANGE 0x00800000 -#define EMAC_RX_IRQE_RX_LATE 0x00400000 -#define EMAC_RX_IRQE_RX_PHY 0x00200000 -#define EMAC_RX_IRQE_RX_DMAO 0x00100000 -#define EMAC_RX_IRQE_RX_ADDR 0x00080000 -#define EMAC_RX_IRQE_RX_FRAG 0x00040000 -#define EMAC_RX_IRQE_RX_LEN 0x00020000 -#define EMAC_RX_IRQE_RX_CRC 0x00010000 -#define EMAC_RX_IRQE_RX_ALIGN 0x00008000 -#define EMAC_RX_IRQE_RX_LONG 0x00004000 -#define EMAC_RX_IRQE_RX_OK 0x00002000 -#define EMAC_RX_IRQE_RX_COMP 0x00001000 - -#define EMAC_TX_STAT_TX_FRLEN_MASK 0x07ff0000 -#define EMAC_TX_STAT_TX_FRLEN_SHIFT 16 -#define EMAC_TX_STAT_TX_RETRY 0x00008000 -#define EMAC_TX_STAT_TX_LOSS 0x00004000 -#define EMAC_TX_STAT_TX_CRS 0x00002000 -#define EMAC_TX_STAT_TX_DEFER 0x00001000 -#define EMAC_TX_STAT_TX_CCNT_MASK 0x00000f00 -#define EMAC_TX_STAT_TX_CCNT_SHIFT 8 -#define EMAC_TX_STAT_TX_MULTI_BROAD_MASK 0x000000c0 -#define EMAC_TX_STAT_TX_MULTI_BROAD_ILLEGAL 0x000000c0 -#define EMAC_TX_STAT_TX_MULTI_BROAD_GROUP 0x00000080 -#define EMAC_TX_STAT_TX_MULTI_BROAD_BROADCAST 0x00000040 -#define EMAC_TX_STAT_TX_MULTI_BROAD_UNICAST 0x00000000 -#define EMAC_TX_STAT_TX_EDEFER 0x00000020 -#define EMAC_TX_STAT_TX_DMAU 0x00000010 -#define EMAC_TX_STAT_TX_LATE 0x00000008 -#define EMAC_TX_STAT_TX_ECOLL 0x00000004 -#define EMAC_TX_STAT_TX_OK 0x00000002 -#define EMAC_TX_STAT_TX_COMP 0x00000001 - -#define EMAC_TX_STKY_TX_RETRY 0x00008000 -#define EMAC_TX_STKY_TX_LOSS 0x00004000 -#define EMAC_TX_STKY_TX_CRS 0x00002000 -#define EMAC_TX_STKY_TX_DEFER 0x00001000 -#define EMAC_TX_STKY_TX_CCNT_MASK 0x00000f00 -#define EMAC_TX_STKY_TX_CCNT_SHIFT 8 -#define EMAC_TX_STKY_TX_MULTI 0x00000080 -#define EMAC_TX_STKY_TX_BROAD 0x00000040 -#define EMAC_TX_STKY_TX_EDEFER 0x00000020 -#define EMAC_TX_STKY_TX_DMAU 0x00000010 -#define EMAC_TX_STKY_TX_LATE 0x00000008 -#define EMAC_TX_STAT_TX_ECOLL 0x00000004 -#define EMAC_TX_STAT_TX_OK 0x00000002 -#define EMAC_TX_STAT_TX_COMP 0x00000001 - -#define EMAC_TX_IRQE_TX_RETRY 0x00008000 -#define EMAC_TX_IRQE_TX_LOSS 0x00004000 -#define EMAC_TX_IRQE_TX_CRS 0x00002000 -#define EMAC_TX_IRQE_TX_DEFER 0x00001000 -#define EMAC_TX_IRQE_TX_CCNT_MASK 0x00000f00 -#define EMAC_TX_IRQE_TX_CCNT_SHIFT 8 -#define EMAC_TX_IRQE_TX_MULTI 0x00000080 -#define EMAC_TX_IRQE_TX_BROAD 0x00000040 -#define EMAC_TX_IRQE_TX_EDEFER 0x00000020 -#define EMAC_TX_IRQE_TX_DMAU 0x00000010 -#define EMAC_TX_IRQE_TX_LATE 0x00000008 -#define EMAC_TX_IRQE_TX_ECOLL 0x00000004 -#define EMAC_TX_IRQE_TX_OK 0x00000002 -#define EMAC_TX_IRQE_TX_COMP 0x00000001 - -#define EMAC_MMC_RIRQS_RX_GE1024_CNT 0x00800000 -#define EMAC_MMC_RIRQS_RX_LT1024_CNT 0x00400000 -#define EMAC_MMC_RIRQS_RX_LT512_CNT 0x00200000 -#define EMAC_MMC_RIRQS_RX_LT256_CNT 0x00100000 -#define EMAC_MMC_RIRQS_RX_LT128_CNT 0x00080000 -#define EMAC_MMC_RIRQS_RX_EQ64_CNT 0x00040000 -#define EMAC_MMC_RIRQS_RX_SHORT_CNT 0x00020000 -#define EMAC_MMC_RIRQS_RX_TYPED_CNT 0x00010000 -#define EMAC_MMC_RIRQS_RX_ALLO_CNT 0x00008000 -#define EMAC_MMC_RIRQS_RX_ALLF_CNT 0x00004000 -#define EMAC_MMC_RIRQS_RX_PAUSE_CNT 0x00002000 -#define EMAC_MMC_RIRQS_RX_OPCODE_CNT 0x00001000 -#define EMAC_MMC_RIRQS_RX_MACCTL_CNT 0x00000800 -#define EMAC_MMC_RIRQS_RX_LONG_CNT 0x00000400 -#define EMAC_MMC_RIRQS_RX_ORL_CNT 0x00000200 -#define EMAC_MMC_RIRQS_RX_IRL_CNT 0x00000100 -#define EMAC_MMC_RIRQS_RX_BROAD_CNT 0x00000080 -#define EMAC_MMC_RIRQS_RX_MULTI_CNT 0x00000040 -#define EMAC_MMC_RIRQS_RX_UNI_CNT 0x00000020 -#define EMAC_MMC_RIRQS_RX_LOST_CNT 0x00000010 -#define EMAC_MMC_RIRQS_RX_OCTET_CNT 0x00000008 -#define EMAC_MMC_RIRQS_RX_ALIGN_CNT 0x00000004 -#define EMAC_MMC_RIRQS_RX_FCS_CNT 0x00000002 -#define EMAC_MMC_RIRQS_RX_OK_CNT 0x00000001 - -#define EMAC_MMC_RIRQE_RX_GE1024_CNT 0x00800000 -#define EMAC_MMC_RIRQE_RX_LT1024_CNT 0x00400000 -#define EMAC_MMC_RIRQE_RX_LT512_CNT 0x00200000 -#define EMAC_MMC_RIRQE_RX_LT256_CNT 0x00100000 -#define EMAC_MMC_RIRQE_RX_LT128_CNT 0x00080000 -#define EMAC_MMC_RIRQE_RX_EQ64_CNT 0x00040000 -#define EMAC_MMC_RIRQE_RX_SHORT_CNT 0x00020000 -#define EMAC_MMC_RIRQE_RX_TYPED_CNT 0x00010000 -#define EMAC_MMC_RIRQE_RX_ALLO_CNT 0x00008000 -#define EMAC_MMC_RIRQE_RX_ALLF_CNT 0x00004000 -#define EMAC_MMC_RIRQE_RX_PAUSE_CNT 0x00002000 -#define EMAC_MMC_RIRQE_RX_OPCODE_CNT 0x00001000 -#define EMAC_MMC_RIRQE_RX_MACCTL_CNT 0x00000800 -#define EMAC_MMC_RIRQE_RX_LONG_CNT 0x00000400 -#define EMAC_MMC_RIRQE_RX_ORL_CNT 0x00000200 -#define EMAC_MMC_RIRQE_RX_IRL_CNT 0x00000100 -#define EMAC_MMC_RIRQE_RX_BROAD_CNT 0x00000080 -#define EMAC_MMC_RIRQE_RX_MULTI_CNT 0x00000040 -#define EMAC_MMC_RIRQE_RX_UNI_CNT 0x00000020 -#define EMAC_MMC_RIRQE_RX_LOST_CNT 0x00000010 -#define EMAC_MMC_RIRQE_RX_OCTET_CNT 0x00000008 -#define EMAC_MMC_RIRQE_RX_ALIGN_CNT 0x00000004 -#define EMAC_MMC_RIRQE_RX_FCS_CNT 0x00000002 -#define EMAC_MMC_RIRQE_RX_OK_CNT 0x00000001 - -#define EMAC_MMC_TIRQS_TX_ABORT_CNT 0x00400000 -#define EMAC_MMC_TIRQS_TX_GE1024_CNT 0x00200000 -#define EMAC_MMC_TIRQS_TX_LT1024_CNT 0x00100000 -#define EMAC_MMC_TIRQS_TX_LT512_CNT 0x00080000 -#define EMAC_MMC_TIRQS_TX_LT256_CNT 0x00040000 -#define EMAC_MMC_TIRQS_TX_LT128_CNT 0x00020000 -#define EMAC_MMC_TIRQS_TX_EQ64_CNT 0x00010000 -#define EMAC_MMC_TIRQS_TX_ALLO_CNT 0x00008000 -#define EMAC_MMC_TIRQS_TX_ALLF_CNT 0x00004000 -#define EMAC_MMC_TIRQS_TX_MACCTL_CNT 0x00002000 -#define EMAC_MMC_TIRQS_TX_EXDEF_CNT 0x00001000 -#define EMAC_MMC_TIRQS_TX_BROAD_CNT 0x00000800 -#define EMAC_MMC_TIRQS_TX_MULTI_CNT 0x00000400 -#define EMAC_MMC_TIRQS_TX_UNI_CNT 0x00000200 -#define EMAC_MMC_TIRQS_TX_CRS_CNT 0x00000100 -#define EMAC_MMC_TIRQS_TX_LOST_CNT 0x00000080 -#define EMAC_MMC_TIRQS_TX_ABORTC_CNT 0x00000040 -#define EMAC_MMC_TIRQS_TX_LATE_CNT 0x00000020 -#define EMAC_MMC_TIRQS_TX_DEFER_CNT 0x00000010 -#define EMAC_MMC_TIRQS_TX_OCTET_CNT 0x00000008 -#define EMAC_MMC_TIRQS_TX_MCOLL_CNT 0x00000004 -#define EMAC_MMC_TIRQS_TX_SCOLL_CNT 0x00000002 -#define EMAC_MMC_TIRQS_TX_OK_CNT 0x00000001 - -#define EMAC_MMC_TIRQE_TX_ABORT_CNT 0x00400000 -#define EMAC_MMC_TIRQE_TX_GE1024_CNT 0x00200000 -#define EMAC_MMC_TIRQE_TX_LT1024_CNT 0x00100000 -#define EMAC_MMC_TIRQE_TX_LT512_CNT 0x00080000 -#define EMAC_MMC_TIRQE_TX_LT256_CNT 0x00040000 -#define EMAC_MMC_TIRQE_TX_LT128_CNT 0x00020000 -#define EMAC_MMC_TIRQE_TX_EQ64_CNT 0x00010000 -#define EMAC_MMC_TIRQE_TX_ALLO_CNT 0x00008000 -#define EMAC_MMC_TIRQE_TX_ALLF_CNT 0x00004000 -#define EMAC_MMC_TIRQE_TX_MACCTL_CNT 0x00002000 -#define EMAC_MMC_TIRQE_TX_EXDEF_CNT 0x00001000 -#define EMAC_MMC_TIRQE_TX_BROAD_CNT 0x00000800 -#define EMAC_MMC_TIRQE_TX_MULTI_CNT 0x00000400 -#define EMAC_MMC_TIRQE_TX_UNI_CNT 0x00000200 -#define EMAC_MMC_TIRQE_TX_CRS_CNT 0x00000100 -#define EMAC_MMC_TIRQE_TX_LOST_CNT 0x00000080 -#define EMAC_MMC_TIRQE_TX_ABORTC_CNT 0x00000040 -#define EMAC_MMC_TIRQE_TX_LATE_CNT 0x00000020 -#define EMAC_MMC_TIRQE_TX_DEFER_CNT 0x00000010 -#define EMAC_MMC_TIRQE_TX_OCTET_CNT 0x00000008 -#define EMAC_MMC_TIRQE_TX_MCOLL_CNT 0x00000004 -#define EMAC_MMC_TIRQE_TX_SCOLL_CNT 0x00000002 -#define EMAC_MMC_TIRQE_TX_OK_CNT 0x00000001 - -#define EMAC_MMC_CTL_MMCE 0x00000008 -#define EMAC_MMC_CTL_CCOR 0x00000004 -#define EMAC_MMC_CTL_CROLL 0x00000002 -#define EMAC_MMC_CTL_RSTC 0x00000001 - - -#endif /* _ethernetRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/gpioRegs.h b/c/src/lib/libcpu/bfin/include/gpioRegs.h deleted file mode 100644 index 02862916e1..0000000000 --- a/c/src/lib/libcpu/bfin/include/gpioRegs.h +++ /dev/null @@ -1,36 +0,0 @@ -/* Blackfin GPIO Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _gpioRegs_h_ -#define _gpioRegs_h_ - - -/* register addresses */ - -#define PORTIO_OFFSET 0x0000 -#define PORTIO_CLEAR_OFFSET 0x0004 -#define PORTIO_SET_OFFSET 0x0008 -#define PORTIO_TOGGLE_OFFSET 0x000c -#define PORTIO_MASKA_OFFSET 0x0010 -#define PORTIO_MASKA_CLEAR_OFFSET 0x0014 -#define PORTIO_MASKA_SET_OFFSET 0x0018 -#define PORTIO_MASKA_TOGGLE_OFFSET 0x001c -#define PORTIO_MASKB_OFFSET 0x0020 -#define PORTIO_MASKB_CLEAR_OFFSET 0x0024 -#define PORTIO_MASKB_SET_OFFSET 0x0028 -#define PORTIO_MASKB_TOGGLE_OFFSET 0x002c -#define PORTIO_DIR_OFFSET 0x0030 -#define PORTIO_POLAR_OFFSET 0x0034 -#define PORTIO_EDGE_OFFSET 0x0038 -#define PORTIO_BOTH_OFFSET 0x003c -#define PORTIO_INEN_OFFSET 0x0040 - - -#endif /* _gpioRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/memoryRegs.h b/c/src/lib/libcpu/bfin/include/memoryRegs.h deleted file mode 100644 index 130235e3d1..0000000000 --- a/c/src/lib/libcpu/bfin/include/memoryRegs.h +++ /dev/null @@ -1,58 +0,0 @@ -/* Blackfin Memory Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _memoryRegs_h_ -#define _memoryRegs_h_ - -/* register addresses */ -#define DMEM_CONTROL 0xffe00004 -#define DTEST_COMMAND 0xffe00300 -#define DTEST_DATA0 0xffe00400 -#define DTEST_DATA1 0xffe00404 - -#define IMEM_CONTROL 0xffe01004 - - -/* register fields */ -#define DMEM_CONTROL_PORT_PREF1 0x00002000 -#define DMEM_CONTROL_PORT_PREF0 0x00001000 -#define DMEM_CONTROL_DCBS 0x00000010 -#define DMEM_CONTROL_DMC_MASK 0x0000000c -#define DMEM_CONTROL_DMC_SHIFT 2 -#define DMEM_CONTROL_ENDCPLB 0x00000002 - -#define DTEST_COMMAND_ACCESS_WAY1 0x02000000 -#define DTEST_COMMAND_ACCESS_INSTRUCTION 0x01000000 -#define DTEST_COMMAND_ACCESS_BANKB 0x00800000 -#define DTEST_COMMAND_SRAM_ADDR_13_12_MASK 0x00030000 -#define DTEST_COMMAND_SRAM_ADDR_13_12_SHIFT 16 -#define DTEST_COMMAND_DATA_CACHE_SELECT 0x00004000 -#define DTEST_COMMAND_SET_INDEX_MASK 0x000007e0 -#define DTEST_COMMAND_SET_INDEX_SHIFT 5 -#define DTEST_COMMAND_DOUBLE_WORD_INDEX_MASK 0x00000018 -#define DTEST_COMMAND_DOUBLE_WORD_INDEX_SHIFT 3 -#define DTEST_COMMAND_ACCESS_DATA_ARRAY 0x00000004 -#define DTEST_COMMAND_WRITE_ACCESS 0x00000002 - -#define DTEST_DATA0_TAG_19_2_MASK 0xffffc000 -#define DTEST_DATA0_TAG_19_2_SHIFT 14 -#define DTEST_DATA0_TAG 0x00000800 -#define DTEST_DATA0_LRU 0x00000004 -#define DTEST_DATA0_DIRTY 0x00000002 -#define DTEST_DATA0_VALID 0x00000001 - -#define IMEM_CONTROL_LRUPRIORST 0x00002000 -#define IMEM_CONTROL_ILOC_MASK 0x00000078 -#define IMEM_CONTROL_ILOC_SHIFT 3 -#define IMEM_CONTROL_IMC 0x00000004 -#define IMEM_CONTROL_ENICPLB 0x00000002 - - -#endif /* _memoryRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/mmuRegs.h b/c/src/lib/libcpu/bfin/include/mmuRegs.h deleted file mode 100644 index 271ef4dcf5..0000000000 --- a/c/src/lib/libcpu/bfin/include/mmuRegs.h +++ /dev/null @@ -1,54 +0,0 @@ -/* Blackfin MMU Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _mmuRegs_h_ -#define _mmuRegs_h_ - -/* register addresses */ -#define DCPLB_ADDR0 0xffe00100 -#define DCPLB_DATA0 0xffe00200 -#define DCPLB_COUNT 16 -#define DCPLB_ADDR_PITCH 4 -#define DCPLB_DATA_PITCH 4 -#define ICPLB_ADDR0 0xffe01100 -#define ICPLB_DATA0 0xffe01200 -#define ICPLB_COUNT 16 -#define ICPLB_ADDR_PITCH 4 -#define ICPLB_DATA_PITCH 4 - - -/* register fields */ -#define DCPLB_DATA_PAGE_SIZE_MASK 0x00030000 -#define DCPLB_DATA_PAGE_SIZE_1KB 0x00000000 -#define DCPLB_DATA_PAGE_SIZE_4KB 0x00010000 -#define DCPLB_DATA_PAGE_SIZE_1MB 0x00020000 -#define DCPLB_DATA_PAGE_SIZE_4MB 0x00030000 -#define DCPLB_DATA_CPLB_L1_AOW 0x00008000 -#define DCPLB_DATA_CPLB_WT 0x00004000 -#define DCPLB_DATA_CPLB_L1_CHBL 0x00001000 -#define DCPLB_DATA_CPLB_DIRTY 0x00000080 -#define DCPLB_DATA_CPLB_SUPV_WR 0x00000010 -#define DCPLB_DATA_CPLB_USER_WR 0x00000008 -#define DCPLB_DATA_CPLB_USER_RD 0x00000004 -#define DCPLB_DATA_CPLB_LOCK 0x00000002 -#define DCPLB_DATA_CPLB_VALID 0x00000001 - -#define ICPLB_DATA_PAGE_SIZE_MASK 0x00030000 -#define ICPLB_DATA_PAGE_SIZE_1KB 0x00000000 -#define ICPLB_DATA_PAGE_SIZE_4KB 0x00010000 -#define ICPLB_DATA_PAGE_SIZE_1MB 0x00020000 -#define ICPLB_DATA_PAGE_SIZE_4MB 0x00030000 -#define ICPLB_DATA_CPLB_L1_CHBL 0x00001000 -#define ICPLB_DATA_CPLB_LRUPRIO 0x00000100 -#define ICPLB_DATA_CPLB_USER_RD 0x00000004 -#define ICPLB_DATA_CPLB_LOCK 0x00000002 -#define ICPLB_DATA_CPLB_VALID 0x00000001 - -#endif /* _mmuRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/ppiRegs.h b/c/src/lib/libcpu/bfin/include/ppiRegs.h deleted file mode 100644 index 0ff301aefc..0000000000 --- a/c/src/lib/libcpu/bfin/include/ppiRegs.h +++ /dev/null @@ -1,58 +0,0 @@ -/* Blackfin Parallel Peripheral Interface Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _ppiRegs_h_ -#define _ppiRegs_h_ - - -/* register addresses */ - -#define PPI_CONTROL_OFFSET 0x0000 -#define PPI_STATUS_OFFSET 0x0004 -#define PPI_COUNT_OFFSET 0x0008 -#define PPI_DELAY_OFFSET 0x000c -#define PPI_FRAME_OFFSET 0x0010 - - -/* register fields */ - -#define PPI_CONTROL_POLS 0x8000 -#define PPI_CONTROL_POLC 0x4000 -#define PPI_CONTROL_DLEN_MASK 0x3800 -#define PPI_CONTROL_DLEN_8 0x0000 -#define PPI_CONTROL_DLEN_10 0x0800 -#define PPI_CONTROL_DLEN_11 0x1000 -#define PPI_CONTROL_DLEN_12 0x1800 -#define PPI_CONTROL_DLEN_13 0x2000 -#define PPI_CONTROL_DLEN_14 0x2800 -#define PPI_CONTROL_DLEN_15 0x3000 -#define PPI_CONTROL_DLEN_16 0x3800 -#define PPI_CONTROL_SKIP_EO 0x0400 -#define PPI_CONTROL_SKIP_EN 0x0200 -#define PPI_CONTROL_PACK_EN 0x0080 -#define PPI_CONTROL_FLD_SEL 0x0040 -#define PPI_CONTROL_PORT_CFG_MASK 0x0030 -#define PPI_CONTROL_PORT_CFG_SHIFT 4 -#define PPI_CONTROL_XFR_TYPE_MASK 0x000c -#define PPI_CONTROL_XFR_TYPE_SHIFT 2 -#define PPI_CONTROL_PORT_DIR 0x0002 -#define PPI_CONTROL_PORT_EN 0x0001 - -#define PPI_STATUS_ERR_NCOR 0x8000 -#define PPI_STATUS_ERR_DET 0x4000 -#define PPI_STATUS_UNDR 0x2000 -#define PPI_STATUS_OVR 0x1000 -#define PPI_STATUS_FT_ERR 0x0800 -#define PPI_STATUS_FLD 0x0400 -#define PPI_STATUS_LT_ERR_UNDR 0x0200 -#define PPI_STATUS_LT_ERR_OVR 0x0100 - - -#endif /* _ppiRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/rtcRegs.h b/c/src/lib/libcpu/bfin/include/rtcRegs.h deleted file mode 100644 index 09245c2b91..0000000000 --- a/c/src/lib/libcpu/bfin/include/rtcRegs.h +++ /dev/null @@ -1,65 +0,0 @@ -/* Blackfin RTC Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _rtcRegs_h_ -#define _rtcRegs_h_ - -/* register addresses */ - -#define RTC_STAT (RTC_BASE_ADDRESS + 0x0000) -#define RTC_ICTL (RTC_BASE_ADDRESS + 0x0004) -#define RTC_ISTAT (RTC_BASE_ADDRESS + 0x0008) -#define RTC_SWCNT (RTC_BASE_ADDRESS + 0x000c) -#define RTC_ALARM (RTC_BASE_ADDRESS + 0x0010) -#define RTC_PREN (RTC_BASE_ADDRESS + 0x0014) - - -/* register fields */ - -#define RTC_STAT_DAYS_MASK 0xfffe0000 -#define RTC_STAT_DAYS_SHIFT 17 -#define RTC_STAT_HOURS_MASK 0x0001f000 -#define RTC_STAT_HOURS_SHIFT 12 -#define RTC_STAT_MINUTES_MASK 0x00000fc0 -#define RTC_STAT_MINUTES_SHIFT 6 -#define RTC_STAT_SECONDS_MASK 0x0000003f -#define RTC_STAT_SECONDS_SHIFT 0 - -#define RTC_ICTL_WCIE 0x8000 -#define RTC_ICTL_DAIE 0x0040 -#define RTC_ICTL_24HIE 0x0020 -#define RTC_ICTL_HIE 0x0010 -#define RTC_ICTL_MIE 0x0008 -#define RTC_ICTL_SIE 0x0004 -#define RTC_ICTL_AIE 0x0002 -#define RTC_ICTL_SWIE 0x0001 - -#define RTC_ISTAT_WC 0x8000 -#define RTC_ISTAT_WP 0x4000 -#define RTC_ISTAT_DAEF 0x0040 -#define RTC_ISTAT_24HE 0x0020 -#define RTC_ISTAT_HEF 0x0010 -#define RTC_ISTAT_MEF 0x0008 -#define RTC_ISTAT_SEF 0x0004 -#define RTC_ISTAT_AEF 0x0002 -#define RTC_ISTAT_SWEF 0x0001 - -#define RTC_ALARM_DAYS_MASK 0xfff70000 -#define RTC_ALARM_DAYS_SHIFT 17 -#define RTC_ALARM_HOURS_MASK 0x0001f000 -#define RTC_ALARM_HOURS_SHIFT 12 -#define RTC_ALARM_MINUTES_MASK 0x00000fc0 -#define RTC_ALARM_MINUTES_SHIFT 10 -#define RTC_ALARM_SECONDS_MASK 0x0000003f -#define RTC_ALARM_SECONDS_SHIFT 0 - -#define RTC_PREN_PREN 0x0001 - -#endif /* _rtcRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/sicRegs.h b/c/src/lib/libcpu/bfin/include/sicRegs.h deleted file mode 100644 index 79fdd0d77c..0000000000 --- a/c/src/lib/libcpu/bfin/include/sicRegs.h +++ /dev/null @@ -1,43 +0,0 @@ -/* Blackfin System Interrupt Controller Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sicRegs_h_ -#define _sicRegs_h_ - -/* register addresses */ - -#define SIC_IMASK (SIC_BASE_ADDRESS + 0x000c) -#define SIC_IMASK_PITCH (0x40) - -#define SIC_ISR (SIC_BASE_ADDRESS + 0x0020) -#define SIC_ISR_PITCH (0x40) - -#define SIC_IAR_BASE_ADDRESS (SIC_BASE_ADDRESS + 0x0010) -#define SIC_IAR_PITCH 0x04 - -#define SIC_IAR0 (SIC_BASE_ADDRESS + 0x0010) -#if SIC_IAR_COUNT > 1 -#define SIC_IAR1 (SIC_BASE_ADDRESS + 0x0014) -#endif -#if SIC_IAR_COUNT > 2 -#define SIC_IAR2 (SIC_BASE_ADDRESS + 0x0018) -#endif -#if SIC_IAR_COUNT > 3 -#define SIC_IAR3 (SIC_BASE_ADDRESS + 0x001c) -#endif - -#define SIC_IWR (SIC_BASE_ADDRESS + 0x0024) - - -/* register fields */ - - - -#endif /* _sicRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/spiRegs.h b/c/src/lib/libcpu/bfin/include/spiRegs.h deleted file mode 100644 index dcf792bb69..0000000000 --- a/c/src/lib/libcpu/bfin/include/spiRegs.h +++ /dev/null @@ -1,69 +0,0 @@ -/* Blackfin SPI Registers - * - * Copyright (c) 2010 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _spiRegs_h_ -#define _spiRegs_h_ - - -/* register addresses */ - -#define SPI_CTL_OFFSET 0x0000 -#define SPI_FLG_OFFSET 0x0004 -#define SPI_STAT_OFFSET 0x0008 -#define SPI_TDBR_OFFSET 0x000c -#define SPI_RDBR_OFFSET 0x0010 -#define SPI_BAUD_OFFSET 0x0014 -#define SPI_SHADOW_OFFSET 0x0018 - - -/* register fields */ - -#define SPI_CTL_SPE 0x4000 -#define SPI_CTL_WOM 0x2000 -#define SPI_CTL_MSTR 0x1000 -#define SPI_CTL_CPOL 0x0800 -#define SPI_CTL_CPHA 0x0400 -#define SPI_CTL_LSBF 0x0200 -#define SPI_CTL_SIZE 0x0100 -#define SPI_CTL_EMISO 0x0020 -#define SPI_CTL_PSSE 0x0010 -#define SPI_CTL_GM 0x0008 -#define SPI_CTL_SZ 0x0004 -#define SPI_CTL_TIMOD_MASK 0x0003 -#define SPI_CTL_TIMOD_RDBR 0x0000 -#define SPI_CTL_TIMOD_TDBR 0x0001 -#define SPI_CTL_TIMOD_DMA_RDBR 0x0002 -#define SPI_CTL_TIMOD_DMA_TDBR 0x0003 - -#define SPI_FLG_FLG7 0x8000 -#define SPI_FLG_FLG6 0x4000 -#define SPI_FLG_FLG5 0x2000 -#define SPI_FLG_FLG4 0x1000 -#define SPI_FLG_FLG3 0x0800 -#define SPI_FLG_FLG2 0x0400 -#define SPI_FLG_FLG1 0x0200 -#define SPI_FLG_FLS7 0x0080 -#define SPI_FLG_FLS6 0x0040 -#define SPI_FLG_FLS5 0x0020 -#define SPI_FLG_FLS4 0x0010 -#define SPI_FLG_FLS3 0x0008 -#define SPI_FLG_FLS2 0x0004 -#define SPI_FLG_FLS1 0x0002 - -#define SPI_STAT_TXCOL 0x0040 -#define SPI_STAT_RXS 0x0020 -#define SPI_STAT_RBSY 0x0010 -#define SPI_STAT_TXS 0x0008 -#define SPI_STAT_TXE 0x0004 -#define SPI_STAT_MODF 0x0002 -#define SPI_STAT_SPIF 0x0001 - - -#endif /* _spiRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/sportRegs.h b/c/src/lib/libcpu/bfin/include/sportRegs.h deleted file mode 100644 index f9f263b024..0000000000 --- a/c/src/lib/libcpu/bfin/include/sportRegs.h +++ /dev/null @@ -1,111 +0,0 @@ -/* Blackfin SPORT Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sportRegs_h_ -#define _sportRegs_h_ - - -/* register addresses */ - -#define SPORT_TCR1_OFFSET 0x0000 -#define SPORT_TCR2_OFFSET 0x0004 -#define SPORT_TCLKDIV_OFFSET 0x0008 -#define SPORT_TFSDIV_OFFSET 0x000c -#define SPORT_TX_OFFSET 0x0010 -#define SPORT_RX_OFFSET 0x0018 -#define SPORT_RCR1_OFFSET 0x0020 -#define SPORT_RCR2_OFFSET 0x0024 -#define SPORT_RCLKDIV_OFFSET 0x0028 -#define SPORT_RFSDIV_OFFSET 0x002c -#define SPORT_STAT_OFFSET 0x0030 -#define SPORT_CHNL_OFFSET 0x0034 -#define SPORT_MCMC1_OFFSET 0x0038 -#define SPORT_MCMC2_OFFSET 0x003c -#define SPORT_MTCS0_OFFSET 0x0040 -#define SPORT_MTCS1_OFFSET 0x0044 -#define SPORT_MTCS2_OFFSET 0x0048 -#define SPORT_MTCS3_OFFSET 0x004c -#define SPORT_MRCS0_OFFSET 0x0050 -#define SPORT_MRCS1_OFFSET 0x0054 -#define SPORT_MRCS2_OFFSET 0x0058 -#define SPORT_MRCS3_OFFSET 0x005c - - -/* register fields */ - -#define SPORT_TCR1_TCKFE 0x4000 -#define SPORT_TCR1_LATFS 0x2000 -#define SPORT_TCR1_LTFS 0x1000 -#define SPORT_TCR1_DITFS 0x0800 -#define SPORT_TCR1_TFSR 0x0400 -#define SPORT_TCR1_ITFS 0x0200 -#define SPORT_TCR1_TLSBIT 0x0010 -#define SPORT_TCR1_TDTYPE_MASK 0x000c -#define SPORT_TCR1_TDTYPE_NORMAL 0x0000 -#define SPORT_TCR1_TDTYPE_ULAW 0x0008 -#define SPORT_TCR1_TDTYPE_ALAW 0x000c -#define SPORT_TCR1_ITCLK 0x0002 -#define SPORT_TCR1_TSPEN 0x0001 - -#define SPORT_TCR2_TRFST 0x0400 -#define SPORT_TCR2_TSFSE 0x0200 -#define SPORT_TCR2_TXSE 0x0100 -#define SPORT_TCR2_SLEN_MASK 0x001f -#define SPORT_TCR2_SLEN_SHIFT 0 - -#define SPORT_RCR1_RCKFE 0x4000 -#define SPORT_RCR1_LARFS 0x2000 -#define SPORT_RCR1_LRFS 0x1000 -#define SPORT_RCR1_RFSR 0x0400 -#define SPORT_RCR1_IRFS 0x0200 -#define SPORT_RCR1_RLSBIT 0x0010 -#define SPORT_RCR1_RDTYPE_MASK 0x000c -#define SPORT_RCR1_RDTYPE_ZEROFILL 0x0000 -#define SPORT_RCR1_RDTYPE_SIGNEXTEND 0x0004 -#define SPORT_RCR1_RDTYPE_ULAW 0x0008 -#define SPORT_RCR1_RDTYPE_ALAW 0x000c -#define SPORT_RCR1_IRCLK 0x0002 -#define SPORT_RCR1_RSPEN 0x0001 - -#define SPORT_RCR2_RRFST 0x0400 -#define SPORT_RCR2_RSFSE 0x0200 -#define SPORT_RCR2_RXSE 0x0100 -#define SPORT_RCR2_SLEN_MASK 0x001f -#define SPORT_RCR2_SLEN_SHIFT 0 - -#define SPORT_STAT_TXHRE 0x0040 -#define SPORT_STAT_TOVF 0x0020 -#define SPORT_STAT_TUVF 0x0010 -#define SPORT_STAT_TXF 0x0008 -#define SPORT_STAT_ROVF 0x0004 -#define SPORT_STAT_RUVF 0x0002 -#define SPORT_STAT_RXNE 0x0001 - -#define SPORT_CHNL_CHNL_MASK 0x03ff -#define SPORT_CHNL_CHNL_SHIFT 0 - -#define SPORT_MCMC1_WSIZE_MASK 0xf000 -#define SPORT_MCMC1_WSIZE_SHIFT 12 -#define SPORT_MCMC1_WOFF_MASK 0x03ff -#define SPORT_MCMC1_WOFF_SHIFT 0 - -#define SPORT_MCMC2_MFD_MASK 0xf000 -#define SPORT_MCMC2_MFD_SHIFT 12 -#define SPORT_MCMC2_FSDR 0x0080 -#define SPORT_MCMC2_MCMEN 0x0010 -#define SPORT_MCMC2_MCDRXPE 0x0008 -#define SPORT_MCMC2_MCDTXPE 0x0004 -#define SPORT_MCMC2_MCCRM_MASK 0x0003 -#define SPORT_MCMC2_MCCRM_BYPASS 0x0000 -#define SPORT_MCMC2_MCCRM_2_4 0x0002 -#define SPORT_MCMC2_MCCRM_8_16 0x0003 - - -#endif /* _sportRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/timerRegs.h b/c/src/lib/libcpu/bfin/include/timerRegs.h deleted file mode 100644 index b66bae3339..0000000000 --- a/c/src/lib/libcpu/bfin/include/timerRegs.h +++ /dev/null @@ -1,45 +0,0 @@ -/* Blackfin General Purpose Timer Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _timerRegs_h_ -#define _timerRegs_h_ - - -/* register addresses */ - -#define TIMER_CONFIG_OFFSET 0x00 -#define TIMER_WIDTH_OFFSET 0x04 -#define TIMER_PERIOD_OFFSET 0x08 -#define TIMER_COUNTER_OFFSET 0x0c - - -/* register fields */ - -#define TIMER_CONFIG_ERR_TYP_MASK 0xc000 -#define TIMER_CONFIG_ERR_TYP_NONE 0x0000 -#define TIMER_CONFIG_ERR_TYP_OVERFLOW 0x4000 -#define TIMER_CONFIG_ERR_TYP_PERIOD 0x8000 -#define TIMER_CONFIG_ERR_TYP_WIDTH 0xc000 -#define TIMER_CONFIG_EMU_RUN 0x0200 -#define TIMER_CONFIG_TOGGLE_HI 0x0100 -#define TIMER_CONFIG_CLK_SEL 0x0080 -#define TIMER_CONFIG_OUT_DIS 0x0040 -#define TIMER_CONFIG_TIN_SEL 0x0020 -#define TIMER_CONFIG_IRQ_ENA 0x0010 -#define TIMER_CONFIG_PERIOD_CNT 0x0008 -#define TIMER_CONFIG_PULSE_HI 0x0004 -#define TIMER_CONFIG_TMODE_MASK 0x0003 -#define TIMER_CONFIG_TMODE_RESET 0x0000 -#define TIMER_CONFIG_TMODE_PWM_OUT 0x0001 -#define TIMER_CONFIG_TMODE_WDTH_CAP 0x0002 -#define TIMER_CONFIG_TMODE_EXT_CLK 0x0003 - - -#endif /* _timerRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/twiRegs.h b/c/src/lib/libcpu/bfin/include/twiRegs.h deleted file mode 100644 index c776f7886e..0000000000 --- a/c/src/lib/libcpu/bfin/include/twiRegs.h +++ /dev/null @@ -1,118 +0,0 @@ -/* Blackfin Two Wire Interface Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _twiRegs_h_ -#define _twiRegs_h_ - - -/* register addresses */ - -#define TWI_CLKDIV_OFFSET 0x0000 -#define TWI_CONTROL_OFFSET 0x0004 -#define TWI_SLAVE_CTL_OFFSET 0x0008 -#define TWI_SLAVE_STAT_OFFSET 0x000c -#define TWI_SLAVE_ADDR_OFFSET 0x0010 -#define TWI_MASTER_CTL_OFFSET 0x0014 -#define TWI_MASTER_STAT_OFFSET 0x0018 -#define TWI_MASTER_ADDR_OFFSET 0x001c -#define TWI_INT_STAT_OFFSET 0x0020 -#define TWI_INT_MASK_OFFSET 0x0024 -#define TWI_FIFO_CTL_OFFSET 0x0028 -#define TWI_FIFO_STAT_OFFSET 0x002c -#define TWI_XMT_DATA8_OFFSET 0x0080 -#define TWI_XMT_DATA16_OFFSET 0x0084 -#define TWI_RCV_DATA8_OFFSET 0x0088 -#define TWI_RCV_DATA16_OFFSET 0x008c - - -/* register fields */ - -#define TWI_CLKDIV_CLKHI_MASK 0xff00 -#define TWI_CLKDIV_CLKHI_SHIFT 8 -#define TWI_CLKDIV_CLKLOW_MASK 0x00ff -#define TWI_CLKDIV_CLKLOW_SHIFT 0 - -#define TWI_CONTROL_SCCB 0x0200 -#define TWI_CONTROL_TWI_ENA 0x0080 -#define TWI_CONTROL_PRESCALE_MASK 0x007f -#define TWI_CONTROL_PRESCALE_SHIFT 0 - -#define TWI_SLAVE_CTL_GEN 0x0010 -#define TWI_SLAVE_CTL_NAK 0x0008 -#define TWI_SLAVE_CTL_STDVAL 0x0004 -#define TWI_SLAVE_CTL_SEN 0x0001 - -#define TWI_SLAVE_STAT_GCALL 0x0002 -#define TWI_SLAVE_STAT_SDIR 0x0001 - -#define TWI_SLAVE_ADDR_SADDR_MASK 0x007f -#define TWI_SLAVE_ADDR_SADDR_SHIFT 0 - -#define TWI_MASTER_CTL_SCLOVR 0x8000 -#define TWI_MASTER_CTL_SDAOVR 0x4000 -#define TWI_MASTER_CTL_DCNT_MASK 0x3fc0 -#define TWI_MASTER_CTL_DCNT_SHIFT 6 -#define TWI_MASTER_CTL_RSTART 0x0020 -#define TWI_MASTER_CTL_STOP 0x0010 -#define TWI_MASTER_CTL_FAST 0x0008 -#define TWI_MASTER_CTL_MDIR 0x0004 -#define TWI_MASTER_CTL_MEN 0x0001 - -#define TWI_MASTER_STAT_BUSBUSY 0x0100 -#define TWI_MASTER_STAT_SCLSEN 0x0080 -#define TWI_MASTER_STAT_SDASEN 0x0040 -#define TWI_MASTER_STAT_BUFWRERR 0x0020 -#define TWI_MASTER_STAT_BUFRDERR 0x0010 -#define TWI_MASTER_STAT_DNAK 0x0008 -#define TWI_MASTER_STAT_ANAK 0x0004 -#define TWI_MASTER_STAT_LOSTARB 0x0002 -#define TWI_MASTER_STAT_MPROG 0x0001 - -#define TWI_MASTER_ADDR_MADDR_MASK 0x007f -#define TWI_MASTER_ADDR_MADDR_SHIFT 0 - -#define TWI_INT_STAT_RCVSERV 0x0080 -#define TWI_INT_STAT_XMTSERV 0x0040 -#define TWI_INT_STAT_MERR 0x0020 -#define TWI_INT_STAT_MCOMP 0x0010 -#define TWI_INT_STAT_SOVF 0x0008 -#define TWI_INT_STAT_SERR 0x0004 -#define TWI_INT_STAT_SCOMP 0x0002 -#define TWI_INT_STAT_SINIT 0x0001 - -#define TWI_INT_MASK_RCVSERVM 0x0080 -#define TWI_INT_MASK_XMTSERVM 0x0040 -#define TWI_INT_MASK_MERRM 0x0020 -#define TWI_INT_MASK_MCOMPM 0x0010 -#define TWI_INT_MASK_SOVFM 0x0008 -#define TWI_INT_MASK_SERRM 0x0004 -#define TWI_INT_MASK_SCOMPM 0x0002 -#define TWI_INT_MASK_SINITM 0x0001 - -#define TWI_FIFO_CTL_RCVINTLEN 0x0008 -#define TWI_FIFO_CTL_XMTINTLEN 0x0004 -#define TWI_FIFO_CTL_RCVFLUSH 0x0002 -#define TWI_FIFO_CTL_XMTFLUSH 0x0001 - -#define TWI_FIFO_STAT_RCVSTAT_MASK 0x000c -#define TWI_FIFO_STAT_RCVSTAT_EMPTY 0x0000 -#define TWI_FIFO_STAT_RCVSTAT_SHIFT 2 -#define TWI_FIFO_STAT_XMTSTAT_MASK 0x0003 -#define TWI_FIFO_STAT_XMTSTAT_FULL 0x0003 -#define TWI_FIFO_STAT_XMTSTAT_SHIFT 0 - -#define TWI_XMT_DATA8_XMTDATA8_MASK 0x00ff -#define TWI_XMT_DATA8_XMTDATA8_SHIFT 0 - -#define TWI_RCV_DATA8_RCVDATA8_MASK 0x00ff -#define TWI_RCV_DATA8_RCVDATA8_SHIFT 0 - - -#endif /* _twiRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/uartRegs.h b/c/src/lib/libcpu/bfin/include/uartRegs.h deleted file mode 100644 index f48052e49b..0000000000 --- a/c/src/lib/libcpu/bfin/include/uartRegs.h +++ /dev/null @@ -1,70 +0,0 @@ -/* Blackfin UART Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _uartRegs_h_ -#define _uartRegs_h_ - -/* register addresses */ - -#define UART_RBR_OFFSET 0x0000 -#define UART_THR_OFFSET 0x0000 -#define UART_DLL_OFFSET 0x0000 -#define UART_IER_OFFSET 0x0004 -#define UART_DLH_OFFSET 0x0004 -#define UART_IIR_OFFSET 0x0008 -#define UART_LCR_OFFSET 0x000c -#define UART_MCR_OFFSET 0x0010 -#define UART_LSR_OFFSET 0x0014 -#define UART_SCR_OFFSET 0x001c -#define UART_GCTL_OFFSET 0x0024 - - -/* register fields */ - -#define UART_LCR_DLAB 0x80 -#define UART_LCR_SB 0x40 -#define UART_LCR_STP 0x20 -#define UART_LCR_EPS 0x10 -#define UART_LCR_PEN 0x08 -#define UART_LCR_STB 0x04 -#define UART_LCR_WLS_MASK 0x03 -#define UART_LCR_WLS_5 0x00 -#define UART_LCR_WLS_6 0x01 -#define UART_LCR_WLS_7 0x02 -#define UART_LCR_WLS_8 0x03 - -#define UART_MCR_LOOP 0x10 - -#define UART_LSR_TEMT 0x40 -#define UART_LSR_THRE 0x20 -#define UART_LSR_BI 0x10 -#define UART_LSR_FE 0x08 -#define UART_LSR_PE 0x04 -#define UART_LSR_OE 0x02 -#define UART_LSR_DR 0x01 - -#define UART_IER_ELSI 0x04 -#define UART_IER_ETBEI 0x02 -#define UART_IER_ERBFI 0x01 - -#define UART_IIR_STATUS_MASK 0x06 -#define UART_IIR_STATUS_THRE 0x02 -#define UART_IIR_STATUS_RDR 0x04 -#define UART_IIR_STATUS_LS 0x06 -#define UART_IIR_NINT 0x01 - -#define UART_GCTL_FFE 0x20 -#define UART_GCTL_FPE 0x10 -#define UART_GCTL_RPOLC 0x08 -#define UART_GCTL_TPOLC 0x04 -#define UART_GCTL_IREN 0x02 -#define UART_GCTL_UCEN 0x01 - -#endif /* _uartRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/include/wdogRegs.h b/c/src/lib/libcpu/bfin/include/wdogRegs.h deleted file mode 100644 index 9e76d345b0..0000000000 --- a/c/src/lib/libcpu/bfin/include/wdogRegs.h +++ /dev/null @@ -1,33 +0,0 @@ -/* Blackfin Watchdog Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _wdogRegs_h_ -#define _wdogRegs_h_ - -/* register addresses */ - -#define WDOG_CTL (WDOG_BASE_ADDRESS + 0x0000) -#define WDOG_CNT (WDOG_BASE_ADDRESS + 0x0004) -#define WDOG_STAT (WDOG_BASE_ADDRESS + 0x0008) - - -/* register fields */ - -#define WDOG_CTL_WDRO 0x8000 -#define WDOG_CTL_WDEN_MASK 0x0ff0 -#define WDOG_CTL_WDEN_DISABLE 0x0ad0 -#define WDOG_CTL_WDEV_MASK 0x0006 -#define WDOG_CTL_WDEV_RESET 0x0000 -#define WDOG_CTL_WDEV_NMI 0x0002 -#define WDOG_CTL_WDEV_GPI 0x0004 -#define WDOG_CTL_WDEV_DISABLE 0x0006 - - -#endif /* _wdogRegs_h_ */ diff --git a/c/src/lib/libcpu/bfin/interrupt/interrupt.h b/c/src/lib/libcpu/bfin/interrupt/interrupt.h deleted file mode 100644 index 2c6b538bde..0000000000 --- a/c/src/lib/libcpu/bfin/interrupt/interrupt.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * RTEMS support for Blackfin interrupt controller - * - * COPYRIGHT (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _interrupt_h_ -#define _interrupt_h_ - -/* Some rules for using this module: - - SIC_IARx registers must not be changed after calling - bfin_interrupt_init(). - - The bfin_isr structures must stick around for as long as the isr is - registered. - - For any interrupt source (SIC bit) that could be shared, it is only - safe to disable an ISR through this module if the ultimate source is - also disabled (the ultimate source must be disabled prior to disabling - it through this module, and must remain disabled until after enabling - it through this module). - - For any source that is shared with modules that cannot be disabled, - give careful thought to the control of those interrupts. - bfin_interrupt_enable_all() or bfin_interrupt_enable_global() can - be used to help solve the problems caused by that. - - - Note that this module does not provide prioritization. It is assumed - that the priorities afforded by the CEC are sufficient. If finer - grained priority control is required then this wlll need to be - redesigned. -*/ - - -#ifdef __cplusplus -extern "C" { -#endif - -/* source is the source to the SIC (the bit number in SIC_ISR). isr is - the function that will be called when the interrupt is active. */ -typedef struct bfin_isr_s { - int source; - void (*isr)(int source); - /* the following are for internal use only */ - uint32_t mask; - int vector; - struct bfin_isr_s *next; -} bfin_isr_t; - -/* If non-default mapping is desired, the BSP should set the SIC_IARx - registers prior to calling this. */ -void bfin_interrupt_init(void); - -/* ISR starts out disabled */ -void bfin_interrupt_register(bfin_isr_t *isr); -void bfin_interrupt_unregister(bfin_isr_t *isr); - -/* enable/disable specific ISR */ -void bfin_interrupt_enable(bfin_isr_t *isr, bool enable); - -/* atomically enable/disable all ISRs attached to specified source */ -void bfin_interrupt_enable_all(int source, bool enable); - -/* disable a source independently of the individual ISR enables (starts - out all enabled) */ -void bfin_interrupt_enable_global(int source, bool enable); - -#ifdef __cplusplus -} -#endif - -#endif /* _interrupt_h_ */ - diff --git a/c/src/lib/libcpu/bfin/mmu/mmu.h b/c/src/lib/libcpu/bfin/mmu/mmu.h deleted file mode 100644 index d6e2ea58a9..0000000000 --- a/c/src/lib/libcpu/bfin/mmu/mmu.h +++ /dev/null @@ -1,73 +0,0 @@ -/* Blackfin MMU Support - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -/* NOTE: this currently only implements a static table. It should be made - to handle more regions than fit in the CPLBs, with an exception handler - to do replacements as needed. This would of course require great care - to insure any storage required by the exception handler, including any - stack space, the exception handler itself, and the region descriptors - it needs to update the CPLBs, are in regions that will never be - replaced. */ - -#ifndef _mmu_h_ -#define _mmu_h_ - -#include <libcpu/mmuRegs.h> - - -#define INSTR_NOCACHE (ICPLB_DATA_CPLB_USER_RD | \ - ICPLB_DATA_CPLB_VALID) - -#define INSTR_CACHEABLE (ICPLB_DATA_CPLB_L1_CHBL | \ - ICPLB_DATA_CPLB_USER_RD | \ - ICPLB_DATA_CPLB_VALID) - -#define DATA_NOCACHE (DCPLB_DATA_CPLB_DIRTY | \ - DCPLB_DATA_CPLB_SUPV_WR | \ - DCPLB_DATA_CPLB_USER_WR | \ - DCPLB_DATA_CPLB_USER_RD | \ - DCPLB_DATA_CPLB_VALID) - -#define DATA_WRITEBACK (DCPLB_DATA_CPLB_L1_AOW | \ - DCPLB_DATA_CPLB_L1_CHBL | \ - DCPLB_DATA_CPLB_DIRTY | \ - DCPLB_DATA_CPLB_SUPV_WR | \ - DCPLB_DATA_CPLB_USER_WR | \ - DCPLB_DATA_CPLB_USER_RD | \ - DCPLB_DATA_CPLB_VALID) - - -#ifdef __cplusplus -extern "C" { -#endif - - -typedef struct { - struct { - void *address; - uint32_t flags; - } instruction[ICPLB_COUNT]; - struct { - void *address; - uint32_t flags; - } data[DCPLB_COUNT]; -} bfin_mmu_config_t; - - -void bfin_mmu_init(bfin_mmu_config_t *config); - - -#ifdef __cplusplus -} -#endif - -#endif /* _mmu_h_ */ - diff --git a/c/src/lib/libcpu/bfin/network/ethernet.h b/c/src/lib/libcpu/bfin/network/ethernet.h deleted file mode 100644 index 0a8fc0c4b0..0000000000 --- a/c/src/lib/libcpu/bfin/network/ethernet.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * RTEMS network driver for Blackfin embedded ethernet controller - * - * COPYRIGHT (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _ethernet_h_ -#define _ethernet_h_ - - -#define BFIN_ETHERNET_DEBUG_NONE 0x0000 -#define BFIN_ETHERNET_DEBUG_ALL 0xFFFF - -#define BFIN_ETHERNET_DEBUG (BFIN_ETHERNET_DEBUG_NONE) - - -#ifdef __cplusplus -extern "C" { -#endif - - -typedef struct { - uint32_t sclk; - void *ethBaseAddress; - void *rxdmaBaseAddress; - void *txdmaBaseAddress; - int rxDescCount; - int txDescCount; - enum {rmii, mii} phyType; - int phyAddr; -} bfin_ethernet_configuration_t; - - -void bfin_ethernet_rxdma_isr(int vector); -void bfin_ethernet_txdma_isr(int vector); -void bfin_ethernet_mac_isr(int vector); - -int bfin_ethernet_driver_attach(struct rtems_bsdnet_ifconfig *config, - int attaching, - bfin_ethernet_configuration_t *chip); - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ethernet_h_ */ - diff --git a/c/src/lib/libcpu/bfin/preinstall.am b/c/src/lib/libcpu/bfin/preinstall.am deleted file mode 100644 index c7298742e3..0000000000 --- a/c/src/lib/libcpu/bfin/preinstall.am +++ /dev/null @@ -1,146 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE) - @: > $(PROJECT_INCLUDE)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) - -$(PROJECT_INCLUDE)/bsp/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp - @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) - -$(PROJECT_INCLUDE)/libcpu/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu - @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - -if bf52x -$(PROJECT_INCLUDE)/bf52x.h: bf52x/include/bf52x.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bf52x.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bf52x.h - -$(PROJECT_INCLUDE)/bsp/interrupt.h: bf52x/interrupt/interrupt.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/interrupt.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/interrupt.h -endif -$(PROJECT_INCLUDE)/libcpu/bf533.h: include/bf533.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/bf533.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/bf533.h - -$(PROJECT_INCLUDE)/libcpu/bf537.h: include/bf537.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/bf537.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/bf537.h - -$(PROJECT_INCLUDE)/libcpu/cecRegs.h: include/cecRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cecRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cecRegs.h - -$(PROJECT_INCLUDE)/libcpu/memoryRegs.h: include/memoryRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/memoryRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/memoryRegs.h - -$(PROJECT_INCLUDE)/libcpu/mmuRegs.h: include/mmuRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmuRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmuRegs.h - -$(PROJECT_INCLUDE)/libcpu/sicRegs.h: include/sicRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/sicRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/sicRegs.h - -$(PROJECT_INCLUDE)/libcpu/ebiuRegs.h: include/ebiuRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/ebiuRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/ebiuRegs.h - -$(PROJECT_INCLUDE)/libcpu/ppiRegs.h: include/ppiRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/ppiRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/ppiRegs.h - -$(PROJECT_INCLUDE)/libcpu/coreTimerRegs.h: include/coreTimerRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/coreTimerRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/coreTimerRegs.h - -$(PROJECT_INCLUDE)/libcpu/wdogRegs.h: include/wdogRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/wdogRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/wdogRegs.h - -$(PROJECT_INCLUDE)/libcpu/timerRegs.h: include/timerRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/timerRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/timerRegs.h - -$(PROJECT_INCLUDE)/libcpu/dmaRegs.h: include/dmaRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/dmaRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/dmaRegs.h - -$(PROJECT_INCLUDE)/libcpu/ethernetRegs.h: include/ethernetRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/ethernetRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/ethernetRegs.h - -$(PROJECT_INCLUDE)/libcpu/uartRegs.h: include/uartRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/uartRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/uartRegs.h - -$(PROJECT_INCLUDE)/libcpu/sportRegs.h: include/sportRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/sportRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/sportRegs.h - -$(PROJECT_INCLUDE)/libcpu/twiRegs.h: include/twiRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/twiRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/twiRegs.h - -$(PROJECT_INCLUDE)/libcpu/spiRegs.h: include/spiRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/spiRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/spiRegs.h - -$(PROJECT_INCLUDE)/libcpu/rtcRegs.h: include/rtcRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/rtcRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/rtcRegs.h - -$(PROJECT_INCLUDE)/libcpu/gpioRegs.h: include/gpioRegs.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/gpioRegs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/gpioRegs.h - -$(PROJECT_INCLUDE)/libcpu/mmu.h: mmu/mmu.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h - -if bf52x -else -$(PROJECT_INCLUDE)/libcpu/interrupt.h: interrupt/interrupt.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/interrupt.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/interrupt.h -endif -$(PROJECT_INCLUDE)/libcpu/uart.h: serial/uart.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/uart.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/uart.h - -$(PROJECT_INCLUDE)/libcpu/sport.h: serial/sport.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/sport.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/sport.h - -$(PROJECT_INCLUDE)/libcpu/spi.h: serial/spi.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/spi.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/spi.h - -$(PROJECT_INCLUDE)/libcpu/twi.h: serial/twi.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/twi.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/twi.h - -if HAS_NETWORKING -$(PROJECT_INCLUDE)/libcpu/ethernet.h: network/ethernet.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/ethernet.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/ethernet.h -endif diff --git a/c/src/lib/libcpu/bfin/serial/spi.h b/c/src/lib/libcpu/bfin/serial/spi.h deleted file mode 100644 index db8bfaa612..0000000000 --- a/c/src/lib/libcpu/bfin/serial/spi.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * RTEMS driver for Blackfin SPI - * - * COPYRIGHT (c) 2010 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _spi_h -#define _spi_h - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - void *base; - /* remaining entries are for internal use */ - rtems_id sem; - int bytes_per_word; - uint16_t idle_pattern; - uint8_t *rd_ptr; - const uint8_t *wr_ptr; - int len; -} bfin_spi_state_t; - -typedef struct { - rtems_libi2c_bus_t bus; - bfin_spi_state_t p; -} bfin_spi_bus_t; - - -void bfin_spi_isr(int v); - -rtems_status_code bfin_spi_init(rtems_libi2c_bus_t *bus); - -rtems_status_code bfin_spi_send_start(rtems_libi2c_bus_t *bus); - -int bfin_spi_read_bytes(rtems_libi2c_bus_t *bus, unsigned char *buf, int len); - -int bfin_spi_write_bytes(rtems_libi2c_bus_t *bus, unsigned char *buf, int len); - -int bfin_spi_ioctl(rtems_libi2c_bus_t *bus, int cmd, void *arg); - -#ifdef __cplusplus -} -#endif - - -#endif /* _spi_h */ diff --git a/c/src/lib/libcpu/bfin/serial/sport.h b/c/src/lib/libcpu/bfin/serial/sport.h deleted file mode 100644 index 6ed481b593..0000000000 --- a/c/src/lib/libcpu/bfin/serial/sport.h +++ /dev/null @@ -1,2 +0,0 @@ -/* placeholder */ - diff --git a/c/src/lib/libcpu/bfin/serial/twi.h b/c/src/lib/libcpu/bfin/serial/twi.h deleted file mode 100644 index 2392ba532b..0000000000 --- a/c/src/lib/libcpu/bfin/serial/twi.h +++ /dev/null @@ -1,68 +0,0 @@ -/* not yet implemented */ - -/* - * RTEMS driver for Blackfin TWI (I2C) - * - * COPYRIGHT (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _twi_h_ -#define _twi_h_ - - -#ifdef __cplusplus -extern "C" { -#endif - - -typedef struct { - uint32_t sclk; - void *base; - bool fast; - int8_t slave_address; -} bfin_twi_config_t; - -typedef struct bfin_twi_request_s { - bool write; - int count; - void *data; - /* Chained requests are done with repeated start conditions in between. - These are useful for atomic address write/data read transactions - (which can be important in multi-master configurations), and for - doing 10-bit addressing. */ - struct bfin_twi_request_s *next; -} bfin_twi_request_t; - -typedef rtems_status_code (*bfin_twi_callback_t)(int channel, - void *arg, - bool general_call, - bool write, - bool done, - int read_count, - uint8_t *data); - - -rtems_status_code bfin_twi_init(int channel, bfin_twi_config_t *config); - -rtems_status_code bfin_twi_register_callback(int channel, - bfin_twi_callback_t callback, - void *arg); - -void bfin_twi_isr(int source); - -rtems_status_code bfin_twi_request(int channel, uint8_t address, - bfin_twi_request_t *request, - rtems_interval timeout); - - -#ifdef __cplusplus -} -#endif - -#endif /* _twi_h_ */ - diff --git a/c/src/lib/libcpu/bfin/serial/uart.h b/c/src/lib/libcpu/bfin/serial/uart.h deleted file mode 100644 index 730e0e261f..0000000000 --- a/c/src/lib/libcpu/bfin/serial/uart.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * RTEMS driver for Blackfin UARTs - * - * COPYRIGHT (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#ifndef _UART_H_ -#define _UART_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** bfin_uart_channel object - */ -typedef struct { - const char *name; /** Holds name of the device */ - uint32_t uart_baseAddress; /** UART base address */ - uint32_t uart_rxDmaBaseAddress; /** RX DMA base address */ - uint32_t uart_txDmaBaseAddress; /** TX DMA base address */ - bool uart_useInterrupts; /** are interrupts used */ - bool uart_useDma; /** is dma used */ - int uart_baud; /** baud rate, 0 for default */ - - void *termios; /** termios associated */ - uint8_t volatile flags; /** flags for internal use */ - uint16_t length; /** length for internal use */ -} bfin_uart_channel_t; - - -typedef struct { - uint32_t freq; - int num_channels; - bfin_uart_channel_t *channels; -} bfin_uart_config_t; - -/** - * @param base_address defines the UART base address - * @param source defines the source that caused the interrupt. This argument - * will help us in identifying if Rx or TX caused the interrupt. - */ -typedef struct { - uint32_t base_address; - int source; -} bfin_uart_arg_t; - - - -char bfin_uart_poll_read(rtems_device_minor_number minor); - -void bfin_uart_poll_write(int minor, char c); - - -/** -* Uart initialization function. -* @param major major number of the device -* @param config configuration parameters -* @return rtems status code -*/ -rtems_status_code bfin_uart_initialize(rtems_device_major_number major, - bfin_uart_config_t *config); - - - -/** - * Opens the device in different modes. The supported modes are - * 1. Polling - * 2. Interrupt - * 3. DMA - * At exit the uart_Exit function will be called to flush the device. - * - * @param major Major number of the device - * @param minor Minor number of the device - * @param arg - * @return - */ -rtems_device_driver bfin_uart_open(rtems_device_major_number major, - rtems_device_minor_number minor, void *arg); - - - -/** - * This function implements TX dma ISR. It clears the IRQ and dequeues a char - * The channel argument will have the base address. Since there are two uart - * and both the uarts can use the same tx dma isr. - * - * TODO: 1. Error checking 2. sending correct length ie after looking at the - * number of elements the uart transmitted. - * - * @param _arg argument passed to the interrupt handler. It contains the - * channel argument. - */ -void bfinUart_txDmaIsr(void *_arg); - - - -/** - * RX DMA ISR. - * The polling route is used for receiving the characters. This is a place - * holder for future implementation. - * @param _arg - */ -void bfinUart_rxDmaIsr(void *_arg); - - -/** - * This function implements TX ISR. The function gets called when the TX FIFO is - * empty. It clears the interrupt and dequeues the character. It only tx one - * character at a time. - * - * TODO: error handling. - * @param _arg gets the channel information. - */ -void bfinUart_txIsr(void *_arg); - - -/** -* This function implements RX ISR -*/ -void bfinUart_rxIsr(void *_arg); - - -#ifdef __cplusplus -} -#endif - -#endif /* _UART_H_ */ - diff --git a/c/src/lib/libcpu/i386/Makefile.am b/c/src/lib/libcpu/i386/Makefile.am index c47b9dfc39..6f1e9fe3ec 100644 --- a/c/src/lib/libcpu/i386/Makefile.am +++ b/c/src/lib/libcpu/i386/Makefile.am @@ -4,11 +4,6 @@ noinst_PROGRAMS = include $(top_srcdir)/../../../automake/compile.am -include_libcpudir = $(includedir)/libcpu - -include_libcpu_HEADERS = page.h cpuModel.h -include_libcpu_HEADERS += byteorder.h - noinst_PROGRAMS += cache.rel cache_rel_SOURCES = cache.c cache_.h \ ../shared/src/cache_manager.c ../shared/include/cache.h @@ -25,5 +20,4 @@ page_rel_SOURCES = page.c page.h page_rel_CPPFLAGS = $(AM_CPPFLAGS) page_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/i386/byteorder.h b/c/src/lib/libcpu/i386/byteorder.h deleted file mode 100644 index 939e51fe84..0000000000 --- a/c/src/lib/libcpu/i386/byteorder.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_BYTEORDER_H -#define _LIBCPU_BYTEORDER_H - -static inline void st_le32(volatile uint32_t *addr, uint32_t value) -{ - *(addr)=value ; -} - -static inline uint32_t ld_le32(volatile uint32_t *addr) -{ - return(*addr); -} - -static inline void st_le16(volatile uint16_t *addr, uint16_t value) -{ - *(addr)=value ; -} - -static inline uint16_t ld_le16(volatile uint16_t *addr) -{ - return(*addr); -} - - -#endif diff --git a/c/src/lib/libcpu/i386/configure.ac b/c/src/lib/libcpu/i386/configure.ac index e03af4824a..3f0f59543a 100644 --- a/c/src/lib/libcpu/i386/configure.ac +++ b/c/src/lib/libcpu/i386/configure.ac @@ -4,6 +4,8 @@ AC_PREREQ([2.69]) AC_INIT([rtems-c-src-lib-libcpu-i386],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([idtr.S]) RTEMS_TOP([../../../../..],[../../..]) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP RTEMS_CANONICAL_TARGET_CPU diff --git a/c/src/lib/libcpu/i386/cpuModel.h b/c/src/lib/libcpu/i386/cpuModel.h deleted file mode 100644 index d17839b7ea..0000000000 --- a/c/src/lib/libcpu/i386/cpuModel.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file contains declaration for variables and code - * that may be used to get the Intel Cpu identification - * that has been performed by checkCPUtypeSetCr0 function. - */ - -/* - * COPYRIGHT (c) 1998 valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef libcpu_cpuModel_h -#define libcpu_cpuModel_h - -/* - * Tell us the machine setup.. - */ - -extern char hard_math; /* floating point coprocessor present indicator */ -extern char x86; /* type of cpu (3 = 386, 4 =486, ...) */ -extern char x86_model; -extern char x86_mask; -extern int x86_capability; /* cpuid:EDX */ -extern int x86_capability_x; /* cpuid:ECX */ -extern int x86_capability_ebx; /* cpuid:EBX */ -extern int x86_capability_cores; /* cpuid.(EAX=4, ECX=0) - physical cores */ -extern char x86_vendor_id[13]; -extern int have_cpuid; -extern unsigned char Cx86_step; /* cyrix processor identification */ - -/* Display this information on console in ascii form */ -extern void printCpuInfo(void); - -/* determine if the CPU has a TSC */ -#define x86_has_tsc() \ - (x86_capability & (1 << 4)) - -static inline unsigned long long -rdtsc(void) -{ - /* Return the value of the on-chip cycle counter. */ - unsigned long long result; - __asm__ volatile(".byte 0x0F, 0x31" : "=A" (result)); - return result; -} /* rdtsc */ - - -#endif diff --git a/c/src/lib/libcpu/i386/page.h b/c/src/lib/libcpu/i386/page.h deleted file mode 100644 index 5e9cec2227..0000000000 --- a/c/src/lib/libcpu/i386/page.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * @file page.h - * - * Copyright (C) 1998 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_i386_PAGE_H -#define _LIBCPU_i386_PAGE_H - -#ifndef ASM - -#include <rtems/score/cpu.h> - -/* C declaration for paging management */ - -extern int _CPU_is_cache_enabled(void); -extern int _CPU_is_paging_enabled(void); -extern int init_paging(void); -extern void _CPU_enable_paging(void); -extern void _CPU_disable_paging(void); -extern void _CPU_disable_cache(void); -extern void _CPU_enable_cache(void); -extern int _CPU_map_phys_address - (void **mappedAddress, void *physAddress, - int size, int flag); -extern int _CPU_unmap_virt_address (void *mappedAddress, int size); -extern int _CPU_change_memory_mapping_attribute - (void **newAddress, void *mappedAddress, - unsigned int size, unsigned int flag); -extern int _CPU_display_memory_attribute(void); - -# endif /* ASM */ - -#endif diff --git a/c/src/lib/libcpu/i386/preinstall.am b/c/src/lib/libcpu/i386/preinstall.am deleted file mode 100644 index 1e6c1dfdba..0000000000 --- a/c/src/lib/libcpu/i386/preinstall.am +++ /dev/null @@ -1,32 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/libcpu/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu - @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - -$(PROJECT_INCLUDE)/libcpu/page.h: page.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/page.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/page.h - -$(PROJECT_INCLUDE)/libcpu/cpuModel.h: cpuModel.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cpuModel.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cpuModel.h - -$(PROJECT_INCLUDE)/libcpu/byteorder.h: byteorder.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/byteorder.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/byteorder.h - diff --git a/c/src/lib/libcpu/lm32/Makefile.am b/c/src/lib/libcpu/lm32/Makefile.am index 5de23de6cb..1e609cabf6 100644 --- a/c/src/lib/libcpu/lm32/Makefile.am +++ b/c/src/lib/libcpu/lm32/Makefile.am @@ -21,6 +21,5 @@ shared_misc_rel_CPPFLAGS = $(AM_CPPFLAGS) $(LM32_CPPFLAGS) shared_misc_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/lm32/configure.ac b/c/src/lib/libcpu/lm32/configure.ac index 53a2e4bcf4..295ae91ee2 100644 --- a/c/src/lib/libcpu/lm32/configure.ac +++ b/c/src/lib/libcpu/lm32/configure.ac @@ -3,6 +3,8 @@ AC_PREREQ([2.69]) AC_INIT([rtems-c-src-lib-libcpu-lm32],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) RTEMS_TOP([../../../../..],[../../..]) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP RTEMS_CANONICAL_TARGET_CPU diff --git a/c/src/lib/libcpu/lm32/preinstall.am b/c/src/lib/libcpu/lm32/preinstall.am deleted file mode 100644 index dba6cc4d81..0000000000 --- a/c/src/lib/libcpu/lm32/preinstall.am +++ /dev/null @@ -1,7 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - diff --git a/c/src/lib/libcpu/m68k/Makefile.am b/c/src/lib/libcpu/m68k/Makefile.am index 18724352d6..2800e421c4 100644 --- a/c/src/lib/libcpu/m68k/Makefile.am +++ b/c/src/lib/libcpu/m68k/Makefile.am @@ -67,10 +67,6 @@ EXTRA_DIST = m68040/fpsp/README if mcf5206 # mcf5206/include -include_mcf5206dir = $(includedir)/mcf5206 -include_mcf5206_HEADERS = mcf5206/include/mcf5206e.h mcf5206/include/mcfmbus.h \ - mcf5206/include/mcfuart.h - ## mcf5206/clock noinst_PROGRAMS += mcf5206/clock.rel mcf5206_clock_rel_SOURCES = mcf5206/clock/ckinit.c @@ -98,9 +94,6 @@ endif if mcf5223x ## mcf5223x/include -include_mcf5223xdir = $(includedir)/mcf5223x -include_mcf5223x_HEADERS = mcf5223x/include/mcf5223x.h - ## mcf5223x/cache noinst_PROGRAMS += mcf5223x/cachepd.rel mcf5223x_cachepd_rel_SOURCES = mcf5223x/cache/cachepd.c @@ -110,9 +103,6 @@ endif if mcf5225x ## mcf5225x/include -include_mcf5225xdir = $(includedir)/mcf5225x -include_mcf5225x_HEADERS = mcf5225x/include/mcf5225x.h - # mcf5225x/cache noinst_PROGRAMS += mcf5225x/cachepd.rel mcf5225x_cachepd_rel_SOURCES = mcf5225x/cache/cachepd.c @@ -121,15 +111,11 @@ mcf5225x_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # Network if HAS_NETWORKING -include_mcf5225x_HEADERS += mcf5225x/include/fec.h endif ## HAS_NETWORKING endif if mcf5235 ## mcf5235/include -include_mcf5235dir = $(includedir)/mcf5235 -include_mcf5235_HEADERS = mcf5235/include/mcf5235.h - ## mcf5235/cache noinst_PROGRAMS += mcf5235/cachepd.rel mcf5235_cachepd_rel_SOURCES = mcf5235/cache/cachepd.c @@ -139,9 +125,6 @@ endif if mcf532x ## mcf532x/include -include_mcf532xdir = $(includedir)/mcf532x -include_mcf532x_HEADERS = mcf532x/include/mcf532x.h - ## mcf532x/cache noinst_PROGRAMS += mcf532x/cachepd.rel mcf532x_cachepd_rel_SOURCES = mcf532x/cache/cachepd.c @@ -151,9 +134,6 @@ endif if mcf5272 ## mcf5272/include -include_mcf5272dir = $(includedir)/mcf5272 -include_mcf5272_HEADERS = mcf5272/include/mcf5272.h - ## clock noinst_PROGRAMS += mcf5272/clock.rel mcf5272_clock_rel_SOURCES = mcf5272/clock/ckinit.c @@ -169,9 +149,6 @@ endif if mcf5282 ## mcf5282/include -include_mcf5282dir = $(includedir)/mcf5282 -include_mcf5282_HEADERS = mcf5282/include/mcf5282.h - noinst_PROGRAMS += mcf5282/cachepd.rel mcf5282_cachepd_rel_SOURCES = mcf5282/cache/cachepd.c mcf5282_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache @@ -180,13 +157,8 @@ endif if mcf548x ## mcf548x/include -include_mcf548xdir = $(includedir)/mcf548x -include_mcf548x_HEADERS = mcf548x/include/mcf548x.h - ## mcf548x/mcdma noinst_PROGRAMS += mcf548x/mcdma.rel -include_mcf548x_HEADERS += mcf548x/mcdma/MCD_progCheck.h mcf548x/mcdma/MCD_dma.h \ - mcf548x/mcdma/MCD_tasksInit.h mcf548x/mcdma/mcdma_glue.h mcf548x_mcdma_rel_SOURCES = mcf548x/mcdma/MCD_dmaApi.c mcf548x/mcdma/MCD_tasksInit.c \ mcf548x/mcdma/MCD_tasks.c mcf548x/mcdma/mcdma_glue.c @@ -194,5 +166,4 @@ mcf548x_mcdma_rel_CPPFLAGS = $(AM_CPPFLAGS) mcf548x_mcdma_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/m68k/configure.ac b/c/src/lib/libcpu/m68k/configure.ac index 99596c1a3e..5f24e9efd4 100644 --- a/c/src/lib/libcpu/m68k/configure.ac +++ b/c/src/lib/libcpu/m68k/configure.ac @@ -4,6 +4,8 @@ AC_PREREQ([2.69]) AC_INIT([rtems-c-src-lib-libcpu-m68k],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([m68040]) RTEMS_TOP([../../../../..],[../../..]) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP RTEMS_CANONICAL_TARGET_CPU diff --git a/c/src/lib/libcpu/m68k/mcf5206/include/mcf5206e.h b/c/src/lib/libcpu/m68k/mcf5206/include/mcf5206e.h deleted file mode 100644 index 06dadca9b1..0000000000 --- a/c/src/lib/libcpu/m68k/mcf5206/include/mcf5206e.h +++ /dev/null @@ -1,609 +0,0 @@ -/* - * Coldfire MCF5206e on-chip peripherial definitions. - * Contents of this file based on information provided in - * Motorola MCF5206e User's Manual - * - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov <vvv@oktet.ru> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __MCF5206E_H__ -#define __MCF5206E_H__ - -#ifdef ASM -#define MCF5206E_REG8(base,ofs) (ofs+base) -#define MCF5206E_REG16(base,ofs) (ofs+base) -#define MCF5206E_REG32(base,ofs) (ofs+base) -#else -#define MCF5206E_REG8(base,ofs) \ - (volatile uint8_t*)((uint8_t*)(base) + (ofs)) -#define MCF5206E_REG16(base,ofs) \ - (volatile uint16_t*)((uint8_t*)(base) + (ofs)) -#define MCF5206E_REG32(base,ofs) \ - (volatile uint32_t*)((uint8_t*)(base) + (ofs)) -#endif - -/*** Instruction Cache -- MCF5206e User's Manual, Chapter 4 ***/ - -/* CACR - Cache Control Register */ -#define MCF5206E_CACR_CENB (0x80000000) /* Cache Enable */ -#define MCF5206E_CACR_CPDI (0x10000000) /* Disable CPUSHL Invalidation */ -#define MCF5206E_CACR_CFRZ (0x08000000) /* Cache Freeze */ -#define MCF5206E_CACR_CINV (0x01000000) /* Cache Invalidate */ -#define MCF5206E_CACR_CEIB (0x00000400) /* Cache Enable Noncacheable - instruction bursting */ -#define MCF5206E_CACR_DCM (0x00000200) /* Default cache mode - noncacheable*/ -#define MCF5206E_CACR_DBWE (0x00000100) /* Default Buffered Write Enable */ -#define MCF5206E_CACR_DWP (0x00000020) /* Default Write Protection */ -#define MCF5206E_CACR_CLNF (0x00000003) /* Cache Line Fill */ - -/* ACR0, ACR1 - Access Control Registers */ -#define MCF5206E_ACR_AB (0xff000000) /* Address Base */ -#define MCF5206E_ACR_AB_S (24) -#define MCF5206E_ACR_AM (0x00ff0000) /* Address Mask */ -#define MCF5206E_ACR_AM_S (16) -#define MCF5206E_ACR_EN (0x00008000) /* Enable ACR */ -#define MCF5206E_ACR_SM (0x00006000) /* Supervisor Mode */ -#define MCF5206E_ACR_SM_USR (0x00000000) /* Match if user mode */ -#define MCF5206E_ACR_SM_SVR (0x00002000) /* Match if supervisor mode */ -#define MCF5206E_ACR_SM_ANY (0x00004000) /* Match Always */ -#define MCF5206E_ACR_CM (0x00000040) /* Cache Mode (1 - noncacheable) */ -#define MCF5206E_ACR_BUFW (0x00000020) /* Buffered Write Enable */ -#define MCF5206E_ACR_WP (0x00000004) /* Write Protect */ -#define MCF5206E_ACR_BASE(base) ((base) & MCF5206E_ACR_AB) -#define MCF5206E_ACR_MASK(mask) (((mask) >> 8) & MCF5206E_ACR_AM) - -/*** SRAM -- MCF5206e User's Manual, Chapter 5 ***/ - -/* RAMBAR - SRAM Base Address Register */ -#define MCF5206E_RAMBAR_BA (0xffffe000) /* SRAM Base Address */ -#define MCF5206E_RAMBAR_WP (0x00000100) /* Write Protect */ -#define MCF5206E_RAMBAR_CI (0x00000020) /* CPU Space mask */ -#define MCF5206E_RAMBAR_SC (0x00000010) /* Supervisor Code Space Mask */ -#define MCF5206E_RAMBAR_SD (0x00000008) /* Supervisor Data Space Mask */ -#define MCF5206E_RAMBAR_UC (0x00000004) /* User Code Space Mask */ -#define MCF5206E_RAMBAR_UD (0x00000002) /* User Data Space Mask */ -#define MCF5206E_RAMBAR_V (0x00000001) /* Contents of RAMBAR are valid */ - -/*** DMA Controller Module -- MCF5206e User's Manual, Chapter 7 ***/ - -/* DMA Source Address Register */ -#define MCF5206E_SAR(mbar,chn) MCF5206E_REG32(mbar,0x200 + ((chn) * 0x40)) - -/* DMA Destination Address Register */ -#define MCF5206E_DAR(mbar,chn) MCF5206E_REG32(mbar,0x204 + ((chn) * 0x40)) - -/* DMA Byte Count Register */ -#define MCF5206E_BCR(mbar,chn) MCF5206E_REG16(mbar,0x20C + ((chn) * 0x40)) - -/* DMA Control Register */ -#define MCF5206E_DCR(mbar,chn) MCF5206E_REG16(mbar,0x208 + ((chn) * 0x40)) -#define MCF5206E_DCR_INT (0x8000) /* Interrupt on completion of transfer */ -#define MCF5206E_DCR_EEXT (0x4000) /* Enable External DMA Request */ -#define MCF5206E_DCR_CS (0x2000) /* Cycle Steal */ -#define MCF5206E_DCR_AA (0x1000) /* Auto Align */ -#define MCF5206E_DCR_BWC (0x0E00) /* Bandwidth Control: */ -#define MCF5206E_DCR_BWC_DISABLE (0x0000) /* Bandwidth Control Disabled */ -#define MCF5206E_DCR_BWC_512 (0x0200) /* 512 bytes */ -#define MCF5206E_DCR_BWC_1024 (0x0400) /* 1024 bytes */ -#define MCF5206E_DCR_BWC_2048 (0x0600) /* 2048 bytes */ -#define MCF5206E_DCR_BWC_4096 (0x0800) /* 4096 bytes */ -#define MCF5206E_DCR_BWC_8192 (0x0A00) /* 8192 bytes */ -#define MCF5206E_DCR_BWC_16384 (0x0C00) /* 16384 bytes */ -#define MCF5206E_DCR_BWC_32768 (0x0E00) /* 32768 bytes */ -#define MCF5206E_DCR_SAA (0x0100) /* Single Address Access */ -#define MCF5206E_DCR_S_RW (0x0080) /* Single Address Access Read/Write Val */ -#define MCF5206E_DCR_SINC (0x0040) /* Source Increment */ -#define MCF5206E_DCR_SSIZE (0x0030) /* Source Size: */ -#define MCF5206E_DCR_SSIZE_LONG (0x0000) /* Longword (4 bytes) */ -#define MCF5206E_DCR_SSIZE_BYTE (0x0010) /* Byte */ -#define MCF5206E_DCR_SSIZE_WORD (0x0020) /* Word (2 bytes) */ -#define MCF5206E_DCR_SSIZE_LINE (0x0030) /* Line (16 bytes) */ -#define MCF5206E_DCR_DINC (0x0008) /* Destination Increment */ -#define MCF5206E_DCR_DSIZE (0x0006) /* Destination Size: */ -#define MCF5206E_DCR_DSIZE_LONG (0x0000) /* Longword (4 bytes) */ -#define MCF5206E_DCR_DSIZE_BYTE (0x0002) /* Byte */ -#define MCF5206E_DCR_DSIZE_WORD (0x0004) /* Word (2 bytes) */ -#define MCF5206E_DCR_DSIZE_LINE (0x0006) /* Line (16 bytes) */ -#define MCF5206E_DCR_START (0x0001) /* Start Transfer */ - -/* DMA Status Register */ -#define MCF5206E_DSR(mbar,chn) MCF5206E_REG8(mbar,0x210 + ((chn) * 0x40)) -#define MCF5206E_DSR_CE (0x40) /* Configuration Error has occured */ -#define MCF5206E_DSR_BES (0x20) /* Bus Error on Source */ -#define MCF5206E_DSR_BED (0x10) /* Bus Error on Destination */ -#define MCF5206E_DSR_REQ (0x04) /* Request */ -#define MCF5206E_DSR_BSY (0x02) /* Busy */ -#define MCF5206E_DSR_DONE (0x01) /* Transaction Done */ - -/* DMA Interrupt Vector Register */ -#define MCF5206E_DIVR(mbar,chn) MCF5206E_REG8(mbar,0x214 + ((chn) * 0x40)) - - -/*** System Integration Module -- MCF5206e User's Manual, Chapter 8 ***/ - -/* MBAR - Module Base Address Register */ -#define MCF5206E_MBAR_BA (0xFFFFFC00) /* Base Address */ -#define MCF5206E_MBAR_SC (0x00000010) /* Supervisor Code Space Mask */ -#define MCF5206E_MBAR_SD (0x00000008) /* Supervisor Data Space Mask */ -#define MCF5206E_MBAR_UC (0x00000004) /* User Code Space Mask */ -#define MCF5206E_MBAR_UD (0x00000002) /* User Data Space Mask */ -#define MCF5206E_MBAR_V (0x00000001) /* Contents of MBAR are valid */ - -/* SIM Configuration Register */ -#define MCF5206E_SIMR(mbar) MCF5206E_REG8(mbar,0x003) -#define MCF5206E_SIMR_FRZ1 (0x80) /* Disable Soft Wdog Timer when FREEZE */ -#define MCF5206E_SIMR_FRZ0 (0x40) /* Disable Bus Timeout monitor when FREEZE*/ -#define MCF5206E_SIMR_BL (0x01) /* Bus Lock Enable */ - -/* Interrupt numbers assignment */ -#define MCF5206E_INTR_EXT_IRQ1 (1) /* External IRQ1 */ -#define MCF5206E_INTR_EXT_IPL1 (1) /* External IPL1 */ -#define MCF5206E_INTR_EXT_IPL2 (2) /* External IPL2 */ -#define MCF5206E_INTR_EXT_IPL3 (3) /* External IPL3 */ -#define MCF5206E_INTR_EXT_IRQ4 (4) /* External IRQ4 */ -#define MCF5206E_INTR_EXT_IPL4 (4) /* External IPL4 */ -#define MCF5206E_INTR_EXT_IPL5 (5) /* External IPL5 */ -#define MCF5206E_INTR_EXT_IPL6 (6) /* External IPL6 */ -#define MCF5206E_INTR_EXT_IRQ7 (7) /* External IRQ7 */ -#define MCF5206E_INTR_EXT_IPL7 (7) /* External IPL7 */ -#define MCF5206E_INTR_SWT (8) /* Software Watchdog Timer */ -#define MCF5206E_INTR_TIMER_1 (9) /* Timer 1 interrupt */ -#define MCF5206E_INTR_TIMER_2 (10) /* Timer 2 interrupt */ -#define MCF5206E_INTR_MBUS (11) /* MBUS interrupt */ -#define MCF5206E_INTR_UART_1 (12) /* UART 1 interrupt */ -#define MCF5206E_INTR_UART_2 (13) /* UART 2 interrupt */ -#define MCF5206E_INTR_DMA_0 (14) /* DMA channel 0 interrupt */ -#define MCF5206E_INTR_DMA_1 (15) /* DMA channel 1 interrupt */ - -#define MCF5206E_INTR_BIT(n) (1 << (n)) - -/* Interrupt Control Registers (ICR1 - ICR15) */ -#define MCF5206E_ICR(mbar,n) MCF5206E_REG8(mbar,0x014 + (n) - 1) - -#define MCF5206E_ICR_AVEC (0x80) /* Autovector Enable */ -#define MCF5206E_ICR_IL (0x1c) /* Interrupt Level */ -#define MCF5206E_ICR_IL_S (2) -#define MCF5206E_ICR_IP (0x03) /* Interrupt Priority */ -#define MCF5206E_ICR_IP_S (0) - -/* Interrupt Mask Register */ -#define MCF5206E_IMR(mbar) MCF5206E_REG16(mbar,0x036) - -/* Interrupt Pending Register */ -#define MCF5206E_IPR(mbar) MCF5206E_REG16(mbar,0x03a) - -/* Reset Status Register */ -#define MCF5206E_RSR(mbar) MCF5206E_REG8(mbar,0x040) -#define MCF5206E_RSR_HRST (0x80) /* Hard Reset or System Reset */ -#define MCF5206E_RSR_SWTR (0x20) /* Software Watchdog Timer Reset */ - -/* System Protection Control Register */ -#define MCF5206E_SYPCR(mbar) MCF5206E_REG8(mbar,0x041) -#define MCF5206E_SYPCR_SWE (0x80) /* Software Watchdog Enable */ -#define MCF5206E_SYPCR_SWRI (0x40) /* Software Watchdog Reset/Interrupt Sel.*/ -#define MCF5206E_SYPCR_SWP (0x20) /* Software Watchdog Prescaler */ -#define MCF5206E_SYPCR_SWT (0x18) /* Software Watchdog Timing: */ -#define MCF5206E_SYPCR_SWT_S (3) -#define MCF5206E_SYPCR_SWT_9 (0x00) /* timeout = (1<<9)/sysfreq */ -#define MCF5206E_SYPCR_SWT_11 (0x08) /* timeout = (1<<11)/sysfreq */ -#define MCF5206E_SYPCR_SWT_13 (0x10) /* timeout = (1<<13)/sysfreq */ -#define MCF5206E_SYPCR_SWT_15 (0x18) /* timeout = (1<<15)/sysfreq */ -#define MCF5206E_SYPCR_SWT_18 (0x20) /* timeout = (1<<18)/sysfreq */ -#define MCF5206E_SYPCR_SWT_20 (0x28) /* timeout = (1<<20)/sysfreq */ -#define MCF5206E_SYPCR_SWT_22 (0x30) /* timeout = (1<<22)/sysfreq */ -#define MCF5206E_SYPCR_SWT_24 (0x38) /* timeout = (1<<24)/sysfreq */ -#define MCF5206E_SYPCR_BME (0x04) /* Bus Timeout Monitor Enable */ -#define MCF5206E_SYPCR_BMT (0x03) /* Bus Monitor Timing: */ -#define MCF5206E_SYPCR_BMT_1024 (0x00) /* timeout 1024 system clocks */ -#define MCF5206E_SYPCR_BMT_512 (0x01) /* timeout 512 system clocks */ -#define MCF5206E_SYPCR_BMT_256 (0x02) /* timeout 256 system clocks */ -#define MCF5206E_SYPCR_BMT_128 (0x03) /* timeout 128 system clocks */ - -/* Software Watchdog Interrupt Vector Register */ -#define MCF5206E_SWIVR(mbar) MCF5206E_REG8(mbar,0x042) - -/* Software Watchdog Service Register */ -#define MCF5206E_SWSR(mbar) MCF5206E_REG8(mbar,0x043) -#define MCF5206E_SWSR_KEY1 (0x55) -#define MCF5206E_SWSR_KEY2 (0xAA) - -/* Pin Assignment Register */ -#define MCF5206E_PAR(mbar) MCF5206E_REG16(mbar,0x0CA) -#define MCF5206E_PAR_PAR9 (0x200) -#define MCF5206E_PAR_PAR9_TOUT (0x000) /* Timer 0 output */ -#define MCF5206E_PAR_PAR9_DREQ1 (0x200) /* DMA channel 1 request */ -#define MCF5206E_PAR_PAR8 (0x100) -#define MCF5206E_PAR_PAR8_TIN0 (0x000) /* Timer 1 input */ -#define MCF5206E_PAR_PAR8_DREQ0 (0x100) /* DMA channel 0 request */ -#define MCF5206E_PAR_PAR7 (0x080) -#define MCF5206E_PAR_PAR7_RSTO (0x000) /* Reset output */ -#define MCF5206E_PAR_PAR7_UART2 (0x080) /* UART 2 RTS output */ -#define MCF5206E_PAR_PAR6 (0x040) -#define MCF5206E_PAR_PAR6_IRQ (0x000) /* IRQ7, IRQ4, IRQ1 */ -#define MCF5206E_PAR_PAR6_IPL (0x040) /* IPL2, IPL1, IPL0 */ -#define MCF5206E_PAR_PAR5 (0x020) -#define MCF5206E_PAR_PAR5_GPIO (0x000) /* General purpose I/O PP7-PP4 */ -#define MCF5206E_PAR_PAR5_PST (0x020) /* BDM signals PST3-PST0 */ -#define MCF5206E_PAR_PAR4 (0x010) -#define MCF5206E_PAR_PAR4_GPIO (0x000) /* General purpose I/O PP3-PP0 */ -#define MCF5206E_PAR_PAR4_DDATA (0x010) /* BDM signals DDATA3-DDATA0 */ -#define MCF5206E_PAR_PAR3 (0x008) -#define MCF5206E_PAR_PAR2 (0x004) -#define MCF5206E_PAR_PAR1 (0x002) -#define MCF5206E_PAR_PAR0 (0x001) -#define MCF5206E_PAR_WE0_WE1_WE2_WE3 (0x000) -#define MCF5206E_PAR_WE0_WE1_CS5_CS4 (0x001) -#define MCF5206E_PAR_WE0_WE1_CS5_A24 (0x002) -#define MCF5206E_PAR_WE0_WE1_A25_A24 (0x003) -#define MCF5206E_PAR_WE0_CS6_CS5_CS4 (0x004) -#define MCF5206E_PAR_WE0_CS6_CS5_A24 (0x005) -#define MCF5206E_PAR_WE0_CS6_A25_A24 (0x006) -#define MCF5206E_PAR_WE0_A26_A25_A24 (0x007) -#define MCF5206E_PAR_CS7_CS6_CS5_CS4 (0x008) -#define MCF5206E_PAR_CS7_CS6_CS4_A24 (0x009) -#define MCF5206E_PAR_CS7_CS6_A25_A24 (0x00A) -#define MCF5206E_PAR_CS7_A26_A25_A24 (0x00B) -#define MCF5206E_PAR_A27_A26_A25_A24 (0x00C) - -/* Bus Master Arbitration Control */ -#define MCF5206E_MARB(mbar) MCF5206E_REG8(mbar,0x007) -#define MCF5206E_MARB_NOARB (0x08) /* Arbiter operation disable */ -#define MCF5206E_MARB_ARBCTRL (0x04) /* Arb. order: Internal DMA, Coldfire */ - -/*** Chip Select Module -- MCF5206e User's Manual, Chapter 9 ***/ - -/* Chip Select Address Register */ -#define MCF5206E_CSAR(mbar,bank) MCF5206E_REG16(mbar,0x064 + ((bank) * 12)) - -/* Chip Select Mask Register */ -#define MCF5206E_CSMR(mbar,bank) MCF5206E_REG32(mbar,0x068 + ((bank) * 12)) -#define MCF5206E_CSMR_BAM (0xffff0000) /* Base Address Mask */ -#define MCF5206E_CSMR_BAM_S (16) -#define MCF5206E_CSMR_MASK_256M (0x0FFF0000) -#define MCF5206E_CSMR_MASK_128M (0x07FF0000) -#define MCF5206E_CSMR_MASK_64M (0x03FF0000) -#define MCF5206E_CSMR_MASK_32M (0x01FF0000) -#define MCF5206E_CSMR_MASK_16M (0x00FF0000) -#define MCF5206E_CSMR_MASK_8M (0x007F0000) -#define MCF5206E_CSMR_MASK_4M (0x003F0000) -#define MCF5206E_CSMR_MASK_2M (0x001F0000) -#define MCF5206E_CSMR_MASK_1M (0x000F0000) -#define MCF5206E_CSMR_MASK_1024K (0x000F0000) -#define MCF5206E_CSMR_MASK_512K (0x00070000) -#define MCF5206E_CSMR_MASK_256K (0x00030000) -#define MCF5206E_CSMR_MASK_128K (0x00010000) -#define MCF5206E_CSMR_MASK_64K (0x00000000) -#define MCF5206E_CSMR_CI (0x00000020) /* CPU Space Mask (CSMR1 only) */ -#define MCF5206E_CSMR_SC (0x00000010) /* Supervisor Code Space Mask */ -#define MCF5206E_CSMR_SD (0x00000008) /* Supervisor Data Space Mask */ -#define MCF5206E_CSMR_UC (0x00000004) /* User Code Space Mask */ -#define MCF5206E_CSMR_UD (0x00000002) /* User Data Space Mask */ - -/* Chip Select Control Register */ -#define MCF5206E_CSCR(mbar,bank) MCF5206E_REG16(mbar,0x6E + ((bank) * 12)) -#define MCF5206E_CSCR_WS (0x3c00) /* Wait States */ -#define MCF5206E_CSCR_WS_S (10) -#define MCF5206E_CSCR_WS0 (0x0000) /* 0 Wait States */ -#define MCF5206E_CSCR_WS1 (0x0400) /* 1 Wait States */ -#define MCF5206E_CSCR_WS2 (0x0800) /* 2 Wait States */ -#define MCF5206E_CSCR_WS3 (0x0C00) /* 3 Wait States */ -#define MCF5206E_CSCR_WS4 (0x1000) /* 4 Wait States */ -#define MCF5206E_CSCR_WS5 (0x1400) /* 5 Wait States */ -#define MCF5206E_CSCR_WS6 (0x1800) /* 6 Wait States */ -#define MCF5206E_CSCR_WS7 (0x1C00) /* 7 Wait States */ -#define MCF5206E_CSCR_WS8 (0x2000) /* 8 Wait States */ -#define MCF5206E_CSCR_WS9 (0x2400) /* 9 Wait States */ -#define MCF5206E_CSCR_WS10 (0x2800) /* 10 Wait States */ -#define MCF5206E_CSCR_WS11 (0x2C00) /* 11 Wait States */ -#define MCF5206E_CSCR_WS12 (0x3000) /* 12 Wait States */ -#define MCF5206E_CSCR_WS13 (0x3400) /* 13 Wait States */ -#define MCF5206E_CSCR_WS14 (0x3800) /* 14 Wait States */ -#define MCF5206E_CSCR_WS15 (0x3C00) /* 15 Wait States */ -#define MCF5206E_CSCR_BRST (0x0200) /* Burst Enable */ -#define MCF5206E_CSCR_AA (0x0100) /* Coldfire Core Auto Acknowledge - Enable */ -#define MCF5206E_CSCR_PS (0x00C0) /* Port Size */ -#define MCF5206E_CSCR_PS_S (6) -#define MCF5206E_CSCR_PS_32 (0x0000) /* Port Size = 32 bits */ -#define MCF5206E_CSCR_PS_8 (0x0040) /* Port Size = 8 bits */ -#define MCF5206E_CSCR_PS_16 (0x0080) /* Port Size = 16 bits */ -#define MCF5206E_CSCR_EMAA (0x0020) /* External Master Automatic Acknowledge - Enable */ -#define MCF5206E_CSCR_ASET (0x0010) /* Address Setup Enable */ -#define MCF5206E_CSCR_WRAH (0x0008) /* Write Address Hold Enable */ -#define MCF5206E_CSCR_RDAH (0x0004) /* Read Address Hold Enable */ -#define MCF5206E_CSCR_WR (0x0002) /* Write Enable */ -#define MCF5206E_CSCR_RD (0x0001) /* Read Enable */ - -/* Default Memory Control Register */ -#define MCF5206E_DMCR(mbar) MCF5206E_REG16(mbar, 0x0C6) - -/*** Parallel Port (GPIO) Module -- MCF5206e User's Manual, Chapter 10 ***/ - -/* Port A Data Direction Register */ -#define MCF5206E_PPDDR(mbar) MCF5206E_REG8(mbar,0x1C5) - -/* Port A Data Register */ -#define MCF5206E_PPDAT(mbar) MCF5206E_REG8(mbar,0x1C9) - -#define MCF5206E_PP_DAT0 (0x01) -#define MCF5206E_PP_DAT1 (0x02) -#define MCF5206E_PP_DAT2 (0x04) -#define MCF5206E_PP_DAT3 (0x08) -#define MCF5206E_PP_DAT4 (0x10) -#define MCF5206E_PP_DAT5 (0x20) -#define MCF5206E_PP_DAT6 (0x40) -#define MCF5206E_PP_DAT7 (0x80) - -/*** DRAM Controller -- MCF5206e User's Manual, Chapter 11 ***/ - -/* DRAM Controller Refresh Register */ -#define MCF5206E_DCRR(mbar) MCF5206E_REG16(mbar,0x046) - -/* DRAM Controller Timing Register */ -#define MCF5206E_DCTR(mbar) MCF5206E_REG16(mbar,0x04A) -#define MCF5206E_DCTR_DAEM (0x8000) /* Drive Multiplexed Address During - External Master DRAM Transfers */ -#define MCF5206E_DCTR_EDO (0x4000) /* Extended Data-Out Enable */ -#define MCF5206E_DCTR_RCD (0x1000) /* RAS-to-CAS Delay Time */ -#define MCF5206E_DCTR_RSH (0x0600) /* RAS Hold Time */ -#define MCF5206E_DCTR_RSH_0 (0x0000) /* See User's Manual for details */ -#define MCF5206E_DCTR_RSH_1 (0x0200) -#define MCF5206E_DCTR_RSH_2 (0x0400) -#define MCF5206E_DCTR_RP (0x0060) /* RAS Precharge Time */ -#define MCF5206E_DCTR_RP_15 (0x0000) /* RAS Precharges for 1.5 system clks */ -#define MCF5206E_DCTR_RP_25 (0x0020) /* RAS Precharges for 2.5 system clks */ -#define MCF5206E_DCTR_RP_35 (0x0040) /* RAS Precharges for 3.5 system clks */ -#define MCF5206E_DCTR_CAS (0x0008) /* Column Address Strobe Time */ -#define MCF5206E_DCTR_CP (0x0002) /* CAS Precharge Time */ -#define MCF5206E_DCTR_CSR (0x0001) /* CAS Setup Time for CAS before RAS - refresh */ - -/* DRAM Controller Address Registers */ -#define MCF5206E_DCAR(mbar,bank) MCF5206E_REG16(mbar,0x4C + ((bank) * 12)) - -/* DRAM Controller Mask Registers */ -#define MCF5206E_DCMR(mbar,bank) MCF5206E_REG32(mbar,0x50 + ((bank) * 12)) -#define MCF5206E_DCMR_BAM (0xffff0000) /* Base Address Mask */ -#define MCF5206E_DCMR_BAM_S (16) -#define MCF5206E_DCMR_MASK_256M (0x0FFE0000) -#define MCF5206E_DCMR_MASK_128M (0x07FE0000) -#define MCF5206E_DCMR_MASK_64M (0x03FE0000) -#define MCF5206E_DCMR_MASK_32M (0x01FE0000) -#define MCF5206E_DCMR_MASK_16M (0x00FE0000) -#define MCF5206E_DCMR_MASK_8M (0x007E0000) -#define MCF5206E_DCMR_MASK_4M (0x003E0000) -#define MCF5206E_DCMR_MASK_2M (0x001E0000) -#define MCF5206E_DCMR_MASK_1M (0x000E0000) -#define MCF5206E_DCMR_MASK_1024K (0x000E0000) -#define MCF5206E_DCMR_MASK_512K (0x00060000) -#define MCF5206E_DCMR_MASK_256K (0x00020000) -#define MCF5206E_DCMR_MASK_128K (0x00000000) -#define MCF5206E_DCMR_SC (0x00000010) /* Supervisor Code Space Mask */ -#define MCF5206E_DCMR_SD (0x00000008) /* Supervisor Data Space Mask */ -#define MCF5206E_DCMR_UC (0x00000004) /* User Code Space Mask */ -#define MCF5206E_DCMR_UD (0x00000002) /* User Data Space Mask */ - -/* DRAM Controller Control Register */ -#define MCF5206E_DCCR(mbar,bank) MCF5206E_REG8(mbar, 0x57 + ((bank) * 12)) -#define MCF5206E_DCCR_PS (0xC0) /* Port Size */ -#define MCF5206E_DCCR_PS_32 (0x00) /* 32 bit Port Size */ -#define MCF5206E_DCCR_PS_8 (0x40) /* 8 bit Port Size */ -#define MCF5206E_DCCR_PS_16 (0x80) /* 16 bit Port Size */ -#define MCF5206E_DCCR_BPS (0x30) /* Bank Page Size */ -#define MCF5206E_DCCR_BPS_512 (0x00) /* 512 Byte Page Size */ -#define MCF5206E_DCCR_BPS_1K (0x10) /* 1 KByte Page Size */ -#define MCF5206E_DCCR_BPS_2K (0x20) /* 2 KByte Page Size */ -#define MCF5206E_DCCR_PM (0x0C) /* Page Mode Select */ -#define MCF5206E_DCCR_PM_NORMAL (0x00) /* Normal Mode */ -#define MCF5206E_DCCR_PM_BURSTP (0x04) /* Burst Page Mode */ -#define MCF5206E_DCCR_PM_FASTP (0x0C) /* Fast Page Mode */ -#define MCF5206E_DCCR_WR (0x02) /* Write Enable */ -#define MCF5206E_DCCR_RD (0x01) /* Read Enable */ - -/*** UART Module -- MCF5206e User's Manual, Chapter 12 ***/ - -#define MCF5206E_UART_CHANNELS (2) -/* UART Mode Register */ -#define MCF5206E_UMR(mbar,n) MCF5206E_REG8(mbar,0x140 + (((n)-1) * 0x40)) -#define MCF5206E_UMR1_RXRTS (0x80) /* Receiver Request-to-Send - Control */ -#define MCF5206E_UMR1_RXIRQ (0x40) /* Receiver Interrupt Select */ -#define MCF5206E_UMR1_ERR (0x20) /* Error Mode */ -#define MCF5206E_UMR1_PM (0x1C) /* Parity Mode, Parity Type */ -#define MCF5206E_UMR1_PM_EVEN (0x00) /* Even Parity */ -#define MCF5206E_UMR1_PM_ODD (0x04) /* Odd Parity */ -#define MCF5206E_UMR1_PM_FORCE_LOW (0x08) /* Force parity low */ -#define MCF5206E_UMR1_PM_FORCE_HIGH (0x0C) /* Force parity high */ -#define MCF5206E_UMR1_PM_NO_PARITY (0x10) /* No Parity */ -#define MCF5206E_UMR1_PM_MULTI_DATA (0x18) /* Multidrop mode - data char */ -#define MCF5206E_UMR1_PM_MULTI_ADDR (0x1C) /* Multidrop mode - addr char */ -#define MCF5206E_UMR1_BC (0x03) /* Bits per Character */ -#define MCF5206E_UMR1_BC_5 (0x00) /* 5 bits per character */ -#define MCF5206E_UMR1_BC_6 (0x01) /* 6 bits per character */ -#define MCF5206E_UMR1_BC_7 (0x02) /* 7 bits per character */ -#define MCF5206E_UMR1_BC_8 (0x03) /* 8 bits per character */ - -#define MCF5206E_UMR2_CM (0xC0) /* Channel Mode */ -#define MCF5206E_UMR2_CM_NORMAL (0x00) /* Normal Mode */ -#define MCF5206E_UMR2_CM_AUTO_ECHO (0x40) /* Automatic Echo Mode */ -#define MCF5206E_UMR2_CM_LOCAL_LOOP (0x80) /* Local Loopback Mode */ -#define MCF5206E_UMR2_CM_REMOTE_LOOP (0xC0) /* Remote Loopback Modde */ -#define MCF5206E_UMR2_TXRTS (0x20) /* Transmitter Ready-to-Send op */ -#define MCF5206E_UMR2_TXCTS (0x10) /* Transmitter Clear-to-Send op */ -#define MCF5206E_UMR2_SB (0x0F) /* Stop Bit Length */ -#define MCF5206E_UMR2_SB_1 (0x07) /* 1 Stop Bit for 6-8 bits char */ -#define MCF5206E_UMR2_SB_15 (0x08) /* 1.5 Stop Bits for 6-8 bits chr*/ -#define MCF5206E_UMR2_SB_2 (0x0F) /* 2 Stop Bits for 6-8 bits char */ -#define MCF5206E_UMR2_SB5_1 (0x00) /* 1 Stop Bits for 5 bit char */ -#define MCF5206E_UMR2_SB5_15 (0x07) /* 1.5 Stop Bits for 5 bit char */ -#define MCF5206E_UMR2_SB5_2 (0x0F) /* 2 Stop Bits for 5 bit char */ - -/* UART Status Register (read only) */ -#define MCF5206E_USR(mbar,n) MCF5206E_REG8(mbar,0x144 + (((n)-1) * 0x40)) -#define MCF5206E_USR_RB (0x80) /* Received Break */ -#define MCF5206E_USR_FE (0x40) /* Framing Error */ -#define MCF5206E_USR_PE (0x20) /* Parity Error */ -#define MCF5206E_USR_OE (0x10) /* Overrun Error */ -#define MCF5206E_USR_TXEMP (0x08) /* Transmitter Empty */ -#define MCF5206E_USR_TXRDY (0x04) /* Transmitter Ready */ -#define MCF5206E_USR_FFULL (0x02) /* FIFO Full */ -#define MCF5206E_USR_RXRDY (0x01) /* Receiver Ready */ - -/* UART Clock Select Register (write only) */ -#define MCF5206E_UCSR(mbar,n) MCF5206E_REG8(mbar,0x144 + (((n)-1) * 0x40)) -#define MCF5206E_UCSR_RCS (0xF0) /* Receiver Clock Select */ -#define MCF5206E_UCSR_RCS_TIMER (0xD0) /* Timer */ -#define MCF5206E_UCSR_RCS_EXT16 (0xE0) /* External clk x16 */ -#define MCF5206E_UCSR_RCS_EXT (0xF0) /* External clk x1 */ -#define MCF5206E_UCSR_TCS (0x0F) /* Transmitter Clock Select */ -#define MCF5206E_UCSR_TCS_TIMER (0x0D) /* Timer */ -#define MCF5206E_UCSR_TCS_EXT16 (0x0E) /* External clk x16 */ -#define MCF5206E_UCSR_TCS_EXT (0x0F) /* External clk x1 */ - -/* UART Command Register (write only) */ -#define MCF5206E_UCR(mbar,n) MCF5206E_REG8(mbar,0x148 + (((n)-1) * 0x40)) -#define MCF5206E_UCR_MISC (0x70) /* Miscellaneous Commands: */ -#define MCF5206E_UCR_MISC_NOP (0x00) /* No Command */ -#define MCF5206E_UCR_MISC_RESET_MR (0x10) /* Reset Mode Register Ptr */ -#define MCF5206E_UCR_MISC_RESET_RX (0x20) /* Reset Receiver */ -#define MCF5206E_UCR_MISC_RESET_TX (0x30) /* Reset Transmitter */ -#define MCF5206E_UCR_MISC_RESET_ERR (0x40) /* Reset Error Status */ -#define MCF5206E_UCR_MISC_RESET_BRK (0x50) /* Reset Break-Change Interrupt */ -#define MCF5206E_UCR_MISC_START_BRK (0x60) /* Start Break */ -#define MCF5206E_UCR_MISC_STOP_BRK (0x70) /* Stop Break */ -#define MCF5206E_UCR_TC (0x0C) /* Transmitter Commands: */ -#define MCF5206E_UCR_TC_NOP (0x00) /* No Action Taken */ -#define MCF5206E_UCR_TC_ENABLE (0x04) /* Transmitter Enable */ -#define MCF5206E_UCR_TC_DISABLE (0x08) /* Transmitter Disable */ -#define MCF5206E_UCR_RC (0x03) /* Receiver Commands: */ -#define MCF5206E_UCR_RC_NOP (0x00) /* No Action Taken */ -#define MCF5206E_UCR_RC_ENABLE (0x01) /* Receiver Enable */ -#define MCF5206E_UCR_RC_DISABLE (0x02) /* Receiver Disable */ - -/* UART Receive Buffer (read only) */ -#define MCF5206E_URB(mbar,n) MCF5206E_REG8(mbar,0x14C + (((n)-1) * 0x40)) - -/* UART Transmit Buffer (write only) */ -#define MCF5206E_UTB(mbar,n) MCF5206E_REG8(mbar,0x14C + (((n)-1) * 0x40)) - -/* UART Input Port Change Register (read only) */ -#define MCF5206E_UIPCR(mbar,n) MCF5206E_REG8(mbar,0x150 + (((n)-1) * 0x40)) -#define MCF5206E_UIPCR_COS (0x10) /* Change of State at CTS input */ -#define MCF5206E_UIPCR_CTS (0x01) /* Current State of CTS */ - -/* UART Auxiliary Control Register (write only) */ -#define MCF5206E_UACR(mbar,n) MCF5206E_REG8(mbar,0x150 + (((n)-1) * 0x40)) -#define MCF5206E_UACR_IEC (0x01) /* Input Enable Control - generate interrupt - on CTS change */ - -/* UART Interrupt Status Register (read only) */ -#define MCF5206E_UISR(mbar,n) MCF5206E_REG8(mbar,0x154 + (((n)-1) * 0x40)) -#define MCF5206E_UISR_COS (0x80) /* Change of State has occured at CTS */ -#define MCF5206E_UISR_DB (0x04) /* Delta Break */ -#define MCF5206E_UISR_RXRDY (0x02) /* Receiver Ready or FIFO Full */ -#define MCF5206E_UISR_TXRDY (0x01) /* Transmitter Ready */ - -/* UART Interrupt Mask Register (write only) */ -#define MCF5206E_UIMR(mbar,n) MCF5206E_REG8(mbar,0x154 + (((n)-1) * 0x40)) -#define MCF5206E_UIMR_COS (0x80) /* Change of State interrupt enable */ -#define MCF5206E_UIMR_DB (0x04) /* Delta Break interrupt enable */ -#define MCF5206E_UIMR_FFULL (0x02) /* FIFO Full interrupt enable */ -#define MCF5206E_UIMR_TXRDY (0x01) /* Transmitter Ready Interrupt enable */ - -/* UART Baud Rate Generator Prescale MSB Register */ -#define MCF5206E_UBG1(mbar,n) MCF5206E_REG8(mbar,0x158 + (((n)-1) * 0x40)) - -/* UART Baud Rate Generator Prescale LSB Register */ -#define MCF5206E_UBG2(mbar,n) MCF5206E_REG8(mbar,0x15C + (((n)-1) * 0x40)) - -/* UART Interrupt Vector Register */ -#define MCF5206E_UIVR(mbar,n) MCF5206E_REG8(mbar,0x170 + (((n)-1) * 0x40)) - -/* UART Input Port Register (read only) */ -#define MCF5206E_UIP(mbar,n) MCF5206E_REG8(mbar,0x174 + (((n)-1) * 0x40)) -#define MCF5206E_UIP_CTS (0x01) /* Current state of CTS input */ - -/* UART Output Port Bit Set Command (address-triggered command, write) */ -#define MCF5206E_UOP1(mbar,n) MCF5206E_REG8(mbar,0x178 + (((n)-1) * 0x40)) - -/* UART Output Port Bit Reset Command (address-triggered command, write */ -#define MCF5206E_UOP0(mbar,n) MCF5206E_REG8(mbar,0x17C + (((n)-1) * 0x40)) - -/*** M-BUS (I2C) Module -- MCF5206e User's Manual, Chapter 13 ***/ - -/* M-Bus Address Register */ -#define MCF5206E_MADR(mbar) MCF5206E_REG8(mbar, 0x1E0) - -/* M-Bus Frequency Divider Register */ -#define MCF5206E_MFDR(mbar) MCF5206E_REG8(mbar, 0x1E4) - -/* M-Bus Control Register */ -#define MCF5206E_MBCR(mbar) MCF5206E_REG8(mbar, 0x1E8) -#define MCF5206E_MBCR_MEN (0x80) /* M-Bus Enable */ -#define MCF5206E_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */ -#define MCF5206E_MBCR_MSTA (0x20) /* Master Mode Selection */ -#define MCF5206E_MBCR_MTX (0x10) /* Transmit Mode Selection */ -#define MCF5206E_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */ -#define MCF5206E_MBCR_RSTA (0x04) /* Repeat Start */ - -/* M-Bus Status Register */ -#define MCF5206E_MBSR(mbar) MCF5206E_REG8(mbar, 0x1EC) -#define MCF5206E_MBSR_MCF (0x80) /* Data Transferring Bit */ -#define MCF5206E_MBSR_MAAS (0x40) /* Addressed as a Slave Bit */ -#define MCF5206E_MBSR_MBB (0x20) /* Bus Busy Bit */ -#define MCF5206E_MBSR_MAL (0x10) /* Arbitration Lost */ -#define MCF5206E_MBSR_SRW (0x04) /* Slave Read/Write */ -#define MCF5206E_MBSR_MIF (0x02) /* MBus Interrupt pending */ -#define MCF5206E_MBSR_RXAK (0x01) /* Received Acknowledge */ - -/* M-Bus Data I/O Register */ -#define MCF5206E_MBDR(mbar) MCF5206E_REG8(mbar, 0x1F0) - -/*** Timer Module -- MCF5206e User's Manual, Chapter 14 ***/ - -/* Timer Mode Register */ -#define MCF5206E_TMR(mbar,n) MCF5206E_REG16(mbar, 0x100 + (((n)-1)*0x20)) -#define MCF5206E_TMR_PS (0xFF00) /* Prescaler Value */ -#define MCF5206E_TMR_PS_S (8) -#define MCF5206E_TMR_CE (0x00C0) /* Capture Edge and Enable - Interrupt */ -#define MCF5206E_TMR_CE_ANY (0x00C0) /* Capture on any edge */ -#define MCF5206E_TMR_CE_FALL (0x0080) /* Capture on falling edge only */ -#define MCF5206E_TMR_CE_RISE (0x0040) /* Capture on rising edge only */ -#define MCF5206E_TMR_CE_NONE (0x0000) /* Disable Interrupt on capture - event */ -#define MCF5206E_TMR_OM (0x0020) /* Output Mode - Toggle output */ -#define MCF5206E_TMR_ORI (0x0010) /* Output Reference Interrupt - Enable */ -#define MCF5206E_TMR_FRR (0x0008) /* Free Run/Restart */ -#define MCF5206E_TMR_ICLK (0x0006) /* Input Clock Source */ -#define MCF5206E_TMR_ICLK_TIN (0x0006) /* TIN pin (falling edge) */ -#define MCF5206E_TMR_ICLK_DIV16 (0x0004) /* Master system clock divided - by 16 */ -#define MCF5206E_TMR_ICLK_MSCLK (0x0002) /* Master System Clock */ -#define MCF5206E_TMR_ICLK_STOP (0x0000) /* Stops counter */ -#define MCF5206E_TMR_RST (0x0001) /* Reset/Enable Timer */ - -/* Timer Reference Register */ -#define MCF5206E_TRR(mbar,n) MCF5206E_REG16(mbar, 0x104 + (((n)-1)*0x20)) - -/* Timer Capture Register */ -#define MCF5206E_TCR(mbar,n) MCF5206E_REG16(mbar, 0x108 + (((n)-1)*0x20)) - -/* Timer Counter Register */ -#define MCF5206E_TCN(mbar,n) MCF5206E_REG16(mbar, 0x10C + (((n)-1)*0x20)) - -/* Timer Event Register */ -#define MCF5206E_TER(mbar,n) MCF5206E_REG8(mbar, 0x111 + (((n)-1)*0x20)) -#define MCF5206E_TER_REF (0x02) /* Output Reference Event */ -#define MCF5206E_TER_CAP (0x01) /* Capture Event */ - - - -#endif diff --git a/c/src/lib/libcpu/m68k/mcf5206/include/mcfmbus.h b/c/src/lib/libcpu/m68k/mcf5206/include/mcfmbus.h deleted file mode 100644 index f70a70e483..0000000000 --- a/c/src/lib/libcpu/m68k/mcf5206/include/mcfmbus.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * MCF5206e MBUS module (I2C bus) driver header file - * - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov <vvv@oktet.ru> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __MCFBSP_MCFMBUS_H__ -#define __MCFBSP_MCFMBUS_H__ - -#include "mcf5206e.h" -#include "i2c.h" - -/* States of I2C machine */ -typedef enum mcfmbus_i2c_state { - STATE_IDLE, - STATE_ADDR_7, - STATE_ADDR_1_W, - STATE_ADDR_1_R, - STATE_SENDING, - STATE_RECEIVING -} mcfmbus_i2c_state; - -typedef struct mcfmbus { - uint32_t base; /* ColdFire internal peripherial base - address */ - enum mcfmbus_i2c_state state;/* State of I2C machine */ - i2c_message *msg; /* Pointer to the first message in transfer */ - int nmsg; /* Number of messages in transfer */ - i2c_message *cmsg; /* Current message */ - int byte; /* Byte number in current message */ - rtems_isr_entry oldisr; /* Old interrupt handler */ - rtems_id sema; /* MBUS semaphore */ - i2c_transfer_done done; /* Transfer done function */ - uintptr_t done_arg_ptr; /* Done function argument ptr */ -} mcfmbus; - -/* mcfmbus_initialize -- - * Initialize ColdFire MBUS I2C bus controller. - * - * PARAMETERS: - * i2c_bus - pointer to the bus descriptor structure - * base - ColdFire internal peripherial base address - * - * RETURNS: - * RTEMS_SUCCESSFUL, or RTEMS error code when initialization failed. - */ -rtems_status_code -mcfmbus_initialize(mcfmbus *i2c_bus, uint32_t base); - -/* mcfmbus_select_clock_divider -- - * Select divider for system clock which is used for I2C bus clock - * generation. Not each divider can be selected for I2C bus; this - * function select nearest larger or equal divider, or maximum - * possible divider, if passed value greater. - * - * PARAMETERS: - * i2c_bus - pointer to the bus descriptor structure - * divider - system frequency divider for I2C serial clock. - * - * RETURNS: - * RTEMS_SUCCESSFUL, if operation performed successfully, or - * RTEMS error code when failed. - */ -rtems_status_code -mcfmbus_select_clock_divider(mcfmbus *i2c_bus, int divider); - -/* mcfmbus_i2c_transfer -- - * Initiate multiple-messages transfer over I2C bus via ColdFire MBUS - * controller. - * - * PARAMETERS: - * bus - pointer to MBUS controller descriptor - * nmsg - number of messages - * msg - pointer to messages array - * done - function which is called when transfer is finished - * done_arg_ptr - arbitrary argument ptr passed to done funciton - * - * RETURNS: - * RTEMS_SUCCESSFUL if transfer initiated successfully, or error - * code when failed. - */ -rtems_status_code -mcfmbus_i2c_transfer(mcfmbus *bus, int nmsg, i2c_message *msg, - i2c_transfer_done done, void *done_arg_ptr); - -/* mcfmbus_i2c_done -- - * Close ColdFire MBUS I2C bus controller and release all resources. - * - * PARAMETERS: - * bus - pointer to MBUS controller descriptor - * - * RETURNS: - * RTEMS_SUCCESSFUL, if transfer initiated successfully, or error - * code when failed. - */ -rtems_status_code -mcfmbus_i2c_done(mcfmbus *i2c_bus); - -/* mcfmbus_i2c_interrupt_handler -- - * ColdFire MBUS I2C bus controller interrupt handler. This function - * called from real interrupt handler, and pointer to MBUS descriptor - * structure passed to this function. - * - * PARAMETERS: - * bus - pointert to the bus descriptor structure - * - * RETURNS: - * none - */ -void mcfmbus_i2c_interrupt_handler(mcfmbus *bus); - -/* mcfmbus_poll -- - * MBUS module poll routine; used to poll events when I2C driver - * operates in poll-driven mode. - * - * PARAMETERS: - * none - * - * RETURNS: - * none - */ -void mcfmbus_poll(mcfmbus *bus); - -#endif /* __MCFBSP_MCFMBUS_H__ */ diff --git a/c/src/lib/libcpu/m68k/mcf5206/include/mcfuart.h b/c/src/lib/libcpu/m68k/mcf5206/include/mcfuart.h deleted file mode 100644 index bd9df5bb56..0000000000 --- a/c/src/lib/libcpu/m68k/mcf5206/include/mcfuart.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Generic UART Serial driver for Motorola Coldfire processors definitions - * - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russian Fed. - * Author: Victor V. Vengerov <vvv@oktet.ru> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __MCFUART_H__ -#define __MCFUART_H__ - -#include <termios.h> -#include "bsp.h" -#include "mcf5206e.h" - -/* - * The MCF5206e System Clock Frequency; 54MHz default - */ -#ifndef SYSTEM_CLOCK_FREQUENCY -#define SYSTEM_CLOCK_FREQUENCY BSP_SYSTEM_FREQUENCY -#endif - -/* - * The following structure is a descriptor of single UART channel. - * It contains the initialization information about channel and - * current operating values - */ -typedef struct mcfuart { - uint32_t chn; /* UART channel number */ - uint8_t intvec; /* UART interrupt vector number, or - 0 if polled I/O */ - void *tty; /* termios channel descriptor */ - - volatile const char *tx_buf; /* Transmit buffer from termios */ - volatile uint32_t tx_buf_len; /* Transmit buffer length */ - volatile uint32_t tx_ptr; /* Index of next char to transmit*/ - rtems_isr_entry old_handler; /* Saved interrupt handler */ - - tcflag_t c_iflag; /* termios input mode flags */ - bool parerr_mark_flag; /* Parity error processing - state */ -} mcfuart; - -/* mcfuart_init -- - * This function verifies the input parameters and perform initialization - * of the Motorola Coldfire on-chip UART descriptor structure. - * - */ -rtems_status_code -mcfuart_init(mcfuart *uart, void *tty, uint8_t intvec, - uint32_t chn); - -/* mcfuart_reset -- - * This function perform the hardware initialization of Motorola - * Coldfire processor on-chip UART controller using parameters - * filled by the mcfuart_init function. - */ -rtems_status_code -mcfuart_reset(mcfuart *uart); - -/* mcfuart_disable -- - * This function disable the operations on Motorola Coldfire UART - * controller - */ -rtems_status_code -mcfuart_disable(mcfuart *uart); - -/* mcfuart_set_attributes -- - * This function parse the termios attributes structure and perform - * the appropriate settings in hardware. - */ -int -mcfuart_set_attributes(mcfuart *mcf, const struct termios *t); - -/* mcfuart_poll_read -- - * This function tried to read character from MCF UART and perform - * error handling. - */ -int -mcfuart_poll_read(mcfuart *uart); - -/* mcfuart_interrupt_write -- - * This function initiate transmitting of the buffer in interrupt mode. - */ -ssize_t -mcfuart_interrupt_write(mcfuart *uart, const char *buf, size_t len); - -/* mcfuart_poll_write -- - * This function transmit buffer byte-by-byte in polling mode. - */ -ssize_t -mcfuart_poll_write(mcfuart *uart, const char *buf, size_t len); - -/* mcfuart_stop_remote_tx -- - * This function stop data flow from remote device. - */ -int -mcfuart_stop_remote_tx(mcfuart *uart); - -/* mcfuart_start_remote_tx -- - * This function resume data flow from remote device. - */ -int -mcfuart_start_remote_tx(mcfuart *uart); - -#endif diff --git a/c/src/lib/libcpu/m68k/mcf5223x/include/mcf5223x.h b/c/src/lib/libcpu/m68k/mcf5223x/include/mcf5223x.h deleted file mode 100644 index 0886105b17..0000000000 --- a/c/src/lib/libcpu/m68k/mcf5223x/include/mcf5223x.h +++ /dev/null @@ -1,3362 +0,0 @@ -/* - * File: mcf5223x.h - * Purpose: Register and bit definitions - */ - -#ifndef __MCF5223x_H__ -#define __MCF5223x_H__ - -typedef volatile unsigned char vuint8; -typedef volatile unsigned short vuint16; -typedef volatile unsigned long vuint32; - -/********************************************************************* -* -* System Control Module (SCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x000000])) -#define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x000008])) -#define MCF_SCM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) -#define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x000010])) -#define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x000011])) -#define MCF_SCM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) -#define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x000013])) -#define MCF_SCM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) -#define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x00001C])) -#define MCF_SCM_MPR (*(vuint32*)(&__IPSBAR[0x000020])) -#define MCF_SCM_PPMRS (*(vuint8 *)(&__IPSBAR[0x000021])) -#define MCF_SCM_PPMRC (*(vuint8 *)(&__IPSBAR[0x000022])) -#define MCF_SCM_IPSBMT (*(vuint8 *)(&__IPSBAR[0x000023])) -#define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x000024])) -#define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x000025])) -#define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x000026])) -#define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x000027])) -#define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x000028])) -#define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x000029])) -#define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x00002A])) -#define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x00002B])) -#define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x00002C])) -#define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x000030])) -#define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x000031])) - -/* Bit definitions and macros for MCF_SCM_IPSBAR */ -#define MCF_SCM_IPSBAR_V (0x00000001) -#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000) - -/* Bit definitions and macros for MCF_SCM_RAMBAR */ -#define MCF_SCM_RAMBAR_BDE (0x00000200) -#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000) - -/* Bit definitions and macros for MCF_SCM_CRSR */ -#define MCF_SCM_CRSR_CWDR (0x20) -#define MCF_SCM_CRSR_EXT (0x80) - -/* Bit definitions and macros for MCF_SCM_CWCR */ -#define MCF_SCM_CWCR_CWTIC (0x01) -#define MCF_SCM_CWCR_CWTAVAL (0x02) -#define MCF_SCM_CWCR_CWTA (0x04) -#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3) -#define MCF_SCM_CWCR_CWRI (0x40) -#define MCF_SCM_CWCR_CWE (0x80) - -/* Bit definitions and macros for MCF_SCM_LPICR */ -#define MCF_SCM_LPICR_XIPL(x) (((x)&0x07)<<4) -#define MCF_SCM_LPICR_ENBSTOP (0x80) - -/* Bit definitions and macros for MCF_SCM_CWSR */ -#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_SCM_PPMRH */ -#define MCF_SCM_PPMRH_CDPORTS (0x00000001) -#define MCF_SCM_PPMRH_CDEPORT (0x00000002) -#define MCF_SCM_PPMRH_CDPIT0 (0x00000008) -#define MCF_SCM_PPMRH_CDPIT1 (0x00000010) -#define MCF_SCM_PPMRH_CDADC (0x00000080) -#define MCF_SCM_PPMRH_CDGPT (0x00000100) -#define MCF_SCM_PPMRH_CDPWN (0x00000200) -#define MCF_SCM_PPMRH_CDFCAN (0x00000400) -#define MCF_SCM_PPMRH_CDCFM (0x00000800) - -/* Bit definitions and macros for MCF_SCM_PPMRL */ -#define MCF_SCM_PPMRL_CDG (0x00000002) -#define MCF_SCM_PPMRL_CDEIM (0x00000008) -#define MCF_SCM_PPMRL_CDDMA (0x00000010) -#define MCF_SCM_PPMRL_CDUART0 (0x00000020) -#define MCF_SCM_PPMRL_CDUART1 (0x00000040) -#define MCF_SCM_PPMRL_CDUART2 (0x00000080) -#define MCF_SCM_PPMRL_CDI2C (0x00000200) -#define MCF_SCM_PPMRL_CDQSPI (0x00000400) -#define MCF_SCM_PPMRL_CDDTIM0 (0x00002000) -#define MCF_SCM_PPMRL_CDDTIM1 (0x00004000) -#define MCF_SCM_PPMRL_CDDTIM2 (0x00008000) -#define MCF_SCM_PPMRL_CDDTIM3 (0x00010000) -#define MCF_SCM_PPMRL_CDINTC0 (0x00020000) - -/* Bit definitions and macros for MCF_SCM_MPARK */ -#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_MPARK_PRKLAST (0x00001000) -#define MCF_SCM_MPARK_TIMEOUT (0x00002000) -#define MCF_SCM_MPARK_FIXED (0x00004000) -#define MCF_SCM_MPARK_M0PRTY(x) (((x)&0x00000003)<<18) -#define MCF_SCM_MPARK_M2PRTY(x) (((x)&0x00000003)<<20) -#define MCF_SCM_MPARK_M3PRTY(x) (((x)&0x00000003)<<22) -#define MCF_SCM_MPARK_BCR24BIT (0x01000000) -#define MCF_SCM_MPARK_M2_P_EN (0x02000000) - -/* Bit definitions and macros for MCF_SCM_PPMRS */ -#define MCF_SCM_PPMRS_DISABLE_ALL (64) -#define MCF_SCM_PPMRS_DISABLE_CFM (43) -#define MCF_SCM_PPMRS_DISABLE_CAN (42) -#define MCF_SCM_PPMRS_DISABLE_PWM (41) -#define MCF_SCM_PPMRS_DISABLE_GPT (40) -#define MCF_SCM_PPMRS_DISABLE_ADC (39) -#define MCF_SCM_PPMRS_DISABLE_PIT1 (36) -#define MCF_SCM_PPMRS_DISABLE_PIT0 (35) -#define MCF_SCM_PPMRS_DISABLE_EPORT (33) -#define MCF_SCM_PPMRS_DISABLE_PORTS (32) -#define MCF_SCM_PPMRS_DISABLE_INTC (17) -#define MCF_SCM_PPMRS_DISABLE_DTIM3 (16) -#define MCF_SCM_PPMRS_DISABLE_DTIM2 (15) -#define MCF_SCM_PPMRS_DISABLE_DTIM1 (14) -#define MCF_SCM_PPMRS_DISABLE_DTIM0 (13) -#define MCF_SCM_PPMRS_DISABLE_QSPI (10) -#define MCF_SCM_PPMRS_DISABLE_I2C (9) -#define MCF_SCM_PPMRS_DISABLE_UART2 (7) -#define MCF_SCM_PPMRS_DISABLE_UART1 (6) -#define MCF_SCM_PPMRS_DISABLE_UART0 (5) -#define MCF_SCM_PPMRS_DISABLE_DMA (4) -#define MCF_SCM_PPMRS_SET_CDG (1) - -/* Bit definitions and macros for MCF_SCM_PPMRC */ -#define MCF_SCM_PPMRC_ENABLE_ALL (64) -#define MCF_SCM_PPMRC_ENABLE_CFM (43) -#define MCF_SCM_PPMRC_ENABLE_CAN (42) -#define MCF_SCM_PPMRC_ENABLE_PWM (41) -#define MCF_SCM_PPMRC_ENABLE_GPT (40) -#define MCF_SCM_PPMRC_ENABLE_ADC (39) -#define MCF_SCM_PPMRC_ENABLE_PIT1 (36) -#define MCF_SCM_PPMRC_ENABLE_PIT0 (35) -#define MCF_SCM_PPMRC_ENABLE_EPORT (33) -#define MCF_SCM_PPMRC_ENABLE_PORTS (32) -#define MCF_SCM_PPMRC_ENABLE_INTC (17) -#define MCF_SCM_PPMRC_ENABLE_DTIM3 (16) -#define MCF_SCM_PPMRC_ENABLE_DTIM2 (15) -#define MCF_SCM_PPMRC_ENABLE_DTIM1 (14) -#define MCF_SCM_PPMRC_ENABLE_DTIM0 (13) -#define MCF_SCM_PPMRC_ENABLE_QSPI (10) -#define MCF_SCM_PPMRC_ENABLE_I2C (9) -#define MCF_SCM_PPMRC_ENABLE_UART2 (7) -#define MCF_SCM_PPMRC_ENABLE_UART1 (6) -#define MCF_SCM_PPMRC_ENABLE_UART0 (5) -#define MCF_SCM_PPMRC_ENABLE_DMA (4) -#define MCF_SCM_PPMRC_CLEAR_CDG (1) - - -/********************************************************************* -* -* Power Management Module (PMM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PMM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) -#define MCF_PMM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) -#define MCF_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) -#define MCF_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) - -/* Bit definitions and macros for MCF_PMM_PPMRH */ -#define MCF_PMM_PPMRH_CDPORTS (0x00000001) -#define MCF_PMM_PPMRH_CDEPORT (0x00000002) -#define MCF_PMM_PPMRH_CDPIT0 (0x00000008) -#define MCF_PMM_PPMRH_CDPIT1 (0x00000010) -#define MCF_PMM_PPMRH_CDADC (0x00000080) -#define MCF_PMM_PPMRH_CDGPT (0x00000100) -#define MCF_PMM_PPMRH_CDPWM (0x00000200) -#define MCF_PMM_PPMRH_CDFCAN (0x00000400) -#define MCF_PMM_PPMRH_CDCFM (0x00000800) - -/* Bit definitions and macros for MCF_PMM_PPMRL */ -#define MCF_PMM_PPMRL_CDG (0x00000002) -#define MCF_PMM_PPMRL_CDEIM (0x00000008) -#define MCF_PMM_PPMRL_CDDMA (0x00000010) -#define MCF_PMM_PPMRL_CDUART0 (0x00000020) -#define MCF_PMM_PPMRL_CDUART1 (0x00000040) -#define MCF_PMM_PPMRL_CDUART2 (0x00000080) -#define MCF_PMM_PPMRL_CDI2C (0x00000200) -#define MCF_PMM_PPMRL_CDQSPI (0x00000400) -#define MCF_PMM_PPMRL_CDDTIM0 (0x00002000) -#define MCF_PMM_PPMRL_CDDTIM1 (0x00004000) -#define MCF_PMM_PPMRL_CDDTIM2 (0x00008000) -#define MCF_PMM_PPMRL_CDDTIM3 (0x00010000) -#define MCF_PMM_PPMRL_CDINTC0 (0x00020000) - -/* Bit definitions and macros for MCF_PMM_LPICR */ -#define MCF_PMM_LPICR_XIPL(x) (((x)&0x07)<<4) -#define MCF_PMM_LPICR_ENBSTOP (0x80) - -/* Bit definitions and macros for MCF_PMM_LPCR */ -#define MCF_PMM_LPCR_LVDSE (0x02) -#define MCF_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF_PMM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF_PMM_LPCR_LPMD_STOP (0xC0) -#define MCF_PMM_LPCR_LPMD_WAIT (0x80) -#define MCF_PMM_LPCR_LPMD_DOZE (0x40) -#define MCF_PMM_LPCR_LPMD_RUN (0x00) - - -/********************************************************************* -* -* DMA Controller Module (DMA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_DMA_DMAREQC (*(vuint32*)(&__IPSBAR[0x000014])) -#define MCF_DMA_SAR0 (*(vuint32*)(&__IPSBAR[0x000100])) -#define MCF_DMA_SAR1 (*(vuint32*)(&__IPSBAR[0x000110])) -#define MCF_DMA_SAR2 (*(vuint32*)(&__IPSBAR[0x000120])) -#define MCF_DMA_SAR3 (*(vuint32*)(&__IPSBAR[0x000130])) -#define MCF_DMA_SAR(x) (*(vuint32*)(&__IPSBAR[0x000100+((x)*0x010)])) -#define MCF_DMA_DAR0 (*(vuint32*)(&__IPSBAR[0x000104])) -#define MCF_DMA_DAR1 (*(vuint32*)(&__IPSBAR[0x000114])) -#define MCF_DMA_DAR2 (*(vuint32*)(&__IPSBAR[0x000124])) -#define MCF_DMA_DAR3 (*(vuint32*)(&__IPSBAR[0x000134])) -#define MCF_DMA_DAR(x) (*(vuint32*)(&__IPSBAR[0x000104+((x)*0x010)])) -#define MCF_DMA_DSR0 (*(vuint8 *)(&__IPSBAR[0x000108])) -#define MCF_DMA_DSR1 (*(vuint8 *)(&__IPSBAR[0x000118])) -#define MCF_DMA_DSR2 (*(vuint8 *)(&__IPSBAR[0x000128])) -#define MCF_DMA_DSR3 (*(vuint8 *)(&__IPSBAR[0x000138])) -#define MCF_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x000108+((x)*0x010)])) -#define MCF_DMA_BCR0 (*(vuint32*)(&__IPSBAR[0x000108])) -#define MCF_DMA_BCR1 (*(vuint32*)(&__IPSBAR[0x000118])) -#define MCF_DMA_BCR2 (*(vuint32*)(&__IPSBAR[0x000128])) -#define MCF_DMA_BCR3 (*(vuint32*)(&__IPSBAR[0x000138])) -#define MCF_DMA_BCR(x) (*(vuint32*)(&__IPSBAR[0x000108+((x)*0x010)])) -#define MCF_DMA_DCR0 (*(vuint32*)(&__IPSBAR[0x00010C])) -#define MCF_DMA_DCR1 (*(vuint32*)(&__IPSBAR[0x00011C])) -#define MCF_DMA_DCR2 (*(vuint32*)(&__IPSBAR[0x00012C])) -#define MCF_DMA_DCR3 (*(vuint32*)(&__IPSBAR[0x00013C])) -#define MCF_DMA_DCR(x) (*(vuint32*)(&__IPSBAR[0x00010C+((x)*0x010)])) - -/* Bit definitions and macros for MCF_DMA_DMAREQC */ -#define MCF_DMA_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) -#define MCF_DMA_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) -#define MCF_DMA_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) -#define MCF_DMA_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) -#define MCF_DMA_DMAREQC_DMAREQC_EXT(x) (((x)&0x0000000F)<<16) - -/* Bit definitions and macros for MCF_DMA_SAR */ -#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DMA_DAR */ -#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DMA_DSR */ -#define MCF_DMA_DSR_DONE (0x01) -#define MCF_DMA_DSR_BSY (0x02) -#define MCF_DMA_DSR_REQ (0x04) -#define MCF_DMA_DSR_BED (0x10) -#define MCF_DMA_DSR_BES (0x20) -#define MCF_DMA_DSR_CE (0x40) - -/* Bit definitions and macros for MCF_DMA_BCR */ -#define MCF_DMA_BCR_BCR(x) (((x)&0x00FFFFFF)<<0) -#define MCF_DMA_BCR_DSR(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_DMA_DCR */ -#define MCF_DMA_DCR_LCH2(x) (((x)&0x00000003)<<0) -#define MCF_DMA_DCR_LCH1(x) (((x)&0x00000003)<<2) -#define MCF_DMA_DCR_LINKCC(x) (((x)&0x00000003)<<4) -#define MCF_DMA_DCR_D_REQ (0x00000080) -#define MCF_DMA_DCR_DMOD(x) (((x)&0x0000000F)<<8) -#define MCF_DMA_DCR_SMOD(x) (((x)&0x0000000F)<<12) -#define MCF_DMA_DCR_START (0x00010000) -#define MCF_DMA_DCR_DSIZE(x) (((x)&0x00000003)<<17) -#define MCF_DMA_DCR_DINC (0x00080000) -#define MCF_DMA_DCR_SSIZE(x) (((x)&0x00000003)<<20) -#define MCF_DMA_DCR_SINC (0x00400000) -#define MCF_DMA_DCR_BWC(x) (((x)&0x00000007)<<25) -#define MCF_DMA_DCR_AA (0x10000000) -#define MCF_DMA_DCR_CS (0x20000000) -#define MCF_DMA_DCR_EEXT (0x40000000) -#define MCF_DMA_DCR_INT (0x80000000) -#define MCF_DMA_DCR_BWC_16K (0x1) -#define MCF_DMA_DCR_BWC_32K (0x2) -#define MCF_DMA_DCR_BWC_64K (0x3) -#define MCF_DMA_DCR_BWC_128K (0x4) -#define MCF_DMA_DCR_BWC_256K (0x5) -#define MCF_DMA_DCR_BWC_512K (0x6) -#define MCF_DMA_DCR_BWC_1024K (0x7) -#define MCF_DMA_DCR_DMOD_DIS (0x0) -#define MCF_DMA_DCR_DMOD_16 (0x1) -#define MCF_DMA_DCR_DMOD_32 (0x2) -#define MCF_DMA_DCR_DMOD_64 (0x3) -#define MCF_DMA_DCR_DMOD_128 (0x4) -#define MCF_DMA_DCR_DMOD_256 (0x5) -#define MCF_DMA_DCR_DMOD_512 (0x6) -#define MCF_DMA_DCR_DMOD_1K (0x7) -#define MCF_DMA_DCR_DMOD_2K (0x8) -#define MCF_DMA_DCR_DMOD_4K (0x9) -#define MCF_DMA_DCR_DMOD_8K (0xA) -#define MCF_DMA_DCR_DMOD_16K (0xB) -#define MCF_DMA_DCR_DMOD_32K (0xC) -#define MCF_DMA_DCR_DMOD_64K (0xD) -#define MCF_DMA_DCR_DMOD_128K (0xE) -#define MCF_DMA_DCR_DMOD_256K (0xF) -#define MCF_DMA_DCR_SMOD_DIS (0x0) -#define MCF_DMA_DCR_SMOD_16 (0x1) -#define MCF_DMA_DCR_SMOD_32 (0x2) -#define MCF_DMA_DCR_SMOD_64 (0x3) -#define MCF_DMA_DCR_SMOD_128 (0x4) -#define MCF_DMA_DCR_SMOD_256 (0x5) -#define MCF_DMA_DCR_SMOD_512 (0x6) -#define MCF_DMA_DCR_SMOD_1K (0x7) -#define MCF_DMA_DCR_SMOD_2K (0x8) -#define MCF_DMA_DCR_SMOD_4K (0x9) -#define MCF_DMA_DCR_SMOD_8K (0xA) -#define MCF_DMA_DCR_SMOD_16K (0xB) -#define MCF_DMA_DCR_SMOD_32K (0xC) -#define MCF_DMA_DCR_SMOD_64K (0xD) -#define MCF_DMA_DCR_SMOD_128K (0xE) -#define MCF_DMA_DCR_SMOD_256K (0xF) -#define MCF_DMA_DCR_SSIZE_LONG (0x0) -#define MCF_DMA_DCR_SSIZE_BYTE (0x1) -#define MCF_DMA_DCR_SSIZE_WORD (0x2) -#define MCF_DMA_DCR_SSIZE_LINE (0x3) -#define MCF_DMA_DCR_DSIZE_LONG (0x0) -#define MCF_DMA_DCR_DSIZE_BYTE (0x1) -#define MCF_DMA_DCR_DSIZE_WORD (0x2) -#define MCF_DMA_DCR_DSIZE_LINE (0x3) -#define MCF_DMA_DCR_LCH1_CH0 (0x0) -#define MCF_DMA_DCR_LCH1_CH1 (0x1) -#define MCF_DMA_DCR_LCH1_CH2 (0x2) -#define MCF_DMA_DCR_LCH1_CH3 (0x3) -#define MCF_DMA_DCR_LCH2_CH0 (0x0) -#define MCF_DMA_DCR_LCH2_CH1 (0x1) -#define MCF_DMA_DCR_LCH2_CH2 (0x2) -#define MCF_DMA_DCR_LCH2_CH3 (0x3) - - -/********************************************************************* -* -* Universal Asynchronous Receiver Transmitter (UART) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_UART0_UMR (*(vuint8 *)(&__IPSBAR[0x000200])) -#define MCF_UART0_USR (*(vuint8 *)(&__IPSBAR[0x000204])) -#define MCF_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x000204])) -#define MCF_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x000208])) -#define MCF_UART0_URB (*(vuint8 *)(&__IPSBAR[0x00020C])) -#define MCF_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x00020C])) -#define MCF_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x000210])) -#define MCF_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x000210])) -#define MCF_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x000214])) -#define MCF_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x000214])) -#define MCF_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x000218])) -#define MCF_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x00021C])) -#define MCF_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x000234])) -#define MCF_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x000238])) -#define MCF_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x00023C])) -#define MCF_UART1_UMR (*(vuint8 *)(&__IPSBAR[0x000240])) -#define MCF_UART1_USR (*(vuint8 *)(&__IPSBAR[0x000244])) -#define MCF_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x000244])) -#define MCF_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x000248])) -#define MCF_UART1_URB (*(vuint8 *)(&__IPSBAR[0x00024C])) -#define MCF_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x00024C])) -#define MCF_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x000250])) -#define MCF_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x000250])) -#define MCF_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x000254])) -#define MCF_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x000254])) -#define MCF_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x000258])) -#define MCF_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x00025C])) -#define MCF_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x000274])) -#define MCF_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x000278])) -#define MCF_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x00027C])) -#define MCF_UART2_UMR (*(vuint8 *)(&__IPSBAR[0x000280])) -#define MCF_UART2_USR (*(vuint8 *)(&__IPSBAR[0x000284])) -#define MCF_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x000284])) -#define MCF_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x000288])) -#define MCF_UART2_URB (*(vuint8 *)(&__IPSBAR[0x00028C])) -#define MCF_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x00028C])) -#define MCF_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x000290])) -#define MCF_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x000290])) -#define MCF_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x000294])) -#define MCF_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x000294])) -#define MCF_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x000298])) -#define MCF_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x00029C])) -#define MCF_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x0002B4])) -#define MCF_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x0002B8])) -#define MCF_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x0002BC])) -#define MCF_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x000200+((x)*0x040)])) -#define MCF_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x000208+((x)*0x040)])) -#define MCF_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x000218+((x)*0x040)])) -#define MCF_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x00021C+((x)*0x040)])) -#define MCF_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x000234+((x)*0x040)])) -#define MCF_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x000238+((x)*0x040)])) -#define MCF_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x00023C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_UART_UMR */ -#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) -#define MCF_UART_UMR_PT (0x04) -#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) -#define MCF_UART_UMR_ERR (0x20) -#define MCF_UART_UMR_RXIRQ (0x40) -#define MCF_UART_UMR_RXRTS (0x80) -#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) -#define MCF_UART_UMR_TXCTS (0x10) -#define MCF_UART_UMR_TXRTS (0x20) -#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) -#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) -#define MCF_UART_UMR_PM_MULTI_DATA (0x18) -#define MCF_UART_UMR_PM_NONE (0x10) -#define MCF_UART_UMR_PM_FORCE_HI (0x0C) -#define MCF_UART_UMR_PM_FORCE_LO (0x08) -#define MCF_UART_UMR_PM_ODD (0x04) -#define MCF_UART_UMR_PM_EVEN (0x00) -#define MCF_UART_UMR_BC_5 (0x00) -#define MCF_UART_UMR_BC_6 (0x01) -#define MCF_UART_UMR_BC_7 (0x02) -#define MCF_UART_UMR_BC_8 (0x03) -#define MCF_UART_UMR_CM_NORMAL (0x00) -#define MCF_UART_UMR_CM_ECHO (0x40) -#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) -#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) -#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) -#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) -#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF_UART_USR */ -#define MCF_UART_USR_RXRDY (0x01) -#define MCF_UART_USR_FFULL (0x02) -#define MCF_UART_USR_TXRDY (0x04) -#define MCF_UART_USR_TXEMP (0x08) -#define MCF_UART_USR_OE (0x10) -#define MCF_UART_USR_PE (0x20) -#define MCF_UART_USR_FE (0x40) -#define MCF_UART_USR_RB (0x80) - -/* Bit definitions and macros for MCF_UART_UCSR */ -#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) -#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) -#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) -#define MCF_UART_UCSR_RCS_CTM16 (0xE0) -#define MCF_UART_UCSR_RCS_CTM (0xF0) -#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) -#define MCF_UART_UCSR_TCS_CTM16 (0x0E) -#define MCF_UART_UCSR_TCS_CTM (0x0F) - -/* Bit definitions and macros for MCF_UART_UCR */ -#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) -#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) -#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) -#define MCF_UART_UCR_NONE (0x00) -#define MCF_UART_UCR_STOP_BREAK (0x70) -#define MCF_UART_UCR_START_BREAK (0x60) -#define MCF_UART_UCR_BKCHGINT (0x50) -#define MCF_UART_UCR_RESET_ERROR (0x40) -#define MCF_UART_UCR_RESET_TX (0x30) -#define MCF_UART_UCR_RESET_RX (0x20) -#define MCF_UART_UCR_RESET_MR (0x10) -#define MCF_UART_UCR_TX_DISABLED (0x08) -#define MCF_UART_UCR_TX_ENABLED (0x04) -#define MCF_UART_UCR_RX_DISABLED (0x02) -#define MCF_UART_UCR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF_UART_UIPCR */ -#define MCF_UART_UIPCR_CTS (0x01) -#define MCF_UART_UIPCR_COS (0x10) - -/* Bit definitions and macros for MCF_UART_UACR */ -#define MCF_UART_UACR_IEC (0x01) - -/* Bit definitions and macros for MCF_UART_UISR */ -#define MCF_UART_UISR_TXRDY (0x01) -#define MCF_UART_UISR_RXRDY_FU (0x02) -#define MCF_UART_UISR_DB (0x04) -#define MCF_UART_UISR_RXFTO (0x08) -#define MCF_UART_UISR_TXFIFO (0x10) -#define MCF_UART_UISR_RXFIFO (0x20) -#define MCF_UART_UISR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIMR */ -#define MCF_UART_UIMR_TXRDY (0x01) -#define MCF_UART_UIMR_RXRDY_FU (0x02) -#define MCF_UART_UIMR_DB (0x04) -#define MCF_UART_UIMR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIP */ -#define MCF_UART_UIP_CTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP1 */ -#define MCF_UART_UOP1_RTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP0 */ -#define MCF_UART_UOP0_RTS (0x01) - -/********************************************************************* -* -* I2C Module (I2C) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_I2C_I2AR (*(vuint8 *)(&__IPSBAR[0x000300])) -#define MCF_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x000304])) -#define MCF_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x000308])) -#define MCF_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x00030C])) -#define MCF_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x000310])) - -/* Bit definitions and macros for MCF_I2C_I2AR */ -#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_I2C_I2FDR */ -#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) - -/* Bit definitions and macros for MCF_I2C_I2CR */ -#define MCF_I2C_I2CR_RSTA (0x04) -#define MCF_I2C_I2CR_TXAK (0x08) -#define MCF_I2C_I2CR_MTX (0x10) -#define MCF_I2C_I2CR_MSTA (0x20) -#define MCF_I2C_I2CR_IIEN (0x40) -#define MCF_I2C_I2CR_IEN (0x80) - -/* Bit definitions and macros for MCF_I2C_I2SR */ -#define MCF_I2C_I2SR_RXAK (0x01) -#define MCF_I2C_I2SR_IIF (0x02) -#define MCF_I2C_I2SR_SRW (0x04) -#define MCF_I2C_I2SR_IAL (0x10) -#define MCF_I2C_I2SR_IBB (0x20) -#define MCF_I2C_I2SR_IAAS (0x40) -#define MCF_I2C_I2SR_ICF (0x80) - -/* Bit definitions and macros for MCF_I2C_I2DR */ -#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_I2C_I2ICR */ -#define MCF_I2C_I2ICR_IE (0x01) -#define MCF_I2C_I2ICR_RE (0x02) -#define MCF_I2C_I2ICR_TE (0x04) -#define MCF_I2C_I2ICR_BNBE (0x08) - -/********************************************************************* -* -* Queued Serial Peripheral Interface (QSPI) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_QSPI_QMR (*(vuint16*)(&__IPSBAR[0x000340])) -#define MCF_QSPI_QDLYR (*(vuint16*)(&__IPSBAR[0x000344])) -#define MCF_QSPI_QWR (*(vuint16*)(&__IPSBAR[0x000348])) -#define MCF_QSPI_QIR (*(vuint16*)(&__IPSBAR[0x00034C])) -#define MCF_QSPI_QAR (*(vuint16*)(&__IPSBAR[0x000350])) -#define MCF_QSPI_QDR (*(vuint16*)(&__IPSBAR[0x000354])) - -/* Bit definitions and macros for MCF_QSPI_QMR */ -#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QMR_CPHA (0x0100) -#define MCF_QSPI_QMR_CPOL (0x0200) -#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) -#define MCF_QSPI_QMR_DOHIE (0x4000) -#define MCF_QSPI_QMR_MSTR (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QDLYR */ -#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define MCF_QSPI_QDLYR_SPE (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QWR */ -#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) -#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define MCF_QSPI_QWR_CSIV (0x1000) -#define MCF_QSPI_QWR_WRTO (0x2000) -#define MCF_QSPI_QWR_WREN (0x4000) -#define MCF_QSPI_QWR_HALT (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QIR */ -#define MCF_QSPI_QIR_SPIF (0x0001) -#define MCF_QSPI_QIR_ABRT (0x0004) -#define MCF_QSPI_QIR_WCEF (0x0008) -#define MCF_QSPI_QIR_SPIFE (0x0100) -#define MCF_QSPI_QIR_ABRTE (0x0400) -#define MCF_QSPI_QIR_WCEFE (0x0800) -#define MCF_QSPI_QIR_ABRTL (0x1000) -#define MCF_QSPI_QIR_ABRTB (0x4000) -#define MCF_QSPI_QIR_WCEFB (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QAR */ -#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) - -/* Bit definitions and macros for MCF_QSPI_QDR */ -#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0) - -/********************************************************************* -* -* DMA Timers (DTIM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_DTIM0_DTMR (*(vuint16*)(&__IPSBAR[0x000400])) -#define MCF_DTIM0_DTXMR (*(vuint8 *)(&__IPSBAR[0x000402])) -#define MCF_DTIM0_DTER (*(vuint8 *)(&__IPSBAR[0x000403])) -#define MCF_DTIM0_DTRR (*(vuint32*)(&__IPSBAR[0x000404])) -#define MCF_DTIM0_DTCR (*(vuint32*)(&__IPSBAR[0x000408])) -#define MCF_DTIM0_DTCN (*(vuint32*)(&__IPSBAR[0x00040C])) -#define MCF_DTIM1_DTMR (*(vuint16*)(&__IPSBAR[0x000440])) -#define MCF_DTIM1_DTXMR (*(vuint8 *)(&__IPSBAR[0x000442])) -#define MCF_DTIM1_DTER (*(vuint8 *)(&__IPSBAR[0x000443])) -#define MCF_DTIM1_DTRR (*(vuint32*)(&__IPSBAR[0x000444])) -#define MCF_DTIM1_DTCR (*(vuint32*)(&__IPSBAR[0x000448])) -#define MCF_DTIM1_DTCN (*(vuint32*)(&__IPSBAR[0x00044C])) -#define MCF_DTIM2_DTMR (*(vuint16*)(&__IPSBAR[0x000480])) -#define MCF_DTIM2_DTXMR (*(vuint8 *)(&__IPSBAR[0x000482])) -#define MCF_DTIM2_DTER (*(vuint8 *)(&__IPSBAR[0x000483])) -#define MCF_DTIM2_DTRR (*(vuint32*)(&__IPSBAR[0x000484])) -#define MCF_DTIM2_DTCR (*(vuint32*)(&__IPSBAR[0x000488])) -#define MCF_DTIM2_DTCN (*(vuint32*)(&__IPSBAR[0x00048C])) -#define MCF_DTIM3_DTMR (*(vuint16*)(&__IPSBAR[0x0004C0])) -#define MCF_DTIM3_DTXMR (*(vuint8 *)(&__IPSBAR[0x0004C2])) -#define MCF_DTIM3_DTER (*(vuint8 *)(&__IPSBAR[0x0004C3])) -#define MCF_DTIM3_DTRR (*(vuint32*)(&__IPSBAR[0x0004C4])) -#define MCF_DTIM3_DTCR (*(vuint32*)(&__IPSBAR[0x0004C8])) -#define MCF_DTIM3_DTCN (*(vuint32*)(&__IPSBAR[0x0004CC])) -#define MCF_DTIM_DTMR(x) (*(vuint16*)(&__IPSBAR[0x000400+((x)*0x040)])) -#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x000402+((x)*0x040)])) -#define MCF_DTIM_DTER(x) (*(vuint8 *)(&__IPSBAR[0x000403+((x)*0x040)])) -#define MCF_DTIM_DTRR(x) (*(vuint32*)(&__IPSBAR[0x000404+((x)*0x040)])) -#define MCF_DTIM_DTCR(x) (*(vuint32*)(&__IPSBAR[0x000408+((x)*0x040)])) -#define MCF_DTIM_DTCN(x) (*(vuint32*)(&__IPSBAR[0x00040C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_DTIM_DTMR */ -#define MCF_DTIM_DTMR_RST (0x0001) -#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) -#define MCF_DTIM_DTMR_FRR (0x0008) -#define MCF_DTIM_DTMR_ORRI (0x0010) -#define MCF_DTIM_DTMR_OM (0x0020) -#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) -#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) -#define MCF_DTIM_DTMR_CE_ANY (0x00C0) -#define MCF_DTIM_DTMR_CE_FALL (0x0080) -#define MCF_DTIM_DTMR_CE_RISE (0x0040) -#define MCF_DTIM_DTMR_CE_NONE (0x0000) -#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) -#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) -#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) -#define MCF_DTIM_DTMR_CLK_STOP (0x0000) - -/* Bit definitions and macros for MCF_DTIM_DTXMR */ -#define MCF_DTIM_DTXMR_MODE16 (0x01) -#define MCF_DTIM_DTXMR_DMAEN (0x80) - -/* Bit definitions and macros for MCF_DTIM_DTER */ -#define MCF_DTIM_DTER_CAP (0x01) -#define MCF_DTIM_DTER_REF (0x02) - -/* Bit definitions and macros for MCF_DTIM_DTRR */ -#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DTIM_DTCR */ -#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DTIM_DTCN */ -#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* -* -* Interrupt Controller (INTC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC0_IPRH (*(vuint32*)(&__IPSBAR[0x000C00])) -#define MCF_INTC0_IPRL (*(vuint32*)(&__IPSBAR[0x000C04])) -#define MCF_INTC0_IMRH (*(vuint32*)(&__IPSBAR[0x000C08])) -#define MCF_INTC0_IMRL (*(vuint32*)(&__IPSBAR[0x000C0C])) -#define MCF_INTC0_INTFRCH (*(vuint32*)(&__IPSBAR[0x000C10])) -#define MCF_INTC0_INTFRCL (*(vuint32*)(&__IPSBAR[0x000C14])) -#define MCF_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0x000C18])) -#define MCF_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000C19])) -#define MCF_INTC0_ICR1 (*(vuint8 *)(&__IPSBAR[0x000C41])) -#define MCF_INTC0_ICR2 (*(vuint8 *)(&__IPSBAR[0x000C42])) -#define MCF_INTC0_ICR3 (*(vuint8 *)(&__IPSBAR[0x000C43])) -#define MCF_INTC0_ICR4 (*(vuint8 *)(&__IPSBAR[0x000C44])) -#define MCF_INTC0_ICR5 (*(vuint8 *)(&__IPSBAR[0x000C45])) -#define MCF_INTC0_ICR6 (*(vuint8 *)(&__IPSBAR[0x000C46])) -#define MCF_INTC0_ICR7 (*(vuint8 *)(&__IPSBAR[0x000C47])) -#define MCF_INTC0_ICR8 (*(vuint8 *)(&__IPSBAR[0x000C48])) -#define MCF_INTC0_ICR9 (*(vuint8 *)(&__IPSBAR[0x000C49])) -#define MCF_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0x000C4A])) -#define MCF_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0x000C4B])) -#define MCF_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0x000C4C])) -#define MCF_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0x000C4D])) -#define MCF_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0x000C4E])) -#define MCF_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0x000C4F])) -#define MCF_INTC0_ICR16 (*(vuint8 *)(&__IPSBAR[0x000C50])) -#define MCF_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0x000C51])) -#define MCF_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0x000C52])) -#define MCF_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0x000C53])) -#define MCF_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0x000C54])) -#define MCF_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0x000C55])) -#define MCF_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0x000C56])) -#define MCF_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0x000C57])) -#define MCF_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0x000C58])) -#define MCF_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0x000C59])) -#define MCF_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0x000C5A])) -#define MCF_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0x000C5B])) -#define MCF_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0x000C5C])) -#define MCF_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0x000C5D])) -#define MCF_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0x000C5E])) -#define MCF_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0x000C5F])) -#define MCF_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0x000C60])) -#define MCF_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0x000C61])) -#define MCF_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0x000C62])) -#define MCF_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0x000C63])) -#define MCF_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0x000C64])) -#define MCF_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0x000C65])) -#define MCF_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0x000C66])) -#define MCF_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0x000C67])) -#define MCF_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0x000C68])) -#define MCF_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0x000C69])) -#define MCF_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0x000C6A])) -#define MCF_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0x000C6B])) -#define MCF_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0x000C6C])) -#define MCF_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0x000C6D])) -#define MCF_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0x000C6E])) -#define MCF_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0x000C6F])) -#define MCF_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0x000C70])) -#define MCF_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0x000C71])) -#define MCF_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0x000C72])) -#define MCF_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0x000C73])) -#define MCF_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0x000C74])) -#define MCF_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0x000C75])) -#define MCF_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0x000C76])) -#define MCF_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0x000C77])) -#define MCF_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0x000C78])) -#define MCF_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0x000C79])) -#define MCF_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0x000C7A])) -#define MCF_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0x000C7B])) -#define MCF_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0x000C7C])) -#define MCF_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0x000C7D])) -#define MCF_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0x000C7E])) -#define MCF_INTC0_ICR63 (*(vuint8 *)(&__IPSBAR[0x000C7F])) -#define MCF_INTC0_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x-1)*0x001)])) -#define MCF_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0x000CE0])) -#define MCF_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0x000CE4])) -#define MCF_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0x000CE8])) -#define MCF_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0x000CEC])) -#define MCF_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0x000CF0])) -#define MCF_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0x000CF4])) -#define MCF_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0x000CF8])) -#define MCF_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0x000CFC])) -#define MCF_INTC0_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x-1)*0x004)])) -#define MCF_INTC1_IPRH (*(vuint32*)(&__IPSBAR[0x000D00])) -#define MCF_INTC1_IPRL (*(vuint32*)(&__IPSBAR[0x000D04])) -#define MCF_INTC1_IMRH (*(vuint32*)(&__IPSBAR[0x000D08])) -#define MCF_INTC1_IMRL (*(vuint32*)(&__IPSBAR[0x000D0C])) -#define MCF_INTC1_INTFRCH (*(vuint32*)(&__IPSBAR[0x000D10])) -#define MCF_INTC1_INTFRCL (*(vuint32*)(&__IPSBAR[0x000D14])) -#define MCF_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0x000D18])) -#define MCF_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000D19])) -#define MCF_INTC1_ICR1 (*(vuint8 *)(&__IPSBAR[0x000D41])) -#define MCF_INTC1_ICR2 (*(vuint8 *)(&__IPSBAR[0x000D42])) -#define MCF_INTC1_ICR3 (*(vuint8 *)(&__IPSBAR[0x000D43])) -#define MCF_INTC1_ICR4 (*(vuint8 *)(&__IPSBAR[0x000D44])) -#define MCF_INTC1_ICR5 (*(vuint8 *)(&__IPSBAR[0x000D45])) -#define MCF_INTC1_ICR6 (*(vuint8 *)(&__IPSBAR[0x000D46])) -#define MCF_INTC1_ICR7 (*(vuint8 *)(&__IPSBAR[0x000D47])) -#define MCF_INTC1_ICR8 (*(vuint8 *)(&__IPSBAR[0x000D48])) -#define MCF_INTC1_ICR9 (*(vuint8 *)(&__IPSBAR[0x000D49])) -#define MCF_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0x000D4A])) -#define MCF_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0x000D4B])) -#define MCF_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0x000D4C])) -#define MCF_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0x000D4D])) -#define MCF_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0x000D4E])) -#define MCF_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0x000D4F])) -#define MCF_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0x000D50])) -#define MCF_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0x000D51])) -#define MCF_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0x000D52])) -#define MCF_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0x000D53])) -#define MCF_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0x000D54])) -#define MCF_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0x000D55])) -#define MCF_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0x000D56])) -#define MCF_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0x000D57])) -#define MCF_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0x000D58])) -#define MCF_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0x000D59])) -#define MCF_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0x000D5A])) -#define MCF_INTC1_ICR27 (*(vuint8 *)(&__IPSBAR[0x000D5B])) -#define MCF_INTC1_ICR28 (*(vuint8 *)(&__IPSBAR[0x000D5C])) -#define MCF_INTC1_ICR29 (*(vuint8 *)(&__IPSBAR[0x000D5D])) -#define MCF_INTC1_ICR30 (*(vuint8 *)(&__IPSBAR[0x000D5E])) -#define MCF_INTC1_ICR31 (*(vuint8 *)(&__IPSBAR[0x000D5F])) -#define MCF_INTC1_ICR32 (*(vuint8 *)(&__IPSBAR[0x000D60])) -#define MCF_INTC1_ICR33 (*(vuint8 *)(&__IPSBAR[0x000D61])) -#define MCF_INTC1_ICR34 (*(vuint8 *)(&__IPSBAR[0x000D62])) -#define MCF_INTC1_ICR35 (*(vuint8 *)(&__IPSBAR[0x000D63])) -#define MCF_INTC1_ICR36 (*(vuint8 *)(&__IPSBAR[0x000D64])) -#define MCF_INTC1_ICR37 (*(vuint8 *)(&__IPSBAR[0x000D65])) -#define MCF_INTC1_ICR38 (*(vuint8 *)(&__IPSBAR[0x000D66])) -#define MCF_INTC1_ICR39 (*(vuint8 *)(&__IPSBAR[0x000D67])) -#define MCF_INTC1_ICR40 (*(vuint8 *)(&__IPSBAR[0x000D68])) -#define MCF_INTC1_ICR41 (*(vuint8 *)(&__IPSBAR[0x000D69])) -#define MCF_INTC1_ICR42 (*(vuint8 *)(&__IPSBAR[0x000D6A])) -#define MCF_INTC1_ICR43 (*(vuint8 *)(&__IPSBAR[0x000D6B])) -#define MCF_INTC1_ICR44 (*(vuint8 *)(&__IPSBAR[0x000D6C])) -#define MCF_INTC1_ICR45 (*(vuint8 *)(&__IPSBAR[0x000D6D])) -#define MCF_INTC1_ICR46 (*(vuint8 *)(&__IPSBAR[0x000D6E])) -#define MCF_INTC1_ICR47 (*(vuint8 *)(&__IPSBAR[0x000D6F])) -#define MCF_INTC1_ICR48 (*(vuint8 *)(&__IPSBAR[0x000D70])) -#define MCF_INTC1_ICR49 (*(vuint8 *)(&__IPSBAR[0x000D71])) -#define MCF_INTC1_ICR50 (*(vuint8 *)(&__IPSBAR[0x000D72])) -#define MCF_INTC1_ICR51 (*(vuint8 *)(&__IPSBAR[0x000D73])) -#define MCF_INTC1_ICR52 (*(vuint8 *)(&__IPSBAR[0x000D74])) -#define MCF_INTC1_ICR53 (*(vuint8 *)(&__IPSBAR[0x000D75])) -#define MCF_INTC1_ICR54 (*(vuint8 *)(&__IPSBAR[0x000D76])) -#define MCF_INTC1_ICR55 (*(vuint8 *)(&__IPSBAR[0x000D77])) -#define MCF_INTC1_ICR56 (*(vuint8 *)(&__IPSBAR[0x000D78])) -#define MCF_INTC1_ICR57 (*(vuint8 *)(&__IPSBAR[0x000D79])) -#define MCF_INTC1_ICR58 (*(vuint8 *)(&__IPSBAR[0x000D7A])) -#define MCF_INTC1_ICR59 (*(vuint8 *)(&__IPSBAR[0x000D7B])) -#define MCF_INTC1_ICR60 (*(vuint8 *)(&__IPSBAR[0x000D7C])) -#define MCF_INTC1_ICR61 (*(vuint8 *)(&__IPSBAR[0x000D7D])) -#define MCF_INTC1_ICR62 (*(vuint8 *)(&__IPSBAR[0x000D7E])) -#define MCF_INTC1_ICR63 (*(vuint8 *)(&__IPSBAR[0x000D7F])) -#define MCF_INTC1_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000D41+((x-1)*0x001)])) -#define MCF_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0x000DE0])) -#define MCF_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0x000DE4])) -#define MCF_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0x000DE8])) -#define MCF_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0x000DEC])) -#define MCF_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0x000DF0])) -#define MCF_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0x000DF4])) -#define MCF_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0x000DF8])) -#define MCF_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0x000DFC])) -#define MCF_INTC1_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000DE4+((x-1)*0x004)])) -#define MCF_INTC_IPRH(x) (*(vuint32*)(&__IPSBAR[0x000C00+((x)*0x100)])) -#define MCF_INTC_IPRL(x) (*(vuint32*)(&__IPSBAR[0x000C04+((x)*0x100)])) -#define MCF_INTC_IMRH(x) (*(vuint32*)(&__IPSBAR[0x000C08+((x)*0x100)])) -#define MCF_INTC_IMRL(x) (*(vuint32*)(&__IPSBAR[0x000C0C+((x)*0x100)])) -#define MCF_INTC_INTFRCH(x) (*(vuint32*)(&__IPSBAR[0x000C10+((x)*0x100)])) -#define MCF_INTC_INTFRCL(x) (*(vuint32*)(&__IPSBAR[0x000C14+((x)*0x100)])) -#define MCF_INTC_IRLR(x) (*(vuint8 *)(&__IPSBAR[0x000C18+((x)*0x100)])) -#define MCF_INTC_IACKLPR(x) (*(vuint8 *)(&__IPSBAR[0x000C19+((x)*0x100)])) -#define MCF_INTC_ICR1(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x)*0x100)])) -#define MCF_INTC_ICR2(x) (*(vuint8 *)(&__IPSBAR[0x000C42+((x)*0x100)])) -#define MCF_INTC_ICR3(x) (*(vuint8 *)(&__IPSBAR[0x000C43+((x)*0x100)])) -#define MCF_INTC_ICR4(x) (*(vuint8 *)(&__IPSBAR[0x000C44+((x)*0x100)])) -#define MCF_INTC_ICR5(x) (*(vuint8 *)(&__IPSBAR[0x000C45+((x)*0x100)])) -#define MCF_INTC_ICR6(x) (*(vuint8 *)(&__IPSBAR[0x000C46+((x)*0x100)])) -#define MCF_INTC_ICR7(x) (*(vuint8 *)(&__IPSBAR[0x000C47+((x)*0x100)])) -#define MCF_INTC_ICR8(x) (*(vuint8 *)(&__IPSBAR[0x000C48+((x)*0x100)])) -#define MCF_INTC_ICR9(x) (*(vuint8 *)(&__IPSBAR[0x000C49+((x)*0x100)])) -#define MCF_INTC_ICR10(x) (*(vuint8 *)(&__IPSBAR[0x000C4A+((x)*0x100)])) -#define MCF_INTC_ICR11(x) (*(vuint8 *)(&__IPSBAR[0x000C4B+((x)*0x100)])) -#define MCF_INTC_ICR12(x) (*(vuint8 *)(&__IPSBAR[0x000C4C+((x)*0x100)])) -#define MCF_INTC_ICR13(x) (*(vuint8 *)(&__IPSBAR[0x000C4D+((x)*0x100)])) -#define MCF_INTC_ICR14(x) (*(vuint8 *)(&__IPSBAR[0x000C4E+((x)*0x100)])) -#define MCF_INTC_ICR15(x) (*(vuint8 *)(&__IPSBAR[0x000C4F+((x)*0x100)])) -#define MCF_INTC_ICR16(x) (*(vuint8 *)(&__IPSBAR[0x000C50+((x)*0x100)])) -#define MCF_INTC_ICR17(x) (*(vuint8 *)(&__IPSBAR[0x000C51+((x)*0x100)])) -#define MCF_INTC_ICR18(x) (*(vuint8 *)(&__IPSBAR[0x000C52+((x)*0x100)])) -#define MCF_INTC_ICR19(x) (*(vuint8 *)(&__IPSBAR[0x000C53+((x)*0x100)])) -#define MCF_INTC_ICR20(x) (*(vuint8 *)(&__IPSBAR[0x000C54+((x)*0x100)])) -#define MCF_INTC_ICR21(x) (*(vuint8 *)(&__IPSBAR[0x000C55+((x)*0x100)])) -#define MCF_INTC_ICR22(x) (*(vuint8 *)(&__IPSBAR[0x000C56+((x)*0x100)])) -#define MCF_INTC_ICR23(x) (*(vuint8 *)(&__IPSBAR[0x000C57+((x)*0x100)])) -#define MCF_INTC_ICR24(x) (*(vuint8 *)(&__IPSBAR[0x000C58+((x)*0x100)])) -#define MCF_INTC_ICR25(x) (*(vuint8 *)(&__IPSBAR[0x000C59+((x)*0x100)])) -#define MCF_INTC_ICR26(x) (*(vuint8 *)(&__IPSBAR[0x000C5A+((x)*0x100)])) -#define MCF_INTC_ICR27(x) (*(vuint8 *)(&__IPSBAR[0x000C5B+((x)*0x100)])) -#define MCF_INTC_ICR28(x) (*(vuint8 *)(&__IPSBAR[0x000C5C+((x)*0x100)])) -#define MCF_INTC_ICR29(x) (*(vuint8 *)(&__IPSBAR[0x000C5D+((x)*0x100)])) -#define MCF_INTC_ICR30(x) (*(vuint8 *)(&__IPSBAR[0x000C5E+((x)*0x100)])) -#define MCF_INTC_ICR31(x) (*(vuint8 *)(&__IPSBAR[0x000C5F+((x)*0x100)])) -#define MCF_INTC_ICR32(x) (*(vuint8 *)(&__IPSBAR[0x000C60+((x)*0x100)])) -#define MCF_INTC_ICR33(x) (*(vuint8 *)(&__IPSBAR[0x000C61+((x)*0x100)])) -#define MCF_INTC_ICR34(x) (*(vuint8 *)(&__IPSBAR[0x000C62+((x)*0x100)])) -#define MCF_INTC_ICR35(x) (*(vuint8 *)(&__IPSBAR[0x000C63+((x)*0x100)])) -#define MCF_INTC_ICR36(x) (*(vuint8 *)(&__IPSBAR[0x000C64+((x)*0x100)])) -#define MCF_INTC_ICR37(x) (*(vuint8 *)(&__IPSBAR[0x000C65+((x)*0x100)])) -#define MCF_INTC_ICR38(x) (*(vuint8 *)(&__IPSBAR[0x000C66+((x)*0x100)])) -#define MCF_INTC_ICR39(x) (*(vuint8 *)(&__IPSBAR[0x000C67+((x)*0x100)])) -#define MCF_INTC_ICR40(x) (*(vuint8 *)(&__IPSBAR[0x000C68+((x)*0x100)])) -#define MCF_INTC_ICR41(x) (*(vuint8 *)(&__IPSBAR[0x000C69+((x)*0x100)])) -#define MCF_INTC_ICR42(x) (*(vuint8 *)(&__IPSBAR[0x000C6A+((x)*0x100)])) -#define MCF_INTC_ICR43(x) (*(vuint8 *)(&__IPSBAR[0x000C6B+((x)*0x100)])) -#define MCF_INTC_ICR44(x) (*(vuint8 *)(&__IPSBAR[0x000C6C+((x)*0x100)])) -#define MCF_INTC_ICR45(x) (*(vuint8 *)(&__IPSBAR[0x000C6D+((x)*0x100)])) -#define MCF_INTC_ICR46(x) (*(vuint8 *)(&__IPSBAR[0x000C6E+((x)*0x100)])) -#define MCF_INTC_ICR47(x) (*(vuint8 *)(&__IPSBAR[0x000C6F+((x)*0x100)])) -#define MCF_INTC_ICR48(x) (*(vuint8 *)(&__IPSBAR[0x000C70+((x)*0x100)])) -#define MCF_INTC_ICR49(x) (*(vuint8 *)(&__IPSBAR[0x000C71+((x)*0x100)])) -#define MCF_INTC_ICR50(x) (*(vuint8 *)(&__IPSBAR[0x000C72+((x)*0x100)])) -#define MCF_INTC_ICR51(x) (*(vuint8 *)(&__IPSBAR[0x000C73+((x)*0x100)])) -#define MCF_INTC_ICR52(x) (*(vuint8 *)(&__IPSBAR[0x000C74+((x)*0x100)])) -#define MCF_INTC_ICR53(x) (*(vuint8 *)(&__IPSBAR[0x000C75+((x)*0x100)])) -#define MCF_INTC_ICR54(x) (*(vuint8 *)(&__IPSBAR[0x000C76+((x)*0x100)])) -#define MCF_INTC_ICR55(x) (*(vuint8 *)(&__IPSBAR[0x000C77+((x)*0x100)])) -#define MCF_INTC_ICR56(x) (*(vuint8 *)(&__IPSBAR[0x000C78+((x)*0x100)])) -#define MCF_INTC_ICR57(x) (*(vuint8 *)(&__IPSBAR[0x000C79+((x)*0x100)])) -#define MCF_INTC_ICR58(x) (*(vuint8 *)(&__IPSBAR[0x000C7A+((x)*0x100)])) -#define MCF_INTC_ICR59(x) (*(vuint8 *)(&__IPSBAR[0x000C7B+((x)*0x100)])) -#define MCF_INTC_ICR60(x) (*(vuint8 *)(&__IPSBAR[0x000C7C+((x)*0x100)])) -#define MCF_INTC_ICR61(x) (*(vuint8 *)(&__IPSBAR[0x000C7D+((x)*0x100)])) -#define MCF_INTC_ICR62(x) (*(vuint8 *)(&__IPSBAR[0x000C7E+((x)*0x100)])) -#define MCF_INTC_ICR63(x) (*(vuint8 *)(&__IPSBAR[0x000C7F+((x)*0x100)])) -#define MCF_INTC_SWIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE0+((x)*0x100)])) -#define MCF_INTC_L1IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x)*0x100)])) -#define MCF_INTC_L2IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE8+((x)*0x100)])) -#define MCF_INTC_L3IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CEC+((x)*0x100)])) -#define MCF_INTC_L4IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF0+((x)*0x100)])) -#define MCF_INTC_L5IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF4+((x)*0x100)])) -#define MCF_INTC_L6IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF8+((x)*0x100)])) -#define MCF_INTC_L7IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CFC+((x)*0x100)])) - -/* Bit definitions and macros for MCF_INTC_IPRH */ -#define MCF_INTC_IPRH_INT32 (0x00000001) -#define MCF_INTC_IPRH_INT33 (0x00000002) -#define MCF_INTC_IPRH_INT34 (0x00000004) -#define MCF_INTC_IPRH_INT35 (0x00000008) -#define MCF_INTC_IPRH_INT36 (0x00000010) -#define MCF_INTC_IPRH_INT37 (0x00000020) -#define MCF_INTC_IPRH_INT38 (0x00000040) -#define MCF_INTC_IPRH_INT39 (0x00000080) -#define MCF_INTC_IPRH_INT40 (0x00000100) -#define MCF_INTC_IPRH_INT41 (0x00000200) -#define MCF_INTC_IPRH_INT42 (0x00000400) -#define MCF_INTC_IPRH_INT43 (0x00000800) -#define MCF_INTC_IPRH_INT44 (0x00001000) -#define MCF_INTC_IPRH_INT45 (0x00002000) -#define MCF_INTC_IPRH_INT46 (0x00004000) -#define MCF_INTC_IPRH_INT47 (0x00008000) -#define MCF_INTC_IPRH_INT48 (0x00010000) -#define MCF_INTC_IPRH_INT49 (0x00020000) -#define MCF_INTC_IPRH_INT50 (0x00040000) -#define MCF_INTC_IPRH_INT51 (0x00080000) -#define MCF_INTC_IPRH_INT52 (0x00100000) -#define MCF_INTC_IPRH_INT53 (0x00200000) -#define MCF_INTC_IPRH_INT54 (0x00400000) -#define MCF_INTC_IPRH_INT55 (0x00800000) -#define MCF_INTC_IPRH_INT56 (0x01000000) -#define MCF_INTC_IPRH_INT57 (0x02000000) -#define MCF_INTC_IPRH_INT58 (0x04000000) -#define MCF_INTC_IPRH_INT59 (0x08000000) -#define MCF_INTC_IPRH_INT60 (0x10000000) -#define MCF_INTC_IPRH_INT61 (0x20000000) -#define MCF_INTC_IPRH_INT62 (0x40000000) -#define MCF_INTC_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IPRL */ -#define MCF_INTC_IPRL_INT1 (0x00000002) -#define MCF_INTC_IPRL_INT2 (0x00000004) -#define MCF_INTC_IPRL_INT3 (0x00000008) -#define MCF_INTC_IPRL_INT4 (0x00000010) -#define MCF_INTC_IPRL_INT5 (0x00000020) -#define MCF_INTC_IPRL_INT6 (0x00000040) -#define MCF_INTC_IPRL_INT7 (0x00000080) -#define MCF_INTC_IPRL_INT8 (0x00000100) -#define MCF_INTC_IPRL_INT9 (0x00000200) -#define MCF_INTC_IPRL_INT10 (0x00000400) -#define MCF_INTC_IPRL_INT11 (0x00000800) -#define MCF_INTC_IPRL_INT12 (0x00001000) -#define MCF_INTC_IPRL_INT13 (0x00002000) -#define MCF_INTC_IPRL_INT14 (0x00004000) -#define MCF_INTC_IPRL_INT15 (0x00008000) -#define MCF_INTC_IPRL_INT16 (0x00010000) -#define MCF_INTC_IPRL_INT17 (0x00020000) -#define MCF_INTC_IPRL_INT18 (0x00040000) -#define MCF_INTC_IPRL_INT19 (0x00080000) -#define MCF_INTC_IPRL_INT20 (0x00100000) -#define MCF_INTC_IPRL_INT21 (0x00200000) -#define MCF_INTC_IPRL_INT22 (0x00400000) -#define MCF_INTC_IPRL_INT23 (0x00800000) -#define MCF_INTC_IPRL_INT24 (0x01000000) -#define MCF_INTC_IPRL_INT25 (0x02000000) -#define MCF_INTC_IPRL_INT26 (0x04000000) -#define MCF_INTC_IPRL_INT27 (0x08000000) -#define MCF_INTC_IPRL_INT28 (0x10000000) -#define MCF_INTC_IPRL_INT29 (0x20000000) -#define MCF_INTC_IPRL_INT30 (0x40000000) -#define MCF_INTC_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRH */ -#define MCF_INTC_IMRH_MASK32 (0x00000001) -#define MCF_INTC_IMRH_MASK33 (0x00000002) -#define MCF_INTC_IMRH_MASK34 (0x00000004) -#define MCF_INTC_IMRH_MASK35 (0x00000008) -#define MCF_INTC_IMRH_MASK36 (0x00000010) -#define MCF_INTC_IMRH_MASK37 (0x00000020) -#define MCF_INTC_IMRH_MASK38 (0x00000040) -#define MCF_INTC_IMRH_MASK39 (0x00000080) -#define MCF_INTC_IMRH_MASK40 (0x00000100) -#define MCF_INTC_IMRH_MASK41 (0x00000200) -#define MCF_INTC_IMRH_MASK42 (0x00000400) -#define MCF_INTC_IMRH_MASK43 (0x00000800) -#define MCF_INTC_IMRH_MASK44 (0x00001000) -#define MCF_INTC_IMRH_MASK45 (0x00002000) -#define MCF_INTC_IMRH_MASK46 (0x00004000) -#define MCF_INTC_IMRH_MASK47 (0x00008000) -#define MCF_INTC_IMRH_MASK48 (0x00010000) -#define MCF_INTC_IMRH_MASK49 (0x00020000) -#define MCF_INTC_IMRH_MASK50 (0x00040000) -#define MCF_INTC_IMRH_MASK51 (0x00080000) -#define MCF_INTC_IMRH_MASK52 (0x00100000) -#define MCF_INTC_IMRH_MASK53 (0x00200000) -#define MCF_INTC_IMRH_MASK54 (0x00400000) -#define MCF_INTC_IMRH_MASK55 (0x00800000) -#define MCF_INTC_IMRH_MASK56 (0x01000000) -#define MCF_INTC_IMRH_MASK57 (0x02000000) -#define MCF_INTC_IMRH_MASK58 (0x04000000) -#define MCF_INTC_IMRH_MASK59 (0x08000000) -#define MCF_INTC_IMRH_MASK60 (0x10000000) -#define MCF_INTC_IMRH_MASK61 (0x20000000) -#define MCF_INTC_IMRH_MASK62 (0x40000000) -#define MCF_INTC_IMRH_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRL */ -#define MCF_INTC_IMRL_MASKALL (0x00000001) -#define MCF_INTC_IMRL_MASK1 (0x00000002) -#define MCF_INTC_IMRL_MASK2 (0x00000004) -#define MCF_INTC_IMRL_MASK3 (0x00000008) -#define MCF_INTC_IMRL_MASK4 (0x00000010) -#define MCF_INTC_IMRL_MASK5 (0x00000020) -#define MCF_INTC_IMRL_MASK6 (0x00000040) -#define MCF_INTC_IMRL_MASK7 (0x00000080) -#define MCF_INTC_IMRL_MASK8 (0x00000100) -#define MCF_INTC_IMRL_MASK9 (0x00000200) -#define MCF_INTC_IMRL_MASK10 (0x00000400) -#define MCF_INTC_IMRL_MASK11 (0x00000800) -#define MCF_INTC_IMRL_MASK12 (0x00001000) -#define MCF_INTC_IMRL_MASK13 (0x00002000) -#define MCF_INTC_IMRL_MASK14 (0x00004000) -#define MCF_INTC_IMRL_MASK15 (0x00008000) -#define MCF_INTC_IMRL_MASK16 (0x00010000) -#define MCF_INTC_IMRL_MASK17 (0x00020000) -#define MCF_INTC_IMRL_MASK18 (0x00040000) -#define MCF_INTC_IMRL_MASK19 (0x00080000) -#define MCF_INTC_IMRL_MASK20 (0x00100000) -#define MCF_INTC_IMRL_MASK21 (0x00200000) -#define MCF_INTC_IMRL_MASK22 (0x00400000) -#define MCF_INTC_IMRL_MASK23 (0x00800000) -#define MCF_INTC_IMRL_MASK24 (0x01000000) -#define MCF_INTC_IMRL_MASK25 (0x02000000) -#define MCF_INTC_IMRL_MASK26 (0x04000000) -#define MCF_INTC_IMRL_MASK27 (0x08000000) -#define MCF_INTC_IMRL_MASK28 (0x10000000) -#define MCF_INTC_IMRL_MASK29 (0x20000000) -#define MCF_INTC_IMRL_MASK30 (0x40000000) -#define MCF_INTC_IMRL_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCH */ -#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCL */ -#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) -#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) -#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) -#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) -#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) -#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) -#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IRLR */ -#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_INTC_IACKLPR */ -#define MCF_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_INTC_ICR */ -#define MCF_INTC_ICR_IP(x) (((x)&0x07)<<0) -#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<3) - -/* Bit definitions and macros for MCF_INTC_SWIACK */ -#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_INTC_LIACK */ -#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) - -/********************************************************************* -* -* General Purpose I/O (GPIO) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPIO_PORTNQ (*(vuint8 *)(&__IPSBAR[0x100008])) -#define MCF_GPIO_PORTAN (*(vuint8 *)(&__IPSBAR[0x10000A])) -#define MCF_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000B])) -#define MCF_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000C])) -#define MCF_GPIO_PORTTA (*(vuint8 *)(&__IPSBAR[0x10000E])) -#define MCF_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F])) -#define MCF_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010])) -#define MCF_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011])) -#define MCF_GPIO_PORTUB (*(vuint8 *)(&__IPSBAR[0x100012])) -#define MCF_GPIO_PORTUC (*(vuint8 *)(&__IPSBAR[0x100013])) -#define MCF_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100014])) -#define MCF_GPIO_PORTLD (*(vuint8 *)(&__IPSBAR[0x100015])) -#define MCF_GPIO_PORTGP (*(vuint8 *)(&__IPSBAR[0x100016])) -#define MCF_GPIO_DDRNQ (*(vuint8 *)(&__IPSBAR[0x100020])) -#define MCF_GPIO_DDRAN (*(vuint8 *)(&__IPSBAR[0x100022])) -#define MCF_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100023])) -#define MCF_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100024])) -#define MCF_GPIO_DDRTA (*(vuint8 *)(&__IPSBAR[0x100026])) -#define MCF_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100027])) -#define MCF_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100028])) -#define MCF_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100029])) -#define MCF_GPIO_DDRUB (*(vuint8 *)(&__IPSBAR[0x10002A])) -#define MCF_GPIO_DDRUC (*(vuint8 *)(&__IPSBAR[0x10002B])) -#define MCF_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10002C])) -#define MCF_GPIO_DDRLD (*(vuint8 *)(&__IPSBAR[0x10002D])) -#define MCF_GPIO_DDRGP (*(vuint8 *)(&__IPSBAR[0x10002E])) -#define MCF_GPIO_SETNQ (*(vuint8 *)(&__IPSBAR[0x100038])) -#define MCF_GPIO_SETAN (*(vuint8 *)(&__IPSBAR[0x10003A])) -#define MCF_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x10003B])) -#define MCF_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x10003C])) -#define MCF_GPIO_SETTA (*(vuint8 *)(&__IPSBAR[0x10003E])) -#define MCF_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x10003F])) -#define MCF_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100040])) -#define MCF_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100041])) -#define MCF_GPIO_SETUB (*(vuint8 *)(&__IPSBAR[0x100042])) -#define MCF_GPIO_SETUC (*(vuint8 *)(&__IPSBAR[0x100043])) -#define MCF_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100044])) -#define MCF_GPIO_SETLD (*(vuint8 *)(&__IPSBAR[0x100045])) -#define MCF_GPIO_SETGP (*(vuint8 *)(&__IPSBAR[0x100046])) -#define MCF_GPIO_CLRNQ (*(vuint8 *)(&__IPSBAR[0x100050])) -#define MCF_GPIO_CLRAN (*(vuint8 *)(&__IPSBAR[0x100052])) -#define MCF_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100053])) -#define MCF_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100054])) -#define MCF_GPIO_CLRTA (*(vuint8 *)(&__IPSBAR[0x100056])) -#define MCF_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x100057])) -#define MCF_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x100058])) -#define MCF_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x100059])) -#define MCF_GPIO_CLRUB (*(vuint8 *)(&__IPSBAR[0x10005A])) -#define MCF_GPIO_CLRUC (*(vuint8 *)(&__IPSBAR[0x10005B])) -#define MCF_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x10005C])) -#define MCF_GPIO_CLRLD (*(vuint8 *)(&__IPSBAR[0x10005D])) -#define MCF_GPIO_CLRGP (*(vuint8 *)(&__IPSBAR[0x10005E])) -#define MCF_GPIO_PNQPAR (*(vuint16*)(&__IPSBAR[0x100068])) -#define MCF_GPIO_PANPAR (*(vuint8 *)(&__IPSBAR[0x10006A])) -#define MCF_GPIO_PASPAR (*(vuint8 *)(&__IPSBAR[0x10006B])) -#define MCF_GPIO_PQSPAR (*(vuint16*)(&__IPSBAR[0x10006C])) -#define MCF_GPIO_PTAPAR (*(vuint8 *)(&__IPSBAR[0x10006E])) -#define MCF_GPIO_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10006F])) -#define MCF_GPIO_PTDPAR (*(vuint8 *)(&__IPSBAR[0x100070])) -#define MCF_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x100071])) -#define MCF_GPIO_PUBPAR (*(vuint8 *)(&__IPSBAR[0x100072])) -#define MCF_GPIO_PUCPAR (*(vuint8 *)(&__IPSBAR[0x100073])) -#define MCF_GPIO_PDDPAR (*(vuint8 *)(&__IPSBAR[0x100074])) -#define MCF_GPIO_PLDPAR (*(vuint8 *)(&__IPSBAR[0x100075])) -#define MCF_GPIO_PGPPAR (*(vuint8 *)(&__IPSBAR[0x100076])) -#define MCF_GPIO_PWOR (*(vuint16*)(&__IPSBAR[0x100078])) -#define MCF_GPIO_PDSRH (*(vuint16*)(&__IPSBAR[0x10007A])) -#define MCF_GPIO_PDSRL (*(vuint32*)(&__IPSBAR[0x10007C])) - -/* Bit definitions and macros for MCF_GPIO_PORTNQ */ -#define MCF_GPIO_PORTNQ_PORTNQ0 (0x01) -#define MCF_GPIO_PORTNQ_PORTNQ1 (0x02) -#define MCF_GPIO_PORTNQ_PORTNQ2 (0x04) -#define MCF_GPIO_PORTNQ_PORTNQ3 (0x08) -#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10) -#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20) -#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40) -#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTAN */ -#define MCF_GPIO_PORTAN_PORTAN0 (0x01) -#define MCF_GPIO_PORTAN_PORTAN1 (0x02) -#define MCF_GPIO_PORTAN_PORTAN2 (0x04) -#define MCF_GPIO_PORTAN_PORTAN3 (0x08) -#define MCF_GPIO_PORTAN_PORTAN4 (0x10) -#define MCF_GPIO_PORTAN_PORTAN5 (0x20) -#define MCF_GPIO_PORTAN_PORTAN6 (0x40) -#define MCF_GPIO_PORTAN_PORTAN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTAS */ -#define MCF_GPIO_PORTAS_PORTAS0 (0x01) -#define MCF_GPIO_PORTAS_PORTAS1 (0x02) -#define MCF_GPIO_PORTAS_PORTAS2 (0x04) -#define MCF_GPIO_PORTAS_PORTAS3 (0x08) -#define MCF_GPIO_PORTAS_PORTAS4 (0x10) -#define MCF_GPIO_PORTAS_PORTAS5 (0x20) -#define MCF_GPIO_PORTAS_PORTAS6 (0x40) -#define MCF_GPIO_PORTAS_PORTAS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTQS */ -#define MCF_GPIO_PORTQS_PORTQS0 (0x01) -#define MCF_GPIO_PORTQS_PORTQS1 (0x02) -#define MCF_GPIO_PORTQS_PORTQS2 (0x04) -#define MCF_GPIO_PORTQS_PORTQS3 (0x08) -#define MCF_GPIO_PORTQS_PORTQS4 (0x10) -#define MCF_GPIO_PORTQS_PORTQS5 (0x20) -#define MCF_GPIO_PORTQS_PORTQS6 (0x40) -#define MCF_GPIO_PORTQS_PORTQS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTA */ -#define MCF_GPIO_PORTTA_PORTTA0 (0x01) -#define MCF_GPIO_PORTTA_PORTTA1 (0x02) -#define MCF_GPIO_PORTTA_PORTTA2 (0x04) -#define MCF_GPIO_PORTTA_PORTTA3 (0x08) -#define MCF_GPIO_PORTTA_PORTTA4 (0x10) -#define MCF_GPIO_PORTTA_PORTTA5 (0x20) -#define MCF_GPIO_PORTTA_PORTTA6 (0x40) -#define MCF_GPIO_PORTTA_PORTTA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTC */ -#define MCF_GPIO_PORTTC_PORTTC0 (0x01) -#define MCF_GPIO_PORTTC_PORTTC1 (0x02) -#define MCF_GPIO_PORTTC_PORTTC2 (0x04) -#define MCF_GPIO_PORTTC_PORTTC3 (0x08) -#define MCF_GPIO_PORTTC_PORTTC4 (0x10) -#define MCF_GPIO_PORTTC_PORTTC5 (0x20) -#define MCF_GPIO_PORTTC_PORTTC6 (0x40) -#define MCF_GPIO_PORTTC_PORTTC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTD */ -#define MCF_GPIO_PORTTD_PORTTD0 (0x01) -#define MCF_GPIO_PORTTD_PORTTD1 (0x02) -#define MCF_GPIO_PORTTD_PORTTD2 (0x04) -#define MCF_GPIO_PORTTD_PORTTD3 (0x08) -#define MCF_GPIO_PORTTD_PORTTD4 (0x10) -#define MCF_GPIO_PORTTD_PORTTD5 (0x20) -#define MCF_GPIO_PORTTD_PORTTD6 (0x40) -#define MCF_GPIO_PORTTD_PORTTD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTUA */ -#define MCF_GPIO_PORTUA_PORTUA0 (0x01) -#define MCF_GPIO_PORTUA_PORTUA1 (0x02) -#define MCF_GPIO_PORTUA_PORTUA2 (0x04) -#define MCF_GPIO_PORTUA_PORTUA3 (0x08) -#define MCF_GPIO_PORTUA_PORTUA4 (0x10) -#define MCF_GPIO_PORTUA_PORTUA5 (0x20) -#define MCF_GPIO_PORTUA_PORTUA6 (0x40) -#define MCF_GPIO_PORTUA_PORTUA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTUB */ -#define MCF_GPIO_PORTUB_PORTUB0 (0x01) -#define MCF_GPIO_PORTUB_PORTUB1 (0x02) -#define MCF_GPIO_PORTUB_PORTUB2 (0x04) -#define MCF_GPIO_PORTUB_PORTUB3 (0x08) -#define MCF_GPIO_PORTUB_PORTUB4 (0x10) -#define MCF_GPIO_PORTUB_PORTUB5 (0x20) -#define MCF_GPIO_PORTUB_PORTUB6 (0x40) -#define MCF_GPIO_PORTUB_PORTUB7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTUC */ -#define MCF_GPIO_PORTUC_PORTUC0 (0x01) -#define MCF_GPIO_PORTUC_PORTUC1 (0x02) -#define MCF_GPIO_PORTUC_PORTUC2 (0x04) -#define MCF_GPIO_PORTUC_PORTUC3 (0x08) -#define MCF_GPIO_PORTUC_PORTUC4 (0x10) -#define MCF_GPIO_PORTUC_PORTUC5 (0x20) -#define MCF_GPIO_PORTUC_PORTUC6 (0x40) -#define MCF_GPIO_PORTUC_PORTUC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTDD */ -#define MCF_GPIO_PORTDD_PORTDD0 (0x01) -#define MCF_GPIO_PORTDD_PORTDD1 (0x02) -#define MCF_GPIO_PORTDD_PORTDD2 (0x04) -#define MCF_GPIO_PORTDD_PORTDD3 (0x08) -#define MCF_GPIO_PORTDD_PORTDD4 (0x10) -#define MCF_GPIO_PORTDD_PORTDD5 (0x20) -#define MCF_GPIO_PORTDD_PORTDD6 (0x40) -#define MCF_GPIO_PORTDD_PORTDD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTLD */ -#define MCF_GPIO_PORTLD_PORTLD0 (0x01) -#define MCF_GPIO_PORTLD_PORTLD1 (0x02) -#define MCF_GPIO_PORTLD_PORTLD2 (0x04) -#define MCF_GPIO_PORTLD_PORTLD3 (0x08) -#define MCF_GPIO_PORTLD_PORTLD4 (0x10) -#define MCF_GPIO_PORTLD_PORTLD5 (0x20) -#define MCF_GPIO_PORTLD_PORTLD6 (0x40) -#define MCF_GPIO_PORTLD_PORTLD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTGP */ -#define MCF_GPIO_PORTGP_PORTGP0 (0x01) -#define MCF_GPIO_PORTGP_PORTGP1 (0x02) -#define MCF_GPIO_PORTGP_PORTGP2 (0x04) -#define MCF_GPIO_PORTGP_PORTGP3 (0x08) -#define MCF_GPIO_PORTGP_PORTGP4 (0x10) -#define MCF_GPIO_PORTGP_PORTGP5 (0x20) -#define MCF_GPIO_PORTGP_PORTGP6 (0x40) -#define MCF_GPIO_PORTGP_PORTGP7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRNQ */ -#define MCF_GPIO_DDRNQ_DDRNQ0 (0x01) -#define MCF_GPIO_DDRNQ_DDRNQ1 (0x02) -#define MCF_GPIO_DDRNQ_DDRNQ2 (0x04) -#define MCF_GPIO_DDRNQ_DDRNQ3 (0x08) -#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10) -#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20) -#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40) -#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRAN */ -#define MCF_GPIO_DDRAN_DDRAN0 (0x01) -#define MCF_GPIO_DDRAN_DDRAN1 (0x02) -#define MCF_GPIO_DDRAN_DDRAN2 (0x04) -#define MCF_GPIO_DDRAN_DDRAN3 (0x08) -#define MCF_GPIO_DDRAN_DDRAN4 (0x10) -#define MCF_GPIO_DDRAN_DDRAN5 (0x20) -#define MCF_GPIO_DDRAN_DDRAN6 (0x40) -#define MCF_GPIO_DDRAN_DDRAN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRAS */ -#define MCF_GPIO_DDRAS_DDRAS0 (0x01) -#define MCF_GPIO_DDRAS_DDRAS1 (0x02) -#define MCF_GPIO_DDRAS_DDRAS2 (0x04) -#define MCF_GPIO_DDRAS_DDRAS3 (0x08) -#define MCF_GPIO_DDRAS_DDRAS4 (0x10) -#define MCF_GPIO_DDRAS_DDRAS5 (0x20) -#define MCF_GPIO_DDRAS_DDRAS6 (0x40) -#define MCF_GPIO_DDRAS_DDRAS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRQS */ -#define MCF_GPIO_DDRQS_DDRQS0 (0x01) -#define MCF_GPIO_DDRQS_DDRQS1 (0x02) -#define MCF_GPIO_DDRQS_DDRQS2 (0x04) -#define MCF_GPIO_DDRQS_DDRQS3 (0x08) -#define MCF_GPIO_DDRQS_DDRQS4 (0x10) -#define MCF_GPIO_DDRQS_DDRQS5 (0x20) -#define MCF_GPIO_DDRQS_DDRQS6 (0x40) -#define MCF_GPIO_DDRQS_DDRQS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTA */ -#define MCF_GPIO_DDRTA_DDRTA0 (0x01) -#define MCF_GPIO_DDRTA_DDRTA1 (0x02) -#define MCF_GPIO_DDRTA_DDRTA2 (0x04) -#define MCF_GPIO_DDRTA_DDRTA3 (0x08) -#define MCF_GPIO_DDRTA_DDRTA4 (0x10) -#define MCF_GPIO_DDRTA_DDRTA5 (0x20) -#define MCF_GPIO_DDRTA_DDRTA6 (0x40) -#define MCF_GPIO_DDRTA_DDRTA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTC */ -#define MCF_GPIO_DDRTC_DDRTC0 (0x01) -#define MCF_GPIO_DDRTC_DDRTC1 (0x02) -#define MCF_GPIO_DDRTC_DDRTC2 (0x04) -#define MCF_GPIO_DDRTC_DDRTC3 (0x08) -#define MCF_GPIO_DDRTC_DDRTC4 (0x10) -#define MCF_GPIO_DDRTC_DDRTC5 (0x20) -#define MCF_GPIO_DDRTC_DDRTC6 (0x40) -#define MCF_GPIO_DDRTC_DDRTC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTD */ -#define MCF_GPIO_DDRTD_DDRTD0 (0x01) -#define MCF_GPIO_DDRTD_DDRTD1 (0x02) -#define MCF_GPIO_DDRTD_DDRTD2 (0x04) -#define MCF_GPIO_DDRTD_DDRTD3 (0x08) -#define MCF_GPIO_DDRTD_DDRTD4 (0x10) -#define MCF_GPIO_DDRTD_DDRTD5 (0x20) -#define MCF_GPIO_DDRTD_DDRTD6 (0x40) -#define MCF_GPIO_DDRTD_DDRTD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRUA */ -#define MCF_GPIO_DDRUA_DDRUA0 (0x01) -#define MCF_GPIO_DDRUA_DDRUA1 (0x02) -#define MCF_GPIO_DDRUA_DDRUA2 (0x04) -#define MCF_GPIO_DDRUA_DDRUA3 (0x08) -#define MCF_GPIO_DDRUA_DDRUA4 (0x10) -#define MCF_GPIO_DDRUA_DDRUA5 (0x20) -#define MCF_GPIO_DDRUA_DDRUA6 (0x40) -#define MCF_GPIO_DDRUA_DDRUA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRUB */ -#define MCF_GPIO_DDRUB_DDRUB0 (0x01) -#define MCF_GPIO_DDRUB_DDRUB1 (0x02) -#define MCF_GPIO_DDRUB_DDRUB2 (0x04) -#define MCF_GPIO_DDRUB_DDRUB3 (0x08) -#define MCF_GPIO_DDRUB_DDRUB4 (0x10) -#define MCF_GPIO_DDRUB_DDRUB5 (0x20) -#define MCF_GPIO_DDRUB_DDRUB6 (0x40) -#define MCF_GPIO_DDRUB_DDRUB7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRUC */ -#define MCF_GPIO_DDRUC_DDRUC0 (0x01) -#define MCF_GPIO_DDRUC_DDRUC1 (0x02) -#define MCF_GPIO_DDRUC_DDRUC2 (0x04) -#define MCF_GPIO_DDRUC_DDRUC3 (0x08) -#define MCF_GPIO_DDRUC_DDRUC4 (0x10) -#define MCF_GPIO_DDRUC_DDRUC5 (0x20) -#define MCF_GPIO_DDRUC_DDRUC6 (0x40) -#define MCF_GPIO_DDRUC_DDRUC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRDD */ -#define MCF_GPIO_DDRDD_DDRDD0 (0x01) -#define MCF_GPIO_DDRDD_DDRDD1 (0x02) -#define MCF_GPIO_DDRDD_DDRDD2 (0x04) -#define MCF_GPIO_DDRDD_DDRDD3 (0x08) -#define MCF_GPIO_DDRDD_DDRDD4 (0x10) -#define MCF_GPIO_DDRDD_DDRDD5 (0x20) -#define MCF_GPIO_DDRDD_DDRDD6 (0x40) -#define MCF_GPIO_DDRDD_DDRDD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRLD */ -#define MCF_GPIO_DDRLD_DDRLD0 (0x01) -#define MCF_GPIO_DDRLD_DDRLD1 (0x02) -#define MCF_GPIO_DDRLD_DDRLD2 (0x04) -#define MCF_GPIO_DDRLD_DDRLD3 (0x08) -#define MCF_GPIO_DDRLD_DDRLD4 (0x10) -#define MCF_GPIO_DDRLD_DDRLD5 (0x20) -#define MCF_GPIO_DDRLD_DDRLD6 (0x40) -#define MCF_GPIO_DDRLD_DDRLD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRGP */ -#define MCF_GPIO_DDRGP_DDRGP0 (0x01) -#define MCF_GPIO_DDRGP_DDRGP1 (0x02) -#define MCF_GPIO_DDRGP_DDRGP2 (0x04) -#define MCF_GPIO_DDRGP_DDRGP3 (0x08) -#define MCF_GPIO_DDRGP_DDRGP4 (0x10) -#define MCF_GPIO_DDRGP_DDRGP5 (0x20) -#define MCF_GPIO_DDRGP_DDRGP6 (0x40) -#define MCF_GPIO_DDRGP_DDRGP7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETNQ */ -#define MCF_GPIO_SETNQ_SETNQ0 (0x01) -#define MCF_GPIO_SETNQ_SETNQ1 (0x02) -#define MCF_GPIO_SETNQ_SETNQ2 (0x04) -#define MCF_GPIO_SETNQ_SETNQ3 (0x08) -#define MCF_GPIO_SETNQ_SETNQ4 (0x10) -#define MCF_GPIO_SETNQ_SETNQ5 (0x20) -#define MCF_GPIO_SETNQ_SETNQ6 (0x40) -#define MCF_GPIO_SETNQ_SETNQ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETAN */ -#define MCF_GPIO_SETAN_SETAN0 (0x01) -#define MCF_GPIO_SETAN_SETAN1 (0x02) -#define MCF_GPIO_SETAN_SETAN2 (0x04) -#define MCF_GPIO_SETAN_SETAN3 (0x08) -#define MCF_GPIO_SETAN_SETAN4 (0x10) -#define MCF_GPIO_SETAN_SETAN5 (0x20) -#define MCF_GPIO_SETAN_SETAN6 (0x40) -#define MCF_GPIO_SETAN_SETAN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETAS */ -#define MCF_GPIO_SETAS_SETAS0 (0x01) -#define MCF_GPIO_SETAS_SETAS1 (0x02) -#define MCF_GPIO_SETAS_SETAS2 (0x04) -#define MCF_GPIO_SETAS_SETAS3 (0x08) -#define MCF_GPIO_SETAS_SETAS4 (0x10) -#define MCF_GPIO_SETAS_SETAS5 (0x20) -#define MCF_GPIO_SETAS_SETAS6 (0x40) -#define MCF_GPIO_SETAS_SETAS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETQS */ -#define MCF_GPIO_SETQS_SETQS0 (0x01) -#define MCF_GPIO_SETQS_SETQS1 (0x02) -#define MCF_GPIO_SETQS_SETQS2 (0x04) -#define MCF_GPIO_SETQS_SETQS3 (0x08) -#define MCF_GPIO_SETQS_SETQS4 (0x10) -#define MCF_GPIO_SETQS_SETQS5 (0x20) -#define MCF_GPIO_SETQS_SETQS6 (0x40) -#define MCF_GPIO_SETQS_SETQS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETTA */ -#define MCF_GPIO_SETTA_SETTA0 (0x01) -#define MCF_GPIO_SETTA_SETTA1 (0x02) -#define MCF_GPIO_SETTA_SETTA2 (0x04) -#define MCF_GPIO_SETTA_SETTA3 (0x08) -#define MCF_GPIO_SETTA_SETTA4 (0x10) -#define MCF_GPIO_SETTA_SETTA5 (0x20) -#define MCF_GPIO_SETTA_SETTA6 (0x40) -#define MCF_GPIO_SETTA_SETTA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETTC */ -#define MCF_GPIO_SETTC_SETTC0 (0x01) -#define MCF_GPIO_SETTC_SETTC1 (0x02) -#define MCF_GPIO_SETTC_SETTC2 (0x04) -#define MCF_GPIO_SETTC_SETTC3 (0x08) -#define MCF_GPIO_SETTC_SETTC4 (0x10) -#define MCF_GPIO_SETTC_SETTC5 (0x20) -#define MCF_GPIO_SETTC_SETTC6 (0x40) -#define MCF_GPIO_SETTC_SETTC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETTD */ -#define MCF_GPIO_SETTD_SETTD0 (0x01) -#define MCF_GPIO_SETTD_SETTD1 (0x02) -#define MCF_GPIO_SETTD_SETTD2 (0x04) -#define MCF_GPIO_SETTD_SETTD3 (0x08) -#define MCF_GPIO_SETTD_SETTD4 (0x10) -#define MCF_GPIO_SETTD_SETTD5 (0x20) -#define MCF_GPIO_SETTD_SETTD6 (0x40) -#define MCF_GPIO_SETTD_SETTD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETUA */ -#define MCF_GPIO_SETUA_SETUA0 (0x01) -#define MCF_GPIO_SETUA_SETUA1 (0x02) -#define MCF_GPIO_SETUA_SETUA2 (0x04) -#define MCF_GPIO_SETUA_SETUA3 (0x08) -#define MCF_GPIO_SETUA_SETUA4 (0x10) -#define MCF_GPIO_SETUA_SETUA5 (0x20) -#define MCF_GPIO_SETUA_SETUA6 (0x40) -#define MCF_GPIO_SETUA_SETUA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETUB */ -#define MCF_GPIO_SETUB_SETUB0 (0x01) -#define MCF_GPIO_SETUB_SETUB1 (0x02) -#define MCF_GPIO_SETUB_SETUB2 (0x04) -#define MCF_GPIO_SETUB_SETUB3 (0x08) -#define MCF_GPIO_SETUB_SETUB4 (0x10) -#define MCF_GPIO_SETUB_SETUB5 (0x20) -#define MCF_GPIO_SETUB_SETUB6 (0x40) -#define MCF_GPIO_SETUB_SETUB7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETUC */ -#define MCF_GPIO_SETUC_SETUC0 (0x01) -#define MCF_GPIO_SETUC_SETUC1 (0x02) -#define MCF_GPIO_SETUC_SETUC2 (0x04) -#define MCF_GPIO_SETUC_SETUC3 (0x08) -#define MCF_GPIO_SETUC_SETUC4 (0x10) -#define MCF_GPIO_SETUC_SETUC5 (0x20) -#define MCF_GPIO_SETUC_SETUC6 (0x40) -#define MCF_GPIO_SETUC_SETUC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETDD */ -#define MCF_GPIO_SETDD_SETDD0 (0x01) -#define MCF_GPIO_SETDD_SETDD1 (0x02) -#define MCF_GPIO_SETDD_SETDD2 (0x04) -#define MCF_GPIO_SETDD_SETDD3 (0x08) -#define MCF_GPIO_SETDD_SETDD4 (0x10) -#define MCF_GPIO_SETDD_SETDD5 (0x20) -#define MCF_GPIO_SETDD_SETDD6 (0x40) -#define MCF_GPIO_SETDD_SETDD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETLD */ -#define MCF_GPIO_SETLD_SETLD0 (0x01) -#define MCF_GPIO_SETLD_SETLD1 (0x02) -#define MCF_GPIO_SETLD_SETLD2 (0x04) -#define MCF_GPIO_SETLD_SETLD3 (0x08) -#define MCF_GPIO_SETLD_SETLD4 (0x10) -#define MCF_GPIO_SETLD_SETLD5 (0x20) -#define MCF_GPIO_SETLD_SETLD6 (0x40) -#define MCF_GPIO_SETLD_SETLD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETGP */ -#define MCF_GPIO_SETGP_SETGP0 (0x01) -#define MCF_GPIO_SETGP_SETGP1 (0x02) -#define MCF_GPIO_SETGP_SETGP2 (0x04) -#define MCF_GPIO_SETGP_SETGP3 (0x08) -#define MCF_GPIO_SETGP_SETGP4 (0x10) -#define MCF_GPIO_SETGP_SETGP5 (0x20) -#define MCF_GPIO_SETGP_SETGP6 (0x40) -#define MCF_GPIO_SETGP_SETGP7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRNQ */ -#define MCF_GPIO_CLRNQ_CLRNQ0 (0x01) -#define MCF_GPIO_CLRNQ_CLRNQ1 (0x02) -#define MCF_GPIO_CLRNQ_CLRNQ2 (0x04) -#define MCF_GPIO_CLRNQ_CLRNQ3 (0x08) -#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10) -#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20) -#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40) -#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRAN */ -#define MCF_GPIO_CLRAN_CLRAN0 (0x01) -#define MCF_GPIO_CLRAN_CLRAN1 (0x02) -#define MCF_GPIO_CLRAN_CLRAN2 (0x04) -#define MCF_GPIO_CLRAN_CLRAN3 (0x08) -#define MCF_GPIO_CLRAN_CLRAN4 (0x10) -#define MCF_GPIO_CLRAN_CLRAN5 (0x20) -#define MCF_GPIO_CLRAN_CLRAN6 (0x40) -#define MCF_GPIO_CLRAN_CLRAN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRAS */ -#define MCF_GPIO_CLRAS_CLRAS0 (0x01) -#define MCF_GPIO_CLRAS_CLRAS1 (0x02) -#define MCF_GPIO_CLRAS_CLRAS2 (0x04) -#define MCF_GPIO_CLRAS_CLRAS3 (0x08) -#define MCF_GPIO_CLRAS_CLRAS4 (0x10) -#define MCF_GPIO_CLRAS_CLRAS5 (0x20) -#define MCF_GPIO_CLRAS_CLRAS6 (0x40) -#define MCF_GPIO_CLRAS_CLRAS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRQS */ -#define MCF_GPIO_CLRQS_CLRQS0 (0x01) -#define MCF_GPIO_CLRQS_CLRQS1 (0x02) -#define MCF_GPIO_CLRQS_CLRQS2 (0x04) -#define MCF_GPIO_CLRQS_CLRQS3 (0x08) -#define MCF_GPIO_CLRQS_CLRQS4 (0x10) -#define MCF_GPIO_CLRQS_CLRQS5 (0x20) -#define MCF_GPIO_CLRQS_CLRQS6 (0x40) -#define MCF_GPIO_CLRQS_CLRQS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRTA */ -#define MCF_GPIO_CLRTA_CLRTA0 (0x01) -#define MCF_GPIO_CLRTA_CLRTA1 (0x02) -#define MCF_GPIO_CLRTA_CLRTA2 (0x04) -#define MCF_GPIO_CLRTA_CLRTA3 (0x08) -#define MCF_GPIO_CLRTA_CLRTA4 (0x10) -#define MCF_GPIO_CLRTA_CLRTA5 (0x20) -#define MCF_GPIO_CLRTA_CLRTA6 (0x40) -#define MCF_GPIO_CLRTA_CLRTA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRTC */ -#define MCF_GPIO_CLRTC_CLRTC0 (0x01) -#define MCF_GPIO_CLRTC_CLRTC1 (0x02) -#define MCF_GPIO_CLRTC_CLRTC2 (0x04) -#define MCF_GPIO_CLRTC_CLRTC3 (0x08) -#define MCF_GPIO_CLRTC_CLRTC4 (0x10) -#define MCF_GPIO_CLRTC_CLRTC5 (0x20) -#define MCF_GPIO_CLRTC_CLRTC6 (0x40) -#define MCF_GPIO_CLRTC_CLRTC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRTD */ -#define MCF_GPIO_CLRTD_CLRTD0 (0x01) -#define MCF_GPIO_CLRTD_CLRTD1 (0x02) -#define MCF_GPIO_CLRTD_CLRTD2 (0x04) -#define MCF_GPIO_CLRTD_CLRTD3 (0x08) -#define MCF_GPIO_CLRTD_CLRTD4 (0x10) -#define MCF_GPIO_CLRTD_CLRTD5 (0x20) -#define MCF_GPIO_CLRTD_CLRTD6 (0x40) -#define MCF_GPIO_CLRTD_CLRTD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRUA */ -#define MCF_GPIO_CLRUA_CLRUA0 (0x01) -#define MCF_GPIO_CLRUA_CLRUA1 (0x02) -#define MCF_GPIO_CLRUA_CLRUA2 (0x04) -#define MCF_GPIO_CLRUA_CLRUA3 (0x08) -#define MCF_GPIO_CLRUA_CLRUA4 (0x10) -#define MCF_GPIO_CLRUA_CLRUA5 (0x20) -#define MCF_GPIO_CLRUA_CLRUA6 (0x40) -#define MCF_GPIO_CLRUA_CLRUA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRUB */ -#define MCF_GPIO_CLRUB_CLRUB0 (0x01) -#define MCF_GPIO_CLRUB_CLRUB1 (0x02) -#define MCF_GPIO_CLRUB_CLRUB2 (0x04) -#define MCF_GPIO_CLRUB_CLRUB3 (0x08) -#define MCF_GPIO_CLRUB_CLRUB4 (0x10) -#define MCF_GPIO_CLRUB_CLRUB5 (0x20) -#define MCF_GPIO_CLRUB_CLRUB6 (0x40) -#define MCF_GPIO_CLRUB_CLRUB7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRUC */ -#define MCF_GPIO_CLRUC_CLRUC0 (0x01) -#define MCF_GPIO_CLRUC_CLRUC1 (0x02) -#define MCF_GPIO_CLRUC_CLRUC2 (0x04) -#define MCF_GPIO_CLRUC_CLRUC3 (0x08) -#define MCF_GPIO_CLRUC_CLRUC4 (0x10) -#define MCF_GPIO_CLRUC_CLRUC5 (0x20) -#define MCF_GPIO_CLRUC_CLRUC6 (0x40) -#define MCF_GPIO_CLRUC_CLRUC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRDD */ -#define MCF_GPIO_CLRDD_CLRDD0 (0x01) -#define MCF_GPIO_CLRDD_CLRDD1 (0x02) -#define MCF_GPIO_CLRDD_CLRDD2 (0x04) -#define MCF_GPIO_CLRDD_CLRDD3 (0x08) -#define MCF_GPIO_CLRDD_CLRDD4 (0x10) -#define MCF_GPIO_CLRDD_CLRDD5 (0x20) -#define MCF_GPIO_CLRDD_CLRDD6 (0x40) -#define MCF_GPIO_CLRDD_CLRDD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRLD */ -#define MCF_GPIO_CLRLD_CLRLD0 (0x01) -#define MCF_GPIO_CLRLD_CLRLD1 (0x02) -#define MCF_GPIO_CLRLD_CLRLD2 (0x04) -#define MCF_GPIO_CLRLD_CLRLD3 (0x08) -#define MCF_GPIO_CLRLD_CLRLD4 (0x10) -#define MCF_GPIO_CLRLD_CLRLD5 (0x20) -#define MCF_GPIO_CLRLD_CLRLD6 (0x40) -#define MCF_GPIO_CLRLD_CLRLD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRGP */ -#define MCF_GPIO_CLRGP_CLRGP0 (0x01) -#define MCF_GPIO_CLRGP_CLRGP1 (0x02) -#define MCF_GPIO_CLRGP_CLRGP2 (0x04) -#define MCF_GPIO_CLRGP_CLRGP3 (0x08) -#define MCF_GPIO_CLRGP_CLRGP4 (0x10) -#define MCF_GPIO_CLRGP_CLRGP5 (0x20) -#define MCF_GPIO_CLRGP_CLRGP6 (0x40) -#define MCF_GPIO_CLRGP_CLRGP7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PNQPAR */ -#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PNQPAR_PNQPAR2(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PNQPAR_PNQPAR4(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PNQPAR_PNQPAR6(x) (((x)&0x0003)<<12) -#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x0003)<<14) -#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x0004) -#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x0010) -#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x0040) -#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x0100) -#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x0400) -#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000) -#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000) -#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x0008) -#define MCF_GPIO_PNQPAR_IRQ1_PWM1 (0x000C) - -/* Bit definitions and macros for MCF_GPIO_PANPAR */ -#define MCF_GPIO_PANPAR_PANPAR0 (0x01) -#define MCF_GPIO_PANPAR_PANPAR1 (0x02) -#define MCF_GPIO_PANPAR_PANPAR2 (0x04) -#define MCF_GPIO_PANPAR_PANPAR3 (0x08) -#define MCF_GPIO_PANPAR_PANPAR4 (0x10) -#define MCF_GPIO_PANPAR_PANPAR5 (0x20) -#define MCF_GPIO_PANPAR_PANPAR6 (0x40) -#define MCF_GPIO_PANPAR_PANPAR7 (0x80) -#define MCF_GPIO_PANPAR_AN0_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN1_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN2_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN3_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN4_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN5_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN6_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN7_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN0_AN0 (0x01) -#define MCF_GPIO_PANPAR_AN1_AN1 (0x02) -#define MCF_GPIO_PANPAR_AN2_AN2 (0x04) -#define MCF_GPIO_PANPAR_AN3_AN3 (0x08) -#define MCF_GPIO_PANPAR_AN4_AN4 (0x10) -#define MCF_GPIO_PANPAR_AN5_AN5 (0x20) -#define MCF_GPIO_PANPAR_AN6_AN6 (0x40) -#define MCF_GPIO_PANPAR_AN7_AN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PASPAR */ -#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PASPAR_PASPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PASPAR_PASPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PASPAR_SCL_GPIO (0x00) -#define MCF_GPIO_PASPAR_SDA_GPIO (0x00) -#define MCF_GPIO_PASPAR_SYNCA_GPIO (0x00) -#define MCF_GPIO_PASPAR_SYNCB_GPIO (0x00) -#define MCF_GPIO_PASPAR_SCL_SCL (0x01) -#define MCF_GPIO_PASPAR_SDA_SDA (0x04) -#define MCF_GPIO_PASPAR_SYNCA_SYNCA (0x10) -#define MCF_GPIO_PASPAR_SYNCB_SYNCB (0x40) -#define MCF_GPIO_PASPAR_SCL_CANTX (0x02) -#define MCF_GPIO_PASPAR_SDA_CANRX (0x08) -#define MCF_GPIO_PASPAR_SYNCA_CANRX (0x20) -#define MCF_GPIO_PASPAR_SYNCB_CANTX (0x80) -#define MCF_GPIO_PASPAR_SCL_TXD2 (0x30) -#define MCF_GPIO_PASPAR_SDA_RXD2 (0xC0) - -/* Bit definitions and macros for MCF_GPIO_PQSPAR */ -#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x0003)<<12) -#define MCF_GPIO_PQSPAR_DOUT_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_DIN_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_SCK_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_CS0_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_CS1_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_CS2_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_CS3_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_DOUT_DOUT (0x0001) -#define MCF_GPIO_PQSPAR_DIN_DIN (0x0004) -#define MCF_GPIO_PQSPAR_SCK_SCK (0x0010) -#define MCF_GPIO_PQSPAR_CS0_CS0 (0x0040) -#define MCF_GPIO_PQSPAR_CS1_CS1 (0x0100) -#define MCF_GPIO_PQSPAR_CS2_CS2 (0x0400) -#define MCF_GPIO_PQSPAR_CS3_CS3 (0x1000) -#define MCF_GPIO_PQSPAR_DOUT_CANTX (0x0002) -#define MCF_GPIO_PQSPAR_DIN_CANRX (0x0008) -#define MCF_GPIO_PQSPAR_SCK_SCL (0x0020) -#define MCF_GPIO_PQSPAR_CS0_SDA (0x0080) -#define MCF_GPIO_PQSPAR_CS3_SYNCA (0x2000) -#define MCF_GPIO_PQSPAR_DOUT_TXD1 (0x0003) -#define MCF_GPIO_PQSPAR_DIN_RXD1 (0x000C) -#define MCF_GPIO_PQSPAR_SCK_RTS1 (0x0030) -#define MCF_GPIO_PQSPAR_CS0_CTS1 (0x00C0) -#define MCF_GPIO_PQSPAR_CS3_SYNCB (0x3000) - -/* Bit definitions and macros for MCF_GPIO_PTAPAR */ -#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PTAPAR_ICOC0_GPIO (0x00) -#define MCF_GPIO_PTAPAR_ICOC1_GPIO (0x00) -#define MCF_GPIO_PTAPAR_ICOC2_GPIO (0x00) -#define MCF_GPIO_PTAPAR_ICOC3_GPIO (0x00) -#define MCF_GPIO_PTAPAR_ICOC0_ICOC0 (0x01) -#define MCF_GPIO_PTAPAR_ICOC1_ICOC1 (0x04) -#define MCF_GPIO_PTAPAR_ICOC2_ICOC2 (0x10) -#define MCF_GPIO_PTAPAR_ICOC3_ICOC3 (0x40) -#define MCF_GPIO_PTAPAR_ICOC0_PWM1 (0x02) -#define MCF_GPIO_PTAPAR_ICOC1_PWM3 (0x08) -#define MCF_GPIO_PTAPAR_ICOC2_PWM5 (0x20) -#define MCF_GPIO_PTAPAR_ICOC3_PWM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PTCPAR */ -#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PTCPAR_TIN0_GPIO (0x00) -#define MCF_GPIO_PTCPAR_TIN1_GPIO (0x00) -#define MCF_GPIO_PTCPAR_TIN2_GPIO (0x00) -#define MCF_GPIO_PTCPAR_TIN3_GPIO (0x00) -#define MCF_GPIO_PTCPAR_TIN0_TIN0 (0x01) -#define MCF_GPIO_PTCPAR_TIN1_TIN1 (0x04) -#define MCF_GPIO_PTCPAR_TIN2_TIN2 (0x10) -#define MCF_GPIO_PTCPAR_TIN3_TIN3 (0x40) -#define MCF_GPIO_PTCPAR_TIN0_TOUT0 (0x02) -#define MCF_GPIO_PTCPAR_TIN1_TOUT1 (0x08) -#define MCF_GPIO_PTCPAR_TIN2_TOUT2 (0x20) -#define MCF_GPIO_PTCPAR_TIN3_TOUT3 (0x80) -#define MCF_GPIO_PTCPAR_TIN0_PWM0 (0x03) -#define MCF_GPIO_PTCPAR_TIN1_PWM2 (0x0C) -#define MCF_GPIO_PTCPAR_TIN2_PWM4 (0x30) -#define MCF_GPIO_PTCPAR_TIN3_PWM6 (0xC0) - -/* Bit definitions and macros for MCF_GPIO_PTDPAR */ -#define MCF_GPIO_PTDPAR_PTDPAR0 (0x01) -#define MCF_GPIO_PTDPAR_PTDPAR1 (0x02) -#define MCF_GPIO_PTDPAR_PTDPAR2 (0x04) -#define MCF_GPIO_PTDPAR_PTDPAR3 (0x08) -#define MCF_GPIO_PTDPAR_PWM1_GPIO (0x00) -#define MCF_GPIO_PTDPAR_PWM3_GPIO (0x00) -#define MCF_GPIO_PTDPAR_PWM5_GPIO (0x00) -#define MCF_GPIO_PTDPAR_PWM7_GPIO (0x00) -#define MCF_GPIO_PTDPAR_PWM1_PWM1 (0x01) -#define MCF_GPIO_PTDPAR_PWM3_PWM3 (0x02) -#define MCF_GPIO_PTDPAR_PWM5_PWM5 (0x04) -#define MCF_GPIO_PTDPAR_PWM7_PWM7 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PUAPAR */ -#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PUAPAR_TXD0_GPIO (0x00) -#define MCF_GPIO_PUAPAR_RXD0_GPIO (0x00) -#define MCF_GPIO_PUAPAR_RTS0_GPIO (0x00) -#define MCF_GPIO_PUAPAR_CTS0_GPIO (0x00) -#define MCF_GPIO_PUAPAR_TXD0_TXD0 (0x01) -#define MCF_GPIO_PUAPAR_RXD0_RXD0 (0x04) -#define MCF_GPIO_PUAPAR_RTS0_RTS0 (0x10) -#define MCF_GPIO_PUAPAR_CTS0_CTS0 (0x40) -#define MCF_GPIO_PUAPAR_RTS0_CANTX (0x20) -#define MCF_GPIO_PUAPAR_CTS0_CANRX (0x80) - -/* Bit definitions and macros for MCF_GPIO_PUBPAR */ -#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PUBPAR_TXD1_GPIO (0x00) -#define MCF_GPIO_PUBPAR_RXD1_GPIO (0x00) -#define MCF_GPIO_PUBPAR_RTS1_GPIO (0x00) -#define MCF_GPIO_PUBPAR_CTS1_GPIO (0x00) -#define MCF_GPIO_PUBPAR_TXD1_TXD1 (0x01) -#define MCF_GPIO_PUBPAR_RXD1_RXD1 (0x04) -#define MCF_GPIO_PUBPAR_RTS1_RTS1 (0x10) -#define MCF_GPIO_PUBPAR_CTS1_CTS1 (0x40) -#define MCF_GPIO_PUBPAR_RTS1_SYNCB (0x20) -#define MCF_GPIO_PUBPAR_CTS1_SYNCA (0x80) -#define MCF_GPIO_PUBPAR_RTS1_TXD2 (0x30) -#define MCF_GPIO_PUBPAR_CTS1_RXD2 (0xC0) - -/* Bit definitions and macros for MCF_GPIO_PUCPAR */ -#define MCF_GPIO_PUCPAR_PUCPAR0 (0x01) -#define MCF_GPIO_PUCPAR_PUCPAR1 (0x02) -#define MCF_GPIO_PUCPAR_PUCPAR2 (0x04) -#define MCF_GPIO_PUCPAR_PUCPAR3 (0x08) -#define MCF_GPIO_PUCPAR_TXD2_GPIO (0x00) -#define MCF_GPIO_PUCPAR_RXD2_GPIO (0x00) -#define MCF_GPIO_PUCPAR_RTS2_GPIO (0x00) -#define MCF_GPIO_PUCPAR_CTS2_GPIO (0x00) -#define MCF_GPIO_PUCPAR_TXD2_TXD2 (0x01) -#define MCF_GPIO_PUCPAR_RXD2_RXD2 (0x02) -#define MCF_GPIO_PUCPAR_RTS2_RTS2 (0x04) -#define MCF_GPIO_PUCPAR_CTS2_CTS2 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDPAR */ -#define MCF_GPIO_PDDPAR_PDDPAR0 (0x01) -#define MCF_GPIO_PDDPAR_PDDPAR1 (0x02) -#define MCF_GPIO_PDDPAR_PDDPAR2 (0x04) -#define MCF_GPIO_PDDPAR_PDDPAR3 (0x08) -#define MCF_GPIO_PDDPAR_PDDPAR4 (0x10) -#define MCF_GPIO_PDDPAR_PDDPAR5 (0x20) -#define MCF_GPIO_PDDPAR_PDDPAR6 (0x40) -#define MCF_GPIO_PDDPAR_PDDPAR7 (0x80) -#define MCF_GPIO_PDDPAR_PDD0_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD1_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD2_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD3_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD4_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD5_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD6_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD7_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD0_PST0 (0x01) -#define MCF_GPIO_PDDPAR_PDD1_PST1 (0x02) -#define MCF_GPIO_PDDPAR_PDD2_PST2 (0x04) -#define MCF_GPIO_PDDPAR_PDD3_PST3 (0x08) -#define MCF_GPIO_PDDPAR_PDD4_DDATA0 (0x10) -#define MCF_GPIO_PDDPAR_PDD5_DDATA1 (0x20) -#define MCF_GPIO_PDDPAR_PDD6_DDATA2 (0x40) -#define MCF_GPIO_PDDPAR_PDD7_DDATA3 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PLDPAR */ -#define MCF_GPIO_PLDPAR_PLDPAR0 (0x01) -#define MCF_GPIO_PLDPAR_PLDPAR1 (0x02) -#define MCF_GPIO_PLDPAR_PLDPAR2 (0x04) -#define MCF_GPIO_PLDPAR_PLDPAR3 (0x08) -#define MCF_GPIO_PLDPAR_PLDPAR4 (0x10) -#define MCF_GPIO_PLDPAR_PLDPAR5 (0x20) -#define MCF_GPIO_PLDPAR_PLDPAR6 (0x40) -#define MCF_GPIO_PLDPAR_ACTLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_LNKLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_SPDLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_DUPLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_COLLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_RXLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_TXLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_ACTLED_ACTLED (0x01) -#define MCF_GPIO_PLDPAR_LNKLED_LNKLED (0x02) -#define MCF_GPIO_PLDPAR_SPDLED_SPDLED (0x04) -#define MCF_GPIO_PLDPAR_DUPLED_DUPLED (0x08) -#define MCF_GPIO_PLDPAR_COLLED_COLLED (0x10) -#define MCF_GPIO_PLDPAR_RXLED_RXLED (0x20) -#define MCF_GPIO_PLDPAR_TXLED_TXLED (0x40) - -/* Bit definitions and macros for MCF_GPIO_PGPPAR */ -#define MCF_GPIO_PGPPAR_PGPPAR0 (0x01) -#define MCF_GPIO_PGPPAR_PGPPAR1 (0x02) -#define MCF_GPIO_PGPPAR_PGPPAR2 (0x04) -#define MCF_GPIO_PGPPAR_PGPPAR3 (0x08) -#define MCF_GPIO_PGPPAR_PGPPAR4 (0x10) -#define MCF_GPIO_PGPPAR_PGPPAR5 (0x20) -#define MCF_GPIO_PGPPAR_PGPPAR6 (0x40) -#define MCF_GPIO_PGPPAR_PGPPAR7 (0x80) -#define MCF_GPIO_PGPPAR_IRQ8_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ9_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ10_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ11_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ12_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ13_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ14_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ15_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ8_IRQ8 (0x01) -#define MCF_GPIO_PGPPAR_IRQ9_IRQ9 (0x02) -#define MCF_GPIO_PGPPAR_IRQ10_IRQ10 (0x04) -#define MCF_GPIO_PGPPAR_IRQ11_IRQ11 (0x08) -#define MCF_GPIO_PGPPAR_IRQ12_IRQ12 (0x10) -#define MCF_GPIO_PGPPAR_IRQ13_IRQ13 (0x30) -#define MCF_GPIO_PGPPAR_IRQ14_IRQ14 (0x40) -#define MCF_GPIO_PGPPAR_IRQ15_IRQ15 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PWOR */ -#define MCF_GPIO_PWOR_PWOR0 (0x0001) -#define MCF_GPIO_PWOR_PWOR1 (0x0002) -#define MCF_GPIO_PWOR_PWOR2 (0x0004) -#define MCF_GPIO_PWOR_PWOR3 (0x0008) -#define MCF_GPIO_PWOR_PWOR4 (0x0010) -#define MCF_GPIO_PWOR_PWOR5 (0x0020) -#define MCF_GPIO_PWOR_PWOR6 (0x0040) -#define MCF_GPIO_PWOR_PWOR7 (0x0080) -#define MCF_GPIO_PWOR_PWOR8 (0x0100) -#define MCF_GPIO_PWOR_PWOR9 (0x0200) -#define MCF_GPIO_PWOR_PWOR10 (0x0400) -#define MCF_GPIO_PWOR_PWOR11 (0x0800) -#define MCF_GPIO_PWOR_PWOR12 (0x1000) -#define MCF_GPIO_PWOR_PWOR13 (0x2000) -#define MCF_GPIO_PWOR_PWOR14 (0x4000) -#define MCF_GPIO_PWOR_PWOR15 (0x8000) - -/* Bit definitions and macros for MCF_GPIO_PDSRH */ -#define MCF_GPIO_PDSRH_PDSR32 (0x0001) -#define MCF_GPIO_PDSRH_PDSR33 (0x0002) -#define MCF_GPIO_PDSRH_PDSR34 (0x0004) -#define MCF_GPIO_PDSRH_PDSR35 (0x0008) -#define MCF_GPIO_PDSRH_PDSR36 (0x0010) -#define MCF_GPIO_PDSRH_PDSR37 (0x0020) -#define MCF_GPIO_PDSRH_PDSR38 (0x0040) -#define MCF_GPIO_PDSRH_PDSR39 (0x0080) -#define MCF_GPIO_PDSRH_PDSR40 (0x0100) -#define MCF_GPIO_PDSRH_PDSR41 (0x0200) -#define MCF_GPIO_PDSRH_PDSR42 (0x0400) -#define MCF_GPIO_PDSRH_PDSR43 (0x0800) -#define MCF_GPIO_PDSRH_PDSR44 (0x1000) -#define MCF_GPIO_PDSRH_PDSR45 (0x2000) -#define MCF_GPIO_PDSRH_PDSR46 (0x4000) -#define MCF_GPIO_PDSRH_PDSR47 (0x8000) - -/* Bit definitions and macros for MCF_GPIO_PDSRL */ -#define MCF_GPIO_PDSRL_PDSR0 (0x00000001) -#define MCF_GPIO_PDSRL_PDSR1 (0x00000002) -#define MCF_GPIO_PDSRL_PDSR2 (0x00000004) -#define MCF_GPIO_PDSRL_PDSR3 (0x00000008) -#define MCF_GPIO_PDSRL_PDSR4 (0x00000010) -#define MCF_GPIO_PDSRL_PDSR5 (0x00000020) -#define MCF_GPIO_PDSRL_PDSR6 (0x00000040) -#define MCF_GPIO_PDSRL_PDSR7 (0x00000080) -#define MCF_GPIO_PDSRL_PDSR8 (0x00000100) -#define MCF_GPIO_PDSRL_PDSR9 (0x00000200) -#define MCF_GPIO_PDSRL_PDSR10 (0x00000400) -#define MCF_GPIO_PDSRL_PDSR11 (0x00000800) -#define MCF_GPIO_PDSRL_PDSR12 (0x00001000) -#define MCF_GPIO_PDSRL_PDSR13 (0x00002000) -#define MCF_GPIO_PDSRL_PDSR14 (0x00004000) -#define MCF_GPIO_PDSRL_PDSR15 (0x00008000) -#define MCF_GPIO_PDSRL_PDSR16 (0x00010000) -#define MCF_GPIO_PDSRL_PDSR17 (0x00020000) -#define MCF_GPIO_PDSRL_PDSR18 (0x00040000) -#define MCF_GPIO_PDSRL_PDSR19 (0x00080000) -#define MCF_GPIO_PDSRL_PDSR20 (0x00100000) -#define MCF_GPIO_PDSRL_PDSR21 (0x00200000) -#define MCF_GPIO_PDSRL_PDSR22 (0x00400000) -#define MCF_GPIO_PDSRL_PDSR23 (0x00800000) -#define MCF_GPIO_PDSRL_PDSR24 (0x01000000) -#define MCF_GPIO_PDSRL_PDSR25 (0x02000000) -#define MCF_GPIO_PDSRL_PDSR26 (0x04000000) -#define MCF_GPIO_PDSRL_PDSR27 (0x08000000) -#define MCF_GPIO_PDSRL_PDSR28 (0x10000000) -#define MCF_GPIO_PDSRL_PDSR29 (0x20000000) -#define MCF_GPIO_PDSRL_PDSR30 (0x40000000) -#define MCF_GPIO_PDSRL_PDSR31 (0x80000000) - -/********************************************************************* -* -* ColdFire Integration Module (CIM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CIM_RCR (*(vuint8 *)(&__IPSBAR[0x110000])) -#define MCF_CIM_RSR (*(vuint8 *)(&__IPSBAR[0x110001])) -#define MCF_CIM_CCR (*(vuint16*)(&__IPSBAR[0x110004])) -#define MCF_CIM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) -#define MCF_CIM_RCON (*(vuint16*)(&__IPSBAR[0x110008])) -#define MCF_CIM_CIR (*(vuint16*)(&__IPSBAR[0x11000A])) - -/* Bit definitions and macros for MCF_CIM_RCR */ -#define MCF_CIM_RCR_LVDE (0x01) -#define MCF_CIM_RCR_LVDRE (0x04) -#define MCF_CIM_RCR_LVDIE (0x08) -#define MCF_CIM_RCR_LVDF (0x10) -#define MCF_CIM_RCR_FRCRSTOUT (0x40) -#define MCF_CIM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for MCF_CIM_RSR */ -#define MCF_CIM_RSR_LOL (0x01) -#define MCF_CIM_RSR_LOC (0x02) -#define MCF_CIM_RSR_EXT (0x04) -#define MCF_CIM_RSR_POR (0x08) -#define MCF_CIM_RSR_WDR (0x10) -#define MCF_CIM_RSR_SOFT (0x20) -#define MCF_CIM_RSR_LVD (0x40) - -/* Bit definitions and macros for MCF_CIM_CCR */ -#define MCF_CIM_CCR_LOAD (0x8000) - -/* Bit definitions and macros for MCF_CIM_LPCR */ -#define MCF_CIM_LPCR_LVDSE (0x02) -#define MCF_CIM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF_CIM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF_CIM_LPCR_LPMD_STOP (0xC0) -#define MCF_CIM_LPCR_LPMD_WAIT (0x80) -#define MCF_CIM_LPCR_LPMD_DOZE (0x40) -#define MCF_CIM_LPCR_LPMD_RUN (0x00) - -/* Bit definitions and macros for MCF_CIM_RCON */ -#define MCF_CIM_RCON_RLOAD (0x0020) - -/********************************************************************* -* -* Clock Module (CLOCK) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CLOCK_SYNCR (*(vuint16*)(&__IPSBAR[0x120000])) -#define MCF_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002])) -#define MCF_CLOCK_LPCR (*(vuint8 *)(&__IPSBAR[0x120007])) -#define MCF_CLOCK_CCHR (*(vuint8 *)(&__IPSBAR[0x120008])) -#define MCF_CLOCK_RTCDR (*(vuint32*)(&__IPSBAR[0x12000C])) - -/* Bit definitions and macros for MCF_CLOCK_SYNCR */ -#define MCF_CLOCK_SYNCR_PLLEN (0x0001) -#define MCF_CLOCK_SYNCR_PLLMODE (0x0002) -#define MCF_CLOCK_SYNCR_CLKSRC (0x0004) -#define MCF_CLOCK_SYNCR_FWKUP (0x0020) -#define MCF_CLOCK_SYNCR_DISCLK (0x0040) -#define MCF_CLOCK_SYNCR_LOCEN (0x0080) -#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) -#define MCF_CLOCK_SYNCR_LOCRE (0x0800) -#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) -#define MCF_CLOCK_SYNCR_LOLRE (0x8000) - -/* Bit definitions and macros for MCF_CLOCK_SYNSR */ -#define MCF_CLOCK_SYNSR_LOCS (0x04) -#define MCF_CLOCK_SYNSR_LOCK (0x08) -#define MCF_CLOCK_SYNSR_LOCKS (0x10) -#define MCF_CLOCK_SYNSR_CRYOSC (0x20) -#define MCF_CLOCK_SYNSR_OCOSC (0x40) -#define MCF_CLOCK_SYNSR_EXTOSC (0x80) - -/* Bit definitions and macros for MCF_CLOCK_LPCR */ -#define MCF_CLOCK_LPCR_LPD(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_CLOCK_CCHR */ -#define MCF_CLOCK_CCHR_PFD(x) (((x)&0x07)<<0) - -/* Bit definitions and macros for MCF_CLOCK_RTCDR */ -#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* -* -* Edge Port Module (EPORT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_EPORT_EPPAR0 (*(vuint16*)(&__IPSBAR[0x130000])) -#define MCF_EPORT_EPPAR1 (*(vuint16*)(&__IPSBAR[0x140000])) -#define MCF_EPORT_EPDDR0 (*(vuint8 *)(&__IPSBAR[0x130002])) -#define MCF_EPORT_EPDDR1 (*(vuint8 *)(&__IPSBAR[0x140002])) -#define MCF_EPORT_EPIER0 (*(vuint8 *)(&__IPSBAR[0x130003])) -#define MCF_EPORT_EPIER1 (*(vuint8 *)(&__IPSBAR[0x140003])) -#define MCF_EPORT_EPDR0 (*(vuint8 *)(&__IPSBAR[0x130004])) -#define MCF_EPORT_EPDR1 (*(vuint8 *)(&__IPSBAR[0x140004])) -#define MCF_EPORT_EPPDR0 (*(vuint8 *)(&__IPSBAR[0x130005])) -#define MCF_EPORT_EPPDR1 (*(vuint8 *)(&__IPSBAR[0x140005])) -#define MCF_EPORT_EPFR0 (*(vuint8 *)(&__IPSBAR[0x130006])) -#define MCF_EPORT_EPFR1 (*(vuint8 *)(&__IPSBAR[0x140006])) - -/* Bit definitions and macros for MCF_EPORT_EPPAR */ -#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_EPPA8(x) (((x)&0x0003)<<0) -#define MCF_EPORT_EPPAR_EPPA9(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA10(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA11(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA12(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA13(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA14(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA15(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_LEVEL (0) -#define MCF_EPORT_EPPAR_RISING (1) -#define MCF_EPORT_EPPAR_FALLING (2) -#define MCF_EPORT_EPPAR_BOTH (3) -#define MCF_EPORT_EPPAR_EPPA15_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA15_RISING (0x4000) -#define MCF_EPORT_EPPAR_EPPA15_FALLING (0x8000) -#define MCF_EPORT_EPPAR_EPPA15_BOTH (0xC000) -#define MCF_EPORT_EPPAR_EPPA14_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA14_RISING (0x1000) -#define MCF_EPORT_EPPAR_EPPA14_FALLING (0x2000) -#define MCF_EPORT_EPPAR_EPPA14_BOTH (0x3000) -#define MCF_EPORT_EPPAR_EPPA13_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA13_RISING (0x0400) -#define MCF_EPORT_EPPAR_EPPA13_FALLING (0x0800) -#define MCF_EPORT_EPPAR_EPPA13_BOTH (0x0C00) -#define MCF_EPORT_EPPAR_EPPA12_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA12_RISING (0x0100) -#define MCF_EPORT_EPPAR_EPPA12_FALLING (0x0200) -#define MCF_EPORT_EPPAR_EPPA12_BOTH (0x0300) -#define MCF_EPORT_EPPAR_EPPA11_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA11_RISING (0x0040) -#define MCF_EPORT_EPPAR_EPPA11_FALLING (0x0080) -#define MCF_EPORT_EPPAR_EPPA11_BOTH (0x00C0) -#define MCF_EPORT_EPPAR_EPPA10_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA10_RISING (0x0010) -#define MCF_EPORT_EPPAR_EPPA10_FALLING (0x0020) -#define MCF_EPORT_EPPAR_EPPA10_BOTH (0x0030) -#define MCF_EPORT_EPPAR_EPPA9_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA9_RISING (0x0004) -#define MCF_EPORT_EPPAR_EPPA9_FALLING (0x0008) -#define MCF_EPORT_EPPAR_EPPA9_BOTH (0x000C) -#define MCF_EPORT_EPPAR_EPPA8_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA8_RISING (0x0001) -#define MCF_EPORT_EPPAR_EPPA8_FALLING (0x0002) -#define MCF_EPORT_EPPAR_EPPA8_BOTH (0x0003) -#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) -#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) -#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) -#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) -#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) -#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) -#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) -#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) -#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) -#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) -#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) -#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) -#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) -#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) -#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) -#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) -#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) -#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) -#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) -#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) -#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) - -/* Bit definitions and macros for MCF_EPORT_EPDDR */ -#define MCF_EPORT_EPDDR_EPDD1 (0x02) -#define MCF_EPORT_EPDDR_EPDD2 (0x04) -#define MCF_EPORT_EPDDR_EPDD3 (0x08) -#define MCF_EPORT_EPDDR_EPDD4 (0x10) -#define MCF_EPORT_EPDDR_EPDD5 (0x20) -#define MCF_EPORT_EPDDR_EPDD6 (0x40) -#define MCF_EPORT_EPDDR_EPDD7 (0x80) -#define MCF_EPORT_EPDDR_EPDD8 (0x01) -#define MCF_EPORT_EPDDR_EPDD9 (0x02) -#define MCF_EPORT_EPDDR_EPDD10 (0x04) -#define MCF_EPORT_EPDDR_EPDD11 (0x08) -#define MCF_EPORT_EPDDR_EPDD12 (0x10) -#define MCF_EPORT_EPDDR_EPDD13 (0x20) -#define MCF_EPORT_EPDDR_EPDD14 (0x40) -#define MCF_EPORT_EPDDR_EPDD15 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPIER */ -#define MCF_EPORT_EPIER_EPIE1 (0x02) -#define MCF_EPORT_EPIER_EPIE2 (0x04) -#define MCF_EPORT_EPIER_EPIE3 (0x08) -#define MCF_EPORT_EPIER_EPIE4 (0x10) -#define MCF_EPORT_EPIER_EPIE5 (0x20) -#define MCF_EPORT_EPIER_EPIE6 (0x40) -#define MCF_EPORT_EPIER_EPIE7 (0x80) -#define MCF_EPORT_EPIER_EPIE8 (0x01) -#define MCF_EPORT_EPIER_EPIE9 (0x02) -#define MCF_EPORT_EPIER_EPIE10 (0x04) -#define MCF_EPORT_EPIER_EPIE11 (0x08) -#define MCF_EPORT_EPIER_EPIE12 (0x10) -#define MCF_EPORT_EPIER_EPIE13 (0x20) -#define MCF_EPORT_EPIER_EPIE14 (0x40) -#define MCF_EPORT_EPIER_EPIE15 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPDR */ -#define MCF_EPORT_EPDR_EPD1 (0x02) -#define MCF_EPORT_EPDR_EPD2 (0x04) -#define MCF_EPORT_EPDR_EPD3 (0x08) -#define MCF_EPORT_EPDR_EPD4 (0x10) -#define MCF_EPORT_EPDR_EPD5 (0x20) -#define MCF_EPORT_EPDR_EPD6 (0x40) -#define MCF_EPORT_EPDR_EPD7 (0x80) -#define MCF_EPORT_EPDR_EPD8 (0x01) -#define MCF_EPORT_EPDR_EPD9 (0x02) -#define MCF_EPORT_EPDR_EPD10 (0x04) -#define MCF_EPORT_EPDR_EPD11 (0x08) -#define MCF_EPORT_EPDR_EPD12 (0x10) -#define MCF_EPORT_EPDR_EPD13 (0x20) -#define MCF_EPORT_EPDR_EPD14 (0x40) -#define MCF_EPORT_EPDR_EPD15 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPPDR */ -#define MCF_EPORT_EPPDR_EPPD1 (0x02) -#define MCF_EPORT_EPPDR_EPPD2 (0x04) -#define MCF_EPORT_EPPDR_EPPD3 (0x08) -#define MCF_EPORT_EPPDR_EPPD4 (0x10) -#define MCF_EPORT_EPPDR_EPPD5 (0x20) -#define MCF_EPORT_EPPDR_EPPD6 (0x40) -#define MCF_EPORT_EPPDR_EPPD7 (0x80) -#define MCF_EPORT_EPPDR_EPPD8 (0x01) -#define MCF_EPORT_EPPDR_EPPD9 (0x02) -#define MCF_EPORT_EPPDR_EPPD10 (0x04) -#define MCF_EPORT_EPPDR_EPPD11 (0x08) -#define MCF_EPORT_EPPDR_EPPD12 (0x10) -#define MCF_EPORT_EPPDR_EPPD13 (0x20) -#define MCF_EPORT_EPPDR_EPPD14 (0x40) -#define MCF_EPORT_EPPDR_EPPD15 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPFR */ -#define MCF_EPORT_EPFR_EPF1 (0x02) -#define MCF_EPORT_EPFR_EPF2 (0x04) -#define MCF_EPORT_EPFR_EPF3 (0x08) -#define MCF_EPORT_EPFR_EPF4 (0x10) -#define MCF_EPORT_EPFR_EPF5 (0x20) -#define MCF_EPORT_EPFR_EPF6 (0x40) -#define MCF_EPORT_EPFR_EPF7 (0x80) -#define MCF_EPORT_EPFR_EPF8 (0x01) -#define MCF_EPORT_EPFR_EPF9 (0x02) -#define MCF_EPORT_EPFR_EPF10 (0x04) -#define MCF_EPORT_EPFR_EPF11 (0x08) -#define MCF_EPORT_EPFR_EPF12 (0x10) -#define MCF_EPORT_EPFR_EPF13 (0x20) -#define MCF_EPORT_EPFR_EPF14 (0x40) -#define MCF_EPORT_EPFR_EPF15 (0x80) - -/********************************************************************* -* -* Programmable Interrupt Timer Modules (PIT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PIT0_PCSR (*(vuint16*)(&__IPSBAR[0x150000])) -#define MCF_PIT0_PMR (*(vuint16*)(&__IPSBAR[0x150002])) -#define MCF_PIT0_PCNTR (*(vuint16*)(&__IPSBAR[0x150004])) -#define MCF_PIT1_PCSR (*(vuint16*)(&__IPSBAR[0x160000])) -#define MCF_PIT1_PMR (*(vuint16*)(&__IPSBAR[0x160002])) -#define MCF_PIT1_PCNTR (*(vuint16*)(&__IPSBAR[0x160004])) -#define MCF_PIT_PCSR(x) (*(vuint16*)(&__IPSBAR[0x150000+((x)*0x10000)])) -#define MCF_PIT_PMR(x) (*(vuint16*)(&__IPSBAR[0x150002+((x)*0x10000)])) -#define MCF_PIT_PCNTR(x) (*(vuint16*)(&__IPSBAR[0x150004+((x)*0x10000)])) - -/* Bit definitions and macros for MCF_PIT_PCSR */ -#define MCF_PIT_PCSR_EN (0x0001) -#define MCF_PIT_PCSR_RLD (0x0002) -#define MCF_PIT_PCSR_PIF (0x0004) -#define MCF_PIT_PCSR_PIE (0x0008) -#define MCF_PIT_PCSR_OVW (0x0010) -#define MCF_PIT_PCSR_HALTED (0x0020) -#define MCF_PIT_PCSR_DOZE (0x0040) -#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) - -/* Bit definitions and macros for MCF_PIT_PMR */ -#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_PIT_PCNTR */ -#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0) - -/********************************************************************* -* -* Analog-to-Digital Converter (ADC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_ADC_CTRL1 (*(vuint16*)(&__IPSBAR[0x190000])) -#define MCF_ADC_CTRL2 (*(vuint16*)(&__IPSBAR[0x190002])) -#define MCF_ADC_ADZCC (*(vuint16*)(&__IPSBAR[0x190004])) -#define MCF_ADC_ADLST1 (*(vuint16*)(&__IPSBAR[0x190006])) -#define MCF_ADC_ADLST2 (*(vuint16*)(&__IPSBAR[0x190008])) -#define MCF_ADC_ADSDIS (*(vuint16*)(&__IPSBAR[0x19000A])) -#define MCF_ADC_ADSTAT (*(vuint16*)(&__IPSBAR[0x19000C])) -#define MCF_ADC_ADLSTAT (*(vuint16*)(&__IPSBAR[0x19000E])) -#define MCF_ADC_ADZCSTAT (*(vuint16*)(&__IPSBAR[0x190010])) -#define MCF_ADC_ADRSLT0 (*(vuint16*)(&__IPSBAR[0x190012])) -#define MCF_ADC_ADRSLT1 (*(vuint16*)(&__IPSBAR[0x190014])) -#define MCF_ADC_ADRSLT2 (*(vuint16*)(&__IPSBAR[0x190016])) -#define MCF_ADC_ADRSLT3 (*(vuint16*)(&__IPSBAR[0x190018])) -#define MCF_ADC_ADRSLT4 (*(vuint16*)(&__IPSBAR[0x19001A])) -#define MCF_ADC_ADRSLT5 (*(vuint16*)(&__IPSBAR[0x19001C])) -#define MCF_ADC_ADRSLT6 (*(vuint16*)(&__IPSBAR[0x19001E])) -#define MCF_ADC_ADRSLT7 (*(vuint16*)(&__IPSBAR[0x190020])) -#define MCF_ADC_ADRSLT(x) (*(vuint16*)(&__IPSBAR[0x190012+((x)*0x002)])) -#define MCF_ADC_ADLLMT0 (*(vuint16*)(&__IPSBAR[0x190022])) -#define MCF_ADC_ADLLMT1 (*(vuint16*)(&__IPSBAR[0x190024])) -#define MCF_ADC_ADLLMT2 (*(vuint16*)(&__IPSBAR[0x190026])) -#define MCF_ADC_ADLLMT3 (*(vuint16*)(&__IPSBAR[0x190028])) -#define MCF_ADC_ADLLMT4 (*(vuint16*)(&__IPSBAR[0x19002A])) -#define MCF_ADC_ADLLMT5 (*(vuint16*)(&__IPSBAR[0x19002C])) -#define MCF_ADC_ADLLMT6 (*(vuint16*)(&__IPSBAR[0x19002E])) -#define MCF_ADC_ADLLMT7 (*(vuint16*)(&__IPSBAR[0x190030])) -#define MCF_ADC_ADLLMT(x) (*(vuint16*)(&__IPSBAR[0x190022+((x)*0x002)])) -#define MCF_ADC_ADHLMT0 (*(vuint16*)(&__IPSBAR[0x190032])) -#define MCF_ADC_ADHLMT1 (*(vuint16*)(&__IPSBAR[0x190034])) -#define MCF_ADC_ADHLMT2 (*(vuint16*)(&__IPSBAR[0x190036])) -#define MCF_ADC_ADHLMT3 (*(vuint16*)(&__IPSBAR[0x190038])) -#define MCF_ADC_ADHLMT4 (*(vuint16*)(&__IPSBAR[0x19003A])) -#define MCF_ADC_ADHLMT5 (*(vuint16*)(&__IPSBAR[0x19003C])) -#define MCF_ADC_ADHLMT6 (*(vuint16*)(&__IPSBAR[0x19003E])) -#define MCF_ADC_ADHLMT7 (*(vuint16*)(&__IPSBAR[0x190040])) -#define MCF_ADC_ADHLMT(x) (*(vuint16*)(&__IPSBAR[0x190032+((x)*0x002)])) -#define MCF_ADC_ADOFS0 (*(vuint16*)(&__IPSBAR[0x190042])) -#define MCF_ADC_ADOFS1 (*(vuint16*)(&__IPSBAR[0x190044])) -#define MCF_ADC_ADOFS2 (*(vuint16*)(&__IPSBAR[0x190046])) -#define MCF_ADC_ADOFS3 (*(vuint16*)(&__IPSBAR[0x190048])) -#define MCF_ADC_ADOFS4 (*(vuint16*)(&__IPSBAR[0x19004A])) -#define MCF_ADC_ADOFS5 (*(vuint16*)(&__IPSBAR[0x19004C])) -#define MCF_ADC_ADOFS6 (*(vuint16*)(&__IPSBAR[0x19004E])) -#define MCF_ADC_ADOFS7 (*(vuint16*)(&__IPSBAR[0x190050])) -#define MCF_ADC_ADOFS(x) (*(vuint16*)(&__IPSBAR[0x190042+((x)*0x002)])) -#define MCF_ADC_POWER (*(vuint16*)(&__IPSBAR[0x190052])) -#define MCF_ADC_CAL (*(vuint16*)(&__IPSBAR[0x190054])) - -/* Bit definitions and macros for MCF_ADC_CTRL1 */ -#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x0007)<<0) -#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0x000F)<<4) -#define MCF_ADC_CTRL1_HLMTIE (0x0100) -#define MCF_ADC_CTRL1_LLMTIE (0x0200) -#define MCF_ADC_CTRL1_ZCIE (0x0400) -#define MCF_ADC_CTRL1_EOSIE0 (0x0800) -#define MCF_ADC_CTRL1_SYNC0 (0x1000) -#define MCF_ADC_CTRL1_START0 (0x2000) -#define MCF_ADC_CTRL1_STOP0 (0x4000) - -/* Bit definitions and macros for MCF_ADC_CTRL2 */ -#define MCF_ADC_CTRL2_DIV(x) (((x)&0x001F)<<0) -#define MCF_ADC_CTRL2_SIMULT (0x0020) -#define MCF_ADC_CTRL2_EOSIE1 (0x0800) -#define MCF_ADC_CTRL2_SYNC1 (0x1000) -#define MCF_ADC_CTRL2_START1 (0x2000) -#define MCF_ADC_CTRL2_STOP1 (0x4000) - -/* Bit definitions and macros for MCF_ADC_ADZCC */ -#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x0003)<<0) -#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x0003)<<2) -#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x0003)<<4) -#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x0003)<<6) -#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x0003)<<8) -#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x0003)<<10) -#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x0003)<<12) -#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x0003)<<14) - -/* Bit definitions and macros for MCF_ADC_ADLST1 */ -#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x0007)<<0) -#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x0007)<<4) -#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x0007)<<8) -#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x0007)<<12) - -/* Bit definitions and macros for MCF_ADC_ADLST2 */ -#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x0007)<<0) -#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x0007)<<4) -#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x0007)<<8) -#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x0007)<<12) - -/* Bit definitions and macros for MCF_ADC_ADSDIS */ -#define MCF_ADC_ADSDIS_DS0 (0x0001) -#define MCF_ADC_ADSDIS_DS1 (0x0002) -#define MCF_ADC_ADSDIS_DS2 (0x0004) -#define MCF_ADC_ADSDIS_DS3 (0x0008) -#define MCF_ADC_ADSDIS_DS4 (0x0010) -#define MCF_ADC_ADSDIS_DS5 (0x0020) -#define MCF_ADC_ADSDIS_DS6 (0x0040) -#define MCF_ADC_ADSDIS_DS7 (0x0080) - -/* Bit definitions and macros for MCF_ADC_ADSTAT */ -#define MCF_ADC_ADSTAT_RDY0 (0x0001) -#define MCF_ADC_ADSTAT_RDY1 (0x0002) -#define MCF_ADC_ADSTAT_RDY2 (0x0004) -#define MCF_ADC_ADSTAT_RDY3 (0x0008) -#define MCF_ADC_ADSTAT_RDY4 (0x0010) -#define MCF_ADC_ADSTAT_RDY5 (0x0020) -#define MCF_ADC_ADSTAT_RDY6 (0x0040) -#define MCF_ADC_ADSTAT_RDY7 (0x0080) -#define MCF_ADC_ADSTAT_HLMT (0x0100) -#define MCF_ADC_ADSTAT_LLMTI (0x0200) -#define MCF_ADC_ADSTAT_ZCI (0x0400) -#define MCF_ADC_ADSTAT_EOSI (0x0800) -#define MCF_ADC_ADSTAT_CIP (0x8000) - -/* Bit definitions and macros for MCF_ADC_ADLSTAT */ -#define MCF_ADC_ADLSTAT_LLS0 (0x0001) -#define MCF_ADC_ADLSTAT_LLS1 (0x0002) -#define MCF_ADC_ADLSTAT_LLS2 (0x0004) -#define MCF_ADC_ADLSTAT_LLS3 (0x0008) -#define MCF_ADC_ADLSTAT_LLS4 (0x0010) -#define MCF_ADC_ADLSTAT_LLS5 (0x0020) -#define MCF_ADC_ADLSTAT_LLS6 (0x0040) -#define MCF_ADC_ADLSTAT_LLS7 (0x0080) -#define MCF_ADC_ADLSTAT_HLS0 (0x0100) -#define MCF_ADC_ADLSTAT_HLS1 (0x0200) -#define MCF_ADC_ADLSTAT_HLS2 (0x0400) -#define MCF_ADC_ADLSTAT_HLS3 (0x0800) -#define MCF_ADC_ADLSTAT_HLS4 (0x1000) -#define MCF_ADC_ADLSTAT_HLS5 (0x2000) -#define MCF_ADC_ADLSTAT_HLS6 (0x4000) -#define MCF_ADC_ADLSTAT_HLS7 (0x8000) - -/* Bit definitions and macros for MCF_ADC_ADZCSTAT */ -#define MCF_ADC_ADZCSTAT_ZCS0 (0x0001) -#define MCF_ADC_ADZCSTAT_ZCS1 (0x0002) -#define MCF_ADC_ADZCSTAT_ZCS2 (0x0004) -#define MCF_ADC_ADZCSTAT_ZCS3 (0x0008) -#define MCF_ADC_ADZCSTAT_ZCS4 (0x0010) -#define MCF_ADC_ADZCSTAT_ZCS5 (0x0020) -#define MCF_ADC_ADZCSTAT_ZCS6 (0x0040) -#define MCF_ADC_ADZCSTAT_ZCS7 (0x0080) - -/* Bit definitions and macros for MCF_ADC_ADRSLT */ -#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0x0FFF)<<3) -#define MCF_ADC_ADRSLT_SEXT (0x8000) - -/* Bit definitions and macros for MCF_ADC_ADLLMT */ -#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0x0FFF)<<3) - -/* Bit definitions and macros for MCF_ADC_ADHLMT */ -#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0x0FFF)<<3) - -/* Bit definitions and macros for MCF_ADC_ADOFS */ -#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0x0FFF)<<3) - -/* Bit definitions and macros for MCF_ADC_POWER */ -#define MCF_ADC_POWER_PD0 (0x0001) -#define MCF_ADC_POWER_PD1 (0x0002) -#define MCF_ADC_POWER_PD2 (0x0004) -#define MCF_ADC_POWER_APD (0x0008) -#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x003F)<<4) -#define MCF_ADC_POWER_PSTS0 (0x0400) -#define MCF_ADC_POWER_PSTS1 (0x0800) -#define MCF_ADC_POWER_PSTS2 (0x1000) -#define MCF_ADC_POWER_ASTBY (0x8000) - -/* Bit definitions and macros for MCF_ADC_CAL */ -#define MCF_ADC_CAL_CAL0 (0x0001) -#define MCF_ADC_CAL_CRS0 (0x0002) -#define MCF_ADC_CAL_CAL1 (0x0004) -#define MCF_ADC_CAL_CRS1 (0x0008) - -/********************************************************************* -* -* General Purpose Timer (GPT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPT_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000])) -#define MCF_GPT_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001])) -#define MCF_GPT_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002])) -#define MCF_GPT_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003])) -#define MCF_GPT_GPTCNT (*(vuint16*)(&__IPSBAR[0x1A0004])) -#define MCF_GPT_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006])) -#define MCF_GPT_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008])) -#define MCF_GPT_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009])) -#define MCF_GPT_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B])) -#define MCF_GPT_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C])) -#define MCF_GPT_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D])) -#define MCF_GPT_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E])) -#define MCF_GPT_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F])) -#define MCF_GPT_GPTC0 (*(vuint16*)(&__IPSBAR[0x1A0010])) -#define MCF_GPT_GPTC1 (*(vuint16*)(&__IPSBAR[0x1A0012])) -#define MCF_GPT_GPTC2 (*(vuint16*)(&__IPSBAR[0x1A0014])) -#define MCF_GPT_GPTC3 (*(vuint16*)(&__IPSBAR[0x1A0016])) -#define MCF_GPT_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1A0010+((x)*0x002)])) -#define MCF_GPT_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018])) -#define MCF_GPT_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019])) -#define MCF_GPT_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1A001A])) -#define MCF_GPT_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D])) -#define MCF_GPT_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E])) - -/* Bit definitions and macros for MCF_GPT_GPTIOS */ -#define MCF_GPT_GPTIOS_IOS0 (0x01) -#define MCF_GPT_GPTIOS_IOS1 (0x02) -#define MCF_GPT_GPTIOS_IOS2 (0x04) -#define MCF_GPT_GPTIOS_IOS3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTCFORC */ -#define MCF_GPT_GPTCFORC_FOC0 (0x01) -#define MCF_GPT_GPTCFORC_FOC1 (0x02) -#define MCF_GPT_GPTCFORC_FOC2 (0x04) -#define MCF_GPT_GPTCFORC_FOC3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTOC3D */ -#define MCF_GPT_GPTOC3D_OC3D0 (0x01) -#define MCF_GPT_GPTOC3D_OC3D1 (0x02) -#define MCF_GPT_GPTOC3D_OC3D2 (0x04) -#define MCF_GPT_GPTOC3D_OC3D3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTSCR1 */ -#define MCF_GPT_GPTSCR1_TFFCA (0x10) -#define MCF_GPT_GPTSCR1_GPTEN (0x80) - -/* Bit definitions and macros for MCF_GPT_GPTTOV */ -#define MCF_GPT_GPTTOV_TOV0 (0x01) -#define MCF_GPT_GPTTOV_TOV1 (0x02) -#define MCF_GPT_GPTTOV_TOV2 (0x04) -#define MCF_GPT_GPTTOV_TOV3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTCTL1 */ -#define MCF_GPT_GPTCTL1_OL0 (0x01) -#define MCF_GPT_GPTCTL1_OM0 (0x02) -#define MCF_GPT_GPTCTL1_OL1 (0x04) -#define MCF_GPT_GPTCTL1_OM1 (0x08) -#define MCF_GPT_GPTCTL1_OL2 (0x10) -#define MCF_GPT_GPTCTL1_OM2 (0x20) -#define MCF_GPT_GPTCTL1_OL3 (0x40) -#define MCF_GPT_GPTCTL1_OM3 (0x80) -#define MCF_GPT_GPTCTL1_OUTPUT3_NOTHING ((0x00)) -#define MCF_GPT_GPTCTL1_OUTPUT3_TOGGLE ((0x40)) -#define MCF_GPT_GPTCTL1_OUTPUT3_CLEAR ((0x80)) -#define MCF_GPT_GPTCTL1_OUTPUT3_SET ((0xC0)) -#define MCF_GPT_GPTCTL1_OUTPUT2_NOTHING ((0x00)) -#define MCF_GPT_GPTCTL1_OUTPUT2_TOGGLE ((0x10)) -#define MCF_GPT_GPTCTL1_OUTPUT2_CLEAR ((0x20)) -#define MCF_GPT_GPTCTL1_OUTPUT2_SET ((0x30)) -#define MCF_GPT_GPTCTL1_OUTPUT1_NOTHING ((0x00)) -#define MCF_GPT_GPTCTL1_OUTPUT1_TOGGLE ((0x04)) -#define MCF_GPT_GPTCTL1_OUTPUT1_CLEAR ((0x08)) -#define MCF_GPT_GPTCTL1_OUTPUT1_SET ((0x0C)) -#define MCF_GPT_GPTCTL1_OUTPUT0_NOTHING ((0x00)) -#define MCF_GPT_GPTCTL1_OUTPUT0_TOGGLE ((0x01)) -#define MCF_GPT_GPTCTL1_OUTPUT0_CLEAR ((0x02)) -#define MCF_GPT_GPTCTL1_OUTPUT0_SET ((0x03)) - -/* Bit definitions and macros for MCF_GPT_GPTCTL2 */ -#define MCF_GPT_GPTCTL2_EDG0A (0x01) -#define MCF_GPT_GPTCTL2_EDG0B (0x02) -#define MCF_GPT_GPTCTL2_EDG1A (0x04) -#define MCF_GPT_GPTCTL2_EDG1B (0x08) -#define MCF_GPT_GPTCTL2_EDG2A (0x10) -#define MCF_GPT_GPTCTL2_EDG2B (0x20) -#define MCF_GPT_GPTCTL2_EDG3A (0x40) -#define MCF_GPT_GPTCTL2_EDG3B (0x80) -#define MCF_GPT_GPTCTL2_INPUT3_DISABLED ((0x00)) -#define MCF_GPT_GPTCTL2_INPUT3_RISING ((0x40)) -#define MCF_GPT_GPTCTL2_INPUT3_FALLING ((0x80)) -#define MCF_GPT_GPTCTL2_INPUT3_ANY ((0xC0)) -#define MCF_GPT_GPTCTL2_INPUT2_DISABLED ((0x00)) -#define MCF_GPT_GPTCTL2_INPUT2_RISING ((0x10)) -#define MCF_GPT_GPTCTL2_INPUT2_FALLING ((0x20)) -#define MCF_GPT_GPTCTL2_INPUT2_ANY ((0x30)) -#define MCF_GPT_GPTCTL2_INPUT1_DISABLED ((0x00)) -#define MCF_GPT_GPTCTL2_INPUT1_RISING ((0x04)) -#define MCF_GPT_GPTCTL2_INPUT1_FALLING ((0x08)) -#define MCF_GPT_GPTCTL2_INPUT1_ANY ((0x0C)) -#define MCF_GPT_GPTCTL2_INPUT0_DISABLED ((0x00)) -#define MCF_GPT_GPTCTL2_INPUT0_RISING ((0x01)) -#define MCF_GPT_GPTCTL2_INPUT0_FALLING ((0x02)) -#define MCF_GPT_GPTCTL2_INPUT0_ANY ((0x03)) - -/* Bit definitions and macros for MCF_GPT_GPTIE */ -#define MCF_GPT_GPTIE_CI0 (0x01) -#define MCF_GPT_GPTIE_CI1 (0x02) -#define MCF_GPT_GPTIE_CI2 (0x04) -#define MCF_GPT_GPTIE_CI3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTSCR2 */ -#define MCF_GPT_GPTSCR2_PR(x) (((x)&0x07)<<0) -#define MCF_GPT_GPTSCR2_TCRE (0x08) -#define MCF_GPT_GPTSCR2_RDPT (0x10) -#define MCF_GPT_GPTSCR2_PUPT (0x20) -#define MCF_GPT_GPTSCR2_TOI (0x80) -#define MCF_GPT_GPTSCR2_PR_1 ((0x00)) -#define MCF_GPT_GPTSCR2_PR_2 ((0x01)) -#define MCF_GPT_GPTSCR2_PR_4 ((0x02)) -#define MCF_GPT_GPTSCR2_PR_8 ((0x03)) -#define MCF_GPT_GPTSCR2_PR_16 ((0x04)) -#define MCF_GPT_GPTSCR2_PR_32 ((0x05)) -#define MCF_GPT_GPTSCR2_PR_64 ((0x06)) -#define MCF_GPT_GPTSCR2_PR_128 ((0x07)) - -/* Bit definitions and macros for MCF_GPT_GPTFLG1 */ -#define MCF_GPT_GPTFLG1_CF0 (0x01) -#define MCF_GPT_GPTFLG1_CF1 (0x02) -#define MCF_GPT_GPTFLG1_CF2 (0x04) -#define MCF_GPT_GPTFLG1_CF3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTFLG2 */ -#define MCF_GPT_GPTFLG2_CF0 (0x01) -#define MCF_GPT_GPTFLG2_CF1 (0x02) -#define MCF_GPT_GPTFLG2_CF2 (0x04) -#define MCF_GPT_GPTFLG2_CF3 (0x08) -#define MCF_GPT_GPTFLG2_TOF (0x80) - -/* Bit definitions and macros for MCF_GPT_GPTC */ -#define MCF_GPT_GPTC_CCNT(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_GPT_GPTPACTL */ -#define MCF_GPT_GPTPACTL_PAI (0x01) -#define MCF_GPT_GPTPACTL_PAOVI (0x02) -#define MCF_GPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) -#define MCF_GPT_GPTPACTL_PEDGE (0x10) -#define MCF_GPT_GPTPACTL_PAMOD (0x20) -#define MCF_GPT_GPTPACTL_PAE (0x40) -#define MCF_GPT_GPTPACTL_CLK_GPTPR ((0x00)) -#define MCF_GPT_GPTPACTL_CLK_PACLK ((0x01)) -#define MCF_GPT_GPTPACTL_CLK_PACLK_256 ((0x02)) -#define MCF_GPT_GPTPACTL_CLK_PACLK_65536 ((0x03)) - -/* Bit definitions and macros for MCF_GPT_GPTPAFLG */ -#define MCF_GPT_GPTPAFLG_PAIF (0x01) -#define MCF_GPT_GPTPAFLG_PAOVF (0x02) - -/* Bit definitions and macros for MCF_GPT_GPTPACNT */ -#define MCF_GPT_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_GPT_GPTPORT */ -#define MCF_GPT_GPTPORT_PORTT(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_GPT_GPTDDR */ -#define MCF_GPT_GPTDDR_DDRT0 (0x01) -#define MCF_GPT_GPTDDR_DDRT1 (0x02) -#define MCF_GPT_GPTDDR_DDRT2 (0x04) -#define MCF_GPT_GPTDDR_DDRT3 (0x08) - -/********************************************************************* -* -* Pulse Width Modulation (PWM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PWM_PWME (*(vuint8 *)(&__IPSBAR[0x1B0000])) -#define MCF_PWM_PWMPOL (*(vuint8 *)(&__IPSBAR[0x1B0001])) -#define MCF_PWM_PWMCLK (*(vuint8 *)(&__IPSBAR[0x1B0002])) -#define MCF_PWM_PWMPRCLK (*(vuint8 *)(&__IPSBAR[0x1B0003])) -#define MCF_PWM_PWMCAE (*(vuint8 *)(&__IPSBAR[0x1B0004])) -#define MCF_PWM_PWMCTL (*(vuint8 *)(&__IPSBAR[0x1B0005])) -#define MCF_PWM_PWMSCLA (*(vuint8 *)(&__IPSBAR[0x1B0008])) -#define MCF_PWM_PWMSCLB (*(vuint8 *)(&__IPSBAR[0x1B0009])) -#define MCF_PWM_PWMCNT0 (*(vuint8 *)(&__IPSBAR[0x1B000C])) -#define MCF_PWM_PWMCNT1 (*(vuint8 *)(&__IPSBAR[0x1B000D])) -#define MCF_PWM_PWMCNT2 (*(vuint8 *)(&__IPSBAR[0x1B000E])) -#define MCF_PWM_PWMCNT3 (*(vuint8 *)(&__IPSBAR[0x1B000F])) -#define MCF_PWM_PWMCNT4 (*(vuint8 *)(&__IPSBAR[0x1B0010])) -#define MCF_PWM_PWMCNT5 (*(vuint8 *)(&__IPSBAR[0x1B0011])) -#define MCF_PWM_PWMCNT6 (*(vuint8 *)(&__IPSBAR[0x1B0012])) -#define MCF_PWM_PWMCNT7 (*(vuint8 *)(&__IPSBAR[0x1B0013])) -#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(&__IPSBAR[0x1B000C+((x)*0x001)])) -#define MCF_PWM_PWMPER0 (*(vuint8 *)(&__IPSBAR[0x1B0014])) -#define MCF_PWM_PWMPER1 (*(vuint8 *)(&__IPSBAR[0x1B0015])) -#define MCF_PWM_PWMPER2 (*(vuint8 *)(&__IPSBAR[0x1B0016])) -#define MCF_PWM_PWMPER3 (*(vuint8 *)(&__IPSBAR[0x1B0017])) -#define MCF_PWM_PWMPER4 (*(vuint8 *)(&__IPSBAR[0x1B0018])) -#define MCF_PWM_PWMPER5 (*(vuint8 *)(&__IPSBAR[0x1B0019])) -#define MCF_PWM_PWMPER6 (*(vuint8 *)(&__IPSBAR[0x1B001A])) -#define MCF_PWM_PWMPER7 (*(vuint8 *)(&__IPSBAR[0x1B001B])) -#define MCF_PWM_PWMPER(x) (*(vuint8 *)(&__IPSBAR[0x1B0014+((x)*0x001)])) -#define MCF_PWM_PWMDTY0 (*(vuint8 *)(&__IPSBAR[0x1B001C])) -#define MCF_PWM_PWMDTY1 (*(vuint8 *)(&__IPSBAR[0x1B001D])) -#define MCF_PWM_PWMDTY2 (*(vuint8 *)(&__IPSBAR[0x1B001E])) -#define MCF_PWM_PWMDTY3 (*(vuint8 *)(&__IPSBAR[0x1B001F])) -#define MCF_PWM_PWMDTY4 (*(vuint8 *)(&__IPSBAR[0x1B0020])) -#define MCF_PWM_PWMDTY5 (*(vuint8 *)(&__IPSBAR[0x1B0021])) -#define MCF_PWM_PWMDTY6 (*(vuint8 *)(&__IPSBAR[0x1B0022])) -#define MCF_PWM_PWMDTY7 (*(vuint8 *)(&__IPSBAR[0x1B0023])) -#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(&__IPSBAR[0x1B001C+((x)*0x001)])) -#define MCF_PWM_PWMSDN (*(vuint8 *)(&__IPSBAR[0x1B0024])) - -/* Bit definitions and macros for MCF_PWM_PWME */ -#define MCF_PWM_PWME_PWME0 (0x01) -#define MCF_PWM_PWME_PWME1 (0x02) -#define MCF_PWM_PWME_PWME2 (0x04) -#define MCF_PWM_PWME_PWME3 (0x08) - -/* Bit definitions and macros for MCF_PWM_PWMPOL */ -#define MCF_PWM_PWMPOL_PPOL0 (0x01) -#define MCF_PWM_PWMPOL_PPOL1 (0x02) -#define MCF_PWM_PWMPOL_PPOL2 (0x04) -#define MCF_PWM_PWMPOL_PPOL3 (0x08) - -/* Bit definitions and macros for MCF_PWM_PWMCLK */ -#define MCF_PWM_PWMCLK_PCLK0 (0x01) -#define MCF_PWM_PWMCLK_PCLK1 (0x02) -#define MCF_PWM_PWMCLK_PCLK2 (0x04) -#define MCF_PWM_PWMCLK_PCLK3 (0x08) - -/* Bit definitions and macros for MCF_PWM_PWMPRCLK */ -#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x07)<<0) -#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_PWM_PWMCAE */ -#define MCF_PWM_PWMCAE_CAE0 (0x01) -#define MCF_PWM_PWMCAE_CAE1 (0x02) -#define MCF_PWM_PWMCAE_CAE2 (0x04) -#define MCF_PWM_PWMCAE_CAE3 (0x08) - -/* Bit definitions and macros for MCF_PWM_PWMCTL */ -#define MCF_PWM_PWMCTL_PFRZ (0x04) -#define MCF_PWM_PWMCTL_PSWAI (0x08) -#define MCF_PWM_PWMCTL_CON01 (0x10) -#define MCF_PWM_PWMCTL_CON23 (0x20) - -/* Bit definitions and macros for MCF_PWM_PWMSCLA */ -#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMSCLB */ -#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMCNT */ -#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMPER */ -#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMDTY */ -#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMSDN */ -#define MCF_PWM_PWMSDN_SDNEN (0x01) -#define MCF_PWM_PWMSDN_PWM7IL (0x02) -#define MCF_PWM_PWMSDN_PWM7IN (0x04) -#define MCF_PWM_PWMSDN_LVL (0x10) -#define MCF_PWM_PWMSDN_RESTART (0x20) -#define MCF_PWM_PWMSDN_IE (0x40) -#define MCF_PWM_PWMSDN_IF (0x80) - -/********************************************************************* -* -* FlexCAN Module (CAN) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CAN_CANMCR (*(vuint32*)(&__IPSBAR[0x1C0000])) -#define MCF_CAN_CANCTRL (*(vuint32*)(&__IPSBAR[0x1C0004])) -#define MCF_CAN_TIMER (*(vuint32*)(&__IPSBAR[0x1C0008])) -#define MCF_CAN_RXGMASK (*(vuint32*)(&__IPSBAR[0x1C0010])) -#define MCF_CAN_RX14MASK (*(vuint32*)(&__IPSBAR[0x1C0014])) -#define MCF_CAN_RX15MASK (*(vuint32*)(&__IPSBAR[0x1C0018])) -#define MCF_CAN_ERRCNT (*(vuint32*)(&__IPSBAR[0x1C001C])) -#define MCF_CAN_ERRSTAT (*(vuint32*)(&__IPSBAR[0x1C0020])) -#define MCF_CAN_IMASK (*(vuint32*)(&__IPSBAR[0x1C0028])) -#define MCF_CAN_IFLAG (*(vuint32*)(&__IPSBAR[0x1C0030])) - -/* Bit definitions and macros for MCF_CAN_CANMCR */ -#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) -#define MCF_CAN_CANMCR_SUPV (0x00800000) -#define MCF_CAN_CANMCR_FRZACK (0x01000000) -#define MCF_CAN_CANMCR_SOFTRST (0x02000000) -#define MCF_CAN_CANMCR_HALT (0x10000000) -#define MCF_CAN_CANMCR_FRZ (0x40000000) -#define MCF_CAN_CANMCR_MDIS (0x80000000) - -/* Bit definitions and macros for MCF_CAN_CANCTRL */ -#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) -#define MCF_CAN_CANCTRL_LOM (0x00000008) -#define MCF_CAN_CANCTRL_LBUF (0x00000010) -#define MCF_CAN_CANCTRL_TSYNC (0x00000020) -#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) -#define MCF_CAN_CANCTRL_SAMP (0x00000080) -#define MCF_CAN_CANCTRL_LPB (0x00001000) -#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) -#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) -#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) -#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) -#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) -#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) -#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_CAN_TIMER */ -#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RXGMASK */ -#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX14MASK */ -#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX15MASK */ -#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_ERRCNT */ -#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) -#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for MCF_CAN_ERRSTAT */ -#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) -#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) -#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) -#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) -#define MCF_CAN_ERRSTAT_TXRX (0x00000040) -#define MCF_CAN_ERRSTAT_IDLE (0x00000080) -#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) -#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) -#define MCF_CAN_ERRSTAT_STFERR (0x00000400) -#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) -#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) -#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) -#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) -#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) -#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) -#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) - -/* Bit definitions and macros for MCF_CAN_IMASK */ -#define MCF_CAN_IMASK_BUF(x) (1<<x) - -/* Bit definitions and macros for MCF_CAN_IFLAG */ -#define MCF_CAN_IFLAG_BUF(x) (1<<x) - -/********************************************************************* -* -* ColdFire Flash Module (CFM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CFM_CFMMCR (*(vuint16*)(&__IPSBAR[0x1D0000])) -#define MCF_CFM_CFMCLKD (*(vuint8 *)(&__IPSBAR[0x1D0002])) -#define MCF_CFM_CFMSEC (*(vuint32*)(&__IPSBAR[0x1D0008])) -#define MCF_CFM_CFMPROT (*(vuint32*)(&__IPSBAR[0x1D0010])) -#define MCF_CFM_CFMSACC (*(vuint32*)(&__IPSBAR[0x1D0014])) -#define MCF_CFM_CFMDACC (*(vuint32*)(&__IPSBAR[0x1D0018])) -#define MCF_CFM_CFMUSTAT (*(vuint8 *)(&__IPSBAR[0x1D0020])) -#define MCF_CFM_CFMCMD (*(vuint8 *)(&__IPSBAR[0x1D0024])) - -/* Bit definitions and macros for MCF_CFM_CFMMCR */ -#define MCF_CFM_CFMMCR_KEYACC (0x0020) -#define MCF_CFM_CFMMCR_CCIE (0x0040) -#define MCF_CFM_CFMMCR_CBEIE (0x0080) -#define MCF_CFM_CFMMCR_AEIE (0x0100) -#define MCF_CFM_CFMMCR_PVIE (0x0200) -#define MCF_CFM_CFMMCR_LOCK (0x0400) - -/* Bit definitions and macros for MCF_CFM_CFMCLKD */ -#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0) -#define MCF_CFM_CFMCLKD_PRDIV8 (0x40) -#define MCF_CFM_CFMCLKD_DIVLD (0x80) - -/* Bit definitions and macros for MCF_CFM_CFMSEC */ -#define MCF_CFM_CFMSEC_SEC(x) (((x)&0x0000FFFF)<<0) -#define MCF_CFM_CFMSEC_SECSTAT (0x40000000) -#define MCF_CFM_CFMSEC_KEYEN (0x80000000) - -/* Bit definitions and macros for MCF_CFM_CFMUSTAT */ -#define MCF_CFM_CFMUSTAT_BLANK (0x04) -#define MCF_CFM_CFMUSTAT_ACCERR (0x10) -#define MCF_CFM_CFMUSTAT_PVIOL (0x20) -#define MCF_CFM_CFMUSTAT_CCIF (0x40) -#define MCF_CFM_CFMUSTAT_CBEIF (0x80) - -/* Bit definitions and macros for MCF_CFM_CFMCMD */ -#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0) -#define MCF_CFM_CFMCMD_RDARY1 (0x05) -#define MCF_CFM_CFMCMD_PGM (0x20) -#define MCF_CFM_CFMCMD_PGERS (0x40) -#define MCF_CFM_CFMCMD_MASERS (0x41) -#define MCF_CFM_CFMCMD_PGERSVER (0x06) - -/********************************************************************* -* -* Interrupt Controller (INTC_IACK) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC_IACK_GSWIACK (*(vuint8 *)(&__IPSBAR[0x000FE0])) -#define MCF_INTC_IACK_GL1IACK (*(vuint8 *)(&__IPSBAR[0x000FE4])) -#define MCF_INTC_IACK_GL2IACK (*(vuint8 *)(&__IPSBAR[0x000FE8])) -#define MCF_INTC_IACK_GL3IACK (*(vuint8 *)(&__IPSBAR[0x000FEC])) -#define MCF_INTC_IACK_GL4IACK (*(vuint8 *)(&__IPSBAR[0x000FF0])) -#define MCF_INTC_IACK_GL5IACK (*(vuint8 *)(&__IPSBAR[0x000FF4])) -#define MCF_INTC_IACK_GL6IACK (*(vuint8 *)(&__IPSBAR[0x000FF8])) -#define MCF_INTC_IACK_GL7IACK (*(vuint8 *)(&__IPSBAR[0x000FFC])) -#define MCF_INTC_IACK_GLIACK(x) (*(vuint8 *)(&__IPSBAR[0x000FE4+((x-1)*0x004)])) - -/* Bit definitions and macros for MCF_INTC_IACK_GSWIACK */ -#define MCF_INTC_IACK_GSWIACK_VECTOR(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_INTC_IACK_GLIACK */ -#define MCF_INTC_IACK_GLIACK_VECTOR(x) (((x)&0xFF)<<0) - -/********************************************************************* -* -* Fast Ethernet Controller (FEC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_FEC_EIR (*(vuint32*)(&__IPSBAR[0x001004])) -#define MCF_FEC_EIMR (*(vuint32*)(&__IPSBAR[0x001008])) -#define MCF_FEC_RDAR (*(vuint32*)(&__IPSBAR[0x001010])) -#define MCF_FEC_TDAR (*(vuint32*)(&__IPSBAR[0x001014])) -#define MCF_FEC_ECR (*(vuint32*)(&__IPSBAR[0x001024])) -#define MCF_FEC_MMFR (*(vuint32*)(&__IPSBAR[0x001040])) -#define MCF_FEC_MSCR (*(vuint32*)(&__IPSBAR[0x001044])) -#define MCF_FEC_MIBC (*(vuint32*)(&__IPSBAR[0x001064])) -#define MCF_FEC_RCR (*(vuint32*)(&__IPSBAR[0x001084])) -#define MCF_FEC_TCR (*(vuint32*)(&__IPSBAR[0x0010C4])) -#define MCF_FEC_PALR (*(vuint32*)(&__IPSBAR[0x0010E4])) -#define MCF_FEC_PAUR (*(vuint32*)(&__IPSBAR[0x0010E8])) -#define MCF_FEC_OPD (*(vuint32*)(&__IPSBAR[0x0010EC])) -#define MCF_FEC_IAUR (*(vuint32*)(&__IPSBAR[0x001118])) -#define MCF_FEC_IALR (*(vuint32*)(&__IPSBAR[0x00111C])) -#define MCF_FEC_GAUR (*(vuint32*)(&__IPSBAR[0x001120])) -#define MCF_FEC_GALR (*(vuint32*)(&__IPSBAR[0x001124])) -#define MCF_FEC_TFWR (*(vuint32*)(&__IPSBAR[0x001144])) -#define MCF_FEC_FRBR (*(vuint32*)(&__IPSBAR[0x00114C])) -#define MCF_FEC_FRSR (*(vuint32*)(&__IPSBAR[0x001150])) -#define MCF_FEC_ERDSR (*(vuint32*)(&__IPSBAR[0x001180])) -#define MCF_FEC_ETDSR (*(vuint32*)(&__IPSBAR[0x001184])) -#define MCF_FEC_EMRBR (*(vuint32*)(&__IPSBAR[0x001188])) -#define MCF_FEC_RMON_T_DROP (*(vuint32*)(&__IPSBAR[0x001200])) -#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(&__IPSBAR[0x001204])) -#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(&__IPSBAR[0x001208])) -#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(&__IPSBAR[0x00120C])) -#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x001210])) -#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x001214])) -#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(&__IPSBAR[0x001218])) -#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(&__IPSBAR[0x00121C])) -#define MCF_FEC_RMON_T_JAB (*(vuint32*)(&__IPSBAR[0x001220])) -#define MCF_FEC_RMON_T_COL (*(vuint32*)(&__IPSBAR[0x001224])) -#define MCF_FEC_RMON_T_P64 (*(vuint32*)(&__IPSBAR[0x001228])) -#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(&__IPSBAR[0x00122C])) -#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(&__IPSBAR[0x001230])) -#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(&__IPSBAR[0x001234])) -#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(&__IPSBAR[0x001238])) -#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x00123C])) -#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x001240])) -#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(&__IPSBAR[0x001244])) -#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(&__IPSBAR[0x001248])) -#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(&__IPSBAR[0x00124C])) -#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(&__IPSBAR[0x001250])) -#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(&__IPSBAR[0x001254])) -#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(&__IPSBAR[0x001258])) -#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(&__IPSBAR[0x00125C])) -#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(&__IPSBAR[0x001260])) -#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(&__IPSBAR[0x001264])) -#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(&__IPSBAR[0x001268])) -#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(&__IPSBAR[0x00126C])) -#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(&__IPSBAR[0x001270])) -#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x001274])) -#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(&__IPSBAR[0x001284])) -#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(&__IPSBAR[0x001288])) -#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(&__IPSBAR[0x00128C])) -#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x001290])) -#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x001294])) -#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(&__IPSBAR[0x001298])) -#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(&__IPSBAR[0x00129C])) -#define MCF_FEC_RMON_R_JAB (*(vuint32*)(&__IPSBAR[0x0012A0])) -#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(&__IPSBAR[0x0012A4])) -#define MCF_FEC_RMON_R_P64 (*(vuint32*)(&__IPSBAR[0x0012A8])) -#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(&__IPSBAR[0x0012AC])) -#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(&__IPSBAR[0x0012B0])) -#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(&__IPSBAR[0x0012B4])) -#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(&__IPSBAR[0x0012B8])) -#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x0012C0])) -#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(&__IPSBAR[0x0012BC])) -#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(&__IPSBAR[0x0012C4])) -#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(&__IPSBAR[0x0012C8])) -#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(&__IPSBAR[0x0012CC])) -#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(&__IPSBAR[0x0012D0])) -#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(&__IPSBAR[0x0012D4])) -#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(&__IPSBAR[0x0012D8])) -#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(&__IPSBAR[0x0012DC])) -#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x0012E0])) - -/* Bit definitions and macros for MCF_FEC_EIR */ -#define MCF_FEC_EIR_UN (0x00080000) -#define MCF_FEC_EIR_RL (0x00100000) -#define MCF_FEC_EIR_LC (0x00200000) -#define MCF_FEC_EIR_EBERR (0x00400000) -#define MCF_FEC_EIR_MII (0x00800000) -#define MCF_FEC_EIR_RXB (0x01000000) -#define MCF_FEC_EIR_RXF (0x02000000) -#define MCF_FEC_EIR_TXB (0x04000000) -#define MCF_FEC_EIR_TXF (0x08000000) -#define MCF_FEC_EIR_GRA (0x10000000) -#define MCF_FEC_EIR_BABT (0x20000000) -#define MCF_FEC_EIR_BABR (0x40000000) -#define MCF_FEC_EIR_HBERR (0x80000000) -#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) - -/* Bit definitions and macros for MCF_FEC_EIMR */ -#define MCF_FEC_EIMR_UN (0x00080000) -#define MCF_FEC_EIMR_RL (0x00100000) -#define MCF_FEC_EIMR_LC (0x00200000) -#define MCF_FEC_EIMR_EBERR (0x00400000) -#define MCF_FEC_EIMR_MII (0x00800000) -#define MCF_FEC_EIMR_RXB (0x01000000) -#define MCF_FEC_EIMR_RXF (0x02000000) -#define MCF_FEC_EIMR_TXB (0x04000000) -#define MCF_FEC_EIMR_TXF (0x08000000) -#define MCF_FEC_EIMR_GRA (0x10000000) -#define MCF_FEC_EIMR_BABT (0x20000000) -#define MCF_FEC_EIMR_BABR (0x40000000) -#define MCF_FEC_EIMR_HBERR (0x80000000) -#define MCF_FEC_EIMR_MASK_ALL (0x00000000) -#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) - -/* Bit definitions and macros for MCF_FEC_RDAR */ -#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_TDAR */ -#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_ECR */ -#define MCF_FEC_ECR_RESET (0x00000001) -#define MCF_FEC_ECR_ETHER_EN (0x00000002) - -/* Bit definitions and macros for MCF_FEC_MMFR */ -#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) -#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) -#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) -#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) -#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) -#define MCF_FEC_MMFR_ST_01 (0x40000000) -#define MCF_FEC_MMFR_OP_READ (0x20000000) -#define MCF_FEC_MMFR_OP_WRITE (0x10000000) -#define MCF_FEC_MMFR_TA_10 (0x00020000) - -/* Bit definitions and macros for MCF_FEC_MSCR */ -#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) -#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) - -/* Bit definitions and macros for MCF_FEC_MIBC */ -#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) -#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) - -/* Bit definitions and macros for MCF_FEC_RCR */ -#define MCF_FEC_RCR_LOOP (0x00000001) -#define MCF_FEC_RCR_DRT (0x00000002) -#define MCF_FEC_RCR_MII_MODE (0x00000004) -#define MCF_FEC_RCR_PROM (0x00000008) -#define MCF_FEC_RCR_BC_REJ (0x00000010) -#define MCF_FEC_RCR_FCE (0x00000020) -#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) - -/* Bit definitions and macros for MCF_FEC_TCR */ -#define MCF_FEC_TCR_GTS (0x00000001) -#define MCF_FEC_TCR_HBC (0x00000002) -#define MCF_FEC_TCR_FDEN (0x00000004) -#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) -#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) - -/* Bit definitions and macros for MCF_FEC_PALR */ -#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_PAUR */ -#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_OPD */ -#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_IAUR */ -#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_IALR */ -#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_GAUR */ -#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_GALR */ -#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_TFWR */ -#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) - -/* Bit definitions and macros for MCF_FEC_FRBR */ -#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_FRSR */ -#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_ERDSR */ -#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_ETDSR */ -#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_EMRBR */ -#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) - -/********************************************************************* -* -* Ethernet PHY (PHY) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PHY_EPHYCTL0 (*(vuint8 *)(&__IPSBAR[0x1E0000])) -#define MCF_PHY_EPHYCTL1 (*(vuint8 *)(&__IPSBAR[0x1E0001])) -#define MCF_PHY_EPHYSR (*(vuint8 *)(&__IPSBAR[0x1E0002])) - -/* Bit definitions and macros for MCF_PHY_EPHYCTL0 */ -#define MCF_PHY_EPHYCTL0_EPHYIEN (0x01) -#define MCF_PHY_EPHYCTL0_EPHYWAI (0x04) -#define MCF_PHY_EPHYCTL0_LEDEN (0x08) -#define MCF_PHY_EPHYCTL0_DIS10 (0x10) -#define MCF_PHY_EPHYCTL0_DIS100 (0x20) -#define MCF_PHY_EPHYCTL0_ANDIS (0x40) -#define MCF_PHY_EPHYCTL0_EPHYEN (0x80) - -/* Bit definitions and macros for MCF_PHY_EPHYCTL1 */ -#define MCF_PHY_EPHYCTL1_PHYADDR(x) (((x)&0x1F)<<0) - -/* Bit definitions and macros for MCF_PHY_EPHYSR */ -#define MCF_PHY_EPHYSR_EPHYIF (0x01) -#define MCF_PHY_EPHYSR_10DIS (0x10) -#define MCF_PHY_EPHYSR_100DIS (0x20) - -/********************************************************************* -* -* Random Number Generator (RNG) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RNG_RNGCR (*(vuint32*)(&__IPSBAR[0x1F0000])) -#define MCF_RNG_RNGSR (*(vuint32*)(&__IPSBAR[0x1F0004])) -#define MCF_RNG_RNGER (*(vuint32*)(&__IPSBAR[0x1F0008])) -#define MCF_RNG_RNGOUT (*(vuint32*)(&__IPSBAR[0x1F000C])) - -/* Bit definitions and macros for MCF_RNG_RNGCR */ -#define MCF_RNG_RNGCR_GO (0x00000001) -#define MCF_RNG_RNGCR_HA (0x00000002) -#define MCF_RNG_RNGCR_IM (0x00000004) -#define MCF_RNG_RNGCR_CI (0x00000008) - -/* Bit definitions and macros for MCF_RNG_RNGSR */ -#define MCF_RNG_RNGSR_SV (0x00000001) -#define MCF_RNG_RNGSR_LRS (0x00000002) -#define MCF_RNG_RNGSR_FUF (0x00000004) -#define MCF_RNG_RNGSR_EI (0x00000008) -#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) -#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) - -/* Bit definitions and macros for MCF_RNG_RNGER */ -#define MCF_RNG_RNGER_ENTROPY(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_RNG_RNGOUT */ -#define MCF_RNG_RNGOUT_OUTPUT(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* -* -* Real-time Clock (RTC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RTC_HOURMIN (*(vuint32*)(&__IPSBAR[0x0003C0])) -#define MCF_RTC_SECONDS (*(vuint32*)(&__IPSBAR[0x0003C4])) -#define MCF_RTC_ALRM_HM (*(vuint32*)(&__IPSBAR[0x0003C8])) -#define MCF_RTC_ALRM_SEC (*(vuint32*)(&__IPSBAR[0x0003CC])) -#define MCF_RTC_CR (*(vuint32*)(&__IPSBAR[0x0003D0])) -#define MCF_RTC_ISR (*(vuint32*)(&__IPSBAR[0x0003D4])) -#define MCF_RTC_IER (*(vuint32*)(&__IPSBAR[0x0003D8])) -#define MCF_RTC_STPWCH (*(vuint32*)(&__IPSBAR[0x0003DC])) -#define MCF_RTC_DAYS (*(vuint32*)(&__IPSBAR[0x0003E0])) -#define MCF_RTC_ALRM_DAY (*(vuint32*)(&__IPSBAR[0x0003E4])) - -/* Bit definitions and macros for MCF_RTC_HOURMIN */ -#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F)<<0) -#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8) - -/* Bit definitions and macros for MCF_RTC_SECONDS */ -#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x0000003F)<<0) - -/* Bit definitions and macros for MCF_RTC_ALRM_HM */ -#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F)<<0) -#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8) - -/* Bit definitions and macros for MCF_RTC_ALRM_SEC */ -#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F)<<0) - -/* Bit definitions and macros for MCF_RTC_CR */ -#define MCF_RTC_CR_SWR (0x00000001) -#define MCF_RTC_CR_XTL(x) (((x)&0x00000003)<<5) -#define MCF_RTC_CR_EN (0x00000080) -#define MCF_RTC_CR_32768 (0x0) -#define MCF_RTC_CR_32000 (0x1) -#define MCF_RTC_CR_38400 (0x2) - -/* Bit definitions and macros for MCF_RTC_ISR */ -#define MCF_RTC_ISR_SW (0x00000001) -#define MCF_RTC_ISR_MIN (0x00000002) -#define MCF_RTC_ISR_ALM (0x00000004) -#define MCF_RTC_ISR_DAY (0x00000008) -#define MCF_RTC_ISR_1HZ (0x00000010) -#define MCF_RTC_ISR_HR (0x00000020) -#define MCF_RTC_ISR_2HZ (0x00000080) -#define MCF_RTC_ISR_SAM0 (0x00000100) -#define MCF_RTC_ISR_SAM1 (0x00000200) -#define MCF_RTC_ISR_SAM2 (0x00000400) -#define MCF_RTC_ISR_SAM3 (0x00000800) -#define MCF_RTC_ISR_SAM4 (0x00001000) -#define MCF_RTC_ISR_SAM5 (0x00002000) -#define MCF_RTC_ISR_SAM6 (0x00004000) -#define MCF_RTC_ISR_SAM7 (0x00008000) - -/* Bit definitions and macros for MCF_RTC_IER */ -#define MCF_RTC_IER_SW (0x00000001) -#define MCF_RTC_IER_MIN (0x00000002) -#define MCF_RTC_IER_ALM (0x00000004) -#define MCF_RTC_IER_DAY (0x00000008) -#define MCF_RTC_IER_1HZ (0x00000010) -#define MCF_RTC_IER_HR (0x00000020) -#define MCF_RTC_IER_2HZ (0x00000080) -#define MCF_RTC_IER_SAM0 (0x00000100) -#define MCF_RTC_IER_SAM1 (0x00000200) -#define MCF_RTC_IER_SAM2 (0x00000400) -#define MCF_RTC_IER_SAM3 (0x00000800) -#define MCF_RTC_IER_SAM4 (0x00001000) -#define MCF_RTC_IER_SAM5 (0x00002000) -#define MCF_RTC_IER_SAM6 (0x00004000) -#define MCF_RTC_IER_SAM7 (0x00008000) - -/* Bit definitions and macros for MCF_RTC_STPWCH */ -#define MCF_RTC_STPWCH_CNT(x) (((x)&0x0000003F)<<0) - -/* Bit definitions and macros for MCF_RTC_DAYS */ -#define MCF_RTC_DAYS_DAYS(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_RTC_ALRM_DAY */ -#define MCF_RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF)<<0) - -/********************************************************************/ - -#endif /* __MCF5223x_H__ */ diff --git a/c/src/lib/libcpu/m68k/mcf5225x/include/fec.h b/c/src/lib/libcpu/m68k/mcf5225x/include/fec.h deleted file mode 100644 index 8d8d6c3763..0000000000 --- a/c/src/lib/libcpu/m68k/mcf5225x/include/fec.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef FEC_H -#define FEC_H - -#include <arch/sys_arch.h> -#include <lwip/netif.h> -#include <stdbool.h> - -struct if_config { - u8_t flags; - u8_t hwaddr_len; - u16_t mtu; - u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; - sys_thread_t net_task; - void(*phy_init)(void); - u8_t name[2]; -}; - -extern err_t mcf5225xif_init(struct netif *); -extern void handle_rx_frame(struct netif*); - -extern void smi_init(u32_t); -extern void smi_write(u8_t,u8_t,u16_t); -extern u16_t smi_read(u8_t,u8_t); - -#define MAX_FRAME_LEN 1518 -#define MTU_SIZE (MAX_FRAME_LEN-18) -#define MSCR_MII_SPEED(clk) ((clk/5000000+1)<<1) -#define PHY_ADDR 1 -#define PHY_REG_ID1 2 -#define PHY_REG_ID2 3 - -#endif /* FEC_H */ diff --git a/c/src/lib/libcpu/m68k/mcf5225x/include/mcf5225x.h b/c/src/lib/libcpu/m68k/mcf5225x/include/mcf5225x.h deleted file mode 100644 index ded447ffac..0000000000 --- a/c/src/lib/libcpu/m68k/mcf5225x/include/mcf5225x.h +++ /dev/null @@ -1,3552 +0,0 @@ -/* - * File: mcf5225x.h - * Purpose: Register and bit definitions - */ - -#ifndef __MCF5225x_H__ -#define __MCF5225x_H__ - -typedef volatile unsigned char vuint8; -typedef volatile unsigned short vuint16; -typedef volatile unsigned long vuint32; - -/********************************************************************* -* -* System Control Module (SCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x000000])) -#define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x000008])) -#define MCF_SCM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) -#define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x000010])) -#define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x000011])) -#define MCF_SCM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) -#define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x000013])) -#define MCF_SCM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) -#define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x00001C])) -#define MCF_SCM_MPR (*(vuint32*)(&__IPSBAR[0x000020])) -#define MCF_SCM_PPMRS (*(vuint8 *)(&__IPSBAR[0x000021])) -#define MCF_SCM_PPMRC (*(vuint8 *)(&__IPSBAR[0x000022])) -#define MCF_SCM_IPSBMT (*(vuint8 *)(&__IPSBAR[0x000023])) -#define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x000024])) -#define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x000025])) -#define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x000026])) -#define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x000027])) -#define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x000028])) -#define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x000029])) -#define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x00002A])) -#define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x00002B])) -#define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x00002C])) -#define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x000030])) -#define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x000031])) - -/* Bit definitions and macros for MCF_SCM_IPSBAR */ -#define MCF_SCM_IPSBAR_V (0x00000001) -#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000) - -/* Bit definitions and macros for MCF_SCM_RAMBAR */ -#define MCF_SCM_RAMBAR_BDE (0x00000200) -#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000) - -/* Bit definitions and macros for MCF_SCM_CRSR */ -#define MCF_SCM_CRSR_CWDR (0x20) -#define MCF_SCM_CRSR_EXT (0x80) - -/* Bit definitions and macros for MCF_SCM_CWCR */ -#define MCF_SCM_CWCR_CWTIC (0x01) -#define MCF_SCM_CWCR_CWTAVAL (0x02) -#define MCF_SCM_CWCR_CWTA (0x04) -#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3) -#define MCF_SCM_CWCR_CWRI (0x40) -#define MCF_SCM_CWCR_CWE (0x80) - -/* Bit definitions and macros for MCF_SCM_LPICR */ -#define MCF_SCM_LPICR_XIPL(x) (((x)&0x07)<<4) -#define MCF_SCM_LPICR_ENBSTOP (0x80) - -/* Bit definitions and macros for MCF_SCM_CWSR */ -#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_SCM_PPMRH */ -#define MCF_SCM_PPMRH_CDPORTS (0x00000001) -#define MCF_SCM_PPMRH_CDEPORT (0x00000002) -#define MCF_SCM_PPMRH_CDPIT0 (0x00000008) -#define MCF_SCM_PPMRH_CDPIT1 (0x00000010) -#define MCF_SCM_PPMRH_CDCAN (0x00000020) -#define MCF_SCM_PPMRH_CDADC (0x00000080) -#define MCF_SCM_PPMRH_CDGPT (0x00000100) -#define MCF_SCM_PPMRH_CDPWN (0x00000200) -#define MCF_SCM_PPMRH_CDFCAN (0x00000400) -#define MCF_SCM_PPMRH_CDCFM (0x00000800) - -/* Bit definitions and macros for MCF_SCM_PPMRL */ -#define MCF_SCM_PPMRL_CDG (0x00000002) -#define MCF_SCM_PPMRL_CDEIM (0x00000008) -#define MCF_SCM_PPMRL_CDDMA (0x00000010) -#define MCF_SCM_PPMRL_CDUART0 (0x00000020) -#define MCF_SCM_PPMRL_CDUART1 (0x00000040) -#define MCF_SCM_PPMRL_CDUART2 (0x00000080) -#define MCF_SCM_PPMRL_CDI2C0 (0x00000200) -#define MCF_SCM_PPMRL_CDI2C1 (0x00000800) -#define MCF_SCM_PPMRL_CDQSPI (0x00000400) -#define MCF_SCM_PPMRL_CDDTIM0 (0x00002000) -#define MCF_SCM_PPMRL_CDDTIM1 (0x00004000) -#define MCF_SCM_PPMRL_CDDTIM2 (0x00008000) -#define MCF_SCM_PPMRL_CDDTIM3 (0x00010000) -#define MCF_SCM_PPMRL_CDINTC0 (0x00020000) -#define MCF_SCM_PPMRL_CDINTC1 (0x00040000) -#define MCF_SCM_PPMRL_CDFEC (0x00200000) - -/* Bit definitions and macros for MCF_SCM_MPARK */ -#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_MPARK_PRKLAST (0x00001000) -#define MCF_SCM_MPARK_TIMEOUT (0x00002000) -#define MCF_SCM_MPARK_FIXED (0x00004000) -#define MCF_SCM_MPARK_M0PRTY(x) (((x)&0x00000003)<<18) -#define MCF_SCM_MPARK_M2PRTY(x) (((x)&0x00000003)<<20) -#define MCF_SCM_MPARK_M3PRTY(x) (((x)&0x00000003)<<22) -#define MCF_SCM_MPARK_BCR24BIT (0x01000000) -#define MCF_SCM_MPARK_M2_P_EN (0x02000000) - -/* Bit definitions and macros for MCF_SCM_PPMRS */ -#define MCF_SCM_PPMRS_DISABLE_ALL (64) -#define MCF_SCM_PPMRS_DISABLE_CFM (43) -#define MCF_SCM_PPMRS_DISABLE_CAN (42) -#define MCF_SCM_PPMRS_DISABLE_PWM (41) -#define MCF_SCM_PPMRS_DISABLE_GPT (40) -#define MCF_SCM_PPMRS_DISABLE_ADC (39) -#define MCF_SCM_PPMRS_DISABLE_PIT1 (36) -#define MCF_SCM_PPMRS_DISABLE_PIT0 (35) -#define MCF_SCM_PPMRS_DISABLE_EPORT (33) -#define MCF_SCM_PPMRS_DISABLE_PORTS (32) -#define MCF_SCM_PPMRS_DISABLE_INTC (17) -#define MCF_SCM_PPMRS_DISABLE_DTIM3 (16) -#define MCF_SCM_PPMRS_DISABLE_DTIM2 (15) -#define MCF_SCM_PPMRS_DISABLE_DTIM1 (14) -#define MCF_SCM_PPMRS_DISABLE_DTIM0 (13) -#define MCF_SCM_PPMRS_DISABLE_QSPI (10) -#define MCF_SCM_PPMRS_DISABLE_I2C (9) -#define MCF_SCM_PPMRS_DISABLE_UART2 (7) -#define MCF_SCM_PPMRS_DISABLE_UART1 (6) -#define MCF_SCM_PPMRS_DISABLE_UART0 (5) -#define MCF_SCM_PPMRS_DISABLE_DMA (4) -#define MCF_SCM_PPMRS_SET_CDG (1) - -/* Bit definitions and macros for MCF_SCM_PPMRC */ -#define MCF_SCM_PPMRC_ENABLE_ALL (64) -#define MCF_SCM_PPMRC_ENABLE_CFM (43) -#define MCF_SCM_PPMRC_ENABLE_CAN (42) -#define MCF_SCM_PPMRC_ENABLE_PWM (41) -#define MCF_SCM_PPMRC_ENABLE_GPT (40) -#define MCF_SCM_PPMRC_ENABLE_ADC (39) -#define MCF_SCM_PPMRC_ENABLE_PIT1 (36) -#define MCF_SCM_PPMRC_ENABLE_PIT0 (35) -#define MCF_SCM_PPMRC_ENABLE_EPORT (33) -#define MCF_SCM_PPMRC_ENABLE_PORTS (32) -#define MCF_SCM_PPMRC_ENABLE_INTC (17) -#define MCF_SCM_PPMRC_ENABLE_DTIM3 (16) -#define MCF_SCM_PPMRC_ENABLE_DTIM2 (15) -#define MCF_SCM_PPMRC_ENABLE_DTIM1 (14) -#define MCF_SCM_PPMRC_ENABLE_DTIM0 (13) -#define MCF_SCM_PPMRC_ENABLE_QSPI (10) -#define MCF_SCM_PPMRC_ENABLE_I2C (9) -#define MCF_SCM_PPMRC_ENABLE_UART2 (7) -#define MCF_SCM_PPMRC_ENABLE_UART1 (6) -#define MCF_SCM_PPMRC_ENABLE_UART0 (5) -#define MCF_SCM_PPMRC_ENABLE_DMA (4) -#define MCF_SCM_PPMRC_CLEAR_CDG (1) - - -/********************************************************************* -* -* Power Management Module (PMM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PMM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) -#define MCF_PMM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) -#define MCF_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) -#define MCF_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) - -/* Bit definitions and macros for MCF_PMM_PPMRH */ -#define MCF_PMM_PPMRH_CDPORTS (0x00000001) -#define MCF_PMM_PPMRH_CDEPORT (0x00000002) -#define MCF_PMM_PPMRH_CDPIT0 (0x00000008) -#define MCF_PMM_PPMRH_CDPIT1 (0x00000010) -#define MCF_PMM_PPMRH_CDADC (0x00000080) -#define MCF_PMM_PPMRH_CDGPT (0x00000100) -#define MCF_PMM_PPMRH_CDPWM (0x00000200) -#define MCF_PMM_PPMRH_CDFCAN (0x00000400) -#define MCF_PMM_PPMRH_CDCFM (0x00000800) - -/* Bit definitions and macros for MCF_PMM_PPMRL */ -#define MCF_PMM_PPMRL_CDG (0x00000002) -#define MCF_PMM_PPMRL_CDEIM (0x00000008) -#define MCF_PMM_PPMRL_CDDMA (0x00000010) -#define MCF_PMM_PPMRL_CDUART0 (0x00000020) -#define MCF_PMM_PPMRL_CDUART1 (0x00000040) -#define MCF_PMM_PPMRL_CDUART2 (0x00000080) -#define MCF_PMM_PPMRL_CDI2C (0x00000200) -#define MCF_PMM_PPMRL_CDQSPI (0x00000400) -#define MCF_PMM_PPMRL_CDDTIM0 (0x00002000) -#define MCF_PMM_PPMRL_CDDTIM1 (0x00004000) -#define MCF_PMM_PPMRL_CDDTIM2 (0x00008000) -#define MCF_PMM_PPMRL_CDDTIM3 (0x00010000) -#define MCF_PMM_PPMRL_CDINTC0 (0x00020000) - -/* Bit definitions and macros for MCF_PMM_LPICR */ -#define MCF_PMM_LPICR_XIPL(x) (((x)&0x07)<<4) -#define MCF_PMM_LPICR_ENBSTOP (0x80) - -/* Bit definitions and macros for MCF_PMM_LPCR */ -#define MCF_PMM_LPCR_LVDSE (0x02) -#define MCF_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF_PMM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF_PMM_LPCR_LPMD_STOP (0xC0) -#define MCF_PMM_LPCR_LPMD_WAIT (0x80) -#define MCF_PMM_LPCR_LPMD_DOZE (0x40) -#define MCF_PMM_LPCR_LPMD_RUN (0x00) - - -/********************************************************************* -* -* DMA Controller Module (DMA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_DMA_DMAREQC (*(vuint32*)(&__IPSBAR[0x000014])) -#define MCF_DMA_SAR0 (*(vuint32*)(&__IPSBAR[0x000100])) -#define MCF_DMA_SAR1 (*(vuint32*)(&__IPSBAR[0x000110])) -#define MCF_DMA_SAR2 (*(vuint32*)(&__IPSBAR[0x000120])) -#define MCF_DMA_SAR3 (*(vuint32*)(&__IPSBAR[0x000130])) -#define MCF_DMA_SAR(x) (*(vuint32*)(&__IPSBAR[0x000100+((x)*0x010)])) -#define MCF_DMA_DAR0 (*(vuint32*)(&__IPSBAR[0x000104])) -#define MCF_DMA_DAR1 (*(vuint32*)(&__IPSBAR[0x000114])) -#define MCF_DMA_DAR2 (*(vuint32*)(&__IPSBAR[0x000124])) -#define MCF_DMA_DAR3 (*(vuint32*)(&__IPSBAR[0x000134])) -#define MCF_DMA_DAR(x) (*(vuint32*)(&__IPSBAR[0x000104+((x)*0x010)])) -#define MCF_DMA_DSR0 (*(vuint8 *)(&__IPSBAR[0x000108])) -#define MCF_DMA_DSR1 (*(vuint8 *)(&__IPSBAR[0x000118])) -#define MCF_DMA_DSR2 (*(vuint8 *)(&__IPSBAR[0x000128])) -#define MCF_DMA_DSR3 (*(vuint8 *)(&__IPSBAR[0x000138])) -#define MCF_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x000108+((x)*0x010)])) -#define MCF_DMA_BCR0 (*(vuint32*)(&__IPSBAR[0x000108])) -#define MCF_DMA_BCR1 (*(vuint32*)(&__IPSBAR[0x000118])) -#define MCF_DMA_BCR2 (*(vuint32*)(&__IPSBAR[0x000128])) -#define MCF_DMA_BCR3 (*(vuint32*)(&__IPSBAR[0x000138])) -#define MCF_DMA_BCR(x) (*(vuint32*)(&__IPSBAR[0x000108+((x)*0x010)])) -#define MCF_DMA_DCR0 (*(vuint32*)(&__IPSBAR[0x00010C])) -#define MCF_DMA_DCR1 (*(vuint32*)(&__IPSBAR[0x00011C])) -#define MCF_DMA_DCR2 (*(vuint32*)(&__IPSBAR[0x00012C])) -#define MCF_DMA_DCR3 (*(vuint32*)(&__IPSBAR[0x00013C])) -#define MCF_DMA_DCR(x) (*(vuint32*)(&__IPSBAR[0x00010C+((x)*0x010)])) - -/* Bit definitions and macros for MCF_DMA_DMAREQC */ -#define MCF_DMA_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) -#define MCF_DMA_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) -#define MCF_DMA_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) -#define MCF_DMA_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) -#define MCF_DMA_DMAREQC_DMAREQC_EXT(x) (((x)&0x0000000F)<<16) - -/* Bit definitions and macros for MCF_DMA_SAR */ -#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DMA_DAR */ -#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DMA_DSR */ -#define MCF_DMA_DSR_DONE (0x01) -#define MCF_DMA_DSR_BSY (0x02) -#define MCF_DMA_DSR_REQ (0x04) -#define MCF_DMA_DSR_BED (0x10) -#define MCF_DMA_DSR_BES (0x20) -#define MCF_DMA_DSR_CE (0x40) - -/* Bit definitions and macros for MCF_DMA_BCR */ -#define MCF_DMA_BCR_BCR(x) (((x)&0x00FFFFFF)<<0) -#define MCF_DMA_BCR_DSR(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_DMA_DCR */ -#define MCF_DMA_DCR_LCH2(x) (((x)&0x00000003)<<0) -#define MCF_DMA_DCR_LCH1(x) (((x)&0x00000003)<<2) -#define MCF_DMA_DCR_LINKCC(x) (((x)&0x00000003)<<4) -#define MCF_DMA_DCR_D_REQ (0x00000080) -#define MCF_DMA_DCR_DMOD(x) (((x)&0x0000000F)<<8) -#define MCF_DMA_DCR_SMOD(x) (((x)&0x0000000F)<<12) -#define MCF_DMA_DCR_START (0x00010000) -#define MCF_DMA_DCR_DSIZE(x) (((x)&0x00000003)<<17) -#define MCF_DMA_DCR_DINC (0x00080000) -#define MCF_DMA_DCR_SSIZE(x) (((x)&0x00000003)<<20) -#define MCF_DMA_DCR_SINC (0x00400000) -#define MCF_DMA_DCR_BWC(x) (((x)&0x00000007)<<25) -#define MCF_DMA_DCR_AA (0x10000000) -#define MCF_DMA_DCR_CS (0x20000000) -#define MCF_DMA_DCR_EEXT (0x40000000) -#define MCF_DMA_DCR_INT (0x80000000) -#define MCF_DMA_DCR_BWC_16K (0x1) -#define MCF_DMA_DCR_BWC_32K (0x2) -#define MCF_DMA_DCR_BWC_64K (0x3) -#define MCF_DMA_DCR_BWC_128K (0x4) -#define MCF_DMA_DCR_BWC_256K (0x5) -#define MCF_DMA_DCR_BWC_512K (0x6) -#define MCF_DMA_DCR_BWC_1024K (0x7) -#define MCF_DMA_DCR_DMOD_DIS (0x0) -#define MCF_DMA_DCR_DMOD_16 (0x1) -#define MCF_DMA_DCR_DMOD_32 (0x2) -#define MCF_DMA_DCR_DMOD_64 (0x3) -#define MCF_DMA_DCR_DMOD_128 (0x4) -#define MCF_DMA_DCR_DMOD_256 (0x5) -#define MCF_DMA_DCR_DMOD_512 (0x6) -#define MCF_DMA_DCR_DMOD_1K (0x7) -#define MCF_DMA_DCR_DMOD_2K (0x8) -#define MCF_DMA_DCR_DMOD_4K (0x9) -#define MCF_DMA_DCR_DMOD_8K (0xA) -#define MCF_DMA_DCR_DMOD_16K (0xB) -#define MCF_DMA_DCR_DMOD_32K (0xC) -#define MCF_DMA_DCR_DMOD_64K (0xD) -#define MCF_DMA_DCR_DMOD_128K (0xE) -#define MCF_DMA_DCR_DMOD_256K (0xF) -#define MCF_DMA_DCR_SMOD_DIS (0x0) -#define MCF_DMA_DCR_SMOD_16 (0x1) -#define MCF_DMA_DCR_SMOD_32 (0x2) -#define MCF_DMA_DCR_SMOD_64 (0x3) -#define MCF_DMA_DCR_SMOD_128 (0x4) -#define MCF_DMA_DCR_SMOD_256 (0x5) -#define MCF_DMA_DCR_SMOD_512 (0x6) -#define MCF_DMA_DCR_SMOD_1K (0x7) -#define MCF_DMA_DCR_SMOD_2K (0x8) -#define MCF_DMA_DCR_SMOD_4K (0x9) -#define MCF_DMA_DCR_SMOD_8K (0xA) -#define MCF_DMA_DCR_SMOD_16K (0xB) -#define MCF_DMA_DCR_SMOD_32K (0xC) -#define MCF_DMA_DCR_SMOD_64K (0xD) -#define MCF_DMA_DCR_SMOD_128K (0xE) -#define MCF_DMA_DCR_SMOD_256K (0xF) -#define MCF_DMA_DCR_SSIZE_LONG (0x0) -#define MCF_DMA_DCR_SSIZE_BYTE (0x1) -#define MCF_DMA_DCR_SSIZE_WORD (0x2) -#define MCF_DMA_DCR_SSIZE_LINE (0x3) -#define MCF_DMA_DCR_DSIZE_LONG (0x0) -#define MCF_DMA_DCR_DSIZE_BYTE (0x1) -#define MCF_DMA_DCR_DSIZE_WORD (0x2) -#define MCF_DMA_DCR_DSIZE_LINE (0x3) -#define MCF_DMA_DCR_LCH1_CH0 (0x0) -#define MCF_DMA_DCR_LCH1_CH1 (0x1) -#define MCF_DMA_DCR_LCH1_CH2 (0x2) -#define MCF_DMA_DCR_LCH1_CH3 (0x3) -#define MCF_DMA_DCR_LCH2_CH0 (0x0) -#define MCF_DMA_DCR_LCH2_CH1 (0x1) -#define MCF_DMA_DCR_LCH2_CH2 (0x2) -#define MCF_DMA_DCR_LCH2_CH3 (0x3) - - -/********************************************************************* -* -* Universal Asynchronous Receiver Transmitter (UART) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_UART0_UMR (*(vuint8 *)(&__IPSBAR[0x000200])) -#define MCF_UART0_USR (*(vuint8 *)(&__IPSBAR[0x000204])) -#define MCF_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x000204])) -#define MCF_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x000208])) -#define MCF_UART0_URB (*(vuint8 *)(&__IPSBAR[0x00020C])) -#define MCF_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x00020C])) -#define MCF_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x000210])) -#define MCF_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x000210])) -#define MCF_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x000214])) -#define MCF_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x000214])) -#define MCF_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x000218])) -#define MCF_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x00021C])) -#define MCF_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x000234])) -#define MCF_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x000238])) -#define MCF_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x00023C])) -#define MCF_UART1_UMR (*(vuint8 *)(&__IPSBAR[0x000240])) -#define MCF_UART1_USR (*(vuint8 *)(&__IPSBAR[0x000244])) -#define MCF_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x000244])) -#define MCF_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x000248])) -#define MCF_UART1_URB (*(vuint8 *)(&__IPSBAR[0x00024C])) -#define MCF_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x00024C])) -#define MCF_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x000250])) -#define MCF_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x000250])) -#define MCF_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x000254])) -#define MCF_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x000254])) -#define MCF_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x000258])) -#define MCF_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x00025C])) -#define MCF_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x000274])) -#define MCF_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x000278])) -#define MCF_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x00027C])) -#define MCF_UART2_UMR (*(vuint8 *)(&__IPSBAR[0x000280])) -#define MCF_UART2_USR (*(vuint8 *)(&__IPSBAR[0x000284])) -#define MCF_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x000284])) -#define MCF_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x000288])) -#define MCF_UART2_URB (*(vuint8 *)(&__IPSBAR[0x00028C])) -#define MCF_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x00028C])) -#define MCF_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x000290])) -#define MCF_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x000290])) -#define MCF_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x000294])) -#define MCF_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x000294])) -#define MCF_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x000298])) -#define MCF_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x00029C])) -#define MCF_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x0002B4])) -#define MCF_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x0002B8])) -#define MCF_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x0002BC])) -#define MCF_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x000200+((x)*0x040)])) -#define MCF_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x000208+((x)*0x040)])) -#define MCF_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x000218+((x)*0x040)])) -#define MCF_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x00021C+((x)*0x040)])) -#define MCF_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x000234+((x)*0x040)])) -#define MCF_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x000238+((x)*0x040)])) -#define MCF_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x00023C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_UART_UMR */ -#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) -#define MCF_UART_UMR_PT (0x04) -#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) -#define MCF_UART_UMR_ERR (0x20) -#define MCF_UART_UMR_RXIRQ (0x40) -#define MCF_UART_UMR_RXRTS (0x80) -#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) -#define MCF_UART_UMR_TXCTS (0x10) -#define MCF_UART_UMR_TXRTS (0x20) -#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) -#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) -#define MCF_UART_UMR_PM_MULTI_DATA (0x18) -#define MCF_UART_UMR_PM_NONE (0x10) -#define MCF_UART_UMR_PM_FORCE_HI (0x0C) -#define MCF_UART_UMR_PM_FORCE_LO (0x08) -#define MCF_UART_UMR_PM_ODD (0x04) -#define MCF_UART_UMR_PM_EVEN (0x00) -#define MCF_UART_UMR_BC_5 (0x00) -#define MCF_UART_UMR_BC_6 (0x01) -#define MCF_UART_UMR_BC_7 (0x02) -#define MCF_UART_UMR_BC_8 (0x03) -#define MCF_UART_UMR_CM_NORMAL (0x00) -#define MCF_UART_UMR_CM_ECHO (0x40) -#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) -#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) -#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) -#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) -#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF_UART_USR */ -#define MCF_UART_USR_RXRDY (0x01) -#define MCF_UART_USR_FFULL (0x02) -#define MCF_UART_USR_TXRDY (0x04) -#define MCF_UART_USR_TXEMP (0x08) -#define MCF_UART_USR_OE (0x10) -#define MCF_UART_USR_PE (0x20) -#define MCF_UART_USR_FE (0x40) -#define MCF_UART_USR_RB (0x80) - -/* Bit definitions and macros for MCF_UART_UCSR */ -#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) -#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) -#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) -#define MCF_UART_UCSR_RCS_CTM16 (0xE0) -#define MCF_UART_UCSR_RCS_CTM (0xF0) -#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) -#define MCF_UART_UCSR_TCS_CTM16 (0x0E) -#define MCF_UART_UCSR_TCS_CTM (0x0F) - -/* Bit definitions and macros for MCF_UART_UCR */ -#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) -#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) -#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) -#define MCF_UART_UCR_NONE (0x00) -#define MCF_UART_UCR_STOP_BREAK (0x70) -#define MCF_UART_UCR_START_BREAK (0x60) -#define MCF_UART_UCR_BKCHGINT (0x50) -#define MCF_UART_UCR_RESET_ERROR (0x40) -#define MCF_UART_UCR_RESET_TX (0x30) -#define MCF_UART_UCR_RESET_RX (0x20) -#define MCF_UART_UCR_RESET_MR (0x10) -#define MCF_UART_UCR_TX_DISABLED (0x08) -#define MCF_UART_UCR_TX_ENABLED (0x04) -#define MCF_UART_UCR_RX_DISABLED (0x02) -#define MCF_UART_UCR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF_UART_UIPCR */ -#define MCF_UART_UIPCR_CTS (0x01) -#define MCF_UART_UIPCR_COS (0x10) - -/* Bit definitions and macros for MCF_UART_UACR */ -#define MCF_UART_UACR_IEC (0x01) - -/* Bit definitions and macros for MCF_UART_UISR */ -#define MCF_UART_UISR_TXRDY (0x01) -#define MCF_UART_UISR_RXRDY_FU (0x02) -#define MCF_UART_UISR_DB (0x04) -#define MCF_UART_UISR_RXFTO (0x08) -#define MCF_UART_UISR_TXFIFO (0x10) -#define MCF_UART_UISR_RXFIFO (0x20) -#define MCF_UART_UISR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIMR */ -#define MCF_UART_UIMR_TXRDY (0x01) -#define MCF_UART_UIMR_RXRDY_FU (0x02) -#define MCF_UART_UIMR_DB (0x04) -#define MCF_UART_UIMR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIP */ -#define MCF_UART_UIP_CTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP1 */ -#define MCF_UART_UOP1_RTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP0 */ -#define MCF_UART_UOP0_RTS (0x01) - -/********************************************************************* -* -* I2C Module (I2C) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_I2C_I2AR (*(vuint8 *)(&__IPSBAR[0x000300])) -#define MCF_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x000304])) -#define MCF_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x000308])) -#define MCF_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x00030C])) -#define MCF_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x000310])) - -/* Bit definitions and macros for MCF_I2C_I2AR */ -#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_I2C_I2FDR */ -#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) - -/* Bit definitions and macros for MCF_I2C_I2CR */ -#define MCF_I2C_I2CR_RSTA (0x04) -#define MCF_I2C_I2CR_TXAK (0x08) -#define MCF_I2C_I2CR_MTX (0x10) -#define MCF_I2C_I2CR_MSTA (0x20) -#define MCF_I2C_I2CR_IIEN (0x40) -#define MCF_I2C_I2CR_IEN (0x80) - -/* Bit definitions and macros for MCF_I2C_I2SR */ -#define MCF_I2C_I2SR_RXAK (0x01) -#define MCF_I2C_I2SR_IIF (0x02) -#define MCF_I2C_I2SR_SRW (0x04) -#define MCF_I2C_I2SR_IAL (0x10) -#define MCF_I2C_I2SR_IBB (0x20) -#define MCF_I2C_I2SR_IAAS (0x40) -#define MCF_I2C_I2SR_ICF (0x80) - -/* Bit definitions and macros for MCF_I2C_I2DR */ -#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_I2C_I2ICR */ -#define MCF_I2C_I2ICR_IE (0x01) -#define MCF_I2C_I2ICR_RE (0x02) -#define MCF_I2C_I2ICR_TE (0x04) -#define MCF_I2C_I2ICR_BNBE (0x08) - -/********************************************************************* -* -* Queued Serial Peripheral Interface (QSPI) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_QSPI_QMR (*(vuint16*)(&__IPSBAR[0x000340])) -#define MCF_QSPI_QDLYR (*(vuint16*)(&__IPSBAR[0x000344])) -#define MCF_QSPI_QWR (*(vuint16*)(&__IPSBAR[0x000348])) -#define MCF_QSPI_QIR (*(vuint16*)(&__IPSBAR[0x00034C])) -#define MCF_QSPI_QAR (*(vuint16*)(&__IPSBAR[0x000350])) -#define MCF_QSPI_QDR (*(vuint16*)(&__IPSBAR[0x000354])) - -/* Bit definitions and macros for MCF_QSPI_QMR */ -#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QMR_CPHA (0x0100) -#define MCF_QSPI_QMR_CPOL (0x0200) -#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) -#define MCF_QSPI_QMR_DOHIE (0x4000) -#define MCF_QSPI_QMR_MSTR (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QDLYR */ -#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define MCF_QSPI_QDLYR_SPE (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QWR */ -#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) -#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define MCF_QSPI_QWR_CSIV (0x1000) -#define MCF_QSPI_QWR_WRTO (0x2000) -#define MCF_QSPI_QWR_WREN (0x4000) -#define MCF_QSPI_QWR_HALT (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QIR */ -#define MCF_QSPI_QIR_SPIF (0x0001) -#define MCF_QSPI_QIR_ABRT (0x0004) -#define MCF_QSPI_QIR_WCEF (0x0008) -#define MCF_QSPI_QIR_SPIFE (0x0100) -#define MCF_QSPI_QIR_ABRTE (0x0400) -#define MCF_QSPI_QIR_WCEFE (0x0800) -#define MCF_QSPI_QIR_ABRTL (0x1000) -#define MCF_QSPI_QIR_ABRTB (0x4000) -#define MCF_QSPI_QIR_WCEFB (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QAR */ -#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) - -/* Bit definitions and macros for MCF_QSPI_QDR */ -#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0) - -/********************************************************************* -* -* DMA Timers (DTIM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_DTIM0_DTMR (*(vuint16*)(&__IPSBAR[0x000400])) -#define MCF_DTIM0_DTXMR (*(vuint8 *)(&__IPSBAR[0x000402])) -#define MCF_DTIM0_DTER (*(vuint8 *)(&__IPSBAR[0x000403])) -#define MCF_DTIM0_DTRR (*(vuint32*)(&__IPSBAR[0x000404])) -#define MCF_DTIM0_DTCR (*(vuint32*)(&__IPSBAR[0x000408])) -#define MCF_DTIM0_DTCN (*(vuint32*)(&__IPSBAR[0x00040C])) -#define MCF_DTIM1_DTMR (*(vuint16*)(&__IPSBAR[0x000440])) -#define MCF_DTIM1_DTXMR (*(vuint8 *)(&__IPSBAR[0x000442])) -#define MCF_DTIM1_DTER (*(vuint8 *)(&__IPSBAR[0x000443])) -#define MCF_DTIM1_DTRR (*(vuint32*)(&__IPSBAR[0x000444])) -#define MCF_DTIM1_DTCR (*(vuint32*)(&__IPSBAR[0x000448])) -#define MCF_DTIM1_DTCN (*(vuint32*)(&__IPSBAR[0x00044C])) -#define MCF_DTIM2_DTMR (*(vuint16*)(&__IPSBAR[0x000480])) -#define MCF_DTIM2_DTXMR (*(vuint8 *)(&__IPSBAR[0x000482])) -#define MCF_DTIM2_DTER (*(vuint8 *)(&__IPSBAR[0x000483])) -#define MCF_DTIM2_DTRR (*(vuint32*)(&__IPSBAR[0x000484])) -#define MCF_DTIM2_DTCR (*(vuint32*)(&__IPSBAR[0x000488])) -#define MCF_DTIM2_DTCN (*(vuint32*)(&__IPSBAR[0x00048C])) -#define MCF_DTIM3_DTMR (*(vuint16*)(&__IPSBAR[0x0004C0])) -#define MCF_DTIM3_DTXMR (*(vuint8 *)(&__IPSBAR[0x0004C2])) -#define MCF_DTIM3_DTER (*(vuint8 *)(&__IPSBAR[0x0004C3])) -#define MCF_DTIM3_DTRR (*(vuint32*)(&__IPSBAR[0x0004C4])) -#define MCF_DTIM3_DTCR (*(vuint32*)(&__IPSBAR[0x0004C8])) -#define MCF_DTIM3_DTCN (*(vuint32*)(&__IPSBAR[0x0004CC])) -#define MCF_DTIM_DTMR(x) (*(vuint16*)(&__IPSBAR[0x000400+((x)*0x040)])) -#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x000402+((x)*0x040)])) -#define MCF_DTIM_DTER(x) (*(vuint8 *)(&__IPSBAR[0x000403+((x)*0x040)])) -#define MCF_DTIM_DTRR(x) (*(vuint32*)(&__IPSBAR[0x000404+((x)*0x040)])) -#define MCF_DTIM_DTCR(x) (*(vuint32*)(&__IPSBAR[0x000408+((x)*0x040)])) -#define MCF_DTIM_DTCN(x) (*(vuint32*)(&__IPSBAR[0x00040C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_DTIM_DTMR */ -#define MCF_DTIM_DTMR_RST (0x0001) -#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) -#define MCF_DTIM_DTMR_FRR (0x0008) -#define MCF_DTIM_DTMR_ORRI (0x0010) -#define MCF_DTIM_DTMR_OM (0x0020) -#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) -#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) -#define MCF_DTIM_DTMR_CE_ANY (0x00C0) -#define MCF_DTIM_DTMR_CE_FALL (0x0080) -#define MCF_DTIM_DTMR_CE_RISE (0x0040) -#define MCF_DTIM_DTMR_CE_NONE (0x0000) -#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) -#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) -#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) -#define MCF_DTIM_DTMR_CLK_STOP (0x0000) - -/* Bit definitions and macros for MCF_DTIM_DTXMR */ -#define MCF_DTIM_DTXMR_MODE16 (0x01) -#define MCF_DTIM_DTXMR_DMAEN (0x80) - -/* Bit definitions and macros for MCF_DTIM_DTER */ -#define MCF_DTIM_DTER_CAP (0x01) -#define MCF_DTIM_DTER_REF (0x02) - -/* Bit definitions and macros for MCF_DTIM_DTRR */ -#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DTIM_DTCR */ -#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DTIM_DTCN */ -#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* -* -* Interrupt Controller (INTC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC0_IPRH (*(vuint32*)(&__IPSBAR[0x000C00])) -#define MCF_INTC0_IPRL (*(vuint32*)(&__IPSBAR[0x000C04])) -#define MCF_INTC0_IMRH (*(vuint32*)(&__IPSBAR[0x000C08])) -#define MCF_INTC0_IMRL (*(vuint32*)(&__IPSBAR[0x000C0C])) -#define MCF_INTC0_INTFRCH (*(vuint32*)(&__IPSBAR[0x000C10])) -#define MCF_INTC0_INTFRCL (*(vuint32*)(&__IPSBAR[0x000C14])) -#define MCF_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0x000C18])) -#define MCF_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000C19])) -#define MCF_INTC0_ICR1 (*(vuint8 *)(&__IPSBAR[0x000C41])) -#define MCF_INTC0_ICR2 (*(vuint8 *)(&__IPSBAR[0x000C42])) -#define MCF_INTC0_ICR3 (*(vuint8 *)(&__IPSBAR[0x000C43])) -#define MCF_INTC0_ICR4 (*(vuint8 *)(&__IPSBAR[0x000C44])) -#define MCF_INTC0_ICR5 (*(vuint8 *)(&__IPSBAR[0x000C45])) -#define MCF_INTC0_ICR6 (*(vuint8 *)(&__IPSBAR[0x000C46])) -#define MCF_INTC0_ICR7 (*(vuint8 *)(&__IPSBAR[0x000C47])) -#define MCF_INTC0_ICR8 (*(vuint8 *)(&__IPSBAR[0x000C48])) -#define MCF_INTC0_ICR9 (*(vuint8 *)(&__IPSBAR[0x000C49])) -#define MCF_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0x000C4A])) -#define MCF_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0x000C4B])) -#define MCF_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0x000C4C])) -#define MCF_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0x000C4D])) -#define MCF_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0x000C4E])) -#define MCF_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0x000C4F])) -#define MCF_INTC0_ICR16 (*(vuint8 *)(&__IPSBAR[0x000C50])) -#define MCF_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0x000C51])) -#define MCF_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0x000C52])) -#define MCF_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0x000C53])) -#define MCF_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0x000C54])) -#define MCF_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0x000C55])) -#define MCF_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0x000C56])) -#define MCF_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0x000C57])) -#define MCF_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0x000C58])) -#define MCF_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0x000C59])) -#define MCF_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0x000C5A])) -#define MCF_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0x000C5B])) -#define MCF_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0x000C5C])) -#define MCF_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0x000C5D])) -#define MCF_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0x000C5E])) -#define MCF_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0x000C5F])) -#define MCF_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0x000C60])) -#define MCF_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0x000C61])) -#define MCF_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0x000C62])) -#define MCF_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0x000C63])) -#define MCF_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0x000C64])) -#define MCF_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0x000C65])) -#define MCF_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0x000C66])) -#define MCF_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0x000C67])) -#define MCF_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0x000C68])) -#define MCF_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0x000C69])) -#define MCF_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0x000C6A])) -#define MCF_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0x000C6B])) -#define MCF_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0x000C6C])) -#define MCF_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0x000C6D])) -#define MCF_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0x000C6E])) -#define MCF_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0x000C6F])) -#define MCF_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0x000C70])) -#define MCF_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0x000C71])) -#define MCF_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0x000C72])) -#define MCF_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0x000C73])) -#define MCF_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0x000C74])) -#define MCF_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0x000C75])) -#define MCF_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0x000C76])) -#define MCF_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0x000C77])) -#define MCF_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0x000C78])) -#define MCF_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0x000C79])) -#define MCF_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0x000C7A])) -#define MCF_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0x000C7B])) -#define MCF_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0x000C7C])) -#define MCF_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0x000C7D])) -#define MCF_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0x000C7E])) -#define MCF_INTC0_ICR63 (*(vuint8 *)(&__IPSBAR[0x000C7F])) -#define MCF_INTC0_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x-1)*0x001)])) -#define MCF_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0x000CE0])) -#define MCF_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0x000CE4])) -#define MCF_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0x000CE8])) -#define MCF_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0x000CEC])) -#define MCF_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0x000CF0])) -#define MCF_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0x000CF4])) -#define MCF_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0x000CF8])) -#define MCF_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0x000CFC])) -#define MCF_INTC0_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x-1)*0x004)])) -#define MCF_INTC1_IPRH (*(vuint32*)(&__IPSBAR[0x000D00])) -#define MCF_INTC1_IPRL (*(vuint32*)(&__IPSBAR[0x000D04])) -#define MCF_INTC1_IMRH (*(vuint32*)(&__IPSBAR[0x000D08])) -#define MCF_INTC1_IMRL (*(vuint32*)(&__IPSBAR[0x000D0C])) -#define MCF_INTC1_INTFRCH (*(vuint32*)(&__IPSBAR[0x000D10])) -#define MCF_INTC1_INTFRCL (*(vuint32*)(&__IPSBAR[0x000D14])) -#define MCF_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0x000D18])) -#define MCF_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000D19])) -#define MCF_INTC1_ICR1 (*(vuint8 *)(&__IPSBAR[0x000D41])) -#define MCF_INTC1_ICR2 (*(vuint8 *)(&__IPSBAR[0x000D42])) -#define MCF_INTC1_ICR3 (*(vuint8 *)(&__IPSBAR[0x000D43])) -#define MCF_INTC1_ICR4 (*(vuint8 *)(&__IPSBAR[0x000D44])) -#define MCF_INTC1_ICR5 (*(vuint8 *)(&__IPSBAR[0x000D45])) -#define MCF_INTC1_ICR6 (*(vuint8 *)(&__IPSBAR[0x000D46])) -#define MCF_INTC1_ICR7 (*(vuint8 *)(&__IPSBAR[0x000D47])) -#define MCF_INTC1_ICR8 (*(vuint8 *)(&__IPSBAR[0x000D48])) -#define MCF_INTC1_ICR9 (*(vuint8 *)(&__IPSBAR[0x000D49])) -#define MCF_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0x000D4A])) -#define MCF_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0x000D4B])) -#define MCF_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0x000D4C])) -#define MCF_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0x000D4D])) -#define MCF_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0x000D4E])) -#define MCF_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0x000D4F])) -#define MCF_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0x000D50])) -#define MCF_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0x000D51])) -#define MCF_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0x000D52])) -#define MCF_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0x000D53])) -#define MCF_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0x000D54])) -#define MCF_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0x000D55])) -#define MCF_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0x000D56])) -#define MCF_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0x000D57])) -#define MCF_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0x000D58])) -#define MCF_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0x000D59])) -#define MCF_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0x000D5A])) -#define MCF_INTC1_ICR27 (*(vuint8 *)(&__IPSBAR[0x000D5B])) -#define MCF_INTC1_ICR28 (*(vuint8 *)(&__IPSBAR[0x000D5C])) -#define MCF_INTC1_ICR29 (*(vuint8 *)(&__IPSBAR[0x000D5D])) -#define MCF_INTC1_ICR30 (*(vuint8 *)(&__IPSBAR[0x000D5E])) -#define MCF_INTC1_ICR31 (*(vuint8 *)(&__IPSBAR[0x000D5F])) -#define MCF_INTC1_ICR32 (*(vuint8 *)(&__IPSBAR[0x000D60])) -#define MCF_INTC1_ICR33 (*(vuint8 *)(&__IPSBAR[0x000D61])) -#define MCF_INTC1_ICR34 (*(vuint8 *)(&__IPSBAR[0x000D62])) -#define MCF_INTC1_ICR35 (*(vuint8 *)(&__IPSBAR[0x000D63])) -#define MCF_INTC1_ICR36 (*(vuint8 *)(&__IPSBAR[0x000D64])) -#define MCF_INTC1_ICR37 (*(vuint8 *)(&__IPSBAR[0x000D65])) -#define MCF_INTC1_ICR38 (*(vuint8 *)(&__IPSBAR[0x000D66])) -#define MCF_INTC1_ICR39 (*(vuint8 *)(&__IPSBAR[0x000D67])) -#define MCF_INTC1_ICR40 (*(vuint8 *)(&__IPSBAR[0x000D68])) -#define MCF_INTC1_ICR41 (*(vuint8 *)(&__IPSBAR[0x000D69])) -#define MCF_INTC1_ICR42 (*(vuint8 *)(&__IPSBAR[0x000D6A])) -#define MCF_INTC1_ICR43 (*(vuint8 *)(&__IPSBAR[0x000D6B])) -#define MCF_INTC1_ICR44 (*(vuint8 *)(&__IPSBAR[0x000D6C])) -#define MCF_INTC1_ICR45 (*(vuint8 *)(&__IPSBAR[0x000D6D])) -#define MCF_INTC1_ICR46 (*(vuint8 *)(&__IPSBAR[0x000D6E])) -#define MCF_INTC1_ICR47 (*(vuint8 *)(&__IPSBAR[0x000D6F])) -#define MCF_INTC1_ICR48 (*(vuint8 *)(&__IPSBAR[0x000D70])) -#define MCF_INTC1_ICR49 (*(vuint8 *)(&__IPSBAR[0x000D71])) -#define MCF_INTC1_ICR50 (*(vuint8 *)(&__IPSBAR[0x000D72])) -#define MCF_INTC1_ICR51 (*(vuint8 *)(&__IPSBAR[0x000D73])) -#define MCF_INTC1_ICR52 (*(vuint8 *)(&__IPSBAR[0x000D74])) -#define MCF_INTC1_ICR53 (*(vuint8 *)(&__IPSBAR[0x000D75])) -#define MCF_INTC1_ICR54 (*(vuint8 *)(&__IPSBAR[0x000D76])) -#define MCF_INTC1_ICR55 (*(vuint8 *)(&__IPSBAR[0x000D77])) -#define MCF_INTC1_ICR56 (*(vuint8 *)(&__IPSBAR[0x000D78])) -#define MCF_INTC1_ICR57 (*(vuint8 *)(&__IPSBAR[0x000D79])) -#define MCF_INTC1_ICR58 (*(vuint8 *)(&__IPSBAR[0x000D7A])) -#define MCF_INTC1_ICR59 (*(vuint8 *)(&__IPSBAR[0x000D7B])) -#define MCF_INTC1_ICR60 (*(vuint8 *)(&__IPSBAR[0x000D7C])) -#define MCF_INTC1_ICR61 (*(vuint8 *)(&__IPSBAR[0x000D7D])) -#define MCF_INTC1_ICR62 (*(vuint8 *)(&__IPSBAR[0x000D7E])) -#define MCF_INTC1_ICR63 (*(vuint8 *)(&__IPSBAR[0x000D7F])) -#define MCF_INTC1_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000D41+((x-1)*0x001)])) -#define MCF_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0x000DE0])) -#define MCF_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0x000DE4])) -#define MCF_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0x000DE8])) -#define MCF_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0x000DEC])) -#define MCF_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0x000DF0])) -#define MCF_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0x000DF4])) -#define MCF_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0x000DF8])) -#define MCF_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0x000DFC])) -#define MCF_INTC1_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000DE4+((x-1)*0x004)])) -#define MCF_INTC_IPRH(x) (*(vuint32*)(&__IPSBAR[0x000C00+((x)*0x100)])) -#define MCF_INTC_IPRL(x) (*(vuint32*)(&__IPSBAR[0x000C04+((x)*0x100)])) -#define MCF_INTC_IMRH(x) (*(vuint32*)(&__IPSBAR[0x000C08+((x)*0x100)])) -#define MCF_INTC_IMRL(x) (*(vuint32*)(&__IPSBAR[0x000C0C+((x)*0x100)])) -#define MCF_INTC_INTFRCH(x) (*(vuint32*)(&__IPSBAR[0x000C10+((x)*0x100)])) -#define MCF_INTC_INTFRCL(x) (*(vuint32*)(&__IPSBAR[0x000C14+((x)*0x100)])) -#define MCF_INTC_IRLR(x) (*(vuint8 *)(&__IPSBAR[0x000C18+((x)*0x100)])) -#define MCF_INTC_IACKLPR(x) (*(vuint8 *)(&__IPSBAR[0x000C19+((x)*0x100)])) -#define MCF_INTC_ICR1(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x)*0x100)])) -#define MCF_INTC_ICR2(x) (*(vuint8 *)(&__IPSBAR[0x000C42+((x)*0x100)])) -#define MCF_INTC_ICR3(x) (*(vuint8 *)(&__IPSBAR[0x000C43+((x)*0x100)])) -#define MCF_INTC_ICR4(x) (*(vuint8 *)(&__IPSBAR[0x000C44+((x)*0x100)])) -#define MCF_INTC_ICR5(x) (*(vuint8 *)(&__IPSBAR[0x000C45+((x)*0x100)])) -#define MCF_INTC_ICR6(x) (*(vuint8 *)(&__IPSBAR[0x000C46+((x)*0x100)])) -#define MCF_INTC_ICR7(x) (*(vuint8 *)(&__IPSBAR[0x000C47+((x)*0x100)])) -#define MCF_INTC_ICR8(x) (*(vuint8 *)(&__IPSBAR[0x000C48+((x)*0x100)])) -#define MCF_INTC_ICR9(x) (*(vuint8 *)(&__IPSBAR[0x000C49+((x)*0x100)])) -#define MCF_INTC_ICR10(x) (*(vuint8 *)(&__IPSBAR[0x000C4A+((x)*0x100)])) -#define MCF_INTC_ICR11(x) (*(vuint8 *)(&__IPSBAR[0x000C4B+((x)*0x100)])) -#define MCF_INTC_ICR12(x) (*(vuint8 *)(&__IPSBAR[0x000C4C+((x)*0x100)])) -#define MCF_INTC_ICR13(x) (*(vuint8 *)(&__IPSBAR[0x000C4D+((x)*0x100)])) -#define MCF_INTC_ICR14(x) (*(vuint8 *)(&__IPSBAR[0x000C4E+((x)*0x100)])) -#define MCF_INTC_ICR15(x) (*(vuint8 *)(&__IPSBAR[0x000C4F+((x)*0x100)])) -#define MCF_INTC_ICR16(x) (*(vuint8 *)(&__IPSBAR[0x000C50+((x)*0x100)])) -#define MCF_INTC_ICR17(x) (*(vuint8 *)(&__IPSBAR[0x000C51+((x)*0x100)])) -#define MCF_INTC_ICR18(x) (*(vuint8 *)(&__IPSBAR[0x000C52+((x)*0x100)])) -#define MCF_INTC_ICR19(x) (*(vuint8 *)(&__IPSBAR[0x000C53+((x)*0x100)])) -#define MCF_INTC_ICR20(x) (*(vuint8 *)(&__IPSBAR[0x000C54+((x)*0x100)])) -#define MCF_INTC_ICR21(x) (*(vuint8 *)(&__IPSBAR[0x000C55+((x)*0x100)])) -#define MCF_INTC_ICR22(x) (*(vuint8 *)(&__IPSBAR[0x000C56+((x)*0x100)])) -#define MCF_INTC_ICR23(x) (*(vuint8 *)(&__IPSBAR[0x000C57+((x)*0x100)])) -#define MCF_INTC_ICR24(x) (*(vuint8 *)(&__IPSBAR[0x000C58+((x)*0x100)])) -#define MCF_INTC_ICR25(x) (*(vuint8 *)(&__IPSBAR[0x000C59+((x)*0x100)])) -#define MCF_INTC_ICR26(x) (*(vuint8 *)(&__IPSBAR[0x000C5A+((x)*0x100)])) -#define MCF_INTC_ICR27(x) (*(vuint8 *)(&__IPSBAR[0x000C5B+((x)*0x100)])) -#define MCF_INTC_ICR28(x) (*(vuint8 *)(&__IPSBAR[0x000C5C+((x)*0x100)])) -#define MCF_INTC_ICR29(x) (*(vuint8 *)(&__IPSBAR[0x000C5D+((x)*0x100)])) -#define MCF_INTC_ICR30(x) (*(vuint8 *)(&__IPSBAR[0x000C5E+((x)*0x100)])) -#define MCF_INTC_ICR31(x) (*(vuint8 *)(&__IPSBAR[0x000C5F+((x)*0x100)])) -#define MCF_INTC_ICR32(x) (*(vuint8 *)(&__IPSBAR[0x000C60+((x)*0x100)])) -#define MCF_INTC_ICR33(x) (*(vuint8 *)(&__IPSBAR[0x000C61+((x)*0x100)])) -#define MCF_INTC_ICR34(x) (*(vuint8 *)(&__IPSBAR[0x000C62+((x)*0x100)])) -#define MCF_INTC_ICR35(x) (*(vuint8 *)(&__IPSBAR[0x000C63+((x)*0x100)])) -#define MCF_INTC_ICR36(x) (*(vuint8 *)(&__IPSBAR[0x000C64+((x)*0x100)])) -#define MCF_INTC_ICR37(x) (*(vuint8 *)(&__IPSBAR[0x000C65+((x)*0x100)])) -#define MCF_INTC_ICR38(x) (*(vuint8 *)(&__IPSBAR[0x000C66+((x)*0x100)])) -#define MCF_INTC_ICR39(x) (*(vuint8 *)(&__IPSBAR[0x000C67+((x)*0x100)])) -#define MCF_INTC_ICR40(x) (*(vuint8 *)(&__IPSBAR[0x000C68+((x)*0x100)])) -#define MCF_INTC_ICR41(x) (*(vuint8 *)(&__IPSBAR[0x000C69+((x)*0x100)])) -#define MCF_INTC_ICR42(x) (*(vuint8 *)(&__IPSBAR[0x000C6A+((x)*0x100)])) -#define MCF_INTC_ICR43(x) (*(vuint8 *)(&__IPSBAR[0x000C6B+((x)*0x100)])) -#define MCF_INTC_ICR44(x) (*(vuint8 *)(&__IPSBAR[0x000C6C+((x)*0x100)])) -#define MCF_INTC_ICR45(x) (*(vuint8 *)(&__IPSBAR[0x000C6D+((x)*0x100)])) -#define MCF_INTC_ICR46(x) (*(vuint8 *)(&__IPSBAR[0x000C6E+((x)*0x100)])) -#define MCF_INTC_ICR47(x) (*(vuint8 *)(&__IPSBAR[0x000C6F+((x)*0x100)])) -#define MCF_INTC_ICR48(x) (*(vuint8 *)(&__IPSBAR[0x000C70+((x)*0x100)])) -#define MCF_INTC_ICR49(x) (*(vuint8 *)(&__IPSBAR[0x000C71+((x)*0x100)])) -#define MCF_INTC_ICR50(x) (*(vuint8 *)(&__IPSBAR[0x000C72+((x)*0x100)])) -#define MCF_INTC_ICR51(x) (*(vuint8 *)(&__IPSBAR[0x000C73+((x)*0x100)])) -#define MCF_INTC_ICR52(x) (*(vuint8 *)(&__IPSBAR[0x000C74+((x)*0x100)])) -#define MCF_INTC_ICR53(x) (*(vuint8 *)(&__IPSBAR[0x000C75+((x)*0x100)])) -#define MCF_INTC_ICR54(x) (*(vuint8 *)(&__IPSBAR[0x000C76+((x)*0x100)])) -#define MCF_INTC_ICR55(x) (*(vuint8 *)(&__IPSBAR[0x000C77+((x)*0x100)])) -#define MCF_INTC_ICR56(x) (*(vuint8 *)(&__IPSBAR[0x000C78+((x)*0x100)])) -#define MCF_INTC_ICR57(x) (*(vuint8 *)(&__IPSBAR[0x000C79+((x)*0x100)])) -#define MCF_INTC_ICR58(x) (*(vuint8 *)(&__IPSBAR[0x000C7A+((x)*0x100)])) -#define MCF_INTC_ICR59(x) (*(vuint8 *)(&__IPSBAR[0x000C7B+((x)*0x100)])) -#define MCF_INTC_ICR60(x) (*(vuint8 *)(&__IPSBAR[0x000C7C+((x)*0x100)])) -#define MCF_INTC_ICR61(x) (*(vuint8 *)(&__IPSBAR[0x000C7D+((x)*0x100)])) -#define MCF_INTC_ICR62(x) (*(vuint8 *)(&__IPSBAR[0x000C7E+((x)*0x100)])) -#define MCF_INTC_ICR63(x) (*(vuint8 *)(&__IPSBAR[0x000C7F+((x)*0x100)])) -#define MCF_INTC_SWIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE0+((x)*0x100)])) -#define MCF_INTC_L1IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x)*0x100)])) -#define MCF_INTC_L2IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE8+((x)*0x100)])) -#define MCF_INTC_L3IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CEC+((x)*0x100)])) -#define MCF_INTC_L4IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF0+((x)*0x100)])) -#define MCF_INTC_L5IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF4+((x)*0x100)])) -#define MCF_INTC_L6IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF8+((x)*0x100)])) -#define MCF_INTC_L7IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CFC+((x)*0x100)])) - -/* Bit definitions and macros for MCF_INTC_IPRH */ -#define MCF_INTC_IPRH_INT32 (0x00000001) -#define MCF_INTC_IPRH_INT33 (0x00000002) -#define MCF_INTC_IPRH_INT34 (0x00000004) -#define MCF_INTC_IPRH_INT35 (0x00000008) -#define MCF_INTC_IPRH_INT36 (0x00000010) -#define MCF_INTC_IPRH_INT37 (0x00000020) -#define MCF_INTC_IPRH_INT38 (0x00000040) -#define MCF_INTC_IPRH_INT39 (0x00000080) -#define MCF_INTC_IPRH_INT40 (0x00000100) -#define MCF_INTC_IPRH_INT41 (0x00000200) -#define MCF_INTC_IPRH_INT42 (0x00000400) -#define MCF_INTC_IPRH_INT43 (0x00000800) -#define MCF_INTC_IPRH_INT44 (0x00001000) -#define MCF_INTC_IPRH_INT45 (0x00002000) -#define MCF_INTC_IPRH_INT46 (0x00004000) -#define MCF_INTC_IPRH_INT47 (0x00008000) -#define MCF_INTC_IPRH_INT48 (0x00010000) -#define MCF_INTC_IPRH_INT49 (0x00020000) -#define MCF_INTC_IPRH_INT50 (0x00040000) -#define MCF_INTC_IPRH_INT51 (0x00080000) -#define MCF_INTC_IPRH_INT52 (0x00100000) -#define MCF_INTC_IPRH_INT53 (0x00200000) -#define MCF_INTC_IPRH_INT54 (0x00400000) -#define MCF_INTC_IPRH_INT55 (0x00800000) -#define MCF_INTC_IPRH_INT56 (0x01000000) -#define MCF_INTC_IPRH_INT57 (0x02000000) -#define MCF_INTC_IPRH_INT58 (0x04000000) -#define MCF_INTC_IPRH_INT59 (0x08000000) -#define MCF_INTC_IPRH_INT60 (0x10000000) -#define MCF_INTC_IPRH_INT61 (0x20000000) -#define MCF_INTC_IPRH_INT62 (0x40000000) -#define MCF_INTC_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IPRL */ -#define MCF_INTC_IPRL_INT1 (0x00000002) -#define MCF_INTC_IPRL_INT2 (0x00000004) -#define MCF_INTC_IPRL_INT3 (0x00000008) -#define MCF_INTC_IPRL_INT4 (0x00000010) -#define MCF_INTC_IPRL_INT5 (0x00000020) -#define MCF_INTC_IPRL_INT6 (0x00000040) -#define MCF_INTC_IPRL_INT7 (0x00000080) -#define MCF_INTC_IPRL_INT8 (0x00000100) -#define MCF_INTC_IPRL_INT9 (0x00000200) -#define MCF_INTC_IPRL_INT10 (0x00000400) -#define MCF_INTC_IPRL_INT11 (0x00000800) -#define MCF_INTC_IPRL_INT12 (0x00001000) -#define MCF_INTC_IPRL_INT13 (0x00002000) -#define MCF_INTC_IPRL_INT14 (0x00004000) -#define MCF_INTC_IPRL_INT15 (0x00008000) -#define MCF_INTC_IPRL_INT16 (0x00010000) -#define MCF_INTC_IPRL_INT17 (0x00020000) -#define MCF_INTC_IPRL_INT18 (0x00040000) -#define MCF_INTC_IPRL_INT19 (0x00080000) -#define MCF_INTC_IPRL_INT20 (0x00100000) -#define MCF_INTC_IPRL_INT21 (0x00200000) -#define MCF_INTC_IPRL_INT22 (0x00400000) -#define MCF_INTC_IPRL_INT23 (0x00800000) -#define MCF_INTC_IPRL_INT24 (0x01000000) -#define MCF_INTC_IPRL_INT25 (0x02000000) -#define MCF_INTC_IPRL_INT26 (0x04000000) -#define MCF_INTC_IPRL_INT27 (0x08000000) -#define MCF_INTC_IPRL_INT28 (0x10000000) -#define MCF_INTC_IPRL_INT29 (0x20000000) -#define MCF_INTC_IPRL_INT30 (0x40000000) -#define MCF_INTC_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRH */ -#define MCF_INTC_IMRH_MASK32 (0x00000001) -#define MCF_INTC_IMRH_MASK33 (0x00000002) -#define MCF_INTC_IMRH_MASK34 (0x00000004) -#define MCF_INTC_IMRH_MASK35 (0x00000008) -#define MCF_INTC_IMRH_MASK36 (0x00000010) -#define MCF_INTC_IMRH_MASK37 (0x00000020) -#define MCF_INTC_IMRH_MASK38 (0x00000040) -#define MCF_INTC_IMRH_MASK39 (0x00000080) -#define MCF_INTC_IMRH_MASK40 (0x00000100) -#define MCF_INTC_IMRH_MASK41 (0x00000200) -#define MCF_INTC_IMRH_MASK42 (0x00000400) -#define MCF_INTC_IMRH_MASK43 (0x00000800) -#define MCF_INTC_IMRH_MASK44 (0x00001000) -#define MCF_INTC_IMRH_MASK45 (0x00002000) -#define MCF_INTC_IMRH_MASK46 (0x00004000) -#define MCF_INTC_IMRH_MASK47 (0x00008000) -#define MCF_INTC_IMRH_MASK48 (0x00010000) -#define MCF_INTC_IMRH_MASK49 (0x00020000) -#define MCF_INTC_IMRH_MASK50 (0x00040000) -#define MCF_INTC_IMRH_MASK51 (0x00080000) -#define MCF_INTC_IMRH_MASK52 (0x00100000) -#define MCF_INTC_IMRH_MASK53 (0x00200000) -#define MCF_INTC_IMRH_MASK54 (0x00400000) -#define MCF_INTC_IMRH_MASK55 (0x00800000) -#define MCF_INTC_IMRH_MASK56 (0x01000000) -#define MCF_INTC_IMRH_MASK57 (0x02000000) -#define MCF_INTC_IMRH_MASK58 (0x04000000) -#define MCF_INTC_IMRH_MASK59 (0x08000000) -#define MCF_INTC_IMRH_MASK60 (0x10000000) -#define MCF_INTC_IMRH_MASK61 (0x20000000) -#define MCF_INTC_IMRH_MASK62 (0x40000000) -#define MCF_INTC_IMRH_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRL */ -#define MCF_INTC_IMRL_MASKALL (0x00000001) -#define MCF_INTC_IMRL_MASK1 (0x00000002) -#define MCF_INTC_IMRL_MASK2 (0x00000004) -#define MCF_INTC_IMRL_MASK3 (0x00000008) -#define MCF_INTC_IMRL_MASK4 (0x00000010) -#define MCF_INTC_IMRL_MASK5 (0x00000020) -#define MCF_INTC_IMRL_MASK6 (0x00000040) -#define MCF_INTC_IMRL_MASK7 (0x00000080) -#define MCF_INTC_IMRL_MASK8 (0x00000100) -#define MCF_INTC_IMRL_MASK9 (0x00000200) -#define MCF_INTC_IMRL_MASK10 (0x00000400) -#define MCF_INTC_IMRL_MASK11 (0x00000800) -#define MCF_INTC_IMRL_MASK12 (0x00001000) -#define MCF_INTC_IMRL_MASK13 (0x00002000) -#define MCF_INTC_IMRL_MASK14 (0x00004000) -#define MCF_INTC_IMRL_MASK15 (0x00008000) -#define MCF_INTC_IMRL_MASK16 (0x00010000) -#define MCF_INTC_IMRL_MASK17 (0x00020000) -#define MCF_INTC_IMRL_MASK18 (0x00040000) -#define MCF_INTC_IMRL_MASK19 (0x00080000) -#define MCF_INTC_IMRL_MASK20 (0x00100000) -#define MCF_INTC_IMRL_MASK21 (0x00200000) -#define MCF_INTC_IMRL_MASK22 (0x00400000) -#define MCF_INTC_IMRL_MASK23 (0x00800000) -#define MCF_INTC_IMRL_MASK24 (0x01000000) -#define MCF_INTC_IMRL_MASK25 (0x02000000) -#define MCF_INTC_IMRL_MASK26 (0x04000000) -#define MCF_INTC_IMRL_MASK27 (0x08000000) -#define MCF_INTC_IMRL_MASK28 (0x10000000) -#define MCF_INTC_IMRL_MASK29 (0x20000000) -#define MCF_INTC_IMRL_MASK30 (0x40000000) -#define MCF_INTC_IMRL_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCH */ -#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCL */ -#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) -#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) -#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) -#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) -#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) -#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) -#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IRLR */ -#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_INTC_IACKLPR */ -#define MCF_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_INTC_ICR */ -#define MCF_INTC_ICR_IP(x) (((x)&0x07)<<0) -#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<3) - -/* Bit definitions and macros for MCF_INTC_SWIACK */ -#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_INTC_LIACK */ -#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) - -/********************************************************************* -* -* General Purpose I/O (GPIO) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPIO_PORTNQ (*(vuint8 *)(&__IPSBAR[0x100008])) -#define MCF_GPIO_PORTAN (*(vuint8 *)(&__IPSBAR[0x10000A])) -#define MCF_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000B])) -#define MCF_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000C])) -#define MCF_GPIO_PORTTA (*(vuint8 *)(&__IPSBAR[0x10000E])) -#define MCF_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F])) -#define MCF_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010])) -#define MCF_GPIO_PORTTE (*(vuint8 *)(&__IPSBAR[0x100000])) -#define MCF_GPIO_PORTTF (*(vuint8 *)(&__IPSBAR[0x100001])) -#define MCF_GPIO_PORTTG (*(vuint8 *)(&__IPSBAR[0x100002])) -#define MCF_GPIO_PORTTH (*(vuint8 *)(&__IPSBAR[0x100003])) -#define MCF_GPIO_PORTTI (*(vuint8 *)(&__IPSBAR[0x100004])) -#define MCF_GPIO_PORTTJ (*(vuint8 *)(&__IPSBAR[0x100006])) -#define MCF_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011])) -#define MCF_GPIO_PORTUB (*(vuint8 *)(&__IPSBAR[0x100012])) -#define MCF_GPIO_PORTUC (*(vuint8 *)(&__IPSBAR[0x100013])) -#define MCF_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100014])) -#define MCF_GPIO_PORTLD (*(vuint8 *)(&__IPSBAR[0x100015])) -#define MCF_GPIO_PORTGP (*(vuint8 *)(&__IPSBAR[0x100016])) -#define MCF_GPIO_DDRNQ (*(vuint8 *)(&__IPSBAR[0x100020])) -#define MCF_GPIO_DDRAN (*(vuint8 *)(&__IPSBAR[0x100022])) -#define MCF_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100023])) -#define MCF_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100024])) -#define MCF_GPIO_DDRTA (*(vuint8 *)(&__IPSBAR[0x100026])) -#define MCF_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100027])) -#define MCF_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100028])) -#define MCF_GPIO_DDRTE (*(vuint8 *)(&__IPSBAR[0x100018])) -#define MCF_GPIO_DDRTF (*(vuint8 *)(&__IPSBAR[0x100019])) -#define MCF_GPIO_DDRTG (*(vuint8 *)(&__IPSBAR[0x10001A])) -#define MCF_GPIO_DDRTH (*(vuint8 *)(&__IPSBAR[0x10001B])) -#define MCF_GPIO_DDRTI (*(vuint8 *)(&__IPSBAR[0x10001C])) -#define MCF_GPIO_DDRTJ (*(vuint8 *)(&__IPSBAR[0x10001E])) -#define MCF_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100029])) -#define MCF_GPIO_DDRUB (*(vuint8 *)(&__IPSBAR[0x10002A])) -#define MCF_GPIO_DDRUC (*(vuint8 *)(&__IPSBAR[0x10002B])) -#define MCF_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10002C])) -#define MCF_GPIO_DDRLD (*(vuint8 *)(&__IPSBAR[0x10002D])) -#define MCF_GPIO_DDRGP (*(vuint8 *)(&__IPSBAR[0x10002E])) -#define MCF_GPIO_SETNQ (*(vuint8 *)(&__IPSBAR[0x100038])) -#define MCF_GPIO_SETAN (*(vuint8 *)(&__IPSBAR[0x10003A])) -#define MCF_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x10003B])) -#define MCF_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x10003C])) -#define MCF_GPIO_SETTA (*(vuint8 *)(&__IPSBAR[0x10003E])) -#define MCF_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x10003F])) -#define MCF_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100040])) -#define MCF_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100041])) -#define MCF_GPIO_SETUB (*(vuint8 *)(&__IPSBAR[0x100042])) -#define MCF_GPIO_SETUC (*(vuint8 *)(&__IPSBAR[0x100043])) -#define MCF_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100044])) -#define MCF_GPIO_SETLD (*(vuint8 *)(&__IPSBAR[0x100045])) -#define MCF_GPIO_SETGP (*(vuint8 *)(&__IPSBAR[0x100046])) -#define MCF_GPIO_CLRNQ (*(vuint8 *)(&__IPSBAR[0x100050])) -#define MCF_GPIO_CLRAN (*(vuint8 *)(&__IPSBAR[0x100052])) -#define MCF_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100053])) -#define MCF_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100054])) -#define MCF_GPIO_CLRTA (*(vuint8 *)(&__IPSBAR[0x100056])) -#define MCF_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x100057])) -#define MCF_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x100058])) -#define MCF_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x100059])) -#define MCF_GPIO_CLRUB (*(vuint8 *)(&__IPSBAR[0x10005A])) -#define MCF_GPIO_CLRUC (*(vuint8 *)(&__IPSBAR[0x10005B])) -#define MCF_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x10005C])) -#define MCF_GPIO_CLRLD (*(vuint8 *)(&__IPSBAR[0x10005D])) -#define MCF_GPIO_CLRGP (*(vuint8 *)(&__IPSBAR[0x10005E])) -#define MCF_GPIO_PNQPAR (*(vuint16*)(&__IPSBAR[0x100068])) -#define MCF_GPIO_PANPAR (*(vuint8 *)(&__IPSBAR[0x10006A])) -#define MCF_GPIO_PASPAR (*(vuint8 *)(&__IPSBAR[0x10006B])) -#define MCF_GPIO_PQSPAR (*(vuint16*)(&__IPSBAR[0x10006C])) -#define MCF_GPIO_PTAPAR (*(vuint8 *)(&__IPSBAR[0x10006E])) -#define MCF_GPIO_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10006F])) -#define MCF_GPIO_PTDPAR (*(vuint8 *)(&__IPSBAR[0x100070])) -#define MCF_GPIO_PTEPAR (*(vuint8 *)(&__IPSBAR[0x100060])) -#define MCF_GPIO_PTFPAR (*(vuint8 *)(&__IPSBAR[0x100061])) -#define MCF_GPIO_PTGPAR (*(vuint8 *)(&__IPSBAR[0x100062])) -#define MCF_GPIO_PTHPAR (*(vuint8 *)(&__IPSBAR[0x100090])) -#define MCF_GPIO_PTIPAR (*(vuint8*)(&__IPSBAR[0x100064])) -#define MCF_GPIO_PTJPAR (*(vuint8*)(&__IPSBAR[0x100066])) -#define MCF_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x100071])) -#define MCF_GPIO_PUBPAR (*(vuint8 *)(&__IPSBAR[0x100072])) -#define MCF_GPIO_PUCPAR (*(vuint8 *)(&__IPSBAR[0x100073])) -#define MCF_GPIO_PDDPAR (*(vuint8 *)(&__IPSBAR[0x100074])) -#define MCF_GPIO_PLDPAR (*(vuint8 *)(&__IPSBAR[0x100075])) -#define MCF_GPIO_PGPPAR (*(vuint8 *)(&__IPSBAR[0x100076])) -#define MCF_GPIO_PWOR (*(vuint16*)(&__IPSBAR[0x100078])) -#define MCF_GPIO_PDSRH (*(vuint16*)(&__IPSBAR[0x10007A])) -#define MCF_GPIO_PDSRL (*(vuint32*)(&__IPSBAR[0x10007C])) - -/* Bit definitions and macros for MCF_GPIO_PORTNQ */ -#define MCF_GPIO_PORTNQ_PORTNQ0 (0x01) -#define MCF_GPIO_PORTNQ_PORTNQ1 (0x02) -#define MCF_GPIO_PORTNQ_PORTNQ2 (0x04) -#define MCF_GPIO_PORTNQ_PORTNQ3 (0x08) -#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10) -#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20) -#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40) -#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTAN */ -#define MCF_GPIO_PORTAN_PORTAN0 (0x01) -#define MCF_GPIO_PORTAN_PORTAN1 (0x02) -#define MCF_GPIO_PORTAN_PORTAN2 (0x04) -#define MCF_GPIO_PORTAN_PORTAN3 (0x08) -#define MCF_GPIO_PORTAN_PORTAN4 (0x10) -#define MCF_GPIO_PORTAN_PORTAN5 (0x20) -#define MCF_GPIO_PORTAN_PORTAN6 (0x40) -#define MCF_GPIO_PORTAN_PORTAN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTAS */ -#define MCF_GPIO_PORTAS_PORTAS0 (0x01) -#define MCF_GPIO_PORTAS_PORTAS1 (0x02) -#define MCF_GPIO_PORTAS_PORTAS2 (0x04) -#define MCF_GPIO_PORTAS_PORTAS3 (0x08) -#define MCF_GPIO_PORTAS_PORTAS4 (0x10) -#define MCF_GPIO_PORTAS_PORTAS5 (0x20) -#define MCF_GPIO_PORTAS_PORTAS6 (0x40) -#define MCF_GPIO_PORTAS_PORTAS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTQS */ -#define MCF_GPIO_PORTQS_PORTQS0 (0x01) -#define MCF_GPIO_PORTQS_PORTQS1 (0x02) -#define MCF_GPIO_PORTQS_PORTQS2 (0x04) -#define MCF_GPIO_PORTQS_PORTQS3 (0x08) -#define MCF_GPIO_PORTQS_PORTQS4 (0x10) -#define MCF_GPIO_PORTQS_PORTQS5 (0x20) -#define MCF_GPIO_PORTQS_PORTQS6 (0x40) -#define MCF_GPIO_PORTQS_PORTQS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTA */ -#define MCF_GPIO_PORTTA_PORTTA0 (0x01) -#define MCF_GPIO_PORTTA_PORTTA1 (0x02) -#define MCF_GPIO_PORTTA_PORTTA2 (0x04) -#define MCF_GPIO_PORTTA_PORTTA3 (0x08) -#define MCF_GPIO_PORTTA_PORTTA4 (0x10) -#define MCF_GPIO_PORTTA_PORTTA5 (0x20) -#define MCF_GPIO_PORTTA_PORTTA6 (0x40) -#define MCF_GPIO_PORTTA_PORTTA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTC */ -#define MCF_GPIO_PORTTC_PORTTC0 (0x01) -#define MCF_GPIO_PORTTC_PORTTC1 (0x02) -#define MCF_GPIO_PORTTC_PORTTC2 (0x04) -#define MCF_GPIO_PORTTC_PORTTC3 (0x08) -#define MCF_GPIO_PORTTC_PORTTC4 (0x10) -#define MCF_GPIO_PORTTC_PORTTC5 (0x20) -#define MCF_GPIO_PORTTC_PORTTC6 (0x40) -#define MCF_GPIO_PORTTC_PORTTC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTD */ -#define MCF_GPIO_PORTTD_PORTTD0 (0x01) -#define MCF_GPIO_PORTTD_PORTTD1 (0x02) -#define MCF_GPIO_PORTTD_PORTTD2 (0x04) -#define MCF_GPIO_PORTTD_PORTTD3 (0x08) -#define MCF_GPIO_PORTTD_PORTTD4 (0x10) -#define MCF_GPIO_PORTTD_PORTTD5 (0x20) -#define MCF_GPIO_PORTTD_PORTTD6 (0x40) -#define MCF_GPIO_PORTTD_PORTTD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTE */ -#define MCF_GPIO_PORTTE_PORTTE0 (0x01) -#define MCF_GPIO_PORTTE_PORTTE1 (0x02) -#define MCF_GPIO_PORTTE_PORTTE2 (0x04) -#define MCF_GPIO_PORTTE_PORTTE3 (0x08) -#define MCF_GPIO_PORTTE_PORTTE4 (0x10) -#define MCF_GPIO_PORTTE_PORTTE5 (0x20) -#define MCF_GPIO_PORTTE_PORTTE6 (0x40) -#define MCF_GPIO_PORTTE_PORTTE7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTF */ -#define MCF_GPIO_PORTTF_PORTTF0 (0x01) -#define MCF_GPIO_PORTTF_PORTTF1 (0x02) -#define MCF_GPIO_PORTTF_PORTTF2 (0x04) -#define MCF_GPIO_PORTTF_PORTTF3 (0x08) -#define MCF_GPIO_PORTTF_PORTTF4 (0x10) -#define MCF_GPIO_PORTTF_PORTTF5 (0x20) -#define MCF_GPIO_PORTTF_PORTTF6 (0x40) -#define MCF_GPIO_PORTTF_PORTTF7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTG */ -#define MCF_GPIO_PORTTG_PORTTG0 (0x01) -#define MCF_GPIO_PORTTG_PORTTG1 (0x02) -#define MCF_GPIO_PORTTG_PORTTG2 (0x04) -#define MCF_GPIO_PORTTG_PORTTG3 (0x08) -#define MCF_GPIO_PORTTG_PORTTG4 (0x10) -#define MCF_GPIO_PORTTG_PORTTG5 (0x20) -#define MCF_GPIO_PORTTG_PORTTG6 (0x40) -#define MCF_GPIO_PORTTG_PORTTG7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTH */ -#define MCF_GPIO_PORTTH_PORTTH0 (0x01) -#define MCF_GPIO_PORTTH_PORTTH1 (0x02) -#define MCF_GPIO_PORTTH_PORTTH2 (0x04) -#define MCF_GPIO_PORTTH_PORTTH3 (0x08) -#define MCF_GPIO_PORTTH_PORTTH4 (0x10) -#define MCF_GPIO_PORTTH_PORTTH5 (0x20) -#define MCF_GPIO_PORTTH_PORTTH6 (0x40) -#define MCF_GPIO_PORTTH_PORTTH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTI */ -#define MCF_GPIO_PORTTI_PORTTI0 (0x01) -#define MCF_GPIO_PORTTI_PORTTI1 (0x02) -#define MCF_GPIO_PORTTI_PORTTI2 (0x04) -#define MCF_GPIO_PORTTI_PORTTI3 (0x08) -#define MCF_GPIO_PORTTI_PORTTI4 (0x10) -#define MCF_GPIO_PORTTI_PORTTI5 (0x20) -#define MCF_GPIO_PORTTI_PORTTI6 (0x40) -#define MCF_GPIO_PORTTI_PORTTI7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTUA */ -#define MCF_GPIO_PORTUA_PORTUA0 (0x01) -#define MCF_GPIO_PORTUA_PORTUA1 (0x02) -#define MCF_GPIO_PORTUA_PORTUA2 (0x04) -#define MCF_GPIO_PORTUA_PORTUA3 (0x08) -#define MCF_GPIO_PORTUA_PORTUA4 (0x10) -#define MCF_GPIO_PORTUA_PORTUA5 (0x20) -#define MCF_GPIO_PORTUA_PORTUA6 (0x40) -#define MCF_GPIO_PORTUA_PORTUA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTUB */ -#define MCF_GPIO_PORTUB_PORTUB0 (0x01) -#define MCF_GPIO_PORTUB_PORTUB1 (0x02) -#define MCF_GPIO_PORTUB_PORTUB2 (0x04) -#define MCF_GPIO_PORTUB_PORTUB3 (0x08) -#define MCF_GPIO_PORTUB_PORTUB4 (0x10) -#define MCF_GPIO_PORTUB_PORTUB5 (0x20) -#define MCF_GPIO_PORTUB_PORTUB6 (0x40) -#define MCF_GPIO_PORTUB_PORTUB7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTUC */ -#define MCF_GPIO_PORTUC_PORTUC0 (0x01) -#define MCF_GPIO_PORTUC_PORTUC1 (0x02) -#define MCF_GPIO_PORTUC_PORTUC2 (0x04) -#define MCF_GPIO_PORTUC_PORTUC3 (0x08) -#define MCF_GPIO_PORTUC_PORTUC4 (0x10) -#define MCF_GPIO_PORTUC_PORTUC5 (0x20) -#define MCF_GPIO_PORTUC_PORTUC6 (0x40) -#define MCF_GPIO_PORTUC_PORTUC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTDD */ -#define MCF_GPIO_PORTDD_PORTDD0 (0x01) -#define MCF_GPIO_PORTDD_PORTDD1 (0x02) -#define MCF_GPIO_PORTDD_PORTDD2 (0x04) -#define MCF_GPIO_PORTDD_PORTDD3 (0x08) -#define MCF_GPIO_PORTDD_PORTDD4 (0x10) -#define MCF_GPIO_PORTDD_PORTDD5 (0x20) -#define MCF_GPIO_PORTDD_PORTDD6 (0x40) -#define MCF_GPIO_PORTDD_PORTDD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTLD */ -#define MCF_GPIO_PORTLD_PORTLD0 (0x01) -#define MCF_GPIO_PORTLD_PORTLD1 (0x02) -#define MCF_GPIO_PORTLD_PORTLD2 (0x04) -#define MCF_GPIO_PORTLD_PORTLD3 (0x08) -#define MCF_GPIO_PORTLD_PORTLD4 (0x10) -#define MCF_GPIO_PORTLD_PORTLD5 (0x20) -#define MCF_GPIO_PORTLD_PORTLD6 (0x40) -#define MCF_GPIO_PORTLD_PORTLD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTGP */ -#define MCF_GPIO_PORTGP_PORTGP0 (0x01) -#define MCF_GPIO_PORTGP_PORTGP1 (0x02) -#define MCF_GPIO_PORTGP_PORTGP2 (0x04) -#define MCF_GPIO_PORTGP_PORTGP3 (0x08) -#define MCF_GPIO_PORTGP_PORTGP4 (0x10) -#define MCF_GPIO_PORTGP_PORTGP5 (0x20) -#define MCF_GPIO_PORTGP_PORTGP6 (0x40) -#define MCF_GPIO_PORTGP_PORTGP7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRNQ */ -#define MCF_GPIO_DDRNQ_DDRNQ0 (0x01) -#define MCF_GPIO_DDRNQ_DDRNQ1 (0x02) -#define MCF_GPIO_DDRNQ_DDRNQ2 (0x04) -#define MCF_GPIO_DDRNQ_DDRNQ3 (0x08) -#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10) -#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20) -#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40) -#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRAN */ -#define MCF_GPIO_DDRAN_DDRAN0 (0x01) -#define MCF_GPIO_DDRAN_DDRAN1 (0x02) -#define MCF_GPIO_DDRAN_DDRAN2 (0x04) -#define MCF_GPIO_DDRAN_DDRAN3 (0x08) -#define MCF_GPIO_DDRAN_DDRAN4 (0x10) -#define MCF_GPIO_DDRAN_DDRAN5 (0x20) -#define MCF_GPIO_DDRAN_DDRAN6 (0x40) -#define MCF_GPIO_DDRAN_DDRAN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRAS */ -#define MCF_GPIO_DDRAS_DDRAS0 (0x01) -#define MCF_GPIO_DDRAS_DDRAS1 (0x02) -#define MCF_GPIO_DDRAS_DDRAS2 (0x04) -#define MCF_GPIO_DDRAS_DDRAS3 (0x08) -#define MCF_GPIO_DDRAS_DDRAS4 (0x10) -#define MCF_GPIO_DDRAS_DDRAS5 (0x20) -#define MCF_GPIO_DDRAS_DDRAS6 (0x40) -#define MCF_GPIO_DDRAS_DDRAS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRQS */ -#define MCF_GPIO_DDRQS_DDRQS0 (0x01) -#define MCF_GPIO_DDRQS_DDRQS1 (0x02) -#define MCF_GPIO_DDRQS_DDRQS2 (0x04) -#define MCF_GPIO_DDRQS_DDRQS3 (0x08) -#define MCF_GPIO_DDRQS_DDRQS4 (0x10) -#define MCF_GPIO_DDRQS_DDRQS5 (0x20) -#define MCF_GPIO_DDRQS_DDRQS6 (0x40) -#define MCF_GPIO_DDRQS_DDRQS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTA */ -#define MCF_GPIO_DDRTA_DDRTA0 (0x01) -#define MCF_GPIO_DDRTA_DDRTA1 (0x02) -#define MCF_GPIO_DDRTA_DDRTA2 (0x04) -#define MCF_GPIO_DDRTA_DDRTA3 (0x08) -#define MCF_GPIO_DDRTA_DDRTA4 (0x10) -#define MCF_GPIO_DDRTA_DDRTA5 (0x20) -#define MCF_GPIO_DDRTA_DDRTA6 (0x40) -#define MCF_GPIO_DDRTA_DDRTA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTC */ -#define MCF_GPIO_DDRTC_DDRTC0 (0x01) -#define MCF_GPIO_DDRTC_DDRTC1 (0x02) -#define MCF_GPIO_DDRTC_DDRTC2 (0x04) -#define MCF_GPIO_DDRTC_DDRTC3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_DDRTD */ -#define MCF_GPIO_DDRTD_DDRTD0 (0x01) -#define MCF_GPIO_DDRTD_DDRTD1 (0x02) -#define MCF_GPIO_DDRTD_DDRTD2 (0x04) -#define MCF_GPIO_DDRTD_DDRTD3 (0x08) -#define MCF_GPIO_DDRTD_DDRTD4 (0x10) -#define MCF_GPIO_DDRTD_DDRTD5 (0x20) -#define MCF_GPIO_DDRTD_DDRTD6 (0x40) -#define MCF_GPIO_DDRTD_DDRTD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTE */ -#define MCF_GPIO_DDRTE_DDRTE0 (0x01) -#define MCF_GPIO_DDRTE_DDRTE1 (0x02) -#define MCF_GPIO_DDRTE_DDRTE2 (0x04) -#define MCF_GPIO_DDRTE_DDRTE3 (0x08) -#define MCF_GPIO_DDRTE_DDRTE4 (0x10) -#define MCF_GPIO_DDRTE_DDRTE5 (0x20) -#define MCF_GPIO_DDRTE_DDRTE6 (0x40) -#define MCF_GPIO_DDRTE_DDRTE7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTF */ -#define MCF_GPIO_DDRTF_DDRTF0 (0x01) -#define MCF_GPIO_DDRTF_DDRTF1 (0x02) -#define MCF_GPIO_DDRTF_DDRTF2 (0x04) -#define MCF_GPIO_DDRTF_DDRTF3 (0x08) -#define MCF_GPIO_DDRTF_DDRTF4 (0x10) -#define MCF_GPIO_DDRTF_DDRTF5 (0x20) -#define MCF_GPIO_DDRTF_DDRTF6 (0x40) -#define MCF_GPIO_DDRTF_DDRTF7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTG */ -#define MCF_GPIO_DDRTG_DDRTG0 (0x01) -#define MCF_GPIO_DDRTG_DDRTG1 (0x02) -#define MCF_GPIO_DDRTG_DDRTG2 (0x04) -#define MCF_GPIO_DDRTG_DDRTG3 (0x08) -#define MCF_GPIO_DDRTG_DDRTG4 (0x10) -#define MCF_GPIO_DDRTG_DDRTG5 (0x20) -#define MCF_GPIO_DDRTG_DDRTG6 (0x40) -#define MCF_GPIO_DDRTG_DDRTG7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTH */ -#define MCF_GPIO_DDRTH_DDRTH0 (0x01) -#define MCF_GPIO_DDRTH_DDRTH1 (0x02) -#define MCF_GPIO_DDRTH_DDRTH2 (0x04) -#define MCF_GPIO_DDRTH_DDRTH3 (0x08) -#define MCF_GPIO_DDRTH_DDRTH4 (0x10) -#define MCF_GPIO_DDRTH_DDRTH5 (0x20) -#define MCF_GPIO_DDRTH_DDRTH6 (0x40) -#define MCF_GPIO_DDRTH_DDRTH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTI */ -#define MCF_GPIO_DDRTI_DDRTI0 (0x01) -#define MCF_GPIO_DDRTI_DDRTI1 (0x02) -#define MCF_GPIO_DDRTI_DDRTI2 (0x04) -#define MCF_GPIO_DDRTI_DDRTI3 (0x08) -#define MCF_GPIO_DDRTI_DDRTI4 (0x10) -#define MCF_GPIO_DDRTI_DDRTI5 (0x20) -#define MCF_GPIO_DDRTI_DDRTI6 (0x40) -#define MCF_GPIO_DDRTI_DDRTI7 (0x80) - -/* Bit definiTJons and macros for MCF_GPIO_DDRTJ */ -#define MCF_GPIO_DDRTJ_DDRTJ0 (0x01) -#define MCF_GPIO_DDRTJ_DDRTJ1 (0x02) -#define MCF_GPIO_DDRTJ_DDRTJ2 (0x04) -#define MCF_GPIO_DDRTJ_DDRTJ3 (0x08) -#define MCF_GPIO_DDRTJ_DDRTJ4 (0x10) -#define MCF_GPIO_DDRTJ_DDRTJ5 (0x20) -#define MCF_GPIO_DDRTJ_DDRTJ6 (0x40) -#define MCF_GPIO_DDRTJ_DDRTJ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRUA */ -#define MCF_GPIO_DDRUA_DDRUA0 (0x01) -#define MCF_GPIO_DDRUA_DDRUA1 (0x02) -#define MCF_GPIO_DDRUA_DDRUA2 (0x04) -#define MCF_GPIO_DDRUA_DDRUA3 (0x08) -#define MCF_GPIO_DDRUA_DDRUA4 (0x10) -#define MCF_GPIO_DDRUA_DDRUA5 (0x20) -#define MCF_GPIO_DDRUA_DDRUA6 (0x40) -#define MCF_GPIO_DDRUA_DDRUA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRUB */ -#define MCF_GPIO_DDRUB_DDRUB0 (0x01) -#define MCF_GPIO_DDRUB_DDRUB1 (0x02) -#define MCF_GPIO_DDRUB_DDRUB2 (0x04) -#define MCF_GPIO_DDRUB_DDRUB3 (0x08) -#define MCF_GPIO_DDRUB_DDRUB4 (0x10) -#define MCF_GPIO_DDRUB_DDRUB5 (0x20) -#define MCF_GPIO_DDRUB_DDRUB6 (0x40) -#define MCF_GPIO_DDRUB_DDRUB7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRUC */ -#define MCF_GPIO_DDRUC_DDRUC0 (0x01) -#define MCF_GPIO_DDRUC_DDRUC1 (0x02) -#define MCF_GPIO_DDRUC_DDRUC2 (0x04) -#define MCF_GPIO_DDRUC_DDRUC3 (0x08) -#define MCF_GPIO_DDRUC_DDRUC4 (0x10) -#define MCF_GPIO_DDRUC_DDRUC5 (0x20) -#define MCF_GPIO_DDRUC_DDRUC6 (0x40) -#define MCF_GPIO_DDRUC_DDRUC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRDD */ -#define MCF_GPIO_DDRDD_DDRDD0 (0x01) -#define MCF_GPIO_DDRDD_DDRDD1 (0x02) -#define MCF_GPIO_DDRDD_DDRDD2 (0x04) -#define MCF_GPIO_DDRDD_DDRDD3 (0x08) -#define MCF_GPIO_DDRDD_DDRDD4 (0x10) -#define MCF_GPIO_DDRDD_DDRDD5 (0x20) -#define MCF_GPIO_DDRDD_DDRDD6 (0x40) -#define MCF_GPIO_DDRDD_DDRDD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRLD */ -#define MCF_GPIO_DDRLD_DDRLD0 (0x01) -#define MCF_GPIO_DDRLD_DDRLD1 (0x02) -#define MCF_GPIO_DDRLD_DDRLD2 (0x04) -#define MCF_GPIO_DDRLD_DDRLD3 (0x08) -#define MCF_GPIO_DDRLD_DDRLD4 (0x10) -#define MCF_GPIO_DDRLD_DDRLD5 (0x20) -#define MCF_GPIO_DDRLD_DDRLD6 (0x40) -#define MCF_GPIO_DDRLD_DDRLD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRGP */ -#define MCF_GPIO_DDRGP_DDRGP0 (0x01) -#define MCF_GPIO_DDRGP_DDRGP1 (0x02) -#define MCF_GPIO_DDRGP_DDRGP2 (0x04) -#define MCF_GPIO_DDRGP_DDRGP3 (0x08) -#define MCF_GPIO_DDRGP_DDRGP4 (0x10) -#define MCF_GPIO_DDRGP_DDRGP5 (0x20) -#define MCF_GPIO_DDRGP_DDRGP6 (0x40) -#define MCF_GPIO_DDRGP_DDRGP7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETNQ */ -#define MCF_GPIO_SETNQ_SETNQ0 (0x01) -#define MCF_GPIO_SETNQ_SETNQ1 (0x02) -#define MCF_GPIO_SETNQ_SETNQ2 (0x04) -#define MCF_GPIO_SETNQ_SETNQ3 (0x08) -#define MCF_GPIO_SETNQ_SETNQ4 (0x10) -#define MCF_GPIO_SETNQ_SETNQ5 (0x20) -#define MCF_GPIO_SETNQ_SETNQ6 (0x40) -#define MCF_GPIO_SETNQ_SETNQ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETAN */ -#define MCF_GPIO_SETAN_SETAN0 (0x01) -#define MCF_GPIO_SETAN_SETAN1 (0x02) -#define MCF_GPIO_SETAN_SETAN2 (0x04) -#define MCF_GPIO_SETAN_SETAN3 (0x08) -#define MCF_GPIO_SETAN_SETAN4 (0x10) -#define MCF_GPIO_SETAN_SETAN5 (0x20) -#define MCF_GPIO_SETAN_SETAN6 (0x40) -#define MCF_GPIO_SETAN_SETAN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETAS */ -#define MCF_GPIO_SETAS_SETAS0 (0x01) -#define MCF_GPIO_SETAS_SETAS1 (0x02) -#define MCF_GPIO_SETAS_SETAS2 (0x04) -#define MCF_GPIO_SETAS_SETAS3 (0x08) -#define MCF_GPIO_SETAS_SETAS4 (0x10) -#define MCF_GPIO_SETAS_SETAS5 (0x20) -#define MCF_GPIO_SETAS_SETAS6 (0x40) -#define MCF_GPIO_SETAS_SETAS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETQS */ -#define MCF_GPIO_SETQS_SETQS0 (0x01) -#define MCF_GPIO_SETQS_SETQS1 (0x02) -#define MCF_GPIO_SETQS_SETQS2 (0x04) -#define MCF_GPIO_SETQS_SETQS3 (0x08) -#define MCF_GPIO_SETQS_SETQS4 (0x10) -#define MCF_GPIO_SETQS_SETQS5 (0x20) -#define MCF_GPIO_SETQS_SETQS6 (0x40) -#define MCF_GPIO_SETQS_SETQS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETTA */ -#define MCF_GPIO_SETTA_SETTA0 (0x01) -#define MCF_GPIO_SETTA_SETTA1 (0x02) -#define MCF_GPIO_SETTA_SETTA2 (0x04) -#define MCF_GPIO_SETTA_SETTA3 (0x08) -#define MCF_GPIO_SETTA_SETTA4 (0x10) -#define MCF_GPIO_SETTA_SETTA5 (0x20) -#define MCF_GPIO_SETTA_SETTA6 (0x40) -#define MCF_GPIO_SETTA_SETTA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETTC */ -#define MCF_GPIO_SETTC_SETTC0 (0x01) -#define MCF_GPIO_SETTC_SETTC1 (0x02) -#define MCF_GPIO_SETTC_SETTC2 (0x04) -#define MCF_GPIO_SETTC_SETTC3 (0x08) -#define MCF_GPIO_SETTC_SETTC4 (0x10) -#define MCF_GPIO_SETTC_SETTC5 (0x20) -#define MCF_GPIO_SETTC_SETTC6 (0x40) -#define MCF_GPIO_SETTC_SETTC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETTD */ -#define MCF_GPIO_SETTD_SETTD0 (0x01) -#define MCF_GPIO_SETTD_SETTD1 (0x02) -#define MCF_GPIO_SETTD_SETTD2 (0x04) -#define MCF_GPIO_SETTD_SETTD3 (0x08) -#define MCF_GPIO_SETTD_SETTD4 (0x10) -#define MCF_GPIO_SETTD_SETTD5 (0x20) -#define MCF_GPIO_SETTD_SETTD6 (0x40) -#define MCF_GPIO_SETTD_SETTD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETUA */ -#define MCF_GPIO_SETUA_SETUA0 (0x01) -#define MCF_GPIO_SETUA_SETUA1 (0x02) -#define MCF_GPIO_SETUA_SETUA2 (0x04) -#define MCF_GPIO_SETUA_SETUA3 (0x08) -#define MCF_GPIO_SETUA_SETUA4 (0x10) -#define MCF_GPIO_SETUA_SETUA5 (0x20) -#define MCF_GPIO_SETUA_SETUA6 (0x40) -#define MCF_GPIO_SETUA_SETUA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETUB */ -#define MCF_GPIO_SETUB_SETUB0 (0x01) -#define MCF_GPIO_SETUB_SETUB1 (0x02) -#define MCF_GPIO_SETUB_SETUB2 (0x04) -#define MCF_GPIO_SETUB_SETUB3 (0x08) -#define MCF_GPIO_SETUB_SETUB4 (0x10) -#define MCF_GPIO_SETUB_SETUB5 (0x20) -#define MCF_GPIO_SETUB_SETUB6 (0x40) -#define MCF_GPIO_SETUB_SETUB7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETUC */ -#define MCF_GPIO_SETUC_SETUC0 (0x01) -#define MCF_GPIO_SETUC_SETUC1 (0x02) -#define MCF_GPIO_SETUC_SETUC2 (0x04) -#define MCF_GPIO_SETUC_SETUC3 (0x08) -#define MCF_GPIO_SETUC_SETUC4 (0x10) -#define MCF_GPIO_SETUC_SETUC5 (0x20) -#define MCF_GPIO_SETUC_SETUC6 (0x40) -#define MCF_GPIO_SETUC_SETUC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETDD */ -#define MCF_GPIO_SETDD_SETDD0 (0x01) -#define MCF_GPIO_SETDD_SETDD1 (0x02) -#define MCF_GPIO_SETDD_SETDD2 (0x04) -#define MCF_GPIO_SETDD_SETDD3 (0x08) -#define MCF_GPIO_SETDD_SETDD4 (0x10) -#define MCF_GPIO_SETDD_SETDD5 (0x20) -#define MCF_GPIO_SETDD_SETDD6 (0x40) -#define MCF_GPIO_SETDD_SETDD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETLD */ -#define MCF_GPIO_SETLD_SETLD0 (0x01) -#define MCF_GPIO_SETLD_SETLD1 (0x02) -#define MCF_GPIO_SETLD_SETLD2 (0x04) -#define MCF_GPIO_SETLD_SETLD3 (0x08) -#define MCF_GPIO_SETLD_SETLD4 (0x10) -#define MCF_GPIO_SETLD_SETLD5 (0x20) -#define MCF_GPIO_SETLD_SETLD6 (0x40) -#define MCF_GPIO_SETLD_SETLD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETGP */ -#define MCF_GPIO_SETGP_SETGP0 (0x01) -#define MCF_GPIO_SETGP_SETGP1 (0x02) -#define MCF_GPIO_SETGP_SETGP2 (0x04) -#define MCF_GPIO_SETGP_SETGP3 (0x08) -#define MCF_GPIO_SETGP_SETGP4 (0x10) -#define MCF_GPIO_SETGP_SETGP5 (0x20) -#define MCF_GPIO_SETGP_SETGP6 (0x40) -#define MCF_GPIO_SETGP_SETGP7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRNQ */ -#define MCF_GPIO_CLRNQ_CLRNQ0 (0x01) -#define MCF_GPIO_CLRNQ_CLRNQ1 (0x02) -#define MCF_GPIO_CLRNQ_CLRNQ2 (0x04) -#define MCF_GPIO_CLRNQ_CLRNQ3 (0x08) -#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10) -#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20) -#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40) -#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRAN */ -#define MCF_GPIO_CLRAN_CLRAN0 (0x01) -#define MCF_GPIO_CLRAN_CLRAN1 (0x02) -#define MCF_GPIO_CLRAN_CLRAN2 (0x04) -#define MCF_GPIO_CLRAN_CLRAN3 (0x08) -#define MCF_GPIO_CLRAN_CLRAN4 (0x10) -#define MCF_GPIO_CLRAN_CLRAN5 (0x20) -#define MCF_GPIO_CLRAN_CLRAN6 (0x40) -#define MCF_GPIO_CLRAN_CLRAN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRAS */ -#define MCF_GPIO_CLRAS_CLRAS0 (0x01) -#define MCF_GPIO_CLRAS_CLRAS1 (0x02) -#define MCF_GPIO_CLRAS_CLRAS2 (0x04) -#define MCF_GPIO_CLRAS_CLRAS3 (0x08) -#define MCF_GPIO_CLRAS_CLRAS4 (0x10) -#define MCF_GPIO_CLRAS_CLRAS5 (0x20) -#define MCF_GPIO_CLRAS_CLRAS6 (0x40) -#define MCF_GPIO_CLRAS_CLRAS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRQS */ -#define MCF_GPIO_CLRQS_CLRQS0 (0x01) -#define MCF_GPIO_CLRQS_CLRQS1 (0x02) -#define MCF_GPIO_CLRQS_CLRQS2 (0x04) -#define MCF_GPIO_CLRQS_CLRQS3 (0x08) -#define MCF_GPIO_CLRQS_CLRQS4 (0x10) -#define MCF_GPIO_CLRQS_CLRQS5 (0x20) -#define MCF_GPIO_CLRQS_CLRQS6 (0x40) -#define MCF_GPIO_CLRQS_CLRQS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRTA */ -#define MCF_GPIO_CLRTA_CLRTA0 (0x01) -#define MCF_GPIO_CLRTA_CLRTA1 (0x02) -#define MCF_GPIO_CLRTA_CLRTA2 (0x04) -#define MCF_GPIO_CLRTA_CLRTA3 (0x08) -#define MCF_GPIO_CLRTA_CLRTA4 (0x10) -#define MCF_GPIO_CLRTA_CLRTA5 (0x20) -#define MCF_GPIO_CLRTA_CLRTA6 (0x40) -#define MCF_GPIO_CLRTA_CLRTA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRTC */ -#define MCF_GPIO_CLRTC_CLRTC0 (0x01) -#define MCF_GPIO_CLRTC_CLRTC1 (0x02) -#define MCF_GPIO_CLRTC_CLRTC2 (0x04) -#define MCF_GPIO_CLRTC_CLRTC3 (0x08) -#define MCF_GPIO_CLRTC_CLRTC4 (0x10) -#define MCF_GPIO_CLRTC_CLRTC5 (0x20) -#define MCF_GPIO_CLRTC_CLRTC6 (0x40) -#define MCF_GPIO_CLRTC_CLRTC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRTD */ -#define MCF_GPIO_CLRTD_CLRTD0 (0x01) -#define MCF_GPIO_CLRTD_CLRTD1 (0x02) -#define MCF_GPIO_CLRTD_CLRTD2 (0x04) -#define MCF_GPIO_CLRTD_CLRTD3 (0x08) -#define MCF_GPIO_CLRTD_CLRTD4 (0x10) -#define MCF_GPIO_CLRTD_CLRTD5 (0x20) -#define MCF_GPIO_CLRTD_CLRTD6 (0x40) -#define MCF_GPIO_CLRTD_CLRTD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRUA */ -#define MCF_GPIO_CLRUA_CLRUA0 (0x01) -#define MCF_GPIO_CLRUA_CLRUA1 (0x02) -#define MCF_GPIO_CLRUA_CLRUA2 (0x04) -#define MCF_GPIO_CLRUA_CLRUA3 (0x08) -#define MCF_GPIO_CLRUA_CLRUA4 (0x10) -#define MCF_GPIO_CLRUA_CLRUA5 (0x20) -#define MCF_GPIO_CLRUA_CLRUA6 (0x40) -#define MCF_GPIO_CLRUA_CLRUA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRUB */ -#define MCF_GPIO_CLRUB_CLRUB0 (0x01) -#define MCF_GPIO_CLRUB_CLRUB1 (0x02) -#define MCF_GPIO_CLRUB_CLRUB2 (0x04) -#define MCF_GPIO_CLRUB_CLRUB3 (0x08) -#define MCF_GPIO_CLRUB_CLRUB4 (0x10) -#define MCF_GPIO_CLRUB_CLRUB5 (0x20) -#define MCF_GPIO_CLRUB_CLRUB6 (0x40) -#define MCF_GPIO_CLRUB_CLRUB7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRUC */ -#define MCF_GPIO_CLRUC_CLRUC0 (0x01) -#define MCF_GPIO_CLRUC_CLRUC1 (0x02) -#define MCF_GPIO_CLRUC_CLRUC2 (0x04) -#define MCF_GPIO_CLRUC_CLRUC3 (0x08) -#define MCF_GPIO_CLRUC_CLRUC4 (0x10) -#define MCF_GPIO_CLRUC_CLRUC5 (0x20) -#define MCF_GPIO_CLRUC_CLRUC6 (0x40) -#define MCF_GPIO_CLRUC_CLRUC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRDD */ -#define MCF_GPIO_CLRDD_CLRDD0 (0x01) -#define MCF_GPIO_CLRDD_CLRDD1 (0x02) -#define MCF_GPIO_CLRDD_CLRDD2 (0x04) -#define MCF_GPIO_CLRDD_CLRDD3 (0x08) -#define MCF_GPIO_CLRDD_CLRDD4 (0x10) -#define MCF_GPIO_CLRDD_CLRDD5 (0x20) -#define MCF_GPIO_CLRDD_CLRDD6 (0x40) -#define MCF_GPIO_CLRDD_CLRDD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRLD */ -#define MCF_GPIO_CLRLD_CLRLD0 (0x01) -#define MCF_GPIO_CLRLD_CLRLD1 (0x02) -#define MCF_GPIO_CLRLD_CLRLD2 (0x04) -#define MCF_GPIO_CLRLD_CLRLD3 (0x08) -#define MCF_GPIO_CLRLD_CLRLD4 (0x10) -#define MCF_GPIO_CLRLD_CLRLD5 (0x20) -#define MCF_GPIO_CLRLD_CLRLD6 (0x40) -#define MCF_GPIO_CLRLD_CLRLD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRGP */ -#define MCF_GPIO_CLRGP_CLRGP0 (0x01) -#define MCF_GPIO_CLRGP_CLRGP1 (0x02) -#define MCF_GPIO_CLRGP_CLRGP2 (0x04) -#define MCF_GPIO_CLRGP_CLRGP3 (0x08) -#define MCF_GPIO_CLRGP_CLRGP4 (0x10) -#define MCF_GPIO_CLRGP_CLRGP5 (0x20) -#define MCF_GPIO_CLRGP_CLRGP6 (0x40) -#define MCF_GPIO_CLRGP_CLRGP7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PTIPAR */ -#define MCF_GPIO_PTIPAR_PTIPAR0 (0x01) -#define MCF_GPIO_PTIPAR_PTIPAR1 (0x02) -#define MCF_GPIO_PTIPAR_PTIPAR2 (0x04) -#define MCF_GPIO_PTIPAR_PTIPAR3 (0x08) -#define MCF_GPIO_PTIPAR_PTIPAR4 (0x10) -#define MCF_GPIO_PTIPAR_PTIPAR5 (0x20) -#define MCF_GPIO_PTIPAR_PTIPAR6 (0x40) -#define MCF_GPIO_PTIPAR_PTIPAR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PTJPAR */ -#define MCF_GPIO_PTJPAR_PTJPAR0 (0x01) -#define MCF_GPIO_PTJPAR_PTJPAR1 (0x02) -#define MCF_GPIO_PTJPAR_PTJPAR2 (0x04) -#define MCF_GPIO_PTJPAR_PTJPAR3 (0x08) -#define MCF_GPIO_PTJPAR_PTJPAR4 (0x10) -#define MCF_GPIO_PTJPAR_PTJPAR5 (0x20) -#define MCF_GPIO_PTJPAR_PTJPAR6 (0x40) -#define MCF_GPIO_PTJPAR_PTJPAR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PNQPAR */ -#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x0003)<<14) -#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x0004) -#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x0010) -#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x0040) -#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x0100) -#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x0400) -#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000) -#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000) -#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x0008) -#define MCF_GPIO_PNQPAR_IRQ1_PWM1 (0x000C) - -/* Bit definitions and macros for MCF_GPIO_PANPAR */ -#define MCF_GPIO_PANPAR_PANPAR0 (0x01) -#define MCF_GPIO_PANPAR_PANPAR1 (0x02) -#define MCF_GPIO_PANPAR_PANPAR2 (0x04) -#define MCF_GPIO_PANPAR_PANPAR3 (0x08) -#define MCF_GPIO_PANPAR_PANPAR4 (0x10) -#define MCF_GPIO_PANPAR_PANPAR5 (0x20) -#define MCF_GPIO_PANPAR_PANPAR6 (0x40) -#define MCF_GPIO_PANPAR_PANPAR7 (0x80) -#define MCF_GPIO_PANPAR_AN0_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN1_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN2_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN3_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN4_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN5_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN6_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN7_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN0_AN0 (0x01) -#define MCF_GPIO_PANPAR_AN1_AN1 (0x02) -#define MCF_GPIO_PANPAR_AN2_AN2 (0x04) -#define MCF_GPIO_PANPAR_AN3_AN3 (0x08) -#define MCF_GPIO_PANPAR_AN4_AN4 (0x10) -#define MCF_GPIO_PANPAR_AN5_AN5 (0x20) -#define MCF_GPIO_PANPAR_AN6_AN6 (0x40) -#define MCF_GPIO_PANPAR_AN7_AN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PASPAR */ -#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PASPAR_PASPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PASPAR_SCL_GPIO (0x00) -#define MCF_GPIO_PASPAR_SDA_GPIO (0x00) -#define MCF_GPIO_PASPAR_SYNCA_GPIO (0x00) -#define MCF_GPIO_PASPAR_SYNCB_GPIO (0x00) -#define MCF_GPIO_PASPAR_SCL_SCL (0x01) -#define MCF_GPIO_PASPAR_SDA_SDA (0x04) -#define MCF_GPIO_PASPAR_SYNCA_SYNCA (0x10) -#define MCF_GPIO_PASPAR_SYNCB_SYNCB (0x40) -#define MCF_GPIO_PASPAR_SCL_CANTX (0x02) -#define MCF_GPIO_PASPAR_SDA_CANRX (0x08) -#define MCF_GPIO_PASPAR_SYNCA_CANRX (0x20) -#define MCF_GPIO_PASPAR_SYNCB_CANTX (0x80) -#define MCF_GPIO_PASPAR_SCL_TXD2 (0x30) -#define MCF_GPIO_PASPAR_SDA_RXD2 (0xC0) - -/* Bit definitions and macros for MCF_GPIO_PQSPAR */ -#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x0003)<<12) -#define MCF_GPIO_PQSPAR_DOUT_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_DIN_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_SCK_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_CS0_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_CS1_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_CS2_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_CS3_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_DOUT_DOUT (0x0001) -#define MCF_GPIO_PQSPAR_DIN_DIN (0x0004) -#define MCF_GPIO_PQSPAR_SCK_SCK (0x0010) -#define MCF_GPIO_PQSPAR_CS0_CS0 (0x0040) -#define MCF_GPIO_PQSPAR_CS1_CS1 (0x0100) -#define MCF_GPIO_PQSPAR_CS2_CS2 (0x0400) -#define MCF_GPIO_PQSPAR_CS3_CS3 (0x1000) -#define MCF_GPIO_PQSPAR_DOUT_CANTX (0x0002) -#define MCF_GPIO_PQSPAR_DIN_CANRX (0x0008) -#define MCF_GPIO_PQSPAR_SCK_SCL (0x0020) -#define MCF_GPIO_PQSPAR_CS0_SDA (0x0080) -#define MCF_GPIO_PQSPAR_CS3_SYNCA (0x2000) -#define MCF_GPIO_PQSPAR_DOUT_TXD1 (0x0003) -#define MCF_GPIO_PQSPAR_DIN_RXD1 (0x000C) -#define MCF_GPIO_PQSPAR_SCK_RTS1 (0x0030) -#define MCF_GPIO_PQSPAR_CS0_CTS1 (0x00C0) -#define MCF_GPIO_PQSPAR_CS3_SYNCB (0x3000) - -/* Bit definitions and macros for MCF_GPIO_PTAPAR */ -#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PTAPAR_ICOC0_GPIO (0x00) -#define MCF_GPIO_PTAPAR_ICOC1_GPIO (0x00) -#define MCF_GPIO_PTAPAR_ICOC2_GPIO (0x00) -#define MCF_GPIO_PTAPAR_ICOC3_GPIO (0x00) -#define MCF_GPIO_PTAPAR_ICOC0_ICOC0 (0x01) -#define MCF_GPIO_PTAPAR_ICOC1_ICOC1 (0x04) -#define MCF_GPIO_PTAPAR_ICOC2_ICOC2 (0x10) -#define MCF_GPIO_PTAPAR_ICOC3_ICOC3 (0x40) -#define MCF_GPIO_PTAPAR_ICOC0_PWM1 (0x02) -#define MCF_GPIO_PTAPAR_ICOC1_PWM3 (0x08) -#define MCF_GPIO_PTAPAR_ICOC2_PWM5 (0x20) -#define MCF_GPIO_PTAPAR_ICOC3_PWM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PTCPAR */ -#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PTCPAR_TIN0_GPIO (0x00) -#define MCF_GPIO_PTCPAR_TIN1_GPIO (0x00) -#define MCF_GPIO_PTCPAR_TIN2_GPIO (0x00) -#define MCF_GPIO_PTCPAR_TIN3_GPIO (0x00) -#define MCF_GPIO_PTCPAR_TIN0_TIN0 (0x01) -#define MCF_GPIO_PTCPAR_TIN1_TIN1 (0x04) -#define MCF_GPIO_PTCPAR_TIN2_TIN2 (0x10) -#define MCF_GPIO_PTCPAR_TIN3_TIN3 (0x40) -#define MCF_GPIO_PTCPAR_TIN0_TOUT0 (0x02) -#define MCF_GPIO_PTCPAR_TIN1_TOUT1 (0x08) -#define MCF_GPIO_PTCPAR_TIN2_TOUT2 (0x20) -#define MCF_GPIO_PTCPAR_TIN3_TOUT3 (0x80) -#define MCF_GPIO_PTCPAR_TIN0_PWM0 (0x03) -#define MCF_GPIO_PTCPAR_TIN1_PWM2 (0x0C) -#define MCF_GPIO_PTCPAR_TIN2_PWM4 (0x30) -#define MCF_GPIO_PTCPAR_TIN3_PWM6 (0xC0) - -/* Bit definitions and macros for MCF_GPIO_PTDPAR */ -#define MCF_GPIO_PTDPAR_PTDPAR0 (0x01) -#define MCF_GPIO_PTDPAR_PTDPAR1 (0x02) -#define MCF_GPIO_PTDPAR_PTDPAR2 (0x04) -#define MCF_GPIO_PTDPAR_PTDPAR3 (0x08) -#define MCF_GPIO_PTDPAR_PWM1_GPIO (0x00) -#define MCF_GPIO_PTDPAR_PWM3_GPIO (0x00) -#define MCF_GPIO_PTDPAR_PWM5_GPIO (0x00) -#define MCF_GPIO_PTDPAR_PWM7_GPIO (0x00) -#define MCF_GPIO_PTDPAR_PWM1_PWM1 (0x01) -#define MCF_GPIO_PTDPAR_PWM3_PWM3 (0x02) -#define MCF_GPIO_PTDPAR_PWM5_PWM5 (0x04) -#define MCF_GPIO_PTDPAR_PWM7_PWM7 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PTEPAR */ -#define MCF_GPIO_PTEPAR_PTEPAR0 (0x01) -#define MCF_GPIO_PTEPAR_PTEPAR1 (0x02) -#define MCF_GPIO_PTEPAR_PTEPAR2 (0x04) -#define MCF_GPIO_PTEPAR_PTEPAR3 (0x08) -#define MCF_GPIO_PTEPAR_PTEPAR4 (0x10) -#define MCF_GPIO_PTEPAR_PTEPAR5 (0x20) -#define MCF_GPIO_PTEPAR_PTEPAR6 (0x40) -#define MCF_GPIO_PTEPAR_PTEPAR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PTFPAR */ -#define MCF_GPIO_PTFPAR_PTFPAR0 (0x01) -#define MCF_GPIO_PTFPAR_PTFPAR1 (0x02) -#define MCF_GPIO_PTFPAR_PTFPAR2 (0x04) -#define MCF_GPIO_PTFPAR_PTFPAR3 (0x08) -#define MCF_GPIO_PTFPAR_PTFPAR4 (0x10) -#define MCF_GPIO_PTFPAR_PTFPAR5 (0x20) -#define MCF_GPIO_PTFPAR_PTFPAR6 (0x40) -#define MCF_GPIO_PTFPAR_PTFPAR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PTGPAR */ -#define MCF_GPIO_PTGPAR_PTGPAR0 (0x01) -#define MCF_GPIO_PTGPAR_PTGPAR1 (0x02) -#define MCF_GPIO_PTGPAR_PTGPAR2 (0x04) -#define MCF_GPIO_PTGPAR_PTGPAR3 (0x08) -#define MCF_GPIO_PTGPAR_PTGPAR4 (0x10) -#define MCF_GPIO_PTGPAR_PTGPAR5 (0x20) -#define MCF_GPIO_PTGPAR_PTGPAR6 (0x40) -#define MCF_GPIO_PTGPAR_PTGPAR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PTHPAR */ -#define MCF_GPIO_PTHPAR_PTHPAR0(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PTHPAR_PTHPAR1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PTHPAR_PTHPAR2(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PTHPAR_PTHPAR3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PTHPAR_PTHPAR4(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PTHPAR_PTHPAR5(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PTHPAR_PTHPAR6(x) (((x)&0x0003)<<12) - - -/* Bit definitions and macros for MCF_GPIO_PUAPAR */ -#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PUAPAR_TXD0_GPIO (0x00) -#define MCF_GPIO_PUAPAR_RXD0_GPIO (0x00) -#define MCF_GPIO_PUAPAR_RTS0_GPIO (0x00) -#define MCF_GPIO_PUAPAR_CTS0_GPIO (0x00) -#define MCF_GPIO_PUAPAR_TXD0_TXD0 (0x01) -#define MCF_GPIO_PUAPAR_RXD0_RXD0 (0x04) -#define MCF_GPIO_PUAPAR_RTS0_RTS0 (0x10) -#define MCF_GPIO_PUAPAR_CTS0_CTS0 (0x40) -#define MCF_GPIO_PUAPAR_RTS0_CANTX (0x20) -#define MCF_GPIO_PUAPAR_CTS0_CANRX (0x80) - -/* Bit definitions and macros for MCF_GPIO_PUBPAR */ -#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PUBPAR_TXD1_GPIO (0x00) -#define MCF_GPIO_PUBPAR_RXD1_GPIO (0x00) -#define MCF_GPIO_PUBPAR_RTS1_GPIO (0x00) -#define MCF_GPIO_PUBPAR_CTS1_GPIO (0x00) -#define MCF_GPIO_PUBPAR_TXD1_TXD1 (0x01) -#define MCF_GPIO_PUBPAR_RXD1_RXD1 (0x04) -#define MCF_GPIO_PUBPAR_RTS1_RTS1 (0x10) -#define MCF_GPIO_PUBPAR_CTS1_CTS1 (0x40) -#define MCF_GPIO_PUBPAR_RTS1_SYNCB (0x20) -#define MCF_GPIO_PUBPAR_CTS1_SYNCA (0x80) -#define MCF_GPIO_PUBPAR_RTS1_TXD2 (0x30) -#define MCF_GPIO_PUBPAR_CTS1_RXD2 (0xC0) - -/* Bit definitions and macros for MCF_GPIO_PUCPAR */ -#define MCF_GPIO_PUCPAR_PUCPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PUCPAR_PUCPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PUCPAR_PUCPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PUCPAR_PUCPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PUCPAR_TXD2_GPIO (0x00) -#define MCF_GPIO_PUCPAR_RXD2_GPIO (0x00) -#define MCF_GPIO_PUCPAR_RTS2_GPIO (0x00) -#define MCF_GPIO_PUCPAR_CTS2_GPIO (0x00) -#define MCF_GPIO_PUCPAR_TXD2_TXD2 (0x01) -#define MCF_GPIO_PUCPAR_RXD2_RXD2 (0x02) -#define MCF_GPIO_PUCPAR_RTS2_RTS2 (0x04) -#define MCF_GPIO_PUCPAR_CTS2_CTS2 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDPAR */ -#define MCF_GPIO_PDDPAR_PDDPAR0 (0x01) -#define MCF_GPIO_PDDPAR_PDDPAR1 (0x02) -#define MCF_GPIO_PDDPAR_PDDPAR2 (0x04) -#define MCF_GPIO_PDDPAR_PDDPAR3 (0x08) -#define MCF_GPIO_PDDPAR_PDDPAR4 (0x10) -#define MCF_GPIO_PDDPAR_PDDPAR5 (0x20) -#define MCF_GPIO_PDDPAR_PDDPAR6 (0x40) -#define MCF_GPIO_PDDPAR_PDDPAR7 (0x80) -#define MCF_GPIO_PDDPAR_PDD0_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD1_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD2_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD3_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD4_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD5_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD6_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD7_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD0_PST0 (0x01) -#define MCF_GPIO_PDDPAR_PDD1_PST1 (0x02) -#define MCF_GPIO_PDDPAR_PDD2_PST2 (0x04) -#define MCF_GPIO_PDDPAR_PDD3_PST3 (0x08) -#define MCF_GPIO_PDDPAR_PDD4_DDATA0 (0x10) -#define MCF_GPIO_PDDPAR_PDD5_DDATA1 (0x20) -#define MCF_GPIO_PDDPAR_PDD6_DDATA2 (0x40) -#define MCF_GPIO_PDDPAR_PDD7_DDATA3 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PLDPAR */ -#define MCF_GPIO_PLDPAR_PLDPAR0 (0x01) -#define MCF_GPIO_PLDPAR_PLDPAR1 (0x02) -#define MCF_GPIO_PLDPAR_PLDPAR2 (0x04) -#define MCF_GPIO_PLDPAR_PLDPAR3 (0x08) -#define MCF_GPIO_PLDPAR_PLDPAR4 (0x10) -#define MCF_GPIO_PLDPAR_PLDPAR5 (0x20) -#define MCF_GPIO_PLDPAR_PLDPAR6 (0x40) -#define MCF_GPIO_PLDPAR_ACTLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_LNKLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_SPDLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_DUPLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_COLLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_RXLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_TXLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_ACTLED_ACTLED (0x01) -#define MCF_GPIO_PLDPAR_LNKLED_LNKLED (0x02) -#define MCF_GPIO_PLDPAR_SPDLED_SPDLED (0x04) -#define MCF_GPIO_PLDPAR_DUPLED_DUPLED (0x08) -#define MCF_GPIO_PLDPAR_COLLED_COLLED (0x10) -#define MCF_GPIO_PLDPAR_RXLED_RXLED (0x20) -#define MCF_GPIO_PLDPAR_TXLED_TXLED (0x40) - -/* Bit definitions and macros for MCF_GPIO_PGPPAR */ -#define MCF_GPIO_PGPPAR_PGPPAR0 (0x01) -#define MCF_GPIO_PGPPAR_PGPPAR1 (0x02) -#define MCF_GPIO_PGPPAR_PGPPAR2 (0x04) -#define MCF_GPIO_PGPPAR_PGPPAR3 (0x08) -#define MCF_GPIO_PGPPAR_PGPPAR4 (0x10) -#define MCF_GPIO_PGPPAR_PGPPAR5 (0x20) -#define MCF_GPIO_PGPPAR_PGPPAR6 (0x40) -#define MCF_GPIO_PGPPAR_PGPPAR7 (0x80) -#define MCF_GPIO_PGPPAR_IRQ8_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ9_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ10_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ11_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ12_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ13_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ14_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ15_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ8_IRQ8 (0x01) -#define MCF_GPIO_PGPPAR_IRQ9_IRQ9 (0x02) -#define MCF_GPIO_PGPPAR_IRQ10_IRQ10 (0x04) -#define MCF_GPIO_PGPPAR_IRQ11_IRQ11 (0x08) -#define MCF_GPIO_PGPPAR_IRQ12_IRQ12 (0x10) -#define MCF_GPIO_PGPPAR_IRQ13_IRQ13 (0x30) -#define MCF_GPIO_PGPPAR_IRQ14_IRQ14 (0x40) -#define MCF_GPIO_PGPPAR_IRQ15_IRQ15 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PWOR */ -#define MCF_GPIO_PWOR_PWOR0 (0x0001) -#define MCF_GPIO_PWOR_PWOR1 (0x0002) -#define MCF_GPIO_PWOR_PWOR2 (0x0004) -#define MCF_GPIO_PWOR_PWOR3 (0x0008) -#define MCF_GPIO_PWOR_PWOR4 (0x0010) -#define MCF_GPIO_PWOR_PWOR5 (0x0020) -#define MCF_GPIO_PWOR_PWOR6 (0x0040) -#define MCF_GPIO_PWOR_PWOR7 (0x0080) -#define MCF_GPIO_PWOR_PWOR8 (0x0100) -#define MCF_GPIO_PWOR_PWOR9 (0x0200) -#define MCF_GPIO_PWOR_PWOR10 (0x0400) -#define MCF_GPIO_PWOR_PWOR11 (0x0800) -#define MCF_GPIO_PWOR_PWOR12 (0x1000) -#define MCF_GPIO_PWOR_PWOR13 (0x2000) -#define MCF_GPIO_PWOR_PWOR14 (0x4000) -#define MCF_GPIO_PWOR_PWOR15 (0x8000) - -/* Bit definitions and macros for MCF_GPIO_PDSRH */ -#define MCF_GPIO_PDSRH_PDSR32 (0x0001) -#define MCF_GPIO_PDSRH_PDSR33 (0x0002) -#define MCF_GPIO_PDSRH_PDSR34 (0x0004) -#define MCF_GPIO_PDSRH_PDSR35 (0x0008) -#define MCF_GPIO_PDSRH_PDSR36 (0x0010) -#define MCF_GPIO_PDSRH_PDSR37 (0x0020) -#define MCF_GPIO_PDSRH_PDSR38 (0x0040) -#define MCF_GPIO_PDSRH_PDSR39 (0x0080) -#define MCF_GPIO_PDSRH_PDSR40 (0x0100) -#define MCF_GPIO_PDSRH_PDSR41 (0x0200) -#define MCF_GPIO_PDSRH_PDSR42 (0x0400) -#define MCF_GPIO_PDSRH_PDSR43 (0x0800) -#define MCF_GPIO_PDSRH_PDSR44 (0x1000) -#define MCF_GPIO_PDSRH_PDSR45 (0x2000) -#define MCF_GPIO_PDSRH_PDSR46 (0x4000) -#define MCF_GPIO_PDSRH_PDSR47 (0x8000) - -/* Bit definitions and macros for MCF_GPIO_PDSRL */ -#define MCF_GPIO_PDSRL_PDSR0 (0x00000001) -#define MCF_GPIO_PDSRL_PDSR1 (0x00000002) -#define MCF_GPIO_PDSRL_PDSR2 (0x00000004) -#define MCF_GPIO_PDSRL_PDSR3 (0x00000008) -#define MCF_GPIO_PDSRL_PDSR4 (0x00000010) -#define MCF_GPIO_PDSRL_PDSR5 (0x00000020) -#define MCF_GPIO_PDSRL_PDSR6 (0x00000040) -#define MCF_GPIO_PDSRL_PDSR7 (0x00000080) -#define MCF_GPIO_PDSRL_PDSR8 (0x00000100) -#define MCF_GPIO_PDSRL_PDSR9 (0x00000200) -#define MCF_GPIO_PDSRL_PDSR10 (0x00000400) -#define MCF_GPIO_PDSRL_PDSR11 (0x00000800) -#define MCF_GPIO_PDSRL_PDSR12 (0x00001000) -#define MCF_GPIO_PDSRL_PDSR13 (0x00002000) -#define MCF_GPIO_PDSRL_PDSR14 (0x00004000) -#define MCF_GPIO_PDSRL_PDSR15 (0x00008000) -#define MCF_GPIO_PDSRL_PDSR16 (0x00010000) -#define MCF_GPIO_PDSRL_PDSR17 (0x00020000) -#define MCF_GPIO_PDSRL_PDSR18 (0x00040000) -#define MCF_GPIO_PDSRL_PDSR19 (0x00080000) -#define MCF_GPIO_PDSRL_PDSR20 (0x00100000) -#define MCF_GPIO_PDSRL_PDSR21 (0x00200000) -#define MCF_GPIO_PDSRL_PDSR22 (0x00400000) -#define MCF_GPIO_PDSRL_PDSR23 (0x00800000) -#define MCF_GPIO_PDSRL_PDSR24 (0x01000000) -#define MCF_GPIO_PDSRL_PDSR25 (0x02000000) -#define MCF_GPIO_PDSRL_PDSR26 (0x04000000) -#define MCF_GPIO_PDSRL_PDSR27 (0x08000000) -#define MCF_GPIO_PDSRL_PDSR28 (0x10000000) -#define MCF_GPIO_PDSRL_PDSR29 (0x20000000) -#define MCF_GPIO_PDSRL_PDSR30 (0x40000000) -#define MCF_GPIO_PDSRL_PDSR31 (0x80000000) - -/********************************************************************* -* -* ColdFire Integration Module (CIM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CIM_RCR (*(vuint8 *)(&__IPSBAR[0x110000])) -#define MCF_CIM_RSR (*(vuint8 *)(&__IPSBAR[0x110001])) -#define MCF_CIM_CCR (*(vuint16*)(&__IPSBAR[0x110004])) -#define MCF_CIM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) -#define MCF_CIM_RCON (*(vuint16*)(&__IPSBAR[0x110008])) -#define MCF_CIM_CIR (*(vuint16*)(&__IPSBAR[0x11000A])) - -/* Bit definitions and macros for MCF_CIM_RCR */ -#define MCF_CIM_RCR_LVDE (0x01) -#define MCF_CIM_RCR_LVDRE (0x04) -#define MCF_CIM_RCR_LVDIE (0x08) -#define MCF_CIM_RCR_LVDF (0x10) -#define MCF_CIM_RCR_FRCRSTOUT (0x40) -#define MCF_CIM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for MCF_CIM_RSR */ -#define MCF_CIM_RSR_LOL (0x01) -#define MCF_CIM_RSR_LOC (0x02) -#define MCF_CIM_RSR_EXT (0x04) -#define MCF_CIM_RSR_POR (0x08) -#define MCF_CIM_RSR_WDR (0x10) -#define MCF_CIM_RSR_SOFT (0x20) -#define MCF_CIM_RSR_LVD (0x40) - -/* Bit definitions and macros for MCF_CIM_CCR */ -#define MCF_CIM_CCR_LOAD (0x8000) -#define MCF_CIM_CCR_EZPORT (0x05) -#define MCF_CIM_CCR_SCHIP (0x06) -#define MCF_CIM_CCR_MODE(x) (((x)&0x7)<<8) - -/* Bit definitions and macros for MCF_CIM_LPCR */ -#define MCF_CIM_LPCR_LVDSE (0x02) -#define MCF_CIM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF_CIM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF_CIM_LPCR_LPMD_STOP (0xC0) -#define MCF_CIM_LPCR_LPMD_WAIT (0x80) -#define MCF_CIM_LPCR_LPMD_DOZE (0x40) -#define MCF_CIM_LPCR_LPMD_RUN (0x00) - -/* Bit definitions and macros for MCF_CIM_RCON */ -#define MCF_CIM_RCON_RLOAD (0x0020) - -/********************************************************************* -* -* Clock Module (CLOCK) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CLOCK_SYNCR (*(vuint16*)(&__IPSBAR[0x120000])) -#define MCF_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002])) -#define MCF_CLOCK_LPCR (*(vuint8 *)(&__IPSBAR[0x120007])) -#define MCF_CLOCK_CCHR (*(vuint8 *)(&__IPSBAR[0x120008])) -#define MCF_CLOCK_CCLR (*(vuint8 *)(&__IPSBAR[0x120009])) -#define MCF_CLOCK_RTCDR (*(vuint32*)(&__IPSBAR[0x12000C])) -#define MCF_CLOCK_RTCCR (*(vuint8*)(&__IPSBAR[0x120012])) - -/* Bit definitions and macros for MCF_CLOCK_SYNCR */ -#define MCF_CLOCK_SYNCR_PLLEN (0x0001) -#define MCF_CLOCK_SYNCR_PLLMODE (0x0002) -#define MCF_CLOCK_SYNCR_CLKSRC (0x0004) -#define MCF_CLOCK_SYNCR_FWKUP (0x0020) -#define MCF_CLOCK_SYNCR_DISCLK (0x0040) -#define MCF_CLOCK_SYNCR_LOCEN (0x0080) -#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) -#define MCF_CLOCK_SYNCR_LOCRE (0x0800) -#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) -#define MCF_CLOCK_SYNCR_LOLRE (0x8000) - -/* Bit definitions and macros for MCF_CLOCK_SYNSR */ -#define MCF_CLOCK_SYNSR_LOCS (0x04) -#define MCF_CLOCK_SYNSR_LOCK (0x08) -#define MCF_CLOCK_SYNSR_LOCKS (0x10) -#define MCF_CLOCK_SYNSR_CRYOSC (0x20) -#define MCF_CLOCK_SYNSR_OCOSC (0x40) -#define MCF_CLOCK_SYNSR_EXTOSC (0x80) - -/* Bit definitions and macros for MCF_CLOCK_LPCR */ -#define MCF_CLOCK_LPCR_LPD(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_CLOCK_CCHR */ -#define MCF_CLOCK_CCHR_PFD(x) (((x)&0x07)<<0) - -/* Bit definitions and macros for MCF_CLOCK_CCHR */ -#define MCF_CLOCK_CCLR_PRIM_OSC (0x00) -#define MCF_CLOCK_CCLR_REL_OSC (0x01) -#define MCF_CLOCK_CCLR_SEC_OSC (0x02) -#define MCF_CLOCK_CCLR_SEC1_OSC (0x03) - -/* Bit definitions and macros for MCF_CLOCK_RTCDR */ -#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CLOCK_RTCCR */ -#define MCF_CLOCK_RTCCR_RTCSEL 0x01U -#define MCF_CLOCK_RTCCR_LPEN 0x02U -#define MCF_CLOCK_RTCCR_REFS 0x04U -#define MCF_CLOCK_RTCCR_KHZEN 0x08U -#define MCF_CLOCK_RTCCR_OSCEN 0x10U -#define MCF_CLOCK_RTCCR_EXTALEN 0x40U - -/********************************************************************* -* -* Edge Port Module (EPORT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_EPORT_EPPAR0 (*(vuint16*)(&__IPSBAR[0x130000])) -#define MCF_EPORT_EPDDR0 (*(vuint8 *)(&__IPSBAR[0x130002])) -#define MCF_EPORT_EPIER0 (*(vuint8 *)(&__IPSBAR[0x130003])) -#define MCF_EPORT_EPDR0 (*(vuint8 *)(&__IPSBAR[0x130004])) -#define MCF_EPORT_EPPDR0 (*(vuint8 *)(&__IPSBAR[0x130005])) -#define MCF_EPORT_EPFR0 (*(vuint8 *)(&__IPSBAR[0x130006])) - -/* Bit definitions and macros for MCF_EPORT_EPPAR */ -#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_EPPA8(x) (((x)&0x0003)<<0) -#define MCF_EPORT_EPPAR_EPPA9(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA10(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA11(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA12(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA13(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA14(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA15(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_LEVEL (0) -#define MCF_EPORT_EPPAR_RISING (1) -#define MCF_EPORT_EPPAR_FALLING (2) -#define MCF_EPORT_EPPAR_BOTH (3) -#define MCF_EPORT_EPPAR_EPPA15_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA15_RISING (0x4000) -#define MCF_EPORT_EPPAR_EPPA15_FALLING (0x8000) -#define MCF_EPORT_EPPAR_EPPA15_BOTH (0xC000) -#define MCF_EPORT_EPPAR_EPPA14_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA14_RISING (0x1000) -#define MCF_EPORT_EPPAR_EPPA14_FALLING (0x2000) -#define MCF_EPORT_EPPAR_EPPA14_BOTH (0x3000) -#define MCF_EPORT_EPPAR_EPPA13_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA13_RISING (0x0400) -#define MCF_EPORT_EPPAR_EPPA13_FALLING (0x0800) -#define MCF_EPORT_EPPAR_EPPA13_BOTH (0x0C00) -#define MCF_EPORT_EPPAR_EPPA12_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA12_RISING (0x0100) -#define MCF_EPORT_EPPAR_EPPA12_FALLING (0x0200) -#define MCF_EPORT_EPPAR_EPPA12_BOTH (0x0300) -#define MCF_EPORT_EPPAR_EPPA11_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA11_RISING (0x0040) -#define MCF_EPORT_EPPAR_EPPA11_FALLING (0x0080) -#define MCF_EPORT_EPPAR_EPPA11_BOTH (0x00C0) -#define MCF_EPORT_EPPAR_EPPA10_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA10_RISING (0x0010) -#define MCF_EPORT_EPPAR_EPPA10_FALLING (0x0020) -#define MCF_EPORT_EPPAR_EPPA10_BOTH (0x0030) -#define MCF_EPORT_EPPAR_EPPA9_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA9_RISING (0x0004) -#define MCF_EPORT_EPPAR_EPPA9_FALLING (0x0008) -#define MCF_EPORT_EPPAR_EPPA9_BOTH (0x000C) -#define MCF_EPORT_EPPAR_EPPA8_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA8_RISING (0x0001) -#define MCF_EPORT_EPPAR_EPPA8_FALLING (0x0002) -#define MCF_EPORT_EPPAR_EPPA8_BOTH (0x0003) -#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) -#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) -#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) -#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) -#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) -#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) -#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) -#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) -#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) -#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) -#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) -#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) -#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) -#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) -#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) -#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) -#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) -#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) -#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) -#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) -#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) - -/* Bit definitions and macros for MCF_EPORT_EPDDR */ -#define MCF_EPORT_EPDDR_EPDD1 (0x02) -#define MCF_EPORT_EPDDR_EPDD2 (0x04) -#define MCF_EPORT_EPDDR_EPDD3 (0x08) -#define MCF_EPORT_EPDDR_EPDD4 (0x10) -#define MCF_EPORT_EPDDR_EPDD5 (0x20) -#define MCF_EPORT_EPDDR_EPDD6 (0x40) -#define MCF_EPORT_EPDDR_EPDD7 (0x80) -#define MCF_EPORT_EPDDR_EPDD8 (0x01) -#define MCF_EPORT_EPDDR_EPDD9 (0x02) -#define MCF_EPORT_EPDDR_EPDD10 (0x04) -#define MCF_EPORT_EPDDR_EPDD11 (0x08) -#define MCF_EPORT_EPDDR_EPDD12 (0x10) -#define MCF_EPORT_EPDDR_EPDD13 (0x20) -#define MCF_EPORT_EPDDR_EPDD14 (0x40) -#define MCF_EPORT_EPDDR_EPDD15 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPIER */ -#define MCF_EPORT_EPIER_EPIE1 (0x02) -#define MCF_EPORT_EPIER_EPIE2 (0x04) -#define MCF_EPORT_EPIER_EPIE3 (0x08) -#define MCF_EPORT_EPIER_EPIE4 (0x10) -#define MCF_EPORT_EPIER_EPIE5 (0x20) -#define MCF_EPORT_EPIER_EPIE6 (0x40) -#define MCF_EPORT_EPIER_EPIE7 (0x80) -#define MCF_EPORT_EPIER_EPIE8 (0x01) -#define MCF_EPORT_EPIER_EPIE9 (0x02) -#define MCF_EPORT_EPIER_EPIE10 (0x04) -#define MCF_EPORT_EPIER_EPIE11 (0x08) -#define MCF_EPORT_EPIER_EPIE12 (0x10) -#define MCF_EPORT_EPIER_EPIE13 (0x20) -#define MCF_EPORT_EPIER_EPIE14 (0x40) -#define MCF_EPORT_EPIER_EPIE15 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPDR */ -#define MCF_EPORT_EPDR_EPD1 (0x02) -#define MCF_EPORT_EPDR_EPD2 (0x04) -#define MCF_EPORT_EPDR_EPD3 (0x08) -#define MCF_EPORT_EPDR_EPD4 (0x10) -#define MCF_EPORT_EPDR_EPD5 (0x20) -#define MCF_EPORT_EPDR_EPD6 (0x40) -#define MCF_EPORT_EPDR_EPD7 (0x80) -#define MCF_EPORT_EPDR_EPD8 (0x01) -#define MCF_EPORT_EPDR_EPD9 (0x02) -#define MCF_EPORT_EPDR_EPD10 (0x04) -#define MCF_EPORT_EPDR_EPD11 (0x08) -#define MCF_EPORT_EPDR_EPD12 (0x10) -#define MCF_EPORT_EPDR_EPD13 (0x20) -#define MCF_EPORT_EPDR_EPD14 (0x40) -#define MCF_EPORT_EPDR_EPD15 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPPDR */ -#define MCF_EPORT_EPPDR_EPPD1 (0x02) -#define MCF_EPORT_EPPDR_EPPD2 (0x04) -#define MCF_EPORT_EPPDR_EPPD3 (0x08) -#define MCF_EPORT_EPPDR_EPPD4 (0x10) -#define MCF_EPORT_EPPDR_EPPD5 (0x20) -#define MCF_EPORT_EPPDR_EPPD6 (0x40) -#define MCF_EPORT_EPPDR_EPPD7 (0x80) -#define MCF_EPORT_EPPDR_EPPD8 (0x01) -#define MCF_EPORT_EPPDR_EPPD9 (0x02) -#define MCF_EPORT_EPPDR_EPPD10 (0x04) -#define MCF_EPORT_EPPDR_EPPD11 (0x08) -#define MCF_EPORT_EPPDR_EPPD12 (0x10) -#define MCF_EPORT_EPPDR_EPPD13 (0x20) -#define MCF_EPORT_EPPDR_EPPD14 (0x40) -#define MCF_EPORT_EPPDR_EPPD15 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPFR */ -#define MCF_EPORT_EPFR_EPF1 (0x02) -#define MCF_EPORT_EPFR_EPF2 (0x04) -#define MCF_EPORT_EPFR_EPF3 (0x08) -#define MCF_EPORT_EPFR_EPF4 (0x10) -#define MCF_EPORT_EPFR_EPF5 (0x20) -#define MCF_EPORT_EPFR_EPF6 (0x40) -#define MCF_EPORT_EPFR_EPF7 (0x80) -#define MCF_EPORT_EPFR_EPF8 (0x01) -#define MCF_EPORT_EPFR_EPF9 (0x02) -#define MCF_EPORT_EPFR_EPF10 (0x04) -#define MCF_EPORT_EPFR_EPF11 (0x08) -#define MCF_EPORT_EPFR_EPF12 (0x10) -#define MCF_EPORT_EPFR_EPF13 (0x20) -#define MCF_EPORT_EPFR_EPF14 (0x40) -#define MCF_EPORT_EPFR_EPF15 (0x80) - - -/********************************************************************* -* -* Backup Watchdog Timer Module (BWT) -* -*********************************************************************/ - -#define MCF_BWT_WCR (*(vuint16*)(&__IPSBAR[0x140000])) -#define MCF_BWT_WMR (*(vuint16*)(&__IPSBAR[0x140002])) -#define MCF_BWT_WCNTR (*(vuint16*)(&__IPSBAR[0x140004])) -#define MCF_BWT_WSR (*(vuint16*)(&__IPSBAR[0x140006])) - -/* Bit definitions and macros for MCF_BWT_WCR */ -#define MCF_BWT_WCR_EN 0x01 -#define MCF_BWT_WCR_DOZE 0x04 -#define MCF_BWT_WCR_WAIT 0x08 -#define MCF_BWT_WCR_STOP 0x10 - -#define MCF_BWT_WSR_SEQ1 0x5555 -#define MCF_BWT_WSR_SEQ2 0xAAAA - -//MPR: TODO this Modules is new in mcf52258 vs. mcf52235 and some macros must be written first - -/********************************************************************* -* -* Programmable Interrupt Timer Modules (PIT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PIT0_PCSR (*(vuint16*)(&__IPSBAR[0x150000])) -#define MCF_PIT0_PMR (*(vuint16*)(&__IPSBAR[0x150002])) -#define MCF_PIT0_PCNTR (*(vuint16*)(&__IPSBAR[0x150004])) -#define MCF_PIT1_PCSR (*(vuint16*)(&__IPSBAR[0x160000])) -#define MCF_PIT1_PMR (*(vuint16*)(&__IPSBAR[0x160002])) -#define MCF_PIT1_PCNTR (*(vuint16*)(&__IPSBAR[0x160004])) -#define MCF_PIT_PCSR(x) (*(vuint16*)(&__IPSBAR[0x150000+((x)*0x10000)])) -#define MCF_PIT_PMR(x) (*(vuint16*)(&__IPSBAR[0x150002+((x)*0x10000)])) -#define MCF_PIT_PCNTR(x) (*(vuint16*)(&__IPSBAR[0x150004+((x)*0x10000)])) - -/* Bit definitions and macros for MCF_PIT_PCSR */ -#define MCF_PIT_PCSR_EN (0x0001) -#define MCF_PIT_PCSR_RLD (0x0002) -#define MCF_PIT_PCSR_PIF (0x0004) -#define MCF_PIT_PCSR_PIE (0x0008) -#define MCF_PIT_PCSR_OVW (0x0010) -#define MCF_PIT_PCSR_HALTED (0x0020) -#define MCF_PIT_PCSR_DOZE (0x0040) -#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) - -/* Bit definitions and macros for MCF_PIT_PMR */ -#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_PIT_PCNTR */ -#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0) - -/********************************************************************* -* -* Analog-to-Digital Converter (ADC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_ADC_CTRL1 (*(vuint16*)(&__IPSBAR[0x190000])) -#define MCF_ADC_CTRL2 (*(vuint16*)(&__IPSBAR[0x190002])) -#define MCF_ADC_ADZCC (*(vuint16*)(&__IPSBAR[0x190004])) -#define MCF_ADC_ADLST1 (*(vuint16*)(&__IPSBAR[0x190006])) -#define MCF_ADC_ADLST2 (*(vuint16*)(&__IPSBAR[0x190008])) -#define MCF_ADC_ADSDIS (*(vuint16*)(&__IPSBAR[0x19000A])) -#define MCF_ADC_ADSTAT (*(vuint16*)(&__IPSBAR[0x19000C])) -#define MCF_ADC_ADLSTAT (*(vuint16*)(&__IPSBAR[0x19000E])) -#define MCF_ADC_ADZCSTAT (*(vuint16*)(&__IPSBAR[0x190010])) -#define MCF_ADC_ADRSLT0 (*(vuint16*)(&__IPSBAR[0x190012])) -#define MCF_ADC_ADRSLT1 (*(vuint16*)(&__IPSBAR[0x190014])) -#define MCF_ADC_ADRSLT2 (*(vuint16*)(&__IPSBAR[0x190016])) -#define MCF_ADC_ADRSLT3 (*(vuint16*)(&__IPSBAR[0x190018])) -#define MCF_ADC_ADRSLT4 (*(vuint16*)(&__IPSBAR[0x19001A])) -#define MCF_ADC_ADRSLT5 (*(vuint16*)(&__IPSBAR[0x19001C])) -#define MCF_ADC_ADRSLT6 (*(vuint16*)(&__IPSBAR[0x19001E])) -#define MCF_ADC_ADRSLT7 (*(vuint16*)(&__IPSBAR[0x190020])) -#define MCF_ADC_ADRSLT(x) (*(vuint16*)(&__IPSBAR[0x190012+((x)*0x002)])) -#define MCF_ADC_ADLLMT0 (*(vuint16*)(&__IPSBAR[0x190022])) -#define MCF_ADC_ADLLMT1 (*(vuint16*)(&__IPSBAR[0x190024])) -#define MCF_ADC_ADLLMT2 (*(vuint16*)(&__IPSBAR[0x190026])) -#define MCF_ADC_ADLLMT3 (*(vuint16*)(&__IPSBAR[0x190028])) -#define MCF_ADC_ADLLMT4 (*(vuint16*)(&__IPSBAR[0x19002A])) -#define MCF_ADC_ADLLMT5 (*(vuint16*)(&__IPSBAR[0x19002C])) -#define MCF_ADC_ADLLMT6 (*(vuint16*)(&__IPSBAR[0x19002E])) -#define MCF_ADC_ADLLMT7 (*(vuint16*)(&__IPSBAR[0x190030])) -#define MCF_ADC_ADLLMT(x) (*(vuint16*)(&__IPSBAR[0x190022+((x)*0x002)])) -#define MCF_ADC_ADHLMT0 (*(vuint16*)(&__IPSBAR[0x190032])) -#define MCF_ADC_ADHLMT1 (*(vuint16*)(&__IPSBAR[0x190034])) -#define MCF_ADC_ADHLMT2 (*(vuint16*)(&__IPSBAR[0x190036])) -#define MCF_ADC_ADHLMT3 (*(vuint16*)(&__IPSBAR[0x190038])) -#define MCF_ADC_ADHLMT4 (*(vuint16*)(&__IPSBAR[0x19003A])) -#define MCF_ADC_ADHLMT5 (*(vuint16*)(&__IPSBAR[0x19003C])) -#define MCF_ADC_ADHLMT6 (*(vuint16*)(&__IPSBAR[0x19003E])) -#define MCF_ADC_ADHLMT7 (*(vuint16*)(&__IPSBAR[0x190040])) -#define MCF_ADC_ADHLMT(x) (*(vuint16*)(&__IPSBAR[0x190032+((x)*0x002)])) -#define MCF_ADC_ADOFS0 (*(vuint16*)(&__IPSBAR[0x190042])) -#define MCF_ADC_ADOFS1 (*(vuint16*)(&__IPSBAR[0x190044])) -#define MCF_ADC_ADOFS2 (*(vuint16*)(&__IPSBAR[0x190046])) -#define MCF_ADC_ADOFS3 (*(vuint16*)(&__IPSBAR[0x190048])) -#define MCF_ADC_ADOFS4 (*(vuint16*)(&__IPSBAR[0x19004A])) -#define MCF_ADC_ADOFS5 (*(vuint16*)(&__IPSBAR[0x19004C])) -#define MCF_ADC_ADOFS6 (*(vuint16*)(&__IPSBAR[0x19004E])) -#define MCF_ADC_ADOFS7 (*(vuint16*)(&__IPSBAR[0x190050])) -#define MCF_ADC_ADOFS(x) (*(vuint16*)(&__IPSBAR[0x190042+((x)*0x002)])) -#define MCF_ADC_POWER (*(vuint16*)(&__IPSBAR[0x190052])) -#define MCF_ADC_CAL (*(vuint16*)(&__IPSBAR[0x190054])) - -/* Bit definitions and macros for MCF_ADC_CTRL1 */ -#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x0007)<<0) -#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0x000F)<<4) -#define MCF_ADC_CTRL1_HLMTIE (0x0100) -#define MCF_ADC_CTRL1_LLMTIE (0x0200) -#define MCF_ADC_CTRL1_ZCIE (0x0400) -#define MCF_ADC_CTRL1_EOSIE0 (0x0800) -#define MCF_ADC_CTRL1_SYNC0 (0x1000) -#define MCF_ADC_CTRL1_START0 (0x2000) -#define MCF_ADC_CTRL1_STOP0 (0x4000) - -/* Bit definitions and macros for MCF_ADC_CTRL2 */ -#define MCF_ADC_CTRL2_DIV(x) (((x)&0x001F)<<0) -#define MCF_ADC_CTRL2_SIMULT (0x0020) -#define MCF_ADC_CTRL2_EOSIE1 (0x0800) -#define MCF_ADC_CTRL2_SYNC1 (0x1000) -#define MCF_ADC_CTRL2_START1 (0x2000) -#define MCF_ADC_CTRL2_STOP1 (0x4000) - -/* Bit definitions and macros for MCF_ADC_ADZCC */ -#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x0003)<<0) -#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x0003)<<2) -#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x0003)<<4) -#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x0003)<<6) -#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x0003)<<8) -#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x0003)<<10) -#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x0003)<<12) -#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x0003)<<14) - -/* Bit definitions and macros for MCF_ADC_ADLST1 */ -#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x0007)<<0) -#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x0007)<<4) -#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x0007)<<8) -#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x0007)<<12) - -/* Bit definitions and macros for MCF_ADC_ADLST2 */ -#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x0007)<<0) -#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x0007)<<4) -#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x0007)<<8) -#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x0007)<<12) - -/* Bit definitions and macros for MCF_ADC_ADSDIS */ -#define MCF_ADC_ADSDIS_DS0 (0x0001) -#define MCF_ADC_ADSDIS_DS1 (0x0002) -#define MCF_ADC_ADSDIS_DS2 (0x0004) -#define MCF_ADC_ADSDIS_DS3 (0x0008) -#define MCF_ADC_ADSDIS_DS4 (0x0010) -#define MCF_ADC_ADSDIS_DS5 (0x0020) -#define MCF_ADC_ADSDIS_DS6 (0x0040) -#define MCF_ADC_ADSDIS_DS7 (0x0080) - -/* Bit definitions and macros for MCF_ADC_ADSTAT */ -#define MCF_ADC_ADSTAT_RDY0 (0x0001) -#define MCF_ADC_ADSTAT_RDY1 (0x0002) -#define MCF_ADC_ADSTAT_RDY2 (0x0004) -#define MCF_ADC_ADSTAT_RDY3 (0x0008) -#define MCF_ADC_ADSTAT_RDY4 (0x0010) -#define MCF_ADC_ADSTAT_RDY5 (0x0020) -#define MCF_ADC_ADSTAT_RDY6 (0x0040) -#define MCF_ADC_ADSTAT_RDY7 (0x0080) -#define MCF_ADC_ADSTAT_HLMT (0x0100) -#define MCF_ADC_ADSTAT_LLMTI (0x0200) -#define MCF_ADC_ADSTAT_ZCI (0x0400) -#define MCF_ADC_ADSTAT_EOSI (0x0800) -#define MCF_ADC_ADSTAT_CIP (0x8000) - -/* Bit definitions and macros for MCF_ADC_ADLSTAT */ -#define MCF_ADC_ADLSTAT_LLS0 (0x0001) -#define MCF_ADC_ADLSTAT_LLS1 (0x0002) -#define MCF_ADC_ADLSTAT_LLS2 (0x0004) -#define MCF_ADC_ADLSTAT_LLS3 (0x0008) -#define MCF_ADC_ADLSTAT_LLS4 (0x0010) -#define MCF_ADC_ADLSTAT_LLS5 (0x0020) -#define MCF_ADC_ADLSTAT_LLS6 (0x0040) -#define MCF_ADC_ADLSTAT_LLS7 (0x0080) -#define MCF_ADC_ADLSTAT_HLS0 (0x0100) -#define MCF_ADC_ADLSTAT_HLS1 (0x0200) -#define MCF_ADC_ADLSTAT_HLS2 (0x0400) -#define MCF_ADC_ADLSTAT_HLS3 (0x0800) -#define MCF_ADC_ADLSTAT_HLS4 (0x1000) -#define MCF_ADC_ADLSTAT_HLS5 (0x2000) -#define MCF_ADC_ADLSTAT_HLS6 (0x4000) -#define MCF_ADC_ADLSTAT_HLS7 (0x8000) - -/* Bit definitions and macros for MCF_ADC_ADZCSTAT */ -#define MCF_ADC_ADZCSTAT_ZCS0 (0x0001) -#define MCF_ADC_ADZCSTAT_ZCS1 (0x0002) -#define MCF_ADC_ADZCSTAT_ZCS2 (0x0004) -#define MCF_ADC_ADZCSTAT_ZCS3 (0x0008) -#define MCF_ADC_ADZCSTAT_ZCS4 (0x0010) -#define MCF_ADC_ADZCSTAT_ZCS5 (0x0020) -#define MCF_ADC_ADZCSTAT_ZCS6 (0x0040) -#define MCF_ADC_ADZCSTAT_ZCS7 (0x0080) - -/* Bit definitions and macros for MCF_ADC_ADRSLT */ -#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0x0FFF)<<3) -#define MCF_ADC_ADRSLT_SEXT (0x8000) - -/* Bit definitions and macros for MCF_ADC_ADLLMT */ -#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0x0FFF)<<3) - -/* Bit definitions and macros for MCF_ADC_ADHLMT */ -#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0x0FFF)<<3) - -/* Bit definitions and macros for MCF_ADC_ADOFS */ -#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0x0FFF)<<3) - -/* Bit definitions and macros for MCF_ADC_POWER */ -#define MCF_ADC_POWER_PD0 (0x0001) -#define MCF_ADC_POWER_PD1 (0x0002) -#define MCF_ADC_POWER_PD2 (0x0004) -#define MCF_ADC_POWER_APD (0x0008) -#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x003F)<<4) -#define MCF_ADC_POWER_PSTS0 (0x0400) -#define MCF_ADC_POWER_PSTS1 (0x0800) -#define MCF_ADC_POWER_PSTS2 (0x1000) -#define MCF_ADC_POWER_ASTBY (0x8000) - -/* Bit definitions and macros for MCF_ADC_CAL */ -#define MCF_ADC_CAL_CAL0 (0x0001) -#define MCF_ADC_CAL_CRS0 (0x0002) -#define MCF_ADC_CAL_CAL1 (0x0004) -#define MCF_ADC_CAL_CRS1 (0x0008) - -/********************************************************************* -* -* General Purpose Timer (GPT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPT_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000])) -#define MCF_GPT_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001])) -#define MCF_GPT_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002])) -#define MCF_GPT_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003])) -#define MCF_GPT_GPTCNT (*(vuint16*)(&__IPSBAR[0x1A0004])) -#define MCF_GPT_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006])) -#define MCF_GPT_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008])) -#define MCF_GPT_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009])) -#define MCF_GPT_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B])) -#define MCF_GPT_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C])) -#define MCF_GPT_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D])) -#define MCF_GPT_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E])) -#define MCF_GPT_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F])) -#define MCF_GPT_GPTC0 (*(vuint16*)(&__IPSBAR[0x1A0010])) -#define MCF_GPT_GPTC1 (*(vuint16*)(&__IPSBAR[0x1A0012])) -#define MCF_GPT_GPTC2 (*(vuint16*)(&__IPSBAR[0x1A0014])) -#define MCF_GPT_GPTC3 (*(vuint16*)(&__IPSBAR[0x1A0016])) -#define MCF_GPT_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1A0010+((x)*0x002)])) -#define MCF_GPT_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018])) -#define MCF_GPT_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019])) -#define MCF_GPT_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1A001A])) -#define MCF_GPT_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D])) -#define MCF_GPT_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E])) - -/* Bit definitions and macros for MCF_GPT_GPTIOS */ -#define MCF_GPT_GPTIOS_IOS0 (0x01) -#define MCF_GPT_GPTIOS_IOS1 (0x02) -#define MCF_GPT_GPTIOS_IOS2 (0x04) -#define MCF_GPT_GPTIOS_IOS3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTCFORC */ -#define MCF_GPT_GPTCFORC_FOC0 (0x01) -#define MCF_GPT_GPTCFORC_FOC1 (0x02) -#define MCF_GPT_GPTCFORC_FOC2 (0x04) -#define MCF_GPT_GPTCFORC_FOC3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTOC3D */ -#define MCF_GPT_GPTOC3D_OC3D0 (0x01) -#define MCF_GPT_GPTOC3D_OC3D1 (0x02) -#define MCF_GPT_GPTOC3D_OC3D2 (0x04) -#define MCF_GPT_GPTOC3D_OC3D3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTSCR1 */ -#define MCF_GPT_GPTSCR1_TFFCA (0x10) -#define MCF_GPT_GPTSCR1_GPTEN (0x80) - -/* Bit definitions and macros for MCF_GPT_GPTTOV */ -#define MCF_GPT_GPTTOV_TOV0 (0x01) -#define MCF_GPT_GPTTOV_TOV1 (0x02) -#define MCF_GPT_GPTTOV_TOV2 (0x04) -#define MCF_GPT_GPTTOV_TOV3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTCTL1 */ -#define MCF_GPT_GPTCTL1_OL0 (0x01) -#define MCF_GPT_GPTCTL1_OM0 (0x02) -#define MCF_GPT_GPTCTL1_OL1 (0x04) -#define MCF_GPT_GPTCTL1_OM1 (0x08) -#define MCF_GPT_GPTCTL1_OL2 (0x10) -#define MCF_GPT_GPTCTL1_OM2 (0x20) -#define MCF_GPT_GPTCTL1_OL3 (0x40) -#define MCF_GPT_GPTCTL1_OM3 (0x80) -#define MCF_GPT_GPTCTL1_OUTPUT3_NOTHING ((0x00)) -#define MCF_GPT_GPTCTL1_OUTPUT3_TOGGLE ((0x40)) -#define MCF_GPT_GPTCTL1_OUTPUT3_CLEAR ((0x80)) -#define MCF_GPT_GPTCTL1_OUTPUT3_SET ((0xC0)) -#define MCF_GPT_GPTCTL1_OUTPUT2_NOTHING ((0x00)) -#define MCF_GPT_GPTCTL1_OUTPUT2_TOGGLE ((0x10)) -#define MCF_GPT_GPTCTL1_OUTPUT2_CLEAR ((0x20)) -#define MCF_GPT_GPTCTL1_OUTPUT2_SET ((0x30)) -#define MCF_GPT_GPTCTL1_OUTPUT1_NOTHING ((0x00)) -#define MCF_GPT_GPTCTL1_OUTPUT1_TOGGLE ((0x04)) -#define MCF_GPT_GPTCTL1_OUTPUT1_CLEAR ((0x08)) -#define MCF_GPT_GPTCTL1_OUTPUT1_SET ((0x0C)) -#define MCF_GPT_GPTCTL1_OUTPUT0_NOTHING ((0x00)) -#define MCF_GPT_GPTCTL1_OUTPUT0_TOGGLE ((0x01)) -#define MCF_GPT_GPTCTL1_OUTPUT0_CLEAR ((0x02)) -#define MCF_GPT_GPTCTL1_OUTPUT0_SET ((0x03)) - -/* Bit definitions and macros for MCF_GPT_GPTCTL2 */ -#define MCF_GPT_GPTCTL2_EDG0A (0x01) -#define MCF_GPT_GPTCTL2_EDG0B (0x02) -#define MCF_GPT_GPTCTL2_EDG1A (0x04) -#define MCF_GPT_GPTCTL2_EDG1B (0x08) -#define MCF_GPT_GPTCTL2_EDG2A (0x10) -#define MCF_GPT_GPTCTL2_EDG2B (0x20) -#define MCF_GPT_GPTCTL2_EDG3A (0x40) -#define MCF_GPT_GPTCTL2_EDG3B (0x80) -#define MCF_GPT_GPTCTL2_INPUT3_DISABLED ((0x00)) -#define MCF_GPT_GPTCTL2_INPUT3_RISING ((0x40)) -#define MCF_GPT_GPTCTL2_INPUT3_FALLING ((0x80)) -#define MCF_GPT_GPTCTL2_INPUT3_ANY ((0xC0)) -#define MCF_GPT_GPTCTL2_INPUT2_DISABLED ((0x00)) -#define MCF_GPT_GPTCTL2_INPUT2_RISING ((0x10)) -#define MCF_GPT_GPTCTL2_INPUT2_FALLING ((0x20)) -#define MCF_GPT_GPTCTL2_INPUT2_ANY ((0x30)) -#define MCF_GPT_GPTCTL2_INPUT1_DISABLED ((0x00)) -#define MCF_GPT_GPTCTL2_INPUT1_RISING ((0x04)) -#define MCF_GPT_GPTCTL2_INPUT1_FALLING ((0x08)) -#define MCF_GPT_GPTCTL2_INPUT1_ANY ((0x0C)) -#define MCF_GPT_GPTCTL2_INPUT0_DISABLED ((0x00)) -#define MCF_GPT_GPTCTL2_INPUT0_RISING ((0x01)) -#define MCF_GPT_GPTCTL2_INPUT0_FALLING ((0x02)) -#define MCF_GPT_GPTCTL2_INPUT0_ANY ((0x03)) - -/* Bit definitions and macros for MCF_GPT_GPTIE */ -#define MCF_GPT_GPTIE_CI0 (0x01) -#define MCF_GPT_GPTIE_CI1 (0x02) -#define MCF_GPT_GPTIE_CI2 (0x04) -#define MCF_GPT_GPTIE_CI3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTSCR2 */ -#define MCF_GPT_GPTSCR2_PR(x) (((x)&0x07)<<0) -#define MCF_GPT_GPTSCR2_TCRE (0x08) -#define MCF_GPT_GPTSCR2_RDPT (0x10) -#define MCF_GPT_GPTSCR2_PUPT (0x20) -#define MCF_GPT_GPTSCR2_TOI (0x80) -#define MCF_GPT_GPTSCR2_PR_1 ((0x00)) -#define MCF_GPT_GPTSCR2_PR_2 ((0x01)) -#define MCF_GPT_GPTSCR2_PR_4 ((0x02)) -#define MCF_GPT_GPTSCR2_PR_8 ((0x03)) -#define MCF_GPT_GPTSCR2_PR_16 ((0x04)) -#define MCF_GPT_GPTSCR2_PR_32 ((0x05)) -#define MCF_GPT_GPTSCR2_PR_64 ((0x06)) -#define MCF_GPT_GPTSCR2_PR_128 ((0x07)) - -/* Bit definitions and macros for MCF_GPT_GPTFLG1 */ -#define MCF_GPT_GPTFLG1_CF0 (0x01) -#define MCF_GPT_GPTFLG1_CF1 (0x02) -#define MCF_GPT_GPTFLG1_CF2 (0x04) -#define MCF_GPT_GPTFLG1_CF3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTFLG2 */ -#define MCF_GPT_GPTFLG2_CF0 (0x01) -#define MCF_GPT_GPTFLG2_CF1 (0x02) -#define MCF_GPT_GPTFLG2_CF2 (0x04) -#define MCF_GPT_GPTFLG2_CF3 (0x08) -#define MCF_GPT_GPTFLG2_TOF (0x80) - -/* Bit definitions and macros for MCF_GPT_GPTC */ -#define MCF_GPT_GPTC_CCNT(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_GPT_GPTPACTL */ -#define MCF_GPT_GPTPACTL_PAI (0x01) -#define MCF_GPT_GPTPACTL_PAOVI (0x02) -#define MCF_GPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) -#define MCF_GPT_GPTPACTL_PEDGE (0x10) -#define MCF_GPT_GPTPACTL_PAMOD (0x20) -#define MCF_GPT_GPTPACTL_PAE (0x40) -#define MCF_GPT_GPTPACTL_CLK_GPTPR ((0x00)) -#define MCF_GPT_GPTPACTL_CLK_PACLK ((0x01)) -#define MCF_GPT_GPTPACTL_CLK_PACLK_256 ((0x02)) -#define MCF_GPT_GPTPACTL_CLK_PACLK_65536 ((0x03)) - -/* Bit definitions and macros for MCF_GPT_GPTPAFLG */ -#define MCF_GPT_GPTPAFLG_PAIF (0x01) -#define MCF_GPT_GPTPAFLG_PAOVF (0x02) - -/* Bit definitions and macros for MCF_GPT_GPTPACNT */ -#define MCF_GPT_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_GPT_GPTPORT */ -#define MCF_GPT_GPTPORT_PORTT(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_GPT_GPTDDR */ -#define MCF_GPT_GPTDDR_DDRT0 (0x01) -#define MCF_GPT_GPTDDR_DDRT1 (0x02) -#define MCF_GPT_GPTDDR_DDRT2 (0x04) -#define MCF_GPT_GPTDDR_DDRT3 (0x08) - -/********************************************************************* -* -* Pulse Width Modulation (PWM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PWM_PWME (*(vuint8 *)(&__IPSBAR[0x1B0000])) -#define MCF_PWM_PWMPOL (*(vuint8 *)(&__IPSBAR[0x1B0001])) -#define MCF_PWM_PWMCLK (*(vuint8 *)(&__IPSBAR[0x1B0002])) -#define MCF_PWM_PWMPRCLK (*(vuint8 *)(&__IPSBAR[0x1B0003])) -#define MCF_PWM_PWMCAE (*(vuint8 *)(&__IPSBAR[0x1B0004])) -#define MCF_PWM_PWMCTL (*(vuint8 *)(&__IPSBAR[0x1B0005])) -#define MCF_PWM_PWMSCLA (*(vuint8 *)(&__IPSBAR[0x1B0008])) -#define MCF_PWM_PWMSCLB (*(vuint8 *)(&__IPSBAR[0x1B0009])) -#define MCF_PWM_PWMCNT0 (*(vuint8 *)(&__IPSBAR[0x1B000C])) -#define MCF_PWM_PWMCNT1 (*(vuint8 *)(&__IPSBAR[0x1B000D])) -#define MCF_PWM_PWMCNT2 (*(vuint8 *)(&__IPSBAR[0x1B000E])) -#define MCF_PWM_PWMCNT3 (*(vuint8 *)(&__IPSBAR[0x1B000F])) -#define MCF_PWM_PWMCNT4 (*(vuint8 *)(&__IPSBAR[0x1B0010])) -#define MCF_PWM_PWMCNT5 (*(vuint8 *)(&__IPSBAR[0x1B0011])) -#define MCF_PWM_PWMCNT6 (*(vuint8 *)(&__IPSBAR[0x1B0012])) -#define MCF_PWM_PWMCNT7 (*(vuint8 *)(&__IPSBAR[0x1B0013])) -#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(&__IPSBAR[0x1B000C+((x)*0x001)])) -#define MCF_PWM_PWMPER0 (*(vuint8 *)(&__IPSBAR[0x1B0014])) -#define MCF_PWM_PWMPER1 (*(vuint8 *)(&__IPSBAR[0x1B0015])) -#define MCF_PWM_PWMPER2 (*(vuint8 *)(&__IPSBAR[0x1B0016])) -#define MCF_PWM_PWMPER3 (*(vuint8 *)(&__IPSBAR[0x1B0017])) -#define MCF_PWM_PWMPER4 (*(vuint8 *)(&__IPSBAR[0x1B0018])) -#define MCF_PWM_PWMPER5 (*(vuint8 *)(&__IPSBAR[0x1B0019])) -#define MCF_PWM_PWMPER6 (*(vuint8 *)(&__IPSBAR[0x1B001A])) -#define MCF_PWM_PWMPER7 (*(vuint8 *)(&__IPSBAR[0x1B001B])) -#define MCF_PWM_PWMPER(x) (*(vuint8 *)(&__IPSBAR[0x1B0014+((x)*0x001)])) -#define MCF_PWM_PWMDTY0 (*(vuint8 *)(&__IPSBAR[0x1B001C])) -#define MCF_PWM_PWMDTY1 (*(vuint8 *)(&__IPSBAR[0x1B001D])) -#define MCF_PWM_PWMDTY2 (*(vuint8 *)(&__IPSBAR[0x1B001E])) -#define MCF_PWM_PWMDTY3 (*(vuint8 *)(&__IPSBAR[0x1B001F])) -#define MCF_PWM_PWMDTY4 (*(vuint8 *)(&__IPSBAR[0x1B0020])) -#define MCF_PWM_PWMDTY5 (*(vuint8 *)(&__IPSBAR[0x1B0021])) -#define MCF_PWM_PWMDTY6 (*(vuint8 *)(&__IPSBAR[0x1B0022])) -#define MCF_PWM_PWMDTY7 (*(vuint8 *)(&__IPSBAR[0x1B0023])) -#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(&__IPSBAR[0x1B001C+((x)*0x001)])) -#define MCF_PWM_PWMSDN (*(vuint8 *)(&__IPSBAR[0x1B0024])) - -/* Bit definitions and macros for MCF_PWM_PWME */ -#define MCF_PWM_PWME_PWME0 (0x01) -#define MCF_PWM_PWME_PWME1 (0x02) -#define MCF_PWM_PWME_PWME2 (0x04) -#define MCF_PWM_PWME_PWME3 (0x08) - -/* Bit definitions and macros for MCF_PWM_PWMPOL */ -#define MCF_PWM_PWMPOL_PPOL0 (0x01) -#define MCF_PWM_PWMPOL_PPOL1 (0x02) -#define MCF_PWM_PWMPOL_PPOL2 (0x04) -#define MCF_PWM_PWMPOL_PPOL3 (0x08) - -/* Bit definitions and macros for MCF_PWM_PWMCLK */ -#define MCF_PWM_PWMCLK_PCLK0 (0x01) -#define MCF_PWM_PWMCLK_PCLK1 (0x02) -#define MCF_PWM_PWMCLK_PCLK2 (0x04) -#define MCF_PWM_PWMCLK_PCLK3 (0x08) - -/* Bit definitions and macros for MCF_PWM_PWMPRCLK */ -#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x07)<<0) -#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_PWM_PWMCAE */ -#define MCF_PWM_PWMCAE_CAE0 (0x01) -#define MCF_PWM_PWMCAE_CAE1 (0x02) -#define MCF_PWM_PWMCAE_CAE2 (0x04) -#define MCF_PWM_PWMCAE_CAE3 (0x08) - -/* Bit definitions and macros for MCF_PWM_PWMCTL */ -#define MCF_PWM_PWMCTL_PFRZ (0x04) -#define MCF_PWM_PWMCTL_PSWAI (0x08) -#define MCF_PWM_PWMCTL_CON01 (0x10) -#define MCF_PWM_PWMCTL_CON23 (0x20) - -/* Bit definitions and macros for MCF_PWM_PWMSCLA */ -#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMSCLB */ -#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMCNT */ -#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMPER */ -#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMDTY */ -#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMSDN */ -#define MCF_PWM_PWMSDN_SDNEN (0x01) -#define MCF_PWM_PWMSDN_PWM7IL (0x02) -#define MCF_PWM_PWMSDN_PWM7IN (0x04) -#define MCF_PWM_PWMSDN_LVL (0x10) -#define MCF_PWM_PWMSDN_RESTART (0x20) -#define MCF_PWM_PWMSDN_IE (0x40) -#define MCF_PWM_PWMSDN_IF (0x80) - -/********************************************************************* -* -* FlexCAN Module (CAN) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CAN_CANMCR (*(vuint32*)(&__IPSBAR[0x1C0000])) -#define MCF_CAN_CANCTRL (*(vuint32*)(&__IPSBAR[0x1C0004])) -#define MCF_CAN_TIMER (*(vuint32*)(&__IPSBAR[0x1C0008])) -#define MCF_CAN_RXGMASK (*(vuint32*)(&__IPSBAR[0x1C0010])) -#define MCF_CAN_RX14MASK (*(vuint32*)(&__IPSBAR[0x1C0014])) -#define MCF_CAN_RX15MASK (*(vuint32*)(&__IPSBAR[0x1C0018])) -#define MCF_CAN_ERRCNT (*(vuint32*)(&__IPSBAR[0x1C001C])) -#define MCF_CAN_ERRSTAT (*(vuint32*)(&__IPSBAR[0x1C0020])) -#define MCF_CAN_IMASK (*(vuint32*)(&__IPSBAR[0x1C0028])) -#define MCF_CAN_IFLAG (*(vuint32*)(&__IPSBAR[0x1C0030])) - -/* Bit definitions and macros for MCF_CAN_CANMCR */ -#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) -#define MCF_CAN_CANMCR_SUPV (0x00800000) -#define MCF_CAN_CANMCR_FRZACK (0x01000000) -#define MCF_CAN_CANMCR_SOFTRST (0x02000000) -#define MCF_CAN_CANMCR_HALT (0x10000000) -#define MCF_CAN_CANMCR_FRZ (0x40000000) -#define MCF_CAN_CANMCR_MDIS (0x80000000) - -/* Bit definitions and macros for MCF_CAN_CANCTRL */ -#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) -#define MCF_CAN_CANCTRL_LOM (0x00000008) -#define MCF_CAN_CANCTRL_LBUF (0x00000010) -#define MCF_CAN_CANCTRL_TSYNC (0x00000020) -#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) -#define MCF_CAN_CANCTRL_SAMP (0x00000080) -#define MCF_CAN_CANCTRL_LPB (0x00001000) -#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) -#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) -#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) -#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) -#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) -#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) -#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_CAN_TIMER */ -#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RXGMASK */ -#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX14MASK */ -#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX15MASK */ -#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_ERRCNT */ -#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) -#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for MCF_CAN_ERRSTAT */ -#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) -#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) -#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) -#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) -#define MCF_CAN_ERRSTAT_TXRX (0x00000040) -#define MCF_CAN_ERRSTAT_IDLE (0x00000080) -#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) -#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) -#define MCF_CAN_ERRSTAT_STFERR (0x00000400) -#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) -#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) -#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) -#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) -#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) -#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) -#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) - -/* Bit definitions and macros for MCF_CAN_IMASK */ -#define MCF_CAN_IMASK_BUF(x) (1<<x) - -/* Bit definitions and macros for MCF_CAN_IFLAG */ -#define MCF_CAN_IFLAG_BUF(x) (1<<x) - -/********************************************************************* -* -* ColdFire Flash Module (CFM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CFM_CFMMCR (*(vuint16*)(&__IPSBAR[0x1D0000])) -#define MCF_CFM_CFMCLKD (*(vuint8 *)(&__IPSBAR[0x1D0002])) -#define MCF_CFM_CFMSEC (*(vuint32*)(&__IPSBAR[0x1D0008])) -#define MCF_CFM_CFMPROT (*(vuint32*)(&__IPSBAR[0x1D0010])) -#define MCF_CFM_CFMSACC (*(vuint32*)(&__IPSBAR[0x1D0014])) -#define MCF_CFM_CFMDACC (*(vuint32*)(&__IPSBAR[0x1D0018])) -#define MCF_CFM_CFMUSTAT (*(vuint8 *)(&__IPSBAR[0x1D0020])) -#define MCF_CFM_CFMCMD (*(vuint8 *)(&__IPSBAR[0x1D0024])) - -/* Bit definitions and macros for MCF_CFM_CFMMCR */ -#define MCF_CFM_CFMMCR_KEYACC (0x0020) -#define MCF_CFM_CFMMCR_CCIE (0x0040) -#define MCF_CFM_CFMMCR_CBEIE (0x0080) -#define MCF_CFM_CFMMCR_AEIE (0x0100) -#define MCF_CFM_CFMMCR_PVIE (0x0200) -#define MCF_CFM_CFMMCR_LOCK (0x0400) - -/* Bit definitions and macros for MCF_CFM_CFMCLKD */ -#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0) -#define MCF_CFM_CFMCLKD_PRDIV8 (0x40) -#define MCF_CFM_CFMCLKD_DIVLD (0x80) - -/* Bit definitions and macros for MCF_CFM_CFMSEC */ -#define MCF_CFM_CFMSEC_SEC(x) (((x)&0x0000FFFF)<<0) -#define MCF_CFM_CFMSEC_SECSTAT (0x40000000) -#define MCF_CFM_CFMSEC_KEYEN (0x80000000) - -/* Bit definitions and macros for MCF_CFM_CFMUSTAT */ -#define MCF_CFM_CFMUSTAT_BLANK (0x04) -#define MCF_CFM_CFMUSTAT_ACCERR (0x10) -#define MCF_CFM_CFMUSTAT_PVIOL (0x20) -#define MCF_CFM_CFMUSTAT_CCIF (0x40) -#define MCF_CFM_CFMUSTAT_CBEIF (0x80) - -/* Bit definitions and macros for MCF_CFM_CFMCMD */ -#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0) -#define MCF_CFM_CFMCMD_RDARY1 (0x05) -#define MCF_CFM_CFMCMD_PGM (0x20) -#define MCF_CFM_CFMCMD_PGERS (0x40) -#define MCF_CFM_CFMCMD_MASERS (0x41) -#define MCF_CFM_CFMCMD_PGERSVER (0x06) - -/********************************************************************* -* -* Interrupt Controller (INTC_IACK) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC_IACK_GSWIACK (*(vuint8 *)(&__IPSBAR[0x000FE0])) -#define MCF_INTC_IACK_GL1IACK (*(vuint8 *)(&__IPSBAR[0x000FE4])) -#define MCF_INTC_IACK_GL2IACK (*(vuint8 *)(&__IPSBAR[0x000FE8])) -#define MCF_INTC_IACK_GL3IACK (*(vuint8 *)(&__IPSBAR[0x000FEC])) -#define MCF_INTC_IACK_GL4IACK (*(vuint8 *)(&__IPSBAR[0x000FF0])) -#define MCF_INTC_IACK_GL5IACK (*(vuint8 *)(&__IPSBAR[0x000FF4])) -#define MCF_INTC_IACK_GL6IACK (*(vuint8 *)(&__IPSBAR[0x000FF8])) -#define MCF_INTC_IACK_GL7IACK (*(vuint8 *)(&__IPSBAR[0x000FFC])) -#define MCF_INTC_IACK_GLIACK(x) (*(vuint8 *)(&__IPSBAR[0x000FE4+((x-1)*0x004)])) - -/* Bit definitions and macros for MCF_INTC_IACK_GSWIACK */ -#define MCF_INTC_IACK_GSWIACK_VECTOR(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_INTC_IACK_GLIACK */ -#define MCF_INTC_IACK_GLIACK_VECTOR(x) (((x)&0xFF)<<0) - -/********************************************************************* -* -* Fast Ethernet Controller (FEC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_FEC_EIR (*(vuint32*)(&__IPSBAR[0x001004])) -#define MCF_FEC_EIMR (*(vuint32*)(&__IPSBAR[0x001008])) -#define MCF_FEC_RDAR (*(vuint32*)(&__IPSBAR[0x001010])) -#define MCF_FEC_TDAR (*(vuint32*)(&__IPSBAR[0x001014])) -#define MCF_FEC_ECR (*(vuint32*)(&__IPSBAR[0x001024])) -#define MCF_FEC_MMFR (*(vuint32*)(&__IPSBAR[0x001040])) -#define MCF_FEC_MSCR (*(vuint32*)(&__IPSBAR[0x001044])) -#define MCF_FEC_MIBC (*(vuint32*)(&__IPSBAR[0x001064])) -#define MCF_FEC_RCR (*(vuint32*)(&__IPSBAR[0x001084])) -#define MCF_FEC_TCR (*(vuint32*)(&__IPSBAR[0x0010C4])) -#define MCF_FEC_PALR (*(vuint32*)(&__IPSBAR[0x0010E4])) -#define MCF_FEC_PAUR (*(vuint32*)(&__IPSBAR[0x0010E8])) -#define MCF_FEC_OPD (*(vuint32*)(&__IPSBAR[0x0010EC])) -#define MCF_FEC_IAUR (*(vuint32*)(&__IPSBAR[0x001118])) -#define MCF_FEC_IALR (*(vuint32*)(&__IPSBAR[0x00111C])) -#define MCF_FEC_GAUR (*(vuint32*)(&__IPSBAR[0x001120])) -#define MCF_FEC_GALR (*(vuint32*)(&__IPSBAR[0x001124])) -#define MCF_FEC_TFWR (*(vuint32*)(&__IPSBAR[0x001144])) -#define MCF_FEC_FRBR (*(vuint32*)(&__IPSBAR[0x00114C])) -#define MCF_FEC_FRSR (*(vuint32*)(&__IPSBAR[0x001150])) -#define MCF_FEC_ERDSR (*(vuint32*)(&__IPSBAR[0x001180])) -#define MCF_FEC_ETDSR (*(vuint32*)(&__IPSBAR[0x001184])) -#define MCF_FEC_EMRBR (*(vuint32*)(&__IPSBAR[0x001188])) -#define MCF_FEC_RMON_T_DROP (*(vuint32*)(&__IPSBAR[0x001200])) -#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(&__IPSBAR[0x001204])) -#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(&__IPSBAR[0x001208])) -#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(&__IPSBAR[0x00120C])) -#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x001210])) -#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x001214])) -#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(&__IPSBAR[0x001218])) -#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(&__IPSBAR[0x00121C])) -#define MCF_FEC_RMON_T_JAB (*(vuint32*)(&__IPSBAR[0x001220])) -#define MCF_FEC_RMON_T_COL (*(vuint32*)(&__IPSBAR[0x001224])) -#define MCF_FEC_RMON_T_P64 (*(vuint32*)(&__IPSBAR[0x001228])) -#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(&__IPSBAR[0x00122C])) -#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(&__IPSBAR[0x001230])) -#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(&__IPSBAR[0x001234])) -#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(&__IPSBAR[0x001238])) -#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x00123C])) -#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x001240])) -#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(&__IPSBAR[0x001244])) -#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(&__IPSBAR[0x001248])) -#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(&__IPSBAR[0x00124C])) -#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(&__IPSBAR[0x001250])) -#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(&__IPSBAR[0x001254])) -#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(&__IPSBAR[0x001258])) -#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(&__IPSBAR[0x00125C])) -#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(&__IPSBAR[0x001260])) -#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(&__IPSBAR[0x001264])) -#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(&__IPSBAR[0x001268])) -#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(&__IPSBAR[0x00126C])) -#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(&__IPSBAR[0x001270])) -#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x001274])) -#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(&__IPSBAR[0x001284])) -#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(&__IPSBAR[0x001288])) -#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(&__IPSBAR[0x00128C])) -#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x001290])) -#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x001294])) -#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(&__IPSBAR[0x001298])) -#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(&__IPSBAR[0x00129C])) -#define MCF_FEC_RMON_R_JAB (*(vuint32*)(&__IPSBAR[0x0012A0])) -#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(&__IPSBAR[0x0012A4])) -#define MCF_FEC_RMON_R_P64 (*(vuint32*)(&__IPSBAR[0x0012A8])) -#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(&__IPSBAR[0x0012AC])) -#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(&__IPSBAR[0x0012B0])) -#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(&__IPSBAR[0x0012B4])) -#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(&__IPSBAR[0x0012B8])) -#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x0012C0])) -#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(&__IPSBAR[0x0012BC])) -#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(&__IPSBAR[0x0012C4])) -#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(&__IPSBAR[0x0012C8])) -#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(&__IPSBAR[0x0012CC])) -#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(&__IPSBAR[0x0012D0])) -#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(&__IPSBAR[0x0012D4])) -#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(&__IPSBAR[0x0012D8])) -#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(&__IPSBAR[0x0012DC])) -#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x0012E0])) - -/* Bit definitions and macros for MCF_FEC_EIR */ -#define MCF_FEC_EIR_UN (0x00080000) -#define MCF_FEC_EIR_RL (0x00100000) -#define MCF_FEC_EIR_LC (0x00200000) -#define MCF_FEC_EIR_EBERR (0x00400000) -#define MCF_FEC_EIR_MII (0x00800000) -#define MCF_FEC_EIR_RXB (0x01000000) -#define MCF_FEC_EIR_RXF (0x02000000) -#define MCF_FEC_EIR_TXB (0x04000000) -#define MCF_FEC_EIR_TXF (0x08000000) -#define MCF_FEC_EIR_GRA (0x10000000) -#define MCF_FEC_EIR_BABT (0x20000000) -#define MCF_FEC_EIR_BABR (0x40000000) -#define MCF_FEC_EIR_HBERR (0x80000000) -#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) - -/* Bit definitions and macros for MCF_FEC_EIMR */ -#define MCF_FEC_EIMR_UN (0x00080000) -#define MCF_FEC_EIMR_RL (0x00100000) -#define MCF_FEC_EIMR_LC (0x00200000) -#define MCF_FEC_EIMR_EBERR (0x00400000) -#define MCF_FEC_EIMR_MII (0x00800000) -#define MCF_FEC_EIMR_RXB (0x01000000) -#define MCF_FEC_EIMR_RXF (0x02000000) -#define MCF_FEC_EIMR_TXB (0x04000000) -#define MCF_FEC_EIMR_TXF (0x08000000) -#define MCF_FEC_EIMR_GRA (0x10000000) -#define MCF_FEC_EIMR_BABT (0x20000000) -#define MCF_FEC_EIMR_BABR (0x40000000) -#define MCF_FEC_EIMR_HBERR (0x80000000) -#define MCF_FEC_EIMR_MASK_ALL (0x00000000) -#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) - -/* Bit definitions and macros for MCF_FEC_RDAR */ -#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_TDAR */ -#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_ECR */ -#define MCF_FEC_ECR_RESET (0x00000001) -#define MCF_FEC_ECR_ETHER_EN (0x00000002) - -/* Bit definitions and macros for MCF_FEC_MMFR */ -#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) -#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) -#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) -#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) -#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) -#define MCF_FEC_MMFR_ST_01 (0x40000000) -#define MCF_FEC_MMFR_OP_READ (0x20000000) -#define MCF_FEC_MMFR_OP_WRITE (0x10000000) -#define MCF_FEC_MMFR_TA_10 (0x00020000) - -/* Bit definitions and macros for MCF_FEC_MSCR */ -#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) -#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) - -/* Bit definitions and macros for MCF_FEC_MIBC */ -#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) -#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) - -/* Bit definitions and macros for MCF_FEC_RCR */ -#define MCF_FEC_RCR_LOOP (0x00000001) -#define MCF_FEC_RCR_DRT (0x00000002) -#define MCF_FEC_RCR_MII_MODE (0x00000004) -#define MCF_FEC_RCR_PROM (0x00000008) -#define MCF_FEC_RCR_BC_REJ (0x00000010) -#define MCF_FEC_RCR_FCE (0x00000020) -#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) - -/* Bit definitions and macros for MCF_FEC_TCR */ -#define MCF_FEC_TCR_GTS (0x00000001) -#define MCF_FEC_TCR_HBC (0x00000002) -#define MCF_FEC_TCR_FDEN (0x00000004) -#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) -#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) - -/* Bit definitions and macros for MCF_FEC_PALR */ -#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_PAUR */ -#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_OPD */ -#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_IAUR */ -#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_IALR */ -#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_GAUR */ -#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_GALR */ -#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_TFWR */ -#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) - -/* Bit definitions and macros for MCF_FEC_FRBR */ -#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_FRSR */ -#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_ERDSR */ -#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_ETDSR */ -#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_EMRBR */ -#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) - -/* buffer descriptor fields */ -/* Tx BD fields */ -#define MCF_FEC_TXBD_R (1 << 15) -#define MCF_FEC_TXBD_W (1 << 13) -#define MCF_FEC_TXBD_L (1 << 11) -#define MCF_FEC_TXBD_TC (1 << 10) - -/* Rx BD fields */ -#define MCF_FEC_RXBD_E (1 << 15) -#define MCF_FEC_RXBD_RO1 (1 << 14) -#define MCF_FEC_RXBD_W (1 << 13) -#define MCF_FEC_RXBD_L (1 << 11) -#define MCF_FEC_RXBD_LG (1 << 5) -#define MCF_FEC_RXBD_NO (1 << 4) -#define MCF_FEC_RXBD_CR (1 << 2) -#define MCF_FEC_RXBD_OV (1 << 1) -#define MCF_FEC_RXBD_TR (1 << 0) - -/********************************************************************* -* -* Random Number Generator (RNG) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RNG_RNGCR (*(vuint32*)(&__IPSBAR[0x1F0000])) -#define MCF_RNG_RNGSR (*(vuint32*)(&__IPSBAR[0x1F0004])) -#define MCF_RNG_RNGER (*(vuint32*)(&__IPSBAR[0x1F0008])) -#define MCF_RNG_RNGOUT (*(vuint32*)(&__IPSBAR[0x1F000C])) - -/* Bit definitions and macros for MCF_RNG_RNGCR */ -#define MCF_RNG_RNGCR_GO (0x00000001) -#define MCF_RNG_RNGCR_HA (0x00000002) -#define MCF_RNG_RNGCR_IM (0x00000004) -#define MCF_RNG_RNGCR_CI (0x00000008) - -/* Bit definitions and macros for MCF_RNG_RNGSR */ -#define MCF_RNG_RNGSR_SV (0x00000001) -#define MCF_RNG_RNGSR_LRS (0x00000002) -#define MCF_RNG_RNGSR_FUF (0x00000004) -#define MCF_RNG_RNGSR_EI (0x00000008) -#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) -#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) - -/* Bit definitions and macros for MCF_RNG_RNGER */ -#define MCF_RNG_RNGER_ENTROPY(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_RNG_RNGOUT */ -#define MCF_RNG_RNGOUT_OUTPUT(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* -* -* Real-time Clock (RTC) -* -*********************************************************************/ -/* Register read/write macros */ -#define MCF_RTC_HOURMIN (*(vuint32*)(&__IPSBAR[0x180000])) -#define MCF_RTC_SECONDS (*(vuint32*)(&__IPSBAR[0x180004])) -#define MCF_RTC_ALRM_HM (*(vuint32*)(&__IPSBAR[0x180008])) -#define MCF_RTC_ALRM_SEC (*(vuint32*)(&__IPSBAR[0x18000C])) -#define MCF_RTC_CR (*(vuint32*)(&__IPSBAR[0x180010])) -#define MCF_RTC_ISR (*(vuint32*)(&__IPSBAR[0x180014])) -#define MCF_RTC_IER (*(vuint32*)(&__IPSBAR[0x180018])) -#define MCF_RTC_STPWCH (*(vuint32*)(&__IPSBAR[0x18001C])) -#define MCF_RTC_DAYS (*(vuint32*)(&__IPSBAR[0x180020])) -#define MCF_RTC_ALRM_DAY (*(vuint32*)(&__IPSBAR[0x180024])) -#define MCF_RTC_OSC_CNT_U (*(vuint32*)(&__IPSBAR[0x180034])) -#define MCF_RTC_OSC_CNT_L (*(vuint32*)(&__IPSBAR[0x180038])) - -/* Bit definitions and macros for MCF_RTC_HOURMIN */ -#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F)<<0) -#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8) - -/* Bit definitions and macros for MCF_RTC_SECONDS */ -#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x0000003F)<<0) - -/* Bit definitions and macros for MCF_RTC_ALRM_HM */ -#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F)<<0) -#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8) - -/* Bit definitions and macros for MCF_RTC_ALRM_SEC */ -#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F)<<0) - -/* Bit definitions and macros for MCF_RTC_CR */ -#define MCF_RTC_CR_SWR (0x00000001) -#define MCF_RTC_CR_EN (0x00000080) - -/* Bit definitions and macros for MCF_RTC_ISR */ -#define MCF_RTC_ISR_SW (0x00000001) -#define MCF_RTC_ISR_MIN (0x00000002) -#define MCF_RTC_ISR_ALM (0x00000004) -#define MCF_RTC_ISR_DAY (0x00000008) -#define MCF_RTC_ISR_1HZ (0x00000010) -#define MCF_RTC_ISR_HR (0x00000020) - -/* Bit definitions and macros for MCF_RTC_IER */ -#define MCF_RTC_IER_SW (0x00000001) -#define MCF_RTC_IER_MIN (0x00000002) -#define MCF_RTC_IER_ALM (0x00000004) -#define MCF_RTC_IER_DAY (0x00000008) -#define MCF_RTC_IER_1HZ (0x00000010) -#define MCF_RTC_IER_HR (0x00000020) - -/* Bit definitions and macros for MCF_RTC_STPWCH */ -#define MCF_RTC_STPWCH_CNT(x) (((x)&0x0000003F)<<0) - -/* Bit definitions and macros for MCF_RTC_DAYS */ -#define MCF_RTC_DAYS_DAYS(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_RTC_ALRM_DAY */ -#define MCF_RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF)<<0) - -#define MCF_RTC_RTCGOCNT(x) (((x)&0x0000FFFF)<<0) -/********************************************************************/ - -#endif /* __MCF5225x_H__ */ diff --git a/c/src/lib/libcpu/m68k/mcf5235/include/mcf5235.h b/c/src/lib/libcpu/m68k/mcf5235/include/mcf5235.h deleted file mode 100644 index 87e0d91541..0000000000 --- a/c/src/lib/libcpu/m68k/mcf5235/include/mcf5235.h +++ /dev/null @@ -1,2998 +0,0 @@ -/* - ******************************************* - * Definitions from Motorola/FreeScale * - ******************************************* - */ - -/* - * File: mcf5235.h - * Purpose: MCF5235 definitions - * - * Notes: - */ - -#ifndef _CPU_MCF5235_H -#define _CPU_MCF5235_H - -#include <stdint.h> - -/********************************************************************/ - -/* - * File: mcf5xxx.h - * Purpose: Definitions common to all ColdFire processors - * - * Notes: - */ - -#ifndef _CPU_MCF5XXX_H -#define _CPU_MCF5XXX_H - -/***********************************************************************/ -/* - * The basic data types - */ - -typedef unsigned char uint8; /* 8 bits */ -typedef unsigned short int uint16; /* 16 bits */ -typedef unsigned long int uint32; /* 32 bits */ - -typedef signed char int8; /* 8 bits */ -typedef signed short int int16; /* 16 bits */ -typedef signed long int int32; /* 32 bits */ - -typedef volatile uint8 vuint8; /* 8 bits */ -typedef volatile uint16 vuint16; /* 16 bits */ -typedef volatile uint32 vuint32; /* 32 bits */ - -/***********************************************************************/ -/* - * Common M68K & ColdFire definitions - * - ***********************************************************************/ - -#define ADDRESS uint32 -#define INSTRUCTION uint16 -#define ILLEGAL 0x4AFC -#define CPU_WORD_SIZE 16 - -#define MCF5XXX_SR_T (0x8000) -#define MCF5XXX_SR_S (0x2000) -#define MCF5XXX_SR_M (0x1000) -#define MCF5XXX_SR_IPL (0x0700) -#define MCF5XXX_SR_IPL_0 (0x0000) -#define MCF5XXX_SR_IPL_1 (0x0100) -#define MCF5XXX_SR_IPL_2 (0x0200) -#define MCF5XXX_SR_IPL_3 (0x0300) -#define MCF5XXX_SR_IPL_4 (0x0400) -#define MCF5XXX_SR_IPL_5 (0x0500) -#define MCF5XXX_SR_IPL_6 (0x0600) -#define MCF5XXX_SR_IPL_7 (0x0700) -#define MCF5XXX_SR_X (0x0010) -#define MCF5XXX_SR_N (0x0008) -#define MCF5XXX_SR_Z (0x0004) -#define MCF5XXX_SR_V (0x0002) -#define MCF5XXX_SR_C (0x0001) - -#define MCF5XXX_CACR_CENB (0x80000000) -#define MCF5XXX_CACR_CPDI (0x10000000) -#define MCF5XXX_CACR_CPD (0x10000000) -#define MCF5XXX_CACR_CFRZ (0x08000000) -#define MCF5XXX_CACR_CINV (0x01000000) -#define MCF5XXX_CACR_DIDI (0x00800000) -#define MCF5XXX_CACR_DISD (0x00400000) -#define MCF5XXX_CACR_INVI (0x00200000) -#define MCF5XXX_CACR_INVD (0x00100000) -#define MCF5XXX_CACR_CEIB (0x00000400) -#define MCF5XXX_CACR_DCM_WR (0x00000000) -#define MCF5XXX_CACR_DCM_CB (0x00000100) -#define MCF5XXX_CACR_DCM_IP (0x00000200) -#define MCF5XXX_CACR_DCM (0x00000200) -#define MCF5XXX_CACR_DCM_II (0x00000300) -#define MCF5XXX_CACR_DBWE (0x00000100) -#define MCF5XXX_CACR_DWP (0x00000020) -#define MCF5XXX_CACR_EUST (0x00000010) -#define MCF5XXX_CACR_CLNF_00 (0x00000000) -#define MCF5XXX_CACR_CLNF_01 (0x00000002) -#define MCF5XXX_CACR_CLNF_10 (0x00000004) -#define MCF5XXX_CACR_CLNF_11 (0x00000006) - -#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) -#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) -#define MCF5XXX_ACR_EN (0x00008000) -#define MCF5XXX_ACR_SM_USER (0x00000000) -#define MCF5XXX_ACR_SM_SUPER (0x00002000) -#define MCF5XXX_ACR_SM_IGNORE (0x00006000) -#define MCF5XXX_ACR_ENIB (0x00000080) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_DCM_WR (0x00000000) -#define MCF5XXX_ACR_DCM_CB (0x00000020) -#define MCF5XXX_ACR_DCM_IP (0x00000040) -#define MCF5XXX_ACR_DCM_II (0x00000060) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_BWE (0x00000020) -#define MCF5XXX_ACR_WP (0x00000004) - -#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) -#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) -#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) -#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) -#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) -#define MCF5XXX_RAMBAR_WP (0x00000100) -#define MCF5XXX_RAMBAR_CI (0x00000020) -#define MCF5XXX_RAMBAR_SC (0x00000010) -#define MCF5XXX_RAMBAR_SD (0x00000008) -#define MCF5XXX_RAMBAR_UC (0x00000004) -#define MCF5XXX_RAMBAR_UD (0x00000002) -#define MCF5XXX_RAMBAR_V (0x00000001) - -/***********************************************************************/ -/* - * The ColdFire family of processors has a simplified exception stack - * frame that looks like the following: - * - * 3322222222221111 111111 - * 1098765432109876 5432109876543210 - * 8 +----------------+----------------+ - * | Program Counter | - * 4 +----------------+----------------+ - * |FS/Fmt/Vector/FS| SR | - * SP --> 0 +----------------+----------------+ - * - * The stack self-aligns to a 4-byte boundary at an exception, with - * the FS/Fmt/Vector/FS field indicating the size of the adjustment - * (SP += 0,1,2,3 bytes). - */ - -#define MCF5XXX_RD_SF_FORMAT(PTR) \ - ((*((uint16 *)(PTR)) >> 12) & 0x00FF) - -#define MCF5XXX_RD_SF_VECTOR(PTR) \ - ((*((uint16 *)(PTR)) >> 2) & 0x00FF) - -#define MCF5XXX_RD_SF_FS(PTR) \ - ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) ) - -#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1) -#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1) - -/********************************************************************/ -/* - * Functions provided by mcf5xxx.s - */ - -int asm_set_ipl (uint32); -void mcf5xxx_wr_cacr (uint32); -void mcf5xxx_wr_acr0 (uint32); -void mcf5xxx_wr_acr1 (uint32); -void mcf5xxx_wr_acr2 (uint32); -void mcf5xxx_wr_acr3 (uint32); -void mcf5xxx_wr_other_a7 (uint32); -void mcf5xxx_wr_other_sp (uint32); -void mcf5xxx_wr_vbr (uint32); -void mcf5xxx_wr_macsr (uint32); -void mcf5xxx_wr_mask (uint32); -void mcf5xxx_wr_acc0 (uint32); -void mcf5xxx_wr_accext01 (uint32); -void mcf5xxx_wr_accext23 (uint32); -void mcf5xxx_wr_acc1 (uint32); -void mcf5xxx_wr_acc2 (uint32); -void mcf5xxx_wr_acc3 (uint32); -void mcf5xxx_wr_sr (uint32); -void mcf5xxx_wr_rambar0 (uint32); -void mcf5xxx_wr_rambar1 (uint32); -void mcf5xxx_wr_mbar (uint32); -void mcf5xxx_wr_mbar0 (uint32); -void mcf5xxx_wr_mbar1 (uint32); - -/********************************************************************/ - -#endif /* _CPU_MCF5XXX_H */ - - -/********************************************************************/ -/* - * Memory map definitions from linker command files - */ -extern char __IPSBAR[]; - -/********************************************************************* -* -* Watchdog Timer Modules (WTM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_WCR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140000))) -#define MCF5235_WMR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140002))) -#define MCF5235_WCNTR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140004))) -#define MCF5235_WSR (*(vuint16*)((uintptr_t)__IPSBAR + (0x140006))) - -/* Bit definitions and macros for MCF5235_WTM_WCR */ -#define MCF5235_WCR_EN (0x0001) -#define MCF5235_WCR_HALTED (0x0002) -#define MCF5235_WCR_DOZE (0x0004) -#define MCF5235_WCR_WAIT (0x0008) - -/* Bit definitions and macros for MCF5235_WTM_WMR */ -#define MCF5235_WMR_WM0 (0x0001) -#define MCF5235_WMR_WM1 (0x0002) -#define MCF5235_WMR_WM2 (0x0004) -#define MCF5235_WMR_WM3 (0x0008) -#define MCF5235_WMR_WM4 (0x0010) -#define MCF5235_WMR_WM5 (0x0020) -#define MCF5235_WMR_WM6 (0x0040) -#define MCF5235_WMR_WM7 (0x0080) -#define MCF5235_WMR_WM8 (0x0100) -#define MCF5235_WMR_WM9 (0x0200) -#define MCF5235_WMR_WM10 (0x0400) -#define MCF5235_WMR_WM11 (0x0800) -#define MCF5235_WMR_WM12 (0x1000) -#define MCF5235_WMR_WM13 (0x2000) -#define MCF5235_WMR_WM14 (0x4000) -#define MCF5235_WMR_WM15 (0x8000) - -/* Bit definitions and macros for MCF5235_WTM_WCNTR */ -#define MCF5235_WCNTR_WC0 (0x0001) -#define MCF5235_WCNTR_WC1 (0x0002) -#define MCF5235_WCNTR_WC2 (0x0004) -#define MCF5235_WCNTR_WC3 (0x0008) -#define MCF5235_WCNTR_WC4 (0x0010) -#define MCF5235_WCNTR_WC5 (0x0020) -#define MCF5235_WCNTR_WC6 (0x0040) -#define MCF5235_WCNTR_WC7 (0x0080) -#define MCF5235_WCNTR_WC8 (0x0100) -#define MCF5235_WCNTR_WC9 (0x0200) -#define MCF5235_WCNTR_WC10 (0x0400) -#define MCF5235_WCNTR_WC11 (0x0800) -#define MCF5235_WCNTR_WC12 (0x1000) -#define MCF5235_WCNTR_WC13 (0x2000) -#define MCF5235_WCNTR_WC14 (0x4000) -#define MCF5235_WCNTR_WC15 (0x8000) -#define MCF5235_WSR_WS0 (0x0001) -#define MCF5235_WSR_WS1 (0x0002) -#define MCF5235_WSR_WS2 (0x0004) -#define MCF5235_WSR_WS3 (0x0008) -#define MCF5235_WSR_WS4 (0x0010) -#define MCF5235_WSR_WS5 (0x0020) -#define MCF5235_WSR_WS6 (0x0040) -#define MCF5235_WSR_WS7 (0x0080) -#define MCF5235_WSR_WS8 (0x0100) -#define MCF5235_WSR_WS9 (0x0200) -#define MCF5235_WSR_WS10 (0x0400) -#define MCF5235_WSR_WS11 (0x0800) -#define MCF5235_WSR_WS12 (0x1000) -#define MCF5235_WSR_WS13 (0x2000) -#define MCF5235_WSR_WS14 (0x4000) -#define MCF5235_WSR_WS15 (0x8000) - -/********************************************************************/ - -/********************************************************************* -* -* Universal Asynchronous Receiver Transmitter (UART) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_UART_UMR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000200))) -#define MCF5235_UART_USR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204))) -#define MCF5235_UART_UCSR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204))) -#define MCF5235_UART_UCR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000208))) -#define MCF5235_UART_URB0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C))) -#define MCF5235_UART_UTB0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C))) -#define MCF5235_UART_UIPCR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210))) -#define MCF5235_UART_UACR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210))) -#define MCF5235_UART_UISR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214))) -#define MCF5235_UART_UIMR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214))) -#define MCF5235_UART_UBG10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000218))) -#define MCF5235_UART_UBG20 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00021C))) -#define MCF5235_UART_UIP0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000234))) -#define MCF5235_UART_UOP10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000238))) -#define MCF5235_UART_UOP00 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00023C))) -#define MCF5235_UART_UMR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000240))) -#define MCF5235_UART_USR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000244))) -#define MCF5235_UART_UCSR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000244))) -#define MCF5235_UART_UCR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000248))) -#define MCF5235_UART_URB1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00024C))) -#define MCF5235_UART_UTB1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00024C))) -#define MCF5235_UART_UIPCR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000250))) -#define MCF5235_UART_UACR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000250))) -#define MCF5235_UART_UISR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000254))) -#define MCF5235_UART_UIMR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000254))) -#define MCF5235_UART_UBG11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000258))) -#define MCF5235_UART_UBG21 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00025C))) -#define MCF5235_UART_UIP1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000274))) -#define MCF5235_UART_UOP11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000278))) -#define MCF5235_UART_UOP01 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00027C))) -#define MCF5235_UART_UMR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000280))) -#define MCF5235_UART_USR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000284))) -#define MCF5235_UART_UCSR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000284))) -#define MCF5235_UART_UCR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000288))) -#define MCF5235_UART_URB2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00028C))) -#define MCF5235_UART_UTB2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00028C))) -#define MCF5235_UART_UIPCR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000290))) -#define MCF5235_UART_UACR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000290))) -#define MCF5235_UART_UISR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000294))) -#define MCF5235_UART_UIMR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000294))) -#define MCF5235_UART_UBG12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000298))) -#define MCF5235_UART_UBG22 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00029C))) -#define MCF5235_UART_UIP2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0002B4))) -#define MCF5235_UART_UOP12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0002B8))) -#define MCF5235_UART_UOP02 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0002BC))) -#define MCF5235_UART_UMR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000200+((x)*0x040)))) -#define MCF5235_UART_USR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204+((x)*0x040)))) -#define MCF5235_UART_UCSR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000204+((x)*0x040)))) -#define MCF5235_UART_UCR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000208+((x)*0x040)))) -#define MCF5235_UART_URB(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C+((x)*0x040)))) -#define MCF5235_UART_UTB(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00020C+((x)*0x040)))) -#define MCF5235_UART_UIPCR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210+((x)*0x040)))) -#define MCF5235_UART_UACR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000210+((x)*0x040)))) -#define MCF5235_UART_UISR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214+((x)*0x040)))) -#define MCF5235_UART_UIMR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000214+((x)*0x040)))) -#define MCF5235_UART_UBG1(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000218+((x)*0x040)))) -#define MCF5235_UART_UBG2(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00021C+((x)*0x040)))) -#define MCF5235_UART_UIP(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000234+((x)*0x040)))) -#define MCF5235_UART_UOP1(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000238+((x)*0x040)))) -#define MCF5235_UART_UOP0(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00023C+((x)*0x040)))) - -/* Bit definitions and macros for MCF5235_UART_UMR */ -#define MCF5235_UART_UMR_BC(x) (((x)&0x03)<<0) -#define MCF5235_UART_UMR_PT (0x04) -#define MCF5235_UART_UMR_PM(x) (((x)&0x03)<<3) -#define MCF5235_UART_UMR_ERR (0x20) -#define MCF5235_UART_UMR_RXIRQ (0x40) -#define MCF5235_UART_UMR_RXRTS (0x80) -#define MCF5235_UART_UMR_SB(x) (((x)&0x0F)<<0) -#define MCF5235_UART_UMR_TXCTS (0x10) -#define MCF5235_UART_UMR_TXRTS (0x20) -#define MCF5235_UART_UMR_CM(x) (((x)&0x03)<<6) -#define MCF5235_UART_UMR_PM_MULTI_ADDR (0x1C) -#define MCF5235_UART_UMR_PM_MULTI_DATA (0x18) -#define MCF5235_UART_UMR_PM_NONE (0x10) -#define MCF5235_UART_UMR_PM_FORCE_HI (0x0C) -#define MCF5235_UART_UMR_PM_FORCE_LO (0x08) -#define MCF5235_UART_UMR_PM_ODD (0x04) -#define MCF5235_UART_UMR_PM_EVEN (0x00) -#define MCF5235_UART_UMR_BC_5 (0x00) -#define MCF5235_UART_UMR_BC_6 (0x01) -#define MCF5235_UART_UMR_BC_7 (0x02) -#define MCF5235_UART_UMR_BC_8 (0x03) -#define MCF5235_UART_UMR_CM_NORMAL (0x00) -#define MCF5235_UART_UMR_CM_ECHO (0x40) -#define MCF5235_UART_UMR_CM_LOCAL_LOOP (0x80) -#define MCF5235_UART_UMR_CM_REMOTE_LOOP (0xC0) -#define MCF5235_UART_UMR_STOP_BITS_1 (0x07) -#define MCF5235_UART_UMR_STOP_BITS_15 (0x08) -#define MCF5235_UART_UMR_STOP_BITS_2 (0x0F) -#define MCF5235_UART_USR_RXRDY (0x01) -#define MCF5235_UART_USR_FFULL (0x02) -#define MCF5235_UART_USR_TXRDY (0x04) -#define MCF5235_UART_USR_TXEMP (0x08) -#define MCF5235_UART_USR_OE (0x10) -#define MCF5235_UART_USR_PE (0x20) -#define MCF5235_UART_USR_FE (0x40) -#define MCF5235_UART_USR_RB (0x80) -#define MCF5235_UART_UCSR_TCS(x) (((x)&0x0F)<<0) -#define MCF5235_UART_UCSR_RCS(x) (((x)&0x0F)<<4) -#define MCF5235_UART_UCSR_RCS_SYS_CLK (0xD0) -#define MCF5235_UART_UCSR_RCS_CTM16 (0xE0) -#define MCF5235_UART_UCSR_RCS_CTM (0xF0) -#define MCF5235_UART_UCSR_TCS_SYS_CLK (0x0D) -#define MCF5235_UART_UCSR_TCS_CTM16 (0x0E) -#define MCF5235_UART_UCSR_TCS_CTM (0x0F) -#define MCF5235_UART_UCR_RXC(x) (((x)&0x03)<<0) -#define MCF5235_UART_UCR_TXC(x) (((x)&0x03)<<2) -#define MCF5235_UART_UCR_MISC(x) (((x)&0x07)<<4) -#define MCF5235_UART_UCR_NONE (0x00) -#define MCF5235_UART_UCR_STOP_BREAK (0x70) -#define MCF5235_UART_UCR_START_BREAK (0x60) -#define MCF5235_UART_UCR_BKCHGINT (0x50) -#define MCF5235_UART_UCR_RESET_ERROR (0x40) -#define MCF5235_UART_UCR_RESET_TX (0x30) -#define MCF5235_UART_UCR_RESET_RX (0x20) -#define MCF5235_UART_UCR_RESET_MR (0x10) -#define MCF5235_UART_UCR_TX_DISABLED (0x08) -#define MCF5235_UART_UCR_TX_ENABLED (0x04) -#define MCF5235_UART_UCR_RX_DISABLED (0x02) -#define MCF5235_UART_UCR_RX_ENABLED (0x01) -#define MCF5235_UART_UIPCR_CTS (0x01) -#define MCF5235_UART_UIPCR_COS (0x10) -#define MCF5235_UART_UACR_IEC (0x01) -#define MCF5235_UART_UISR_TXRDY (0x01) -#define MCF5235_UART_UISR_RXRDY (0x02) -#define MCF5235_UART_UISR_DB (0x04) -#define MCF5235_UART_UISR_RXFTO (0x08) -#define MCF5235_UART_UISR_TXFIFO (0x10) -#define MCF5235_UART_UISR_RXFIFO (0x20) -#define MCF5235_UART_UISR_COS (0x80) -#define MCF5235_UART_UIMR_TXRDY (0x01) -#define MCF5235_UART_UIMR_FFULL (0x02) -#define MCF5235_UART_UIMR_DB (0x04) -#define MCF5235_UART_UIMR_COS (0x80) -#define MCF5235_UART_UIP_CTS (0x01) -#define MCF5235_UART_UOP1_RTS (0x01) -#define MCF5235_UART_UOP0_RTS (0x01) - - -/********************************************************************* -* -* SDRAM Controller (SDRAMC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_SDRAMC_DCR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000040))) -#define MCF5235_SDRAMC_DACR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000048))) -#define MCF5235_SDRAMC_DMR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00004C))) -#define MCF5235_SDRAMC_DACR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000050))) -#define MCF5235_SDRAMC_DMR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000054))) - -/* Bit definitions and macros for MCF5235_SDRAMC_DCR */ -#define MCF5235_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0) -#define MCF5235_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9) -#define MCF5235_SDRAMC_DCR_IS (0x0800) -#define MCF5235_SDRAMC_DCR_COC (0x1000) -#define MCF5235_SDRAMC_DCR_NAM (0x2000) -#define MCF5235_SDRAMC_DACR0_IP (0x00000008) -#define MCF5235_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4) -#define MCF5235_SDRAMC_DACR0_MRS (0x00000040) -#define MCF5235_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8) -#define MCF5235_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12) -#define MCF5235_SDRAMC_DACR0_RE (0x00008000) -#define MCF5235_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18) -#define MCF5235_SDRAMC_DMR0_V (0x00000001) -#define MCF5235_SDRAMC_DMR0_WP (0x00000100) -#define MCF5235_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18) -#define MCF5235_SDRAMC_DACR1_IP (0x00000008) -#define MCF5235_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4) -#define MCF5235_SDRAMC_DACR1_MRS (0x00000040) -#define MCF5235_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8) -#define MCF5235_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12) -#define MCF5235_SDRAMC_DACR1_RE (0x00008000) -#define MCF5235_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18) -#define MCF5235_SDRAMC_DMR1_V (0x00000001) -#define MCF5235_SDRAMC_DMR1_WP (0x00000100) -#define MCF5235_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18) -#define MCF5235_SDRAMC_DMR_BAM_4G (0xFFFC0000) -#define MCF5235_SDRAMC_DMR_BAM_2G (0x7FFC0000) -#define MCF5235_SDRAMC_DMR_BAM_1G (0x3FFC0000) -#define MCF5235_SDRAMC_DMR_BAM_1024M (0x3FFC0000) -#define MCF5235_SDRAMC_DMR_BAM_512M (0x1FFC0000) -#define MCF5235_SDRAMC_DMR_BAM_256M (0x0FFC0000) -#define MCF5235_SDRAMC_DMR_BAM_128M (0x07FC0000) -#define MCF5235_SDRAMC_DMR_BAM_64M (0x03FC0000) -#define MCF5235_SDRAMC_DMR_BAM_32M (0x01FC0000) -#define MCF5235_SDRAMC_DMR_BAM_16M (0x00FC0000) -#define MCF5235_SDRAMC_DMR_BAM_8M (0x007C0000) -#define MCF5235_SDRAMC_DMR_BAM_4M (0x003C0000) -#define MCF5235_SDRAMC_DMR_BAM_2M (0x001C0000) -#define MCF5235_SDRAMC_DMR_BAM_1M (0x000C0000) -#define MCF5235_SDRAMC_DMR_BAM_1024K (0x000C0000) -#define MCF5235_SDRAMC_DMR_BAM_512K (0x00040000) -#define MCF5235_SDRAMC_DMR_BAM_256K (0x00000000) -#define MCF5235_SDRAMC_DMR_WP (0x00000100) -#define MCF5235_SDRAMC_DMR_CI (0x00000040) -#define MCF5235_SDRAMC_DMR_AM (0x00000020) -#define MCF5235_SDRAMC_DMR_SC (0x00000010) -#define MCF5235_SDRAMC_DMR_SD (0x00000008) -#define MCF5235_SDRAMC_DMR_UC (0x00000004) -#define MCF5235_SDRAMC_DMR_UD (0x00000002) -#define MCF5235_SDRAMC_DMR_V (0x00000001) - -/********************************************************************* -* -* DMA Timers (TIMER) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_TIMER_DTMR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000400))) -#define MCF5235_TIMER_DTXMR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000402))) -#define MCF5235_TIMER_DTER0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000403))) -#define MCF5235_TIMER_DTRR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000404))) -#define MCF5235_TIMER_DTCR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000408))) -#define MCF5235_TIMER_DTCN0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00040C))) -#define MCF5235_TIMER_DTMR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000440))) -#define MCF5235_TIMER_DTXMR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000442))) -#define MCF5235_TIMER_DTER1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000443))) -#define MCF5235_TIMER_DTRR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000444))) -#define MCF5235_TIMER_DTCR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000448))) -#define MCF5235_TIMER_DTCN1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00044C))) -#define MCF5235_TIMER_DTMR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000480))) -#define MCF5235_TIMER_DTXMR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000482))) -#define MCF5235_TIMER_DTER2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000483))) -#define MCF5235_TIMER_DTRR2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000484))) -#define MCF5235_TIMER_DTCR2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000488))) -#define MCF5235_TIMER_DTCN2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00048C))) -#define MCF5235_TIMER3_DTMR (*(vuint16*)((uintptr_t)__IPSBAR + (0x0004C0))) -#define MCF5235_TIMER_DTXMR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0004C2))) -#define MCF5235_TIMER_DTER3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x0004C3))) -#define MCF5235_TIMER_DTRR3 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0004C4))) -#define MCF5235_TIMER_DTCR3 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0004C8))) -#define MCF5235_TIMER3_DTCN (*(vuint32*)((uintptr_t)__IPSBAR + (0x0004CC))) -#define MCF5235_TIMER_DTMR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x000400+((x)*0x040)))) -#define MCF5235_TIMER_DTXMR(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000402+((x)*0x040)))) -#define MCF5235_TIMER_DTER(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000403+((x)*0x040)))) -#define MCF5235_TIMER_DTRR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x000404+((x)*0x040)))) -#define MCF5235_TIMER_DTCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x000408+((x)*0x040)))) -#define MCF5235_TIMER_DTCN(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x00040C+((x)*0x040)))) - -/* Bit definitions and macros for MCF5235_TIMER_DTMR */ -#define MCF5235_TIMER_DTMR_RST (0x0001) -#define MCF5235_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1) -#define MCF5235_TIMER_DTMR_FRR (0x0008) -#define MCF5235_TIMER_DTMR_ORRI (0x0010) -#define MCF5235_TIMER_DTMR_OM (0x0020) -#define MCF5235_TIMER_DTMR_CE(x) (((x)&0x0003)<<6) -#define MCF5235_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8) -#define MCF5235_TIMER_DTMR_CE_ANY (0x00C0) -#define MCF5235_TIMER_DTMR_CE_FALL (0x0080) -#define MCF5235_TIMER_DTMR_CE_RISE (0x0040) -#define MCF5235_TIMER_DTMR_CE_NONE (0x0000) -#define MCF5235_TIMER_DTMR_CLK_DTIN (0x0006) -#define MCF5235_TIMER_DTMR_CLK_DIV16 (0x0004) -#define MCF5235_TIMER_DTMR_CLK_DIV1 (0x0002) -#define MCF5235_TIMER_DTMR_CLK_STOP (0x0000) -#define MCF5235_TIMER_DTXMR_MODE16 (0x01) -#define MCF5235_TIMER_DTXMR_DMAEN (0x80) -#define MCF5235_TIMER_DTER_CAP (0x01) -#define MCF5235_TIMER_DTER_REF (0x02) - -/********************************************************************* -* -* System SRAM (SRAM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_SRAM_RAMBAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x20000000))) - -/* Bit definitions and macros for MCF5235_SRAM_RAMBAR */ -#define MCF5235_SRAM_RAMBAR_V (0x00000001) -#define MCF5235_SRAM_RAMBAR_UD (0x00000002) -#define MCF5235_SRAM_RAMBAR_UC (0x00000004) -#define MCF5235_SRAM_RAMBAR_SD (0x00000008) -#define MCF5235_SRAM_RAMBAR_SC (0x00000010) -#define MCF5235_SRAM_RAMBAR_CI (0x00000020) -#define MCF5235_SRAM_RAMBAR_WP (0x00000100) -#define MCF5235_SRAM_RAMBAR_SPV (0x00000200) -#define MCF5235_SRAM_RAMBAR_PRI2 (0x00000400) -#define MCF5235_SRAM_RAMBAR_PRI1 (0x00000800) -#define MCF5235_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) - -/********************************************************************* -* -* System Control Module (SCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_SCM_IPSBAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x000000))) -#define MCF5235_SCM_RAMBAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x000008))) -#define MCF5235_SCM_CRSR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000010))) -#define MCF5235_SCM_CWCR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000011))) -#define MCF5235_SCM_LPICR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000012))) -#define MCF5235_SCM_CWSR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000013))) -#define MCF5235_SCM_DMAREQC (*(vuint32*)((uintptr_t)__IPSBAR + (0x000014))) -#define MCF5235_SCM_MPARK (*(vuint32*)((uintptr_t)__IPSBAR + (0x00001C))) -#define MCF5235_SCM_MPR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000020))) -#define MCF5235_SCM_PACR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000024))) -#define MCF5235_SCM_PACR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000025))) -#define MCF5235_SCM_PACR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000026))) -#define MCF5235_SCM_PACR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000027))) -#define MCF5235_SCM_PACR4 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000028))) -#define MCF5235_SCM_PACR5 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002A))) -#define MCF5235_SCM_PACR6 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002B))) -#define MCF5235_SCM_PACR7 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002C))) -#define MCF5235_SCM_PACR8 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00002E))) -#define MCF5235_SCM_GPACR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000030))) - -/* Bit definitions */ -#define MCF5235_SCM_IPSBAR_V (0x00000001) -#define MCF5235_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30) -#define MCF5235_SCM_RAMBAR_BDE (0x00000200) -#define MCF5235_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) -#define MCF5235_SCM_CRSR_CWDR (0x20) -#define MCF5235_SCM_CRSR_EXT (0x80) -#define MCF5235_SCM_CWCR_CWTIC (0x01) -#define MCF5235_SCM_CWCR_CWTAVAL (0x02) -#define MCF5235_SCM_CWCR_CWTA (0x04) -#define MCF5235_SCM_CWCR_CWT(x) (((x)&0x07)<<3) -#define MCF5235_SCM_CWCR_CWRI (0x40) -#define MCF5235_SCM_CWCR_CWE (0x80) -#define MCF5235_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) -#define MCF5235_SCM_LPICR_ENBSTOP (0x80) -#define MCF5235_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) -#define MCF5235_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) -#define MCF5235_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) -#define MCF5235_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) -#define MCF5235_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) -#define MCF5235_SCM_MPARK_PRKLAST (0x00001000) -#define MCF5235_SCM_MPARK_TIMEOUT (0x00002000) -#define MCF5235_SCM_MPARK_FIXED (0x00004000) -#define MCF5235_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16) -#define MCF5235_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18) -#define MCF5235_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20) -#define MCF5235_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22) -#define MCF5235_SCM_MPARK_BCR24BIT (0x01000000) -#define MCF5235_SCM_MPARK_M2_P_EN (0x02000000) -#define MCF5235_SCM_MPR_MPR(x) (((x)&0x0F)<<0) -#define MCF5235_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF5235_SCM_PACR0_LOCK0 (0x08) -#define MCF5235_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF5235_SCM_PACR0_LOCK1 (0x80) -#define MCF5235_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF5235_SCM_PACR1_LOCK0 (0x08) -#define MCF5235_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF5235_SCM_PACR1_LOCK1 (0x80) -#define MCF5235_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF5235_SCM_PACR2_LOCK0 (0x08) -#define MCF5235_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF5235_SCM_PACR2_LOCK1 (0x80) -#define MCF5235_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF5235_SCM_PACR3_LOCK0 (0x08) -#define MCF5235_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF5235_SCM_PACR3_LOCK1 (0x80) -#define MCF5235_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF5235_SCM_PACR4_LOCK0 (0x08) -#define MCF5235_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF5235_SCM_PACR4_LOCK1 (0x80) -#define MCF5235_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF5235_SCM_PACR5_LOCK0 (0x08) -#define MCF5235_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF5235_SCM_PACR5_LOCK1 (0x80) -#define MCF5235_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF5235_SCM_PACR6_LOCK0 (0x08) -#define MCF5235_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF5235_SCM_PACR6_LOCK1 (0x80) -#define MCF5235_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF5235_SCM_PACR7_LOCK0 (0x08) -#define MCF5235_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF5235_SCM_PACR7_LOCK1 (0x80) -#define MCF5235_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF5235_SCM_PACR8_LOCK0 (0x08) -#define MCF5235_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF5235_SCM_PACR8_LOCK1 (0x80) -#define MCF5235_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0) -#define MCF5235_SCM_GPACR0_LOCK (0x80) - - -/********************************************************************* -* -* FlexCAN Module (CAN) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_CAN_CANMCR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0000))) -#define MCF5235_CAN_CANCTRL0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0004))) -#define MCF5235_CAN_TIMER0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0008))) -#define MCF5235_CAN_RXGMASK0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0010))) -#define MCF5235_CAN_RX14MASK0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0014))) -#define MCF5235_CAN_RX15MASK0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0018))) -#define MCF5235_CAN_ERRCNT0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C001C))) -#define MCF5235_CAN_ERRSTAT0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0020))) -#define MCF5235_CAN_IMASK0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C002A))) -#define MCF5235_CAN_IFLAG0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C0032))) -#define MCF5235_CAN_CANMCR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0000))) -#define MCF5235_CAN_CANCTRL1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0004))) -#define MCF5235_CAN_TIMER1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0008))) -#define MCF5235_CAN_RXGMASK1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0010))) -#define MCF5235_CAN_RX14MASK1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0014))) -#define MCF5235_CAN_RX15MASK1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0018))) -#define MCF5235_CAN_ERRCNT1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F001C))) -#define MCF5235_CAN_ERRSTAT1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x1F0020))) -#define MCF5235_CAN_IMASK1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1F002A))) -#define MCF5235_CAN_IFLAG1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x1F0032))) -#define MCF5235_CAN_CANMCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0000+((x)*0x30000)))) -#define MCF5235_CAN_CANCTRL(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0004+((x)*0x30000)))) -#define MCF5235_CAN_TIMER(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0008+((x)*0x30000)))) -#define MCF5235_CAN_RXGMASK(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0010+((x)*0x30000)))) -#define MCF5235_CAN_RX14MASK(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0014+((x)*0x30000)))) -#define MCF5235_CAN_RX15MASK(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0018+((x)*0x30000)))) -#define MCF5235_CAN_ERRCNT(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C001C+((x)*0x30000)))) -#define MCF5235_CAN_ERRSTAT(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1C0020+((x)*0x30000)))) -#define MCF5235_CAN_IMASK(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C002A+((x)*0x30000)))) -#define MCF5235_CAN_IFLAG(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x1C0032+((x)*0x30000)))) - -#define MCF5235_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0080+((x)*0x30000)))) -#define MCF5235_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0082+((x)*0x30000)))) -#define MCF5235_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0084+((x)*0x30000)))) -#define MCF5235_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0088+((x)*0x30000)))) -#define MCF5235_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0089+((x)*0x30000)))) -#define MCF5235_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008A+((x)*0x30000)))) -#define MCF5235_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008B+((x)*0x30000)))) -#define MCF5235_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008C+((x)*0x30000)))) -#define MCF5235_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008D+((x)*0x30000)))) -#define MCF5235_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008E+((x)*0x30000)))) -#define MCF5235_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C008F+((x)*0x30000)))) -#define MCF5235_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0090+((x)*0x30000)))) -#define MCF5235_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0092+((x)*0x30000)))) -#define MCF5235_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0094+((x)*0x30000)))) -#define MCF5235_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0098+((x)*0x30000)))) -#define MCF5235_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0099+((x)*0x30000)))) -#define MCF5235_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009A+((x)*0x30000)))) -#define MCF5235_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009B+((x)*0x30000)))) -#define MCF5235_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009C+((x)*0x30000)))) -#define MCF5235_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009D+((x)*0x30000)))) -#define MCF5235_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009E+((x)*0x30000)))) -#define MCF5235_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C009F+((x)*0x30000)))) -#define MCF5235_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A0+((x)*0x30000)))) -#define MCF5235_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A4+((x)*0x30000)))) -#define MCF5235_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A8+((x)*0x30000)))) -#define MCF5235_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A9+((x)*0x30000)))) -#define MCF5235_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AA+((x)*0x30000)))) -#define MCF5235_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AB+((x)*0x30000)))) -#define MCF5235_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AC+((x)*0x30000)))) -#define MCF5235_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AD+((x)*0x30000)))) -#define MCF5235_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AE+((x)*0x30000)))) -#define MCF5235_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AF+((x)*0x30000)))) -#define MCF5235_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B0+((x)*0x30000)))) -#define MCF5235_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B4+((x)*0x30000)))) -#define MCF5235_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B8+((x)*0x30000)))) -#define MCF5235_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00B9+((x)*0x30000)))) -#define MCF5235_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BA+((x)*0x30000)))) -#define MCF5235_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BB+((x)*0x30000)))) -#define MCF5235_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BC+((x)*0x30000)))) -#define MCF5235_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BD+((x)*0x30000)))) -#define MCF5235_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BE+((x)*0x30000)))) -#define MCF5235_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00BF+((x)*0x30000)))) -#define MCF5235_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C0+((x)*0x30000)))) -#define MCF5235_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C4+((x)*0x30000)))) -#define MCF5235_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C8+((x)*0x30000)))) -#define MCF5235_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00C9+((x)*0x30000)))) -#define MCF5235_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CA+((x)*0x30000)))) -#define MCF5235_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CB+((x)*0x30000)))) -#define MCF5235_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CC+((x)*0x30000)))) -#define MCF5235_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CD+((x)*0x30000)))) -#define MCF5235_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CE+((x)*0x30000)))) -#define MCF5235_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00CF+((x)*0x30000)))) -#define MCF5235_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D0+((x)*0x30000)))) -#define MCF5235_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D4+((x)*0x30000)))) -#define MCF5235_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D8+((x)*0x30000)))) -#define MCF5235_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00D9+((x)*0x30000)))) -#define MCF5235_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DA+((x)*0x30000)))) -#define MCF5235_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DB+((x)*0x30000)))) -#define MCF5235_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DC+((x)*0x30000)))) -#define MCF5235_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DD+((x)*0x30000)))) -#define MCF5235_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DE+((x)*0x30000)))) -#define MCF5235_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00DF+((x)*0x30000)))) -#define MCF5235_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E0+((x)*0x30000)))) -#define MCF5235_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E4+((x)*0x30000)))) -#define MCF5235_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E8+((x)*0x30000)))) -#define MCF5235_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00E9+((x)*0x30000)))) -#define MCF5235_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EA+((x)*0x30000)))) -#define MCF5235_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EB+((x)*0x30000)))) -#define MCF5235_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EC+((x)*0x30000)))) -#define MCF5235_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00ED+((x)*0x30000)))) -#define MCF5235_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EE+((x)*0x30000)))) -#define MCF5235_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00EF+((x)*0x30000)))) -#define MCF5235_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F0+((x)*0x30000)))) -#define MCF5235_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F4+((x)*0x30000)))) -#define MCF5235_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F8+((x)*0x30000)))) -#define MCF5235_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00F9+((x)*0x30000)))) -#define MCF5235_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FA+((x)*0x30000)))) -#define MCF5235_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FB+((x)*0x30000)))) -#define MCF5235_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FC+((x)*0x30000)))) -#define MCF5235_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FD+((x)*0x30000)))) -#define MCF5235_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FE+((x)*0x30000)))) -#define MCF5235_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C00FF+((x)*0x30000)))) -#define MCF5235_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0100+((x)*0x30000)))) -#define MCF5235_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0104+((x)*0x30000)))) -#define MCF5235_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0108+((x)*0x30000)))) -#define MCF5235_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0109+((x)*0x30000)))) -#define MCF5235_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010A+((x)*0x30000)))) -#define MCF5235_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010B+((x)*0x30000)))) -#define MCF5235_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010C+((x)*0x30000)))) -#define MCF5235_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010D+((x)*0x30000)))) -#define MCF5235_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010E+((x)*0x30000)))) -#define MCF5235_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C010F+((x)*0x30000)))) -#define MCF5235_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0100+((x)*0x30000)))) -#define MCF5235_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0114+((x)*0x30000)))) -#define MCF5235_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0118+((x)*0x30000)))) -#define MCF5235_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0119+((x)*0x30000)))) -#define MCF5235_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011A+((x)*0x30000)))) -#define MCF5235_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011B+((x)*0x30000)))) -#define MCF5235_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011C+((x)*0x30000)))) -#define MCF5235_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011D+((x)*0x30000)))) -#define MCF5235_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011E+((x)*0x30000)))) -#define MCF5235_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C011F+((x)*0x30000)))) -#define MCF5235_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0120+((x)*0x30000)))) -#define MCF5235_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0124+((x)*0x30000)))) -#define MCF5235_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0128+((x)*0x30000)))) -#define MCF5235_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0129+((x)*0x30000)))) -#define MCF5235_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012A+((x)*0x30000)))) -#define MCF5235_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012B+((x)*0x30000)))) -#define MCF5235_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012C+((x)*0x30000)))) -#define MCF5235_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012D+((x)*0x30000)))) -#define MCF5235_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012E+((x)*0x30000)))) -#define MCF5235_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C012F+((x)*0x30000)))) -#define MCF5235_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0130+((x)*0x30000)))) -#define MCF5235_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0134+((x)*0x30000)))) -#define MCF5235_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0138+((x)*0x30000)))) -#define MCF5235_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0139+((x)*0x30000)))) -#define MCF5235_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013A+((x)*0x30000)))) -#define MCF5235_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013B+((x)*0x30000)))) -#define MCF5235_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013C+((x)*0x30000)))) -#define MCF5235_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013D+((x)*0x30000)))) -#define MCF5235_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013E+((x)*0x30000)))) -#define MCF5235_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C013F+((x)*0x30000)))) -#define MCF5235_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0140+((x)*0x30000)))) -#define MCF5235_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0144+((x)*0x30000)))) -#define MCF5235_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0148+((x)*0x30000)))) -#define MCF5235_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0149+((x)*0x30000)))) -#define MCF5235_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014A+((x)*0x30000)))) -#define MCF5235_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014B+((x)*0x30000)))) -#define MCF5235_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014C+((x)*0x30000)))) -#define MCF5235_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014D+((x)*0x30000)))) -#define MCF5235_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014E+((x)*0x30000)))) -#define MCF5235_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C014F+((x)*0x30000)))) -#define MCF5235_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0150+((x)*0x30000)))) -#define MCF5235_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0154+((x)*0x30000)))) -#define MCF5235_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0158+((x)*0x30000)))) -#define MCF5235_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0159+((x)*0x30000)))) -#define MCF5235_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015A+((x)*0x30000)))) -#define MCF5235_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015B+((x)*0x30000)))) -#define MCF5235_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015C+((x)*0x30000)))) -#define MCF5235_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015D+((x)*0x30000)))) -#define MCF5235_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015E+((x)*0x30000)))) -#define MCF5235_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C015F+((x)*0x30000)))) -#define MCF5235_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0160+((x)*0x30000)))) -#define MCF5235_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0164+((x)*0x30000)))) -#define MCF5235_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0168+((x)*0x30000)))) -#define MCF5235_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0169+((x)*0x30000)))) -#define MCF5235_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016A+((x)*0x30000)))) -#define MCF5235_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016B+((x)*0x30000)))) -#define MCF5235_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016C+((x)*0x30000)))) -#define MCF5235_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016D+((x)*0x30000)))) -#define MCF5235_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016E+((x)*0x30000)))) -#define MCF5235_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C016F+((x)*0x30000)))) -#define MCF5235_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)((uintptr_t)__IPSBAR + (0x1C0170+((x)*0x30000)))) -#define MCF5235_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0174+((x)*0x30000)))) -#define MCF5235_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0178+((x)*0x30000)))) -#define MCF5235_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C0179+((x)*0x30000)))) -#define MCF5235_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017A+((x)*0x30000)))) -#define MCF5235_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017B+((x)*0x30000)))) -#define MCF5235_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017C+((x)*0x30000)))) -#define MCF5235_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017D+((x)*0x30000)))) -#define MCF5235_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017E+((x)*0x30000)))) -#define MCF5235_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)((uintptr_t)__IPSBAR + (0x1C017F+((x)*0x30000)))) -#define MCF5235_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0088+((x)*0x30000)))) -#define MCF5235_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C008C+((x)*0x30000)))) -#define MCF5235_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C0098+((x)*0x30000)))) -#define MCF5235_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C009C+((x)*0x30000)))) -#define MCF5235_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00A8+((x)*0x30000)))) -#define MCF5235_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)((uintptr_t)__IPSBAR + (0x1C00AC+((x)*0x30000)))) - - -/* Bit definitions and macros for MCF5235_CAN_CANMCR */ -#define MCF5235_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) -#define MCF5235_CAN_CANMCR_SUPV (0x00800000) -#define MCF5235_CAN_CANMCR_FRZACK (0x01000000) -#define MCF5235_CAN_CANMCR_SOFTRST (0x02000000) -#define MCF5235_CAN_CANMCR_HALT (0x10000000) -#define MCF5235_CAN_CANMCR_FRZ (0x40000000) -#define MCF5235_CAN_CANMCR_MDIS (0x80000000) -#define MCF5235_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) -#define MCF5235_CAN_CANCTRL_LOM (0x00000008) -#define MCF5235_CAN_CANCTRL_LBUF (0x00000010) -#define MCF5235_CAN_CANCTRL_TSYNC (0x00000020) -#define MCF5235_CAN_CANCTRL_BOFFREC (0x00000040) -#define MCF5235_CAN_CANCTRL_SAMP (0x00000080) -#define MCF5235_CAN_CANCTRL_LPB (0x00001000) -#define MCF5235_CAN_CANCTRL_CLKSRC (0x00002000) -#define MCF5235_CAN_CANCTRL_ERRMSK (0x00004000) -#define MCF5235_CAN_CANCTRL_BOFFMSK (0x00008000) -#define MCF5235_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) -#define MCF5235_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) -#define MCF5235_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) -#define MCF5235_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) -#define MCF5235_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) -#define MCF5235_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) -#define MCF5235_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) -#define MCF5235_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) -#define MCF5235_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) -#define MCF5235_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) -#define MCF5235_CAN_ERRSTAT_WAKINT (0x00000001) -#define MCF5235_CAN_ERRSTAT_ERRINT (0x00000002) -#define MCF5235_CAN_ERRSTAT_BOFFINT (0x00000004) -#define MCF5235_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) -#define MCF5235_CAN_ERRSTAT_TXRX (0x00000040) -#define MCF5235_CAN_ERRSTAT_IDLE (0x00000080) -#define MCF5235_CAN_ERRSTAT_RXWRN (0x00000100) -#define MCF5235_CAN_ERRSTAT_TXWRN (0x00000200) -#define MCF5235_CAN_ERRSTAT_STFERR (0x00000400) -#define MCF5235_CAN_ERRSTAT_FRMERR (0x00000800) -#define MCF5235_CAN_ERRSTAT_CRCERR (0x00001000) -#define MCF5235_CAN_ERRSTAT_ACKERR (0x00002000) -#define MCF5235_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) -#define MCF5235_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) -#define MCF5235_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) -#define MCF5235_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) -#define MCF5235_CAN_IMASK_BUF0M (0x0001) -#define MCF5235_CAN_IMASK_BUF1M (0x0002) -#define MCF5235_CAN_IMASK_BUF2M (0x0004) -#define MCF5235_CAN_IMASK_BUF3M (0x0008) -#define MCF5235_CAN_IMASK_BUF4M (0x0010) -#define MCF5235_CAN_IMASK_BUF5M (0x0020) -#define MCF5235_CAN_IMASK_BUF6M (0x0040) -#define MCF5235_CAN_IMASK_BUF7M (0x0080) -#define MCF5235_CAN_IMASK_BUF8M (0x0100) -#define MCF5235_CAN_IMASK_BUF9M (0x0200) -#define MCF5235_CAN_IMASK_BUF10M (0x0400) -#define MCF5235_CAN_IMASK_BUF11M (0x0800) -#define MCF5235_CAN_IMASK_BUF12M (0x1000) -#define MCF5235_CAN_IMASK_BUF13M (0x2000) -#define MCF5235_CAN_IMASK_BUF14M (0x4000) -#define MCF5235_CAN_IMASK_BUF15M (0x8000) - -/* Bit definitions and macros for MCF5235_CAN_IFLAG */ -#define MCF5235_CAN_IFLAG_BUF0I (0x0001) -#define MCF5235_CAN_IFLAG_BUF1I (0x0002) -#define MCF5235_CAN_IFLAG_BUF2I (0x0004) -#define MCF5235_CAN_IFLAG_BUF3I (0x0008) -#define MCF5235_CAN_IFLAG_BUF4I (0x0010) -#define MCF5235_CAN_IFLAG_BUF5I (0x0020) -#define MCF5235_CAN_IFLAG_BUF6I (0x0040) -#define MCF5235_CAN_IFLAG_BUF7I (0x0080) -#define MCF5235_CAN_IFLAG_BUF8I (0x0100) -#define MCF5235_CAN_IFLAG_BUF9I (0x0200) -#define MCF5235_CAN_IFLAG_BUF10I (0x0400) -#define MCF5235_CAN_IFLAG_BUF11I (0x0800) -#define MCF5235_CAN_IFLAG_BUF12I (0x1000) -#define MCF5235_CAN_IFLAG_BUF13I (0x2000) -#define MCF5235_CAN_IFLAG_BUF14I (0x4000) -#define MCF5235_CAN_IFLAG_BUF15I (0x8000) - - -/********************************************************************* -* -* Chip Configuration Module (CCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_CCM_CCR (*(vuint16*)((uintptr_t)__IPSBAR + (0x110004))) -#define MCF5235_CCM_LPCR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x110007))) -#define MCF5235_CCM_CIR (*(vuint16*)((uintptr_t)__IPSBAR + (0x11000A))) -#define MCF5235_CCM_RCON (*(vuint16*)((uintptr_t)__IPSBAR + (0x110008))) - -/* Bit definitions and macros for MCF5235_CCM_CCR */ -#define MCF5235_CCM_CCR_BMT(x) (((x)&0x0007)<<0) -#define MCF5235_CCM_CCR_BME (0x0008) -#define MCF5235_CCM_CCR_SZEN (0x0040) -#define MCF5235_CCM_CCR_MODE(x) (((x)&0x0007)<<8) -#define MCF5235_CCM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF5235_CCM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF5235_CCM_LPCR_LPMD_STOP (0xC0) -#define MCF5235_CCM_LPCR_LPMD_WAIT (0x80) -#define MCF5235_CCM_LPCR_LPMD_DOZE (0x40) -#define MCF5235_CCM_LPCR_LPMD_RUN (0x00) -#define MCF5235_CCM_CIR_PRN(x) (((x)&0x003F)<<0) -#define MCF5235_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) -#define MCF5235_CCM_RCON_MODE (0x0001) -#define MCF5235_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) -#define MCF5235_CCM_RCON_RLOAD (0x0020) -#define MCF5235_CCM_RCON_RCSC(x) (((x)&0x0003)<<8) - -/********************************************************************* -* -* Chip Selects (CS) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_CS_CSAR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000080))) -#define MCF5235_CS_CSMR0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000084))) -#define MCF5235_CS_CSCR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x00008A))) -#define MCF5235_CS_CSAR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x00008C))) -#define MCF5235_CS_CSMR1 (*(vuint32*)((uintptr_t)__IPSBAR + (0x000090))) -#define MCF5235_CS_CSCR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000096))) -#define MCF5235_CS_CSAR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x000098))) -#define MCF5235_CS_CSMR2 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00009C))) -#define MCF5235_CS_CSCR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000A2))) -#define MCF5235_CS_CSAR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000A4))) -#define MCF5235_CS_CSMR3 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000A8))) -#define MCF5235_CS_CSCR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000AE))) -#define MCF5235_CS_CSAR4 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000B0))) -#define MCF5235_CS_CSMR4 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000B4))) -#define MCF5235_CS_CSCR4 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000BA))) -#define MCF5235_CS_CSAR5 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000BC))) -#define MCF5235_CS_CSMR5 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000C0))) -#define MCF5235_CS_CSCR5 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000C6))) -#define MCF5235_CS_CSAR6 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000C8))) -#define MCF5235_CS_CSMR6 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000CC))) -#define MCF5235_CS_CSCR6 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000D2))) -#define MCF5235_CS_CSAR7 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000D4))) -#define MCF5235_CS_CSMR7 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0000D8))) -#define MCF5235_CS_CSCR7 (*(vuint16*)((uintptr_t)__IPSBAR + (0x0000DE))) -#define MCF5235_CS_CSAR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x000080+((x)*0x00C)))) -#define MCF5235_CS_CSMR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x000084+((x)*0x00C)))) -#define MCF5235_CS_CSCR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x00008A+((x)*0x00C)))) - -/* Bit definitions and macros for MCF5235_CS_CSAR */ -#define MCF5235_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16)) -#define MCF5235_CS_CSMR_V (0x00000001) -#define MCF5235_CS_CSMR_UD (0x00000002) -#define MCF5235_CS_CSMR_UC (0x00000004) -#define MCF5235_CS_CSMR_SD (0x00000008) -#define MCF5235_CS_CSMR_SC (0x00000010) -#define MCF5235_CS_CSMR_CI (0x00000020) -#define MCF5235_CS_CSMR_AM (0x00000040) -#define MCF5235_CS_CSMR_WP (0x00000100) -#define MCF5235_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) -#define MCF5235_CS_CSMR_BAM_4G (0xFFFF0000) -#define MCF5235_CS_CSMR_BAM_2G (0x7FFF0000) -#define MCF5235_CS_CSMR_BAM_1G (0x3FFF0000) -#define MCF5235_CS_CSMR_BAM_1024M (0x3FFF0000) -#define MCF5235_CS_CSMR_BAM_512M (0x1FFF0000) -#define MCF5235_CS_CSMR_BAM_256M (0x0FFF0000) -#define MCF5235_CS_CSMR_BAM_128M (0x07FF0000) -#define MCF5235_CS_CSMR_BAM_64M (0x03FF0000) -#define MCF5235_CS_CSMR_BAM_32M (0x01FF0000) -#define MCF5235_CS_CSMR_BAM_16M (0x00FF0000) -#define MCF5235_CS_CSMR_BAM_8M (0x007F0000) -#define MCF5235_CS_CSMR_BAM_4M (0x003F0000) -#define MCF5235_CS_CSMR_BAM_2M (0x001F0000) -#define MCF5235_CS_CSMR_BAM_1M (0x000F0000) -#define MCF5235_CS_CSMR_BAM_1024K (0x000F0000) -#define MCF5235_CS_CSMR_BAM_512K (0x00070000) -#define MCF5235_CS_CSMR_BAM_256K (0x00030000) -#define MCF5235_CS_CSMR_BAM_128K (0x00010000) -#define MCF5235_CS_CSMR_BAM_64K (0x00000000) -#define MCF5235_CS_CSCR_SWWS(x) (((x)&0x0007)<<0) -#define MCF5235_CS_CSCR_BSTW (0x0008) -#define MCF5235_CS_CSCR_BSTR (0x0010) -#define MCF5235_CS_CSCR_BEM (0x0020) -#define MCF5235_CS_CSCR_PS(x) (((x)&0x0003)<<6) -#define MCF5235_CS_CSCR_AA (0x0100) -#define MCF5235_CS_CSCR_IWS(x) (((x)&0x000F)<<10) -#define MCF5235_CS_CSCR_SRWS(x) (((x)&0x0003)<<14) -#define MCF5235_CS_CSCR_PS_8 (0x0040) -#define MCF5235_CS_CSCR_PS_16 (0x0080) -#define MCF5235_CS_CSCR_PS_32 (0x0000) - -/********************************************************************* -* -* Edge Port Module (EPORT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_EPORT_EPPAR (*(vuint16*)((uintptr_t)__IPSBAR + (0x130000))) -#define MCF5235_EPORT_EPDDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130002))) -#define MCF5235_EPORT_EPIER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130003))) -#define MCF5235_EPORT_EPDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130004))) -#define MCF5235_EPORT_EPPDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130005))) -#define MCF5235_EPORT_EPFR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x130006))) - -/* Bit definitions and macros for MCF5235_EPORT_EPPAR */ -#define MCF5235_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define MCF5235_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define MCF5235_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define MCF5235_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define MCF5235_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define MCF5235_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define MCF5235_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define MCF5235_EPORT_EPPAR_EPPAx_LEVEL (0) -#define MCF5235_EPORT_EPPAR_EPPAx_RISING (1) -#define MCF5235_EPORT_EPPAR_EPPAx_FALLING (2) -#define MCF5235_EPORT_EPPAR_EPPAx_BOTH (3) -#define MCF5235_EPORT_EPDDR_EPDD1 (0x02) -#define MCF5235_EPORT_EPDDR_EPDD2 (0x04) -#define MCF5235_EPORT_EPDDR_EPDD3 (0x08) -#define MCF5235_EPORT_EPDDR_EPDD4 (0x10) -#define MCF5235_EPORT_EPDDR_EPDD5 (0x20) -#define MCF5235_EPORT_EPDDR_EPDD6 (0x40) -#define MCF5235_EPORT_EPDDR_EPDD7 (0x80) -#define MCF5235_EPORT_EPIER_EPIE1 (0x02) -#define MCF5235_EPORT_EPIER_EPIE2 (0x04) -#define MCF5235_EPORT_EPIER_EPIE3 (0x08) -#define MCF5235_EPORT_EPIER_EPIE4 (0x10) -#define MCF5235_EPORT_EPIER_EPIE5 (0x20) -#define MCF5235_EPORT_EPIER_EPIE6 (0x40) -#define MCF5235_EPORT_EPIER_EPIE7 (0x80) -#define MCF5235_EPORT_EPDR_EPD1 (0x02) -#define MCF5235_EPORT_EPDR_EPD2 (0x04) -#define MCF5235_EPORT_EPDR_EPD3 (0x08) -#define MCF5235_EPORT_EPDR_EPD4 (0x10) -#define MCF5235_EPORT_EPDR_EPD5 (0x20) -#define MCF5235_EPORT_EPDR_EPD6 (0x40) -#define MCF5235_EPORT_EPDR_EPD7 (0x80) -#define MCF5235_EPORT_EPPDR_EPPD1 (0x02) -#define MCF5235_EPORT_EPPDR_EPPD2 (0x04) -#define MCF5235_EPORT_EPPDR_EPPD3 (0x08) -#define MCF5235_EPORT_EPPDR_EPPD4 (0x10) -#define MCF5235_EPORT_EPPDR_EPPD5 (0x20) -#define MCF5235_EPORT_EPPDR_EPPD6 (0x40) -#define MCF5235_EPORT_EPPDR_EPPD7 (0x80) -#define MCF5235_EPORT_EPFR_EPF1 (0x02) -#define MCF5235_EPORT_EPFR_EPF2 (0x04) -#define MCF5235_EPORT_EPFR_EPF3 (0x08) -#define MCF5235_EPORT_EPFR_EPF4 (0x10) -#define MCF5235_EPORT_EPFR_EPF5 (0x20) -#define MCF5235_EPORT_EPFR_EPF6 (0x40) -#define MCF5235_EPORT_EPFR_EPF7 (0x80) - - -/********************************************************************* -* -* enhanced Time Processor Unit (ETPU) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_ETPU_EMCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0000))) -#define MCF5235_ETPU_ECDCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0004))) -#define MCF5235_ETPU_EMISCCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D000C))) -#define MCF5235_ETPU_ESCMODR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0010))) -#define MCF5235_ETPU_EECR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0014))) -#define MCF5235_ETPU_ETBCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0020))) -#define MCF5235_ETPU_ETB1R (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0024))) -#define MCF5235_ETPU_ETB2R (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0028))) -#define MCF5235_ETPU_EREDCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D002C))) -#define MCF5235_ETPU_ECISR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0200))) -#define MCF5235_ETPU_ECDTRSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0210))) -#define MCF5235_ETPU_ECIOSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0220))) -#define MCF5235_ETPU_ECDTROSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0230))) -#define MCF5235_ETPU_ECIER (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0240))) -#define MCF5235_ETPU_ECDTRER (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0250))) -#define MCF5235_ETPU_ECPSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0280))) -#define MCF5235_ETPU_ECSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0290))) -#define MCF5235_ETPU_EC0SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0404))) -#define MCF5235_ETPU_EC1SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0414))) -#define MCF5235_ETPU_EC2SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0424))) -#define MCF5235_ETPU_EC3SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0434))) -#define MCF5235_ETPU_EC4SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0444))) -#define MCF5235_ETPU_EC5SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0454))) -#define MCF5235_ETPU_EC6SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0464))) -#define MCF5235_ETPU_EC7SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0474))) -#define MCF5235_ETPU_EC8SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0484))) -#define MCF5235_ETPU_EC9SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0494))) -#define MCF5235_ETPU_EC10SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04A4))) -#define MCF5235_ETPU_EC11SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04B4))) -#define MCF5235_ETPU_EC12SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04C4))) -#define MCF5235_ETPU_EC13SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04D4))) -#define MCF5235_ETPU_EC14SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04E4))) -#define MCF5235_ETPU_EC15SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04F4))) -#define MCF5235_ETPU_EC16SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0504))) -#define MCF5235_ETPU_EC17SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0514))) -#define MCF5235_ETPU_EC18SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0524))) -#define MCF5235_ETPU_EC19SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0534))) -#define MCF5235_ETPU_EC20SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0544))) -#define MCF5235_ETPU_EC21SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0554))) -#define MCF5235_ETPU_EC22SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0564))) -#define MCF5235_ETPU_EC23SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0574))) -#define MCF5235_ETPU_EC24SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0584))) -#define MCF5235_ETPU_EC25SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0594))) -#define MCF5235_ETPU_EC26SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05A4))) -#define MCF5235_ETPU_EC27SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05B4))) -#define MCF5235_ETPU_EC28SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05C4))) -#define MCF5235_ETPU_EC29SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05D4))) -#define MCF5235_ETPU_EC30SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05E4))) -#define MCF5235_ETPU_EC31SCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05F4))) -#define MCF5235_ETPU_ECnSCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0404+((x)*0x010)))) -#define MCF5235_ETPU_EC0CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0400))) -#define MCF5235_ETPU_EC1CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0410))) -#define MCF5235_ETPU_EC2CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0420))) -#define MCF5235_ETPU_EC3CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0430))) -#define MCF5235_ETPU_EC4CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0440))) -#define MCF5235_ETPU_EC5CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0450))) -#define MCF5235_ETPU_EC6CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0460))) -#define MCF5235_ETPU_EC7CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0470))) -#define MCF5235_ETPU_EC8CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0480))) -#define MCF5235_ETPU_EC9CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0490))) -#define MCF5235_ETPU_EC10CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04A0))) -#define MCF5235_ETPU_EC11CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04B0))) -#define MCF5235_ETPU_EC12CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04C0))) -#define MCF5235_ETPU_EC13CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04D0))) -#define MCF5235_ETPU_EC14CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04E0))) -#define MCF5235_ETPU_EC15CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04F0))) -#define MCF5235_ETPU_EC16CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0500))) -#define MCF5235_ETPU_EC17CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0510))) -#define MCF5235_ETPU_EC18CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0520))) -#define MCF5235_ETPU_EC19CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0530))) -#define MCF5235_ETPU_EC20CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0540))) -#define MCF5235_ETPU_EC21CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0550))) -#define MCF5235_ETPU_EC22CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0560))) -#define MCF5235_ETPU_EC23CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0570))) -#define MCF5235_ETPU_EC24CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0580))) -#define MCF5235_ETPU_EC25CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0590))) -#define MCF5235_ETPU_EC26CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05A0))) -#define MCF5235_ETPU_EC27CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05B0))) -#define MCF5235_ETPU_EC28CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05C0))) -#define MCF5235_ETPU_EC29CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05D0))) -#define MCF5235_ETPU_EC30CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05E0))) -#define MCF5235_ETPU_EC31CR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05F0))) -#define MCF5235_ETPU_ECnCR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0400+((x)*0x010)))) -#define MCF5235_ETPU_EC0HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0408))) -#define MCF5235_ETPU_EC1HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0418))) -#define MCF5235_ETPU_EC2HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0428))) -#define MCF5235_ETPU_EC3HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0438))) -#define MCF5235_ETPU_EC4HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0448))) -#define MCF5235_ETPU_EC5HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0458))) -#define MCF5235_ETPU_EC6HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0468))) -#define MCF5235_ETPU_EC7HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0478))) -#define MCF5235_ETPU_EC8HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0488))) -#define MCF5235_ETPU_EC9HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0498))) -#define MCF5235_ETPU_EC10HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04A8))) -#define MCF5235_ETPU_EC11HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04B8))) -#define MCF5235_ETPU_EC12HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04C8))) -#define MCF5235_ETPU_EC13HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04D8))) -#define MCF5235_ETPU_EC14HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04E8))) -#define MCF5235_ETPU_EC15HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D04F8))) -#define MCF5235_ETPU_EC16HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0508))) -#define MCF5235_ETPU_EC17HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0518))) -#define MCF5235_ETPU_EC18HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0528))) -#define MCF5235_ETPU_EC19HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0538))) -#define MCF5235_ETPU_EC20HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0548))) -#define MCF5235_ETPU_EC21HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0558))) -#define MCF5235_ETPU_EC22HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0568))) -#define MCF5235_ETPU_EC23HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0578))) -#define MCF5235_ETPU_EC24HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0588))) -#define MCF5235_ETPU_EC25HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0598))) -#define MCF5235_ETPU_EC26HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05A8))) -#define MCF5235_ETPU_EC27HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05B8))) -#define MCF5235_ETPU_EC28HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05C8))) -#define MCF5235_ETPU_EC29HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05D8))) -#define MCF5235_ETPU_EC30HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05E8))) -#define MCF5235_ETPU_EC31HSSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D05F8))) -#define MCF5235_ETPU_ECnHSSR(x) (*(vuint32*)((uintptr_t)__IPSBAR + (0x1D0408+((x)*0x010)))) - -/* Bit definitions and macros for MCF5235_ETPU_EMCR */ -#define MCF5235_ETPU_EMCR_GTBE (0x00000001) -#define MCF5235_ETPU_EMCR_VIS (0x00000040) -#define MCF5235_ETPU_EMCR_SCMMISEN (0x00000200) -#define MCF5235_ETPU_EMCR_SCMMISF (0x00000400) -#define MCF5235_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16) -#define MCF5235_ETPU_EMCR_ILF2 (0x01000000) -#define MCF5235_ETPU_EMCR_ILF1 (0x02000000) -#define MCF5235_ETPU_EMCR_MGE2 (0x04000000) -#define MCF5235_ETPU_EMCR_MGE1 (0x08000000) -#define MCF5235_ETPU_EMCR_GEC (0x80000000) -#define MCF5235_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0) -#define MCF5235_ETPU_ECDCR_WR (0x00000080) -#define MCF5235_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8) -#define MCF5235_ETPU_ECDCR_PWIDTH (0x00008000) -#define MCF5235_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16) -#define MCF5235_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26) -#define MCF5235_ETPU_ECDCR_STS (0x80000000) -#define MCF5235_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0) -#define MCF5235_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14) -#define MCF5235_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16) -#define MCF5235_ETPU_EECR_HLTF (0x00800000) -#define MCF5235_ETPU_EECR_STF (0x10000000) -#define MCF5235_ETPU_EECR_MDIS (0x40000000) -#define MCF5235_ETPU_EECR_FEND (0x80000000) -#define MCF5235_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0) -#define MCF5235_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14) -#define MCF5235_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16) -#define MCF5235_ETPU_ETBCR_AM (0x02000000) -#define MCF5235_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27) -#define MCF5235_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29) -#define MCF5235_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0) -#define MCF5235_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0) -#define MCF5235_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0) -#define MCF5235_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8) -#define MCF5235_ETPU_EREDCR_RSC2 (0x00004000) -#define MCF5235_ETPU_EREDCR_REN2 (0x00008000) -#define MCF5235_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16) -#define MCF5235_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24) -#define MCF5235_ETPU_EREDCR_RSC1 (0x40000000) -#define MCF5235_ETPU_EREDCR_REN1 (0x80000000) -#define MCF5235_ETPU_ECISR_CIS0 (0x00000001) -#define MCF5235_ETPU_ECISR_CIS1 (0x00000002) -#define MCF5235_ETPU_ECISR_CIS2 (0x00000004) -#define MCF5235_ETPU_ECISR_CIS3 (0x00000008) -#define MCF5235_ETPU_ECISR_CIS4 (0x00000010) -#define MCF5235_ETPU_ECISR_CIS5 (0x00000020) -#define MCF5235_ETPU_ECISR_CIS6 (0x00000040) -#define MCF5235_ETPU_ECISR_CIS7 (0x00000080) -#define MCF5235_ETPU_ECISR_CIS8 (0x00000100) -#define MCF5235_ETPU_ECISR_CIS9 (0x00000200) -#define MCF5235_ETPU_ECISR_CIS10 (0x00000400) -#define MCF5235_ETPU_ECISR_CIS11 (0x00000800) -#define MCF5235_ETPU_ECISR_CIS12 (0x00001000) -#define MCF5235_ETPU_ECISR_CIS13 (0x00002000) -#define MCF5235_ETPU_ECISR_CIS14 (0x00004000) -#define MCF5235_ETPU_ECISR_CIS15 (0x00008000) -#define MCF5235_ETPU_ECISR_CIS16 (0x00010000) -#define MCF5235_ETPU_ECISR_CIS17 (0x00020000) -#define MCF5235_ETPU_ECISR_CIS18 (0x00040000) -#define MCF5235_ETPU_ECISR_CIS19 (0x00080000) -#define MCF5235_ETPU_ECISR_CIS20 (0x00100000) -#define MCF5235_ETPU_ECISR_CIS21 (0x00200000) -#define MCF5235_ETPU_ECISR_CIS22 (0x00400000) -#define MCF5235_ETPU_ECISR_CIS23 (0x00800000) -#define MCF5235_ETPU_ECISR_CIS24 (0x01000000) -#define MCF5235_ETPU_ECISR_CIS25 (0x02000000) -#define MCF5235_ETPU_ECISR_CIS26 (0x04000000) -#define MCF5235_ETPU_ECISR_CIS27 (0x08000000) -#define MCF5235_ETPU_ECISR_CIS28 (0x10000000) -#define MCF5235_ETPU_ECISR_CIS29 (0x20000000) -#define MCF5235_ETPU_ECISR_CIS30 (0x40000000) -#define MCF5235_ETPU_ECISR_CIS31 (0x80000000) -#define MCF5235_ETPU_ECDTRSR_DTRS0 (0x00000001) -#define MCF5235_ETPU_ECDTRSR_DTRS1 (0x00000002) -#define MCF5235_ETPU_ECDTRSR_DTRS2 (0x00000004) -#define MCF5235_ETPU_ECDTRSR_DTRS3 (0x00000008) -#define MCF5235_ETPU_ECDTRSR_DTRS4 (0x00000010) -#define MCF5235_ETPU_ECDTRSR_DTRS5 (0x00000020) -#define MCF5235_ETPU_ECDTRSR_DTRS6 (0x00000040) -#define MCF5235_ETPU_ECDTRSR_DTRS7 (0x00000080) -#define MCF5235_ETPU_ECDTRSR_DTRS8 (0x00000100) -#define MCF5235_ETPU_ECDTRSR_DTRS9 (0x00000200) -#define MCF5235_ETPU_ECDTRSR_DTRS10 (0x00000400) -#define MCF5235_ETPU_ECDTRSR_DTRS11 (0x00000800) -#define MCF5235_ETPU_ECDTRSR_DTRS12 (0x00001000) -#define MCF5235_ETPU_ECDTRSR_DTRS13 (0x00002000) -#define MCF5235_ETPU_ECDTRSR_DTRS14 (0x00004000) -#define MCF5235_ETPU_ECDTRSR_DTRS15 (0x00008000) -#define MCF5235_ETPU_ECDTRSR_DTRS16 (0x00010000) -#define MCF5235_ETPU_ECDTRSR_DTRS17 (0x00020000) -#define MCF5235_ETPU_ECDTRSR_DTRS18 (0x00040000) -#define MCF5235_ETPU_ECDTRSR_DTRS19 (0x00080000) -#define MCF5235_ETPU_ECDTRSR_DTRS20 (0x00100000) -#define MCF5235_ETPU_ECDTRSR_DTRS21 (0x00200000) -#define MCF5235_ETPU_ECDTRSR_DTRS22 (0x00400000) -#define MCF5235_ETPU_ECDTRSR_DTRS23 (0x00800000) -#define MCF5235_ETPU_ECDTRSR_DTRS24 (0x01000000) -#define MCF5235_ETPU_ECDTRSR_DTRS25 (0x02000000) -#define MCF5235_ETPU_ECDTRSR_DTRS26 (0x04000000) -#define MCF5235_ETPU_ECDTRSR_DTRS27 (0x08000000) -#define MCF5235_ETPU_ECDTRSR_DTRS28 (0x10000000) -#define MCF5235_ETPU_ECDTRSR_DTRS29 (0x20000000) -#define MCF5235_ETPU_ECDTRSR_DTRS30 (0x40000000) -#define MCF5235_ETPU_ECDTRSR_DTRS31 (0x80000000) -#define MCF5235_ETPU_ECIOSR_CIOS0 (0x00000001) -#define MCF5235_ETPU_ECIOSR_CIOS1 (0x00000002) -#define MCF5235_ETPU_ECIOSR_CIOS2 (0x00000004) -#define MCF5235_ETPU_ECIOSR_CIOS3 (0x00000008) -#define MCF5235_ETPU_ECIOSR_CIOS4 (0x00000010) -#define MCF5235_ETPU_ECIOSR_CIOS5 (0x00000020) -#define MCF5235_ETPU_ECIOSR_CIOS6 (0x00000040) -#define MCF5235_ETPU_ECIOSR_CIOS7 (0x00000080) -#define MCF5235_ETPU_ECIOSR_CIOS8 (0x00000100) -#define MCF5235_ETPU_ECIOSR_CIOS9 (0x00000200) -#define MCF5235_ETPU_ECIOSR_CIOS10 (0x00000400) -#define MCF5235_ETPU_ECIOSR_CIOS11 (0x00000800) -#define MCF5235_ETPU_ECIOSR_CIOS12 (0x00001000) -#define MCF5235_ETPU_ECIOSR_CIOS13 (0x00002000) -#define MCF5235_ETPU_ECIOSR_CIOS14 (0x00004000) -#define MCF5235_ETPU_ECIOSR_CIOS15 (0x00008000) -#define MCF5235_ETPU_ECIOSR_CIOS16 (0x00010000) -#define MCF5235_ETPU_ECIOSR_CIOS17 (0x00020000) -#define MCF5235_ETPU_ECIOSR_CIOS18 (0x00040000) -#define MCF5235_ETPU_ECIOSR_CIOS19 (0x00080000) -#define MCF5235_ETPU_ECIOSR_CIOS20 (0x00100000) -#define MCF5235_ETPU_ECIOSR_CIOS21 (0x00200000) -#define MCF5235_ETPU_ECIOSR_CIOS22 (0x00400000) -#define MCF5235_ETPU_ECIOSR_CIOS23 (0x00800000) -#define MCF5235_ETPU_ECIOSR_CIOS24 (0x01000000) -#define MCF5235_ETPU_ECIOSR_CIOS25 (0x02000000) -#define MCF5235_ETPU_ECIOSR_CIOS26 (0x04000000) -#define MCF5235_ETPU_ECIOSR_CIOS27 (0x08000000) -#define MCF5235_ETPU_ECIOSR_CIOS28 (0x10000000) -#define MCF5235_ETPU_ECIOSR_CIOS29 (0x20000000) -#define MCF5235_ETPU_ECIOSR_CIOS30 (0x40000000) -#define MCF5235_ETPU_ECIOSR_CIOS31 (0x80000000) -#define MCF5235_ETPU_ECDTROSR_DTROS0 (0x00000001) -#define MCF5235_ETPU_ECDTROSR_DTROS1 (0x00000002) -#define MCF5235_ETPU_ECDTROSR_DTROS2 (0x00000004) -#define MCF5235_ETPU_ECDTROSR_DTROS3 (0x00000008) -#define MCF5235_ETPU_ECDTROSR_DTROS4 (0x00000010) -#define MCF5235_ETPU_ECDTROSR_DTROS5 (0x00000020) -#define MCF5235_ETPU_ECDTROSR_DTROS6 (0x00000040) -#define MCF5235_ETPU_ECDTROSR_DTROS7 (0x00000080) -#define MCF5235_ETPU_ECDTROSR_DTROS8 (0x00000100) -#define MCF5235_ETPU_ECDTROSR_DTROS9 (0x00000200) -#define MCF5235_ETPU_ECDTROSR_DTROS10 (0x00000400) -#define MCF5235_ETPU_ECDTROSR_DTROS11 (0x00000800) -#define MCF5235_ETPU_ECDTROSR_DTROS12 (0x00001000) -#define MCF5235_ETPU_ECDTROSR_DTROS13 (0x00002000) -#define MCF5235_ETPU_ECDTROSR_DTROS14 (0x00004000) -#define MCF5235_ETPU_ECDTROSR_DTROS15 (0x00008000) -#define MCF5235_ETPU_ECDTROSR_DTROS16 (0x00010000) -#define MCF5235_ETPU_ECDTROSR_DTROS17 (0x00020000) -#define MCF5235_ETPU_ECDTROSR_DTROS18 (0x00040000) -#define MCF5235_ETPU_ECDTROSR_DTROS19 (0x00080000) -#define MCF5235_ETPU_ECDTROSR_DTROS20 (0x00100000) -#define MCF5235_ETPU_ECDTROSR_DTROS21 (0x00200000) -#define MCF5235_ETPU_ECDTROSR_DTROS22 (0x00400000) -#define MCF5235_ETPU_ECDTROSR_DTROS23 (0x00800000) -#define MCF5235_ETPU_ECDTROSR_DTROS24 (0x01000000) -#define MCF5235_ETPU_ECDTROSR_DTROS25 (0x02000000) -#define MCF5235_ETPU_ECDTROSR_DTROS26 (0x04000000) -#define MCF5235_ETPU_ECDTROSR_DTROS27 (0x08000000) -#define MCF5235_ETPU_ECDTROSR_DTROS28 (0x10000000) -#define MCF5235_ETPU_ECDTROSR_DTROS29 (0x20000000) -#define MCF5235_ETPU_ECDTROSR_DTROS30 (0x40000000) -#define MCF5235_ETPU_ECDTROSR_DTROS31 (0x80000000) -#define MCF5235_ETPU_ECIER_CIE0 (0x00000001) -#define MCF5235_ETPU_ECIER_CIE1 (0x00000002) -#define MCF5235_ETPU_ECIER_CIE2 (0x00000004) -#define MCF5235_ETPU_ECIER_CIE3 (0x00000008) -#define MCF5235_ETPU_ECIER_CIE4 (0x00000010) -#define MCF5235_ETPU_ECIER_CIE5 (0x00000020) -#define MCF5235_ETPU_ECIER_CIE6 (0x00000040) -#define MCF5235_ETPU_ECIER_CIE7 (0x00000080) -#define MCF5235_ETPU_ECIER_CIE8 (0x00000100) -#define MCF5235_ETPU_ECIER_CIE9 (0x00000200) -#define MCF5235_ETPU_ECIER_CIE10 (0x00000400) -#define MCF5235_ETPU_ECIER_CIE11 (0x00000800) -#define MCF5235_ETPU_ECIER_CIE12 (0x00001000) -#define MCF5235_ETPU_ECIER_CIE13 (0x00002000) -#define MCF5235_ETPU_ECIER_CIE14 (0x00004000) -#define MCF5235_ETPU_ECIER_CIE15 (0x00008000) -#define MCF5235_ETPU_ECIER_CIE16 (0x00010000) -#define MCF5235_ETPU_ECIER_CIE17 (0x00020000) -#define MCF5235_ETPU_ECIER_CIE18 (0x00040000) -#define MCF5235_ETPU_ECIER_CIE19 (0x00080000) -#define MCF5235_ETPU_ECIER_CIE20 (0x00100000) -#define MCF5235_ETPU_ECIER_CIE21 (0x00200000) -#define MCF5235_ETPU_ECIER_CIE22 (0x00400000) -#define MCF5235_ETPU_ECIER_CIE23 (0x00800000) -#define MCF5235_ETPU_ECIER_CIE24 (0x01000000) -#define MCF5235_ETPU_ECIER_CIE25 (0x02000000) -#define MCF5235_ETPU_ECIER_CIE26 (0x04000000) -#define MCF5235_ETPU_ECIER_CIE27 (0x08000000) -#define MCF5235_ETPU_ECIER_CIE28 (0x10000000) -#define MCF5235_ETPU_ECIER_CIE29 (0x20000000) -#define MCF5235_ETPU_ECIER_CIE30 (0x40000000) -#define MCF5235_ETPU_ECIER_CIE31 (0x80000000) -#define MCF5235_ETPU_ECDTRER_DTRE0 (0x00000001) -#define MCF5235_ETPU_ECDTRER_DTRE1 (0x00000002) -#define MCF5235_ETPU_ECDTRER_DTRE2 (0x00000004) -#define MCF5235_ETPU_ECDTRER_DTRE3 (0x00000008) -#define MCF5235_ETPU_ECDTRER_DTRE4 (0x00000010) -#define MCF5235_ETPU_ECDTRER_DTRE5 (0x00000020) -#define MCF5235_ETPU_ECDTRER_DTRE6 (0x00000040) -#define MCF5235_ETPU_ECDTRER_DTRE7 (0x00000080) -#define MCF5235_ETPU_ECDTRER_DTRE8 (0x00000100) -#define MCF5235_ETPU_ECDTRER_DTRE9 (0x00000200) -#define MCF5235_ETPU_ECDTRER_DTRE10 (0x00000400) -#define MCF5235_ETPU_ECDTRER_DTRE11 (0x00000800) -#define MCF5235_ETPU_ECDTRER_DTRE12 (0x00001000) -#define MCF5235_ETPU_ECDTRER_DTRE13 (0x00002000) -#define MCF5235_ETPU_ECDTRER_DTRE14 (0x00004000) -#define MCF5235_ETPU_ECDTRER_DTRE15 (0x00008000) -#define MCF5235_ETPU_ECDTRER_DTRE16 (0x00010000) -#define MCF5235_ETPU_ECDTRER_DTRE17 (0x00020000) -#define MCF5235_ETPU_ECDTRER_DTRE18 (0x00040000) -#define MCF5235_ETPU_ECDTRER_DTRE19 (0x00080000) -#define MCF5235_ETPU_ECDTRER_DTRE20 (0x00100000) -#define MCF5235_ETPU_ECDTRER_DTRE21 (0x00200000) -#define MCF5235_ETPU_ECDTRER_DTRE22 (0x00400000) -#define MCF5235_ETPU_ECDTRER_DTRE23 (0x00800000) -#define MCF5235_ETPU_ECDTRER_DTRE24 (0x01000000) -#define MCF5235_ETPU_ECDTRER_DTRE25 (0x02000000) -#define MCF5235_ETPU_ECDTRER_DTRE26 (0x04000000) -#define MCF5235_ETPU_ECDTRER_DTRE27 (0x08000000) -#define MCF5235_ETPU_ECDTRER_DTRE28 (0x10000000) -#define MCF5235_ETPU_ECDTRER_DTRE29 (0x20000000) -#define MCF5235_ETPU_ECDTRER_DTRE30 (0x40000000) -#define MCF5235_ETPU_ECDTRER_DTRE31 (0x80000000) -#define MCF5235_ETPU_ECPSSR_SR0 (0x00000001) -#define MCF5235_ETPU_ECPSSR_SR1 (0x00000002) -#define MCF5235_ETPU_ECPSSR_SR2 (0x00000004) -#define MCF5235_ETPU_ECPSSR_SR3 (0x00000008) -#define MCF5235_ETPU_ECPSSR_SR4 (0x00000010) -#define MCF5235_ETPU_ECPSSR_SR5 (0x00000020) -#define MCF5235_ETPU_ECPSSR_SR6 (0x00000040) -#define MCF5235_ETPU_ECPSSR_SR7 (0x00000080) -#define MCF5235_ETPU_ECPSSR_SR8 (0x00000100) -#define MCF5235_ETPU_ECPSSR_SR9 (0x00000200) -#define MCF5235_ETPU_ECPSSR_SR10 (0x00000400) -#define MCF5235_ETPU_ECPSSR_SR11 (0x00000800) -#define MCF5235_ETPU_ECPSSR_SR12 (0x00001000) -#define MCF5235_ETPU_ECPSSR_SR13 (0x00002000) -#define MCF5235_ETPU_ECPSSR_SR14 (0x00004000) -#define MCF5235_ETPU_ECPSSR_SR15 (0x00008000) -#define MCF5235_ETPU_ECPSSR_SR16 (0x00010000) -#define MCF5235_ETPU_ECPSSR_SR17 (0x00020000) -#define MCF5235_ETPU_ECPSSR_SR18 (0x00040000) -#define MCF5235_ETPU_ECPSSR_SR19 (0x00080000) -#define MCF5235_ETPU_ECPSSR_SR20 (0x00100000) -#define MCF5235_ETPU_ECPSSR_SR21 (0x00200000) -#define MCF5235_ETPU_ECPSSR_SR22 (0x00400000) -#define MCF5235_ETPU_ECPSSR_SR23 (0x00800000) -#define MCF5235_ETPU_ECPSSR_SR24 (0x01000000) -#define MCF5235_ETPU_ECPSSR_SR25 (0x02000000) -#define MCF5235_ETPU_ECPSSR_SR26 (0x04000000) -#define MCF5235_ETPU_ECPSSR_SR27 (0x08000000) -#define MCF5235_ETPU_ECPSSR_SR28 (0x10000000) -#define MCF5235_ETPU_ECPSSR_SR29 (0x20000000) -#define MCF5235_ETPU_ECPSSR_SR30 (0x40000000) -#define MCF5235_ETPU_ECPSSR_SR31 (0x80000000) -#define MCF5235_ETPU_ECSSR_SS0 (0x00000001) -#define MCF5235_ETPU_ECSSR_SS1 (0x00000002) -#define MCF5235_ETPU_ECSSR_SS2 (0x00000004) -#define MCF5235_ETPU_ECSSR_SS3 (0x00000008) -#define MCF5235_ETPU_ECSSR_SS4 (0x00000010) -#define MCF5235_ETPU_ECSSR_SS5 (0x00000020) -#define MCF5235_ETPU_ECSSR_SS6 (0x00000040) -#define MCF5235_ETPU_ECSSR_SS7 (0x00000080) -#define MCF5235_ETPU_ECSSR_SS8 (0x00000100) -#define MCF5235_ETPU_ECSSR_SS9 (0x00000200) -#define MCF5235_ETPU_ECSSR_SS10 (0x00000400) -#define MCF5235_ETPU_ECSSR_SS11 (0x00000800) -#define MCF5235_ETPU_ECSSR_SS12 (0x00001000) -#define MCF5235_ETPU_ECSSR_SS13 (0x00002000) -#define MCF5235_ETPU_ECSSR_SS14 (0x00004000) -#define MCF5235_ETPU_ECSSR_SS15 (0x00008000) -#define MCF5235_ETPU_ECSSR_SS16 (0x00010000) -#define MCF5235_ETPU_ECSSR_SS17 (0x00020000) -#define MCF5235_ETPU_ECSSR_SS18 (0x00040000) -#define MCF5235_ETPU_ECSSR_SS19 (0x00080000) -#define MCF5235_ETPU_ECSSR_SS20 (0x00100000) -#define MCF5235_ETPU_ECSSR_SS21 (0x00200000) -#define MCF5235_ETPU_ECSSR_SS22 (0x00400000) -#define MCF5235_ETPU_ECSSR_SS23 (0x00800000) -#define MCF5235_ETPU_ECSSR_SS24 (0x01000000) -#define MCF5235_ETPU_ECSSR_SS25 (0x02000000) -#define MCF5235_ETPU_ECSSR_SS26 (0x04000000) -#define MCF5235_ETPU_ECSSR_SS27 (0x08000000) -#define MCF5235_ETPU_ECSSR_SS28 (0x10000000) -#define MCF5235_ETPU_ECSSR_SS29 (0x20000000) -#define MCF5235_ETPU_ECSSR_SS30 (0x40000000) -#define MCF5235_ETPU_ECSSR_SS31 (0x80000000) -#define MCF5235_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0) -#define MCF5235_ETPU_ECnSCR_OBE (0x00002000) -#define MCF5235_ETPU_ECnSCR_OPS (0x00004000) -#define MCF5235_ETPU_ECnSCR_IPS (0x00008000) -#define MCF5235_ETPU_ECnSCR_DTROS (0x00400000) -#define MCF5235_ETPU_ECnSCR_DTRS (0x00800000) -#define MCF5235_ETPU_ECnSCR_CIOS (0x40000000) -#define MCF5235_ETPU_ECnSCR_CIS (0x80000000) -#define MCF5235_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0) -#define MCF5235_ETPU_ECnCR_OPOL (0x00004000) -#define MCF5235_ETPU_ECnCR_ODIS (0x00008000) -#define MCF5235_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16) -#define MCF5235_ETPU_ECnCR_ETCS (0x01000000) -#define MCF5235_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28) -#define MCF5235_ETPU_ECnCR_DTRE (0x40000000) -#define MCF5235_ETPU_ECnCR_CIE (0x80000000) -#define MCF5235_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0) - - -/********************************************************************* -* -* Fast Ethernet Controller (FEC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_FEC_EIR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001004))) -#define MCF5235_FEC_EIMR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001008))) -#define MCF5235_FEC_RDAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001010))) -#define MCF5235_FEC_TDAR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001014))) -#define MCF5235_FEC_ECR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001024))) -#define MCF5235_FEC_MMFR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001040))) -#define MCF5235_FEC_MSCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001044))) -#define MCF5235_FEC_MIBC (*(vuint32*)((uintptr_t)__IPSBAR + (0x001064))) -#define MCF5235_FEC_RCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001084))) -#define MCF5235_FEC_TCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010C4))) -#define MCF5235_FEC_PALR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010E4))) -#define MCF5235_FEC_PAUR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010E8))) -#define MCF5235_FEC_OPD (*(vuint32*)((uintptr_t)__IPSBAR + (0x0010EC))) -#define MCF5235_FEC_IAUR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001118))) -#define MCF5235_FEC_IALR (*(vuint32*)((uintptr_t)__IPSBAR + (0x00111C))) -#define MCF5235_FEC_GAUR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001120))) -#define MCF5235_FEC_GALR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001124))) -#define MCF5235_FEC_TFWR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001144))) -#define MCF5235_FEC_FRBR (*(vuint32*)((uintptr_t)__IPSBAR + (0x00114C))) -#define MCF5235_FEC_FRSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001150))) -#define MCF5235_FEC_ERDSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001180))) -#define MCF5235_FEC_ETDSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001184))) -#define MCF5235_FEC_EMRBR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001188))) -#define MCF5235_FEC_RMON_T_DROP (*(vuint32*)((uintptr_t)__IPSBAR + (0x001200))) -#define MCF5235_FEC_RMON_T_PACKETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x001204))) -#define MCF5235_FEC_RMON_T_BC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x001208))) -#define MCF5235_FEC_RMON_T_MC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x00120C))) -#define MCF5235_FEC_RMON_T_CRC_ALIGN (*(vuint32*)((uintptr_t)__IPSBAR + (0x001210))) -#define MCF5235_FEC_RMON_T_UNDERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001214))) -#define MCF5235_FEC_RMON_T_OVERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001218))) -#define MCF5235_FEC_RMON_T_FRAG (*(vuint32*)((uintptr_t)__IPSBAR + (0x00121C))) -#define MCF5235_FEC_RMON_T_JAB (*(vuint32*)((uintptr_t)__IPSBAR + (0x001220))) -#define MCF5235_FEC_RMON_T_COL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001224))) -#define MCF5235_FEC_RMON_T_P64 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001228))) -#define MCF5235_FEC_RMON_T_P65TO127 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00122C))) -#define MCF5235_FEC_RMON_T_P128TO255 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001230))) -#define MCF5235_FEC_RMON_T_P256TO511 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001234))) -#define MCF5235_FEC_RMON_T_P512TO1023 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001238))) -#define MCF5235_FEC_RMON_T_P1024TO2047 (*(vuint32*)((uintptr_t)__IPSBAR + (0x00123C))) -#define MCF5235_FEC_RMON_T_P_GTE2048 (*(vuint32*)((uintptr_t)__IPSBAR + (0x001240))) -#define MCF5235_FEC_RMON_T_OCTETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x001244))) -#define MCF5235_FEC_IEEE_T_DROP (*(vuint32*)((uintptr_t)__IPSBAR + (0x001248))) -#define MCF5235_FEC_IEEE_T_FRAME_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x00124C))) -#define MCF5235_FEC_IEEE_T_1COL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001250))) -#define MCF5235_FEC_IEEE_T_MCOL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001254))) -#define MCF5235_FEC_IEEE_T_DEF (*(vuint32*)((uintptr_t)__IPSBAR + (0x001258))) -#define MCF5235_FEC_IEEE_T_LCOL (*(vuint32*)((uintptr_t)__IPSBAR + (0x00125C))) -#define MCF5235_FEC_IEEE_T_EXCOL (*(vuint32*)((uintptr_t)__IPSBAR + (0x001260))) -#define MCF5235_FEC_IEEE_T_MACERR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001264))) -#define MCF5235_FEC_IEEE_T_CSERR (*(vuint32*)((uintptr_t)__IPSBAR + (0x001268))) -#define MCF5235_FEC_IEEE_T_SQE (*(vuint32*)((uintptr_t)__IPSBAR + (0x00126C))) -#define MCF5235_FEC_IEEE_T_FDXFC (*(vuint32*)((uintptr_t)__IPSBAR + (0x001270))) -#define MCF5235_FEC_IEEE_T_OCTETS_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x001274))) -#define MCF5235_FEC_RMON_R_PACKETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x001284))) -#define MCF5235_FEC_RMON_R_BC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x001288))) -#define MCF5235_FEC_RMON_R_MC_PKT (*(vuint32*)((uintptr_t)__IPSBAR + (0x00128C))) -#define MCF5235_FEC_RMON_R_CRC_ALIGN (*(vuint32*)((uintptr_t)__IPSBAR + (0x001290))) -#define MCF5235_FEC_RMON_R_UNDERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001294))) -#define MCF5235_FEC_RMON_R_OVERSIZE (*(vuint32*)((uintptr_t)__IPSBAR + (0x001298))) -#define MCF5235_FEC_RMON_R_FRAG (*(vuint32*)((uintptr_t)__IPSBAR + (0x00129C))) -#define MCF5235_FEC_RMON_R_JAB (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012A0))) -#define MCF5235_FEC_RMON_R_RESVD_0 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012A4))) -#define MCF5235_FEC_RMON_R_P64 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012A8))) -#define MCF5235_FEC_RMON_R_P65T0127 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012AC))) -#define MCF5235_FEC_RMON_R_P128TO255 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012B0))) -#define MCF5235_FEC_RMON_R_P256TO511 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012B4))) -#define MCF5235_FEC_RMON_R_P512TO1023 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012B8))) -#define MCF5235_FEC_RMON_R_GTE2048 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012C0))) -#define MCF5235_FEC_RMON_R_P1024TO2047 (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012BC))) -#define MCF5235_FEC_RMON_R_OCTETS (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012C4))) -#define MCF5235_FEC_IEEE_R_DROP (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012C8))) -#define MCF5235_FEC_IEEE_R_FRAME_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012CC))) -#define MCF5235_FEC_IEEE_R_CRC (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012D0))) -#define MCF5235_FEC_IEEE_R_ALIGN (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012D4))) -#define MCF5235_FEC_IEEE_R_MACERR (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012D8))) -#define MCF5235_FEC_IEEE_R_FDXFC (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012DC))) -#define MCF5235_FEC_IEEE_R_OCTETS_OK (*(vuint32*)((uintptr_t)__IPSBAR + (0x0012E0))) - -/* Bit definitions and macros for MCF5235_FEC_EIR */ -#define MCF5235_FEC_EIR_UN (0x00080000) -#define MCF5235_FEC_EIR_RL (0x00100000) -#define MCF5235_FEC_EIR_LC (0x00200000) -#define MCF5235_FEC_EIR_EBERR (0x00400000) -#define MCF5235_FEC_EIR_MII (0x00800000) -#define MCF5235_FEC_EIR_RXB (0x01000000) -#define MCF5235_FEC_EIR_RXF (0x02000000) -#define MCF5235_FEC_EIR_TXB (0x04000000) -#define MCF5235_FEC_EIR_TXF (0x08000000) -#define MCF5235_FEC_EIR_GRA (0x10000000) -#define MCF5235_FEC_EIR_BABT (0x20000000) -#define MCF5235_FEC_EIR_BABR (0x40000000) -#define MCF5235_FEC_EIR_HBERR (0x80000000) -#define MCF5235_FEC_EIMR_UN (0x00080000) -#define MCF5235_FEC_EIMR_RL (0x00100000) -#define MCF5235_FEC_EIMR_LC (0x00200000) -#define MCF5235_FEC_EIMR_EBERR (0x00400000) -#define MCF5235_FEC_EIMR_MII (0x00800000) -#define MCF5235_FEC_EIMR_RXB (0x01000000) -#define MCF5235_FEC_EIMR_RXF (0x02000000) -#define MCF5235_FEC_EIMR_TXB (0x04000000) -#define MCF5235_FEC_EIMR_TXF (0x08000000) -#define MCF5235_FEC_EIMR_GRA (0x10000000) -#define MCF5235_FEC_EIMR_BABT (0x20000000) -#define MCF5235_FEC_EIMR_BABR (0x40000000) -#define MCF5235_FEC_EIMR_HBERR (0x80000000) -#define MCF5235_FEC_RDAR_R_DES_ACTIVE (0x01000000) -#define MCF5235_FEC_TDAR_X_DES_ACTIVE (0x01000000) -#define MCF5235_FEC_ECR_RESET (0x00000001) -#define MCF5235_FEC_ECR_ETHER_EN (0x00000002) -#define MCF5235_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) -#define MCF5235_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) -#define MCF5235_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) -#define MCF5235_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) -#define MCF5235_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) -#define MCF5235_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) -#define MCF5235_FEC_MMFR_ST_01 (0x40000000) -#define MCF5235_FEC_MMFR_OP_READ (0x20000000) -#define MCF5235_FEC_MMFR_OP_WRITE (0x10000000) -#define MCF5235_FEC_MMFR_TA_10 (0x00020000) -#define MCF5235_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) -#define MCF5235_FEC_MSCR_DIS_PREAMBLE (0x00000080) -#define MCF5235_FEC_MIBC_MIB_IDLE (0x40000000) -#define MCF5235_FEC_MIBC_MIB_DISABLE (0x80000000) -#define MCF5235_FEC_RCR_LOOP (0x00000001) -#define MCF5235_FEC_RCR_DRT (0x00000002) -#define MCF5235_FEC_RCR_MII_MODE (0x00000004) -#define MCF5235_FEC_RCR_PROM (0x00000008) -#define MCF5235_FEC_RCR_BC_REJ (0x00000010) -#define MCF5235_FEC_RCR_FCE (0x00000020) -#define MCF5235_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) -#define MCF5235_FEC_TCR_GTS (0x00000001) -#define MCF5235_FEC_TCR_HBC (0x00000002) -#define MCF5235_FEC_TCR_FDEN (0x00000004) -#define MCF5235_FEC_TCR_TFC_PAUSE (0x00000008) -#define MCF5235_FEC_TCR_RFC_PAUSE (0x00000010) -#define MCF5235_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) -#define MCF5235_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) -#define MCF5235_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) -#define MCF5235_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) -#define MCF5235_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) -#define MCF5235_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) -#define MCF5235_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) -#define MCF5235_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) -#define MCF5235_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) -#define MCF5235_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) -#define MCF5235_FEC_TxBD_R 0x8000 -#define MCF5235_FEC_TxBD_BUSY 0x4000 -#define MCF5235_FEC_TxBD_TO1 0x4000 -#define MCF5235_FEC_TxBD_W 0x2000 -#define MCF5235_FEC_TxBD_TO2 0x1000 -#define MCF5235_FEC_TxBD_FIRST 0x1000 -#define MCF5235_FEC_TxBD_L 0x0800 -#define MCF5235_FEC_TxBD_TC 0x0400 -#define MCF5235_FEC_TxBD_DEF 0x0200 -#define MCF5235_FEC_TxBD_HB 0x0100 -#define MCF5235_FEC_TxBD_LC 0x0080 -#define MCF5235_FEC_TxBD_RL 0x0040 -#define MCF5235_FEC_TxBD_UN 0x0002 -#define MCF5235_FEC_TxBD_CSL 0x0001 -#define MCF5235_FEC_RxBD_E 0x8000 -#define MCF5235_FEC_RxBD_INUSE 0x4000 -#define MCF5235_FEC_RxBD_R01 0x4000 -#define MCF5235_FEC_RxBD_W 0x2000 -#define MCF5235_FEC_RxBD_R02 0x1000 -#define MCF5235_FEC_RxBD_L 0x0800 -#define MCF5235_FEC_RxBD_M 0x0100 -#define MCF5235_FEC_RxBD_BC 0x0080 -#define MCF5235_FEC_RxBD_MC 0x0040 -#define MCF5235_FEC_RxBD_LG 0x0020 -#define MCF5235_FEC_RxBD_NO 0x0010 -#define MCF5235_FEC_RxBD_CR 0x0004 -#define MCF5235_FEC_RxBD_OV 0x0002 -#define MCF5235_FEC_RxBD_TR 0x0001 - -/************************************************************ -* -* Clock -*************************************************************/ -/* Register read/write macros */ -#define MCF5235_FMPLL_SYNCR (*(vuint32*)((uintptr_t)__IPSBAR + (0x120000))) -#define MCF5235_FMPLL_SYNSR (*(vuint32*)((uintptr_t)__IPSBAR + (0x120004))) - -/* Bit definitions and macros for MCF5235_FMPLL_SYNCR */ -#define MCF5235_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0) -#define MCF5235_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10) -#define MCF5235_FMPLL_SYNCR_RATE (0x00001000) -#define MCF5235_FMPLL_SYNCR_LOCIRQ (0x00002000) -#define MCF5235_FMPLL_SYNCR_LOLIRQ (0x00004000) -#define MCF5235_FMPLL_SYNCR_DISCLK (0x00008000) -#define MCF5235_FMPLL_SYNCR_LOCRE (0x00010000) -#define MCF5235_FMPLL_SYNCR_LOLRE (0x00020000) -#define MCF5235_FMPLL_SYNCR_LOCEN (0x00040000) -#define MCF5235_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19) -#define MCF5235_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24) -#define MCF5235_FMPLL_SYNSR_CALPASS (0x00000001) -#define MCF5235_FMPLL_SYNSR_CALDONE (0x00000002) -#define MCF5235_FMPLL_SYNSR_LOCF (0x00000004) -#define MCF5235_FMPLL_SYNSR_LOCK (0x00000008) -#define MCF5235_FMPLL_SYNSR_LOCKS (0x00000010) -#define MCF5235_FMPLL_SYNSR_PLLREF (0x00000020) -#define MCF5235_FMPLL_SYNSR_PLLSEL (0x00000040) -#define MCF5235_FMPLL_SYNSR_MODE (0x00000080) -#define MCF5235_FMPLL_SYNSR_LOC (0x00000100) -#define MCF5235_FMPLL_SYNSR_LOLF (0x00000200) - - -/********************************************************************* -* -* General Purpose I/O (GPIO) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_GPIO_PODR_ADDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100000))) -#define MCF5235_GPIO_PODR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100001))) -#define MCF5235_GPIO_PODR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100002))) -#define MCF5235_GPIO_PODR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100003))) -#define MCF5235_GPIO_PODR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100004))) -#define MCF5235_GPIO_PODR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100005))) -#define MCF5235_GPIO_PODR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100006))) -#define MCF5235_GPIO_PODR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100007))) -#define MCF5235_GPIO_PODR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100008))) -#define MCF5235_GPIO_PODR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100009))) -#define MCF5235_GPIO_PODR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10000A))) -#define MCF5235_GPIO_PODR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10000B))) -#define MCF5235_GPIO_PODR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10000C))) -#define MCF5235_GPIO_PDDR_APDDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100010))) -#define MCF5235_GPIO_PDDR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100011))) -#define MCF5235_GPIO_PDDR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100012))) -#define MCF5235_GPIO_PDDR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100013))) -#define MCF5235_GPIO_PDDR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100014))) -#define MCF5235_GPIO_PDDR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100015))) -#define MCF5235_GPIO_PDDR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100016))) -#define MCF5235_GPIO_PDDR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100017))) -#define MCF5235_GPIO_PDDR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100018))) -#define MCF5235_GPIO_PDDR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100019))) -#define MCF5235_GPIO_PDDR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10001A))) -#define MCF5235_GPIO_PDDR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10001B))) -#define MCF5235_GPIO_PDDR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10001C))) -#define MCF5235_GPIO_PPDSDR_ADDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100020))) -#define MCF5235_GPIO_PPDSDR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100021))) -#define MCF5235_GPIO_PPDSDR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100022))) -#define MCF5235_GPIO_PPDSDR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100023))) -#define MCF5235_GPIO_PPDSDR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100024))) -#define MCF5235_GPIO_PPDSDR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100027))) -#define MCF5235_GPIO_PPDSDR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100025))) -#define MCF5235_GPIO_PPDSDR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100026))) -#define MCF5235_GPIO_PPDSDR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100028))) -#define MCF5235_GPIO_PPDSDR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100029))) -#define MCF5235_GPIO_PPDSDR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10002A))) -#define MCF5235_GPIO_PPDSDR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10002B))) -#define MCF5235_GPIO_PPDSDR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10002C))) -#define MCF5235_GPIO_PCLRR_ADDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100030))) -#define MCF5235_GPIO_PCLRR_DATAH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100031))) -#define MCF5235_GPIO_PCLRR_DATAL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100032))) -#define MCF5235_GPIO_PCLRR_BUSCTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100033))) -#define MCF5235_GPIO_PCLRR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100034))) -#define MCF5235_GPIO_PCLRR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100035))) -#define MCF5235_GPIO_PCLRR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100036))) -#define MCF5235_GPIO_PCLRR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100037))) -#define MCF5235_GPIO_PCLRR_UARTH (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100038))) -#define MCF5235_GPIO_PCLRR_UARTL (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100039))) -#define MCF5235_GPIO_PCLRR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10003A))) -#define MCF5235_GPIO_PCLRR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10003B))) -#define MCF5235_GPIO_PCLRR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10003C))) -#define MCF5235_GPIO_PAR_AD (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100040))) -#define MCF5235_GPIO_PAR_BUSCTL (*(vuint16*)((uintptr_t)__IPSBAR + (0x100042))) -#define MCF5235_GPIO_PAR_BS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100044))) -#define MCF5235_GPIO_PAR_CS (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100045))) -#define MCF5235_GPIO_PAR_SDRAM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100046))) -#define MCF5235_GPIO_PAR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100047))) -#define MCF5235_GPIO_UART (*(vuint16*)((uintptr_t)__IPSBAR + (0x100048))) -#define MCF5235_GPIO_PAR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10004A))) -#define MCF5235_GPIO_PAR_TIMER (*(vuint16*)((uintptr_t)__IPSBAR + (0x10004C))) -#define MCF5235_GPIO_PAR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x10004E))) -#define MCF5235_GPIO_DSCR_EIM (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100050))) -#define MCF5235_GPIO_DSCR_ETPU (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100051))) -#define MCF5235_GPIO_DSCR_FECI2C (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100052))) -#define MCF5235_GPIO_DSCR_UART (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100053))) -#define MCF5235_GPIO_DSCR_QSPI (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100054))) -#define MCF5235_GPIO_DSCR_TIMER (*(vuint8 *)((uintptr_t)__IPSBAR + (0x100055))) - -/* Bit definitions and macros for MCF5235_GPIO_PODR_ADDR */ -#define MCF5235_GPIO_PODR_ADDR_PODR_ADDR5 (0x20) -#define MCF5235_GPIO_PODR_ADDR_PODR_ADDR6 (0x40) -#define MCF5235_GPIO_PODR_ADDR_PODR_ADDR7 (0x80) -#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH0 (0x01) -#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH1 (0x02) -#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH2 (0x04) -#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH3 (0x08) -#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH4 (0x10) -#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH5 (0x20) -#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH6 (0x40) -#define MCF5235_GPIO_PODR_DATAH_PODR_DATAH7 (0x80) -#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL0 (0x01) -#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL1 (0x02) -#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL2 (0x04) -#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL3 (0x08) -#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL4 (0x10) -#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL5 (0x20) -#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL6 (0x40) -#define MCF5235_GPIO_PODR_DATAL_PODR_DATAL7 (0x80) -#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01) -#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) -#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) -#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) -#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL4 (0x10) -#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL5 (0x20) -#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL6 (0x40) -#define MCF5235_GPIO_PODR_BUSCTL_PODR_BUSCTL7 (0x80) -#define MCF5235_GPIO_PODR_BS_PODR_BS0 (0x01) -#define MCF5235_GPIO_PODR_BS_PODR_BS1 (0x02) -#define MCF5235_GPIO_PODR_BS_PODR_BS2 (0x04) -#define MCF5235_GPIO_PODR_BS_PODR_BS3 (0x08) -#define MCF5235_GPIO_PODR_CS_PODR_CS1 (0x02) -#define MCF5235_GPIO_PODR_CS_PODR_CS2 (0x04) -#define MCF5235_GPIO_PODR_CS_PODR_CS3 (0x08) -#define MCF5235_GPIO_PODR_CS_PODR_CS4 (0x10) -#define MCF5235_GPIO_PODR_CS_PODR_CS5 (0x20) -#define MCF5235_GPIO_PODR_CS_PODR_CS6 (0x40) -#define MCF5235_GPIO_PODR_CS_PODR_CS7 (0x80) -#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM0 (0x01) -#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM1 (0x02) -#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM2 (0x04) -#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM3 (0x08) -#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM4 (0x10) -#define MCF5235_GPIO_PODR_SDRAM_PODR_SDRAM5 (0x20) -#define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) -#define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) -#define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) -#define MCF5235_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) -#define MCF5235_GPIO_PODR_UARTH_PODR_UARTH0 (0x01) -#define MCF5235_GPIO_PODR_UARTH_PODR_UARTH1 (0x02) -#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL0 (0x01) -#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL1 (0x02) -#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL2 (0x04) -#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL3 (0x08) -#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL4 (0x10) -#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL5 (0x20) -#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL6 (0x40) -#define MCF5235_GPIO_PODR_UARTL_PODR_UARTL7 (0x80) -#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) -#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) -#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) -#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) -#define MCF5235_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) -#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) -#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) -#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) -#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) -#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER4 (0x10) -#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER5 (0x20) -#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER6 (0x40) -#define MCF5235_GPIO_PODR_TIMER_PODR_TIMER7 (0x80) -#define MCF5235_GPIO_PODR_ETPU_PODR_ETPU0 (0x01) -#define MCF5235_GPIO_PODR_ETPU_PODR_ETPU1 (0x02) -#define MCF5235_GPIO_PODR_ETPU_PODR_ETPU2 (0x04) -#define MCF5235_GPIO_PDDR_APDDR_PDDR_APDDR5 (0x20) -#define MCF5235_GPIO_PDDR_APDDR_PDDR_APDDR6 (0x40) -#define MCF5235_GPIO_PDDR_APDDR_PDDR_APDDR7 (0x80) -#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH0 (0x01) -#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH1 (0x02) -#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH2 (0x04) -#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH3 (0x08) -#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH4 (0x10) -#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH5 (0x20) -#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH6 (0x40) -#define MCF5235_GPIO_PDDR_DATAH_PDDR_DATAH7 (0x80) -#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL0 (0x01) -#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL1 (0x02) -#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL2 (0x04) -#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL3 (0x08) -#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL4 (0x10) -#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL5 (0x20) -#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL6 (0x40) -#define MCF5235_GPIO_PDDR_DATAL_PDDR_DATAL7 (0x80) -#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01) -#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) -#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) -#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) -#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4 (0x10) -#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5 (0x20) -#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6 (0x40) -#define MCF5235_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7 (0x80) -#define MCF5235_GPIO_PDDR_BS_PDDR_BS0 (0x01) -#define MCF5235_GPIO_PDDR_BS_PDDR_BS3(x) (((x)&0x07)<<1) -#define MCF5235_GPIO_PDDR_CS_PDDR_CS1 (0x02) -#define MCF5235_GPIO_PDDR_CS_PDDR_CS2 (0x04) -#define MCF5235_GPIO_PDDR_CS_PDDR_CS3 (0x08) -#define MCF5235_GPIO_PDDR_CS_PDDR_CS4 (0x10) -#define MCF5235_GPIO_PDDR_CS_PDDR_CS5 (0x20) -#define MCF5235_GPIO_PDDR_CS_PDDR_CS6 (0x40) -#define MCF5235_GPIO_PDDR_CS_PDDR_CS7 (0x80) -#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM0 (0x01) -#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM1 (0x02) -#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM2 (0x04) -#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM3 (0x08) -#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM4 (0x10) -#define MCF5235_GPIO_PDDR_SDRAM_PDDR_SDRAM5 (0x20) -#define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) -#define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) -#define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) -#define MCF5235_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) -#define MCF5235_GPIO_PDDR_UARTH_PDDR_UARTH0 (0x01) -#define MCF5235_GPIO_PDDR_UARTH_PDDR_UARTH1 (0x02) -#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL0 (0x01) -#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL1 (0x02) -#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL2 (0x04) -#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL3 (0x08) -#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL4 (0x10) -#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL5 (0x20) -#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL6 (0x40) -#define MCF5235_GPIO_PDDR_UARTL_PDDR_UARTL7 (0x80) -#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) -#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) -#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) -#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) -#define MCF5235_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) -#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) -#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) -#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) -#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) -#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER4 (0x10) -#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER5 (0x20) -#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER6 (0x40) -#define MCF5235_GPIO_PDDR_TIMER_PDDR_TIMER7 (0x80) -#define MCF5235_GPIO_PDDR_ETPU_PDDR_ETPU0 (0x01) -#define MCF5235_GPIO_PDDR_ETPU_PDDR_ETPU1 (0x02) -#define MCF5235_GPIO_PDDR_ETPU_PDDR_ETPU2 (0x04) -#define MCF5235_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5 (0x20) -#define MCF5235_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6 (0x40) -#define MCF5235_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7 (0x80) -#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0 (0x01) -#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1 (0x02) -#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2 (0x04) -#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3 (0x08) -#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4 (0x10) -#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5 (0x20) -#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6 (0x40) -#define MCF5235_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7 (0x80) -#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0 (0x01) -#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1 (0x02) -#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2 (0x04) -#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3 (0x08) -#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4 (0x10) -#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5 (0x20) -#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6 (0x40) -#define MCF5235_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7 (0x80) -#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01) -#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) -#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) -#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) -#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4 (0x10) -#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5 (0x20) -#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6 (0x40) -#define MCF5235_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7 (0x80) -#define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS0 (0x01) -#define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS1 (0x02) -#define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS2 (0x04) -#define MCF5235_GPIO_PPDSDR_BS_PPDSDR_BS3 (0x08) -#define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) -#define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) -#define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) -#define MCF5235_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) -#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) -#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) -#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) -#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) -#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) -#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS6 (0x40) -#define MCF5235_GPIO_PPDSDR_CS_PPDSDR_CS7 (0x80) -#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0 (0x01) -#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1 (0x02) -#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2 (0x04) -#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3 (0x08) -#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4 (0x10) -#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5 (0x20) -#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6 (0x40) -#define MCF5235_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7 (0x80) -#define MCF5235_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0 (0x01) -#define MCF5235_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1 (0x02) -#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0 (0x01) -#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1 (0x02) -#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2 (0x04) -#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3 (0x08) -#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4 (0x10) -#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5 (0x20) -#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6 (0x40) -#define MCF5235_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7 (0x80) -#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) -#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) -#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) -#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) -#define MCF5235_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) -#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) -#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) -#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) -#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) -#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4 (0x10) -#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5 (0x20) -#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6 (0x40) -#define MCF5235_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7 (0x80) -#define MCF5235_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0 (0x01) -#define MCF5235_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1 (0x02) -#define MCF5235_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2 (0x04) -#define MCF5235_GPIO_PCLRR_ADDR_PCLRR_ADDR5 (0x20) -#define MCF5235_GPIO_PCLRR_ADDR_PCLRR_ADDR6 (0x40) -#define MCF5235_GPIO_PCLRR_ADDR_PCLRR_ADDR7 (0x80) -#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH0 (0x01) -#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH1 (0x02) -#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH2 (0x04) -#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH3 (0x08) -#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH4 (0x10) -#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH5 (0x20) -#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH6 (0x40) -#define MCF5235_GPIO_PCLRR_DATAH_PCLRR_DATAH7 (0x80) -#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL0 (0x01) -#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL1 (0x02) -#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL2 (0x04) -#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL3 (0x08) -#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL4 (0x10) -#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL5 (0x20) -#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL6 (0x40) -#define MCF5235_GPIO_PCLRR_DATAL_PCLRR_DATAL7 (0x80) -#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01) -#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) -#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) -#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) -#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4 (0x10) -#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5 (0x20) -#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6 (0x40) -#define MCF5235_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7 (0x80) -#define MCF5235_GPIO_PCLRR_BS_PCLRR_BS0 (0x01) -#define MCF5235_GPIO_PCLRR_BS_PCLRR_BS1 (0x02) -#define MCF5235_GPIO_PCLRR_BS_PCLRR_BS2 (0x04) -#define MCF5235_GPIO_PCLRR_BS_PCLRR_BS3 (0x08) -#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) -#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) -#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) -#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) -#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) -#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS6 (0x40) -#define MCF5235_GPIO_PCLRR_CS_PCLRR_CS7 (0x80)*/ -#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0 (0x01) -#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1 (0x02) -#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2 (0x04) -#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3 (0x08) -#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4 (0x10) -#define MCF5235_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5 (0x20) -#define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) -#define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) -#define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) -#define MCF5235_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) -#define MCF5235_GPIO_PCLRR_UARTH_PCLRR_UARTH0 (0x01) -#define MCF5235_GPIO_PCLRR_UARTH_PCLRR_UARTH1 (0x02) -#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL0 (0x01) -#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL1 (0x02) -#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL2 (0x04) -#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL3 (0x08) -#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL4 (0x10) -#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL5 (0x20) -#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL6 (0x40) -#define MCF5235_GPIO_PCLRR_UARTL_PCLRR_UARTL7 (0x80) -#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) -#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) -#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) -#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) -#define MCF5235_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) -#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) -#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) -#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) -#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) -#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER4 (0x10) -#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER5 (0x20) -#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER6 (0x40) -#define MCF5235_GPIO_PCLRR_TIMER_PCLRR_TIMER7 (0x80) -#define MCF5235_GPIO_PCLRR_ETPU_PCLRR_ETPU0 (0x01) -#define MCF5235_GPIO_PCLRR_ETPU_PCLRR_ETPU1 (0x02) -#define MCF5235_GPIO_PCLRR_ETPU_PCLRR_ETPU2 (0x04) -#define MCF5235_GPIO_PAR_AD_PAR_DATAL (0x01) -#define MCF5235_GPIO_PAR_AD_PAR_ADDR21 (0x20) -#define MCF5235_GPIO_PAR_AD_PAR_ADDR22 (0x40) -#define MCF5235_GPIO_PAR_AD_PAR_ADDR23 (0x80) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP(x) (((x)&0x0003)<<0) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x0003)<<2) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TSIZ0 (0x0010) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TSIZ1 (0x0040) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_RWB (0x0100) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA(x) (((x)&0x0003)<<10) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TA (0x1000) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_OE (0x4000) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA_GPIO (0x0000) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA_DMA (0x0800) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TEA_TEA (0x0C00) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x0000) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TS_DMA (0x0080) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TS_TS (0x00C0) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP_GPIO (0x0000) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP_DMA (0x0002) -#define MCF5235_GPIO_PAR_BUSCTL_PAR_TIP_TEA (0x0003) -#define MCF5235_GPIO_PAR_BS_PAR_BS0 (0x01) -#define MCF5235_GPIO_PAR_BS_PAR_BS1 (0x02) -#define MCF5235_GPIO_PAR_BS_PAR_BS2 (0x04) -#define MCF5235_GPIO_PAR_BS_PAR_BS3 (0x08) -#define MCF5235_GPIO_PAR_CS_PAR_CS1 (0x02) -#define MCF5235_GPIO_PAR_CS_PAR_CS2 (0x04) -#define MCF5235_GPIO_PAR_CS_PAR_CS3 (0x08) -#define MCF5235_GPIO_PAR_CS_PAR_CS4 (0x10) -#define MCF5235_GPIO_PAR_CS_PAR_CS5 (0x20) -#define MCF5235_GPIO_PAR_CS_PAR_CS6 (0x40) -#define MCF5235_GPIO_PAR_CS_PAR_CS7 (0x80) -#define MCF5235_GPIO_PAR_SDRAM_PAR_SDCS0 (0x01) -#define MCF5235_GPIO_PAR_SDRAM_PAR_SDCS1 (0x02) -#define MCF5235_GPIO_PAR_SDRAM_PAR_SCKE (0x04) -#define MCF5235_GPIO_PAR_SDRAM_PAR_SRAS (0x08) -#define MCF5235_GPIO_PAR_SDRAM_PAR_SCAS (0x10) -#define MCF5235_GPIO_PAR_SDRAM_PAR_SDWE (0x20) -#define MCF5235_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) -#define MCF5235_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) -#define MCF5235_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) -#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO(x) (((x)&0x03)<<4) -#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC(x) (((x)&0x03)<<6) -#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_GPIO (0x00) -#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_UART2 (0x40) -#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_I2C (0x80) -#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDC_FEC (0xC0) -#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO (0x00) -#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_UART2 (0x10) -#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_I2C (0x20) -#define MCF5235_GPIO_PAR_FECI2C_PAR_EMDIO_FEC (0x30) -#define MCF5235_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) -#define MCF5235_GPIO_PAR_FECI2C_PAR_SCL_FLEX (0x08) -#define MCF5235_GPIO_PAR_FECI2C_PAR_SCL_I2C (0x0C) -#define MCF5235_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) -#define MCF5235_GPIO_PAR_FECI2C_PAR_SDA_FLEX (0x02) -#define MCF5235_GPIO_PAR_FECI2C_PAR_SDA_I2C (0x03) -#define MCF5235_GPIO_PAR_UART_PAR_U0RTS (0x0001) -#define MCF5235_GPIO_PAR_UART_PAR_U0CTS (0x0002) -#define MCF5235_GPIO_PAR_UART_PAR_U0TXD (0x0004) -#define MCF5235_GPIO_PAR_UART_PAR_U0RXD (0x0008) -#define MCF5235_GPIO_PAR_UART_PAR_U1RTS(x) (((x)&0x0003)<<4) -#define MCF5235_GPIO_PAR_UART_PAR_U1CTS(x) (((x)&0x0003)<<6) -#define MCF5235_GPIO_PAR_UART_PAR_U1TXD(x) (((x)&0x0003)<<8) -#define MCF5235_GPIO_PAR_UART_PAR_U1RXD(x) (((x)&0x0003)<<10) -#define MCF5235_GPIO_PAR_UART_PAR_U2TXD (0x1000) -#define MCF5235_GPIO_PAR_UART_PAR_U2RXD (0x2000) -#define MCF5235_GPIO_PAR_UART_PAR_CAN1EN (0x4000) -#define MCF5235_GPIO_PAR_UART_PAR_DREQ2 (0x8000) -#define MCF5235_GPIO_PAR_UART_PAR_U1RXD_GPIO (0x0000) -#define MCF5235_GPIO_PAR_UART_PAR_U1RXD_FLEX (0x0800) -#define MCF5235_GPIO_PAR_UART_PAR_U1RXD_UART1 (0x0C00) -#define MCF5235_GPIO_PAR_UART_PAR_U1TXD_GPIO (0x0000) -#define MCF5235_GPIO_PAR_UART_PAR_U1TXD_FLEX (0x0200) -#define MCF5235_GPIO_PAR_UART_PAR_U1TXD_UART1 (0x0300) -#define MCF5235_GPIO_PAR_UART_PAR_U1CTS_GPIO (0x0000) -#define MCF5235_GPIO_PAR_UART_PAR_U1CTS_UART2 (0x0080) -#define MCF5235_GPIO_PAR_UART_PAR_U1CTS_UART1 (0x00C0) -#define MCF5235_GPIO_PAR_UART_PAR_U1RTS_GPIO (0x0000) -#define MCF5235_GPIO_PAR_UART_PAR_U1RTS_UART2 (0x0020) -#define MCF5235_GPIO_PAR_UART_PAR_U1RTS_UART1 (0x0030) -#define MCF5235_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x03)<<0) -#define MCF5235_GPIO_PAR_QSPI_PAR_DOUT (0x04) -#define MCF5235_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x03)<<3) -#define MCF5235_GPIO_PAR_QSPI_PAR_PCS0 (0x20) -#define MCF5235_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x03)<<6) -#define MCF5235_GPIO_PAR_QSPI_PAR_PCS1_GPIO (0x00) -#define MCF5235_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC (0x80) -#define MCF5235_GPIO_PAR_QSPI_PAR_PCS1_QSPI (0xC0) -#define MCF5235_GPIO_PAR_QSPI_PAR_DIN_GPIO (0x00) -#define MCF5235_GPIO_PAR_QSPI_PAR_DIN_I2C (0x10) -#define MCF5235_GPIO_PAR_QSPI_PAR_DIN_QSPI (0x1C) -#define MCF5235_GPIO_PAR_QSPI_PAR_SCK_GPIO (0x00) -#define MCF5235_GPIO_PAR_QSPI_PAR_SCK_I2C (0x02) -#define MCF5235_GPIO_PAR_QSPI_PAR_SCK_QSPI (0x03) -#define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT(x) (((x)&0x0003)<<0) -#define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT(x) (((x)&0x0003)<<2) -#define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT(x) (((x)&0x0003)<<4) -#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT(x) (((x)&0x0003)<<6) -#define MCF5235_GPIO_PAR_TIMER_PAR_T0IN(x) (((x)&0x0003)<<8) -#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN(x) (((x)&0x0003)<<10) -#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN(x) (((x)&0x0003)<<12) -#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN(x) (((x)&0x0003)<<14) -#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_GPIO (0x0000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_QSPI (0x4000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_UART2 (0x8000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T3IN_T3IN (0xC000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_GPIO (0x0000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_T2OUT (0x1000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_DMA (0x2000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T2IN_T2IN (0x3000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_GPIO (0x0000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_T1OUT (0x0400) -#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_DMA (0x0800) -#define MCF5235_GPIO_PAR_TIMER_PAR_T1IN_T1IN (0x0C00) -#define MCF5235_GPIO_PAR_TIMER_PAR_T0IN_GPIO (0x0000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T0IN_DMA (0x0200) -#define MCF5235_GPIO_PAR_TIMER_PAR_T0IN_T0IN (0x0300) -#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_GPIO (0x0000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_QSPI (0x0040) -#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_UART2 (0x0080) -#define MCF5235_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT (0x00C0) -#define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT_GPIO (0x0000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT_DMA (0x0020) -#define MCF5235_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT (0x0030) -#define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT_GPIO (0x0000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT_DMA (0x0008) -#define MCF5235_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT (0x000C) -#define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT_GPIO (0x0000) -#define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT_DMA (0x0002) -#define MCF5235_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT (0x0003) -#define MCF5235_GPIO_PAR_ETPU_PAR_LTPU_ODIS (0x01) -#define MCF5235_GPIO_PAR_ETPU_PAR_UTPU_ODIS (0x02) -#define MCF5235_GPIO_PAR_ETPU_PAR_TCRCLK (0x04) -#define MCF5235_GPIO_DSCR_EIM_DSCR_EIM0 (0x01) -#define MCF5235_GPIO_DSCR_EIM_DSCR_EIM1 (0x10) -#define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_7_0 (0x01) -#define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_15_8 (0x04) -#define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_23_16 (0x10) -#define MCF5235_GPIO_DSCR_ETPU_DSCR_ETPU_31_24 (0x40) -#define MCF5235_GPIO_DSCR_FECI2C_DSCR_I2C (0x01) -#define MCF5235_GPIO_DSCR_FECI2C_DSCR_FEC (0x10) -#define MCF5235_GPIO_DSCR_UART_DSCR_UART0 (0x01) -#define MCF5235_GPIO_DSCR_UART_DSCR_UART1 (0x04) -#define MCF5235_GPIO_DSCR_UART_DSCR_UART2 (0x10) -#define MCF5235_GPIO_DSCR_UART_DSCR_IRQ (0x40) -#define MCF5235_GPIO_DSCR_QSPI_DSCR_QSPI (0x01)*/ -#define MCF5235_GPIO_DSCR_TIMER_DSCR_TIMER (0x01) - -/********************************************************************* -* -* I2C Module (I2C) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_I2C_I2AR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000300))) -#define MCF5235_I2C_I2FDR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000304))) -#define MCF5235_I2C_I2CR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000308))) -#define MCF5235_I2C_I2SR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x00030C))) -#define MCF5235_I2C_I2DR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000310))) -#define MCF5235_I2C_I2ICR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000320))) - -/* Bit definitions and macros for MCF5235_I2C_I2AR */ -#define MCF5235_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) -#define MCF5235_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) -#define MCF5235_I2C_I2CR_RSTA (0x04) -#define MCF5235_I2C_I2CR_TXAK (0x08) -#define MCF5235_I2C_I2CR_MTX (0x10) -#define MCF5235_I2C_I2CR_MSTA (0x20) -#define MCF5235_I2C_I2CR_IIEN (0x40) -#define MCF5235_I2C_I2CR_IEN (0x80) -#define MCF5235_I2C_I2SR_RXAK (0x01) -#define MCF5235_I2C_I2SR_IIF (0x02) -#define MCF5235_I2C_I2SR_SRW (0x04) -#define MCF5235_I2C_I2SR_IAL (0x10) -#define MCF5235_I2C_I2SR_IBB (0x20) -#define MCF5235_I2C_I2SR_IAAS (0x40) -#define MCF5235_I2C_I2SR_ICF (0x80) -#define MCF5235_I2C_I2ICR_IE (0x01) -#define MCF5235_I2C_I2ICR_RE (0x02) -#define MCF5235_I2C_I2ICR_TE (0x04) -#define MCF5235_I2C_I2ICR_BNBE (0x08) - -/********************************************************************* -* -* Interrupt Controller 0 (INTC0) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_INTC0_IPRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C00))) -#define MCF5235_INTC0_IPRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C04))) -#define MCF5235_INTC0_IMRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C08))) -#define MCF5235_INTC0_IMRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C0C))) -#define MCF5235_INTC0_INTFRCH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C10))) -#define MCF5235_INTC0_INTFRCL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000C14))) -#define MCF5235_INTC0_IRLR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C18))) -#define MCF5235_INTC0_IACKLPR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C19))) -#define MCF5235_INTC0_ICR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C40))) -#define MCF5235_INTC0_ICR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C41))) -#define MCF5235_INTC0_ICR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C42))) -#define MCF5235_INTC0_ICR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C43))) -#define MCF5235_INTC0_ICR4 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C44))) -#define MCF5235_INTC0_ICR5 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C45))) -#define MCF5235_INTC0_ICR6 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C46))) -#define MCF5235_INTC0_ICR7 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C47))) -#define MCF5235_INTC0_ICR8 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C48))) -#define MCF5235_INTC0_ICR9 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C49))) -#define MCF5235_INTC0_ICR10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4A))) -#define MCF5235_INTC0_ICR11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4B))) -#define MCF5235_INTC0_ICR12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4C))) -#define MCF5235_INTC0_ICR13 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4D))) -#define MCF5235_INTC0_ICR14 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4E))) -#define MCF5235_INTC0_ICR15 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C4F))) -#define MCF5235_INTC0_ICR16 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C50))) -#define MCF5235_INTC0_ICR17 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C51))) -#define MCF5235_INTC0_ICR18 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C52))) -#define MCF5235_INTC0_ICR19 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C53))) -#define MCF5235_INTC0_ICR20 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C54))) -#define MCF5235_INTC0_ICR21 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C55))) -#define MCF5235_INTC0_ICR22 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C56))) -#define MCF5235_INTC0_ICR23 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C57))) -#define MCF5235_INTC0_ICR24 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C58))) -#define MCF5235_INTC0_ICR25 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C59))) -#define MCF5235_INTC0_ICR26 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5A))) -#define MCF5235_INTC0_ICR27 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5B))) -#define MCF5235_INTC0_ICR28 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5C))) -#define MCF5235_INTC0_ICR29 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5D))) -#define MCF5235_INTC0_ICR30 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5E))) -#define MCF5235_INTC0_ICR31 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C5F))) -#define MCF5235_INTC0_ICR32 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C60))) -#define MCF5235_INTC0_ICR33 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C61))) -#define MCF5235_INTC0_ICR34 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C62))) -#define MCF5235_INTC0_ICR35 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C63))) -#define MCF5235_INTC0_ICR36 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C64))) -#define MCF5235_INTC0_ICR37 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C65))) -#define MCF5235_INTC0_ICR38 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C66))) -#define MCF5235_INTC0_ICR39 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C67))) -#define MCF5235_INTC0_ICR40 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C68))) -#define MCF5235_INTC0_ICR41 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C69))) -#define MCF5235_INTC0_ICR42 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6A))) -#define MCF5235_INTC0_ICR43 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6B))) -#define MCF5235_INTC0_ICR44 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6C))) -#define MCF5235_INTC0_ICR45 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6D))) -#define MCF5235_INTC0_ICR46 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6E))) -#define MCF5235_INTC0_ICR47 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C6F))) -#define MCF5235_INTC0_ICR48 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C70))) -#define MCF5235_INTC0_ICR49 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C71))) -#define MCF5235_INTC0_ICR50 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C72))) -#define MCF5235_INTC0_ICR51 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C73))) -#define MCF5235_INTC0_ICR52 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C74))) -#define MCF5235_INTC0_ICR53 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C75))) -#define MCF5235_INTC0_ICR54 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C76))) -#define MCF5235_INTC0_ICR55 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C77))) -#define MCF5235_INTC0_ICR56 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C78))) -#define MCF5235_INTC0_ICR57 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C79))) -#define MCF5235_INTC0_ICR58 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7A))) -#define MCF5235_INTC0_ICR59 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7B))) -#define MCF5235_INTC0_ICR60 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7C))) -#define MCF5235_INTC0_ICR61 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7D))) -#define MCF5235_INTC0_ICR62 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7E))) -#define MCF5235_INTC0_ICR63 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C7F))) -#define MCF5235_INTC0_ICRn(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000C40+((x)*0x001)))) -#define MCF5235_INTC0_SWIACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE0))) -#define MCF5235_INTC0_L1IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE4))) -#define MCF5235_INTC0_L2IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE8))) -#define MCF5235_INTC0_L3IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CEC))) -#define MCF5235_INTC0_L4IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CF0))) -#define MCF5235_INTC0_L5IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CF4))) -#define MCF5235_INTC0_L6IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CF8))) -#define MCF5235_INTC0_L7IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CFC))) -#define MCF5235_INTC0_LnIACK(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000CE4+((x)*0x004)))) -#define MCF5235_INTC1_IPRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D00))) -#define MCF5235_INTC1_IPRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D04))) -#define MCF5235_INTC1_IMRH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D08))) -#define MCF5235_INTC1_IMRL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D0C))) -#define MCF5235_INTC1_INTFRCH (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D10))) -#define MCF5235_INTC1_INTFRCL (*(vuint32*)((uintptr_t)__IPSBAR + (0x000D14))) -#define MCF5235_INTC1_IRLR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D18))) -#define MCF5235_INTC1_IACKLPR (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D19))) -#define MCF5235_INTC1_ICR0 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D40))) -#define MCF5235_INTC1_ICR1 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D41))) -#define MCF5235_INTC1_ICR2 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D42))) -#define MCF5235_INTC1_ICR3 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D43))) -#define MCF5235_INTC1_ICR4 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D44))) -#define MCF5235_INTC1_ICR5 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D45))) -#define MCF5235_INTC1_ICR6 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D46))) -#define MCF5235_INTC1_ICR7 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D47))) -#define MCF5235_INTC1_ICR8 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D48))) -#define MCF5235_INTC1_ICR9 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D49))) -#define MCF5235_INTC1_ICR10 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4A))) -#define MCF5235_INTC1_ICR11 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4B))) -#define MCF5235_INTC1_ICR12 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4C))) -#define MCF5235_INTC1_ICR13 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4D))) -#define MCF5235_INTC1_ICR14 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4E))) -#define MCF5235_INTC1_ICR15 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D4F))) -#define MCF5235_INTC1_ICR16 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D50))) -#define MCF5235_INTC1_ICR17 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D51))) -#define MCF5235_INTC1_ICR18 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D52))) -#define MCF5235_INTC1_ICR19 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D53))) -#define MCF5235_INTC1_ICR20 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D54))) -#define MCF5235_INTC1_ICR21 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D55))) -#define MCF5235_INTC1_ICR22 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D56))) -#define MCF5235_INTC1_ICR23 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D57))) -#define MCF5235_INTC1_ICR24 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D58))) -#define MCF5235_INTC1_ICR25 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D59))) -#define MCF5235_INTC1_ICR26 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5A))) -#define MCF5235_INTC1_ICR27 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5B))) -#define MCF5235_INTC1_ICR28 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5C))) -#define MCF5235_INTC1_ICR29 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5D))) -#define MCF5235_INTC1_ICR30 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5E))) -#define MCF5235_INTC1_ICR31 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D5F))) -#define MCF5235_INTC1_ICR32 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D60))) -#define MCF5235_INTC1_ICR33 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D61))) -#define MCF5235_INTC1_ICR34 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D62))) -#define MCF5235_INTC1_ICR35 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D63))) -#define MCF5235_INTC1_ICR36 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D64))) -#define MCF5235_INTC1_ICR37 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D65))) -#define MCF5235_INTC1_ICR38 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D66))) -#define MCF5235_INTC1_ICR39 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D67))) -#define MCF5235_INTC1_ICR40 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D68))) -#define MCF5235_INTC1_ICR41 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D69))) -#define MCF5235_INTC1_ICR42 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6A))) -#define MCF5235_INTC1_ICR43 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6B))) -#define MCF5235_INTC1_ICR44 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6C))) -#define MCF5235_INTC1_ICR45 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6D))) -#define MCF5235_INTC1_ICR46 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6E))) -#define MCF5235_INTC1_ICR47 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D6F))) -#define MCF5235_INTC1_ICR48 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D70))) -#define MCF5235_INTC1_ICR49 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D71))) -#define MCF5235_INTC1_ICR50 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D72))) -#define MCF5235_INTC1_ICR51 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D73))) -#define MCF5235_INTC1_ICR52 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D74))) -#define MCF5235_INTC1_ICR53 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D75))) -#define MCF5235_INTC1_ICR54 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D76))) -#define MCF5235_INTC1_ICR55 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D77))) -#define MCF5235_INTC1_ICR56 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D78))) -#define MCF5235_INTC1_ICR57 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D79))) -#define MCF5235_INTC1_ICR58 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7A))) -#define MCF5235_INTC1_ICR59 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7B))) -#define MCF5235_INTC1_ICR60 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7C))) -#define MCF5235_INTC1_ICR61 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7D))) -#define MCF5235_INTC1_ICR62 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7E))) -#define MCF5235_INTC1_ICR63 (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D7F))) -#define MCF5235_INTC1_ICRn(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000D40+((x)*0x001)))) -#define MCF5235_INTC1_SWIACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE0))) -#define MCF5235_INTC1_L1IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE4))) -#define MCF5235_INTC1_L2IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE8))) -#define MCF5235_INTC1_L3IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DEC))) -#define MCF5235_INTC1_L4IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DF0))) -#define MCF5235_INTC1_L5IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DF4))) -#define MCF5235_INTC1_L6IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DF8))) -#define MCF5235_INTC1_L7IACK (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DFC))) -#define MCF5235_INTC1_LnIACK(x) (*(vuint8 *)((uintptr_t)__IPSBAR + (0x000DE4+((x)*0x004)))) - -/* Bit definitions and macros for MCF5235_INTC0_IPRH */ -#define MCF5235_INTC0_IPRH_INT32 (0x00000001) -#define MCF5235_INTC0_IPRH_INT33 (0x00000002) -#define MCF5235_INTC0_IPRH_INT34 (0x00000004) -#define MCF5235_INTC0_IPRH_INT35 (0x00000008) -#define MCF5235_INTC0_IPRH_INT36 (0x00000010) -#define MCF5235_INTC0_IPRH_INT37 (0x00000020) -#define MCF5235_INTC0_IPRH_INT38 (0x00000040) -#define MCF5235_INTC0_IPRH_INT39 (0x00000080) -#define MCF5235_INTC0_IPRH_INT40 (0x00000100) -#define MCF5235_INTC0_IPRH_INT41 (0x00000200) -#define MCF5235_INTC0_IPRH_INT42 (0x00000400) -#define MCF5235_INTC0_IPRH_INT43 (0x00000800) -#define MCF5235_INTC0_IPRH_INT44 (0x00001000) -#define MCF5235_INTC0_IPRH_INT45 (0x00002000) -#define MCF5235_INTC0_IPRH_INT46 (0x00004000) -#define MCF5235_INTC0_IPRH_INT47 (0x00008000) -#define MCF5235_INTC0_IPRH_INT48 (0x00010000) -#define MCF5235_INTC0_IPRH_INT49 (0x00020000) -#define MCF5235_INTC0_IPRH_INT50 (0x00040000) -#define MCF5235_INTC0_IPRH_INT51 (0x00080000) -#define MCF5235_INTC0_IPRH_INT52 (0x00100000) -#define MCF5235_INTC0_IPRH_INT53 (0x00200000) -#define MCF5235_INTC0_IPRH_INT54 (0x00400000) -#define MCF5235_INTC0_IPRH_INT55 (0x00800000) -#define MCF5235_INTC0_IPRH_INT56 (0x01000000) -#define MCF5235_INTC0_IPRH_INT57 (0x02000000) -#define MCF5235_INTC0_IPRH_INT58 (0x04000000) -#define MCF5235_INTC0_IPRH_INT59 (0x08000000) -#define MCF5235_INTC0_IPRH_INT60 (0x10000000) -#define MCF5235_INTC0_IPRH_INT61 (0x20000000) -#define MCF5235_INTC0_IPRH_INT62 (0x40000000) -#define MCF5235_INTC0_IPRH_INT63 (0x80000000) -#define MCF5235_INTC0_IPRL_INT1 (0x00000002) -#define MCF5235_INTC0_IPRL_INT2 (0x00000004) -#define MCF5235_INTC0_IPRL_INT3 (0x00000008) -#define MCF5235_INTC0_IPRL_INT4 (0x00000010) -#define MCF5235_INTC0_IPRL_INT5 (0x00000020) -#define MCF5235_INTC0_IPRL_INT6 (0x00000040) -#define MCF5235_INTC0_IPRL_INT7 (0x00000080) -#define MCF5235_INTC0_IPRL_INT8 (0x00000100) -#define MCF5235_INTC0_IPRL_INT9 (0x00000200) -#define MCF5235_INTC0_IPRL_INT10 (0x00000400) -#define MCF5235_INTC0_IPRL_INT11 (0x00000800) -#define MCF5235_INTC0_IPRL_INT12 (0x00001000) -#define MCF5235_INTC0_IPRL_INT13 (0x00002000) -#define MCF5235_INTC0_IPRL_INT14 (0x00004000) -#define MCF5235_INTC0_IPRL_INT15 (0x00008000) -#define MCF5235_INTC0_IPRL_INT16 (0x00010000) -#define MCF5235_INTC0_IPRL_INT17 (0x00020000) -#define MCF5235_INTC0_IPRL_INT18 (0x00040000) -#define MCF5235_INTC0_IPRL_INT19 (0x00080000) -#define MCF5235_INTC0_IPRL_INT20 (0x00100000) -#define MCF5235_INTC0_IPRL_INT21 (0x00200000) -#define MCF5235_INTC0_IPRL_INT22 (0x00400000) -#define MCF5235_INTC0_IPRL_INT23 (0x00800000) -#define MCF5235_INTC0_IPRL_INT24 (0x01000000) -#define MCF5235_INTC0_IPRL_INT25 (0x02000000) -#define MCF5235_INTC0_IPRL_INT26 (0x04000000) -#define MCF5235_INTC0_IPRL_INT27 (0x08000000) -#define MCF5235_INTC0_IPRL_INT28 (0x10000000) -#define MCF5235_INTC0_IPRL_INT29 (0x20000000) -#define MCF5235_INTC0_IPRL_INT30 (0x40000000) -#define MCF5235_INTC0_IPRL_INT31 (0x80000000) -#define MCF5235_INTC0_IMRH_INT32 (0x00000001) -#define MCF5235_INTC0_IMRH_INT33 (0x00000002) -#define MCF5235_INTC0_IMRH_INT34 (0x00000004) -#define MCF5235_INTC0_IMRH_INT35 (0x00000008) -#define MCF5235_INTC0_IMRH_INT36 (0x00000010) -#define MCF5235_INTC0_IMRH_INT37 (0x00000020) -#define MCF5235_INTC0_IMRH_INT38 (0x00000040) -#define MCF5235_INTC0_IMRH_INT39 (0x00000080) -#define MCF5235_INTC0_IMRH_INT40 (0x00000100) -#define MCF5235_INTC0_IMRH_INT41 (0x00000200) -#define MCF5235_INTC0_IMRH_INT42 (0x00000400) -#define MCF5235_INTC0_IMRH_INT43 (0x00000800) -#define MCF5235_INTC0_IMRH_INT44 (0x00001000) -#define MCF5235_INTC0_IMRH_INT45 (0x00002000) -#define MCF5235_INTC0_IMRH_INT46 (0x00004000) -#define MCF5235_INTC0_IMRH_INT47 (0x00008000) -#define MCF5235_INTC0_IMRH_INT48 (0x00010000) -#define MCF5235_INTC0_IMRH_INT49 (0x00020000) -#define MCF5235_INTC0_IMRH_INT50 (0x00040000) -#define MCF5235_INTC0_IMRH_INT51 (0x00080000) -#define MCF5235_INTC0_IMRH_INT52 (0x00100000) -#define MCF5235_INTC0_IMRH_INT53 (0x00200000) -#define MCF5235_INTC0_IMRH_INT54 (0x00400000) -#define MCF5235_INTC0_IMRH_INT55 (0x00800000) -#define MCF5235_INTC0_IMRH_INT56 (0x01000000) -#define MCF5235_INTC0_IMRH_INT57 (0x02000000) -#define MCF5235_INTC0_IMRH_INT58 (0x04000000) -#define MCF5235_INTC0_IMRH_INT59 (0x08000000) -#define MCF5235_INTC0_IMRH_INT60 (0x10000000) -#define MCF5235_INTC0_IMRH_INT61 (0x20000000) -#define MCF5235_INTC0_IMRH_INT62 (0x40000000) -#define MCF5235_INTC0_IMRH_INT63 (0x80000000) -#define MCF5235_INTC0_IMRL_MASKALL (0x00000001) -#define MCF5235_INTC0_IMRL_INT1 (0x00000002) -#define MCF5235_INTC0_IMRL_INT2 (0x00000004) -#define MCF5235_INTC0_IMRL_INT3 (0x00000008) -#define MCF5235_INTC0_IMRL_INT4 (0x00000010) -#define MCF5235_INTC0_IMRL_INT5 (0x00000020) -#define MCF5235_INTC0_IMRL_INT6 (0x00000040) -#define MCF5235_INTC0_IMRL_INT7 (0x00000080) -#define MCF5235_INTC0_IMRL_INT8 (0x00000100) -#define MCF5235_INTC0_IMRL_INT9 (0x00000200) -#define MCF5235_INTC0_IMRL_INT10 (0x00000400) -#define MCF5235_INTC0_IMRL_INT11 (0x00000800) -#define MCF5235_INTC0_IMRL_INT12 (0x00001000) -#define MCF5235_INTC0_IMRL_INT13 (0x00002000) -#define MCF5235_INTC0_IMRL_INT14 (0x00004000) -#define MCF5235_INTC0_IMRL_INT15 (0x00008000) -#define MCF5235_INTC0_IMRL_INT16 (0x00010000) -#define MCF5235_INTC0_IMRL_INT17 (0x00020000) -#define MCF5235_INTC0_IMRL_INT18 (0x00040000) -#define MCF5235_INTC0_IMRL_INT19 (0x00080000) -#define MCF5235_INTC0_IMRL_INT20 (0x00100000) -#define MCF5235_INTC0_IMRL_INT21 (0x00200000) -#define MCF5235_INTC0_IMRL_INT22 (0x00400000) -#define MCF5235_INTC0_IMRL_INT23 (0x00800000) -#define MCF5235_INTC0_IMRL_INT24 (0x01000000) -#define MCF5235_INTC0_IMRL_INT25 (0x02000000) -#define MCF5235_INTC0_IMRL_INT26 (0x04000000) -#define MCF5235_INTC0_IMRL_INT27 (0x08000000) -#define MCF5235_INTC0_IMRL_INT28 (0x10000000) -#define MCF5235_INTC0_IMRL_INT29 (0x20000000) -#define MCF5235_INTC0_IMRL_INT30 (0x40000000) -#define MCF5235_INTC0_IMRL_INT31 (0x80000000) -#define MCF5235_INTC0_INTFRCH_INTFRC32 (0x00000001) -#define MCF5235_INTC0_INTFRCH_INTFRC33 (0x00000002) -#define MCF5235_INTC0_INTFRCH_INTFRC34 (0x00000004) -#define MCF5235_INTC0_INTFRCH_INTFRC35 (0x00000008) -#define MCF5235_INTC0_INTFRCH_INTFRC36 (0x00000010) -#define MCF5235_INTC0_INTFRCH_INTFRC37 (0x00000020) -#define MCF5235_INTC0_INTFRCH_INTFRC38 (0x00000040) -#define MCF5235_INTC0_INTFRCH_INTFRC39 (0x00000080) -#define MCF5235_INTC0_INTFRCH_INTFRC40 (0x00000100) -#define MCF5235_INTC0_INTFRCH_INTFRC41 (0x00000200) -#define MCF5235_INTC0_INTFRCH_INTFRC42 (0x00000400) -#define MCF5235_INTC0_INTFRCH_INTFRC43 (0x00000800) -#define MCF5235_INTC0_INTFRCH_INTFRC44 (0x00001000) -#define MCF5235_INTC0_INTFRCH_INTFRC45 (0x00002000) -#define MCF5235_INTC0_INTFRCH_INTFRC46 (0x00004000) -#define MCF5235_INTC0_INTFRCH_INTFRC47 (0x00008000) -#define MCF5235_INTC0_INTFRCH_INTFRC48 (0x00010000) -#define MCF5235_INTC0_INTFRCH_INTFRC49 (0x00020000) -#define MCF5235_INTC0_INTFRCH_INTFRC50 (0x00040000) -#define MCF5235_INTC0_INTFRCH_INTFRC51 (0x00080000) -#define MCF5235_INTC0_INTFRCH_INTFRC52 (0x00100000) -#define MCF5235_INTC0_INTFRCH_INTFRC53 (0x00200000) -#define MCF5235_INTC0_INTFRCH_INTFRC54 (0x00400000) -#define MCF5235_INTC0_INTFRCH_INTFRC55 (0x00800000) -#define MCF5235_INTC0_INTFRCH_INTFRC56 (0x01000000) -#define MCF5235_INTC0_INTFRCH_INTFRC57 (0x02000000) -#define MCF5235_INTC0_INTFRCH_INTFRC58 (0x04000000) -#define MCF5235_INTC0_INTFRCH_INTFRC59 (0x08000000) -#define MCF5235_INTC0_INTFRCH_INTFRC60 (0x10000000) -#define MCF5235_INTC0_INTFRCH_INTFRC61 (0x20000000) -#define MCF5235_INTC0_INTFRCH_INTFRC62 (0x40000000) -#define MCF5235_INTC0_INTFRCH_INTFRC63 (0x80000000) -#define MCF5235_INTC0_INTFRCL_INTFRC1 (0x00000002) -#define MCF5235_INTC0_INTFRCL_INTFRC2 (0x00000004) -#define MCF5235_INTC0_INTFRCL_INTFRC3 (0x00000008) -#define MCF5235_INTC0_INTFRCL_INTFRC4 (0x00000010) -#define MCF5235_INTC0_INTFRCL_INTFRC5 (0x00000020) -#define MCF5235_INTC0_INTFRCL_INT6 (0x00000040) -#define MCF5235_INTC0_INTFRCL_INT7 (0x00000080) -#define MCF5235_INTC0_INTFRCL_INT8 (0x00000100) -#define MCF5235_INTC0_INTFRCL_INT9 (0x00000200) -#define MCF5235_INTC0_INTFRCL_INT10 (0x00000400) -#define MCF5235_INTC0_INTFRCL_INTFRC11 (0x00000800) -#define MCF5235_INTC0_INTFRCL_INTFRC12 (0x00001000) -#define MCF5235_INTC0_INTFRCL_INTFRC13 (0x00002000) -#define MCF5235_INTC0_INTFRCL_INTFRC14 (0x00004000) -#define MCF5235_INTC0_INTFRCL_INT15 (0x00008000) -#define MCF5235_INTC0_INTFRCL_INTFRC16 (0x00010000) -#define MCF5235_INTC0_INTFRCL_INTFRC17 (0x00020000) -#define MCF5235_INTC0_INTFRCL_INTFRC18 (0x00040000) -#define MCF5235_INTC0_INTFRCL_INTFRC19 (0x00080000) -#define MCF5235_INTC0_INTFRCL_INTFRC20 (0x00100000) -#define MCF5235_INTC0_INTFRCL_INTFRC21 (0x00200000) -#define MCF5235_INTC0_INTFRCL_INTFRC22 (0x00400000) -#define MCF5235_INTC0_INTFRCL_INTFRC23 (0x00800000) -#define MCF5235_INTC0_INTFRCL_INTFRC24 (0x01000000) -#define MCF5235_INTC0_INTFRCL_INTFRC25 (0x02000000) -#define MCF5235_INTC0_INTFRCL_INTFRC26 (0x04000000) -#define MCF5235_INTC0_INTFRCL_INTFRC27 (0x08000000) -#define MCF5235_INTC0_INTFRCL_INTFRC28 (0x10000000) -#define MCF5235_INTC0_INTFRCL_INTFRC29 (0x20000000) -#define MCF5235_INTC0_INTFRCL_INTFRC30 (0x40000000) -#define MCF5235_INTC0_INTFRCL_INTFRC31 (0x80000000) -#define MCF5235_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1) -#define MCF5235_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF5235_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4) -#define MCF5235_INTC_ICR_IP(x) (((x)&0x07)<<0) -#define MCF5235_INTC_ICR_IL(x) (((x)&0x07)<<3) -#define MCF5235_INTC1_IPRH_INT32 (0x00000001) -#define MCF5235_INTC1_IPRH_INT33 (0x00000002) -#define MCF5235_INTC1_IPRH_INT34 (0x00000004) -#define MCF5235_INTC1_IPRH_INT35 (0x00000008) -#define MCF5235_INTC1_IPRH_INT36 (0x00000010) -#define MCF5235_INTC1_IPRH_INT37 (0x00000020) -#define MCF5235_INTC1_IPRH_INT38 (0x00000040) -#define MCF5235_INTC1_IPRH_INT39 (0x00000080) -#define MCF5235_INTC1_IPRH_INT40 (0x00000100) -#define MCF5235_INTC1_IPRH_INT41 (0x00000200) -#define MCF5235_INTC1_IPRH_INT42 (0x00000400) -#define MCF5235_INTC1_IPRH_INT43 (0x00000800) -#define MCF5235_INTC1_IPRH_INT44 (0x00001000) -#define MCF5235_INTC1_IPRH_INT45 (0x00002000) -#define MCF5235_INTC1_IPRH_INT46 (0x00004000) -#define MCF5235_INTC1_IPRH_INT47 (0x00008000) -#define MCF5235_INTC1_IPRH_INT48 (0x00010000) -#define MCF5235_INTC1_IPRH_INT49 (0x00020000) -#define MCF5235_INTC1_IPRH_INT50 (0x00040000) -#define MCF5235_INTC1_IPRH_INT51 (0x00080000) -#define MCF5235_INTC1_IPRH_INT52 (0x00100000) -#define MCF5235_INTC1_IPRH_INT53 (0x00200000) -#define MCF5235_INTC1_IPRH_INT54 (0x00400000) -#define MCF5235_INTC1_IPRH_INT55 (0x00800000) -#define MCF5235_INTC1_IPRH_INT56 (0x01000000) -#define MCF5235_INTC1_IPRH_INT57 (0x02000000) -#define MCF5235_INTC1_IPRH_INT58 (0x04000000) -#define MCF5235_INTC1_IPRH_INT59 (0x08000000) -#define MCF5235_INTC1_IPRH_INT60 (0x10000000) -#define MCF5235_INTC1_IPRH_INT61 (0x20000000) -#define MCF5235_INTC1_IPRH_INT62 (0x40000000) -#define MCF5235_INTC1_IPRH_INT63 (0x80000000) -#define MCF5235_INTC1_IPRL_INT1 (0x00000002) -#define MCF5235_INTC1_IPRL_INT2 (0x00000004) -#define MCF5235_INTC1_IPRL_INT3 (0x00000008) -#define MCF5235_INTC1_IPRL_INT4 (0x00000010) -#define MCF5235_INTC1_IPRL_INT5 (0x00000020) -#define MCF5235_INTC1_IPRL_INT6 (0x00000040) -#define MCF5235_INTC1_IPRL_INT7 (0x00000080) -#define MCF5235_INTC1_IPRL_INT8 (0x00000100) -#define MCF5235_INTC1_IPRL_INT9 (0x00000200) -#define MCF5235_INTC1_IPRL_INT10 (0x00000400) -#define MCF5235_INTC1_IPRL_INT11 (0x00000800) -#define MCF5235_INTC1_IPRL_INT12 (0x00001000) -#define MCF5235_INTC1_IPRL_INT13 (0x00002000) -#define MCF5235_INTC1_IPRL_INT14 (0x00004000) -#define MCF5235_INTC1_IPRL_INT15 (0x00008000) -#define MCF5235_INTC1_IPRL_INT16 (0x00010000) -#define MCF5235_INTC1_IPRL_INT17 (0x00020000) -#define MCF5235_INTC1_IPRL_INT18 (0x00040000) -#define MCF5235_INTC1_IPRL_INT19 (0x00080000) -#define MCF5235_INTC1_IPRL_INT20 (0x00100000) -#define MCF5235_INTC1_IPRL_INT21 (0x00200000) -#define MCF5235_INTC1_IPRL_INT22 (0x00400000) -#define MCF5235_INTC1_IPRL_INT23 (0x00800000) -#define MCF5235_INTC1_IPRL_INT24 (0x01000000) -#define MCF5235_INTC1_IPRL_INT25 (0x02000000) -#define MCF5235_INTC1_IPRL_INT26 (0x04000000) -#define MCF5235_INTC1_IPRL_INT27 (0x08000000) -#define MCF5235_INTC1_IPRL_INT28 (0x10000000) -#define MCF5235_INTC1_IPRL_INT29 (0x20000000) -#define MCF5235_INTC1_IPRL_INT30 (0x40000000) -#define MCF5235_INTC1_IPRL_INT31 (0x80000000) -#define MCF5235_INTC1_IMRH_INT_MASK32 (0x00000001) -#define MCF5235_INTC1_IMRH_INT_MASK33 (0x00000002) -#define MCF5235_INTC1_IMRH_INT_MASK34 (0x00000004) -#define MCF5235_INTC1_IMRH_INT_MASK35 (0x00000008) -#define MCF5235_INTC1_IMRH_INT_MASK36 (0x00000010) -#define MCF5235_INTC1_IMRH_INT_MASK37 (0x00000020) -#define MCF5235_INTC1_IMRH_INT_MASK38 (0x00000040) -#define MCF5235_INTC1_IMRH_INT_MASK39 (0x00000080) -#define MCF5235_INTC1_IMRH_INT_MASK40 (0x00000100) -#define MCF5235_INTC1_IMRH_INT_MASK41 (0x00000200) -#define MCF5235_INTC1_IMRH_INT_MASK42 (0x00000400) -#define MCF5235_INTC1_IMRH_INT_MASK43 (0x00000800) -#define MCF5235_INTC1_IMRH_INT_MASK44 (0x00001000) -#define MCF5235_INTC1_IMRH_INT_MASK45 (0x00002000) -#define MCF5235_INTC1_IMRH_INT_MASK46 (0x00004000) -#define MCF5235_INTC1_IMRH_INT_MASK47 (0x00008000) -#define MCF5235_INTC1_IMRH_INT_MASK48 (0x00010000) -#define MCF5235_INTC1_IMRH_INT_MASK49 (0x00020000) -#define MCF5235_INTC1_IMRH_INT_MASK50 (0x00040000) -#define MCF5235_INTC1_IMRH_INT_MASK51 (0x00080000) -#define MCF5235_INTC1_IMRH_INT_MASK52 (0x00100000) -#define MCF5235_INTC1_IMRH_INT_MASK53 (0x00200000) -#define MCF5235_INTC1_IMRH_INT_MASK54 (0x00400000) -#define MCF5235_INTC1_IMRH_INT_MASK55 (0x00800000) -#define MCF5235_INTC1_IMRH_INT_MASK56 (0x01000000) -#define MCF5235_INTC1_IMRH_INT_MASK57 (0x02000000) -#define MCF5235_INTC1_IMRH_INT_MASK58 (0x04000000) -#define MCF5235_INTC1_IMRH_INT_MASK59 (0x08000000) -#define MCF5235_INTC1_IMRH_INT_MASK60 (0x10000000) -#define MCF5235_INTC1_IMRH_INT_MASK61 (0x20000000) -#define MCF5235_INTC1_IMRH_INT_MASK62 (0x40000000) -#define MCF5235_INTC1_IMRH_INT_MASK63 (0x80000000) -#define MCF5235_INTC1_IMRL_MASKALL (0x00000001) -#define MCF5235_INTC1_IMRL_INT_MASK1 (0x00000002) -#define MCF5235_INTC1_IMRL_INT_MASK2 (0x00000004) -#define MCF5235_INTC1_IMRL_INT_MASK3 (0x00000008) -#define MCF5235_INTC1_IMRL_INT_MASK4 (0x00000010) -#define MCF5235_INTC1_IMRL_INT_MASK5 (0x00000020) -#define MCF5235_INTC1_IMRL_INT_MASK6 (0x00000040) -#define MCF5235_INTC1_IMRL_INT_MASK7 (0x00000080) -#define MCF5235_INTC1_IMRL_INT_MASK8 (0x00000100) -#define MCF5235_INTC1_IMRL_INT_MASK9 (0x00000200) -#define MCF5235_INTC1_IMRL_INT_MASK10 (0x00000400) -#define MCF5235_INTC1_IMRL_INT_MASK11 (0x00000800) -#define MCF5235_INTC1_IMRL_INT_MASK12 (0x00001000) -#define MCF5235_INTC1_IMRL_INT_MASK13 (0x00002000) -#define MCF5235_INTC1_IMRL_INT_MASK14 (0x00004000) -#define MCF5235_INTC1_IMRL_INT_MASK15 (0x00008000) -#define MCF5235_INTC1_IMRL_INT_MASK16 (0x00010000) -#define MCF5235_INTC1_IMRL_INT_MASK17 (0x00020000) -#define MCF5235_INTC1_IMRL_INT_MASK18 (0x00040000) -#define MCF5235_INTC1_IMRL_INT_MASK19 (0x00080000) -#define MCF5235_INTC1_IMRL_INT_MASK20 (0x00100000) -#define MCF5235_INTC1_IMRL_INT_MASK21 (0x00200000) -#define MCF5235_INTC1_IMRL_INT_MASK22 (0x00400000) -#define MCF5235_INTC1_IMRL_INT_MASK23 (0x00800000) -#define MCF5235_INTC1_IMRL_INT_MASK24 (0x01000000) -#define MCF5235_INTC1_IMRL_INT_MASK25 (0x02000000) -#define MCF5235_INTC1_IMRL_INT_MASK26 (0x04000000) -#define MCF5235_INTC1_IMRL_INT_MASK27 (0x08000000) -#define MCF5235_INTC1_IMRL_INT_MASK28 (0x10000000) -#define MCF5235_INTC1_IMRL_INT_MASK29 (0x20000000) -#define MCF5235_INTC1_IMRL_INT_MASK30 (0x40000000) -#define MCF5235_INTC1_IMRL_INT_MASK31 (0x80000000) -#define MCF5235_INTC1_INTFRCH_INTFRC32 (0x00000001) -#define MCF5235_INTC1_INTFRCH_INTFRC33 (0x00000002) -#define MCF5235_INTC1_INTFRCH_INTFRC34 (0x00000004) -#define MCF5235_INTC1_INTFRCH_INTFRC35 (0x00000008) -#define MCF5235_INTC1_INTFRCH_INTFRC36 (0x00000010) -#define MCF5235_INTC1_INTFRCH_INTFRC37 (0x00000020) -#define MCF5235_INTC1_INTFRCH_INTFRC38 (0x00000040) -#define MCF5235_INTC1_INTFRCH_INTFRC39 (0x00000080) -#define MCF5235_INTC1_INTFRCH_INTFRC40 (0x00000100) -#define MCF5235_INTC1_INTFRCH_INTFRC41 (0x00000200) -#define MCF5235_INTC1_INTFRCH_INTFRC42 (0x00000400) -#define MCF5235_INTC1_INTFRCH_INTFRC43 (0x00000800) -#define MCF5235_INTC1_INTFRCH_INTFRC44 (0x00001000) -#define MCF5235_INTC1_INTFRCH_INTFRC45 (0x00002000) -#define MCF5235_INTC1_INTFRCH_INTFRC46 (0x00004000) -#define MCF5235_INTC1_INTFRCH_INTFRC47 (0x00008000) -#define MCF5235_INTC1_INTFRCH_INTFRC48 (0x00010000) -#define MCF5235_INTC1_INTFRCH_INTFRC49 (0x00020000) -#define MCF5235_INTC1_INTFRCH_INTFRC50 (0x00040000) -#define MCF5235_INTC1_INTFRCH_INTFRC51 (0x00080000) -#define MCF5235_INTC1_INTFRCH_INTFRC52 (0x00100000) -#define MCF5235_INTC1_INTFRCH_INTFRC53 (0x00200000) -#define MCF5235_INTC1_INTFRCH_INTFRC54 (0x00400000) -#define MCF5235_INTC1_INTFRCH_INTFRC55 (0x00800000) -#define MCF5235_INTC1_INTFRCH_INTFRC56 (0x01000000) -#define MCF5235_INTC1_INTFRCH_INTFRC57 (0x02000000) -#define MCF5235_INTC1_INTFRCH_INTFRC58 (0x04000000) -#define MCF5235_INTC1_INTFRCH_INTFRC59 (0x08000000) -#define MCF5235_INTC1_INTFRCH_INTFRC60 (0x10000000) -#define MCF5235_INTC1_INTFRCH_INTFRC61 (0x20000000) -#define MCF5235_INTC1_INTFRCH_INTFRC62 (0x40000000) -#define MCF5235_INTC1_INTFRCH_INTFRC63 (0x80000000) -#define MCF5235_INTC1_INTFRCL_INTFRC1 (0x00000002) -#define MCF5235_INTC1_INTFRCL_INTFRC2 (0x00000004) -#define MCF5235_INTC1_INTFRCL_INTFRC3 (0x00000008) -#define MCF5235_INTC1_INTFRCL_INTFRC4 (0x00000010) -#define MCF5235_INTC1_INTFRCL_INTFRC5 (0x00000020) -#define MCF5235_INTC1_INTFRCL_INT6 (0x00000040) -#define MCF5235_INTC1_INTFRCL_INT7 (0x00000080) -#define MCF5235_INTC1_INTFRCL_INT8 (0x00000100) -#define MCF5235_INTC1_INTFRCL_INT9 (0x00000200) -#define MCF5235_INTC1_INTFRCL_INT10 (0x00000400) -#define MCF5235_INTC1_INTFRCL_INTFRC11 (0x00000800) -#define MCF5235_INTC1_INTFRCL_INTFRC12 (0x00001000) -#define MCF5235_INTC1_INTFRCL_INTFRC13 (0x00002000) -#define MCF5235_INTC1_INTFRCL_INTFRC14 (0x00004000) -#define MCF5235_INTC1_INTFRCL_INT15 (0x00008000) -#define MCF5235_INTC1_INTFRCL_INTFRC16 (0x00010000) -#define MCF5235_INTC1_INTFRCL_INTFRC17 (0x00020000) -#define MCF5235_INTC1_INTFRCL_INTFRC18 (0x00040000) -#define MCF5235_INTC1_INTFRCL_INTFRC19 (0x00080000) -#define MCF5235_INTC1_INTFRCL_INTFRC20 (0x00100000) -#define MCF5235_INTC1_INTFRCL_INTFRC21 (0x00200000) -#define MCF5235_INTC1_INTFRCL_INTFRC22 (0x00400000) -#define MCF5235_INTC1_INTFRCL_INTFRC23 (0x00800000) -#define MCF5235_INTC1_INTFRCL_INTFRC24 (0x01000000) -#define MCF5235_INTC1_INTFRCL_INTFRC25 (0x02000000) -#define MCF5235_INTC1_INTFRCL_INTFRC26 (0x04000000) -#define MCF5235_INTC1_INTFRCL_INTFRC27 (0x08000000) -#define MCF5235_INTC1_INTFRCL_INTFRC28 (0x10000000) -#define MCF5235_INTC1_INTFRCL_INTFRC29 (0x20000000) -#define MCF5235_INTC1_INTFRCL_INTFRC30 (0x40000000) -#define MCF5235_INTC1_INTFRCL_INTFRC31 (0x80000000) -#define MCF5235_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1) -#define MCF5235_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF5235_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/********************************************************************* -* -* Programmable Interrupt Timer Modules (PIT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_PIT_PCSR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x150000))) -#define MCF5235_PIT_PMR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x150002))) -#define MCF5235_PIT_PCNTR0 (*(vuint16*)((uintptr_t)__IPSBAR + (0x150004))) -#define MCF5235_PIT_PCSR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x160000))) -#define MCF5235_PIT_PMR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x160002))) -#define MCF5235_PIT_PCNTR1 (*(vuint16*)((uintptr_t)__IPSBAR + (0x160004))) -#define MCF5235_PIT_PCSR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x170000))) -#define MCF5235_PIT_PMR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x170002))) -#define MCF5235_PIT_PCNTR2 (*(vuint16*)((uintptr_t)__IPSBAR + (0x170004))) -#define MCF5235_PIT_PCSR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x180000))) -#define MCF5235_PIT_PMR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x180002))) -#define MCF5235_PIT_PCNTR3 (*(vuint16*)((uintptr_t)__IPSBAR + (0x180004))) -#define MCF5235_PIT_PCSR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x150000+((x)*0x10000)))) -#define MCF5235_PIT_PMR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x150002+((x)*0x10000)))) -#define MCF5235_PIT_PCNTR(x) (*(vuint16*)((uintptr_t)__IPSBAR + (0x150004+((x)*0x10000)))) -#define MCF5235_PIT_PCSR_EN (0x0001) -#define MCF5235_PIT_PCSR_RLD (0x0002) -#define MCF5235_PIT_PCSR_PIF (0x0004) -#define MCF5235_PIT_PCSR_PIE (0x0008) -#define MCF5235_PIT_PCSR_OVW (0x0010) -#define MCF5235_PIT_PCSR_HALTED (0x0020) -#define MCF5235_PIT_PCSR_DOZE (0x0040) -#define MCF5235_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) -#define MCF5235_PIT_PMR_PM0 (0x0001) -#define MCF5235_PIT_PMR_PM1 (0x0002) -#define MCF5235_PIT_PMR_PM2 (0x0004) -#define MCF5235_PIT_PMR_PM3 (0x0008) -#define MCF5235_PIT_PMR_PM4 (0x0010) -#define MCF5235_PIT_PMR_PM5 (0x0020) -#define MCF5235_PIT_PMR_PM6 (0x0040) -#define MCF5235_PIT_PMR_PM7 (0x0080) -#define MCF5235_PIT_PMR_PM8 (0x0100) -#define MCF5235_PIT_PMR_PM9 (0x0200) -#define MCF5235_PIT_PMR_PM10 (0x0400) -#define MCF5235_PIT_PMR_PM11 (0x0800) -#define MCF5235_PIT_PMR_PM12 (0x1000) -#define MCF5235_PIT_PMR_PM13 (0x2000) -#define MCF5235_PIT_PMR_PM14 (0x4000) -#define MCF5235_PIT_PMR_PM15 (0x8000) -#define MCF5235_PIT_PCNTR_PC0 (0x0001) -#define MCF5235_PIT_PCNTR_PC1 (0x0002) -#define MCF5235_PIT_PCNTR_PC2 (0x0004) -#define MCF5235_PIT_PCNTR_PC3 (0x0008) -#define MCF5235_PIT_PCNTR_PC4 (0x0010) -#define MCF5235_PIT_PCNTR_PC5 (0x0020) -#define MCF5235_PIT_PCNTR_PC6 (0x0040) -#define MCF5235_PIT_PCNTR_PC7 (0x0080) -#define MCF5235_PIT_PCNTR_PC8 (0x0100) -#define MCF5235_PIT_PCNTR_PC9 (0x0200) -#define MCF5235_PIT_PCNTR_PC10 (0x0400) -#define MCF5235_PIT_PCNTR_PC11 (0x0800) -#define MCF5235_PIT_PCNTR_PC12 (0x1000) -#define MCF5235_PIT_PCNTR_PC13 (0x2000) -#define MCF5235_PIT_PCNTR_PC14 (0x4000) -#define MCF5235_PIT_PCNTR_PC15 (0x8000) - -/********************************************************************* -* -* Queued Serial Peripheral Interface (QSPI) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF5235_QSPI_QMR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000340))) -#define MCF5235_QSPI_QDLYR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000344))) -#define MCF5235_QSPI_QWR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000348))) -#define MCF5235_QSPI_QIR (*(vuint16*)((uintptr_t)__IPSBAR + (0x00034C))) -#define MCF5235_QSPI_QAR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000350))) -#define MCF5235_QSPI_QDR (*(vuint16*)((uintptr_t)__IPSBAR + (0x000354))) - -/* Bit definitions and macros for MCF5235_QSPI_QMR */ -#define MCF5235_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) -#define MCF5235_QSPI_QMR_CPHA (0x0100) -#define MCF5235_QSPI_QMR_CPOL (0x0200) -#define MCF5235_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) -#define MCF5235_QSPI_QMR_DOHIE (0x4000) -#define MCF5235_QSPI_QMR_MSTR (0x8000) -#define MCF5235_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) -#define MCF5235_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define MCF5235_QSPI_QDLYR_SPE (0x8000) -#define MCF5235_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) -#define MCF5235_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define MCF5235_QSPI_QWR_CSIV (0x1000) -#define MCF5235_QSPI_QWR_WRTO (0x2000) -#define MCF5235_QSPI_QWR_WREN (0x4000) -#define MCF5235_QSPI_QWR_HALT (0x8000) -#define MCF5235_QSPI_QIR_SPIF (0x0001) -#define MCF5235_QSPI_QIR_ABRT (0x0004) -#define MCF5235_QSPI_QIR_WCEF (0x0008) -#define MCF5235_QSPI_QIR_SPIFE (0x0100) -#define MCF5235_QSPI_QIR_ABRTE (0x0400) -#define MCF5235_QSPI_QIR_WCEFE (0x0800) -#define MCF5235_QSPI_QIR_ABRTL (0x1000) -#define MCF5235_QSPI_QIR_ABRTB (0x4000) -#define MCF5235_QSPI_QIR_WCEFB (0x8000) -#define MCF5235_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) - -/********************************************************************/ - - -#endif /* _CPU_MCF5235_H */ diff --git a/c/src/lib/libcpu/m68k/mcf5272/include/mcf5272.h b/c/src/lib/libcpu/m68k/mcf5272/include/mcf5272.h deleted file mode 100644 index 37dae92d98..0000000000 --- a/c/src/lib/libcpu/m68k/mcf5272/include/mcf5272.h +++ /dev/null @@ -1,699 +0,0 @@ -/* - * Coldfire MCF5272 definitions. - * Contents of this file based on information provided in - * Motorola MCF5272 User's Manual. - * - * Copyright (C) 2004 Jay Monkman <jtm@lopingdog.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __MCF5272_H__ -#define __MCF5272_H__ - -#ifndef ASM -#include <rtems.h> -#endif - -#define bit(x) (1 << (x)) - -#define MCF5272_SIM_BASE(mbar) ((mbar) + 0x0000) -#define MCF5272_INT_BASE(mbar) ((mbar) + 0x0020) -#define MCF5272_CS_BASE(mbar) ((mbar) + 0x0040) -#define MCF5272_GPIO_BASE(mbar) ((mbar) + 0x0080) -#define MCF5272_QSPI_BASE(mbar) ((mbar) + 0x00A0) -#define MCF5272_PWM_BASE(mbar) ((mbar) + 0x00C0) -#define MCF5272_DMAC_BASE(mbar) ((mbar) + 0x00E0) -#define MCF5272_UART0_BASE(mbar) ((mbar) + 0x0100) -#define MCF5272_UART1_BASE(mbar) ((mbar) + 0x0140) -#define MCF5272_SDRAMC_BASE(mbar) ((mbar) + 0x0180) -#define MCF5272_TIMER_BASE(mbar) ((mbar) + 0x0200) -#define MCF5272_PLIC_BASE(mbar) ((mbar) + 0x0300) -#define MCF5272_ENET_BASE(mbar) ((mbar) + 0x0840) -#define MCF5272_USB_BASE(mbar) ((mbar) + 0x1000) - - -/* RAMBAR - SRAM Base Address Register */ -#define MCF5272_RAMBAR_BA (0xfffff000) /* SRAM Base Address */ -#define MCF5272_RAMBAR_WP (0x00000100) /* Write Protect */ -#define MCF5272_RAMBAR_CI (0x00000020) /* CPU Space mask */ -#define MCF5272_RAMBAR_SC (0x00000010) /* Supervisor Code Space Mask */ -#define MCF5272_RAMBAR_SD (0x00000008) /* Supervisor Data Space Mask */ -#define MCF5272_RAMBAR_UC (0x00000004) /* User Code Space Mask */ -#define MCF5272_RAMBAR_UD (0x00000002) /* User Data Space Mask */ -#define MCF5272_RAMBAR_V (0x00000001) /* Contents of RAMBAR are valid */ - -/* MBAR - Module Base Address Register */ -#define MCF5272_MBAR_BA (0xffff0000) /* Base Address */ -#define MCF5272_MBAR_SC (0x00000010) /* Supervisor Code Space Mask */ -#define MCF5272_MBAR_SD (0x00000008) /* Supervisor Data Space Mask */ -#define MCF5272_MBAR_UC (0x00000004) /* User Code Space Mask */ -#define MCF5272_MBAR_UD (0x00000002) /* User Data Space Mask */ -#define MCF5272_MBAR_V (0x00000001) /* Contents of MBAR are valid */ - -/* CACR - Cache Control Register */ -#define MCF5272_CACR_CENB (0x80000000) /* Cache Enable */ -#define MCF5272_CACR_CPDI (0x10000000) /* Disable CPUSHL Invalidation */ -#define MCF5272_CACR_CFRZ (0x08000000) /* Cache Freeze */ -#define MCF5272_CACR_CINV (0x01000000) /* Cache Invalidate */ -#define MCF5272_CACR_CEIB (0x00000400) /* Cache Enable Noncacheable - instruction bursting */ -#define MCF5272_CACR_DCM (0x00000200) /* Default cache mode - noncacheable*/ -#define MCF5272_CACR_DBWE (0x00000100) /* Default Buffered Write Enable */ -#define MCF5272_CACR_DWP (0x00000020) /* Default Write Protection */ -#define MCF5272_CACR_CLNF (0x00000003) /* Cache Line Fill */ - -/* ACRx - Cache Access Control Registers */ -#define MCF5272_ACR_BA (0xff000000) /* Address Base */ -#define MCF5272_ACR_BAM (0x00ff0000) /* Address Mask */ -#define MCF5272_ACR_EN (0x00008000) /* Enable */ -#define MCF5272_ACR_SM_USR (0x00000000) /* Match if user mode */ -#define MCF5272_ACR_SM_SVR (0x00002000) /* Match if supervisor mode */ -#define MCF5272_ACR_SM_ANY (0x00004000) /* Match Always */ -#define MCF527_ACR_CM (0x00000040) /* Cache Mode (1 - noncacheable) */ -#define MCF5272_ACR_BWE (0x00000020) /* Buffered Write Enable */ -#define MCF5272_ACR_WP (0x00000004) /* Write Protect */ -#define MCF5272_ACR_BASE(base) ((base) & MCF5272_ACR_BA) -#define MCF5272_ACR_MASK(mask) (((mask) >> 8) & MCF5272_ACR_BAM) - - -#define MCF5272_ICR1_INT1_PI (bit(31)) -#define MCF5272_ICR1_INT1_IPL(x) ((x) << 28) -#define MCF5272_ICR1_INT1_MASK ((7) << 28) -#define MCF5272_ICR1_INT2_PI (bit(27)) -#define MCF5272_ICR1_INT2_IPL(x) ((x) << 24) -#define MCF5272_ICR1_INT2_MASK ((7) << 24) -#define MCF5272_ICR1_INT3_PI (bit(23)) -#define MCF5272_ICR1_INT3_IPL(x) ((x) << 20) -#define MCF5272_ICR1_INT3_MASK ((7) << 20) -#define MCF5272_ICR1_INT3_PI (bit(19)) -#define MCF5272_ICR1_INT3_IPL(x) ((x) << 16) -#define MCF5272_ICR1_INT3_MASK ((7) << 16) -#define MCF5272_ICR1_TMR0_PI (bit(15)) -#define MCF5272_ICR1_TMR0_IPL(x) ((x) << 12) -#define MCF5272_ICR1_TMR0_MASK ((7) << 12) -#define MCF5272_ICR1_TMR1_PI (bit(11)) -#define MCF5272_ICR1_TMR1_IPL(x) ((x) << 8) -#define MCF5272_ICR1_TMR1_MASK ((7) << 8) -#define MCF5272_ICR1_TMR2_PI (bit(7)) -#define MCF5272_ICR1_TMR2_IPL(x) ((x) << 4) -#define MCF5272_ICR1_TMR2_MASK ((7) << 4) -#define MCF5272_ICR1_TMR3_PI (bit(3)) -#define MCF5272_ICR1_TMR3_IPL(x) ((x) << 0) -#define MCF5272_ICR1_TMR3_MASK ((7) << 0) - -#define MCF5272_ICR3_USB4_PI (bit(31)) -#define MCF5272_ICR3_USB4_IPL(x) ((x) << 28) -#define MCF5272_ICR3_USB4_MASK ((7) << 28) -#define MCF5272_ICR3_USB5_PI (bit(27)) -#define MCF5272_ICR3_USB5_IPL(x) ((x) << 24) -#define MCF5272_ICR3_USB5_MASK ((7) << 24) -#define MCF5272_ICR3_USB6_PI (bit(23)) -#define MCF5272_ICR3_USB6_IPL(x) ((x) << 20) -#define MCF5272_ICR3_USB6_MASK ((7) << 20) -#define MCF5272_ICR3_USB7_PI (bit(19)) -#define MCF5272_ICR3_USB7_IPL(x) ((x) << 16) -#define MCF5272_ICR3_USB7_MASK ((7) << 16) -#define MCF5272_ICR3_DMA_PI (bit(15)) -#define MCF5272_ICR3_DMA_IPL(x) ((x) << 12) -#define MCF5272_ICR3_DMA_MASK ((7) << 12) -#define MCF5272_ICR3_ERX_PI (bit(11)) -#define MCF5272_ICR3_ERX_IPL(x) ((x) << 8) -#define MCF5272_ICR3_ERX_MASK ((7) << 8) -#define MCF5272_ICR3_ETX_PI (bit(7)) -#define MCF5272_ICR3_ETX_IPL(x) ((x) << 4) -#define MCF5272_ICR3_ETX_MASK ((7) << 4) -#define MCF5272_ICR3_ENTC_PI (bit(3)) -#define MCF5272_ICR3_ENTC_IPL(x) ((x) << 0) -#define MCF5272_ICR3_ENTC_MASK ((7) << 0) - - -#define MCF5272_USR_RB (bit(7)) -#define MCF5272_USR_FE (bit(6)) -#define MCF5272_USR_PE (bit(5)) -#define MCF5272_USR_OE (bit(4)) -#define MCF5272_USR_TXEMP (bit(3)) -#define MCF5272_USR_TXRDY (bit(2)) -#define MCF5272_USR_FFULL (bit(1)) -#define MCF5272_USR_RXRDY (bit(0)) - -#define MCF5272_TMR_PS_MASK 0xff00 -#define MCF5272_TMR_PS_SHIFT 8 -#define MCF5272_TMR_CE_DISABLE (0 << 6) -#define MCF5272_TMR_CE_RISING (1 << 6) -#define MCF5272_TMR_CE_FALLING (2 << 6) -#define MCF5272_TMR_CE_ANY (3 << 6) -#define MCF5272_TMR_OM (bit(5)) -#define MCF5272_TMR_ORI (bit(4)) -#define MCF5272_TMR_FRR (bit(3)) -#define MCF5272_TMR_CLK_STOP (0 << 1) -#define MCF5272_TMR_CLK_MSTR (1 << 1) -#define MCF5272_TMR_CLK_MSTR16 (2 << 1) -#define MCF5272_TMR_CLK_TIN (3 << 1) -#define MCF5272_TMR_RST (bit(0)) -#define MCF5272_TER_REF (bit(1)) -#define MCF5272_TER_CAP (bit(0)) - -#define MCF5272_SCR_PRI (bit(8)) -#define MCF5272_SCR_AR (bit(7)) -#define MCF5272_SCR_SRST (bit(6)) -#define MCF5272_SCR_BUSLOCK (bit(3)) -#define MCF5272_SCR_HWR_128 (0) -#define MCF5272_SCR_HWR_256 (1) -#define MCF5272_SCR_HWR_512 (2) -#define MCF5272_SCR_HWR_1024 (3) -#define MCF5272_SCR_HWR_2048 (4) -#define MCF5272_SCR_HWR_4096 (5) -#define MCF5272_SCR_HWR_8192 (6) -#define MCF5272_SCR_HWR_16384 (7) - -#define MCF5272_SPR_ADC (bit(15)) -#define MCF5272_SPR_WPV (bit(15)) -#define MCF5272_SPR_SMV (bit(15)) -#define MCF5272_SPR_PE (bit(15)) -#define MCF5272_SPR_HWT (bit(15)) -#define MCF5272_SPR_RPV (bit(15)) -#define MCF5272_SPR_EXT (bit(15)) -#define MCF5272_SPR_SUV (bit(15)) -#define MCF5272_SPR_ADCEN (bit(15)) -#define MCF5272_SPR_WPVEN (bit(15)) -#define MCF5272_SPR_SMVEN (bit(15)) -#define MCF5272_SPR_PEEN (bit(15)) -#define MCF5272_SPR_HWTEN (bit(15)) -#define MCF5272_SPR_RPVEN (bit(15)) -#define MCF5272_SPR_EXTEN (bit(15)) -#define MCF5272_SPR_SUVEN (bit(15)) - -#define MCF5272_ENET_TX_RT (bit(25)) -#define MCF5272_ENET_ETHERN_EN (bit(1)) -#define MCF5272_ENET_RESET (bit(0)) - -#define MCF5272_ENET_EIR_HBERR (bit(31)) -#define MCF5272_ENET_EIR_BABR (bit(30)) -#define MCF5272_ENET_EIR_BABT (bit(29)) -#define MCF5272_ENET_EIR_GRA (bit(28)) -#define MCF5272_ENET_EIR_TXF (bit(27)) -#define MCF5272_ENET_EIR_TXB (bit(26)) -#define MCF5272_ENET_EIR_RXF (bit(25)) -#define MCF5272_ENET_EIR_RXB (bit(24)) -#define MCF5272_ENET_EIR_MII (bit(23)) -#define MCF5272_ENET_EIR_EBERR (bit(22)) -#define MCF5272_ENET_EIR_UMINT (bit(21)) - -#define MCF5272_ENET_RCR_PROM (bit(3)) -#define MCF5272_ENET_RCR_MII (bit(2)) -#define MCF5272_ENET_RCR_DRT (bit(1)) -#define MCF5272_ENET_RCR_LOOP (bit(0)) - -#define MCF5272_ENET_TCR_FDEN (bit(2)) -#define MCF5272_ENET_TCR_HBC (bit(1)) -#define MCF5272_ENET_TCR_GTS (bit(0)) - - -#ifndef ASM -typedef struct { - volatile uint32_t mbar; /* READ ONLY!! */ - - volatile uint16_t scr; - volatile uint16_t _res0; - - volatile uint16_t _res1; - volatile uint16_t spr; - - volatile uint32_t pmr; - - volatile uint16_t _res2; - volatile uint16_t alpr; - - volatile uint32_t dir; -} sim_regs_t; - -typedef struct { - volatile uint32_t icr1; - volatile uint32_t icr2; - volatile uint32_t icr3; - volatile uint32_t icr4; - volatile uint32_t isr; - volatile uint32_t pitr; - volatile uint32_t piwr; - volatile uint8_t _res0[3]; - volatile uint8_t pivr; -} intctrl_regs_t; - -typedef struct { - volatile uint32_t csbr0; - volatile uint32_t csor0; - volatile uint32_t csbr1; - volatile uint32_t csor1; - volatile uint32_t csbr2; - volatile uint32_t csor2; - volatile uint32_t csbr3; - volatile uint32_t csor3; - volatile uint32_t csbr4; - volatile uint32_t csor4; - volatile uint32_t csbr5; - volatile uint32_t csor5; - volatile uint32_t csbr6; - volatile uint32_t csor6; - volatile uint32_t csbr7; - volatile uint32_t csor7; -} chipsel_regs_t; - -typedef struct { - volatile uint32_t pacnt; - - volatile uint16_t paddr; - volatile uint16_t _res0; - - volatile uint16_t _res1; - volatile uint16_t padat; - - volatile uint32_t pbcnt; - - volatile uint16_t pbddr; - volatile uint16_t _res2; - - volatile uint16_t _res3; - volatile uint16_t pbdat; - - volatile uint16_t pcddr; - volatile uint16_t _res4; - - volatile uint16_t _res5; - volatile uint16_t pcdat; - - volatile uint32_t pdcnt; -} gpio_regs_t; - -typedef struct { - volatile uint32_t qmr; - volatile uint32_t qdlyr; - volatile uint32_t qwr; - volatile uint32_t qir; - volatile uint32_t qar; - volatile uint32_t qdr; -} qspi_regs_t; - -typedef struct { - volatile uint8_t pwcr1; - volatile uint8_t _res0[3]; - - volatile uint8_t pwcr2; - volatile uint8_t _res1[3]; - - volatile uint8_t pwcr3; - volatile uint8_t _res2[3]; - - volatile uint8_t pwwd1; - volatile uint8_t _res3[3]; - - volatile uint8_t pwwd2; - volatile uint8_t _res4[3]; - - volatile uint8_t pwwd3; - volatile uint8_t _res5[3]; -} pwm_regs_t; - -typedef struct { - volatile uint32_t dcmr; - - volatile uint16_t _res0; - volatile uint16_t dcir; - - volatile uint32_t dbcr; - - volatile uint32_t dsar; - - volatile uint32_t ddar; -} dma_regs_t; - -typedef struct { - volatile uint8_t umr; /* 0x000 */ - volatile uint8_t _res0[3]; - - volatile uint8_t ucsr; /* 0x004 */ - volatile uint8_t _res2[3]; - - volatile uint8_t ucr; /* 0x008 */ - volatile uint8_t _res3[3]; - - volatile uint8_t udata; /* 0x00c */ - volatile uint8_t _res4[3]; - - volatile uint8_t uccr; /* 0x010 */ - volatile uint8_t _res6[3]; - - volatile uint8_t uisr; /* 0x014 */ - volatile uint8_t _res8[3]; - - volatile uint8_t ubg1; /* 0x018 */ - volatile uint8_t _res10[3]; - - volatile uint8_t ubg2; /* 0x01c */ - volatile uint8_t _res11[3]; - - volatile uint8_t uabr1; /* 0x020 */ - volatile uint8_t _res12[3]; - - volatile uint8_t uabr2; /* 0x024 */ - volatile uint8_t _res13[3]; - - volatile uint8_t utxfcsr; /* 0x028 */ - volatile uint8_t _res14[3]; - - volatile uint8_t urxfcsr; /* 0x02c */ - volatile uint8_t _res15[3]; - - volatile uint8_t ufpdn; /* 0x030 */ - volatile uint8_t _res16[3]; - - volatile uint8_t uip; /* 0x034 */ - volatile uint8_t _res17[3]; - - volatile uint8_t uop1; /* 0x038 */ - volatile uint8_t _res18[3]; - - volatile uint8_t uop0; /* 0x03c */ - volatile uint8_t _res19[3]; -} uart_regs_t; - -typedef struct { - volatile uint16_t tmr0; - volatile uint16_t _res0; - - volatile uint16_t trr0; - volatile uint16_t _res1; - - volatile uint16_t tcap0; - volatile uint16_t _res2; - - volatile uint16_t tcn0; - volatile uint16_t _res3; - - volatile uint16_t ter0; - volatile uint16_t _res4; - - volatile uint8_t _res40[12]; - - volatile uint16_t tmr1; - volatile uint16_t _res5; - - volatile uint16_t trr1; - volatile uint16_t _res6; - - volatile uint16_t tcap1; - volatile uint16_t _res7; - - volatile uint16_t tcn1; - volatile uint16_t _res8; - - volatile uint16_t ter1; - volatile uint16_t _res9; - - volatile uint8_t _res91[12]; - - volatile uint16_t tmr2; - volatile uint16_t _res10; - - volatile uint16_t trr2; - volatile uint16_t _res11; - - volatile uint16_t tcap2; - volatile uint16_t _res12; - - volatile uint16_t tcn2; - volatile uint16_t _res13; - - volatile uint16_t ter2; - volatile uint16_t _res14; - - volatile uint8_t _res140[12]; - - volatile uint16_t tmr3; - volatile uint16_t _res15; - - volatile uint16_t trr3; - volatile uint16_t _res16; - - volatile uint16_t tcap3; - volatile uint16_t _res17; - - volatile uint16_t tcn3; - volatile uint16_t _res18; - - volatile uint16_t ter3; - volatile uint16_t _res19; - - volatile uint8_t _res190[12]; - - volatile uint16_t wrrr; - volatile uint16_t _res20; - - volatile uint16_t wirr; - volatile uint16_t _res21; - - volatile uint16_t wcr; - volatile uint16_t _res22; - - volatile uint16_t wer; - volatile uint16_t _res23; -} timer_regs_t; - -typedef struct { - volatile uint32_t p0b1rr; - volatile uint32_t p1b1rr; - volatile uint32_t p2b1rr; - volatile uint32_t p3b1rr; - volatile uint32_t p0b2rr; - volatile uint32_t p1b2rr; - volatile uint32_t p2b2rr; - volatile uint32_t p3b2rr; - - volatile uint8_t p0drr; - volatile uint8_t p1drr; - volatile uint8_t p2drr; - volatile uint8_t p3drr; - - volatile uint32_t p0b1tr; - volatile uint32_t p1b1tr; - volatile uint32_t p2b1tr; - volatile uint32_t p3b1tr; - volatile uint32_t p0b2tr; - volatile uint32_t p1b2tr; - volatile uint32_t p2b2tr; - volatile uint32_t p3b2tr; - - volatile uint8_t p0dtr; - volatile uint8_t p1dtr; - volatile uint8_t p2dtr; - volatile uint8_t p3dtr; - - volatile uint16_t p0cr; - volatile uint16_t p1cr; - volatile uint16_t p2cr; - volatile uint16_t p3cr; - volatile uint16_t p0icr; - volatile uint16_t p1icr; - volatile uint16_t p2icr; - volatile uint16_t p3icr; - volatile uint16_t p0gmr; - volatile uint16_t p1gmr; - volatile uint16_t p2gmr; - volatile uint16_t p3gmr; - volatile uint16_t p0gmt; - volatile uint16_t p1gmt; - volatile uint16_t p2gmt; - volatile uint16_t p3gmt; - - volatile uint8_t _res0; - volatile uint8_t pgmts; - volatile uint8_t pgmta; - volatile uint8_t _res1; - volatile uint8_t p0gcir; - volatile uint8_t p1gcir; - volatile uint8_t p2gcir; - volatile uint8_t p3gcir; - volatile uint8_t p0gcit; - volatile uint8_t p1gcit; - volatile uint8_t p2gcit; - volatile uint8_t p3gcit; - volatile uint8_t _res3[3]; - volatile uint8_t pgcitsr; - volatile uint8_t _res4[3]; - volatile uint8_t pdcsr; - - volatile uint16_t p0psr; - volatile uint16_t p1psr; - volatile uint16_t p2psr; - volatile uint16_t p3psr; - volatile uint16_t pasr; - volatile uint8_t _res5; - volatile uint8_t plcr; - volatile uint16_t _res6; - volatile uint16_t pdrqr; - volatile uint16_t p0sdr; - volatile uint16_t p1sdr; - volatile uint16_t p2sdr; - volatile uint16_t p3sdr; - volatile uint16_t _res7; - volatile uint16_t pcsr; -} plic_regs_t; - -typedef struct { - volatile uint32_t ecr; - volatile uint32_t eir; - volatile uint32_t eimr; - volatile uint32_t ivsr; - volatile uint32_t rdar; - volatile uint32_t tdar; - volatile uint32_t _res0[10]; - volatile uint32_t mmfr; - volatile uint32_t mscr; - volatile uint32_t _res1[17]; - volatile uint32_t frbr; - volatile uint32_t frsr; - volatile uint32_t _res2[4]; - volatile uint32_t tfwr; - volatile uint32_t _res3[1]; - volatile uint32_t tfsr; - volatile uint32_t _res4[21]; - volatile uint32_t rcr; - volatile uint32_t mflr; - volatile uint32_t _res5[14]; - volatile uint32_t tcr; - volatile uint32_t _res6[158]; - volatile uint32_t malr; - volatile uint32_t maur; - volatile uint32_t htur; - volatile uint32_t htlr; - volatile uint32_t erdsr; - volatile uint32_t etdsr; - volatile uint32_t emrbr; -/* volatile uint8_t fifo[448]; */ -} enet_regs_t; - -typedef struct { - volatile uint16_t _res0; - volatile uint16_t fnr; - volatile uint16_t _res1; - volatile uint16_t fnmr; - volatile uint16_t _res2; - volatile uint16_t rfmr; - volatile uint16_t _res3; - volatile uint16_t rfmmr; - volatile uint8_t _res4[3]; - volatile uint8_t far; - volatile uint32_t asr; - volatile uint32_t drr1; - volatile uint32_t drr2; - volatile uint16_t _res5; - volatile uint16_t specr; - volatile uint16_t _res6; - volatile uint16_t ep0sr; - - volatile uint32_t iep0cfg; - volatile uint32_t oep0cfg; - volatile uint32_t ep1cfg; - volatile uint32_t ep2cfg; - volatile uint32_t ep3cfg; - volatile uint32_t ep4cfg; - volatile uint32_t ep5cfg; - volatile uint32_t ep6cfg; - volatile uint32_t ep7cfg; - volatile uint32_t ep0ctl; - - volatile uint16_t _res7; - volatile uint16_t ep1ctl; - volatile uint16_t _res8; - volatile uint16_t ep2ctl; - volatile uint16_t _res9; - volatile uint16_t ep3ctl; - volatile uint16_t _res10; - volatile uint16_t ep4ctl; - volatile uint16_t _res11; - volatile uint16_t ep5ctl; - volatile uint16_t _res12; - volatile uint16_t ep6ctl; - volatile uint16_t _res13; - volatile uint16_t ep7ctl; - - volatile uint32_t ep0isr; - - volatile uint16_t _res14; - volatile uint16_t ep1isr; - volatile uint16_t _res15; - volatile uint16_t ep2isr; - volatile uint16_t _res16; - volatile uint16_t ep3isr; - volatile uint16_t _res17; - volatile uint16_t ep4isr; - volatile uint16_t _res18; - volatile uint16_t ep5isr; - volatile uint16_t _res19; - volatile uint16_t ep6isr; - volatile uint16_t _res20; - volatile uint16_t ep7isr; - - volatile uint32_t ep0imr; - - volatile uint16_t _res21; - volatile uint16_t ep1imr; - volatile uint16_t _res22; - volatile uint16_t ep2imr; - volatile uint16_t _res23; - volatile uint16_t ep3imr; - volatile uint16_t _res24; - volatile uint16_t ep4imr; - volatile uint16_t _res25; - volatile uint16_t ep5imr; - volatile uint16_t _res26; - volatile uint16_t ep6imr; - volatile uint16_t _res27; - volatile uint16_t ep7imr; - - volatile uint32_t ep0dr; - volatile uint32_t ep1dr; - volatile uint32_t ep2dr; - volatile uint32_t ep3dr; - volatile uint32_t ep4dr; - volatile uint32_t ep5dr; - volatile uint32_t ep6dr; - volatile uint32_t ep7dr; - - volatile uint16_t _res28; - volatile uint16_t ep0dpr; - volatile uint16_t _res29; - volatile uint16_t ep1dpr; - volatile uint16_t _res30; - volatile uint16_t ep2dpr; - volatile uint16_t _res31; - volatile uint16_t ep3dpr; - volatile uint16_t _res32; - volatile uint16_t ep4dpr; - volatile uint16_t _res33; - volatile uint16_t ep5dpr; - volatile uint16_t _res34; - volatile uint16_t ep6dpr; - volatile uint16_t _res35; - volatile uint16_t ep7dpr; -/* uint8_t ram[1024]; */ -} usb_regs_t; - -extern intctrl_regs_t *g_intctrl_regs; -extern chipsel_regs_t *g_chipsel_regs; -extern gpio_regs_t *g_gpio_regs; -extern qspi_regs_t *g_qspi_regs; -extern pwm_regs_t *g_pwm_regs; -extern dma_regs_t *g_dma_regs; -extern uart_regs_t *g_uart0_regs; -extern uart_regs_t *g_uart1_regs; -extern timer_regs_t *g_timer_regs; -extern plic_regs_t *g_plic_regs; -extern enet_regs_t *g_enet_regs; -extern usb_regs_t *g_usb_regs; - -#endif /* ASM */ - -#endif /* __MCF5272_H__ */ diff --git a/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h b/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h deleted file mode 100644 index 3724f489de..0000000000 --- a/c/src/lib/libcpu/m68k/mcf5282/include/mcf5282.h +++ /dev/null @@ -1,2407 +0,0 @@ -/* - ******************************************* - * Definitions from Motorola/FreeScale * - ******************************************* - */ - -/* - * File: mcf5282.h - * Purpose: MCF5282 definitions - * - * Notes: - */ - -#ifndef _CPU_MCF5282_H -#define _CPU_MCF5282_H - -/********************************************************************/ - -/* - * File: mcf5xxx.h - * Purpose: Definitions common to all ColdFire processors - * - * Notes: - */ - -#ifndef _CPU_MCF5XXX_H -#define _CPU_MCF5XXX_H - -/***********************************************************************/ -/* - * The basic data types - * - * Those are low-level so we mark them so that they may alias anything - */ - -typedef unsigned char uint8; /* 8 bits */ -typedef unsigned short int uint16 __attribute__((__may_alias__)); /* 16 bits */ -typedef unsigned long int uint32 __attribute__((__may_alias__)); /* 32 bits */ - -typedef signed char int8; /* 8 bits */ -typedef signed short int int16 __attribute__((__may_alias__)); /* 16 bits */ -typedef signed long int int32 __attribute__((__may_alias__)); /* 32 bits */ - -typedef volatile uint8 vuint8 __attribute__((__may_alias__)); /* 8 bits */ -typedef volatile uint16 vuint16 __attribute__((__may_alias__)); /* 16 bits */ -typedef volatile uint32 vuint32 __attribute__((__may_alias__)); /* 32 bits */ - -/***********************************************************************/ -/* - * Common M68K & ColdFire definitions - */ - -#define ADDRESS uint32 -#define INSTRUCTION uint16 -#define ILLEGAL 0x4AFC -#define CPU_WORD_SIZE 16 - -#define MCF5XXX_SR_T (0x8000) -#define MCF5XXX_SR_S (0x2000) -#define MCF5XXX_SR_M (0x1000) -#define MCF5XXX_SR_IPL (0x0700) -#define MCF5XXX_SR_IPL_0 (0x0000) -#define MCF5XXX_SR_IPL_1 (0x0100) -#define MCF5XXX_SR_IPL_2 (0x0200) -#define MCF5XXX_SR_IPL_3 (0x0300) -#define MCF5XXX_SR_IPL_4 (0x0400) -#define MCF5XXX_SR_IPL_5 (0x0500) -#define MCF5XXX_SR_IPL_6 (0x0600) -#define MCF5XXX_SR_IPL_7 (0x0700) -#define MCF5XXX_SR_X (0x0010) -#define MCF5XXX_SR_N (0x0008) -#define MCF5XXX_SR_Z (0x0004) -#define MCF5XXX_SR_V (0x0002) -#define MCF5XXX_SR_C (0x0001) - -/* - * Used to set the initialize the cacr register to the BSP's desired - * starting value. - */ -void mcf5xxx_initialize_cacr(uint32_t); - -#define MCF5XXX_CACR_CENB (0x80000000) -#define MCF5XXX_CACR_CPDI (0x10000000) -#define MCF5XXX_CACR_CPD (0x10000000) -#define MCF5XXX_CACR_CFRZ (0x08000000) -#define MCF5XXX_CACR_CINV (0x01000000) -#define MCF5XXX_CACR_DIDI (0x00800000) -#define MCF5XXX_CACR_DISD (0x00400000) -#define MCF5XXX_CACR_INVI (0x00200000) -#define MCF5XXX_CACR_INVD (0x00100000) -#define MCF5XXX_CACR_CEIB (0x00000400) -#define MCF5XXX_CACR_DCM_WR (0x00000000) -#define MCF5XXX_CACR_DCM_CB (0x00000100) -#define MCF5XXX_CACR_DCM_IP (0x00000200) -#define MCF5XXX_CACR_DCM (0x00000200) -#define MCF5XXX_CACR_DCM_II (0x00000300) -#define MCF5XXX_CACR_DBWE (0x00000100) -#define MCF5XXX_CACR_DWP (0x00000020) -#define MCF5XXX_CACR_EUST (0x00000010) -#define MCF5XXX_CACR_CLNF_00 (0x00000000) -#define MCF5XXX_CACR_CLNF_01 (0x00000002) -#define MCF5XXX_CACR_CLNF_10 (0x00000004) -#define MCF5XXX_CACR_CLNF_11 (0x00000006) - -#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) -#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) -#define MCF5XXX_ACR_EN (0x00008000) -#define MCF5XXX_ACR_SM_USER (0x00000000) -#define MCF5XXX_ACR_SM_SUPER (0x00002000) -#define MCF5XXX_ACR_SM_IGNORE (0x00006000) -#define MCF5XXX_ACR_ENIB (0x00000080) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_DCM_WR (0x00000000) -#define MCF5XXX_ACR_DCM_CB (0x00000020) -#define MCF5XXX_ACR_DCM_IP (0x00000040) -#define MCF5XXX_ACR_DCM_II (0x00000060) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_BWE (0x00000020) -#define MCF5XXX_ACR_WP (0x00000004) - -#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) -#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) -#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) -#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) -#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) -#define MCF5XXX_RAMBAR_WP (0x00000100) -#define MCF5XXX_RAMBAR_CI (0x00000020) -#define MCF5XXX_RAMBAR_SC (0x00000010) -#define MCF5XXX_RAMBAR_SD (0x00000008) -#define MCF5XXX_RAMBAR_UC (0x00000004) -#define MCF5XXX_RAMBAR_UD (0x00000002) -#define MCF5XXX_RAMBAR_V (0x00000001) - -/***********************************************************************/ -/* - * The ColdFire family of processors has a simplified exception stack - * frame that looks like the following: - * - * 3322222222221111 111111 - * 1098765432109876 5432109876543210 - * 8 +----------------+----------------+ - * | Program Counter | - * 4 +----------------+----------------+ - * |FS/Fmt/Vector/FS| SR | - * SP --> 0 +----------------+----------------+ - * - * The stack self-aligns to a 4-byte boundary at an exception, with - * the FS/Fmt/Vector/FS field indicating the size of the adjustment - * (SP += 0,1,2,3 bytes). - */ - -#define MCF5XXX_RD_SF_FORMAT(PTR) \ - ((*((uint16 *)(PTR)) >> 12) & 0x00FF) - -#define MCF5XXX_RD_SF_VECTOR(PTR) \ - ((*((uint16 *)(PTR)) >> 2) & 0x00FF) - -#define MCF5XXX_RD_SF_FS(PTR) \ - ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) ) - -#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1) -#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1) - -/********************************************************************/ -/* - * Functions provided by mcf5xxx.s - */ - -int asm_set_ipl (uint32); -void mcf5xxx_wr_cacr (uint32); -void mcf5xxx_wr_acr0 (uint32); -void mcf5xxx_wr_acr1 (uint32); -void mcf5xxx_wr_acr2 (uint32); -void mcf5xxx_wr_acr3 (uint32); -void mcf5xxx_wr_other_a7 (uint32); -void mcf5xxx_wr_other_sp (uint32); -void mcf5xxx_wr_vbr (uint32); -void mcf5xxx_wr_macsr (uint32); -void mcf5xxx_wr_mask (uint32); -void mcf5xxx_wr_acc0 (uint32); -void mcf5xxx_wr_accext01 (uint32); -void mcf5xxx_wr_accext23 (uint32); -void mcf5xxx_wr_acc1 (uint32); -void mcf5xxx_wr_acc2 (uint32); -void mcf5xxx_wr_acc3 (uint32); -void mcf5xxx_wr_sr (uint32); -void mcf5xxx_wr_rambar0 (uint32); -void mcf5xxx_wr_rambar1 (uint32); -void mcf5xxx_wr_mbar (uint32); -void mcf5xxx_wr_mbar0 (uint32); -void mcf5xxx_wr_mbar1 (uint32); - -/********************************************************************/ - -#endif /* _CPU_MCF5XXX_H */ - - -/********************************************************************/ -/* - * Memory map definitions from linker command files - */ -extern uint8 __IPSBAR[]; - -/********************************************************************* -* -* System Control Module (SCM) -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_SCM_IPSBAR (*(vuint32 *)(&__IPSBAR[0x0000])) -#define MCF5282_SCM_RAMBAR (*(vuint32 *)(&__IPSBAR[0x0008])) -#define MCF5282_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x0010])) -#define MCF5282_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x0011])) -#define MCF5282_SCM_LPICR (*(vuint8 *)(&__IPSBAR[0x0012])) -#define MCF5282_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x0013])) -#define MCF5282_SCM_DMAREQC (*(vuint32 *)(&__IPSBAR[0x0014])) -#define MCF5282_SCM_MPARK (*(vuint32 *)(&__IPSBAR[0x001C])) -#define MCF5282_SCM_MPR (*(vuint8 *)(&__IPSBAR[0x0020])) -#define MCF5282_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x0024])) -#define MCF5282_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x0025])) -#define MCF5282_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x0026])) -#define MCF5282_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x0027])) -#define MCF5282_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x0028])) -#define MCF5282_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x002A])) -#define MCF5282_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x002B])) -#define MCF5282_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x002C])) -#define MCF5282_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x002E])) -#define MCF5282_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x0030])) -#define MCF5282_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x0031])) - -/* Bit level definitions and macros */ -#define MCF5282_SCM_IPSBAR_BA(x) ((x)&0xC0000000) -#define MCF5282_SCM_IPSBAR_V (0x00000001) - -#define MCF5282_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000) -#define MCF5282_SCM_RAMBAR_BDE (0x00000200) - -#define MCF5282_SCM_CRSR_EXT (0x80) -#define MCF5282_SCM_CRSR_CWDR (0x20) - -#define MCF5282_SCM_CWCR_CWE (0x80) -#define MCF5282_SCM_CWCR_CWRI (0x40) -#define MCF5282_SCM_CWCR_CWT(x) (((x)&0x03)<<3) -#define MCF5282_SCM_CWCR_CWTA (0x04) -#define MCF5282_SCM_CWCR_CWTAVAL (0x02) -#define MCF5282_SCM_CWCR_CWTIC (0x01) - -#define MCF5282_SCM_LPICR_ENBSTOP (0x80) -#define MCF5282_SCM_LPICR_XSTOP_IPL(x) (((x)&0x07)<<4) - -#define MCF5282_SCM_CWSR_SEQ1 (0x55) -#define MCF5282_SCM_CWSR_SEQ2 (0xAA) - -#define MCF5282_SCM_DMAREQC_DMAC3(x) (((x)&0x000F)<<12) -#define MCF5282_SCM_DMAREQC_DMAC2(x) (((x)&0x000F)<<8) -#define MCF5282_SCM_DMAREQC_DMAC1(x) (((x)&0x000F)<<4) -#define MCF5282_SCM_DMAREQC_DMAC0(x) (((x)&0x000F)) -#define MCF5282_SCM_DMAREQC_DMATIMER0 (0x4) -#define MCF5282_SCM_DMAREQC_DMATIMER1 (0x5) -#define MCF5282_SCM_DMAREQC_DMATIMER2 (0x6) -#define MCF5282_SCM_DMAREQC_DMATIMER3 (0x7) -#define MCF5282_SCM_DMAREQC_UART0 (0x8) -#define MCF5282_SCM_DMAREQC_UART1 (0x9) -#define MCF5282_SCM_DMAREQC_UART2 (0xA) - -#define MCF5282_SCM_MPARK_M2_P_EN (0x02000000) -#define MCF5282_SCM_MPARK_BCR24BIT (0x01000000) -#define MCF5282_SCM_MPARK_M3_PRTY(x) (((x)&0x03)<<22) -#define MCF5282_SCM_MPARK_M2_PRTY(x) (((x)&0x03)<<20) -#define MCF5282_SCM_MPARK_M0_PRTY(x) (((x)&0x03)<<18) -#define MCF5282_SCM_MPARK_M1_PRTY(x) (((x)&0x03)<<16) -#define MCF5282_SCM_MPARK_FIXED (0x00040000) -#define MCF5282_SCM_MPARK_TIMEOUT (0x00020000) -#define MCF5282_SCM_MPARK_PRK_LAST (0x00010000) -#define MCF5282_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x000F)<<8) - -#define MCF5282_SCM_MPARK_MX_PRTY_FIRST (0x3) -#define MCF5282_SCM_MPARK_MX_PRTY_SECOND (0x2) -#define MCF5282_SCM_MPARK_MX_PRTY_THIRD (0x1) -#define MCF5282_SCM_MPARK_MX_PRTY_FOURTH (0x0) - -#define MCF5282_SCM_MPR_MPR(x) (((x)&0x0F)) - -#define MCF5282_SCM_PACR_LOCK1 (0x80) -#define MCF5282_SCM_PACR_ACCESSCTRL1(x) (((x)&0x07)<<4) -#define MCF5282_SCM_PACR_LOCK0 (0x08) -#define MCF5282_SCM_PACR_ACCESSCTRL0(x) (((x)&0x07)) -#define MCF5282_SCM_PACR_RW_NA (0x0) -#define MCF5282_SCM_PACR_R_NA (0x1) -#define MCF5282_SCM_PACR_R_R (0x2) -#define MCF5282_SCM_PACR_RW_RW (0x4) -#define MCF5282_SCM_PACR_RW_R (0x5) -#define MCF5282_SCM_PACR_NA_NA (0x7) - -#define MCF5282_SCM_GPACR_LOCK (0x80) -#define MCF5282_SCM_GPACR_ACCESSCTRL(x) (((x)&0x0F)) -#define MCF5282_SCM_GPACR_ACCESSCTRL_RW_NA (0x0) -#define MCF5282_SCM_GPACR_ACCESSCTRL_R_NA (0x1) -#define MCF5282_SCM_GPACR_ACCESSCTRL_R_R (0x2) -#define MCF5282_SCM_GPACR_ACCESSCTRL_RW_RW (0x4) -#define MCF5282_SCM_GPACR_ACCESSCTRL_RW_R (0x5) -#define MCF5282_SCM_GPACR_ACCESSCTRL_NA_NA (0x7) -#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_NA (0x8) -#define MCF5282_SCM_GPACR_ACCESSCTRL_RE_NA (0x9) -#define MCF5282_SCM_GPACR_ACCESSCTRL_RE_RE (0xA) -#define MCF5282_SCM_GPACR_ACCESSCTRL_E_NA (0xB) -#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_RWE (0xC) -#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_RE (0xD) -#define MCF5282_SCM_GPACR_ACCESSCTRL_RWE_E (0xF) - -/********************************************************************* -* -* SDRAM Controller Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_SDRAMC_DCR (*(vuint16 *)(&__IPSBAR[0x0040])) -#define MCF5282_SDRAMC_DACR0 (*(vuint32 *)(&__IPSBAR[0x0048])) -#define MCF5282_SDRAMC_DMR0 (*(vuint32 *)(&__IPSBAR[0x004C])) -#define MCF5282_SDRAMC_DACR1 (*(vuint32 *)(&__IPSBAR[0x0050])) -#define MCF5282_SDRAMC_DMR1 (*(vuint32 *)(&__IPSBAR[0x0054])) - -/* Bit level definitions and macros */ -#define MCF5282_SDRAMC_DCR_NAM (0x2000) -#define MCF5282_SDRAMC_DCR_COC (0x1000) -#define MCF5282_SDRAMC_DCR_IS (0x0800) -#define MCF5282_SDRAMC_DCR_RTIM_3 (0x0000) -#define MCF5282_SDRAMC_DCR_RTIM_6 (0x0200) -#define MCF5282_SDRAMC_DCR_RTIM_9 (0x0400) -#define MCF5282_SDRAMC_DCR_RC(x) ((x)&0x01FF) - -#define MCF5282_SDRAMC_DACR_BASE(x) ((x)&0xFFFC0000) -#define MCF5282_SDRAMC_DACR_RE (0x00008000) -#define MCF5282_SDRAMC_DACR_CASL(x) (((x)&0x03)<<12) -#define MCF5282_SDRAMC_DACR_CBM(x) (((x)&0x07)<<8) -#define MCF5282_SDRAMC_DACR_PS_32 (0x00000000) -#define MCF5282_SDRAMC_DACR_PS_8 (0x00000010) -#define MCF5282_SDRAMC_DACR_PS_16 (0x00000020) -#define MCF5282_SDRAMC_DACR_IMRS (0x00000040) -#define MCF5282_SDRAMC_DACR_IP (0x00000008) - -#define MCF5282_SDRAMC_DMR_BAM_4G (0xFFFC0000) -#define MCF5282_SDRAMC_DMR_BAM_2G (0x7FFC0000) -#define MCF5282_SDRAMC_DMR_BAM_1G (0x3FFC0000) -#define MCF5282_SDRAMC_DMR_BAM_1024M (0x3FFC0000) -#define MCF5282_SDRAMC_DMR_BAM_512M (0x1FFC0000) -#define MCF5282_SDRAMC_DMR_BAM_256M (0x0FFC0000) -#define MCF5282_SDRAMC_DMR_BAM_128M (0x07FC0000) -#define MCF5282_SDRAMC_DMR_BAM_64M (0x03FC0000) -#define MCF5282_SDRAMC_DMR_BAM_32M (0x01FC0000) -#define MCF5282_SDRAMC_DMR_BAM_16M (0x00FC0000) -#define MCF5282_SDRAMC_DMR_BAM_8M (0x007C0000) -#define MCF5282_SDRAMC_DMR_BAM_4M (0x003C0000) -#define MCF5282_SDRAMC_DMR_BAM_2M (0x001C0000) -#define MCF5282_SDRAMC_DMR_BAM_1M (0x000C0000) -#define MCF5282_SDRAMC_DMR_BAM_1024K (0x000C0000) -#define MCF5282_SDRAMC_DMR_BAM_512K (0x00040000) -#define MCF5282_SDRAMC_DMR_BAM_256K (0x00000000) -#define MCF5282_SDRAMC_DMR_WP (0x00000100) -#define MCF5282_SDRAMC_DMR_CI (0x00000040) -#define MCF5282_SDRAMC_DMR_AM (0x00000020) -#define MCF5282_SDRAMC_DMR_SC (0x00000010) -#define MCF5282_SDRAMC_DMR_SD (0x00000008) -#define MCF5282_SDRAMC_DMR_UC (0x00000004) -#define MCF5282_SDRAMC_DMR_UD (0x00000002) -#define MCF5282_SDRAMC_DMR_V (0x00000001) - -/********************************************************************* -* -* Chip Select Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_CS0_CSAR (*(vuint16 *)(&__IPSBAR[0x0080])) -#define MCF5282_CS0_CSMR (*(vuint32 *)(&__IPSBAR[0x0084])) -#define MCF5282_CS0_CSCR (*(vuint16 *)(&__IPSBAR[0x008A])) - -#define MCF5282_CS1_CSAR (*(vuint16 *)(&__IPSBAR[0x008C])) -#define MCF5282_CS1_CSMR (*(vuint32 *)(&__IPSBAR[0x0090])) -#define MCF5282_CS1_CSCR (*(vuint16 *)(&__IPSBAR[0x0096])) - -#define MCF5282_CS2_CSAR (*(vuint16 *)(&__IPSBAR[0x0098])) -#define MCF5282_CS2_CSMR (*(vuint32 *)(&__IPSBAR[0x009C])) -#define MCF5282_CS2_CSCR (*(vuint16 *)(&__IPSBAR[0x00A2])) - -#define MCF5282_CS3_CSAR (*(vuint16 *)(&__IPSBAR[0x00A4])) -#define MCF5282_CS3_CSMR (*(vuint32 *)(&__IPSBAR[0x00A8])) -#define MCF5282_CS3_CSCR (*(vuint16 *)(&__IPSBAR[0x00AE])) - -#define MCF5282_CS4_CSAR (*(vuint16 *)(&__IPSBAR[0x00B0])) -#define MCF5282_CS4_CSMR (*(vuint32 *)(&__IPSBAR[0x00B4])) -#define MCF5282_CS4_CSCR (*(vuint16 *)(&__IPSBAR[0x00BA])) - -#define MCF5282_CS5_CSAR (*(vuint16 *)(&__IPSBAR[0x00BC])) -#define MCF5282_CS5_CSMR (*(vuint32 *)(&__IPSBAR[0x00C0])) -#define MCF5282_CS5_CSCR (*(vuint16 *)(&__IPSBAR[0x00C6])) - -#define MCF5282_CS6_CSAR (*(vuint16 *)(&__IPSBAR[0x00C8])) -#define MCF5282_CS6_CSMR (*(vuint32 *)(&__IPSBAR[0x00CC])) -#define MCF5282_CS6_CSCR (*(vuint16 *)(&__IPSBAR[0x00D2])) - -#define MCF5282_CS_CSAR(x) (*(vuint16 *)(&__IPSBAR[0x0080+((x)*0x0C)])) -#define MCF5282_CS_CSMR(x) (*(vuint32 *)(&__IPSBAR[0x0084+((x)*0x0C)])) -#define MCF5282_CS_CSCR(x) (*(vuint16 *)(&__IPSBAR[0x008A+((x)*0x0C)])) - -/* Bit level definitions and macros */ -#define MCF5282_CS_CSAR_BA(a) (uint16)(((a)&0xFFFF0000)>>16) - -#define MCF5282_CS_CSMR_BAM_4G (0xFFFF0000) -#define MCF5282_CS_CSMR_BAM_2G (0x7FFF0000) -#define MCF5282_CS_CSMR_BAM_1G (0x3FFF0000) -#define MCF5282_CS_CSMR_BAM_1024M (0x3FFF0000) -#define MCF5282_CS_CSMR_BAM_512M (0x1FFF0000) -#define MCF5282_CS_CSMR_BAM_256M (0x0FFF0000) -#define MCF5282_CS_CSMR_BAM_128M (0x07FF0000) -#define MCF5282_CS_CSMR_BAM_64M (0x03FF0000) -#define MCF5282_CS_CSMR_BAM_32M (0x01FF0000) -#define MCF5282_CS_CSMR_BAM_16M (0x00FF0000) -#define MCF5282_CS_CSMR_BAM_8M (0x007F0000) -#define MCF5282_CS_CSMR_BAM_4M (0x003F0000) -#define MCF5282_CS_CSMR_BAM_2M (0x001F0000) -#define MCF5282_CS_CSMR_BAM_1M (0x000F0000) -#define MCF5282_CS_CSMR_BAM_1024K (0x000F0000) -#define MCF5282_CS_CSMR_BAM_512K (0x00070000) -#define MCF5282_CS_CSMR_BAM_256K (0x00030000) -#define MCF5282_CS_CSMR_BAM_128K (0x00010000) -#define MCF5282_CS_CSMR_BAM_64K (0x00000000) -#define MCF5282_CS_CSMR_WP (0x00000100) -#define MCF5282_CS_CSMR_AM (0x00000040) -#define MCF5282_CS_CSMR_CI (0x00000020) -#define MCF5282_CS_CSMR_SC (0x00000010) -#define MCF5282_CS_CSMR_SD (0x00000008) -#define MCF5282_CS_CSMR_UC (0x00000004) -#define MCF5282_CS_CSMR_UD (0x00000002) -#define MCF5282_CS_CSMR_V (0x00000001) - -#define MCF5282_CS_CSCR_WS(x) (((x)&0x0F)<<10) -#define MCF5282_CS_CSCR_AA (0x0100) -#define MCF5282_CS_CSCR_PS_8 (0x0040) -#define MCF5282_CS_CSCR_PS_16 (0x0080) -#define MCF5282_CS_CSCR_PS_32 (0x0000) -#define MCF5282_CS_CSCR_BEM (0x0020) -#define MCF5282_CS_CSCR_BSTR (0x0010) -#define MCF5282_CS_CSCR_BSTW (0x0008) - -/********************************************************************* -* -* Direct Memory Access (DMA) Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_DMA0_SAR (*(vuint32 *)(&__IPSBAR[0x0100])) -#define MCF5282_DMA0_DAR (*(vuint32 *)(&__IPSBAR[0x0104])) -#define MCF5282_DMA0_DCR (*(vuint32 *)(&__IPSBAR[0x0108])) -#define MCF5282_DMA0_BCR (*(vuint32 *)(&__IPSBAR[0x010C])) -#define MCF5282_DMA0_DSR (*(vuint8 *)(&__IPSBAR[0x0110])) - -#define MCF5282_DMA1_SAR (*(vuint32 *)(&__IPSBAR[0x0140])) -#define MCF5282_DMA1_DAR (*(vuint32 *)(&__IPSBAR[0x0144])) -#define MCF5282_DMA1_DCR (*(vuint32 *)(&__IPSBAR[0x0148])) -#define MCF5282_DMA1_BCR (*(vuint32 *)(&__IPSBAR[0x014C])) -#define MCF5282_DMA1_DSR (*(vuint8 *)(&__IPSBAR[0x0150])) - -#define MCF5282_DMA2_SAR (*(vuint32 *)(&__IPSBAR[0x0180])) -#define MCF5282_DMA2_DAR (*(vuint32 *)(&__IPSBAR[0x0184])) -#define MCF5282_DMA2_DCR (*(vuint32 *)(&__IPSBAR[0x0188])) -#define MCF5282_DMA2_BCR (*(vuint32 *)(&__IPSBAR[0x018C])) -#define MCF5282_DMA2_DSR (*(vuint8 *)(&__IPSBAR[0x0190])) - -#define MCF5282_DMA3_SAR (*(vuint32 *)(&__IPSBAR[0x01C0])) -#define MCF5282_DMA3_DAR (*(vuint32 *)(&__IPSBAR[0x01C4])) -#define MCF5282_DMA3_DCR (*(vuint32 *)(&__IPSBAR[0x01C8])) -#define MCF5282_DMA3_BCR (*(vuint32 *)(&__IPSBAR[0x01CC])) -#define MCF5282_DMA3_DSR (*(vuint8 *)(&__IPSBAR[0x01D0])) - -#define MCF5282_DMA_SAR(x) (*(vuint32 *)(&__IPSBAR[0x0100+((x)*0x40)])) -#define MCF5282_DMA_DAR(x) (*(vuint32 *)(&__IPSBAR[0x0104+((x)*0x40)])) -#define MCF5282_DMA_DCR(x) (*(vuint32 *)(&__IPSBAR[0x0108+((x)*0x40)])) -#define MCF5282_DMA_BCR(x) (*(vuint32 *)(&__IPSBAR[0x010C+((x)*0x40)])) -#define MCF5282_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x0110+((x)*0x40)])) - -/* Bit level definitions and macros */ -#define MCF5282_DMA_DCR_INT (0x80000000) -#define MCF5282_DMA_DCR_EEXT (0x40000000) -#define MCF5282_DMA_DCR_CS (0x20000000) -#define MCF5282_DMA_DCR_AA (0x10000000) -#define MCF5282_DMA_DCR_BWC_DMA (0x00000000) -#define MCF5282_DMA_DCR_BWC_512 (0x02000000) -#define MCF5282_DMA_DCR_BWC_1024 (0x04000000) -#define MCF5282_DMA_DCR_BWC_2048 (0x06000000) -#define MCF5282_DMA_DCR_BWC_4096 (0x08000000) -#define MCF5282_DMA_DCR_BWC_8192 (0x0A000000) -#define MCF5282_DMA_DCR_BWC_16384 (0x0C000000) -#define MCF5282_DMA_DCR_BWC_32768 (0x0E000000) -#define MCF5282_DMA_DCR_SINC (0x00400000) -#define MCF5282_DMA_DCR_SSIZE_LONG (0x00000000) -#define MCF5282_DMA_DCR_SSIZE_BYTE (0x00100000) -#define MCF5282_DMA_DCR_SSIZE_WORD (0x00200000) -#define MCF5282_DMA_DCR_SSIZE_LINE (0x00300000) -#define MCF5282_DMA_DCR_DINC (0x00080000) -#define MCF5282_DMA_DCR_DSIZE_LONG (0x00000000) -#define MCF5282_DMA_DCR_DSIZE_BYTE (0x00020000) -#define MCF5282_DMA_DCR_DSIZE_WORD (0x00040000) -#define MCF5282_DMA_DCR_START (0x00010000) -#define MCF5282_DMA_DCR_AT (0x00008000) - -#define MCF5282_DMA_DSR_CE (0x40) -#define MCF5282_DMA_DSR_BES (0x20) -#define MCF5282_DMA_DSR_BED (0x10) -#define MCF5282_DMA_DSR_REQ (0x04) -#define MCF5282_DMA_DSR_BSY (0x02) -#define MCF5282_DMA_DSR_DONE (0x01) - -/********************************************************************* -* -* Universal Asychronous Receiver/Transmitter (UART) Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_UART0_UMR (*(vuint8 *)(&__IPSBAR[0x0200])) -#define MCF5282_UART0_USR (*(vuint8 *)(&__IPSBAR[0x0204])) -#define MCF5282_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x0204])) -#define MCF5282_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x0208])) -#define MCF5282_UART0_URB (*(vuint8 *)(&__IPSBAR[0x020C])) -#define MCF5282_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x020C])) -#define MCF5282_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x0210])) -#define MCF5282_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x0210])) -#define MCF5282_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x0214])) -#define MCF5282_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x0214])) -#define MCF5282_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x0218])) -#define MCF5282_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x021C])) -#define MCF5282_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x0234])) -#define MCF5282_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x0238])) -#define MCF5282_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x023C])) - -#define MCF5282_UART1_UMR (*(vuint8 *)(&__IPSBAR[0x0240])) -#define MCF5282_UART1_USR (*(vuint8 *)(&__IPSBAR[0x0244])) -#define MCF5282_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x0244])) -#define MCF5282_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x0248])) -#define MCF5282_UART1_URB (*(vuint8 *)(&__IPSBAR[0x024C])) -#define MCF5282_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x024C])) -#define MCF5282_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x0250])) -#define MCF5282_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x0250])) -#define MCF5282_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x0254])) -#define MCF5282_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x0254])) -#define MCF5282_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x0258])) -#define MCF5282_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x025C])) -#define MCF5282_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x0274])) -#define MCF5282_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x0278])) -#define MCF5282_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x027C])) - -#define MCF5282_UART2_UMR (*(vuint8 *)(&__IPSBAR[0x0280])) -#define MCF5282_UART2_USR (*(vuint8 *)(&__IPSBAR[0x0284])) -#define MCF5282_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x0284])) -#define MCF5282_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x0288])) -#define MCF5282_UART2_URB (*(vuint8 *)(&__IPSBAR[0x028C])) -#define MCF5282_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x028C])) -#define MCF5282_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x0290])) -#define MCF5282_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x0290])) -#define MCF5282_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x0294])) -#define MCF5282_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x0294])) -#define MCF5282_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x0298])) -#define MCF5282_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x029C])) -#define MCF5282_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x02B4])) -#define MCF5282_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x02B8])) -#define MCF5282_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x02BC])) - -#define MCF5282_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x0200+((x)*0x40)])) -#define MCF5282_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x0204+((x)*0x40)])) -#define MCF5282_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x0204+((x)*0x40)])) -#define MCF5282_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x0208+((x)*0x40)])) -#define MCF5282_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x020C+((x)*0x40)])) -#define MCF5282_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x020C+((x)*0x40)])) -#define MCF5282_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x0210+((x)*0x40)])) -#define MCF5282_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x0210+((x)*0x40)])) -#define MCF5282_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x0214+((x)*0x40)])) -#define MCF5282_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x0214+((x)*0x40)])) -#define MCF5282_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x0218+((x)*0x40)])) -#define MCF5282_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x021C+((x)*0x40)])) -#define MCF5282_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x0234+((x)*0x40)])) -#define MCF5282_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x0238+((x)*0x40)])) -#define MCF5282_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x023C+((x)*0x40)])) - -/* Bit level definitions and macros */ -#define MCF5282_UART_UMR1_RXRTS (0x80) -#define MCF5282_UART_UMR1_RXIRQ (0x40) -#define MCF5282_UART_UMR1_ERR (0x20) -#define MCF5282_UART_UMR1_PM_MULTI_ADDR (0x1C) -#define MCF5282_UART_UMR1_PM_MULTI_DATA (0x18) -#define MCF5282_UART_UMR1_PM_NONE (0x10) -#define MCF5282_UART_UMR1_PM_FORCE_HI (0x0C) -#define MCF5282_UART_UMR1_PM_FORCE_LO (0x08) -#define MCF5282_UART_UMR1_PM_ODD (0x04) -#define MCF5282_UART_UMR1_PM_EVEN (0x00) -#define MCF5282_UART_UMR1_BC_5 (0x00) -#define MCF5282_UART_UMR1_BC_6 (0x01) -#define MCF5282_UART_UMR1_BC_7 (0x02) -#define MCF5282_UART_UMR1_BC_8 (0x03) - -#define MCF5282_UART_UMR2_CM_NORMAL (0x00) -#define MCF5282_UART_UMR2_CM_ECHO (0x40) -#define MCF5282_UART_UMR2_CM_LOCAL_LOOP (0x80) -#define MCF5282_UART_UMR2_CM_REMOTE_LOOP (0xC0) -#define MCF5282_UART_UMR2_TXRTS (0x20) -#define MCF5282_UART_UMR2_TXCTS (0x10) -#define MCF5282_UART_UMR2_STOP_BITS_1 (0x07) -#define MCF5282_UART_UMR2_STOP_BITS_15 (0x08) -#define MCF5282_UART_UMR2_STOP_BITS_2 (0x0F) -#define MCF5282_UART_UMR2_STOP_BITS(a) ((a)&0x0f) - -#define MCF5282_UART_USR_RB (0x80) -#define MCF5282_UART_USR_FE (0x40) -#define MCF5282_UART_USR_PE (0x20) -#define MCF5282_UART_USR_OE (0x10) -#define MCF5282_UART_USR_TXEMP (0x08) -#define MCF5282_UART_USR_TXRDY (0x04) -#define MCF5282_UART_USR_FFULL (0x02) -#define MCF5282_UART_USR_RXRDY (0x01) - -#define MCF5282_UART_UCSR_RCS_SYS_CLK (0xD0) -#define MCF5282_UART_UCSR_RCS_DTIN16 (0xE0) -#define MCF5282_UART_UCSR_RCS_DTIN (0xF0) -#define MCF5282_UART_UCSR_TCS_SYS_CLK (0x0D) -#define MCF5282_UART_UCSR_TCS_DTIN16 (0x0E) -#define MCF5282_UART_UCSR_TCS_DTIN (0x0F) - -#define MCF5282_UART_UCR_NONE (0x00) -#define MCF5282_UART_UCR_STOP_BREAK (0x70) -#define MCF5282_UART_UCR_START_BREAK (0x60) -#define MCF5282_UART_UCR_RESET_BKCHGINT (0x50) -#define MCF5282_UART_UCR_RESET_ERROR (0x40) -#define MCF5282_UART_UCR_RESET_TX (0x30) -#define MCF5282_UART_UCR_RESET_RX (0x20) -#define MCF5282_UART_UCR_RESET_MR (0x10) -#define MCF5282_UART_UCR_TX_DISABLED (0x08) -#define MCF5282_UART_UCR_TX_ENABLED (0x04) -#define MCF5282_UART_UCR_RX_DISABLED (0x02) -#define MCF5282_UART_UCR_RX_ENABLED (0x01) - -#define MCF5282_UART_UIPCR_COS (0x10) -#define MCF5282_UART_UIPCR_CTS (0x01) - -#define MCF5282_UART_UACR_IEC (0x01) - -#define MCF5282_UART_UISR_COS (0x80) -#define MCF5282_UART_UISR_ABC (0x40) -#define MCF5282_UART_UISR_RXFIFO (0x20) -#define MCF5282_UART_UISR_TXFIFO (0x10) -#define MCF5282_UART_UISR_RXFTO (0x08) -#define MCF5282_UART_UISR_DB (0x04) -#define MCF5282_UART_UISR_RXRDY (0x02) -#define MCF5282_UART_UISR_TXRDY (0x01) - -#define MCF5282_UART_UIMR_COS (0x80) -#define MCF5282_UART_UIMR_DB (0x04) -#define MCF5282_UART_UIMR_FFULL (0x02) -#define MCF5282_UART_UIMR_TXRDY (0x01) - -#define MCF5282_UART_UIP_CTS (0x01) - -#define MCF5282_UART_UOP_RTS (0x01) - -/********************************************************************* -* -* Inter-IC (I2C) Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_I2C_I2ADR (*(vuint8 *)(&__IPSBAR[0x0300])) -#define MCF5282_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x0304])) -#define MCF5282_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x0308])) -#define MCF5282_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x030C])) -#define MCF5282_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x0310])) - -/* Bit level definitions and macros */ -#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) - -#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F)) - -#define MCF5282_I2C_I2CR_IEN (0x80) -#define MCF5282_I2C_I2CR_IIEN (0x40) -#define MCF5282_I2C_I2CR_MSTA (0x20) -#define MCF5282_I2C_I2CR_MTX (0x10) -#define MCF5282_I2C_I2CR_TXAK (0x08) -#define MCF5282_I2C_I2CR_RSTA (0x04) - -#define MCF5282_I2C_I2SR_ICF (0x80) -#define MCF5282_I2C_I2SR_IAAS (0x40) -#define MCF5282_I2C_I2SR_IBB (0x20) -#define MCF5282_I2C_I2SR_IAL (0x10) -#define MCF5282_I2C_I2SR_SRW (0x04) -#define MCF5282_I2C_I2SR_IIF (0x02) -#define MCF5282_I2C_I2SR_RXAK (0x01) - -/********************************************************************* -* -* Queued Serial Peripheral Interface (QSPI) Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_QSPI_QMR (*(vuint16 *)(&__IPSBAR[0x0340])) -#define MCF5282_QSPI_QDLYR (*(vuint16 *)(&__IPSBAR[0x0344])) -#define MCF5282_QSPI_QWR (*(vuint16 *)(&__IPSBAR[0x0348])) -#define MCF5282_QSPI_QIR (*(vuint16 *)(&__IPSBAR[0x034C])) -#define MCF5282_QSPI_QAR (*(vuint16 *)(&__IPSBAR[0x0350])) -#define MCF5282_QSPI_QDR (*(vuint16 *)(&__IPSBAR[0x0354])) -#define MCF5282_QSPI_QCR (*(vuint16 *)(&__IPSBAR[0x0354])) - -/* Bit level definitions and macros */ -#define MCF5282_QSPI_QMR_MSTR (0x8000) -#define MCF5282_QSPI_QMR_DOHIE (0x4000) -#define MCF5282_QSPI_QMR_BITS_16 (0x0000) -#define MCF5282_QSPI_QMR_BITS_8 (0x2000) -#define MCF5282_QSPI_QMR_BITS_9 (0x2400) -#define MCF5282_QSPI_QMR_BITS_10 (0x2800) -#define MCF5282_QSPI_QMR_BITS_11 (0x2C00) -#define MCF5282_QSPI_QMR_BITS_12 (0x3000) -#define MCF5282_QSPI_QMR_BITS_13 (0x3400) -#define MCF5282_QSPI_QMR_BITS_14 (0x3800) -#define MCF5282_QSPI_QMR_BITS_15 (0x3C00) -#define MCF5282_QSPI_QMR_CPOL (0x0200) -#define MCF5282_QSPI_QMR_CPHA (0x0100) -#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF)) - -#define MCF5282_QSPI_QDLYR_SPE (0x8000) -#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF)) - -#define MCF5282_QSPI_QWR_HALT (0x8000) -#define MCF5282_QSPI_QWR_WREN (0x4000) -#define MCF5282_QSPI_QWR_WRTO (0x2000) -#define MCF5282_QSPI_QWR_CSIV (0x1000) -#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4) -#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F)) - -#define MCF5282_QSPI_QIR_WCEFB (0x8000) -#define MCF5282_QSPI_QIR_ABRTB (0x4000) -#define MCF5282_QSPI_QIR_ABRTL (0x1000) -#define MCF5282_QSPI_QIR_WCEFE (0x0800) -#define MCF5282_QSPI_QIR_ABRTE (0x0400) -#define MCF5282_QSPI_QIR_SPIFE (0x0100) -#define MCF5282_QSPI_QIR_WCEF (0x0008) -#define MCF5282_QSPI_QIR_ABRT (0x0004) -#define MCF5282_QSPI_QIR_SPIF (0x0001) - -#define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F)) - -#define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00)) - -#define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8) -#define MCF5282_QSPI_QCR_CONT (0x8000) -#define MCF5282_QSPI_QCR_BITSE (0x4000) -#define MCF5282_QSPI_QCR_DT (0x2000) -#define MCF5282_QSPI_QCR_DSCK (0x1000) -#define MCF5282_QSPI_QCR_CS(x) (((x)&0x000F)<<8) - -/********************************************************************* -* -* DMA Timer Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_TIMER0_DTMR (*(vuint16 *)(&__IPSBAR[0x0400])) -#define MCF5282_TIMER0_DTXMR (*(vuint8 *)(&__IPSBAR[0x0402])) -#define MCF5282_TIMER0_DTER (*(vuint8 *)(&__IPSBAR[0x0403])) -#define MCF5282_TIMER0_DTRR (*(vuint32 *)(&__IPSBAR[0x0404])) -#define MCF5282_TIMER0_DTCR (*(vuint32 *)(&__IPSBAR[0x0408])) -#define MCF5282_TIMER0_DTCN (*(vuint32 *)(&__IPSBAR[0x040C])) - -#define MCF5282_TIMER1_DTMR (*(vuint16 *)(&__IPSBAR[0x0440])) -#define MCF5282_TIMER1_DTXMR (*(vuint8 *)(&__IPSBAR[0x0442])) -#define MCF5282_TIMER1_DTER (*(vuint8 *)(&__IPSBAR[0x0443])) -#define MCF5282_TIMER1_DTRR (*(vuint32 *)(&__IPSBAR[0x0444])) -#define MCF5282_TIMER1_DTCR (*(vuint32 *)(&__IPSBAR[0x0448])) -#define MCF5282_TIMER1_DTCN (*(vuint32 *)(&__IPSBAR[0x044C])) - -#define MCF5282_TIMER2_DTMR (*(vuint16 *)(&__IPSBAR[0x0480])) -#define MCF5282_TIMER2_DTXMR (*(vuint8 *)(&__IPSBAR[0x0482])) -#define MCF5282_TIMER2_DTER (*(vuint8 *)(&__IPSBAR[0x0483])) -#define MCF5282_TIMER2_DTRR (*(vuint32 *)(&__IPSBAR[0x0484])) -#define MCF5282_TIMER2_DTCR (*(vuint32 *)(&__IPSBAR[0x0488])) -#define MCF5282_TIMER2_DTCN (*(vuint32 *)(&__IPSBAR[0x048C])) - -#define MCF5282_TIMER3_DTMR (*(vuint16 *)(&__IPSBAR[0x04C0])) -#define MCF5282_TIMER3_DTXMR (*(vuint8 *)(&__IPSBAR[0x04C2])) -#define MCF5282_TIMER3_DTER (*(vuint8 *)(&__IPSBAR[0x04C3])) -#define MCF5282_TIMER3_DTRR (*(vuint32 *)(&__IPSBAR[0x04C4])) -#define MCF5282_TIMER3_DTCR (*(vuint32 *)(&__IPSBAR[0x04C8])) -#define MCF5282_TIMER3_DTCN (*(vuint32 *)(&__IPSBAR[0x04CC])) - -#define MCF5282_TIMER_DTMR(x) (*(vuint16 *)(&__IPSBAR[0x0400+((x)*0x40)])) -#define MCF5282_TIMER_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x0402+((x)*0x40)])) -#define MCF5282_TIMER_DTER(x) (*(vuint8 *)(&__IPSBAR[0x0403+((x)*0x40)])) -#define MCF5282_TIMER_DTRR(x) (*(vuint32 *)(&__IPSBAR[0x0404+((x)*0x40)])) -#define MCF5282_TIMER_DTCR(x) (*(vuint32 *)(&__IPSBAR[0x0408+((x)*0x40)])) -#define MCF5282_TIMER_DTCN(x) (*(vuint32 *)(&__IPSBAR[0x040C+((x)*0x40)])) - -/* Bit level definitions and macros */ -#define MCF5282_TIMER_DTMR_PS(a) (((a)&0x00FF)<<8) -#define MCF5282_TIMER_DTMR_CE_ANY (0x00C0) -#define MCF5282_TIMER_DTMR_CE_FALL (0x0080) -#define MCF5282_TIMER_DTMR_CE_RISE (0x0040) -#define MCF5282_TIMER_DTMR_CE_NONE (0x0000) -#define MCF5282_TIMER_DTMR_OM (0x0020) -#define MCF5282_TIMER_DTMR_ORRI (0x0010) -#define MCF5282_TIMER_DTMR_FRR (0x0008) -#define MCF5282_TIMER_DTMR_CLK_DTIN (0x0006) -#define MCF5282_TIMER_DTMR_CLK_DIV16 (0x0004) -#define MCF5282_TIMER_DTMR_CLK_DIV1 (0x0002) -#define MCF5282_TIMER_DTMR_CLK_STOP (0x0000) -#define MCF5282_TIMER_DTMR_RST (0x0001) - -#define MCF5282_TIMER_DTXMR_DMAEN (0x80) -#define MCF5282_TIMER_DTXMR_MODE16 (0x01) - -#define MCF5282_TIMER_DTER_REF (0x02) -#define MCF5282_TIMER_DTER_CAP (0x01) - -/********************************************************************* -* -* Interrupt Controller (INTC) Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_INTC0_IPRH (*(vuint32 *)(&__IPSBAR[0x0C00])) -#define MCF5282_INTC0_IPRL (*(vuint32 *)(&__IPSBAR[0x0C04])) -#define MCF5282_INTC0_IMRH (*(vuint32 *)(&__IPSBAR[0x0C08])) -#define MCF5282_INTC0_IMRL (*(vuint32 *)(&__IPSBAR[0x0C0C])) -#define MCF5282_INTC0_INTFRCH (*(vuint32 *)(&__IPSBAR[0x0C10])) -#define MCF5282_INTC0_INTFRCL (*(vuint32 *)(&__IPSBAR[0x0C14])) -#define MCF5282_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0x0C18])) -#define MCF5282_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0x0C19])) -#define MCF5282_INTC0_ICR1 (*(vuint8 *)(&__IPSBAR[0x0C41])) -#define MCF5282_INTC0_ICR2 (*(vuint8 *)(&__IPSBAR[0x0C42])) -#define MCF5282_INTC0_ICR3 (*(vuint8 *)(&__IPSBAR[0x0C43])) -#define MCF5282_INTC0_ICR4 (*(vuint8 *)(&__IPSBAR[0x0C44])) -#define MCF5282_INTC0_ICR5 (*(vuint8 *)(&__IPSBAR[0x0C45])) -#define MCF5282_INTC0_ICR6 (*(vuint8 *)(&__IPSBAR[0x0C46])) -#define MCF5282_INTC0_ICR7 (*(vuint8 *)(&__IPSBAR[0x0C47])) -#define MCF5282_INTC0_ICR8 (*(vuint8 *)(&__IPSBAR[0x0C48])) -#define MCF5282_INTC0_ICR9 (*(vuint8 *)(&__IPSBAR[0x0C49])) -#define MCF5282_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0x0C4A])) -#define MCF5282_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0x0C4B])) -#define MCF5282_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0x0C4C])) -#define MCF5282_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0x0C4D])) -#define MCF5282_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0x0C4E])) -#define MCF5282_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0x0C4F])) -#define MCF5282_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0x0C51])) -#define MCF5282_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0x0C52])) -#define MCF5282_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0x0C53])) -#define MCF5282_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0x0C54])) -#define MCF5282_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0x0C55])) -#define MCF5282_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0x0C56])) -#define MCF5282_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0x0C57])) -#define MCF5282_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0x0C58])) -#define MCF5282_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0x0C59])) -#define MCF5282_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0x0C5A])) -#define MCF5282_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0x0C5B])) -#define MCF5282_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0x0C5C])) -#define MCF5282_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0x0C5D])) -#define MCF5282_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0x0C5E])) -#define MCF5282_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0x0C5F])) -#define MCF5282_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0x0C60])) -#define MCF5282_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0x0C61])) -#define MCF5282_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0x0C62])) -#define MCF5282_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0x0C63])) -#define MCF5282_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0x0C64])) -#define MCF5282_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0x0C65])) -#define MCF5282_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0x0C66])) -#define MCF5282_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0x0C67])) -#define MCF5282_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0x0C68])) -#define MCF5282_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0x0C69])) -#define MCF5282_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0x0C6A])) -#define MCF5282_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0x0C6B])) -#define MCF5282_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0x0C6C])) -#define MCF5282_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0x0C6D])) -#define MCF5282_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0x0C6E])) -#define MCF5282_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0x0C6F])) -#define MCF5282_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0x0C70])) -#define MCF5282_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0x0C71])) -#define MCF5282_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0x0C72])) -#define MCF5282_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0x0C73])) -#define MCF5282_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0x0C74])) -#define MCF5282_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0x0C75])) -#define MCF5282_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0x0C76])) -#define MCF5282_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0x0C77])) -#define MCF5282_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0x0C78])) -#define MCF5282_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0x0C79])) -#define MCF5282_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0x0C7A])) -#define MCF5282_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0x0C7B])) -#define MCF5282_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0x0C7C])) -#define MCF5282_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0x0C7D])) -#define MCF5282_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0x0C7E])) -#define MCF5282_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0x0CE0])) -#define MCF5282_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0x0CE4])) -#define MCF5282_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0x0CE8])) -#define MCF5282_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0x0CEC])) -#define MCF5282_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0x0CF0])) -#define MCF5282_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0x0CF4])) -#define MCF5282_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0x0CF8])) -#define MCF5282_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0x0CFC])) - -#define MCF5282_INTC1_IPRH (*(vuint32 *)(&__IPSBAR[0x0D00])) -#define MCF5282_INTC1_IPRL (*(vuint32 *)(&__IPSBAR[0x0D04])) -#define MCF5282_INTC1_IMRH (*(vuint32 *)(&__IPSBAR[0x0D08])) -#define MCF5282_INTC1_IMRL (*(vuint32 *)(&__IPSBAR[0x0D0C])) -#define MCF5282_INTC1_INTFRCH (*(vuint32 *)(&__IPSBAR[0x0D10])) -#define MCF5282_INTC1_INTFRCL (*(vuint32 *)(&__IPSBAR[0x0D14])) -#define MCF5282_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0x0D18])) -#define MCF5282_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0x0D19])) -#define MCF5282_INTC1_ICR08 (*(vuint8 *)(&__IPSBAR[0x0D48])) -#define MCF5282_INTC1_ICR09 (*(vuint8 *)(&__IPSBAR[0x0D49])) -#define MCF5282_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0x0D4A])) -#define MCF5282_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0x0D4B])) -#define MCF5282_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0x0D4C])) -#define MCF5282_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0x0D4D])) -#define MCF5282_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0x0D4E])) -#define MCF5282_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0x0D4F])) -#define MCF5282_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0x0D50])) -#define MCF5282_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0x0D51])) -#define MCF5282_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0x0D52])) -#define MCF5282_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0x0D53])) -#define MCF5282_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0x0D54])) -#define MCF5282_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0x0D55])) -#define MCF5282_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0x0D56])) -#define MCF5282_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0x0D57])) -#define MCF5282_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0x0D58])) -#define MCF5282_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0x0D59])) -#define MCF5282_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0x0D5A])) -#define MCF5282_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0x0DE0])) -#define MCF5282_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0x0DE4])) -#define MCF5282_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0x0DE8])) -#define MCF5282_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0x0DEC])) -#define MCF5282_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0x0DF0])) -#define MCF5282_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0x0DF4])) -#define MCF5282_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0x0DF8])) -#define MCF5282_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0x0DFC])) - -/* Bit level definitions and macros */ -#define MCF5282_INTC_IPRH_INT63 (0x80000000) -#define MCF5282_INTC_IPRH_INT62 (0x40000000) -#define MCF5282_INTC_IPRH_INT61 (0x20000000) -#define MCF5282_INTC_IPRH_INT60 (0x10000000) -#define MCF5282_INTC_IPRH_INT59 (0x08000000) -#define MCF5282_INTC_IPRH_INT58 (0x04000000) -#define MCF5282_INTC_IPRH_INT57 (0x02000000) -#define MCF5282_INTC_IPRH_INT56 (0x01000000) -#define MCF5282_INTC_IPRH_INT55 (0x00800000) -#define MCF5282_INTC_IPRH_INT54 (0x00400000) -#define MCF5282_INTC_IPRH_INT53 (0x00200000) -#define MCF5282_INTC_IPRH_INT52 (0x00100000) -#define MCF5282_INTC_IPRH_INT51 (0x00080000) -#define MCF5282_INTC_IPRH_INT50 (0x00040000) -#define MCF5282_INTC_IPRH_INT49 (0x00020000) -#define MCF5282_INTC_IPRH_INT48 (0x00010000) -#define MCF5282_INTC_IPRH_INT47 (0x00008000) -#define MCF5282_INTC_IPRH_INT46 (0x00004000) -#define MCF5282_INTC_IPRH_INT45 (0x00002000) -#define MCF5282_INTC_IPRH_INT44 (0x00001000) -#define MCF5282_INTC_IPRH_INT43 (0x00000800) -#define MCF5282_INTC_IPRH_INT42 (0x00000400) -#define MCF5282_INTC_IPRH_INT41 (0x00000200) -#define MCF5282_INTC_IPRH_INT40 (0x00000100) -#define MCF5282_INTC_IPRH_INT39 (0x00000080) -#define MCF5282_INTC_IPRH_INT38 (0x00000040) -#define MCF5282_INTC_IPRH_INT37 (0x00000020) -#define MCF5282_INTC_IPRH_INT36 (0x00000010) -#define MCF5282_INTC_IPRH_INT35 (0x00000008) -#define MCF5282_INTC_IPRH_INT34 (0x00000004) -#define MCF5282_INTC_IPRH_INT33 (0x00000002) -#define MCF5282_INTC_IPRH_INT32 (0x00000001) - -#define MCF5282_INTC_IPRL_INT31 (0x80000000) -#define MCF5282_INTC_IPRL_INT30 (0x40000000) -#define MCF5282_INTC_IPRL_INT29 (0x20000000) -#define MCF5282_INTC_IPRL_INT28 (0x10000000) -#define MCF5282_INTC_IPRL_INT27 (0x08000000) -#define MCF5282_INTC_IPRL_INT26 (0x04000000) -#define MCF5282_INTC_IPRL_INT25 (0x02000000) -#define MCF5282_INTC_IPRL_INT24 (0x01000000) -#define MCF5282_INTC_IPRL_INT23 (0x00800000) -#define MCF5282_INTC_IPRL_INT22 (0x00400000) -#define MCF5282_INTC_IPRL_INT21 (0x00200000) -#define MCF5282_INTC_IPRL_INT20 (0x00100000) -#define MCF5282_INTC_IPRL_INT19 (0x00080000) -#define MCF5282_INTC_IPRL_INT18 (0x00040000) -#define MCF5282_INTC_IPRL_INT17 (0x00020000) -#define MCF5282_INTC_IPRL_INT16 (0x00010000) -#define MCF5282_INTC_IPRL_INT15 (0x00008000) -#define MCF5282_INTC_IPRL_INT14 (0x00004000) -#define MCF5282_INTC_IPRL_INT13 (0x00002000) -#define MCF5282_INTC_IPRL_INT12 (0x00001000) -#define MCF5282_INTC_IPRL_INT11 (0x00000800) -#define MCF5282_INTC_IPRL_INT10 (0x00000400) -#define MCF5282_INTC_IPRL_INT9 (0x00000200) -#define MCF5282_INTC_IPRL_INT8 (0x00000100) -#define MCF5282_INTC_IPRL_INT7 (0x00000080) -#define MCF5282_INTC_IPRL_INT6 (0x00000040) -#define MCF5282_INTC_IPRL_INT5 (0x00000020) -#define MCF5282_INTC_IPRL_INT4 (0x00000010) -#define MCF5282_INTC_IPRL_INT3 (0x00000008) -#define MCF5282_INTC_IPRL_INT2 (0x00000004) -#define MCF5282_INTC_IPRL_INT1 (0x00000002) - -#define MCF5282_INTC_IMRH_INT63 (0x80000000) -#define MCF5282_INTC_IMRH_INT62 (0x40000000) -#define MCF5282_INTC_IMRH_INT61 (0x20000000) -#define MCF5282_INTC_IMRH_INT60 (0x10000000) -#define MCF5282_INTC_IMRH_INT59 (0x08000000) -#define MCF5282_INTC_IMRH_INT58 (0x04000000) -#define MCF5282_INTC_IMRH_INT57 (0x02000000) -#define MCF5282_INTC_IMRH_INT56 (0x01000000) -#define MCF5282_INTC_IMRH_INT55 (0x00800000) -#define MCF5282_INTC_IMRH_INT54 (0x00400000) -#define MCF5282_INTC_IMRH_INT53 (0x00200000) -#define MCF5282_INTC_IMRH_INT52 (0x00100000) -#define MCF5282_INTC_IMRH_INT51 (0x00080000) -#define MCF5282_INTC_IMRH_INT50 (0x00040000) -#define MCF5282_INTC_IMRH_INT49 (0x00020000) -#define MCF5282_INTC_IMRH_INT48 (0x00010000) -#define MCF5282_INTC_IMRH_INT47 (0x00008000) -#define MCF5282_INTC_IMRH_INT46 (0x00004000) -#define MCF5282_INTC_IMRH_INT45 (0x00002000) -#define MCF5282_INTC_IMRH_INT44 (0x00001000) -#define MCF5282_INTC_IMRH_INT43 (0x00000800) -#define MCF5282_INTC_IMRH_INT42 (0x00000400) -#define MCF5282_INTC_IMRH_INT41 (0x00000200) -#define MCF5282_INTC_IMRH_INT40 (0x00000100) -#define MCF5282_INTC_IMRH_INT39 (0x00000080) -#define MCF5282_INTC_IMRH_INT38 (0x00000040) -#define MCF5282_INTC_IMRH_INT37 (0x00000020) -#define MCF5282_INTC_IMRH_INT36 (0x00000010) -#define MCF5282_INTC_IMRH_INT35 (0x00000008) -#define MCF5282_INTC_IMRH_INT34 (0x00000004) -#define MCF5282_INTC_IMRH_INT33 (0x00000002) -#define MCF5282_INTC_IMRH_INT32 (0x00000001) - -#define MCF5282_INTC_IMRL_INT31 (0x80000000) -#define MCF5282_INTC_IMRL_INT30 (0x40000000) -#define MCF5282_INTC_IMRL_INT29 (0x20000000) -#define MCF5282_INTC_IMRL_INT28 (0x10000000) -#define MCF5282_INTC_IMRL_INT27 (0x08000000) -#define MCF5282_INTC_IMRL_INT26 (0x04000000) -#define MCF5282_INTC_IMRL_INT25 (0x02000000) -#define MCF5282_INTC_IMRL_INT24 (0x01000000) -#define MCF5282_INTC_IMRL_INT23 (0x00800000) -#define MCF5282_INTC_IMRL_INT22 (0x00400000) -#define MCF5282_INTC_IMRL_INT21 (0x00200000) -#define MCF5282_INTC_IMRL_INT20 (0x00100000) -#define MCF5282_INTC_IMRL_INT19 (0x00080000) -#define MCF5282_INTC_IMRL_INT18 (0x00040000) -#define MCF5282_INTC_IMRL_INT17 (0x00020000) -#define MCF5282_INTC_IMRL_INT16 (0x00010000) -#define MCF5282_INTC_IMRL_INT15 (0x00008000) -#define MCF5282_INTC_IMRL_INT14 (0x00004000) -#define MCF5282_INTC_IMRL_INT13 (0x00002000) -#define MCF5282_INTC_IMRL_INT12 (0x00001000) -#define MCF5282_INTC_IMRL_INT11 (0x00000800) -#define MCF5282_INTC_IMRL_INT10 (0x00000400) -#define MCF5282_INTC_IMRL_INT9 (0x00000200) -#define MCF5282_INTC_IMRL_INT8 (0x00000100) -#define MCF5282_INTC_IMRL_INT7 (0x00000080) -#define MCF5282_INTC_IMRL_INT6 (0x00000040) -#define MCF5282_INTC_IMRL_INT5 (0x00000020) -#define MCF5282_INTC_IMRL_INT4 (0x00000010) -#define MCF5282_INTC_IMRL_INT3 (0x00000008) -#define MCF5282_INTC_IMRL_INT2 (0x00000004) -#define MCF5282_INTC_IMRL_INT1 (0x00000002) -#define MCF5282_INTC_IMRL_MASKALL (0x00000001) - -#define MCF5282_INTC_INTFRCH_INT63 (0x80000000) -#define MCF5282_INTC_INTFRCH_INT62 (0x40000000) -#define MCF5282_INTC_INTFRCH_INT61 (0x20000000) -#define MCF5282_INTC_INTFRCH_INT60 (0x10000000) -#define MCF5282_INTC_INTFRCH_INT59 (0x08000000) -#define MCF5282_INTC_INTFRCH_INT58 (0x04000000) -#define MCF5282_INTC_INTFRCH_INT57 (0x02000000) -#define MCF5282_INTC_INTFRCH_INT56 (0x01000000) -#define MCF5282_INTC_INTFRCH_INT55 (0x00800000) -#define MCF5282_INTC_INTFRCH_INT54 (0x00400000) -#define MCF5282_INTC_INTFRCH_INT53 (0x00200000) -#define MCF5282_INTC_INTFRCH_INT52 (0x00100000) -#define MCF5282_INTC_INTFRCH_INT51 (0x00080000) -#define MCF5282_INTC_INTFRCH_INT50 (0x00040000) -#define MCF5282_INTC_INTFRCH_INT49 (0x00020000) -#define MCF5282_INTC_INTFRCH_INT48 (0x00010000) -#define MCF5282_INTC_INTFRCH_INT47 (0x00008000) -#define MCF5282_INTC_INTFRCH_INT46 (0x00004000) -#define MCF5282_INTC_INTFRCH_INT45 (0x00002000) -#define MCF5282_INTC_INTFRCH_INT44 (0x00001000) -#define MCF5282_INTC_INTFRCH_INT43 (0x00000800) -#define MCF5282_INTC_INTFRCH_INT42 (0x00000400) -#define MCF5282_INTC_INTFRCH_INT41 (0x00000200) -#define MCF5282_INTC_INTFRCH_INT40 (0x00000100) -#define MCF5282_INTC_INTFRCH_INT39 (0x00000080) -#define MCF5282_INTC_INTFRCH_INT38 (0x00000040) -#define MCF5282_INTC_INTFRCH_INT37 (0x00000020) -#define MCF5282_INTC_INTFRCH_INT36 (0x00000010) -#define MCF5282_INTC_INTFRCH_INT35 (0x00000008) -#define MCF5282_INTC_INTFRCH_INT34 (0x00000004) -#define MCF5282_INTC_INTFRCH_INT33 (0x00000002) -#define MCF5282_INTC_INTFRCH_INT32 (0x00000001) - -#define MCF5282_INTC_INTFRCL_INT31 (0x80000000) -#define MCF5282_INTC_INTFRCL_INT30 (0x40000000) -#define MCF5282_INTC_INTFRCL_INT29 (0x20000000) -#define MCF5282_INTC_INTFRCL_INT28 (0x10000000) -#define MCF5282_INTC_INTFRCL_INT27 (0x08000000) -#define MCF5282_INTC_INTFRCL_INT26 (0x04000000) -#define MCF5282_INTC_INTFRCL_INT25 (0x02000000) -#define MCF5282_INTC_INTFRCL_INT24 (0x01000000) -#define MCF5282_INTC_INTFRCL_INT23 (0x00800000) -#define MCF5282_INTC_INTFRCL_INT22 (0x00400000) -#define MCF5282_INTC_INTFRCL_INT21 (0x00200000) -#define MCF5282_INTC_INTFRCL_INT20 (0x00100000) -#define MCF5282_INTC_INTFRCL_INT19 (0x00080000) -#define MCF5282_INTC_INTFRCL_INT18 (0x00040000) -#define MCF5282_INTC_INTFRCL_INT17 (0x00020000) -#define MCF5282_INTC_INTFRCL_INT16 (0x00010000) -#define MCF5282_INTC_INTFRCL_INT15 (0x00008000) -#define MCF5282_INTC_INTFRCL_INT14 (0x00004000) -#define MCF5282_INTC_INTFRCL_INT13 (0x00002000) -#define MCF5282_INTC_INTFRCL_INT12 (0x00001000) -#define MCF5282_INTC_INTFRCL_INT11 (0x00000800) -#define MCF5282_INTC_INTFRCL_INT10 (0x00000400) -#define MCF5282_INTC_INTFRCL_INT9 (0x00000200) -#define MCF5282_INTC_INTFRCL_INT8 (0x00000100) -#define MCF5282_INTC_INTFRCL_INT7 (0x00000080) -#define MCF5282_INTC_INTFRCL_INT6 (0x00000040) -#define MCF5282_INTC_INTFRCL_INT5 (0x00000020) -#define MCF5282_INTC_INTFRCL_INT4 (0x00000010) -#define MCF5282_INTC_INTFRCL_INT3 (0x00000008) -#define MCF5282_INTC_INTFRCL_INT2 (0x00000004) -#define MCF5282_INTC_INTFRCL_INT1 (0x00000002) - -#define MCF5282_INTC_IRLR_IRQ7 (0x80) -#define MCF5282_INTC_IRLR_IRQ6 (0x40) -#define MCF5282_INTC_IRLR_IRQ5 (0x20) -#define MCF5282_INTC_IRLR_IRQ4 (0x10) -#define MCF5282_INTC_IRLR_IRQ3 (0x08) -#define MCF5282_INTC_IRLR_IRQ2 (0x04) -#define MCF5282_INTC_IRLR_IRQ1 (0x02) - -#define MCF5282_INTC_ICR_IL(x) (((x)&0x07)<<3) -#define MCF5282_INTC_ICR_IP(x) (((x)&0x07)<<0) - -/********************************************************************* -* -* Global Interrupt Acknowledge Cycle (GIAC) Registers -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_GIAC_GSWIACK (*(vuint8 *)(&__IPSBAR[0x0FE0])) -#define MCF5282_GIAC_GL1IACK (*(vuint8 *)(&__IPSBAR[0x0FE4])) -#define MCF5282_GIAC_GL2IACK (*(vuint8 *)(&__IPSBAR[0x0FE8])) -#define MCF5282_GIAC_GL3IACK (*(vuint8 *)(&__IPSBAR[0x0FEC])) -#define MCF5282_GIAC_GL4IACK (*(vuint8 *)(&__IPSBAR[0x0FF0])) -#define MCF5282_GIAC_GL5IACK (*(vuint8 *)(&__IPSBAR[0x0FF4])) -#define MCF5282_GIAC_GL6IACK (*(vuint8 *)(&__IPSBAR[0x0FF8])) -#define MCF5282_GIAC_GL7IACK (*(vuint8 *)(&__IPSBAR[0x0FFC])) - -/* Bit level definitions and macros */ - -/* To do - add bit level definintions */ - -/********************************************************************* -* -* Fast Ethernet Controller (FEC) Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_FEC_EIR (*(vuint32 *)(&__IPSBAR[0x1004])) -#define MCF5282_FEC_EIMR (*(vuint32 *)(&__IPSBAR[0x1008])) -#define MCF5282_FEC_RDAR (*(vuint32 *)(&__IPSBAR[0x1010])) -#define MCF5282_FEC_TDAR (*(vuint32 *)(&__IPSBAR[0x1014])) -#define MCF5282_FEC_ECR (*(vuint32 *)(&__IPSBAR[0x1024])) -#define MCF5282_FEC_MMFR (*(vuint32 *)(&__IPSBAR[0x1040])) -#define MCF5282_FEC_MSCR (*(vuint32 *)(&__IPSBAR[0x1044])) -#define MCF5282_FEC_MIBC (*(vuint32 *)(&__IPSBAR[0x1064])) -#define MCF5282_FEC_RCR (*(vuint32 *)(&__IPSBAR[0x1084])) -#define MCF5282_FEC_TCR (*(vuint32 *)(&__IPSBAR[0x10C4])) -#define MCF5282_FEC_PALR (*(vuint32 *)(&__IPSBAR[0x10E4])) -#define MCF5282_FEC_PAUR (*(vuint32 *)(&__IPSBAR[0x10E8])) -#define MCF5282_FEC_OPD (*(vuint32 *)(&__IPSBAR[0x10EC])) -#define MCF5282_FEC_IAUR (*(vuint32 *)(&__IPSBAR[0x1118])) -#define MCF5282_FEC_IALR (*(vuint32 *)(&__IPSBAR[0x111C])) -#define MCF5282_FEC_GAUR (*(vuint32 *)(&__IPSBAR[0x1120])) -#define MCF5282_FEC_GALR (*(vuint32 *)(&__IPSBAR[0x1124])) -#define MCF5282_FEC_TFWR (*(vuint32 *)(&__IPSBAR[0x1144])) -#define MCF5282_FEC_FRBR (*(vuint32 *)(&__IPSBAR[0x114C])) -#define MCF5282_FEC_FRSR (*(vuint32 *)(&__IPSBAR[0x1150])) -#define MCF5282_FEC_ERDSR (*(vuint32 *)(&__IPSBAR[0x1180])) -#define MCF5282_FEC_ETDSR (*(vuint32 *)(&__IPSBAR[0x1184])) -#define MCF5282_FEC_EMRBR (*(vuint32 *)(&__IPSBAR[0x1188])) - -#define MCF5282_FEC_RMON_T_DROP (*(vuint32 *)(&__IPSBAR[0x1200])) -#define MCF5282_FEC_RMON_T_PACKETS (*(vuint32 *)(&__IPSBAR[0x1204])) -#define MCF5282_FEC_RMON_T_BC_PKT (*(vuint32 *)(&__IPSBAR[0x1208])) -#define MCF5282_FEC_RMON_T_MC_PKT (*(vuint32 *)(&__IPSBAR[0x120C])) -#define MCF5282_FEC_RMON_T_CRC_ALIGN (*(vuint32 *)(&__IPSBAR[0x1210])) -#define MCF5282_FEC_RMON_T_UNDERSIZE (*(vuint32 *)(&__IPSBAR[0x1214])) -#define MCF5282_FEC_RMON_T_OVERSIZE (*(vuint32 *)(&__IPSBAR[0x1218])) -#define MCF5282_FEC_RMON_T_FRAG (*(vuint32 *)(&__IPSBAR[0x121C])) -#define MCF5282_FEC_RMON_T_JAB (*(vuint32 *)(&__IPSBAR[0x1220])) -#define MCF5282_FEC_RMON_T_COL (*(vuint32 *)(&__IPSBAR[0x1224])) -#define MCF5282_FEC_RMON_T_P64 (*(vuint32 *)(&__IPSBAR[0x1228])) -#define MCF5282_FEC_RMON_T_P65TO127 (*(vuint32 *)(&__IPSBAR[0x122C])) -#define MCF5282_FEC_RMON_T_P128TO255 (*(vuint32 *)(&__IPSBAR[0x1230])) -#define MCF5282_FEC_RMON_T_P256TO511 (*(vuint32 *)(&__IPSBAR[0x1234])) -#define MCF5282_FEC_RMON_T_P512TO1023 (*(vuint32 *)(&__IPSBAR[0x1238])) -#define MCF5282_FEC_RMON_T_P1024TO2047 (*(vuint32 *)(&__IPSBAR[0x123C])) -#define MCF5282_FEC_RMON_T_P_GTE2048 (*(vuint32 *)(&__IPSBAR[0x1240])) -#define MCF5282_FEC_RMON_T_OCTETS (*(vuint32 *)(&__IPSBAR[0x1244])) -#define MCF5282_FEC_IEEE_T_DROP (*(vuint32 *)(&__IPSBAR[0x1248])) -#define MCF5282_FEC_IEEE_T_FRAME_OK (*(vuint32 *)(&__IPSBAR[0x124C])) -#define MCF5282_FEC_IEEE_T_1COL (*(vuint32 *)(&__IPSBAR[0x1250])) -#define MCF5282_FEC_IEEE_T_MCOL (*(vuint32 *)(&__IPSBAR[0x1254])) -#define MCF5282_FEC_IEEE_T_DEF (*(vuint32 *)(&__IPSBAR[0x1258])) -#define MCF5282_FEC_IEEE_T_LCOL (*(vuint32 *)(&__IPSBAR[0x125C])) -#define MCF5282_FEC_IEEE_T_EXCOL (*(vuint32 *)(&__IPSBAR[0x1260])) -#define MCF5282_FEC_IEEE_T_MACERR (*(vuint32 *)(&__IPSBAR[0x1264])) -#define MCF5282_FEC_IEEE_T_CSERR (*(vuint32 *)(&__IPSBAR[0x1268])) -#define MCF5282_FEC_IEEE_T_SQE (*(vuint32 *)(&__IPSBAR[0x126C])) -#define MCF5282_FEC_IEEE_T_FDXFC (*(vuint32 *)(&__IPSBAR[0x1270])) -#define MCF5282_FEC_IEEE_T_OCTETS_OK (*(vuint32 *)(&__IPSBAR[0x1274])) -#define MCF5282_FEC_RMON_R_PACKETS (*(vuint32 *)(&__IPSBAR[0x1284])) -#define MCF5282_FEC_RMON_R_BC_PKT (*(vuint32 *)(&__IPSBAR[0x1288])) -#define MCF5282_FEC_RMON_R_MC_PKT (*(vuint32 *)(&__IPSBAR[0x128C])) -#define MCF5282_FEC_RMON_R_CRC_ALIGN (*(vuint32 *)(&__IPSBAR[0x1290])) -#define MCF5282_FEC_RMON_R_UNDERSIZE (*(vuint32 *)(&__IPSBAR[0x1294])) -#define MCF5282_FEC_RMON_R_OVERSIZE (*(vuint32 *)(&__IPSBAR[0x1298])) -#define MCF5282_FEC_RMON_R_FRAG (*(vuint32 *)(&__IPSBAR[0x129C])) -#define MCF5282_FEC_RMON_R_JAB (*(vuint32 *)(&__IPSBAR[0x12A0])) -#define MCF5282_FEC_RMON_R_RESVD_0 (*(vuint32 *)(&__IPSBAR[0x12A4])) -#define MCF5282_FEC_RMON_R_P64 (*(vuint32 *)(&__IPSBAR[0x12A8])) -#define MCF5282_FEC_RMON_R_P65T0127 (*(vuint32 *)(&__IPSBAR[0x12AC])) -#define MCF5282_FEC_RMON_R_P128TO255 (*(vuint32 *)(&__IPSBAR[0x12B0])) -#define MCF5282_FEC_RMON_R_P256TO511 (*(vuint32 *)(&__IPSBAR[0x12B4])) -#define MCF5282_FEC_RMON_R_P512TO1023 (*(vuint32 *)(&__IPSBAR[0x12B8])) -#define MCF5282_FEC_RMON_R_P1024TO2047 (*(vuint32 *)(&__IPSBAR[0x12BC])) -#define MCF5282_FEC_RMON_R_GTE2048 (*(vuint32 *)(&__IPSBAR[0x12C0])) -#define MCF5282_FEC_RMON_R_OCTETS (*(vuint32 *)(&__IPSBAR[0x12C4])) -#define MCF5282_FEC_IEEE_R_DROP (*(vuint32 *)(&__IPSBAR[0x12C8])) -#define MCF5282_FEC_IEEE_R_FRAME_OK (*(vuint32 *)(&__IPSBAR[0x12CC])) -#define MCF5282_FEC_IEEE_R_CRC (*(vuint32 *)(&__IPSBAR[0x12D0])) -#define MCF5282_FEC_IEEE_R_ALIGN (*(vuint32 *)(&__IPSBAR[0x12D4])) -#define MCF5282_FEC_IEEE_R_MACERR (*(vuint32 *)(&__IPSBAR[0x12D8])) -#define MCF5282_FEC_IEEE_R_FDXFC (*(vuint32 *)(&__IPSBAR[0x12DC])) -#define MCF5282_FEC_IEEE_R_OCTETS_OK (*(vuint32 *)(&__IPSBAR[0x12E0])) - -/* Bit level definitions and macros */ -#define MCF5282_FEC_EIR_HBERR (0x80000000) -#define MCF5282_FEC_EIR_BABR (0x40000000) -#define MCF5282_FEC_EIR_BABT (0x20000000) -#define MCF5282_FEC_EIR_GRA (0x10000000) -#define MCF5282_FEC_EIR_TXF (0x08000000) -#define MCF5282_FEC_EIR_TXB (0x04000000) -#define MCF5282_FEC_EIR_RXF (0x02000000) -#define MCF5282_FEC_EIR_RXB (0x01000000) -#define MCF5282_FEC_EIR_MII (0x00800000) -#define MCF5282_FEC_EIR_EBERR (0x00400000) -#define MCF5282_FEC_EIR_LC (0x00200000) -#define MCF5282_FEC_EIR_RL (0x00100000) -#define MCF5282_FEC_EIR_UN (0x00080000) - -#define MCF5282_FEC_EIMR_HBERR (0x80000000) -#define MCF5282_FEC_EIMR_BABR (0x40000000) -#define MCF5282_FEC_EIMR_BABT (0x20000000) -#define MCF5282_FEC_EIMR_GRA (0x10000000) -#define MCF5282_FEC_EIMR_TXF (0x08000000) -#define MCF5282_FEC_EIMR_TXB (0x04000000) -#define MCF5282_FEC_EIMR_RXF (0x02000000) -#define MCF5282_FEC_EIMR_RXB (0x01000000) -#define MCF5282_FEC_EIMR_MII (0x00800000) -#define MCF5282_FEC_EIMR_EBERR (0x00400000) -#define MCF5282_FEC_EIMR_LC (0x00200000) -#define MCF5282_FEC_EIMR_RL (0x00100000) -#define MCF5282_FEC_EIMR_UN (0x00080000) - -#define MCF5282_FEC_RDAR_R_DES_ACTIVE (0x01000000) - -#define MCF5282_FEC_TDAR_X_DES_ACTIVE (0x01000000) - -#define MCF5282_FEC_ECR_ETHER_EN (0x00000002) -#define MCF5282_FEC_ECR_RESET (0x00000001) - -#define MCF5282_FEC_MMFR_ST (0x40000000) -#define MCF5282_FEC_MMFR_OP_RD (0x20000000) -#define MCF5282_FEC_MMFR_OP_WR (0x10000000) -#define MCF5282_FEC_MMFR_PA(x) (((x)&0x1F)<<23) -#define MCF5282_FEC_MMFR_RA(x) (((x)&0x1F)<<18) -#define MCF5282_FEC_MMFR_TA (0x00020000) -#define MCF5282_FEC_MMFR_DATA(x) (((x)&0xFFFF)) - -#define MCF5282_FEC_MSCR_DIS_PREAMBLE (0x00000008) -#define MCF5282_FEC_MSCR_MII_SPEED(x) (((x)&0x1F)<<1) - -#define MCF5282_FEC_MIBC_MIB_DISABLE (0x80000000) -#define MCF5282_FEC_MIBC_MIB_IDLE (0x40000000) - -#define MCF5282_FEC_RCR_MAX_FL(x) (((x)&0x07FF)<<16) -#define MCF5282_FEC_RCR_FCE (0x00000020) -#define MCF5282_FEC_RCR_BC_REJ (0x00000010) -#define MCF5282_FEC_RCR_PROM (0x00000008) -#define MCF5282_FEC_RCR_MII_MODE (0x00000004) -#define MCF5282_FEC_RCR_DRT (0x00000002) -#define MCF5282_FEC_RCR_LOOP (0x00000001) - -#define MCF5282_FEC_TCR_RFC_PAUSE (0x00000010) -#define MCF5282_FEC_TCR_TFC_PAUSE (0x00000008) -#define MCF5282_FEC_TCR_FDEN (0x00000004) -#define MCF5282_FEC_TCR_HBC (0x00000002) -#define MCF5282_FEC_TCR_GTS (0x00000001) - -#define MCF5282_FEC_PALR_BYTE0(x) (((x)&0xFF)<<24) -#define MCF5282_FEC_PALR_BYTE1(x) (((x)&0xFF)<<16) -#define MCF5282_FEC_PALR_BYTE2(x) (((x)&0xFF)<<8) -#define MCF5282_FEC_PALR_BYTE3(x) (((x)&0xFF)) - -#define MCF5282_FEC_PAUR_BYTE4(x) (((x)&0xFF)<<24) -#define MCF5282_FEC_PAUR_BYTE5(x) (((x)&0xFF)<<16) - -#define MCF5282_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)) - -#define MCF5282_FEC_TFWR_X_WMRK_64 (0x00000001) -#define MCF5282_FEC_TFWR_X_WMRK_128 (0x00000002) -#define MCF5282_FEC_TFWR_X_WMRK_192 (0x00000003) - -#define MCF5282_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4) - -#define MCF5282_FEC_TxBD_R 0x8000 -#define MCF5282_FEC_TxBD_BUSY 0x4000 -#define MCF5282_FEC_TxBD_TO1 0x4000 -#define MCF5282_FEC_TxBD_W 0x2000 -#define MCF5282_FEC_TxBD_TO2 0x1000 -#define MCF5282_FEC_TxBD_FIRST 0x1000 -#define MCF5282_FEC_TxBD_L 0x0800 -#define MCF5282_FEC_TxBD_TC 0x0400 -#define MCF5282_FEC_TxBD_DEF 0x0200 -#define MCF5282_FEC_TxBD_HB 0x0100 -#define MCF5282_FEC_TxBD_LC 0x0080 -#define MCF5282_FEC_TxBD_RL 0x0040 -#define MCF5282_FEC_TxBD_UN 0x0002 -#define MCF5282_FEC_TxBD_CSL 0x0001 - -#define MCF5282_FEC_RxBD_E 0x8000 -#define MCF5282_FEC_RxBD_INUSE 0x4000 -#define MCF5282_FEC_RxBD_R01 0x4000 -#define MCF5282_FEC_RxBD_W 0x2000 -#define MCF5282_FEC_RxBD_R02 0x1000 -#define MCF5282_FEC_RxBD_L 0x0800 -#define MCF5282_FEC_RxBD_M 0x0100 -#define MCF5282_FEC_RxBD_BC 0x0080 -#define MCF5282_FEC_RxBD_MC 0x0040 -#define MCF5282_FEC_RxBD_LG 0x0020 -#define MCF5282_FEC_RxBD_NO 0x0010 -#define MCF5282_FEC_RxBD_CR 0x0004 -#define MCF5282_FEC_RxBD_OV 0x0002 -#define MCF5282_FEC_RxBD_TR 0x0001 - -/********************************************************************* -* -* General Purpose I/O (GPIO) Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_GPIO_PORTA (*(vuint8 *)(&__IPSBAR[0x100000])) -#define MCF5282_GPIO_PORTB (*(vuint8 *)(&__IPSBAR[0x100001])) -#define MCF5282_GPIO_PORTC (*(vuint8 *)(&__IPSBAR[0x100002])) -#define MCF5282_GPIO_PORTD (*(vuint8 *)(&__IPSBAR[0x100003])) -#define MCF5282_GPIO_PORTE (*(vuint8 *)(&__IPSBAR[0x100004])) -#define MCF5282_GPIO_PORTF (*(vuint8 *)(&__IPSBAR[0x100005])) -#define MCF5282_GPIO_PORTG (*(vuint8 *)(&__IPSBAR[0x100006])) -#define MCF5282_GPIO_PORTH (*(vuint8 *)(&__IPSBAR[0x100007])) -#define MCF5282_GPIO_PORTJ (*(vuint8 *)(&__IPSBAR[0x100008])) -#define MCF5282_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100009])) -#define MCF5282_GPIO_PORTEH (*(vuint8 *)(&__IPSBAR[0x10000A])) -#define MCF5282_GPIO_PORTEL (*(vuint8 *)(&__IPSBAR[0x10000B])) -#define MCF5282_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000C])) -#define MCF5282_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000D])) -#define MCF5282_GPIO_PORTSD (*(vuint8 *)(&__IPSBAR[0x10000E])) -#define MCF5282_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F])) -#define MCF5282_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010])) -#define MCF5282_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011])) - -#define MCF5282_GPIO_DDRA (*(vuint8 *)(&__IPSBAR[0x100014])) -#define MCF5282_GPIO_DDRB (*(vuint8 *)(&__IPSBAR[0x100015])) -#define MCF5282_GPIO_DDRC (*(vuint8 *)(&__IPSBAR[0x100016])) -#define MCF5282_GPIO_DDRD (*(vuint8 *)(&__IPSBAR[0x100017])) -#define MCF5282_GPIO_DDRE (*(vuint8 *)(&__IPSBAR[0x100018])) -#define MCF5282_GPIO_DDRF (*(vuint8 *)(&__IPSBAR[0x100019])) -#define MCF5282_GPIO_DDRG (*(vuint8 *)(&__IPSBAR[0x10001A])) -#define MCF5282_GPIO_DDRH (*(vuint8 *)(&__IPSBAR[0x10001B])) -#define MCF5282_GPIO_DDRJ (*(vuint8 *)(&__IPSBAR[0x10001C])) -#define MCF5282_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10001D])) -#define MCF5282_GPIO_DDREH (*(vuint8 *)(&__IPSBAR[0x10001E])) -#define MCF5282_GPIO_DDREL (*(vuint8 *)(&__IPSBAR[0x10001F])) -#define MCF5282_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100020])) -#define MCF5282_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100021])) -#define MCF5282_GPIO_DDRSD (*(vuint8 *)(&__IPSBAR[0x100022])) -#define MCF5282_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100023])) -#define MCF5282_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100024])) -#define MCF5282_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100025])) - -#define MCF5282_GPIO_PORTAP (*(vuint8 *)(&__IPSBAR[0x100028])) -#define MCF5282_GPIO_PORTBP (*(vuint8 *)(&__IPSBAR[0x100029])) -#define MCF5282_GPIO_PORTCP (*(vuint8 *)(&__IPSBAR[0x10002A])) -#define MCF5282_GPIO_PORTDP (*(vuint8 *)(&__IPSBAR[0x10002B])) -#define MCF5282_GPIO_PORTEP (*(vuint8 *)(&__IPSBAR[0x10002C])) -#define MCF5282_GPIO_PORTFP (*(vuint8 *)(&__IPSBAR[0x10002D])) -#define MCF5282_GPIO_PORTGP (*(vuint8 *)(&__IPSBAR[0x10002E])) -#define MCF5282_GPIO_PORTHP (*(vuint8 *)(&__IPSBAR[0x10002F])) -#define MCF5282_GPIO_PORTJP (*(vuint8 *)(&__IPSBAR[0x100030])) -#define MCF5282_GPIO_PORTDDP (*(vuint8 *)(&__IPSBAR[0x100031])) -#define MCF5282_GPIO_PORTEHP (*(vuint8 *)(&__IPSBAR[0x100032])) -#define MCF5282_GPIO_PORTELP (*(vuint8 *)(&__IPSBAR[0x100033])) -#define MCF5282_GPIO_PORTASP (*(vuint8 *)(&__IPSBAR[0x100034])) -#define MCF5282_GPIO_PORTQSP (*(vuint8 *)(&__IPSBAR[0x100035])) -#define MCF5282_GPIO_PORTSDP (*(vuint8 *)(&__IPSBAR[0x100036])) -#define MCF5282_GPIO_PORTTCP (*(vuint8 *)(&__IPSBAR[0x100037])) -#define MCF5282_GPIO_PORTTDP (*(vuint8 *)(&__IPSBAR[0x100038])) -#define MCF5282_GPIO_PORTUAP (*(vuint8 *)(&__IPSBAR[0x100039])) - -#define MCF5282_GPIO_SETA (*(vuint8 *)(&__IPSBAR[0x100028])) -#define MCF5282_GPIO_SETB (*(vuint8 *)(&__IPSBAR[0x100029])) -#define MCF5282_GPIO_SETC (*(vuint8 *)(&__IPSBAR[0x10002A])) -#define MCF5282_GPIO_SETD (*(vuint8 *)(&__IPSBAR[0x10002B])) -#define MCF5282_GPIO_SETE (*(vuint8 *)(&__IPSBAR[0x10002C])) -#define MCF5282_GPIO_SETF (*(vuint8 *)(&__IPSBAR[0x10002D])) -#define MCF5282_GPIO_SETG (*(vuint8 *)(&__IPSBAR[0x10002E])) -#define MCF5282_GPIO_SETH (*(vuint8 *)(&__IPSBAR[0x10002F])) -#define MCF5282_GPIO_SETJ (*(vuint8 *)(&__IPSBAR[0x100030])) -#define MCF5282_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100031])) -#define MCF5282_GPIO_SETEH (*(vuint8 *)(&__IPSBAR[0x100032])) -#define MCF5282_GPIO_SETEL (*(vuint8 *)(&__IPSBAR[0x100033])) -#define MCF5282_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x100034])) -#define MCF5282_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x100035])) -#define MCF5282_GPIO_SETSD (*(vuint8 *)(&__IPSBAR[0x100036])) -#define MCF5282_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x100037])) -#define MCF5282_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100038])) -#define MCF5282_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100039])) - -#define MCF5282_GPIO_CLRA (*(vuint8 *)(&__IPSBAR[0x10003C])) -#define MCF5282_GPIO_CLRB (*(vuint8 *)(&__IPSBAR[0x10003D])) -#define MCF5282_GPIO_CLRC (*(vuint8 *)(&__IPSBAR[0x10003E])) -#define MCF5282_GPIO_CLRD (*(vuint8 *)(&__IPSBAR[0x10003F])) -#define MCF5282_GPIO_CLRE (*(vuint8 *)(&__IPSBAR[0x100040])) -#define MCF5282_GPIO_CLRF (*(vuint8 *)(&__IPSBAR[0x100041])) -#define MCF5282_GPIO_CLRG (*(vuint8 *)(&__IPSBAR[0x100042])) -#define MCF5282_GPIO_CLRH (*(vuint8 *)(&__IPSBAR[0x100043])) -#define MCF5282_GPIO_CLRJ (*(vuint8 *)(&__IPSBAR[0x100044])) -#define MCF5282_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x100045])) -#define MCF5282_GPIO_CLREH (*(vuint8 *)(&__IPSBAR[0x100046])) -#define MCF5282_GPIO_CLREL (*(vuint8 *)(&__IPSBAR[0x100047])) -#define MCF5282_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100048])) -#define MCF5282_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100049])) -#define MCF5282_GPIO_CLRSD (*(vuint8 *)(&__IPSBAR[0x10004A])) -#define MCF5282_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x10004B])) -#define MCF5282_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x10004C])) -#define MCF5282_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x10004D])) - -#define MCF5282_GPIO_PBCDPAR (*(vuint8 *)(&__IPSBAR[0x100050])) -#define MCF5282_GPIO_PFPAR (*(vuint8 *)(&__IPSBAR[0x100051])) -#define MCF5282_GPIO_PEPAR (*(vuint16 *)(&__IPSBAR[0x100052])) -#define MCF5282_GPIO_PJPAR (*(vuint8 *)(&__IPSBAR[0x100054])) -#define MCF5282_GPIO_PSDPAR (*(vuint8 *)(&__IPSBAR[0x100055])) -#define MCF5282_GPIO_PASPAR (*(vuint16 *)(&__IPSBAR[0x100056])) -#define MCF5282_GPIO_PEHLPAR (*(vuint8 *)(&__IPSBAR[0x100058])) -#define MCF5282_GPIO_PQSPAR (*(vuint8 *)(&__IPSBAR[0x100059])) -#define MCF5282_GPIO_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10005A])) -#define MCF5282_GPIO_PTDPAR (*(vuint8 *)(&__IPSBAR[0x10005B])) -#define MCF5282_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x10005C])) - -/* Bit level definitions and macros */ -#define MCF5282_GPIO_PORTx7 (0x80) -#define MCF5282_GPIO_PORTx6 (0x40) -#define MCF5282_GPIO_PORTx5 (0x20) -#define MCF5282_GPIO_PORTx4 (0x10) -#define MCF5282_GPIO_PORTx3 (0x08) -#define MCF5282_GPIO_PORTx2 (0x04) -#define MCF5282_GPIO_PORTx1 (0x02) -#define MCF5282_GPIO_PORTx0 (0x01) -#define MCF5282_GPIO_PORTx(x) (0x01<<(x)) - -#define MCF5282_GPIO_DDRx7 (0x80) -#define MCF5282_GPIO_DDRx6 (0x40) -#define MCF5282_GPIO_DDRx5 (0x20) -#define MCF5282_GPIO_DDRx4 (0x10) -#define MCF5282_GPIO_DDRx3 (0x08) -#define MCF5282_GPIO_DDRx2 (0x04) -#define MCF5282_GPIO_DDRx1 (0x02) -#define MCF5282_GPIO_DDRx0 (0x01) -#define MCF5282_GPIO_DDRx(x) (0x01<<(x)) - -#define MCF5282_GPIO_PORTxP7 (0x80) -#define MCF5282_GPIO_PORTxP6 (0x40) -#define MCF5282_GPIO_PORTxP5 (0x20) -#define MCF5282_GPIO_PORTxP4 (0x10) -#define MCF5282_GPIO_PORTxP3 (0x08) -#define MCF5282_GPIO_PORTxP2 (0x04) -#define MCF5282_GPIO_PORTxP1 (0x02) -#define MCF5282_GPIO_PORTxP0 (0x01) -#define MCF5282_GPIO_PORTxP(x) (0x01<<(x)) - -#define MCF5282_GPIO_SETx7 (0x80) -#define MCF5282_GPIO_SETx6 (0x40) -#define MCF5282_GPIO_SETx5 (0x20) -#define MCF5282_GPIO_SETx4 (0x10) -#define MCF5282_GPIO_SETx3 (0x08) -#define MCF5282_GPIO_SETx2 (0x04) -#define MCF5282_GPIO_SETx1 (0x02) -#define MCF5282_GPIO_SETx0 (0x01) -#define MCF5282_GPIO_SETx(x) (0x01<<(x)) - -#define MCF5282_GPIO_CLRx7 (0x80) -#define MCF5282_GPIO_CLRx6 (0x40) -#define MCF5282_GPIO_CLRx5 (0x20) -#define MCF5282_GPIO_CLRx4 (0x10) -#define MCF5282_GPIO_CLRx3 (0x08) -#define MCF5282_GPIO_CLRx2 (0x04) -#define MCF5282_GPIO_CLRx1 (0x02) -#define MCF5282_GPIO_CLRx0 (0x01) -#define MCF5282_GPIO_CLRx(x) (0x01<<(x)) - -#define MCF5282_GPIO_PBCDPAR_PBPA (0x80) -#define MCF5282_GPIO_PBCDPAR_PCDPA (0x40) - -#define MCF5282_GPIO_PEPAR_PEPA7 (0x4000) -#define MCF5282_GPIO_PEPAR_PEPA6 (0x1000) -#define MCF5282_GPIO_PEPAR_PEPA5 (0x0400) -#define MCF5282_GPIO_PEPAR_PEPA4 (0x0100) -#define MCF5282_GPIO_PEPAR_PEPA3 (0x0040) -#define MCF5282_GPIO_PEPAR_PEPA2 (0x0010) -#define MCF5282_GPIO_PEPAR_PEPA1(x) (((x)&0x3)<<2) -#define MCF5282_GPIO_PEPAR_PEPA0(x) (((x)&0x3)) - -#define MCF5282_GPIO_PFPAR_PFPA7 (0x80) -#define MCF5282_GPIO_PFPAR_PFPA6 (0x40) -#define MCF5282_GPIO_PFPAR_PFPA5 (0x20) - -#define MCF5282_GPIO_PJPAR_PJPA7 (0x80) -#define MCF5282_GPIO_PJPAR_PJPA6 (0x40) -#define MCF5282_GPIO_PJPAR_PJPA5 (0x20) -#define MCF5282_GPIO_PJPAR_PJPA4 (0x10) -#define MCF5282_GPIO_PJPAR_PJPA3 (0x08) -#define MCF5282_GPIO_PJPAR_PJPA2 (0x04) -#define MCF5282_GPIO_PJPAR_PJPA1 (0x02) -#define MCF5282_GPIO_PJPAR_PJPA0 (0x01) -#define MCF5282_GPIO_PJPAR_PJPA(x) (0x01<<(x)) - -#define MCF5282_GPIO_PSDPAR_PSDPA (0x80) - -#define MCF5282_GPIO_PASPAR_PASPA5(x) (((x)&0x3)<<10) -#define MCF5282_GPIO_PASPAR_PASPA4(x) (((x)&0x3)<<8) -#define MCF5282_GPIO_PASPAR_PASPA3(x) (((x)&0x3)<<6) -#define MCF5282_GPIO_PASPAR_PASPA2(x) (((x)&0x3)<<4) -#define MCF5282_GPIO_PASPAR_PASPA1(x) (((x)&0x3)<<2) -#define MCF5282_GPIO_PASPAR_PASPA0(x) (((x)&0x3)) - -#define MCF5282_GPIO_PEHLPAR_PEHPA (0x80) -#define MCF5282_GPIO_PEHLPAR_PELPA (0x40) - -#define MCF5282_GPIO_PQSPAR_PQSPA6 (0x40) -#define MCF5282_GPIO_PQSPAR_PQSPA5 (0x20) -#define MCF5282_GPIO_PQSPAR_PQSPA4 (0x10) -#define MCF5282_GPIO_PQSPAR_PQSPA3 (0x08) -#define MCF5282_GPIO_PQSPAR_PQSPA2 (0x04) -#define MCF5282_GPIO_PQSPAR_PQSPA1 (0x02) -#define MCF5282_GPIO_PQSPAR_PQSPA0 (0x01) -#define MCF5282_GPIO_PQSPAR_PQSPA(x) (0x01<<(x)) - -#define MCF5282_GPIO_PTCPAR_PTCPA3(x) (((x)&0x3)<<6) -#define MCF5282_GPIO_PTCPAR_PTCPA2(x) (((x)&0x3)<<4) -#define MCF5282_GPIO_PTCPAR_PTCPA1(x) (((x)&0x3)<<2) -#define MCF5282_GPIO_PTCPAR_PTCPA0(x) (((x)&0x3)) - -#define MCF5282_GPIO_PTDPAR_PTDPA3(x) (((x)&0x3)<<6) -#define MCF5282_GPIO_PTDPAR_PTDPA2(x) (((x)&0x3)<<4) -#define MCF5282_GPIO_PTDPAR_PTDPA1(x) (((x)&0x3)<<2) -#define MCF5282_GPIO_PTDPAR_PTDPA0(x) (((x)&0x3)) - -#define MCF5282_GPIO_PUAPAR_PUAPA3 (0x08) -#define MCF5282_GPIO_PUAPAR_PUAPA2 (0x04) -#define MCF5282_GPIO_PUAPAR_PUAPA1 (0x02) -#define MCF5282_GPIO_PUAPAR_PUAPA0 (0x01) - -/********************************************************************* -* -* Reset Controller Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_RESET_RCR (*(vuint8 *)(&__IPSBAR[0x110000])) -#define MCF5282_RESET_RSR (*(vuint8 *)(&__IPSBAR[0x110001])) - -/* Bit level definitions and macros */ -#define MCF5282_RESET_RCR_SOFTRST (0x80) -#define MCF5282_RESET_RCR_FRCRSTOUT (0x40) -#define MCF5282_RESET_RCR_LVDF (0x10) -#define MCF5282_RESET_RCR_LVDIE (0x08) -#define MCF5282_RESET_RCR_LVDRE (0x04) -#define MCF5282_RESET_RCR_LVDE (0x01) - -#define MCF5282_RESET_RSR_LVD (0x40) -#define MCF5282_RESET_RSR_SOFT (0x20) -#define MCF5282_RESET_RSR_WDR (0x10) -#define MCF5282_RESET_RSR_POR (0x08) -#define MCF5282_RESET_RSR_EXT (0x04) -#define MCF5282_RESET_RSR_LOC (0x02) -#define MCF5282_RESET_RSR_LOL (0x01) - -/********************************************************************* -* -* Chip Configuration Module (CCM) -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_CCM_CCR (*(vuint16 *)(&__IPSBAR[0x110004])) -#define MCF5282_CCM_RCON (*(vuint16 *)(&__IPSBAR[0x110008])) -#define MCF5282_CCM_CIR (*(vuint16 *)(&__IPSBAR[0x11000A])) - -/* Bit level definitions and macros */ -#define MCF5282_CCM_CCR_LOAD (0x8000) -#define MCF5282_CCM_CCR_MODE(x) (((x)&0x0007)<<8) -#define MCF5282_CCM_CCR_SZEN (0x0040) -#define MCF5282_CCM_CCR_PSTEN (0x0020) -#define MCF5282_CCM_CCR_BME (0x0008) -#define MCF5282_CCM_CCR_BMT(x) (((x)&0x0007)) - -/********************************************************************* -* -* Power Management Module (PMM) -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) -#define MCF5282_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) - -/* Bit level definitions and macros */ -#define MCF5282_PMM_LPICR_ENBSTOP (0x80) -#define MCF5282_PMM_LPICR_XLMP_IPL(x) (((x)&0x07)<<4) - -#define MCF5282_PMM_LPCR_LPMD_STOP (0xC0) -#define MCF5282_PMM_LPCR_LPMD_WAIT (0x80) -#define MCF5282_PMM_LPCR_LPMD_DOZE (0x40) -#define MCF5282_PMM_LPCR_LPMD_RUN (0x00) -#define MCF5282_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF5282_PMM_LPCR_LVDSE (0x02) - -/********************************************************************* -* -* Clock Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_CLOCK_SYNCR (*(vuint16 *)(&__IPSBAR[0x120000])) -#define MCF5282_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002])) - -/* Bit level definitions and macros */ -#define MCF5282_CLOCK_SYNCR_LOLRE (0x8000) -#define MCF5282_CLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) -#define MCF5282_CLOCK_SYNCR_LOCRE (0x0800) -#define MCF5282_CLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) -#define MCF5282_CLOCK_SYNCR_LOCEN (0x0080) -#define MCF5282_CLOCK_SYNCR_DISCLK (0x0040) -#define MCF5282_CLOCK_SYNCR_FWKUP (0x0020) -#define MCF5282_CLOCK_SYNCR_STPMD(x) (((x)&0x0003)<<2) - -#define MCF5282_CLOCK_SYNSR_PLLMODE (0x80) -#define MCF5282_CLOCK_SYNSR_PLLSEL (0x40) -#define MCF5282_CLOCK_SYNSR_PLLREF (0x20) -#define MCF5282_CLOCK_SYNSR_LOCKS (0x10) -#define MCF5282_CLOCK_SYNSR_LOCK (0x08) -#define MCF5282_CLOCK_SYNSR_LOCS (0x04) - -/********************************************************************* -* -* Edge Port (EPORT) Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_EPORT_EPPAR (*(vuint16 *)(&__IPSBAR[0x130000])) -#define MCF5282_EPORT_EPDDR (*(vuint8 *)(&__IPSBAR[0x130002])) -#define MCF5282_EPORT_EPIER (*(vuint8 *)(&__IPSBAR[0x130003])) -#define MCF5282_EPORT_EPDR (*(vuint8 *)(&__IPSBAR[0x130004])) -#define MCF5282_EPORT_EPPDR (*(vuint8 *)(&__IPSBAR[0x130005])) -#define MCF5282_EPORT_EPFR (*(vuint8 *)(&__IPSBAR[0x130006])) - -/* Bit level definitions and macros */ -#define MCF5282_EPORT_EPPAR_EPPA7_LEVEL (0x0000) -#define MCF5282_EPORT_EPPAR_EPPA7_RISING (0x4000) -#define MCF5282_EPORT_EPPAR_EPPA7_FALLING (0x8000) -#define MCF5282_EPORT_EPPAR_EPPA7_BOTHEDGE (0xC000) -#define MCF5282_EPORT_EPPAR_EPPA6_LEVEL (0x0000) -#define MCF5282_EPORT_EPPAR_EPPA6_RISING (0x1000) -#define MCF5282_EPORT_EPPAR_EPPA6_FALLING (0x2000) -#define MCF5282_EPORT_EPPAR_EPPA6_BOTHEDGE (0x3000) -#define MCF5282_EPORT_EPPAR_EPPA5_LEVEL (0x0000) -#define MCF5282_EPORT_EPPAR_EPPA5_RISING (0x0400) -#define MCF5282_EPORT_EPPAR_EPPA5_FALLING (0x0800) -#define MCF5282_EPORT_EPPAR_EPPA5_BOTHEDGE (0x0C00) -#define MCF5282_EPORT_EPPAR_EPPA4_LEVEL (0x0000) -#define MCF5282_EPORT_EPPAR_EPPA4_RISING (0x0100) -#define MCF5282_EPORT_EPPAR_EPPA4_FALLING (0x0200) -#define MCF5282_EPORT_EPPAR_EPPA4_BOTHEDGE (0x0300) -#define MCF5282_EPORT_EPPAR_EPPA3_LEVEL (0x0000) -#define MCF5282_EPORT_EPPAR_EPPA3_RISING (0x0040) -#define MCF5282_EPORT_EPPAR_EPPA3_FALLING (0x0080) -#define MCF5282_EPORT_EPPAR_EPPA3_BOTHEDGE (0x00C0) -#define MCF5282_EPORT_EPPAR_EPPA2_LEVEL (0x0000) -#define MCF5282_EPORT_EPPAR_EPPA2_RISING (0x0010) -#define MCF5282_EPORT_EPPAR_EPPA2_FALLING (0x0020) -#define MCF5282_EPORT_EPPAR_EPPA2_BOTHEDGE (0x0030) -#define MCF5282_EPORT_EPPAR_EPPA1_LEVEL (0x0000) -#define MCF5282_EPORT_EPPAR_EPPA1_RISING (0x0004) -#define MCF5282_EPORT_EPPAR_EPPA1_FALLING (0x0008) -#define MCF5282_EPORT_EPPAR_EPPA1_BOTHEDGE (0x000C) - - -#define MCF5282_EPORT_EPDDR_EPDD7 (0x80) -#define MCF5282_EPORT_EPDDR_EPDD6 (0x40) -#define MCF5282_EPORT_EPDDR_EPDD5 (0x20) -#define MCF5282_EPORT_EPDDR_EPDD4 (0x10) -#define MCF5282_EPORT_EPDDR_EPDD3 (0x08) -#define MCF5282_EPORT_EPDDR_EPDD2 (0x04) -#define MCF5282_EPORT_EPDDR_EPDD1 (0x02) -#define MCF5282_EPORT_EPDDR_EPDD(x) (0x01<<(x)) - -#define MCF5282_EPORT_EPIER_EPIE7 (0x80) -#define MCF5282_EPORT_EPIER_EPIE6 (0x40) -#define MCF5282_EPORT_EPIER_EPIE5 (0x20) -#define MCF5282_EPORT_EPIER_EPIE4 (0x10) -#define MCF5282_EPORT_EPIER_EPIE3 (0x08) -#define MCF5282_EPORT_EPIER_EPIE2 (0x04) -#define MCF5282_EPORT_EPIER_EPIE1 (0x02) -#define MCF5282_EPORT_EPIER_EPIE(x) (0x01<<(x)) - -#define MCF5282_EPORT_EPDR_EPD7 (0x80) -#define MCF5282_EPORT_EPDR_EPD6 (0x40) -#define MCF5282_EPORT_EPDR_EPD5 (0x20) -#define MCF5282_EPORT_EPDR_EPD4 (0x10) -#define MCF5282_EPORT_EPDR_EPD3 (0x08) -#define MCF5282_EPORT_EPDR_EPD2 (0x04) -#define MCF5282_EPORT_EPDR_EPD1 (0x02) -#define MCF5282_EPORT_EPDR_EPD(x) (0x01<<(x)) - -#define MCF5282_EPORT_EPPDR_EPPD7 (0x80) -#define MCF5282_EPORT_EPPDR_EPPD6 (0x40) -#define MCF5282_EPORT_EPPDR_EPPD5 (0x20) -#define MCF5282_EPORT_EPPDR_EPPD4 (0x10) -#define MCF5282_EPORT_EPPDR_EPPD3 (0x08) -#define MCF5282_EPORT_EPPDR_EPPD2 (0x04) -#define MCF5282_EPORT_EPPDR_EPPD1 (0x02) -#define MCF5282_EPORT_EPPDR_EPPD(x) (0x01<<(x)) - -#define MCF5282_EPORT_EPFR_EPF7 (0x80) -#define MCF5282_EPORT_EPFR_EPF6 (0x40) -#define MCF5282_EPORT_EPFR_EPF5 (0x20) -#define MCF5282_EPORT_EPFR_EPF4 (0x10) -#define MCF5282_EPORT_EPFR_EPF3 (0x08) -#define MCF5282_EPORT_EPFR_EPF2 (0x04) -#define MCF5282_EPORT_EPFR_EPF1 (0x02) -#define MCF5282_EPORT_EPFR_EPF(x) (0x01<<(x)) - -/********************************************************************* -* -* Watchdog Timer Module (WTM) -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_WTM_WCR (*(vuint16 *)(&__IPSBAR[0x140000])) -#define MCF5282_WTM_WMR (*(vuint16 *)(&__IPSBAR[0x140002])) -#define MCF5282_WTM_WCNTR (*(vuint16 *)(&__IPSBAR[0x140004])) -#define MCF5282_WTM_WSR (*(vuint16 *)(&__IPSBAR[0x140006])) - -/* Bit level definitions and macros */ -#define MCF5282_WTM_WCR_WAIT (0x0008) -#define MCF5282_WTM_WCR_DOZE (0x0004) -#define MCF5282_WTM_WCR_HALTED (0x0002) -#define MCF5282_WTM_WCR_EN (0x0001) - -#define MCF5282_WTM_WSR_SEQ1 (0x5555) -#define MCF5282_WTM_WSR_SEQ2 (0xAAAA) - -/********************************************************************* -* -* Programmable Interrupt Timer (PIT) Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_PIT0_PCSR (*(vuint16 *)(&__IPSBAR[0x150000])) -#define MCF5282_PIT0_PMR (*(vuint16 *)(&__IPSBAR[0x150002])) -#define MCF5282_PIT0_PCNTR (*(vuint16 *)(&__IPSBAR[0x150004])) - -#define MCF5282_PIT1_PCSR (*(vuint16 *)(&__IPSBAR[0x160000])) -#define MCF5282_PIT1_PMR (*(vuint16 *)(&__IPSBAR[0x160002])) -#define MCF5282_PIT1_PCNTR (*(vuint16 *)(&__IPSBAR[0x160004])) - -#define MCF5282_PIT2_PCSR (*(vuint16 *)(&__IPSBAR[0x170000])) -#define MCF5282_PIT2_PMR (*(vuint16 *)(&__IPSBAR[0x170002])) -#define MCF5282_PIT2_PCNTR (*(vuint16 *)(&__IPSBAR[0x170004])) - -#define MCF5282_PIT3_PCSR (*(vuint16 *)(&__IPSBAR[0x180000])) -#define MCF5282_PIT3_PMR (*(vuint16 *)(&__IPSBAR[0x180002])) -#define MCF5282_PIT3_PCNTR (*(vuint16 *)(&__IPSBAR[0x180004])) - -#define MCF5282_PIT_PCSR(x) (*(vuint16 *)(&__IPSBAR[0x150000+(0x1000*(x))])) -#define MCF5282_PIT_PMR(x) (*(vuint16 *)(&__IPSBAR[0x150002+(0x1000*(x))])) -#define MCF5282_PIT_PCNTR(x) (*(vuint16 *)(&__IPSBAR[0x150004+(0x1000*(x))])) - -/* Bit level definitions and macros */ -#define MCF5282_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) -#define MCF5282_PIT_PCSR_DOZE (0x0040) -#define MCF5282_PIT_PCSR_HALTED (0x0020) -#define MCF5282_PIT_PCSR_OVW (0x0010) -#define MCF5282_PIT_PCSR_PIE (0x0008) -#define MCF5282_PIT_PCSR_PIF (0x0004) -#define MCF5282_PIT_PCSR_RLD (0x0002) -#define MCF5282_PIT_PCSR_EN (0x0001) - -/********************************************************************* -* -* Queued Analog to Digital Converter (QADC) Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_QADC_QADCMCR (*(vuint16 *)(&__IPSBAR[0x190000])) -#define MCF5282_QADC_PORTQA (*(vuint8 *)(&__IPSBAR[0x190006])) -#define MCF5282_QADC_PORTQB (*(vuint8 *)(&__IPSBAR[0x190007])) -#define MCF5282_QADC_DDRQA (*(vuint8 *)(&__IPSBAR[0x190008])) -#define MCF5282_QADC_DDRQB (*(vuint8 *)(&__IPSBAR[0x190009])) -#define MCF5282_QADC_QACR0 (*(vuint16 *)(&__IPSBAR[0x19000A])) -#define MCF5282_QADC_QACR1 (*(vuint16 *)(&__IPSBAR[0x19000C])) -#define MCF5282_QADC_QACR2 (*(vuint16 *)(&__IPSBAR[0x19000E])) -#define MCF5282_QADC_QASR0 (*(vuint16 *)(&__IPSBAR[0x190010])) -#define MCF5282_QADC_QASR1 (*(vuint16 *)(&__IPSBAR[0x190012])) -#define MCF5282_QADC_CCW(x) (*(vuint16 *)(&__IPSBAR[0x190200+((x)*2)])) -#define MCF5282_QADC_RJURR(x) (*(vuint16 *)(&__IPSBAR[0x190280+((x)*2)])) -#define MCF5282_QADC_LJSRR(x) (*(vuint16 *)(&__IPSBAR[0x190300+((x)*2)])) -#define MCF5282_QADC_LJURR(x) (*(vuint16 *)(&__IPSBAR[0x190380+((x)*2)])) - -/* Bit level definitions and macros */ -#define MCF5282_QADC_QADCMCR_QSTOP (0x8000) -#define MCF5282_QADC_QADCMCR_QDBG (0x4000) -#define MCF5282_QADC_QADCMCR_SUPV (0x0080) - -#define MCF5282_QADC_PORTQA_PQA4 (0x10) -#define MCF5282_QADC_PORTQA_PQA3 (0x08) -#define MCF5282_QADC_PORTQA_PQA1 (0x02) -#define MCF5282_QADC_PORTQA_PQA0 (0x01) -#define MCF5282_QADC_PORTQA_AN56 (0x10) -#define MCF5282_QADC_PORTQA_AN55 (0x08) -#define MCF5282_QADC_PORTQA_ETRIG2 (0x10) -#define MCF5282_QADC_PORTQA_ETRIG1 (0x08) -#define MCF5282_QADC_PORTQA_AN53 (0x02) -#define MCF5282_QADC_PORTQA_AN52 (0x01) -#define MCF5282_QADC_PORTQA_MA1 (0x02) -#define MCF5282_QADC_PORTQA_MA0 (0x01) - -#define MCF5282_QADC_PORTQB_PQB3 (0x08) -#define MCF5282_QADC_PORTQB_PQB2 (0x04) -#define MCF5282_QADC_PORTQB_PQB1 (0x02) -#define MCF5282_QADC_PORTQB_PQB0 (0x01) -#define MCF5282_QADC_PORTQB_AN3 (0x08) -#define MCF5282_QADC_PORTQB_AN2 (0x04) -#define MCF5282_QADC_PORTQB_AN1 (0x02) -#define MCF5282_QADC_PORTQB_AN0 (0x01) -#define MCF5282_QADC_PORTQB_ANZ (0x08) -#define MCF5282_QADC_PORTQB_ANY (0x04) -#define MCF5282_QADC_PORTQB_ANX (0x02) -#define MCF5282_QADC_PORTQB_ANW (0x01) - -#define MCF5282_QADC_DDRQA_DDQA4 (0x10) -#define MCF5282_QADC_DDRQA_DDQA3 (0x08) -#define MCF5282_QADC_DDRQA_DDQA1 (0x02) -#define MCF5282_QADC_DDRQA_DDQA0 (0x01) - -#define MCF5282_QADC_DDRQB_DDQB3 (0x08) -#define MCF5282_QADC_DDRQB_DDQB2 (0x04) -#define MCF5282_QADC_DDRQB_DDQB1 (0x02) -#define MCF5282_QADC_DDRQB_DDQB0 (0x01) - -#define MCF5282_QADC_QACR0_MUX (0x8000) -#define MCF5282_QADC_QACR0_TRG (0x1000) -#define MCF5282_QADC_QACR0_QPR(x) (((x)&0x007F)) - -#define MCF5282_QADC_QACRx_CIE (0x8000) -#define MCF5282_QADC_QACRx_PIE (0x4000) -#define MCF5282_QADC_QACRx_SSE (0x2000) -#define MCF5282_QADC_QACRx_MQ(x) (((x)&0x001F)<<8) -#define MCF5282_QADC_QACRx_RESUME (0x0080) -#define MCF5282_QADC_QACRx_BQ(x) (((x)&0x007F)) - -#define MCF5282_QADC_QASR0_CF1 (0x8000) -#define MCF5282_QADC_QASR0_PF1 (0x4000) -#define MCF5282_QADC_QASR0_CF2 (0x2000) -#define MCF5282_QADC_QASR0_PF2 (0x1000) -#define MCF5282_QADC_QASR0_TOR1 (0x0800) -#define MCF5282_QADC_QASR0_TOR2 (0x0400) - -#define MCF5282_QADC_CCW_P (0x0200) -#define MCF5282_QADC_CCW_BYP (0x0100) -#define MCF5282_QADC_CCW_IST(x) (((x)&0x0003)<<14) -#define MCF5282_QADC_CCW_CHAN(x) (((x)&0x003F)) - -/********************************************************************* -* -* General Purpose Timer (GPT) Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_GPTA_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000])) -#define MCF5282_GPTA_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001])) -#define MCF5282_GPTA_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002])) -#define MCF5282_GPTA_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003])) -#define MCF5282_GPTA_GPTCNT (*(vuint16 *)(&__IPSBAR[0x1A0004])) -#define MCF5282_GPTA_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006])) -#define MCF5282_GPTA_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008])) -#define MCF5282_GPTA_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009])) -#define MCF5282_GPTA_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B])) -#define MCF5282_GPTA_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C])) -#define MCF5282_GPTA_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D])) -#define MCF5282_GPTA_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E])) -#define MCF5282_GPTA_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F])) -#define MCF5282_GPTA_GPTC0 (*(vuint16 *)(&__IPSBAR[0x1A0010])) -#define MCF5282_GPTA_GPTC1 (*(vuint16 *)(&__IPSBAR[0x1A0012])) -#define MCF5282_GPTA_GPTC2 (*(vuint16 *)(&__IPSBAR[0x1A0014])) -#define MCF5282_GPTA_GPTC3 (*(vuint16 *)(&__IPSBAR[0x1A0016])) -#define MCF5282_GPTA_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018])) -#define MCF5282_GPTA_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019])) -#define MCF5282_GPTA_GPTPACNT (*(vuint16 *)(&__IPSBAR[0x1A001A])) -#define MCF5282_GPTA_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D])) -#define MCF5282_GPTA_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E])) - -#define MCF5282_GPTB_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1B0000])) -#define MCF5282_GPTB_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1B0001])) -#define MCF5282_GPTB_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1B0002])) -#define MCF5282_GPTB_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1B0003])) -#define MCF5282_GPTB_GPTCNT (*(vuint16 *)(&__IPSBAR[0x1B0004])) -#define MCF5282_GPTB_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1B0006])) -#define MCF5282_GPTB_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1B0008])) -#define MCF5282_GPTB_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1B0009])) -#define MCF5282_GPTB_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1B000B])) -#define MCF5282_GPTB_GPTIE (*(vuint8 *)(&__IPSBAR[0x1B000C])) -#define MCF5282_GPTB_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1B000D])) -#define MCF5282_GPTB_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1B000E])) -#define MCF5282_GPTB_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1B000F])) -#define MCF5282_GPTB_GPTC0 (*(vuint16 *)(&__IPSBAR[0x1B0010])) -#define MCF5282_GPTB_GPTC1 (*(vuint16 *)(&__IPSBAR[0x1B0012])) -#define MCF5282_GPTB_GPTC2 (*(vuint16 *)(&__IPSBAR[0x1B0014])) -#define MCF5282_GPTB_GPTC3 (*(vuint16 *)(&__IPSBAR[0x1B0016])) -#define MCF5282_GPTB_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1B0018])) -#define MCF5282_GPTB_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1B0019])) -#define MCF5282_GPTB_GPTPACNT (*(vuint16 *)(&__IPSBAR[0x1B001A])) -#define MCF5282_GPTB_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1B001D])) -#define MCF5282_GPTB_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1B001E])) - -/* Bit level definitions and macros */ -#define MCF5282_GPT_GPTIOS_IOS3 (0x08) -#define MCF5282_GPT_GPTIOS_IOS2 (0x04) -#define MCF5282_GPT_GPTIOS_IOS1 (0x02) -#define MCF5282_GPT_GPTIOS_IOS0 (0x01) - -#define MCF5282_GPT_GPTCFORC_FOC3 (0x08) -#define MCF5282_GPT_GPTCFORC_FOC2 (0x04) -#define MCF5282_GPT_GPTCFORC_FOC1 (0x02) -#define MCF5282_GPT_GPTCFORC_FOC0 (0x01) - -#define MCF5282_GPT_GPTOC3M_OC3M3 (0x08) -#define MCF5282_GPT_GPTOC3M_OC3M2 (0x04) -#define MCF5282_GPT_GPTOC3M_OC3M1 (0x02) -#define MCF5282_GPT_GPTOC3M_OC3M0 (0x01) - -#define MCF5282_GPT_GPTOC3M_OC3D(x) (((x)&0x04)) - -#define MCF5282_GPT_GPTSCR1_GPTEN (0x80) -#define MCF5282_GPT_GPTSCR1_TFFCA (0x10) - -#define MCF5282_GPT_GPTTOV3 (0x08) -#define MCF5282_GPT_GPTTOV2 (0x04) -#define MCF5282_GPT_GPTTOV1 (0x02) -#define MCF5282_GPT_GPTTOV0 (0x01) - -#define MCF5282_GPT_GPTCTL_OMOL3(x) (((x)&0x03)<<6) -#define MCF5282_GPT_GPTCTL_OMOL2(x) (((x)&0x03)<<4) -#define MCF5282_GPT_GPTCTL_OMOL1(x) (((x)&0x03)<<2) -#define MCF5282_GPT_GPTCTL_OMOL0(x) (((x)&0x03)) - -#define MCF5282_GPT_GPTCTL2_EDG3(x) (((x)&0x03)<<6) -#define MCF5282_GPT_GPTCTL2_EDG2(x) (((x)&0x03)<<4) -#define MCF5282_GPT_GPTCTL2_EDG1(x) (((x)&0x03)<<2) -#define MCF5282_GPT_GPTCTL2_EDG0(x) (((x)&0x03)) - -#define MCF5282_GPT_GPTIE_C3I (0x08) -#define MCF5282_GPT_GPTIE_C2I (0x04) -#define MCF5282_GPT_GPTIE_C1I (0x02) -#define MCF5282_GPT_GPTIE_C0I (0x01) - -#define MCF5282_GPT_GPTSCR2_TOI (0x80) -#define MCF5282_GPT_GPTSCR2_PUPT (0x20) -#define MCF5282_GPT_GPTSCR2_RDPT (0x10) -#define MCF5282_GPT_GPTSCR2_TCRE (0x08) -#define MCF5282_GPT_GPTSCR2_PR(x) (((x)&0x07)) - -#define MCF5282_GPT_GPTFLG1_C3F (0x08) -#define MCF5282_GPT_GPTFLG1_C2F (0x04) -#define MCF5282_GPT_GPTFLG1_C1F (0x02) -#define MCF5282_GPT_GPTFLG1_C0F (0x01) - -#define MCF5282_GPT_GPTFLG2_TOF (0x80) -#define MCF5282_GPT_GPTFLG2_C3F (0x08) -#define MCF5282_GPT_GPTFLG2_C2F (0x04) -#define MCF5282_GPT_GPTFLG2_C1F (0x02) -#define MCF5282_GPT_GPTFLG2_C0F (0x01) - -#define MCF5282_GPT_GPTPACTL_PAE (0x40) -#define MCF5282_GPT_GPTPACTL_PAMOD (0x20) -#define MCF5282_GPT_GPTPACTL_PEDGE (0x10) -#define MCF5282_GPT_GPTPACTL_CLK_PACLK (0x04) -#define MCF5282_GPT_GPTPACTL_CLK_PACLK256 (0x08) -#define MCF5282_GPT_GPTPACTL_CLK_PACLK65536 (0x0C) -#define MCF5282_GPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) -#define MCF5282_GPT_GPTPACTL_PAOVI (0x02) -#define MCF5282_GPT_GPTPACTL_PAI (0x01) - -#define MCF5282_GPT_GPTPAFLG_PAOVF (0x02) -#define MCF5282_GPT_GPTPAFLG_PAIF (0x01) - -#define MCF5282_GPT_GPTPORT_PORTT3 (0x08) -#define MCF5282_GPT_GPTPORT_PORTT2 (0x04) -#define MCF5282_GPT_GPTPORT_PORTT1 (0x02) -#define MCF5282_GPT_GPTPORT_PORTT0 (0x01) - -#define MCF5282_GPT_GPTDDR_DDRT3 (0x08) -#define MCF5282_GPT_GPTDDR_DDRT2 (0x04) -#define MCF5282_GPT_GPTDDR_DDRT1 (0x02) -#define MCF5282_GPT_GPTDDR_DDRT0 (0x01) - -/********************************************************************* -* -* FlexCAN Module -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_FLEXCAN_CANMCR (*(vuint16 *)(&__IPSBAR[0x1C0000])) -#define MCF5282_FLEXCAN_CANCTRL0 (*(vuint8 *)(&__IPSBAR[0x1C0006])) -#define MCF5282_FLEXCAN_CANCTRL1 (*(vuint8 *)(&__IPSBAR[0x1C0007])) -#define MCF5282_FLEXCAN_PRESDIV (*(vuint8 *)(&__IPSBAR[0x1C0008])) -#define MCF5282_FLEXCAN_CANCTRL2 (*(vuint8 *)(&__IPSBAR[0x1C0009])) -#define MCF5282_FLEXCAN_TIMER (*(vuint16 *)(&__IPSBAR[0x1C000A])) -#define MCF5282_FLEXCAN_RXGMASK (*(vuint32 *)(&__IPSBAR[0x1C0010])) -#define MCF5282_FLEXCAN_RX14MASK (*(vuint32 *)(&__IPSBAR[0x1C0014])) -#define MCF5282_FLEXCAN_RX15MASK (*(vuint32 *)(&__IPSBAR[0x1C0018])) -#define MCF5282_FLEXCAN_ESTAT (*(vuint16 *)(&__IPSBAR[0x1C0020])) -#define MCF5282_FLEXCAN_IMASK (*(vuint16 *)(&__IPSBAR[0x1C0022])) -#define MCF5282_FLEXCAN_IFLAG (*(vuint16 *)(&__IPSBAR[0x1C0024])) -#define MCF5282_FLEXCAN_RXECTR (*(vuint8 *)(&__IPSBAR[0x1C0026])) -#define MCF5282_FLEXCAN_TXECTR (*(vuint8 *)(&__IPSBAR[0x1C0027])) -#define MCF5282_FLEXCAN_MBUF0_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0081])) -#define MCF5282_FLEXCAN_MBUF0_IDH (*(vuint16 *)(&__IPSBAR[0x1C0082])) -#define MCF5282_FLEXCAN_MBUF0_IDL (*(vuint16 *)(&__IPSBAR[0x1C0084])) -#define MCF5282_FLEXCAN_MBUF0_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0086])) -#define MCF5282_FLEXCAN_MBUF0_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0087])) -#define MCF5282_FLEXCAN_MBUF0_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0088])) -#define MCF5282_FLEXCAN_MBUF0_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0089])) -#define MCF5282_FLEXCAN_MBUF0_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C008A])) -#define MCF5282_FLEXCAN_MBUF0_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C008B])) -#define MCF5282_FLEXCAN_MBUF0_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C008C])) -#define MCF5282_FLEXCAN_MBUF0_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C008D])) -#define MCF5282_FLEXCAN_MBUF1_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0091])) -#define MCF5282_FLEXCAN_MBUF1_IDH (*(vuint16 *)(&__IPSBAR[0x1C0092])) -#define MCF5282_FLEXCAN_MBUF1_IDL (*(vuint16 *)(&__IPSBAR[0x1C0094])) -#define MCF5282_FLEXCAN_MBUF1_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0096])) -#define MCF5282_FLEXCAN_MBUF1_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0097])) -#define MCF5282_FLEXCAN_MBUF1_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0098])) -#define MCF5282_FLEXCAN_MBUF1_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0099])) -#define MCF5282_FLEXCAN_MBUF1_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C009A])) -#define MCF5282_FLEXCAN_MBUF1_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C009B])) -#define MCF5282_FLEXCAN_MBUF1_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C009C])) -#define MCF5282_FLEXCAN_MBUF1_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C009D])) -#define MCF5282_FLEXCAN_MBUF2_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00A1])) -#define MCF5282_FLEXCAN_MBUF2_IDH (*(vuint16 *)(&__IPSBAR[0x1C00A2])) -#define MCF5282_FLEXCAN_MBUF2_IDL (*(vuint16 *)(&__IPSBAR[0x1C00A4])) -#define MCF5282_FLEXCAN_MBUF2_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00A6])) -#define MCF5282_FLEXCAN_MBUF2_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00A7])) -#define MCF5282_FLEXCAN_MBUF2_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00A8])) -#define MCF5282_FLEXCAN_MBUF2_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00A9])) -#define MCF5282_FLEXCAN_MBUF2_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00AA])) -#define MCF5282_FLEXCAN_MBUF2_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00AB])) -#define MCF5282_FLEXCAN_MBUF2_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00AC])) -#define MCF5282_FLEXCAN_MBUF2_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00AD])) -#define MCF5282_FLEXCAN_MBUF3_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00B1])) -#define MCF5282_FLEXCAN_MBUF3_IDH (*(vuint16 *)(&__IPSBAR[0x1C00B2])) -#define MCF5282_FLEXCAN_MBUF3_IDL (*(vuint16 *)(&__IPSBAR[0x1C00B4])) -#define MCF5282_FLEXCAN_MBUF3_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00B6])) -#define MCF5282_FLEXCAN_MBUF3_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00B7])) -#define MCF5282_FLEXCAN_MBUF3_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00B8])) -#define MCF5282_FLEXCAN_MBUF3_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00B9])) -#define MCF5282_FLEXCAN_MBUF3_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00BA])) -#define MCF5282_FLEXCAN_MBUF3_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00BB])) -#define MCF5282_FLEXCAN_MBUF3_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00BC])) -#define MCF5282_FLEXCAN_MBUF3_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00BD])) -#define MCF5282_FLEXCAN_MBUF4_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00C1])) -#define MCF5282_FLEXCAN_MBUF4_IDH (*(vuint16 *)(&__IPSBAR[0x1C00C2])) -#define MCF5282_FLEXCAN_MBUF4_IDL (*(vuint16 *)(&__IPSBAR[0x1C00C4])) -#define MCF5282_FLEXCAN_MBUF4_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00C6])) -#define MCF5282_FLEXCAN_MBUF4_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00C7])) -#define MCF5282_FLEXCAN_MBUF4_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00C8])) -#define MCF5282_FLEXCAN_MBUF4_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00C9])) -#define MCF5282_FLEXCAN_MBUF4_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00CA])) -#define MCF5282_FLEXCAN_MBUF4_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00CB])) -#define MCF5282_FLEXCAN_MBUF4_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00CC])) -#define MCF5282_FLEXCAN_MBUF4_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00CD])) -#define MCF5282_FLEXCAN_MBUF5_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00D1])) -#define MCF5282_FLEXCAN_MBUF5_IDH (*(vuint16 *)(&__IPSBAR[0x1C00D2])) -#define MCF5282_FLEXCAN_MBUF5_IDL (*(vuint16 *)(&__IPSBAR[0x1C00D4])) -#define MCF5282_FLEXCAN_MBUF5_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00D6])) -#define MCF5282_FLEXCAN_MBUF5_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00D7])) -#define MCF5282_FLEXCAN_MBUF5_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00D8])) -#define MCF5282_FLEXCAN_MBUF5_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00D9])) -#define MCF5282_FLEXCAN_MBUF5_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00DA])) -#define MCF5282_FLEXCAN_MBUF5_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00DB])) -#define MCF5282_FLEXCAN_MBUF5_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00DC])) -#define MCF5282_FLEXCAN_MBUF5_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00DD])) -#define MCF5282_FLEXCAN_MBUF6_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00E1])) -#define MCF5282_FLEXCAN_MBUF6_IDH (*(vuint16 *)(&__IPSBAR[0x1C00E2])) -#define MCF5282_FLEXCAN_MBUF6_IDL (*(vuint16 *)(&__IPSBAR[0x1C00E4])) -#define MCF5282_FLEXCAN_MBUF6_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00E6])) -#define MCF5282_FLEXCAN_MBUF6_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00E7])) -#define MCF5282_FLEXCAN_MBUF6_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00E8])) -#define MCF5282_FLEXCAN_MBUF6_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00E9])) -#define MCF5282_FLEXCAN_MBUF6_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00EA])) -#define MCF5282_FLEXCAN_MBUF6_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00EB])) -#define MCF5282_FLEXCAN_MBUF6_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00EC])) -#define MCF5282_FLEXCAN_MBUF6_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00ED])) -#define MCF5282_FLEXCAN_MBUF7_CTRL (*(vuint8 *)(&__IPSBAR[0x1C00F1])) -#define MCF5282_FLEXCAN_MBUF7_IDH (*(vuint16 *)(&__IPSBAR[0x1C00F2])) -#define MCF5282_FLEXCAN_MBUF7_IDL (*(vuint16 *)(&__IPSBAR[0x1C00F4])) -#define MCF5282_FLEXCAN_MBUF7_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C00F6])) -#define MCF5282_FLEXCAN_MBUF7_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C00F7])) -#define MCF5282_FLEXCAN_MBUF7_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C00F8])) -#define MCF5282_FLEXCAN_MBUF7_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C00F9])) -#define MCF5282_FLEXCAN_MBUF7_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C00FA])) -#define MCF5282_FLEXCAN_MBUF7_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C00FB])) -#define MCF5282_FLEXCAN_MBUF7_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C00FC])) -#define MCF5282_FLEXCAN_MBUF7_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C00FD])) -#define MCF5282_FLEXCAN_MBUF8_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0101])) -#define MCF5282_FLEXCAN_MBUF8_IDH (*(vuint16 *)(&__IPSBAR[0x1C0102])) -#define MCF5282_FLEXCAN_MBUF8_IDL (*(vuint16 *)(&__IPSBAR[0x1C0104])) -#define MCF5282_FLEXCAN_MBUF8_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0106])) -#define MCF5282_FLEXCAN_MBUF8_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0107])) -#define MCF5282_FLEXCAN_MBUF8_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0108])) -#define MCF5282_FLEXCAN_MBUF8_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0109])) -#define MCF5282_FLEXCAN_MBUF8_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C010A])) -#define MCF5282_FLEXCAN_MBUF8_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C010B])) -#define MCF5282_FLEXCAN_MBUF8_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C010C])) -#define MCF5282_FLEXCAN_MBUF8_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C010D])) -#define MCF5282_FLEXCAN_MBUF9_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0111])) -#define MCF5282_FLEXCAN_MBUF9_IDH (*(vuint16 *)(&__IPSBAR[0x1C0112])) -#define MCF5282_FLEXCAN_MBUF9_IDL (*(vuint16 *)(&__IPSBAR[0x1C0114])) -#define MCF5282_FLEXCAN_MBUF9_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0116])) -#define MCF5282_FLEXCAN_MBUF9_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0117])) -#define MCF5282_FLEXCAN_MBUF9_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0118])) -#define MCF5282_FLEXCAN_MBUF9_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0119])) -#define MCF5282_FLEXCAN_MBUF9_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C011A])) -#define MCF5282_FLEXCAN_MBUF9_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C011B])) -#define MCF5282_FLEXCAN_MBUF9_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C011C])) -#define MCF5282_FLEXCAN_MBUF9_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C011D])) -#define MCF5282_FLEXCAN_MBUF10_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0121])) -#define MCF5282_FLEXCAN_MBUF10_IDH (*(vuint16 *)(&__IPSBAR[0x1C0122])) -#define MCF5282_FLEXCAN_MBUF10_IDL (*(vuint16 *)(&__IPSBAR[0x1C0124])) -#define MCF5282_FLEXCAN_MBUF10_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0126])) -#define MCF5282_FLEXCAN_MBUF10_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0127])) -#define MCF5282_FLEXCAN_MBUF10_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0128])) -#define MCF5282_FLEXCAN_MBUF10_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0129])) -#define MCF5282_FLEXCAN_MBUF10_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C012A])) -#define MCF5282_FLEXCAN_MBUF10_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C012B])) -#define MCF5282_FLEXCAN_MBUF10_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C012C])) -#define MCF5282_FLEXCAN_MBUF10_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C012D])) -#define MCF5282_FLEXCAN_MBUF11_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0131])) -#define MCF5282_FLEXCAN_MBUF11_IDH (*(vuint16 *)(&__IPSBAR[0x1C0132])) -#define MCF5282_FLEXCAN_MBUF11_IDL (*(vuint16 *)(&__IPSBAR[0x1C0134])) -#define MCF5282_FLEXCAN_MBUF11_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0136])) -#define MCF5282_FLEXCAN_MBUF11_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0137])) -#define MCF5282_FLEXCAN_MBUF11_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0138])) -#define MCF5282_FLEXCAN_MBUF11_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0139])) -#define MCF5282_FLEXCAN_MBUF11_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C013A])) -#define MCF5282_FLEXCAN_MBUF11_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C013B])) -#define MCF5282_FLEXCAN_MBUF11_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C013C])) -#define MCF5282_FLEXCAN_MBUF11_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C013D])) -#define MCF5282_FLEXCAN_MBUF12_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0141])) -#define MCF5282_FLEXCAN_MBUF12_IDH (*(vuint16 *)(&__IPSBAR[0x1C0142])) -#define MCF5282_FLEXCAN_MBUF12_IDL (*(vuint16 *)(&__IPSBAR[0x1C0144])) -#define MCF5282_FLEXCAN_MBUF12_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0146])) -#define MCF5282_FLEXCAN_MBUF12_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0147])) -#define MCF5282_FLEXCAN_MBUF12_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0148])) -#define MCF5282_FLEXCAN_MBUF12_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0149])) -#define MCF5282_FLEXCAN_MBUF12_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C014A])) -#define MCF5282_FLEXCAN_MBUF12_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C014B])) -#define MCF5282_FLEXCAN_MBUF12_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C014C])) -#define MCF5282_FLEXCAN_MBUF12_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C014D])) -#define MCF5282_FLEXCAN_MBUF13_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0151])) -#define MCF5282_FLEXCAN_MBUF13_IDH (*(vuint16 *)(&__IPSBAR[0x1C0152])) -#define MCF5282_FLEXCAN_MBUF13_IDL (*(vuint16 *)(&__IPSBAR[0x1C0154])) -#define MCF5282_FLEXCAN_MBUF13_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0156])) -#define MCF5282_FLEXCAN_MBUF13_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0157])) -#define MCF5282_FLEXCAN_MBUF13_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0158])) -#define MCF5282_FLEXCAN_MBUF13_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0159])) -#define MCF5282_FLEXCAN_MBUF13_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C015A])) -#define MCF5282_FLEXCAN_MBUF13_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C015B])) -#define MCF5282_FLEXCAN_MBUF13_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C015C])) -#define MCF5282_FLEXCAN_MBUF13_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C015D])) -#define MCF5282_FLEXCAN_MBUF14_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0161])) -#define MCF5282_FLEXCAN_MBUF14_IDH (*(vuint16 *)(&__IPSBAR[0x1C0162])) -#define MCF5282_FLEXCAN_MBUF14_IDL (*(vuint16 *)(&__IPSBAR[0x1C0164])) -#define MCF5282_FLEXCAN_MBUF14_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0166])) -#define MCF5282_FLEXCAN_MBUF14_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0167])) -#define MCF5282_FLEXCAN_MBUF14_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0168])) -#define MCF5282_FLEXCAN_MBUF14_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0169])) -#define MCF5282_FLEXCAN_MBUF14_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C016A])) -#define MCF5282_FLEXCAN_MBUF14_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C016B])) -#define MCF5282_FLEXCAN_MBUF14_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C016C])) -#define MCF5282_FLEXCAN_MBUF14_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C016D])) -#define MCF5282_FLEXCAN_MBUF15_CTRL (*(vuint8 *)(&__IPSBAR[0x1C0171])) -#define MCF5282_FLEXCAN_MBUF15_IDH (*(vuint16 *)(&__IPSBAR[0x1C0172])) -#define MCF5282_FLEXCAN_MBUF15_IDL (*(vuint16 *)(&__IPSBAR[0x1C0174])) -#define MCF5282_FLEXCAN_MBUF15_BYTE0 (*(vuint8 *)(&__IPSBAR[0x1C0176])) -#define MCF5282_FLEXCAN_MBUF15_BYTE1 (*(vuint8 *)(&__IPSBAR[0x1C0177])) -#define MCF5282_FLEXCAN_MBUF15_BYTE2 (*(vuint8 *)(&__IPSBAR[0x1C0178])) -#define MCF5282_FLEXCAN_MBUF15_BYTE3 (*(vuint8 *)(&__IPSBAR[0x1C0179])) -#define MCF5282_FLEXCAN_MBUF15_BYTE4 (*(vuint8 *)(&__IPSBAR[0x1C017A])) -#define MCF5282_FLEXCAN_MBUF15_BYTE5 (*(vuint8 *)(&__IPSBAR[0x1C017B])) -#define MCF5282_FLEXCAN_MBUF15_BYTE6 (*(vuint8 *)(&__IPSBAR[0x1C017C])) -#define MCF5282_FLEXCAN_MBUF15_BYTE7 (*(vuint8 *)(&__IPSBAR[0x1C017D])) - -#define MCF5282_FLEXCAN_MBUF0_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0086+(x))])) -#define MCF5282_FLEXCAN_MBUF1_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0096+(x))])) -#define MCF5282_FLEXCAN_MBUF2_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00A6+(x))])) -#define MCF5282_FLEXCAN_MBUF3_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00B6+(x))])) -#define MCF5282_FLEXCAN_MBUF4_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00C6+(x))])) -#define MCF5282_FLEXCAN_MBUF5_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00D6+(x))])) -#define MCF5282_FLEXCAN_MBUF6_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00E6+(x))])) -#define MCF5282_FLEXCAN_MBUF7_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C00F6+(x))])) -#define MCF5282_FLEXCAN_MBUF8_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0106+(x))])) -#define MCF5282_FLEXCAN_MBUF9_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0116+(x))])) -#define MCF5282_FLEXCAN_MBUF10_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0126+(x))])) -#define MCF5282_FLEXCAN_MBUF11_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0136+(x))])) -#define MCF5282_FLEXCAN_MBUF12_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0146+(x))])) -#define MCF5282_FLEXCAN_MBUF13_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0156+(x))])) -#define MCF5282_FLEXCAN_MBUF14_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0166+(x))])) -#define MCF5282_FLEXCAN_MBUF15_BYTE(x) (*(vuint8 *)(&__IPSBAR[(0x1C0176+(x))])) - -#define MCF5282_FLEXCAN_MBUF_BYTE(x,y) (*(vuint8 *)(&__IPSBAR[((0x1C0086+(0x10*(x))+(y))])) - -/* Bit level definitions and macros */ -#define MCF5282_FLEXCAN_CANMCR_STOP (0x8000) -#define MCF5282_FLEXCAN_CANMCR_FRZ (0x4000) -#define MCF5282_FLEXCAN_CANMCR_HALT (0x1000) -#define MCF5282_FLEXCAN_CANMCR_NOTRDY (0x0800) -#define MCF5282_FLEXCAN_CANMCR_WAKEMSK (0x0400) -#define MCF5282_FLEXCAN_CANMCR_SOFTRST (0x0200) -#define MCF5282_FLEXCAN_CANMCR_FRZACK (0x0100) -#define MCF5282_FLEXCAN_CANMCR_SUPV (0x0080) -#define MCF5282_FLEXCAN_CANMCR_SELFWAKE (0x0040) -#define MCF5282_FLEXCAN_CANMCR_APS (0x0020) - -#define MCF5282_FLEXCAN_CANCTRL0_BOFFMSK (0x80) -#define MCF5282_FLEXCAN_CANCTRL0_ERRMSK (0x40) -#define MCF5282_FLEXCAN_CANCTRL0_RXMODE (0x04) -#define MCF5282_FLEXCAN_CANCTRL0_TXMODE_CMOSPOS (0x00) -#define MCF5282_FLEXCAN_CANCTRL0_TXMODE_CMOSNEG (0x01) -#define MCF5282_FLEXCAN_CANCTRL0_TXMODE_OPENDRAIN (0x02) - -#define MCF5282_FLEXCAN_CANCTRL1_SAMP (0x80) -#define MCF5282_FLEXCAN_CANCTRL1_TSYNC (0x20) -#define MCF5282_FLEXCAN_CANCTRL1_LBUF (0x10) -#define MCF5282_FLEXCAN_CANCTRL1_LOM (0x08) -#define MCF5282_FLEXCAN_CANCTRL1_PROPSEG(x) (((x)&0x07)) - -#define MCF5282_FLEXCAN_CANCTRL2_RJW(x) (((x)&0x03)<<6) -#define MCF5282_FLEXCAN_CANCTRL2_PSEG1(x) (((x)&0x07)<<3) -#define MCF5282_FLEXCAN_CANCTRL2_PSEG2(x) (((x)&0x07)<<0) - -#define MCF5282_FLEXCAN_ESTAT_BITERR(x) (((x)&0x03)<<14) -#define MCF5282_FLEXCAN_ESTAT_ACKERR (0x2000) -#define MCF5282_FLEXCAN_ESTAT_CRCERR (0x1000) -#define MCF5282_FLEXCAN_ESTAT_FORMERR (0x0800) -#define MCF5282_FLEXCAN_ESTAT_STUFFERR (0x0400) -#define MCF5282_FLEXCAN_ESTAT_TXWARN (0x0200) -#define MCF5282_FLEXCAN_ESTAT_RXWARN (0x0100) -#define MCF5282_FLEXCAN_ESTAT_IDLE (0x0080) -#define MCF5282_FLEXCAN_ESTAT_TXRX (0x0040) -#define MCF5282_FLEXCAN_ESTAT_FCS(x) (((x)&0x03)<<4) -#define MCF5282_FLEXCAN_ESTAT_BOFFINT (0x0004) -#define MCF5282_FLEXCAN_ESTAT_ERRINT (0x0002) -#define MCF5282_FLEXCAN_ESTAT_WAKEINT (0x0001) - -#define MCF5282_FLEXCAN_IMASK_BUF15M (0x8000) -#define MCF5282_FLEXCAN_IMASK_BUF14M (0x4000) -#define MCF5282_FLEXCAN_IMASK_BUF13M (0x2000) -#define MCF5282_FLEXCAN_IMASK_BUF12M (0x1000) -#define MCF5282_FLEXCAN_IMASK_BUF11M (0x0800) -#define MCF5282_FLEXCAN_IMASK_BUF10M (0x0400) -#define MCF5282_FLEXCAN_IMASK_BUF9M (0x0200) -#define MCF5282_FLEXCAN_IMASK_BUF8M (0x0100) -#define MCF5282_FLEXCAN_IMASK_BUF7M (0x0080) -#define MCF5282_FLEXCAN_IMASK_BUF6M (0x0040) -#define MCF5282_FLEXCAN_IMASK_BUF5M (0x0020) -#define MCF5282_FLEXCAN_IMASK_BUF4M (0x0010) -#define MCF5282_FLEXCAN_IMASK_BUF3M (0x0008) -#define MCF5282_FLEXCAN_IMASK_BUF2M (0x0004) -#define MCF5282_FLEXCAN_IMASK_BUF1M (0x0002) -#define MCF5282_FLEXCAN_IMASK_BUF0M (0x0001) - -#define MCF5282_FLEXCAN_IFLAG_BUF15I (0x8000) -#define MCF5282_FLEXCAN_IFLAG_BUF14I (0x4000) -#define MCF5282_FLEXCAN_IFLAG_BUF13I (0x2000) -#define MCF5282_FLEXCAN_IFLAG_BUF12I (0x1000) -#define MCF5282_FLEXCAN_IFLAG_BUF11I (0x0800) -#define MCF5282_FLEXCAN_IFLAG_BUF10I (0x0400) -#define MCF5282_FLEXCAN_IFLAG_BUF9I (0x0200) -#define MCF5282_FLEXCAN_IFLAG_BUF8I (0x0100) -#define MCF5282_FLEXCAN_IFLAG_BUF7I (0x0080) -#define MCF5282_FLEXCAN_IFLAG_BUF6I (0x0040) -#define MCF5282_FLEXCAN_IFLAG_BUF5I (0x0020) -#define MCF5282_FLEXCAN_IFLAG_BUF4I (0x0010) -#define MCF5282_FLEXCAN_IFLAG_BUF3I (0x0008) -#define MCF5282_FLEXCAN_IFLAG_BUF2I (0x0004) -#define MCF5282_FLEXCAN_IFLAG_BUF1I (0x0002) -#define MCF5282_FLEXCAN_IFLAG_BUF0I (0x0001) - -/********************************************************************* -* -* ColdFire Flash Module (CFM) -* -*********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF5282_CFM_CFMMCR (*(vuint16 *)(&__IPSBAR[0x1D0000])) -#define MCF5282_CFM_CFMCLKD (*(vuint8 *)(&__IPSBAR[0x1D0002])) -#define MCF5282_CFM_CFMSEC (*(vuint32 *)(&__IPSBAR[0x1D0008])) -#define MCF5282_CFM_CFMPROT (*(vuint32 *)(&__IPSBAR[0x1D0010])) -#define MCF5282_CFM_CFMSACC (*(vuint32 *)(&__IPSBAR[0x1D0014])) -#define MCF5282_CFM_CFMDACC (*(vuint32 *)(&__IPSBAR[0x1D0018])) -#define MCF5282_CFM_CFMUSTAT (*(vuint8 *)(&__IPSBAR[0x1D0020])) -#define MCF5282_CFM_CFMCMD (*(vuint8 *)(&__IPSBAR[0x1D0024])) -#define MCF5282_CFM_CFMDISU (*(vuint16 *)(&__IPSBAR[0x1D0042])) - -/* Bit level definitions and macros */ -#define MCF5282_CFM_FLASHBAR_BA(a) ((a)&0xFFF8000) -#define MCF5282_CFM_FLASHBAR_WP (0x00000100) -#define MCF5282_CFM_FLASHBAR_CI (0x00000020) -#define MCF5282_CFM_FLASHBAR_SC (0x00000010) -#define MCF5282_CFM_FLASHBAR_SD (0x00000008) -#define MCF5282_CFM_FLASHBAR_UC (0x00000004) -#define MCF5282_CFM_FLASHBAR_UD (0x00000002) -#define MCF5282_CFM_FLASHBAR_V (0x00000001) - -#define MCF5282_CFM_CFMMCR_LOCK (0x0400) -#define MCF5282_CFM_CFMMCR_PVIE (0x0200) -#define MCF5282_CFM_CFMMCR_AEIE (0x0100) -#define MCF5282_CFM_CFMMCR_CBEIE (0x0080) -#define MCF5282_CFM_CFMMCR_CCIE (0x0040) -#define MCF5282_CFM_CFMMCR_KEYACC (0x0020) - -#define MCF5282_CFM_CFMCLKD_DIVLD (0x80) -#define MCF5282_CFM_CFMCLKD_PRDIV8 (0x40) -#define MCF5282_CFM_CFMCLKD_DIV(x) (((x)&0x3F)) - -#define MCF5282_CFM_CFMSEC_KEYEN (0x80000000) -#define MCF5282_CFM_CFMSEC_SECSTAT (0x40000000) -#define MCF5282_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)) - -#define MCF5282_CFM_CFMUSTAT_CBEIF (0x80) -#define MCF5282_CFM_CFMUSTAT_CCIF (0x40) -#define MCF5282_CFM_CFMUSTAT_PVIOL (0x20) -#define MCF5282_CFM_CFMUSTAT_ACCERR (0x10) -#define MCF5282_CFM_CFMUSTAT_BLANK (0x04) - -#define MCF5282_CFM_CFMCMD_CMD(x) (((x)&0x7F)) - -/********************************************************************/ - -#endif /* _CPU_MCF5282_H */ diff --git a/c/src/lib/libcpu/m68k/mcf532x/include/mcf532x.h b/c/src/lib/libcpu/m68k/mcf532x/include/mcf532x.h deleted file mode 100644 index 798fb1175b..0000000000 --- a/c/src/lib/libcpu/m68k/mcf532x/include/mcf532x.h +++ /dev/null @@ -1,4483 +0,0 @@ -/* - * File: mcf532x.h - * Purpose: Register and bit definitions - */ - -#ifndef __MCF532X_H__ -#define __MCF532X_H__ - -/********************************************************************* -* -* Cache -* -*********************************************************************/ - -#define MCF_CACR_CENB (1 << 31) -#define MCF_CACR_ESB (1 << 29) -#define MCF_CACR_DPI (1 << 28) -#define MCF_CACR_HLCK (1 << 27) -#define MCF_CACR_CINVA (1 << 24) -#define MCF_CACR_DNFB (1 << 10) -#define MCF_CACR_DCM(A) (((A) & 0x3) << 8) -#define MCF_CACR_DW (1 << 5) -#define MCF_CACR_EUSP (1 << 4) - -#define MCF_ACR_ADDR_BASE(A) (((A) & 0xFF) << 24) -#define MCF_ACR_ADDR_MASK(A) (((A) & 0xFF) << 16) -#define MCF_ACR_E (1 << 15) -#define MCF_ACR_S(A) (((A) & 0x3) << 13) -#define MCF_ACR_CM(A) (((A) & 0x3) << 5) -#define MCF_ACR_W (1 << 2) - -/********************************************************************* -* -* System Control Module (SCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SCM_MPR0 (*(vuint32*)(0xEC000000)) -#define MCF_SCM_MPR1 (*(vuint32*)(0xFC000000)) -#define MCF_SCM_BMT0 (*(vuint32*)(0xEC000054)) -#define MCF_SCM_BMT1 (*(vuint32*)(0xFC000054)) -#define MCF_SCM_PACRA (*(vuint32*)(0xFC000020)) -#define MCF_SCM_PACRB (*(vuint32*)(0xFC000024)) -#define MCF_SCM_PACRC (*(vuint32*)(0xFC000028)) -#define MCF_SCM_PACRD (*(vuint32*)(0xFC00002C)) -#define MCF_SCM_PACRE (*(vuint32*)(0xFC000040)) -#define MCF_SCM_PACRF (*(vuint32*)(0xFC000044)) -#define MCF_SCM_PACRG (*(vuint32*)(0xEC000048)) -#define MCF_SCM_PACRH (*(vuint32*)(0xEC000040)) -#define MCF_SCM_CWCR (*(vuint16*)(0xFC040016)) -#define MCF_SCM_CWSR (*(vuint8 *)(0xFC04001B)) -#define MCF_SCM_CWIR (*(vuint8 *)(0xFC04001F)) -#define MCF_SCM_BCR (*(vuint32*)(0xFC040024)) -#define MCF_SCM_CFADR (*(vuint32*)(0xFC040070)) -#define MCF_SCM_CFIER (*(vuint8 *)(0xFC040075)) -#define MCF_SCM_CFLOC (*(vuint8 *)(0xFC040076)) -#define MCF_SCM_CFATR (*(vuint8 *)(0xFC040077)) -#define MCF_SCM_CFDTR (*(vuint32*)(0xFC04007C)) - -/* Bit definitions and macros for MCF_SCM_MPR */ -#define MCF_SCM_MPR_MPROT6(x) (((x)&0x0000000F)<<4) -#define MCF_SCM_MPR_MPROT5(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_MPR_MPROT4(x) (((x)&0x0000000F)<<12) -#define MCF_SCM_MPR_MPROT2(x) (((x)&0x0000000F)<<20) -#define MCF_SCM_MPR_MPROT1(x) (((x)&0x0000000F)<<24) -#define MCF_SCM_MPR_MPROT0(x) (((x)&0x0000000F)<<28) -#define MCF_SCM_MPR_MPROT_MTR (0x4) -#define MCF_SCM_MPR_MPROT_MTW (0x2) -#define MCF_SCM_MPR_MPROT_MPL (0x1) - -/* Bit definitions and macros for MCF_SCM_BMT */ -#define MCF_SCM_BMT_BMT(x) (((x)&0x00000007)<<0) -#define MCF_SCM_BMT_BME (0x00000008) -#define MCF_SCM_BMT_BMT_1024 (0x00000000) -#define MCF_SCM_BMT_BMT_512 (0x00000001) -#define MCF_SCM_BMT_BMT_256 (0x00000002) -#define MCF_SCM_BMT_BMT_128 (0x00000003) -#define MCF_SCM_BMT_BMT_64 (0x00000004) -#define MCF_SCM_BMT_BMT_32 (0x00000005) -#define MCF_SCM_BMT_BMT_16 (0x00000006) -#define MCF_SCM_BMT_BMT_8 (0x00000007) - -/* Bit definitions and macros for MCF_SCM_PACRA */ -#define MCF_SCM_PACRA_PACR2(x) (((x)&0x0000000F)<<20) -#define MCF_SCM_PACRA_PACR1(x) (((x)&0x0000000F)<<24) -#define MCF_SCM_PACRA_PACR0(x) (((x)&0x0000000F)<<28) -#define MCF_SCM_PACRA_PACR_SP (0x4) -#define MCF_SCM_PACRA_PACR_WP (0x2) -#define MCF_SCM_PACRA_PACR_TP (0x1) - -/* Bit definitions and macros for MCF_SCM_PACRB */ -#define MCF_SCM_PACRB_PACR12(x) (((x)&0x0000000F)<<12) -#define MCF_SCM_PACRB_PACR8(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SCM_PACRC */ -#define MCF_SCM_PACRC_PACR23(x) (((x)&0x0000000F)<<0) -#define MCF_SCM_PACRC_PACR22(x) (((x)&0x0000000F)<<4) -#define MCF_SCM_PACRC_PACR21(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_PACRC_PACR19(x) (((x)&0x0000000F)<<16) -#define MCF_SCM_PACRC_PACR18(x) (((x)&0x0000000F)<<20) -#define MCF_SCM_PACRC_PACR17(x) (((x)&0x0000000F)<<24) -#define MCF_SCM_PACRC_PACR16(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SCM_PACRD */ -#define MCF_SCM_PACRD_PACR31(x) (((x)&0x0000000F)<<0) -#define MCF_SCM_PACRD_PACR30(x) (((x)&0x0000000F)<<4) -#define MCF_SCM_PACRD_PACR29(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_PACRD_PACR28(x) (((x)&0x0000000F)<<12) -#define MCF_SCM_PACRD_PACR26(x) (((x)&0x0000000F)<<20) -#define MCF_SCM_PACRD_PACR25(x) (((x)&0x0000000F)<<24) -#define MCF_SCM_PACRD_PACR24(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SCM_PACRE */ -#define MCF_SCM_PACRE_PACR38(x) (((x)&0x0000000F)<<4) -#define MCF_SCM_PACRE_PACR37(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_PACRE_PACR36(x) (((x)&0x0000000F)<<12) -#define MCF_SCM_PACRE_PACR35(x) (((x)&0x0000000F)<<16) -#define MCF_SCM_PACRE_PACR34(x) (((x)&0x0000000F)<<20) -#define MCF_SCM_PACRE_PACR33(x) (((x)&0x0000000F)<<24) -#define MCF_SCM_PACRE_PACR32(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SCM_PACRF */ -#define MCF_SCM_PACRF_PACR47(x) (((x)&0x0000000F)<<0) -#define MCF_SCM_PACRF_PACR46(x) (((x)&0x0000000F)<<4) -#define MCF_SCM_PACRF_PACR45(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_PACRF_PACR44(x) (((x)&0x0000000F)<<12) -#define MCF_SCM_PACRF_PACR43(x) (((x)&0x0000000F)<<16) -#define MCF_SCM_PACRF_PACR42(x) (((x)&0x0000000F)<<20) -#define MCF_SCM_PACRF_PACR41(x) (((x)&0x0000000F)<<24) -#define MCF_SCM_PACRF_PACR40(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SCM_PACRG */ -#define MCF_SCM_PACRG_PACR48(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SCM_PACRH */ -#define MCF_SCM_PACRH_PACR58(x) (((x)&0x0000000F)<<20) -#define MCF_SCM_PACRH_PACR57(x) (((x)&0x0000000F)<<24) -#define MCF_SCM_PACRH_PACR56(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SCM_CWCR */ -#define MCF_SCM_CWCR_CWT(x) (((x)&0x001F)<<0) -#define MCF_SCM_CWCR_CWRI(x) (((x)&0x0003)<<5) -#define MCF_SCM_CWCR_CWE (0x0080) -#define MCF_SCM_CWCR_CWR_WH (0x0100) -#define MCF_SCM_CWCR_RO (0x8000) -#define MCF_SCM_CWCR_CWRI_INT (0x0000) -#define MCF_SCM_CWCR_CWRI_INT_THEN_RESET (0x0020) -#define MCF_SCM_CWCR_CWRI_RESET (0x0040) -#define MCF_SCM_CWCR_CWRI_WINDOW (0x0060) - -/* Bit definitions and macros for MCF_SCM_CWSR */ -#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_SCM_CWIR */ -#define MCF_SCM_CWIR_CWIC (0x01) -#define MCF_SCM_CWIR_CFEI (0x02) - -/* Bit definitions and macros for MCF_SCM_BCR */ -#define MCF_SCM_BCR_S1 (0x00000002) -#define MCF_SCM_BCR_S4 (0x00000010) -#define MCF_SCM_BCR_S6 (0x00000040) -#define MCF_SCM_BCR_S7 (0x00000080) -#define MCF_SCM_BCR_GBW (0x00000100) -#define MCF_SCM_BCR_GBR (0x00000200) - -/* Bit definitions and macros for MCF_SCM_CFADR */ -#define MCF_SCM_CFADR_ADDR(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_SCM_CFIER */ -#define MCF_SCM_CFIER_ECFEI (0x01) - -/* Bit definitions and macros for MCF_SCM_CFLOC */ -#define MCF_SCM_CFLOC_LOC (0x80) - -/* Bit definitions and macros for MCF_SCM_CFATR */ -#define MCF_SCM_CFATR_TYPE (0x01) -#define MCF_SCM_CFATR_MODE (0x02) -#define MCF_SCM_CFATR_CACHE (0x08) -#define MCF_SCM_CFATR_SIZE(x) (((x)&0x07)<<4) -#define MCF_SCM_CFATR_WRITE (0x80) - -/* Bit definitions and macros for MCF_SCM_CFDTR */ -#define MCF_SCM_CFDTR_CFDTR(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* -* -* Message Digest Hardware Accelerator (MDHA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_MDHA_MDMR (*(vuint32*)(0xEC080000)) -#define MCF_MDHA_MDCR (*(vuint32*)(0xEC080004)) -#define MCF_MDHA_MDCMR (*(vuint32*)(0xEC080008)) -#define MCF_MDHA_MDSR (*(vuint32*)(0xEC08000C)) -#define MCF_MDHA_MDISR (*(vuint32*)(0xEC080010)) -#define MCF_MDHA_MDIMR (*(vuint32*)(0xEC080014)) -#define MCF_MDHA_MDDSR (*(vuint32*)(0xEC08001C)) -#define MCF_MDHA_MDIN (*(vuint32*)(0xEC080020)) -#define MCF_MDHA_MDA0 (*(vuint32*)(0xEC080030)) -#define MCF_MDHA_MDB0 (*(vuint32*)(0xEC080034)) -#define MCF_MDHA_MDC0 (*(vuint32*)(0xEC080038)) -#define MCF_MDHA_MDD0 (*(vuint32*)(0xEC08003C)) -#define MCF_MDHA_MDE0 (*(vuint32*)(0xEC080040)) -#define MCF_MDHA_MDMDS (*(vuint32*)(0xEC080044)) -#define MCF_MDHA_MDA1 (*(vuint32*)(0xEC080070)) -#define MCF_MDHA_MDB1 (*(vuint32*)(0xEC080074)) -#define MCF_MDHA_MDC1 (*(vuint32*)(0xEC080078)) -#define MCF_MDHA_MDD1 (*(vuint32*)(0xEC08007C)) -#define MCF_MDHA_MDE1 (*(vuint32*)(0xEC080080)) - -/* Bit definitions and macros for MCF_MDHA_MDMR */ -#define MCF_MDHA_MDMR_ALG (0x00000001) -#define MCF_MDHA_MDMR_PDATA (0x00000004) -#define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3) -#define MCF_MDHA_MDMR_INIT (0x00000020) -#define MCF_MDHA_MDMR_IPAD (0x00000040) -#define MCF_MDHA_MDMR_OPAD (0x00000080) -#define MCF_MDHA_MDMR_SWAP (0x00000100) -#define MCF_MDHA_MDMR_MACFULL (0x00000200) -#define MCF_MDHA_MDMR_SSL (0x00000400) - -/* Bit definitions and macros for MCF_MDHA_MDCR */ -#define MCF_MDHA_MDCR_IE (0x00000001) -#define MCF_MDHA_MDCR_DMA (0x00000002) -#define MCF_MDHA_MDCR_ENDIAN (0x00000004) -#define MCF_MDHA_MDCR_DMAL(x) (((x)&0x0000001F)<<16) - -/* Bit definitions and macros for MCF_MDHA_MDCMR */ -#define MCF_MDHA_MDCMR_SWR (0x00000001) -#define MCF_MDHA_MDCMR_RI (0x00000002) -#define MCF_MDHA_MDCMR_CI (0x00000004) -#define MCF_MDHA_MDCMR_GO (0x00000008) - -/* Bit definitions and macros for MCF_MDHA_MDSR */ -#define MCF_MDHA_MDSR_INT (0x00000001) -#define MCF_MDHA_MDSR_DONE (0x00000002) -#define MCF_MDHA_MDSR_ERR (0x00000004) -#define MCF_MDHA_MDSR_RD (0x00000008) -#define MCF_MDHA_MDSR_BUSY (0x00000010) -#define MCF_MDHA_MDSR_END (0x00000020) -#define MCF_MDHA_MDSR_HSH (0x00000040) -#define MCF_MDHA_MDSR_GNW (0x00000080) -#define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8) -#define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13) -#define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16) - -/* Bit definitions and macros for MCF_MDHA_MDISR */ -#define MCF_MDHA_MDISR_IFO (0x00000001) -#define MCF_MDHA_MDISR_NON (0x00000004) -#define MCF_MDHA_MDISR_IME (0x00000010) -#define MCF_MDHA_MDISR_IDS (0x00000020) -#define MCF_MDHA_MDISR_RMDP (0x00000080) -#define MCF_MDHA_MDISR_ERE (0x00000100) -#define MCF_MDHA_MDISR_GTDS (0x00000200) - -/* Bit definitions and macros for MCF_MDHA_MDIMR */ -#define MCF_MDHA_MDIMR_IFO (0x00000001) -#define MCF_MDHA_MDIMR_NON (0x00000004) -#define MCF_MDHA_MDIMR_IME (0x00000010) -#define MCF_MDHA_MDIMR_IDS (0x00000020) -#define MCF_MDHA_MDIMR_RMDP (0x00000080) -#define MCF_MDHA_MDIMR_ERE (0x00000100) -#define MCF_MDHA_MDIMR_GTDS (0x00000200) - -/* Bit definitions and macros for MCF_MDHA_MDDSR */ -#define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_MDHA_MDIN */ -#define MCF_MDHA_MDIN_DATAIN(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_MDHA_MDA0 */ -#define MCF_MDHA_MDA0_DATA(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_MDHA_MDB0 */ -#define MCF_MDHA_MDB0_DATA(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_MDHA_MDC0 */ -#define MCF_MDHA_MDC0_DATA(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_MDHA_MDD0 */ -#define MCF_MDHA_MDD0_DATA(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_MDHA_MDE0 */ -#define MCF_MDHA_MDE0_DATA(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_MDHA_MDMDS */ -#define MCF_MDHA_MDMDS_DATASIZE(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_MDHA_MDA1 */ -#define MCF_MDHA_MDA1_DATA(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_MDHA_MDB1 */ -#define MCF_MDHA_MDB1_DATA(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_MDHA_MDC1 */ -#define MCF_MDHA_MDC1_DATA(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_MDHA_MDD1 */ -#define MCF_MDHA_MDD1_DATA(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_MDHA_MDE1 */ -#define MCF_MDHA_MDE1_DATA(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* -* -* Symmetric Key Hardware Accelerator (SKHA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SKHA_SKMR (*(vuint32*)(0xEC084000)) -#define MCF_SKHA_SKCR (*(vuint32*)(0xEC084004)) -#define MCF_SKHA_SKCMR (*(vuint32*)(0xEC084008)) -#define MCF_SKHA_SKSR (*(vuint32*)(0xEC08400C)) -#define MCF_SKHA_SKISR (*(vuint32*)(0xEC084010)) -#define MCF_SKHA_SKIMR (*(vuint32*)(0xEC084014)) -#define MCF_SKHA_SKKSR (*(vuint32*)(0xEC084018)) -#define MCF_SKHA_SKDSR (*(vuint32*)(0xEC08401C)) -#define MCF_SKHA_SKIN (*(vuint32*)(0xEC084020)) -#define MCF_SKHA_SKOUT (*(vuint32*)(0xEC084024)) -#define MCF_SKHA_SKK0 (*(vuint32*)(0xEC084030)) -#define MCF_SKHA_SKK1 (*(vuint32*)(0xEC084034)) -#define MCF_SKHA_SKK2 (*(vuint32*)(0xEC084038)) -#define MCF_SKHA_SKK3 (*(vuint32*)(0xEC08403C)) -#define MCF_SKHA_SKK4 (*(vuint32*)(0xEC084040)) -#define MCF_SKHA_SKK5 (*(vuint32*)(0xEC084044)) -#define MCF_SKHA_SKK(x) (*(vuint32*)(0xEC084030+((x)*0x004))) -#define MCF_SKHA_SKC0 (*(vuint32*)(0xEC084070)) -#define MCF_SKHA_SKC1 (*(vuint32*)(0xEC084074)) -#define MCF_SKHA_SKC2 (*(vuint32*)(0xEC084078)) -#define MCF_SKHA_SKC3 (*(vuint32*)(0xEC08407C)) -#define MCF_SKHA_SKC4 (*(vuint32*)(0xEC084080)) -#define MCF_SKHA_SKC5 (*(vuint32*)(0xEC084084)) -#define MCF_SKHA_SKC6 (*(vuint32*)(0xEC084088)) -#define MCF_SKHA_SKC7 (*(vuint32*)(0xEC08408C)) -#define MCF_SKHA_SKC8 (*(vuint32*)(0xEC084090)) -#define MCF_SKHA_SKC9 (*(vuint32*)(0xEC084094)) -#define MCF_SKHA_SKC10 (*(vuint32*)(0xEC084098)) -#define MCF_SKHA_SKC11 (*(vuint32*)(0xEC08409C)) -#define MCF_SKHA_SKC(x) (*(vuint32*)(0xEC084070+((x)*0x004))) - -/* Bit definitions and macros for MCF_SKHA_SKMR */ -#define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0) -#define MCF_SKHA_SKMR_DIR (0x00000004) -#define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3) -#define MCF_SKHA_SKMR_DKP (0x00000100) -#define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9) -#define MCF_SKHA_SKMR_CM_ECB (0x00000000) -#define MCF_SKHA_SKMR_CM_CBC (0x00000008) -#define MCF_SKHA_SKMR_CM_CTR (0x00000018) -#define MCF_SKHA_SKMR_DIR_DEC (0x00000000) -#define MCF_SKHA_SKMR_DIR_ENC (0x00000004) -#define MCF_SKHA_SKMR_ALG_AES (0x00000000) -#define MCF_SKHA_SKMR_ALG_DES (0x00000001) -#define MCF_SKHA_SKMR_ALG_TDES (0x00000002) - -/* Bit definitions and macros for MCF_SKHA_SKCR */ -#define MCF_SKHA_SKCR_IE (0x00000001) -#define MCF_SKHA_SKCR_IDMA (0x00000002) -#define MCF_SKHA_SKCR_ODMA (0x00000004) -#define MCF_SKHA_SKCR_ENDIAN (0x00000008) -#define MCF_SKHA_SKCR_IDMAL(x) (((x)&0x0000003F)<<16) -#define MCF_SKHA_SKCR_ODMAL(x) (((x)&0x0000003F)<<24) - -/* Bit definitions and macros for MCF_SKHA_SKCMR */ -#define MCF_SKHA_SKCMR_SWR (0x00000001) -#define MCF_SKHA_SKCMR_RI (0x00000002) -#define MCF_SKHA_SKCMR_CI (0x00000004) -#define MCF_SKHA_SKCMR_GO (0x00000008) - -/* Bit definitions and macros for MCF_SKHA_SKSR */ -#define MCF_SKHA_SKSR_INT (0x00000001) -#define MCF_SKHA_SKSR_DONE (0x00000002) -#define MCF_SKHA_SKSR_ERR (0x00000004) -#define MCF_SKHA_SKSR_RD (0x00000008) -#define MCF_SKHA_SKSR_BUSY (0x00000010) -#define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16) -#define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_SKHA_SKISR */ -#define MCF_SKHA_SKISR_IFO (0x00000001) -#define MCF_SKHA_SKISR_OFU (0x00000002) -#define MCF_SKHA_SKISR_NEIF (0x00000004) -#define MCF_SKHA_SKISR_NEOF (0x00000008) -#define MCF_SKHA_SKISR_IME (0x00000010) -#define MCF_SKHA_SKISR_DSE (0x00000020) -#define MCF_SKHA_SKISR_KSE (0x00000040) -#define MCF_SKHA_SKISR_RMDP (0x00000080) -#define MCF_SKHA_SKISR_ERE (0x00000100) -#define MCF_SKHA_SKISR_KPE (0x00000200) -#define MCF_SKHA_SKISR_KRE (0x00000400) -#define MCF_SKHA_SKISR_DRL (0x00000800) - -/* Bit definitions and macros for MCF_SKHA_SKIMR */ -#define MCF_SKHA_SKIMR_IFO (0x00000001) -#define MCF_SKHA_SKIMR_OFU (0x00000002) -#define MCF_SKHA_SKIMR_NEIF (0x00000004) -#define MCF_SKHA_SKIMR_NEOF (0x00000008) -#define MCF_SKHA_SKIMR_IME (0x00000010) -#define MCF_SKHA_SKIMR_DSE (0x00000020) -#define MCF_SKHA_SKIMR_KSE (0x00000040) -#define MCF_SKHA_SKIMR_RMDP (0x00000080) -#define MCF_SKHA_SKIMR_ERE (0x00000100) -#define MCF_SKHA_SKIMR_KPE (0x00000200) -#define MCF_SKHA_SKIMR_KRE (0x00000400) -#define MCF_SKHA_SKIMR_DRL (0x00000800) - -/* Bit definitions and macros for MCF_SKHA_SKKSR */ -#define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0) - -/* Bit definitions and macros for MCF_SKHA_SKDSR */ -#define MCF_SKHA_SKDSR_DATASIZE(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_SKHA_SKIN */ -#define MCF_SKHA_SKIN_DATAIN(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_SKHA_SKOUT */ -#define MCF_SKHA_SKOUT_DATAOUT(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_SKHA_SKK */ -#define MCF_SKHA_SKK_KEY(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_SKHA_SKC */ -#define MCF_SKHA_SKC_CONTEXT(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* -* -* Random Number Generator (RNG) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RNG_RNGCR (*(vuint32*)(0xEC088000)) -#define MCF_RNG_RNGSR (*(vuint32*)(0xEC088004)) -#define MCF_RNG_RNGER (*(vuint32*)(0xEC088008)) -#define MCF_RNG_RNGOUT (*(vuint32*)(0xEC08800C)) - -/* Bit definitions and macros for MCF_RNG_RNGCR */ -#define MCF_RNG_RNGCR_GO (0x00000001) -#define MCF_RNG_RNGCR_HA (0x00000002) -#define MCF_RNG_RNGCR_IM (0x00000004) -#define MCF_RNG_RNGCR_CI (0x00000008) - -/* Bit definitions and macros for MCF_RNG_RNGSR */ -#define MCF_RNG_RNGSR_SV (0x00000001) -#define MCF_RNG_RNGSR_LRS (0x00000002) -#define MCF_RNG_RNGSR_FUF (0x00000004) -#define MCF_RNG_RNGSR_EI (0x00000008) -#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) -#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) - -/* Bit definitions and macros for MCF_RNG_RNGER */ -#define MCF_RNG_RNGER_ENTROPY(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_RNG_RNGOUT */ -#define MCF_RNG_RNGOUT_OUTPUT(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* -* -* Power Management Module (PMM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PMM_WCR (*(vuint8 *)(0xFC040013)) -#define MCF_PMM_PPMSR0 (*(vuint8 *)(0xFC04002C)) -#define MCF_PMM_PPMSR1 (*(vuint8 *)(0xFC04002E)) -#define MCF_PMM_PPMCR0 (*(vuint8 *)(0xFC04002D)) -#define MCF_PMM_PPMCR1 (*(vuint8 *)(0xFC04002F)) -#define MCF_PMM_PPMHR0 (*(vuint32*)(0xFC040030)) -#define MCF_PMM_PPMLR0 (*(vuint32*)(0xFC040034)) -#define MCF_PMM_PPMHR1 (*(vuint32*)(0xFC040038)) -#define MCF_PMM_LPCR (*(vuint8 *)(0xFC0A0007)) - -/* Bit definitions and macros for MCF_PMM_WCR */ -#define MCF_PMM_WCR_PRILVL(x) (((x)&0x07)<<0) -#define MCF_PMM_WCR_ENBWCR (0x80) - -/* Bit definitions and macros for MCF_PMM_PPMSR */ -#define MCF_PMM_PPMSR_SMCD(x) (((x)&0x3F)<<0) -#define MCF_PMM_PPMSR_SAMCD (0x40) - -/* Bit definitions and macros for MCF_PMM_PPMCR */ -#define MCF_PMM_PPMCR_CMCD(x) (((x)&0x3F)<<0) -#define MCF_PMM_PPMCR_CAMCD (0x40) - -/* Bit definitions and macros for MCF_PMM_PPMHR0 */ -#define MCF_PMM_PPMHR0_CD32 (0x00000001) -#define MCF_PMM_PPMHR0_CD33 (0x00000002) -#define MCF_PMM_PPMHR0_CD34 (0x00000004) -#define MCF_PMM_PPMHR0_CD35 (0x00000008) -#define MCF_PMM_PPMHR0_CD36 (0x00000010) -#define MCF_PMM_PPMHR0_CD37 (0x00000020) -#define MCF_PMM_PPMHR0_CD38 (0x00000040) -#define MCF_PMM_PPMHR0_CD40 (0x00000100) -#define MCF_PMM_PPMHR0_CD41 (0x00000200) -#define MCF_PMM_PPMHR0_CD42 (0x00000400) -#define MCF_PMM_PPMHR0_CD43 (0x00000800) -#define MCF_PMM_PPMHR0_CD44 (0x00001000) -#define MCF_PMM_PPMHR0_CD45 (0x00002000) -#define MCF_PMM_PPMHR0_CD46 (0x00004000) -#define MCF_PMM_PPMHR0_CD47 (0x00008000) -#define MCF_PMM_PPMHR0_CD48 (0x00010000) - -/* Bit definitions and macros for MCF_PMM_PPMLR0 */ -#define MCF_PMM_PPMLR0_CD2 (0x00000004) -#define MCF_PMM_PPMLR0_CD8 (0x00000100) -#define MCF_PMM_PPMLR0_CD12 (0x00001000) -#define MCF_PMM_PPMLR0_CD17 (0x00020000) -#define MCF_PMM_PPMLR0_CD18 (0x00040000) -#define MCF_PMM_PPMLR0_CD19 (0x00080000) -#define MCF_PMM_PPMLR0_CD21 (0x00200000) -#define MCF_PMM_PPMLR0_CD22 (0x00400000) -#define MCF_PMM_PPMLR0_CD23 (0x00800000) -#define MCF_PMM_PPMLR0_CD24 (0x01000000) -#define MCF_PMM_PPMLR0_CD25 (0x02000000) -#define MCF_PMM_PPMLR0_CD26 (0x04000000) -#define MCF_PMM_PPMLR0_CD28 (0x10000000) -#define MCF_PMM_PPMLR0_CD29 (0x20000000) -#define MCF_PMM_PPMLR0_CD30 (0x40000000) -#define MCF_PMM_PPMLR0_CD31 (0x80000000) - -/* Bit definitions and macros for MCF_PMM_PPMHR1 */ -#define MCF_PMM_PPMHR1_CD32 (0x00000001) -#define MCF_PMM_PPMHR1_CD33 (0x00000002) -#define MCF_PMM_PPMHR1_CD34 (0x00000004) - -/* Bit definitions and macros for MCF_PMM_LPCR */ -#define MCF_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF_PMM_LPCR_FWKUP (0x20) -#define MCF_PMM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF_PMM_LPCR_LPMD_RUN (0x00) -#define MCF_PMM_LPCR_LPMD_DOZE (0x40) -#define MCF_PMM_LPCR_LPMD_WAIT (0x80) -#define MCF_PMM_LPCR_LPMD_STOP (0xC0) -#define MCF_PMM_LPCR_STPMD_SYS_DISABLED (0x00) -#define MCF_PMM_LPCR_STPMD_SYS_BUSCLK_DISABLED (0x04) -#define MCF_PMM_LPCR_STPMD_ONLY_OSC_ENABLED (0x08) -#define MCF_PMM_LPCR_STPMD_ALL_DISABLED (0x0C) - -/********************************************************************* -* -* Cross-bar switch (XBS) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_XBS_PRS1 (*(vuint32*)(0xFC004100)) -#define MCF_XBS_PRS2 (*(vuint32*)(0xFC004200)) -#define MCF_XBS_PRS3 (*(vuint32*)(0xFC004300)) -#define MCF_XBS_PRS4 (*(vuint32*)(0xFC004400)) -#define MCF_XBS_PRS5 (*(vuint32*)(0xFC004500)) -#define MCF_XBS_PRS6 (*(vuint32*)(0xFC004600)) -#define MCF_XBS_PRS7 (*(vuint32*)(0xFC004700)) -#define MCF_XBS_PRS(x) (*(vuint32*)(0xFC004100+((x-1)*0x100))) -#define MCF_XBS_CRS1 (*(vuint32*)(0xFC004110)) -#define MCF_XBS_CRS2 (*(vuint32*)(0xFC004210)) -#define MCF_XBS_CRS3 (*(vuint32*)(0xFC004310)) -#define MCF_XBS_CRS4 (*(vuint32*)(0xFC004410)) -#define MCF_XBS_CRS5 (*(vuint32*)(0xFC004510)) -#define MCF_XBS_CRS6 (*(vuint32*)(0xFC004610)) -#define MCF_XBS_CRS7 (*(vuint32*)(0xFC004710)) -#define MCF_XBS_CRS(x) (*(vuint32*)(0xFC004110+((x-1)*0x100))) - -/* Bit definitions and macros for MCF_XBS_PRS */ -#define MCF_XBS_PRS_M0(x) (((x)&0x00000007)<<0) -#define MCF_XBS_PRS_M1(x) (((x)&0x00000007)<<4) -#define MCF_XBS_PRS_M2(x) (((x)&0x00000007)<<8) -#define MCF_XBS_PRS_M4(x) (((x)&0x00000007)<<16) -#define MCF_XBS_PRS_M5(x) (((x)&0x00000007)<<20) -#define MCF_XBS_PRS_M6(x) (((x)&0x00000007)<<24) - -/* Bit definitions and macros for MCF_XBS_CRS */ -#define MCF_XBS_CRS_PARK(x) (((x)&0x00000007)<<0) -#define MCF_XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) -#define MCF_XBS_CRS_ARB (0x00000100) -#define MCF_XBS_CRS_RO (0x80000000) -#define MCF_XBS_CRS_PCTL_PARK_FIELD (0x00000000) -#define MCF_XBS_CRS_PCTL_PARK_ON_LAST (0x00000010) -#define MCF_XBS_CRS_PCTL_PARK_NO_MASTER (0x00000020) -#define MCF_XBS_CRS_PCTL_PARK_CORE (0x00000000) -#define MCF_XBS_CRS_PCTL_PARK_EDMA (0x00000001) -#define MCF_XBS_CRS_PCTL_PARK_FEC (0x00000002) - -/********************************************************************* -* -* FlexBus Chip Selects (FBCS) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_FBCS0_CSAR (*(vuint32*)(0xFC008000)) -#define MCF_FBCS0_CSMR (*(vuint32*)(0xFC008004)) -#define MCF_FBCS0_CSCR (*(vuint32*)(0xFC008008)) -#define MCF_FBCS1_CSAR (*(vuint32*)(0xFC00800C)) -#define MCF_FBCS1_CSMR (*(vuint32*)(0xFC008010)) -#define MCF_FBCS1_CSCR (*(vuint32*)(0xFC008014)) -#define MCF_FBCS2_CSAR (*(vuint32*)(0xFC008018)) -#define MCF_FBCS2_CSMR (*(vuint32*)(0xFC00801C)) -#define MCF_FBCS2_CSCR (*(vuint32*)(0xFC008020)) -#define MCF_FBCS3_CSAR (*(vuint32*)(0xFC008024)) -#define MCF_FBCS3_CSMR (*(vuint32*)(0xFC008028)) -#define MCF_FBCS3_CSCR (*(vuint32*)(0xFC00802C)) -#define MCF_FBCS4_CSAR (*(vuint32*)(0xFC008030)) -#define MCF_FBCS4_CSMR (*(vuint32*)(0xFC008034)) -#define MCF_FBCS4_CSCR (*(vuint32*)(0xFC008038)) -#define MCF_FBCS5_CSAR (*(vuint32*)(0xFC00803C)) -#define MCF_FBCS5_CSMR (*(vuint32*)(0xFC008040)) -#define MCF_FBCS5_CSCR (*(vuint32*)(0xFC008044)) -#define MCF_FBCS_CSAR(x) (*(vuint32*)(0xFC008000+((x)*0x00C))) -#define MCF_FBCS_CSMR(x) (*(vuint32*)(0xFC008004+((x)*0x00C))) -#define MCF_FBCS_CSCR(x) (*(vuint32*)(0xFC008008+((x)*0x00C))) - -/* Bit definitions and macros for MCF_FBCS_CSAR */ -#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) - -/* Bit definitions and macros for MCF_FBCS_CSMR */ -#define MCF_FBCS_CSMR_V (0x00000001) -#define MCF_FBCS_CSMR_WP (0x00000100) -#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) -#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) -#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) -#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) -#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) -#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) -#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) -#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) -#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) -#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) -#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) -#define MCF_FBCS_CSMR_BAM_8M (0x007F0000) -#define MCF_FBCS_CSMR_BAM_4M (0x003F0000) -#define MCF_FBCS_CSMR_BAM_2M (0x001F0000) -#define MCF_FBCS_CSMR_BAM_1M (0x000F0000) -#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) -#define MCF_FBCS_CSMR_BAM_512K (0x00070000) -#define MCF_FBCS_CSMR_BAM_256K (0x00030000) -#define MCF_FBCS_CSMR_BAM_128K (0x00010000) -#define MCF_FBCS_CSMR_BAM_64K (0x00000000) - -/* Bit definitions and macros for MCF_FBCS_CSCR */ -#define MCF_FBCS_CSCR_BSTW (0x00000008) -#define MCF_FBCS_CSCR_BSTR (0x00000010) -#define MCF_FBCS_CSCR_BEM (0x00000020) -#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) -#define MCF_FBCS_CSCR_AA (0x00000100) -#define MCF_FBCS_CSCR_SBM (0x00000200) -#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) -#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) -#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) -#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) -#define MCF_FBCS_CSCR_SWSEN (0x00800000) -#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) -#define MCF_FBCS_CSCR_PS_8 (0x00000040) -#define MCF_FBCS_CSCR_PS_16 (0x00000080) -#define MCF_FBCS_CSCR_PS_32 (0x00000000) - -/********************************************************************* -* -* FlexCAN Module (CAN) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CAN_CANMCR (*(vuint32*)(0xFC020000)) -#define MCF_CAN_CANCTRL (*(vuint32*)(0xFC020004)) -#define MCF_CAN_TIMER (*(vuint32*)(0xFC020008)) -#define MCF_CAN_RXGMASK (*(vuint32*)(0xFC020010)) -#define MCF_CAN_RX14MASK (*(vuint32*)(0xFC020014)) -#define MCF_CAN_RX15MASK (*(vuint32*)(0xFC020018)) -#define MCF_CAN_ERRCNT (*(vuint32*)(0xFC02001C)) -#define MCF_CAN_ERRSTAT (*(vuint32*)(0xFC020020)) -#define MCF_CAN_IMASK (*(vuint32*)(0xFC020028)) -#define MCF_CAN_IFLAG (*(vuint32*)(0xFC020030)) - -/* Bit definitions and macros for MCF_CAN_CANMCR */ -#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) -#define MCF_CAN_CANMCR_LPMACK (0x00100000) -#define MCF_CAN_CANMCR_SUPV (0x00800000) -#define MCF_CAN_CANMCR_FRZACK (0x01000000) -#define MCF_CAN_CANMCR_SOFTRST (0x02000000) -#define MCF_CAN_CANMCR_NOTRDY (0x08000000) -#define MCF_CAN_CANMCR_HALT (0x10000000) -#define MCF_CAN_CANMCR_FRZ (0x40000000) -#define MCF_CAN_CANMCR_MDIS (0x80000000) - -/* Bit definitions and macros for MCF_CAN_CANCTRL */ -#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) -#define MCF_CAN_CANCTRL_LOM (0x00000008) -#define MCF_CAN_CANCTRL_LBUF (0x00000010) -#define MCF_CAN_CANCTRL_TSYNC (0x00000020) -#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) -#define MCF_CAN_CANCTRL_SAMP (0x00000080) -#define MCF_CAN_CANCTRL_LPB (0x00001000) -#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) -#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) -#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) -#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) -#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) -#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) -#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_CAN_TIMER */ -#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RXGMASK */ -#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX14MASK */ -#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX15MASK */ -#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_ERRCNT */ -#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) -#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for MCF_CAN_ERRSTAT */ -#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) -#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) -#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) -#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) -#define MCF_CAN_ERRSTAT_TXRX (0x00000040) -#define MCF_CAN_ERRSTAT_IDLE (0x00000080) -#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) -#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) -#define MCF_CAN_ERRSTAT_STFERR (0x00000400) -#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) -#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) -#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) -#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) -#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) -#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) -#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) - -/* Bit definitions and macros for MCF_CAN_IMASK */ -#define MCF_CAN_IMASK_BUF0M (0x00000001) -#define MCF_CAN_IMASK_BUF1M (0x00000002) -#define MCF_CAN_IMASK_BUF2M (0x00000004) -#define MCF_CAN_IMASK_BUF3M (0x00000008) -#define MCF_CAN_IMASK_BUF4M (0x00000010) -#define MCF_CAN_IMASK_BUF5M (0x00000020) -#define MCF_CAN_IMASK_BUF6M (0x00000040) -#define MCF_CAN_IMASK_BUF7M (0x00000080) -#define MCF_CAN_IMASK_BUF8M (0x00000100) -#define MCF_CAN_IMASK_BUF9M (0x00000200) -#define MCF_CAN_IMASK_BUF10M (0x00000400) -#define MCF_CAN_IMASK_BUF11M (0x00000800) -#define MCF_CAN_IMASK_BUF12M (0x00001000) -#define MCF_CAN_IMASK_BUF13M (0x00002000) -#define MCF_CAN_IMASK_BUF14M (0x00004000) -#define MCF_CAN_IMASK_BUF15M (0x00008000) -#define MCF_CAN_IMASK_BUF(x) (1<<x) - -/* Bit definitions and macros for MCF_CAN_IFLAG */ -#define MCF_CAN_IFLAG_BUF0I (0x00000001) -#define MCF_CAN_IFLAG_BUF1I (0x00000002) -#define MCF_CAN_IFLAG_BUF2I (0x00000004) -#define MCF_CAN_IFLAG_BUF3I (0x00000008) -#define MCF_CAN_IFLAG_BUF4I (0x00000010) -#define MCF_CAN_IFLAG_BUF5I (0x00000020) -#define MCF_CAN_IFLAG_BUF6I (0x00000040) -#define MCF_CAN_IFLAG_BUF7I (0x00000080) -#define MCF_CAN_IFLAG_BUF8I (0x00000100) -#define MCF_CAN_IFLAG_BUF9I (0x00000200) -#define MCF_CAN_IFLAG_BUF10I (0x00000400) -#define MCF_CAN_IFLAG_BUF11I (0x00000800) -#define MCF_CAN_IFLAG_BUF12I (0x00001000) -#define MCF_CAN_IFLAG_BUF13I (0x00002000) -#define MCF_CAN_IFLAG_BUF14I (0x00004000) -#define MCF_CAN_IFLAG_BUF15I (0x00008000) -#define MCF_CAN_IFLAG_BUF(x) (1<<x) - -/********************************************************************* -* -* Fast Ethernet Controller (FEC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_FEC_EIR (*(vuint32*)(0xFC030004)) -#define MCF_FEC_EIMR (*(vuint32*)(0xFC030008)) -#define MCF_FEC_RDAR (*(vuint32*)(0xFC030010)) -#define MCF_FEC_TDAR (*(vuint32*)(0xFC030014)) -#define MCF_FEC_ECR (*(vuint32*)(0xFC030024)) -#define MCF_FEC_MMFR (*(vuint32*)(0xFC030040)) -#define MCF_FEC_MSCR (*(vuint32*)(0xFC030044)) -#define MCF_FEC_MIBC (*(vuint32*)(0xFC030064)) -#define MCF_FEC_RCR (*(vuint32*)(0xFC030084)) -#define MCF_FEC_TCR (*(vuint32*)(0xFC0300C4)) -#define MCF_FEC_PALR (*(vuint32*)(0xFC0300E4)) -#define MCF_FEC_PAUR (*(vuint32*)(0xFC0300E8)) -#define MCF_FEC_OPD (*(vuint32*)(0xFC0300EC)) -#define MCF_FEC_IAUR (*(vuint32*)(0xFC030118)) -#define MCF_FEC_IALR (*(vuint32*)(0xFC03011C)) -#define MCF_FEC_GAUR (*(vuint32*)(0xFC030120)) -#define MCF_FEC_GALR (*(vuint32*)(0xFC030124)) -#define MCF_FEC_TFWR (*(vuint32*)(0xFC030144)) -#define MCF_FEC_FRBR (*(vuint32*)(0xFC03014C)) -#define MCF_FEC_FRSR (*(vuint32*)(0xFC030150)) -#define MCF_FEC_ERDSR (*(vuint32*)(0xFC030180)) -#define MCF_FEC_ETDSR (*(vuint32*)(0xFC030184)) -#define MCF_FEC_EMRBR (*(vuint32*)(0xFC030188)) -#define MCF_FEC_RMON_T_DROP (*(vuint32*)(0xFC030200)) -#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(0xFC030204)) -#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(0xFC030208)) -#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(0xFC03020C)) -#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(0xFC030210)) -#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(0xFC030214)) -#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(0xFC030218)) -#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(0xFC03021C)) -#define MCF_FEC_RMON_T_JAB (*(vuint32*)(0xFC030220)) -#define MCF_FEC_RMON_T_COL (*(vuint32*)(0xFC030224)) -#define MCF_FEC_RMON_T_P64 (*(vuint32*)(0xFC030228)) -#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(0xFC03022C)) -#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(0xFC030230)) -#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(0xFC030234)) -#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(0xFC030238)) -#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(0xFC03023C)) -#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(0xFC030240)) -#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(0xFC030244)) -#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(0xFC030248)) -#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(0xFC03024C)) -#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(0xFC030250)) -#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(0xFC030254)) -#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(0xFC030258)) -#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(0xFC03025C)) -#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(0xFC030260)) -#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(0xFC030264)) -#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(0xFC030268)) -#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(0xFC03026C)) -#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(0xFC030270)) -#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(0xFC030274)) -#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(0xFC030284)) -#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(0xFC030288)) -#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(0xFC03028C)) -#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(0xFC030290)) -#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(0xFC030294)) -#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(0xFC030298)) -#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(0xFC03029C)) -#define MCF_FEC_RMON_R_JAB (*(vuint32*)(0xFC0302A0)) -#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(0xFC0302A4)) -#define MCF_FEC_RMON_R_P64 (*(vuint32*)(0xFC0302A8)) -#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(0xFC0302AC)) -#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(0xFC0302B0)) -#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(0xFC0302B4)) -#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(0xFC0302B8)) -#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(0xFC0302C0)) -#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(0xFC0302BC)) -#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(0xFC0302C4)) -#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(0xFC0302C8)) -#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(0xFC0302CC)) -#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(0xFC0302D0)) -#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(0xFC0302D4)) -#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(0xFC0302D8)) -#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(0xFC0302DC)) -#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(0xFC0302E0)) - -/* Bit definitions and macros for MCF_FEC_EIR */ -#define MCF_FEC_EIR_UN (0x00080000) -#define MCF_FEC_EIR_RL (0x00100000) -#define MCF_FEC_EIR_LC (0x00200000) -#define MCF_FEC_EIR_EBERR (0x00400000) -#define MCF_FEC_EIR_MII (0x00800000) -#define MCF_FEC_EIR_RXB (0x01000000) -#define MCF_FEC_EIR_RXF (0x02000000) -#define MCF_FEC_EIR_TXB (0x04000000) -#define MCF_FEC_EIR_TXF (0x08000000) -#define MCF_FEC_EIR_GRA (0x10000000) -#define MCF_FEC_EIR_BABT (0x20000000) -#define MCF_FEC_EIR_BABR (0x40000000) -#define MCF_FEC_EIR_HBERR (0x80000000) -#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) - -/* Bit definitions and macros for MCF_FEC_EIMR */ -#define MCF_FEC_EIMR_UN (0x00080000) -#define MCF_FEC_EIMR_RL (0x00100000) -#define MCF_FEC_EIMR_LC (0x00200000) -#define MCF_FEC_EIMR_EBERR (0x00400000) -#define MCF_FEC_EIMR_MII (0x00800000) -#define MCF_FEC_EIMR_RXB (0x01000000) -#define MCF_FEC_EIMR_RXF (0x02000000) -#define MCF_FEC_EIMR_TXB (0x04000000) -#define MCF_FEC_EIMR_TXF (0x08000000) -#define MCF_FEC_EIMR_GRA (0x10000000) -#define MCF_FEC_EIMR_BABT (0x20000000) -#define MCF_FEC_EIMR_BABR (0x40000000) -#define MCF_FEC_EIMR_HBERR (0x80000000) -#define MCF_FEC_EIMR_MASK_ALL (0x00000000) -#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) - -/* Bit definitions and macros for MCF_FEC_RDAR */ -#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_TDAR */ -#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_ECR */ -#define MCF_FEC_ECR_RESET (0x00000001) -#define MCF_FEC_ECR_ETHER_EN (0x00000002) - -/* Bit definitions and macros for MCF_FEC_MMFR */ -#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) -#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) -#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) -#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) -#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) -#define MCF_FEC_MMFR_ST_01 (0x40000000) -#define MCF_FEC_MMFR_OP_READ (0x20000000) -#define MCF_FEC_MMFR_OP_WRITE (0x10000000) -#define MCF_FEC_MMFR_TA_10 (0x00020000) - -/* Bit definitions and macros for MCF_FEC_MSCR */ -#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) -#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) - -/* Bit definitions and macros for MCF_FEC_MIBC */ -#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) -#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) - -/* Bit definitions and macros for MCF_FEC_RCR */ -#define MCF_FEC_RCR_LOOP (0x00000001) -#define MCF_FEC_RCR_DRT (0x00000002) -#define MCF_FEC_RCR_MII_MODE (0x00000004) -#define MCF_FEC_RCR_PROM (0x00000008) -#define MCF_FEC_RCR_BC_REJ (0x00000010) -#define MCF_FEC_RCR_FCE (0x00000020) -#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) - -/* Bit definitions and macros for MCF_FEC_TCR */ -#define MCF_FEC_TCR_GTS (0x00000001) -#define MCF_FEC_TCR_HBC (0x00000002) -#define MCF_FEC_TCR_FDEN (0x00000004) -#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) -#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) - -/* Bit definitions and macros for MCF_FEC_PALR */ -#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_PAUR */ -#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_OPD */ -#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_IAUR */ -#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_IALR */ -#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_GAUR */ -#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_GALR */ -#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_FEC_TFWR */ -#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) - -/* Bit definitions and macros for MCF_FEC_FRBR */ -#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_FRSR */ -#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_ERDSR */ -#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_ETDSR */ -#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_EMRBR */ -#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) - -#define MCF_FEC_TxBD_R 0x8000 -#define MCF_FEC_TxBD_BUSY 0x4000 -#define MCF_FEC_TxBD_TO1 0x4000 -#define MCF_FEC_TxBD_W 0x2000 -#define MCF_FEC_TxBD_TO2 0x1000 -#define MCF_FEC_TxBD_FIRST 0x1000 -#define MCF_FEC_TxBD_L 0x0800 -#define MCF_FEC_TxBD_TC 0x0400 -#define MCF_FEC_TxBD_DEF 0x0200 -#define MCF_FEC_TxBD_HB 0x0100 -#define MCF_FEC_TxBD_LC 0x0080 -#define MCF_FEC_TxBD_RL 0x0040 -#define MCF_FEC_TxBD_UN 0x0002 -#define MCF_FEC_TxBD_CSL 0x0001 -#define MCF_FEC_RxBD_E 0x8000 -#define MCF_FEC_RxBD_INUSE 0x4000 -#define MCF_FEC_RxBD_R01 0x4000 -#define MCF_FEC_RxBD_W 0x2000 -#define MCF_FEC_RxBD_R02 0x1000 -#define MCF_FEC_RxBD_L 0x0800 -#define MCF_FEC_RxBD_M 0x0100 -#define MCF_FEC_RxBD_BC 0x0080 -#define MCF_FEC_RxBD_MC 0x0040 -#define MCF_FEC_RxBD_LG 0x0020 -#define MCF_FEC_RxBD_NO 0x0010 -#define MCF_FEC_RxBD_CR 0x0004 -#define MCF_FEC_RxBD_OV 0x0002 -#define MCF_FEC_RxBD_TR 0x0001 - -/********************************************************************* -* -* Enhanced DMA (EDMA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_EDMA_CR (*(vuint32*)(0xFC044000)) -#define MCF_EDMA_ES (*(vuint32*)(0xFC044004)) -#define MCF_EDMA_ERQ (*(vuint16*)(0xFC04400E)) -#define MCF_EDMA_EEI (*(vuint16*)(0xFC044016)) -#define MCF_EDMA_SERQ (*(vuint8 *)(0xFC044018)) -#define MCF_EDMA_CERQ (*(vuint8 *)(0xFC044019)) -#define MCF_EDMA_SEEI (*(vuint8 *)(0xFC04401A)) -#define MCF_EDMA_CEEI (*(vuint8 *)(0xFC04401B)) -#define MCF_EDMA_CINT (*(vuint8 *)(0xFC04401C)) -#define MCF_EDMA_CERR (*(vuint8 *)(0xFC04401D)) -#define MCF_EDMA_SSRT (*(vuint8 *)(0xFC04401E)) -#define MCF_EDMA_CDNE (*(vuint8 *)(0xFC04401F)) -#define MCF_EDMA_INT (*(vuint16*)(0xFC044026)) -#define MCF_EDMA_ERR (*(vuint16*)(0xFC04402E)) -#define MCF_EDMA_DCHPRI0 (*(vuint8 *)(0xFC044100)) -#define MCF_EDMA_DCHPRI1 (*(vuint8 *)(0xFC044101)) -#define MCF_EDMA_DCHPRI2 (*(vuint8 *)(0xFC044102)) -#define MCF_EDMA_DCHPRI3 (*(vuint8 *)(0xFC044103)) -#define MCF_EDMA_DCHPRI4 (*(vuint8 *)(0xFC044104)) -#define MCF_EDMA_DCHPRI5 (*(vuint8 *)(0xFC044105)) -#define MCF_EDMA_DCHPRI6 (*(vuint8 *)(0xFC044106)) -#define MCF_EDMA_DCHPRI7 (*(vuint8 *)(0xFC044107)) -#define MCF_EDMA_DCHPRI8 (*(vuint8 *)(0xFC044108)) -#define MCF_EDMA_DCHPRI9 (*(vuint8 *)(0xFC044109)) -#define MCF_EDMA_DCHPRI10 (*(vuint8 *)(0xFC04410A)) -#define MCF_EDMA_DCHPRI11 (*(vuint8 *)(0xFC04410B)) -#define MCF_EDMA_DCHPRI12 (*(vuint8 *)(0xFC04410C)) -#define MCF_EDMA_DCHPRI13 (*(vuint8 *)(0xFC04410D)) -#define MCF_EDMA_DCHPRI14 (*(vuint8 *)(0xFC04410E)) -#define MCF_EDMA_DCHPRI15 (*(vuint8 *)(0xFC04410F)) -#define MCF_EDMA_DCHPRI(x) (*(vuint8 *)(0xFC044100+((x)*0x001))) -#define MCF_EDMA_TCD0_SADDR (*(vuint32*)(0xFC045000)) -#define MCF_EDMA_TCD1_SADDR (*(vuint32*)(0xFC045020)) -#define MCF_EDMA_TCD2_SADDR (*(vuint32*)(0xFC045040)) -#define MCF_EDMA_TCD3_SADDR (*(vuint32*)(0xFC045060)) -#define MCF_EDMA_TCD4_SADDR (*(vuint32*)(0xFC045080)) -#define MCF_EDMA_TCD5_SADDR (*(vuint32*)(0xFC0450A0)) -#define MCF_EDMA_TCD6_SADDR (*(vuint32*)(0xFC0450C0)) -#define MCF_EDMA_TCD7_SADDR (*(vuint32*)(0xFC0450E0)) -#define MCF_EDMA_TCD8_SADDR (*(vuint32*)(0xFC045100)) -#define MCF_EDMA_TCD9_SADDR (*(vuint32*)(0xFC045120)) -#define MCF_EDMA_TCD10_SADDR (*(vuint32*)(0xFC045140)) -#define MCF_EDMA_TCD11_SADDR (*(vuint32*)(0xFC045160)) -#define MCF_EDMA_TCD12_SADDR (*(vuint32*)(0xFC045180)) -#define MCF_EDMA_TCD13_SADDR (*(vuint32*)(0xFC0451A0)) -#define MCF_EDMA_TCD14_SADDR (*(vuint32*)(0xFC0451C0)) -#define MCF_EDMA_TCD15_SADDR (*(vuint32*)(0xFC0451E0)) -#define MCF_EDMA_TCD_SADDR(x) (*(vuint32*)(0xFC045000+((x)*0x020))) -#define MCF_EDMA_TCD0_ATTR (*(vuint16*)(0xFC045004)) -#define MCF_EDMA_TCD1_ATTR (*(vuint16*)(0xFC045024)) -#define MCF_EDMA_TCD2_ATTR (*(vuint16*)(0xFC045044)) -#define MCF_EDMA_TCD3_ATTR (*(vuint16*)(0xFC045064)) -#define MCF_EDMA_TCD4_ATTR (*(vuint16*)(0xFC045084)) -#define MCF_EDMA_TCD5_ATTR (*(vuint16*)(0xFC0450A4)) -#define MCF_EDMA_TCD6_ATTR (*(vuint16*)(0xFC0450C4)) -#define MCF_EDMA_TCD7_ATTR (*(vuint16*)(0xFC0450E4)) -#define MCF_EDMA_TCD8_ATTR (*(vuint16*)(0xFC045104)) -#define MCF_EDMA_TCD9_ATTR (*(vuint16*)(0xFC045124)) -#define MCF_EDMA_TCD10_ATTR (*(vuint16*)(0xFC045144)) -#define MCF_EDMA_TCD11_ATTR (*(vuint16*)(0xFC045164)) -#define MCF_EDMA_TCD12_ATTR (*(vuint16*)(0xFC045184)) -#define MCF_EDMA_TCD13_ATTR (*(vuint16*)(0xFC0451A4)) -#define MCF_EDMA_TCD14_ATTR (*(vuint16*)(0xFC0451C4)) -#define MCF_EDMA_TCD15_ATTR (*(vuint16*)(0xFC0451E4)) -#define MCF_EDMA_TCD_ATTR(x) (*(vuint16*)(0xFC045004+((x)*0x020))) -#define MCF_EDMA_TCD0_SOFF (*(vuint16*)(0xFC045006)) -#define MCF_EDMA_TCD1_SOFF (*(vuint16*)(0xFC045026)) -#define MCF_EDMA_TCD2_SOFF (*(vuint16*)(0xFC045046)) -#define MCF_EDMA_TCD3_SOFF (*(vuint16*)(0xFC045066)) -#define MCF_EDMA_TCD4_SOFF (*(vuint16*)(0xFC045086)) -#define MCF_EDMA_TCD5_SOFF (*(vuint16*)(0xFC0450A6)) -#define MCF_EDMA_TCD6_SOFF (*(vuint16*)(0xFC0450C6)) -#define MCF_EDMA_TCD7_SOFF (*(vuint16*)(0xFC0450E6)) -#define MCF_EDMA_TCD8_SOFF (*(vuint16*)(0xFC045106)) -#define MCF_EDMA_TCD9_SOFF (*(vuint16*)(0xFC045126)) -#define MCF_EDMA_TCD10_SOFF (*(vuint16*)(0xFC045146)) -#define MCF_EDMA_TCD11_SOFF (*(vuint16*)(0xFC045166)) -#define MCF_EDMA_TCD12_SOFF (*(vuint16*)(0xFC045186)) -#define MCF_EDMA_TCD13_SOFF (*(vuint16*)(0xFC0451A6)) -#define MCF_EDMA_TCD14_SOFF (*(vuint16*)(0xFC0451C6)) -#define MCF_EDMA_TCD15_SOFF (*(vuint16*)(0xFC0451E6)) -#define MCF_EDMA_TCD_SOFF(x) (*(vuint16*)(0xFC045006+((x)*0x020))) -#define MCF_EDMA_TCD0_NBYTES (*(vuint32*)(0xFC045008)) -#define MCF_EDMA_TCD1_NBYTES (*(vuint32*)(0xFC045028)) -#define MCF_EDMA_TCD2_NBYTES (*(vuint32*)(0xFC045048)) -#define MCF_EDMA_TCD3_NBYTES (*(vuint32*)(0xFC045068)) -#define MCF_EDMA_TCD4_NBYTES (*(vuint32*)(0xFC045088)) -#define MCF_EDMA_TCD5_NBYTES (*(vuint32*)(0xFC0450A8)) -#define MCF_EDMA_TCD6_NBYTES (*(vuint32*)(0xFC0450C8)) -#define MCF_EDMA_TCD7_NBYTES (*(vuint32*)(0xFC0450E8)) -#define MCF_EDMA_TCD8_NBYTES (*(vuint32*)(0xFC045108)) -#define MCF_EDMA_TCD9_NBYTES (*(vuint32*)(0xFC045128)) -#define MCF_EDMA_TCD10_NBYTES (*(vuint32*)(0xFC045148)) -#define MCF_EDMA_TCD11_NBYTES (*(vuint32*)(0xFC045168)) -#define MCF_EDMA_TCD12_NBYTES (*(vuint32*)(0xFC045188)) -#define MCF_EDMA_TCD13_NBYTES (*(vuint32*)(0xFC0451A8)) -#define MCF_EDMA_TCD14_NBYTES (*(vuint32*)(0xFC0451C8)) -#define MCF_EDMA_TCD15_NBYTES (*(vuint32*)(0xFC0451E8)) -#define MCF_EDMA_TCD_NBYTES(x) (*(vuint32*)(0xFC045008+((x)*0x020))) -#define MCF_EDMA_TCD0_SLAST (*(vuint32*)(0xFC04500C)) -#define MCF_EDMA_TCD1_SLAST (*(vuint32*)(0xFC04502C)) -#define MCF_EDMA_TCD2_SLAST (*(vuint32*)(0xFC04504C)) -#define MCF_EDMA_TCD3_SLAST (*(vuint32*)(0xFC04506C)) -#define MCF_EDMA_TCD4_SLAST (*(vuint32*)(0xFC04508C)) -#define MCF_EDMA_TCD5_SLAST (*(vuint32*)(0xFC0450AC)) -#define MCF_EDMA_TCD6_SLAST (*(vuint32*)(0xFC0450CC)) -#define MCF_EDMA_TCD7_SLAST (*(vuint32*)(0xFC0450EC)) -#define MCF_EDMA_TCD8_SLAST (*(vuint32*)(0xFC04510C)) -#define MCF_EDMA_TCD9_SLAST (*(vuint32*)(0xFC04512C)) -#define MCF_EDMA_TCD10_SLAST (*(vuint32*)(0xFC04514C)) -#define MCF_EDMA_TCD11_SLAST (*(vuint32*)(0xFC04516C)) -#define MCF_EDMA_TCD12_SLAST (*(vuint32*)(0xFC04518C)) -#define MCF_EDMA_TCD13_SLAST (*(vuint32*)(0xFC0451AC)) -#define MCF_EDMA_TCD14_SLAST (*(vuint32*)(0xFC0451CC)) -#define MCF_EDMA_TCD15_SLAST (*(vuint32*)(0xFC0451EC)) -#define MCF_EDMA_TCD_SLAST(x) (*(vuint32*)(0xFC04500C+((x)*0x020))) -#define MCF_EDMA_TCD0_DADDR (*(vuint32*)(0xFC045010)) -#define MCF_EDMA_TCD1_DADDR (*(vuint32*)(0xFC045030)) -#define MCF_EDMA_TCD2_DADDR (*(vuint32*)(0xFC045050)) -#define MCF_EDMA_TCD3_DADDR (*(vuint32*)(0xFC045070)) -#define MCF_EDMA_TCD4_DADDR (*(vuint32*)(0xFC045090)) -#define MCF_EDMA_TCD5_DADDR (*(vuint32*)(0xFC0450B0)) -#define MCF_EDMA_TCD6_DADDR (*(vuint32*)(0xFC0450D0)) -#define MCF_EDMA_TCD7_DADDR (*(vuint32*)(0xFC0450F0)) -#define MCF_EDMA_TCD8_DADDR (*(vuint32*)(0xFC045110)) -#define MCF_EDMA_TCD9_DADDR (*(vuint32*)(0xFC045130)) -#define MCF_EDMA_TCD10_DADDR (*(vuint32*)(0xFC045150)) -#define MCF_EDMA_TCD11_DADDR (*(vuint32*)(0xFC045170)) -#define MCF_EDMA_TCD12_DADDR (*(vuint32*)(0xFC045190)) -#define MCF_EDMA_TCD13_DADDR (*(vuint32*)(0xFC0451B0)) -#define MCF_EDMA_TCD14_DADDR (*(vuint32*)(0xFC0451D0)) -#define MCF_EDMA_TCD15_DADDR (*(vuint32*)(0xFC0451F0)) -#define MCF_EDMA_TCD_DADDR(x) (*(vuint32*)(0xFC045010+((x)*0x020))) -#define MCF_EDMA_TCD0_CITER (*(vuint16*)(0xFC045014)) -#define MCF_EDMA_TCD1_CITER (*(vuint16*)(0xFC045034)) -#define MCF_EDMA_TCD2_CITER (*(vuint16*)(0xFC045054)) -#define MCF_EDMA_TCD3_CITER (*(vuint16*)(0xFC045074)) -#define MCF_EDMA_TCD4_CITER (*(vuint16*)(0xFC045094)) -#define MCF_EDMA_TCD5_CITER (*(vuint16*)(0xFC0450B4)) -#define MCF_EDMA_TCD6_CITER (*(vuint16*)(0xFC0450D4)) -#define MCF_EDMA_TCD7_CITER (*(vuint16*)(0xFC0450F4)) -#define MCF_EDMA_TCD8_CITER (*(vuint16*)(0xFC045114)) -#define MCF_EDMA_TCD9_CITER (*(vuint16*)(0xFC045134)) -#define MCF_EDMA_TCD10_CITER (*(vuint16*)(0xFC045154)) -#define MCF_EDMA_TCD11_CITER (*(vuint16*)(0xFC045174)) -#define MCF_EDMA_TCD12_CITER (*(vuint16*)(0xFC045194)) -#define MCF_EDMA_TCD13_CITER (*(vuint16*)(0xFC0451B4)) -#define MCF_EDMA_TCD14_CITER (*(vuint16*)(0xFC0451D4)) -#define MCF_EDMA_TCD15_CITER (*(vuint16*)(0xFC0451F4)) -#define MCF_EDMA_TCD_CITER(x) (*(vuint16*)(0xFC045014+((x)*0x020))) -#define MCF_EDMA_TCD0_CITER_ELINK (*(vuint16*)(0xFC045014)) -#define MCF_EDMA_TCD1_CITER_ELINK (*(vuint16*)(0xFC045034)) -#define MCF_EDMA_TCD2_CITER_ELINK (*(vuint16*)(0xFC045054)) -#define MCF_EDMA_TCD3_CITER_ELINK (*(vuint16*)(0xFC045074)) -#define MCF_EDMA_TCD4_CITER_ELINK (*(vuint16*)(0xFC045094)) -#define MCF_EDMA_TCD5_CITER_ELINK (*(vuint16*)(0xFC0450B4)) -#define MCF_EDMA_TCD6_CITER_ELINK (*(vuint16*)(0xFC0450D4)) -#define MCF_EDMA_TCD7_CITER_ELINK (*(vuint16*)(0xFC0450F4)) -#define MCF_EDMA_TCD8_CITER_ELINK (*(vuint16*)(0xFC045114)) -#define MCF_EDMA_TCD9_CITER_ELINK (*(vuint16*)(0xFC045134)) -#define MCF_EDMA_TCD10_CITER_ELINK (*(vuint16*)(0xFC045154)) -#define MCF_EDMA_TCD11_CITER_ELINK (*(vuint16*)(0xFC045174)) -#define MCF_EDMA_TCD12_CITER_ELINK (*(vuint16*)(0xFC045194)) -#define MCF_EDMA_TCD13_CITER_ELINK (*(vuint16*)(0xFC0451B4)) -#define MCF_EDMA_TCD14_CITER_ELINK (*(vuint16*)(0xFC0451D4)) -#define MCF_EDMA_TCD15_CITER_ELINK (*(vuint16*)(0xFC0451F4)) -#define MCF_EDMA_TCD_CITER_ELINK(x) (*(vuint16*)(0xFC045014+((x)*0x020))) -#define MCF_EDMA_TCD0_DOFF (*(vuint16*)(0xFC045016)) -#define MCF_EDMA_TCD1_DOFF (*(vuint16*)(0xFC045036)) -#define MCF_EDMA_TCD2_DOFF (*(vuint16*)(0xFC045056)) -#define MCF_EDMA_TCD3_DOFF (*(vuint16*)(0xFC045076)) -#define MCF_EDMA_TCD4_DOFF (*(vuint16*)(0xFC045096)) -#define MCF_EDMA_TCD5_DOFF (*(vuint16*)(0xFC0450B6)) -#define MCF_EDMA_TCD6_DOFF (*(vuint16*)(0xFC0450D6)) -#define MCF_EDMA_TCD7_DOFF (*(vuint16*)(0xFC0450F6)) -#define MCF_EDMA_TCD8_DOFF (*(vuint16*)(0xFC045116)) -#define MCF_EDMA_TCD9_DOFF (*(vuint16*)(0xFC045136)) -#define MCF_EDMA_TCD10_DOFF (*(vuint16*)(0xFC045156)) -#define MCF_EDMA_TCD11_DOFF (*(vuint16*)(0xFC045176)) -#define MCF_EDMA_TCD12_DOFF (*(vuint16*)(0xFC045196)) -#define MCF_EDMA_TCD13_DOFF (*(vuint16*)(0xFC0451B6)) -#define MCF_EDMA_TCD14_DOFF (*(vuint16*)(0xFC0451D6)) -#define MCF_EDMA_TCD15_DOFF (*(vuint16*)(0xFC0451F6)) -#define MCF_EDMA_TCD_DOFF(x) (*(vuint16*)(0xFC045016+((x)*0x020))) -#define MCF_EDMA_TCD0_DLAST_SGA (*(vuint32*)(0xFC045018)) -#define MCF_EDMA_TCD1_DLAST_SGA (*(vuint32*)(0xFC045038)) -#define MCF_EDMA_TCD2_DLAST_SGA (*(vuint32*)(0xFC045058)) -#define MCF_EDMA_TCD3_DLAST_SGA (*(vuint32*)(0xFC045078)) -#define MCF_EDMA_TCD4_DLAST_SGA (*(vuint32*)(0xFC045098)) -#define MCF_EDMA_TCD5_DLAST_SGA (*(vuint32*)(0xFC0450B8)) -#define MCF_EDMA_TCD6_DLAST_SGA (*(vuint32*)(0xFC0450D8)) -#define MCF_EDMA_TCD7_DLAST_SGA (*(vuint32*)(0xFC0450F8)) -#define MCF_EDMA_TCD8_DLAST_SGA (*(vuint32*)(0xFC045118)) -#define MCF_EDMA_TCD9_DLAST_SGA (*(vuint32*)(0xFC045138)) -#define MCF_EDMA_TCD10_DLAST_SGA (*(vuint32*)(0xFC045158)) -#define MCF_EDMA_TCD11_DLAST_SGA (*(vuint32*)(0xFC045178)) -#define MCF_EDMA_TCD12_DLAST_SGA (*(vuint32*)(0xFC045198)) -#define MCF_EDMA_TCD13_DLAST_SGA (*(vuint32*)(0xFC0451B8)) -#define MCF_EDMA_TCD14_DLAST_SGA (*(vuint32*)(0xFC0451D8)) -#define MCF_EDMA_TCD15_DLAST_SGA (*(vuint32*)(0xFC0451F8)) -#define MCF_EDMA_TCD_DLAST_SGA(x) (*(vuint32*)(0xFC045018+((x)*0x020))) -#define MCF_EDMA_TCD0_BITER (*(vuint16*)(0xFC04501C)) -#define MCF_EDMA_TCD1_BITER (*(vuint16*)(0xFC04503C)) -#define MCF_EDMA_TCD2_BITER (*(vuint16*)(0xFC04505C)) -#define MCF_EDMA_TCD3_BITER (*(vuint16*)(0xFC04507C)) -#define MCF_EDMA_TCD4_BITER (*(vuint16*)(0xFC04509C)) -#define MCF_EDMA_TCD5_BITER (*(vuint16*)(0xFC0450BC)) -#define MCF_EDMA_TCD6_BITER (*(vuint16*)(0xFC0450DC)) -#define MCF_EDMA_TCD7_BITER (*(vuint16*)(0xFC0450FC)) -#define MCF_EDMA_TCD8_BITER (*(vuint16*)(0xFC04511C)) -#define MCF_EDMA_TCD9_BITER (*(vuint16*)(0xFC04513C)) -#define MCF_EDMA_TCD10_BITER (*(vuint16*)(0xFC04515C)) -#define MCF_EDMA_TCD11_BITER (*(vuint16*)(0xFC04517C)) -#define MCF_EDMA_TCD12_BITER (*(vuint16*)(0xFC04519C)) -#define MCF_EDMA_TCD13_BITER (*(vuint16*)(0xFC0451BC)) -#define MCF_EDMA_TCD14_BITER (*(vuint16*)(0xFC0451DC)) -#define MCF_EDMA_TCD15_BITER (*(vuint16*)(0xFC0451FC)) -#define MCF_EDMA_TCD_BITER(x) (*(vuint16*)(0xFC04501C+((x)*0x020))) -#define MCF_EDMA_TCD0_BITER_ELINK (*(vuint16*)(0xFC04501C)) -#define MCF_EDMA_TCD1_BITER_ELINK (*(vuint16*)(0xFC04503C)) -#define MCF_EDMA_TCD2_BITER_ELINK (*(vuint16*)(0xFC04505C)) -#define MCF_EDMA_TCD3_BITER_ELINK (*(vuint16*)(0xFC04507C)) -#define MCF_EDMA_TCD4_BITER_ELINK (*(vuint16*)(0xFC04509C)) -#define MCF_EDMA_TCD5_BITER_ELINK (*(vuint16*)(0xFC0450BC)) -#define MCF_EDMA_TCD6_BITER_ELINK (*(vuint16*)(0xFC0450DC)) -#define MCF_EDMA_TCD7_BITER_ELINK (*(vuint16*)(0xFC0450FC)) -#define MCF_EDMA_TCD8_BITER_ELINK (*(vuint16*)(0xFC04511C)) -#define MCF_EDMA_TCD9_BITER_ELINK (*(vuint16*)(0xFC04513C)) -#define MCF_EDMA_TCD10_BITER_ELINK (*(vuint16*)(0xFC04515C)) -#define MCF_EDMA_TCD11_BITER_ELINK (*(vuint16*)(0xFC04517C)) -#define MCF_EDMA_TCD12_BITER_ELINK (*(vuint16*)(0xFC04519C)) -#define MCF_EDMA_TCD13_BITER_ELINK (*(vuint16*)(0xFC0451BC)) -#define MCF_EDMA_TCD14_BITER_ELINK (*(vuint16*)(0xFC0451DC)) -#define MCF_EDMA_TCD15_BITER_ELINK (*(vuint16*)(0xFC0451FC)) -#define MCF_EDMA_TCD_BITER_ELINK(x) (*(vuint16*)(0xFC04501C+((x)*0x020))) -#define MCF_EDMA_TCD0_CSR (*(vuint16*)(0xFC04501E)) -#define MCF_EDMA_TCD1_CSR (*(vuint16*)(0xFC04503E)) -#define MCF_EDMA_TCD2_CSR (*(vuint16*)(0xFC04505E)) -#define MCF_EDMA_TCD3_CSR (*(vuint16*)(0xFC04507E)) -#define MCF_EDMA_TCD4_CSR (*(vuint16*)(0xFC04509E)) -#define MCF_EDMA_TCD5_CSR (*(vuint16*)(0xFC0450BE)) -#define MCF_EDMA_TCD6_CSR (*(vuint16*)(0xFC0450DE)) -#define MCF_EDMA_TCD7_CSR (*(vuint16*)(0xFC0450FE)) -#define MCF_EDMA_TCD8_CSR (*(vuint16*)(0xFC04511E)) -#define MCF_EDMA_TCD9_CSR (*(vuint16*)(0xFC04513E)) -#define MCF_EDMA_TCD10_CSR (*(vuint16*)(0xFC04515E)) -#define MCF_EDMA_TCD11_CSR (*(vuint16*)(0xFC04517E)) -#define MCF_EDMA_TCD12_CSR (*(vuint16*)(0xFC04519E)) -#define MCF_EDMA_TCD13_CSR (*(vuint16*)(0xFC0451BE)) -#define MCF_EDMA_TCD14_CSR (*(vuint16*)(0xFC0451DE)) -#define MCF_EDMA_TCD15_CSR (*(vuint16*)(0xFC0451FE)) -#define MCF_EDMA_TCD_CSR(x) (*(vuint16*)(0xFC04501E +((x)*0x020))) - -/* Bit definitions and macros for MCF_EDMA_CR */ -#define MCF_EDMA_CR_EDBG (0x00000002) -#define MCF_EDMA_CR_ERCA (0x00000004) - -/* Bit definitions and macros for MCF_EDMA_ES */ -#define MCF_EDMA_ES_DBE (0x00000001) -#define MCF_EDMA_ES_SBE (0x00000002) -#define MCF_EDMA_ES_SGE (0x00000004) -#define MCF_EDMA_ES_NCE (0x00000008) -#define MCF_EDMA_ES_DOE (0x00000010) -#define MCF_EDMA_ES_DAE (0x00000020) -#define MCF_EDMA_ES_SOE (0x00000040) -#define MCF_EDMA_ES_SAE (0x00000080) -#define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000000F)<<8) -#define MCF_EDMA_ES_CPE (0x00004000) -#define MCF_EDMA_ES_VLD (0x80000000) - -/* Bit definitions and macros for MCF_EDMA_ERQ */ -#define MCF_EDMA_ERQ_ERQ0 (0x0001) -#define MCF_EDMA_ERQ_ERQ1 (0x0002) -#define MCF_EDMA_ERQ_ERQ2 (0x0004) -#define MCF_EDMA_ERQ_ERQ3 (0x0008) -#define MCF_EDMA_ERQ_ERQ4 (0x0010) -#define MCF_EDMA_ERQ_ERQ5 (0x0020) -#define MCF_EDMA_ERQ_ERQ6 (0x0040) -#define MCF_EDMA_ERQ_ERQ7 (0x0080) -#define MCF_EDMA_ERQ_ERQ8 (0x0100) -#define MCF_EDMA_ERQ_ERQ9 (0x0200) -#define MCF_EDMA_ERQ_ERQ10 (0x0400) -#define MCF_EDMA_ERQ_ERQ11 (0x0800) -#define MCF_EDMA_ERQ_ERQ12 (0x1000) -#define MCF_EDMA_ERQ_ERQ13 (0x2000) -#define MCF_EDMA_ERQ_ERQ14 (0x4000) -#define MCF_EDMA_ERQ_ERQ15 (0x8000) - -/* Bit definitions and macros for MCF_EDMA_EEI */ -#define MCF_EDMA_EEI_EEI0 (0x0001) -#define MCF_EDMA_EEI_EEI1 (0x0002) -#define MCF_EDMA_EEI_EEI2 (0x0004) -#define MCF_EDMA_EEI_EEI3 (0x0008) -#define MCF_EDMA_EEI_EEI4 (0x0010) -#define MCF_EDMA_EEI_EEI5 (0x0020) -#define MCF_EDMA_EEI_EEI6 (0x0040) -#define MCF_EDMA_EEI_EEI7 (0x0080) -#define MCF_EDMA_EEI_EEI8 (0x0100) -#define MCF_EDMA_EEI_EEI9 (0x0200) -#define MCF_EDMA_EEI_EEI10 (0x0400) -#define MCF_EDMA_EEI_EEI11 (0x0800) -#define MCF_EDMA_EEI_EEI12 (0x1000) -#define MCF_EDMA_EEI_EEI13 (0x2000) -#define MCF_EDMA_EEI_EEI14 (0x4000) -#define MCF_EDMA_EEI_EEI15 (0x8000) - -/* Bit definitions and macros for MCF_EDMA_SERQ */ -#define MCF_EDMA_SERQ_SERQ(x) (((x)&0x0F)<<0) -#define MCF_EDMA_SERQ_SAER (0x40) - -/* Bit definitions and macros for MCF_EDMA_CERQ */ -#define MCF_EDMA_CERQ_CERQ(x) (((x)&0x0F)<<0) -#define MCF_EDMA_CERQ_CAER (0x40) - -/* Bit definitions and macros for MCF_EDMA_SEEI */ -#define MCF_EDMA_SEEI_SEEI(x) (((x)&0x0F)<<0) -#define MCF_EDMA_SEEI_SAEE (0x40) - -/* Bit definitions and macros for MCF_EDMA_CEEI */ -#define MCF_EDMA_CEEI_CEEI(x) (((x)&0x0F)<<0) -#define MCF_EDMA_CEEI_CAEE (0x40) - -/* Bit definitions and macros for MCF_EDMA_CINT */ -#define MCF_EDMA_CINT_CINT(x) (((x)&0x0F)<<0) -#define MCF_EDMA_CINT_CAIR (0x40) - -/* Bit definitions and macros for MCF_EDMA_CERR */ -#define MCF_EDMA_CERR_CERR(x) (((x)&0x0F)<<0) -#define MCF_EDMA_CERR_CAER (0x40) - -/* Bit definitions and macros for MCF_EDMA_SSRT */ -#define MCF_EDMA_SSRT_SSRT(x) (((x)&0x0F)<<0) -#define MCF_EDMA_SSRT_SAST (0x40) - -/* Bit definitions and macros for MCF_EDMA_CDNE */ -#define MCF_EDMA_CDNE_CDNE(x) (((x)&0x0F)<<0) -#define MCF_EDMA_CDNE_CADN (0x40) - -/* Bit definitions and macros for MCF_EDMA_INT */ -#define MCF_EDMA_INT_INT0 (0x0001) -#define MCF_EDMA_INT_INT1 (0x0002) -#define MCF_EDMA_INT_INT2 (0x0004) -#define MCF_EDMA_INT_INT3 (0x0008) -#define MCF_EDMA_INT_INT4 (0x0010) -#define MCF_EDMA_INT_INT5 (0x0020) -#define MCF_EDMA_INT_INT6 (0x0040) -#define MCF_EDMA_INT_INT7 (0x0080) -#define MCF_EDMA_INT_INT8 (0x0100) -#define MCF_EDMA_INT_INT9 (0x0200) -#define MCF_EDMA_INT_INT10 (0x0400) -#define MCF_EDMA_INT_INT11 (0x0800) -#define MCF_EDMA_INT_INT12 (0x1000) -#define MCF_EDMA_INT_INT13 (0x2000) -#define MCF_EDMA_INT_INT14 (0x4000) -#define MCF_EDMA_INT_INT15 (0x8000) - -/* Bit definitions and macros for MCF_EDMA_ERR */ -#define MCF_EDMA_ERR_ERR0 (0x0001) -#define MCF_EDMA_ERR_ERR1 (0x0002) -#define MCF_EDMA_ERR_ERR2 (0x0004) -#define MCF_EDMA_ERR_ERR3 (0x0008) -#define MCF_EDMA_ERR_ERR4 (0x0010) -#define MCF_EDMA_ERR_ERR5 (0x0020) -#define MCF_EDMA_ERR_ERR6 (0x0040) -#define MCF_EDMA_ERR_ERR7 (0x0080) -#define MCF_EDMA_ERR_ERR8 (0x0100) -#define MCF_EDMA_ERR_ERR9 (0x0200) -#define MCF_EDMA_ERR_ERR10 (0x0400) -#define MCF_EDMA_ERR_ERR11 (0x0800) -#define MCF_EDMA_ERR_ERR12 (0x1000) -#define MCF_EDMA_ERR_ERR13 (0x2000) -#define MCF_EDMA_ERR_ERR14 (0x4000) -#define MCF_EDMA_ERR_ERR15 (0x8000) - -/* Bit definitions and macros for MCF_EDMA_DCHPRI */ -#define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F)<<0) -#define MCF_EDMA_DCHPRI_ECP (0x80) - -/* Bit definitions and macros for MCF_EDMA_TCD_SADDR */ -#define MCF_EDMA_TCD_SADDR_SADDR(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_EDMA_TCD_ATTR */ -#define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007)<<0) -#define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3) -#define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8) -#define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11) -#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000) -#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) -#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) -#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400) -#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000) -#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) -#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) -#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004) - -/* Bit definitions and macros for MCF_EDMA_TCD_SOFF */ -#define MCF_EDMA_TCD_SOFF_SOFF(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_EDMA_TCD_NBYTES */ -#define MCF_EDMA_TCD_NBYTES_NBYTES(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_EDMA_TCD_SLAST */ -#define MCF_EDMA_TCD_SLAST_SLAST(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_EDMA_TCD_DADDR */ -#define MCF_EDMA_TCD_DADDR_DADDR(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_EDMA_TCD_CITER */ -#define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF)<<0) -#define MCF_EDMA_TCD_CITER_E_LINK (0x8000) - -/* Bit definitions and macros for MCF_EDMA_TCD_CITER_ELINK */ -#define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF)<<0) -#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) -#define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000) - -/* Bit definitions and macros for MCF_EDMA_TCD_DOFF */ -#define MCF_EDMA_TCD_DOFF_DOFF(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_EDMA_TCD_DLAST_SGA */ -#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_EDMA_TCD_BITER */ -#define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF)<<0) -#define MCF_EDMA_TCD_BITER_E_LINK (0x8000) - -/* Bit definitions and macros for MCF_EDMA_TCD_BITER_ELINK */ -#define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF)<<0) -#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) -#define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000) - -/* Bit definitions and macros for MCF_EDMA_TCD_CSR */ -#define MCF_EDMA_TCD_CSR_START (0x0001) -#define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002) -#define MCF_EDMA_TCD_CSR_INT_HALF (0x0004) -#define MCF_EDMA_TCD_CSR_D_REQ (0x0008) -#define MCF_EDMA_TCD_CSR_E_SG (0x0010) -#define MCF_EDMA_TCD_CSR_E_LINK (0x0020) -#define MCF_EDMA_TCD_CSR_ACTIVE (0x0040) -#define MCF_EDMA_TCD_CSR_DONE (0x0080) -#define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8) -#define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14) -#define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000) -#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000) -#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000) - -/********************************************************************* -* -* Interrupt Controller (INTC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC0_IPRH (*(vuint32*)(0xFC048000)) -#define MCF_INTC0_IPRL (*(vuint32*)(0xFC048004)) -#define MCF_INTC0_IMRH (*(vuint32*)(0xFC048008)) -#define MCF_INTC0_IMRL (*(vuint32*)(0xFC04800C)) -#define MCF_INTC0_INTFRCH (*(vuint32*)(0xFC048010)) -#define MCF_INTC0_INTFRCL (*(vuint32*)(0xFC048014)) -#define MCF_INTC0_ICONFIG (*(vuint16*)(0xFC04801A)) -#define MCF_INTC0_SIMR (*(vuint8 *)(0xFC04801C)) -#define MCF_INTC0_CIMR (*(vuint8 *)(0xFC04801D)) -#define MCF_INTC0_CLMASK (*(vuint8 *)(0xFC04801E)) -#define MCF_INTC0_SLMASK (*(vuint8 *)(0xFC04801F)) -#define MCF_INTC0_ICR0 (*(vuint8 *)(0xFC048040)) -#define MCF_INTC0_ICR1 (*(vuint8 *)(0xFC048041)) -#define MCF_INTC0_ICR2 (*(vuint8 *)(0xFC048042)) -#define MCF_INTC0_ICR3 (*(vuint8 *)(0xFC048043)) -#define MCF_INTC0_ICR4 (*(vuint8 *)(0xFC048044)) -#define MCF_INTC0_ICR5 (*(vuint8 *)(0xFC048045)) -#define MCF_INTC0_ICR6 (*(vuint8 *)(0xFC048046)) -#define MCF_INTC0_ICR7 (*(vuint8 *)(0xFC048047)) -#define MCF_INTC0_ICR8 (*(vuint8 *)(0xFC048048)) -#define MCF_INTC0_ICR9 (*(vuint8 *)(0xFC048049)) -#define MCF_INTC0_ICR10 (*(vuint8 *)(0xFC04804A)) -#define MCF_INTC0_ICR11 (*(vuint8 *)(0xFC04804B)) -#define MCF_INTC0_ICR12 (*(vuint8 *)(0xFC04804C)) -#define MCF_INTC0_ICR13 (*(vuint8 *)(0xFC04804D)) -#define MCF_INTC0_ICR14 (*(vuint8 *)(0xFC04804E)) -#define MCF_INTC0_ICR15 (*(vuint8 *)(0xFC04804F)) -#define MCF_INTC0_ICR16 (*(vuint8 *)(0xFC048050)) -#define MCF_INTC0_ICR17 (*(vuint8 *)(0xFC048051)) -#define MCF_INTC0_ICR18 (*(vuint8 *)(0xFC048052)) -#define MCF_INTC0_ICR19 (*(vuint8 *)(0xFC048053)) -#define MCF_INTC0_ICR20 (*(vuint8 *)(0xFC048054)) -#define MCF_INTC0_ICR21 (*(vuint8 *)(0xFC048055)) -#define MCF_INTC0_ICR22 (*(vuint8 *)(0xFC048056)) -#define MCF_INTC0_ICR23 (*(vuint8 *)(0xFC048057)) -#define MCF_INTC0_ICR24 (*(vuint8 *)(0xFC048058)) -#define MCF_INTC0_ICR25 (*(vuint8 *)(0xFC048059)) -#define MCF_INTC0_ICR26 (*(vuint8 *)(0xFC04805A)) -#define MCF_INTC0_ICR27 (*(vuint8 *)(0xFC04805B)) -#define MCF_INTC0_ICR28 (*(vuint8 *)(0xFC04805C)) -#define MCF_INTC0_ICR29 (*(vuint8 *)(0xFC04805D)) -#define MCF_INTC0_ICR30 (*(vuint8 *)(0xFC04805E)) -#define MCF_INTC0_ICR31 (*(vuint8 *)(0xFC04805F)) -#define MCF_INTC0_ICR32 (*(vuint8 *)(0xFC048060)) -#define MCF_INTC0_ICR33 (*(vuint8 *)(0xFC048061)) -#define MCF_INTC0_ICR34 (*(vuint8 *)(0xFC048062)) -#define MCF_INTC0_ICR35 (*(vuint8 *)(0xFC048063)) -#define MCF_INTC0_ICR36 (*(vuint8 *)(0xFC048064)) -#define MCF_INTC0_ICR37 (*(vuint8 *)(0xFC048065)) -#define MCF_INTC0_ICR38 (*(vuint8 *)(0xFC048066)) -#define MCF_INTC0_ICR39 (*(vuint8 *)(0xFC048067)) -#define MCF_INTC0_ICR40 (*(vuint8 *)(0xFC048068)) -#define MCF_INTC0_ICR41 (*(vuint8 *)(0xFC048069)) -#define MCF_INTC0_ICR42 (*(vuint8 *)(0xFC04806A)) -#define MCF_INTC0_ICR43 (*(vuint8 *)(0xFC04806B)) -#define MCF_INTC0_ICR44 (*(vuint8 *)(0xFC04806C)) -#define MCF_INTC0_ICR45 (*(vuint8 *)(0xFC04806D)) -#define MCF_INTC0_ICR46 (*(vuint8 *)(0xFC04806E)) -#define MCF_INTC0_ICR47 (*(vuint8 *)(0xFC04806F)) -#define MCF_INTC0_ICR48 (*(vuint8 *)(0xFC048070)) -#define MCF_INTC0_ICR49 (*(vuint8 *)(0xFC048071)) -#define MCF_INTC0_ICR50 (*(vuint8 *)(0xFC048072)) -#define MCF_INTC0_ICR51 (*(vuint8 *)(0xFC048073)) -#define MCF_INTC0_ICR52 (*(vuint8 *)(0xFC048074)) -#define MCF_INTC0_ICR53 (*(vuint8 *)(0xFC048075)) -#define MCF_INTC0_ICR54 (*(vuint8 *)(0xFC048076)) -#define MCF_INTC0_ICR55 (*(vuint8 *)(0xFC048077)) -#define MCF_INTC0_ICR56 (*(vuint8 *)(0xFC048078)) -#define MCF_INTC0_ICR57 (*(vuint8 *)(0xFC048079)) -#define MCF_INTC0_ICR58 (*(vuint8 *)(0xFC04807A)) -#define MCF_INTC0_ICR59 (*(vuint8 *)(0xFC04807B)) -#define MCF_INTC0_ICR60 (*(vuint8 *)(0xFC04807C)) -#define MCF_INTC0_ICR61 (*(vuint8 *)(0xFC04807D)) -#define MCF_INTC0_ICR62 (*(vuint8 *)(0xFC04807E)) -#define MCF_INTC0_ICR63 (*(vuint8 *)(0xFC04807F)) -#define MCF_INTC0_ICR(x) (*(vuint8 *)(0xFC048040+((x)*0x001))) -#define MCF_INTC0_SWIACK (*(vuint8 *)(0xFC0480E0)) -#define MCF_INTC0_L1IACK (*(vuint8 *)(0xFC0480E4)) -#define MCF_INTC0_L2IACK (*(vuint8 *)(0xFC0480E8)) -#define MCF_INTC0_L3IACK (*(vuint8 *)(0xFC0480EC)) -#define MCF_INTC0_L4IACK (*(vuint8 *)(0xFC0480F0)) -#define MCF_INTC0_L5IACK (*(vuint8 *)(0xFC0480F4)) -#define MCF_INTC0_L6IACK (*(vuint8 *)(0xFC0480F8)) -#define MCF_INTC0_L7IACK (*(vuint8 *)(0xFC0480FC)) -#define MCF_INTC0_LIACK(x) (*(vuint8 *)(0xFC0480E4+((x-1)*0x004))) -#define MCF_INTC1_IPRH (*(vuint32*)(0xFC04C000)) -#define MCF_INTC1_IPRL (*(vuint32*)(0xFC04C004)) -#define MCF_INTC1_IMRH (*(vuint32*)(0xFC04C008)) -#define MCF_INTC1_IMRL (*(vuint32*)(0xFC04C00C)) -#define MCF_INTC1_INTFRCH (*(vuint32*)(0xFC04C010)) -#define MCF_INTC1_INTFRCL (*(vuint32*)(0xFC04C014)) -#define MCF_INTC1_ICONFIG (*(vuint16*)(0xFC04C01A)) -#define MCF_INTC1_SIMR (*(vuint8 *)(0xFC04C01C)) -#define MCF_INTC1_CIMR (*(vuint8 *)(0xFC04C01D)) -#define MCF_INTC1_CLMASK (*(vuint8 *)(0xFC04C01E)) -#define MCF_INTC1_SLMASK (*(vuint8 *)(0xFC04C01F)) -#define MCF_INTC1_ICR0 (*(vuint8 *)(0xFC04C040)) -#define MCF_INTC1_ICR1 (*(vuint8 *)(0xFC04C041)) -#define MCF_INTC1_ICR2 (*(vuint8 *)(0xFC04C042)) -#define MCF_INTC1_ICR3 (*(vuint8 *)(0xFC04C043)) -#define MCF_INTC1_ICR4 (*(vuint8 *)(0xFC04C044)) -#define MCF_INTC1_ICR5 (*(vuint8 *)(0xFC04C045)) -#define MCF_INTC1_ICR6 (*(vuint8 *)(0xFC04C046)) -#define MCF_INTC1_ICR7 (*(vuint8 *)(0xFC04C047)) -#define MCF_INTC1_ICR8 (*(vuint8 *)(0xFC04C048)) -#define MCF_INTC1_ICR9 (*(vuint8 *)(0xFC04C049)) -#define MCF_INTC1_ICR10 (*(vuint8 *)(0xFC04C04A)) -#define MCF_INTC1_ICR11 (*(vuint8 *)(0xFC04C04B)) -#define MCF_INTC1_ICR12 (*(vuint8 *)(0xFC04C04C)) -#define MCF_INTC1_ICR13 (*(vuint8 *)(0xFC04C04D)) -#define MCF_INTC1_ICR14 (*(vuint8 *)(0xFC04C04E)) -#define MCF_INTC1_ICR15 (*(vuint8 *)(0xFC04C04F)) -#define MCF_INTC1_ICR16 (*(vuint8 *)(0xFC04C050)) -#define MCF_INTC1_ICR17 (*(vuint8 *)(0xFC04C051)) -#define MCF_INTC1_ICR18 (*(vuint8 *)(0xFC04C052)) -#define MCF_INTC1_ICR19 (*(vuint8 *)(0xFC04C053)) -#define MCF_INTC1_ICR20 (*(vuint8 *)(0xFC04C054)) -#define MCF_INTC1_ICR21 (*(vuint8 *)(0xFC04C055)) -#define MCF_INTC1_ICR22 (*(vuint8 *)(0xFC04C056)) -#define MCF_INTC1_ICR23 (*(vuint8 *)(0xFC04C057)) -#define MCF_INTC1_ICR24 (*(vuint8 *)(0xFC04C058)) -#define MCF_INTC1_ICR25 (*(vuint8 *)(0xFC04C059)) -#define MCF_INTC1_ICR26 (*(vuint8 *)(0xFC04C05A)) -#define MCF_INTC1_ICR27 (*(vuint8 *)(0xFC04C05B)) -#define MCF_INTC1_ICR28 (*(vuint8 *)(0xFC04C05C)) -#define MCF_INTC1_ICR29 (*(vuint8 *)(0xFC04C05D)) -#define MCF_INTC1_ICR30 (*(vuint8 *)(0xFC04C05E)) -#define MCF_INTC1_ICR31 (*(vuint8 *)(0xFC04C05F)) -#define MCF_INTC1_ICR32 (*(vuint8 *)(0xFC04C060)) -#define MCF_INTC1_ICR33 (*(vuint8 *)(0xFC04C061)) -#define MCF_INTC1_ICR34 (*(vuint8 *)(0xFC04C062)) -#define MCF_INTC1_ICR35 (*(vuint8 *)(0xFC04C063)) -#define MCF_INTC1_ICR36 (*(vuint8 *)(0xFC04C064)) -#define MCF_INTC1_ICR37 (*(vuint8 *)(0xFC04C065)) -#define MCF_INTC1_ICR38 (*(vuint8 *)(0xFC04C066)) -#define MCF_INTC1_ICR39 (*(vuint8 *)(0xFC04C067)) -#define MCF_INTC1_ICR40 (*(vuint8 *)(0xFC04C068)) -#define MCF_INTC1_ICR41 (*(vuint8 *)(0xFC04C069)) -#define MCF_INTC1_ICR42 (*(vuint8 *)(0xFC04C06A)) -#define MCF_INTC1_ICR43 (*(vuint8 *)(0xFC04C06B)) -#define MCF_INTC1_ICR44 (*(vuint8 *)(0xFC04C06C)) -#define MCF_INTC1_ICR45 (*(vuint8 *)(0xFC04C06D)) -#define MCF_INTC1_ICR46 (*(vuint8 *)(0xFC04C06E)) -#define MCF_INTC1_ICR47 (*(vuint8 *)(0xFC04C06F)) -#define MCF_INTC1_ICR48 (*(vuint8 *)(0xFC04C070)) -#define MCF_INTC1_ICR49 (*(vuint8 *)(0xFC04C071)) -#define MCF_INTC1_ICR50 (*(vuint8 *)(0xFC04C072)) -#define MCF_INTC1_ICR51 (*(vuint8 *)(0xFC04C073)) -#define MCF_INTC1_ICR52 (*(vuint8 *)(0xFC04C074)) -#define MCF_INTC1_ICR53 (*(vuint8 *)(0xFC04C075)) -#define MCF_INTC1_ICR54 (*(vuint8 *)(0xFC04C076)) -#define MCF_INTC1_ICR55 (*(vuint8 *)(0xFC04C077)) -#define MCF_INTC1_ICR56 (*(vuint8 *)(0xFC04C078)) -#define MCF_INTC1_ICR57 (*(vuint8 *)(0xFC04C079)) -#define MCF_INTC1_ICR58 (*(vuint8 *)(0xFC04C07A)) -#define MCF_INTC1_ICR59 (*(vuint8 *)(0xFC04C07B)) -#define MCF_INTC1_ICR60 (*(vuint8 *)(0xFC04C07C)) -#define MCF_INTC1_ICR61 (*(vuint8 *)(0xFC04C07D)) -#define MCF_INTC1_ICR62 (*(vuint8 *)(0xFC04C07E)) -#define MCF_INTC1_ICR63 (*(vuint8 *)(0xFC04C07F)) -#define MCF_INTC1_ICR(x) (*(vuint8 *)(0xFC04C040+((x)*0x001))) -#define MCF_INTC1_SWIACK (*(vuint8 *)(0xFC04C0E0)) -#define MCF_INTC1_L1IACK (*(vuint8 *)(0xFC04C0E4)) -#define MCF_INTC1_L2IACK (*(vuint8 *)(0xFC04C0E8)) -#define MCF_INTC1_L3IACK (*(vuint8 *)(0xFC04C0EC)) -#define MCF_INTC1_L4IACK (*(vuint8 *)(0xFC04C0F0)) -#define MCF_INTC1_L5IACK (*(vuint8 *)(0xFC04C0F4)) -#define MCF_INTC1_L6IACK (*(vuint8 *)(0xFC04C0F8)) -#define MCF_INTC1_L7IACK (*(vuint8 *)(0xFC04C0FC)) -#define MCF_INTC1_LIACK(x) (*(vuint8 *)(0xFC04C0E4+((x-1)*0x004))) -#define MCF_INTC_IPRH(x) (*(vuint32*)(0xFC048000+((x)*0x4000))) -#define MCF_INTC_IPRL(x) (*(vuint32*)(0xFC048004+((x)*0x4000))) -#define MCF_INTC_IMRH(x) (*(vuint32*)(0xFC048008+((x)*0x4000))) -#define MCF_INTC_IMRL(x) (*(vuint32*)(0xFC04800C+((x)*0x4000))) -#define MCF_INTC_INTFRCH(x) (*(vuint32*)(0xFC048010+((x)*0x4000))) -#define MCF_INTC_INTFRCL(x) (*(vuint32*)(0xFC048014+((x)*0x4000))) -#define MCF_INTC_ICONFIG(x) (*(vuint16*)(0xFC04801A+((x)*0x4000))) -#define MCF_INTC_SIMR(x) (*(vuint8 *)(0xFC04801C+((x)*0x4000))) -#define MCF_INTC_CIMR(x) (*(vuint8 *)(0xFC04801D+((x)*0x4000))) -#define MCF_INTC_CLMASK(x) (*(vuint8 *)(0xFC04801E+((x)*0x4000))) -#define MCF_INTC_SLMASK(x) (*(vuint8 *)(0xFC04801F+((x)*0x4000))) -#define MCF_INTC_ICR0(x) (*(vuint8 *)(0xFC048040+((x)*0x4000))) -#define MCF_INTC_ICR1(x) (*(vuint8 *)(0xFC048041+((x)*0x4000))) -#define MCF_INTC_ICR2(x) (*(vuint8 *)(0xFC048042+((x)*0x4000))) -#define MCF_INTC_ICR3(x) (*(vuint8 *)(0xFC048043+((x)*0x4000))) -#define MCF_INTC_ICR4(x) (*(vuint8 *)(0xFC048044+((x)*0x4000))) -#define MCF_INTC_ICR5(x) (*(vuint8 *)(0xFC048045+((x)*0x4000))) -#define MCF_INTC_ICR6(x) (*(vuint8 *)(0xFC048046+((x)*0x4000))) -#define MCF_INTC_ICR7(x) (*(vuint8 *)(0xFC048047+((x)*0x4000))) -#define MCF_INTC_ICR8(x) (*(vuint8 *)(0xFC048048+((x)*0x4000))) -#define MCF_INTC_ICR9(x) (*(vuint8 *)(0xFC048049+((x)*0x4000))) -#define MCF_INTC_ICR10(x) (*(vuint8 *)(0xFC04804A+((x)*0x4000))) -#define MCF_INTC_ICR11(x) (*(vuint8 *)(0xFC04804B+((x)*0x4000))) -#define MCF_INTC_ICR12(x) (*(vuint8 *)(0xFC04804C+((x)*0x4000))) -#define MCF_INTC_ICR13(x) (*(vuint8 *)(0xFC04804D+((x)*0x4000))) -#define MCF_INTC_ICR14(x) (*(vuint8 *)(0xFC04804E+((x)*0x4000))) -#define MCF_INTC_ICR15(x) (*(vuint8 *)(0xFC04804F+((x)*0x4000))) -#define MCF_INTC_ICR16(x) (*(vuint8 *)(0xFC048050+((x)*0x4000))) -#define MCF_INTC_ICR17(x) (*(vuint8 *)(0xFC048051+((x)*0x4000))) -#define MCF_INTC_ICR18(x) (*(vuint8 *)(0xFC048052+((x)*0x4000))) -#define MCF_INTC_ICR19(x) (*(vuint8 *)(0xFC048053+((x)*0x4000))) -#define MCF_INTC_ICR20(x) (*(vuint8 *)(0xFC048054+((x)*0x4000))) -#define MCF_INTC_ICR21(x) (*(vuint8 *)(0xFC048055+((x)*0x4000))) -#define MCF_INTC_ICR22(x) (*(vuint8 *)(0xFC048056+((x)*0x4000))) -#define MCF_INTC_ICR23(x) (*(vuint8 *)(0xFC048057+((x)*0x4000))) -#define MCF_INTC_ICR24(x) (*(vuint8 *)(0xFC048058+((x)*0x4000))) -#define MCF_INTC_ICR25(x) (*(vuint8 *)(0xFC048059+((x)*0x4000))) -#define MCF_INTC_ICR26(x) (*(vuint8 *)(0xFC04805A+((x)*0x4000))) -#define MCF_INTC_ICR27(x) (*(vuint8 *)(0xFC04805B+((x)*0x4000))) -#define MCF_INTC_ICR28(x) (*(vuint8 *)(0xFC04805C+((x)*0x4000))) -#define MCF_INTC_ICR29(x) (*(vuint8 *)(0xFC04805D+((x)*0x4000))) -#define MCF_INTC_ICR30(x) (*(vuint8 *)(0xFC04805E+((x)*0x4000))) -#define MCF_INTC_ICR31(x) (*(vuint8 *)(0xFC04805F+((x)*0x4000))) -#define MCF_INTC_ICR32(x) (*(vuint8 *)(0xFC048060+((x)*0x4000))) -#define MCF_INTC_ICR33(x) (*(vuint8 *)(0xFC048061+((x)*0x4000))) -#define MCF_INTC_ICR34(x) (*(vuint8 *)(0xFC048062+((x)*0x4000))) -#define MCF_INTC_ICR35(x) (*(vuint8 *)(0xFC048063+((x)*0x4000))) -#define MCF_INTC_ICR36(x) (*(vuint8 *)(0xFC048064+((x)*0x4000))) -#define MCF_INTC_ICR37(x) (*(vuint8 *)(0xFC048065+((x)*0x4000))) -#define MCF_INTC_ICR38(x) (*(vuint8 *)(0xFC048066+((x)*0x4000))) -#define MCF_INTC_ICR39(x) (*(vuint8 *)(0xFC048067+((x)*0x4000))) -#define MCF_INTC_ICR40(x) (*(vuint8 *)(0xFC048068+((x)*0x4000))) -#define MCF_INTC_ICR41(x) (*(vuint8 *)(0xFC048069+((x)*0x4000))) -#define MCF_INTC_ICR42(x) (*(vuint8 *)(0xFC04806A+((x)*0x4000))) -#define MCF_INTC_ICR43(x) (*(vuint8 *)(0xFC04806B+((x)*0x4000))) -#define MCF_INTC_ICR44(x) (*(vuint8 *)(0xFC04806C+((x)*0x4000))) -#define MCF_INTC_ICR45(x) (*(vuint8 *)(0xFC04806D+((x)*0x4000))) -#define MCF_INTC_ICR46(x) (*(vuint8 *)(0xFC04806E+((x)*0x4000))) -#define MCF_INTC_ICR47(x) (*(vuint8 *)(0xFC04806F+((x)*0x4000))) -#define MCF_INTC_ICR48(x) (*(vuint8 *)(0xFC048070+((x)*0x4000))) -#define MCF_INTC_ICR49(x) (*(vuint8 *)(0xFC048071+((x)*0x4000))) -#define MCF_INTC_ICR50(x) (*(vuint8 *)(0xFC048072+((x)*0x4000))) -#define MCF_INTC_ICR51(x) (*(vuint8 *)(0xFC048073+((x)*0x4000))) -#define MCF_INTC_ICR52(x) (*(vuint8 *)(0xFC048074+((x)*0x4000))) -#define MCF_INTC_ICR53(x) (*(vuint8 *)(0xFC048075+((x)*0x4000))) -#define MCF_INTC_ICR54(x) (*(vuint8 *)(0xFC048076+((x)*0x4000))) -#define MCF_INTC_ICR55(x) (*(vuint8 *)(0xFC048077+((x)*0x4000))) -#define MCF_INTC_ICR56(x) (*(vuint8 *)(0xFC048078+((x)*0x4000))) -#define MCF_INTC_ICR57(x) (*(vuint8 *)(0xFC048079+((x)*0x4000))) -#define MCF_INTC_ICR58(x) (*(vuint8 *)(0xFC04807A+((x)*0x4000))) -#define MCF_INTC_ICR59(x) (*(vuint8 *)(0xFC04807B+((x)*0x4000))) -#define MCF_INTC_ICR60(x) (*(vuint8 *)(0xFC04807C+((x)*0x4000))) -#define MCF_INTC_ICR61(x) (*(vuint8 *)(0xFC04807D+((x)*0x4000))) -#define MCF_INTC_ICR62(x) (*(vuint8 *)(0xFC04807E+((x)*0x4000))) -#define MCF_INTC_ICR63(x) (*(vuint8 *)(0xFC04807F+((x)*0x4000))) -#define MCF_INTC_SWIACK(x) (*(vuint8 *)(0xFC0480E0+((x)*0x4000))) -#define MCF_INTC_L1IACK(x) (*(vuint8 *)(0xFC0480E4+((x)*0x4000))) -#define MCF_INTC_L2IACK(x) (*(vuint8 *)(0xFC0480E8+((x)*0x4000))) -#define MCF_INTC_L3IACK(x) (*(vuint8 *)(0xFC0480EC+((x)*0x4000))) -#define MCF_INTC_L4IACK(x) (*(vuint8 *)(0xFC0480F0+((x)*0x4000))) -#define MCF_INTC_L5IACK(x) (*(vuint8 *)(0xFC0480F4+((x)*0x4000))) -#define MCF_INTC_L6IACK(x) (*(vuint8 *)(0xFC0480F8+((x)*0x4000))) -#define MCF_INTC_L7IACK(x) (*(vuint8 *)(0xFC0480FC+((x)*0x4000))) - -/* Bit definitions and macros for MCF_INTC_IPRH */ -#define MCF_INTC_IPRH_INT32 (0x00000001) -#define MCF_INTC_IPRH_INT33 (0x00000002) -#define MCF_INTC_IPRH_INT34 (0x00000004) -#define MCF_INTC_IPRH_INT35 (0x00000008) -#define MCF_INTC_IPRH_INT36 (0x00000010) -#define MCF_INTC_IPRH_INT37 (0x00000020) -#define MCF_INTC_IPRH_INT38 (0x00000040) -#define MCF_INTC_IPRH_INT39 (0x00000080) -#define MCF_INTC_IPRH_INT40 (0x00000100) -#define MCF_INTC_IPRH_INT41 (0x00000200) -#define MCF_INTC_IPRH_INT42 (0x00000400) -#define MCF_INTC_IPRH_INT43 (0x00000800) -#define MCF_INTC_IPRH_INT44 (0x00001000) -#define MCF_INTC_IPRH_INT45 (0x00002000) -#define MCF_INTC_IPRH_INT46 (0x00004000) -#define MCF_INTC_IPRH_INT47 (0x00008000) -#define MCF_INTC_IPRH_INT48 (0x00010000) -#define MCF_INTC_IPRH_INT49 (0x00020000) -#define MCF_INTC_IPRH_INT50 (0x00040000) -#define MCF_INTC_IPRH_INT51 (0x00080000) -#define MCF_INTC_IPRH_INT52 (0x00100000) -#define MCF_INTC_IPRH_INT53 (0x00200000) -#define MCF_INTC_IPRH_INT54 (0x00400000) -#define MCF_INTC_IPRH_INT55 (0x00800000) -#define MCF_INTC_IPRH_INT56 (0x01000000) -#define MCF_INTC_IPRH_INT57 (0x02000000) -#define MCF_INTC_IPRH_INT58 (0x04000000) -#define MCF_INTC_IPRH_INT59 (0x08000000) -#define MCF_INTC_IPRH_INT60 (0x10000000) -#define MCF_INTC_IPRH_INT61 (0x20000000) -#define MCF_INTC_IPRH_INT62 (0x40000000) -#define MCF_INTC_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IPRL */ -#define MCF_INTC_IPRL_INT0 (0x00000001) -#define MCF_INTC_IPRL_INT1 (0x00000002) -#define MCF_INTC_IPRL_INT2 (0x00000004) -#define MCF_INTC_IPRL_INT3 (0x00000008) -#define MCF_INTC_IPRL_INT4 (0x00000010) -#define MCF_INTC_IPRL_INT5 (0x00000020) -#define MCF_INTC_IPRL_INT6 (0x00000040) -#define MCF_INTC_IPRL_INT7 (0x00000080) -#define MCF_INTC_IPRL_INT8 (0x00000100) -#define MCF_INTC_IPRL_INT9 (0x00000200) -#define MCF_INTC_IPRL_INT10 (0x00000400) -#define MCF_INTC_IPRL_INT11 (0x00000800) -#define MCF_INTC_IPRL_INT12 (0x00001000) -#define MCF_INTC_IPRL_INT13 (0x00002000) -#define MCF_INTC_IPRL_INT14 (0x00004000) -#define MCF_INTC_IPRL_INT15 (0x00008000) -#define MCF_INTC_IPRL_INT16 (0x00010000) -#define MCF_INTC_IPRL_INT17 (0x00020000) -#define MCF_INTC_IPRL_INT18 (0x00040000) -#define MCF_INTC_IPRL_INT19 (0x00080000) -#define MCF_INTC_IPRL_INT20 (0x00100000) -#define MCF_INTC_IPRL_INT21 (0x00200000) -#define MCF_INTC_IPRL_INT22 (0x00400000) -#define MCF_INTC_IPRL_INT23 (0x00800000) -#define MCF_INTC_IPRL_INT24 (0x01000000) -#define MCF_INTC_IPRL_INT25 (0x02000000) -#define MCF_INTC_IPRL_INT26 (0x04000000) -#define MCF_INTC_IPRL_INT27 (0x08000000) -#define MCF_INTC_IPRL_INT28 (0x10000000) -#define MCF_INTC_IPRL_INT29 (0x20000000) -#define MCF_INTC_IPRL_INT30 (0x40000000) -#define MCF_INTC_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRH */ -#define MCF_INTC_IMRH_INT_MASK32 (0x00000001) -#define MCF_INTC_IMRH_INT_MASK33 (0x00000002) -#define MCF_INTC_IMRH_INT_MASK34 (0x00000004) -#define MCF_INTC_IMRH_INT_MASK35 (0x00000008) -#define MCF_INTC_IMRH_INT_MASK36 (0x00000010) -#define MCF_INTC_IMRH_INT_MASK37 (0x00000020) -#define MCF_INTC_IMRH_INT_MASK38 (0x00000040) -#define MCF_INTC_IMRH_INT_MASK39 (0x00000080) -#define MCF_INTC_IMRH_INT_MASK40 (0x00000100) -#define MCF_INTC_IMRH_INT_MASK41 (0x00000200) -#define MCF_INTC_IMRH_INT_MASK42 (0x00000400) -#define MCF_INTC_IMRH_INT_MASK43 (0x00000800) -#define MCF_INTC_IMRH_INT_MASK44 (0x00001000) -#define MCF_INTC_IMRH_INT_MASK45 (0x00002000) -#define MCF_INTC_IMRH_INT_MASK46 (0x00004000) -#define MCF_INTC_IMRH_INT_MASK47 (0x00008000) -#define MCF_INTC_IMRH_INT_MASK48 (0x00010000) -#define MCF_INTC_IMRH_INT_MASK49 (0x00020000) -#define MCF_INTC_IMRH_INT_MASK50 (0x00040000) -#define MCF_INTC_IMRH_INT_MASK51 (0x00080000) -#define MCF_INTC_IMRH_INT_MASK52 (0x00100000) -#define MCF_INTC_IMRH_INT_MASK53 (0x00200000) -#define MCF_INTC_IMRH_INT_MASK54 (0x00400000) -#define MCF_INTC_IMRH_INT_MASK55 (0x00800000) -#define MCF_INTC_IMRH_INT_MASK56 (0x01000000) -#define MCF_INTC_IMRH_INT_MASK57 (0x02000000) -#define MCF_INTC_IMRH_INT_MASK58 (0x04000000) -#define MCF_INTC_IMRH_INT_MASK59 (0x08000000) -#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) -#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) -#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) -#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRL */ -#define MCF_INTC_IMRL_INT_MASK0 (0x00000001) -#define MCF_INTC_IMRL_INT_MASK1 (0x00000002) -#define MCF_INTC_IMRL_INT_MASK2 (0x00000004) -#define MCF_INTC_IMRL_INT_MASK3 (0x00000008) -#define MCF_INTC_IMRL_INT_MASK4 (0x00000010) -#define MCF_INTC_IMRL_INT_MASK5 (0x00000020) -#define MCF_INTC_IMRL_INT_MASK6 (0x00000040) -#define MCF_INTC_IMRL_INT_MASK7 (0x00000080) -#define MCF_INTC_IMRL_INT_MASK8 (0x00000100) -#define MCF_INTC_IMRL_INT_MASK9 (0x00000200) -#define MCF_INTC_IMRL_INT_MASK10 (0x00000400) -#define MCF_INTC_IMRL_INT_MASK11 (0x00000800) -#define MCF_INTC_IMRL_INT_MASK12 (0x00001000) -#define MCF_INTC_IMRL_INT_MASK13 (0x00002000) -#define MCF_INTC_IMRL_INT_MASK14 (0x00004000) -#define MCF_INTC_IMRL_INT_MASK15 (0x00008000) -#define MCF_INTC_IMRL_INT_MASK16 (0x00010000) -#define MCF_INTC_IMRL_INT_MASK17 (0x00020000) -#define MCF_INTC_IMRL_INT_MASK18 (0x00040000) -#define MCF_INTC_IMRL_INT_MASK19 (0x00080000) -#define MCF_INTC_IMRL_INT_MASK20 (0x00100000) -#define MCF_INTC_IMRL_INT_MASK21 (0x00200000) -#define MCF_INTC_IMRL_INT_MASK22 (0x00400000) -#define MCF_INTC_IMRL_INT_MASK23 (0x00800000) -#define MCF_INTC_IMRL_INT_MASK24 (0x01000000) -#define MCF_INTC_IMRL_INT_MASK25 (0x02000000) -#define MCF_INTC_IMRL_INT_MASK26 (0x04000000) -#define MCF_INTC_IMRL_INT_MASK27 (0x08000000) -#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) -#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) -#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) -#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCH */ -#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCL */ -#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001) -#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) -#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) -#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) -#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) -#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) -#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) -#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_ICONFIG */ -#define MCF_INTC_ICONFIG_EMASK (0x0020) -#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200) -#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400) -#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800) -#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000) -#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000) -#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000) -#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000) - -/* Bit definitions and macros for MCF_INTC_SIMR */ -#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0) - -/* Bit definitions and macros for MCF_INTC_CIMR */ -#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0) - -/* Bit definitions and macros for MCF_INTC_CLMASK */ -#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_INTC_SLMASK */ -#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_INTC_ICR */ -#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0) - -/* Bit definitions and macros for MCF_INTC_SWIACK */ -#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_INTC_LIACK */ -#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) - -/********************************************************************* -* -* Interrupt Controller (INTC_IACK) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC_IACK_GSWIACK (*(vuint8 *)(0xFC0540E0)) -#define MCF_INTC_IACK_GL1IACK (*(vuint8 *)(0xFC0540E4)) -#define MCF_INTC_IACK_GL2IACK (*(vuint8 *)(0xFC0540E8)) -#define MCF_INTC_IACK_GL3IACK (*(vuint8 *)(0xFC0540EC)) -#define MCF_INTC_IACK_GL4IACK (*(vuint8 *)(0xFC0540F0)) -#define MCF_INTC_IACK_GL5IACK (*(vuint8 *)(0xFC0540F4)) -#define MCF_INTC_IACK_GL6IACK (*(vuint8 *)(0xFC0540F8)) -#define MCF_INTC_IACK_GL7IACK (*(vuint8 *)(0xFC0540FC)) -#define MCF_INTC_IACK_GLIACK(x) (*(vuint8 *)(0xFC0540E4+((x-1)*0x004))) - -/* Bit definitions and macros for MCF_INTC_IACK_GSWIACK */ -#define MCF_INTC_IACK_GSWIACK_VECTOR(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_INTC_IACK_GLIACK */ -#define MCF_INTC_IACK_GLIACK_VECTOR(x) (((x)&0xFF)<<0) - -/********************************************************************* -* -* I2C Module (I2C) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_I2C_I2AR (*(vuint8 *)(0xFC058000)) -#define MCF_I2C_I2FDR (*(vuint8 *)(0xFC058004)) -#define MCF_I2C_I2CR (*(vuint8 *)(0xFC058008)) -#define MCF_I2C_I2SR (*(vuint8 *)(0xFC05800C)) -#define MCF_I2C_I2DR (*(vuint8 *)(0xFC058010)) - -/* Bit definitions and macros for MCF_I2C_I2AR */ -#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_I2C_I2FDR */ -#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) - -/* Bit definitions and macros for MCF_I2C_I2CR */ -#define MCF_I2C_I2CR_RSTA (0x04) -#define MCF_I2C_I2CR_TXAK (0x08) -#define MCF_I2C_I2CR_MTX (0x10) -#define MCF_I2C_I2CR_MSTA (0x20) -#define MCF_I2C_I2CR_IIEN (0x40) -#define MCF_I2C_I2CR_IEN (0x80) - -/* Bit definitions and macros for MCF_I2C_I2SR */ -#define MCF_I2C_I2SR_RXAK (0x01) -#define MCF_I2C_I2SR_IIF (0x02) -#define MCF_I2C_I2SR_SRW (0x04) -#define MCF_I2C_I2SR_IAL (0x10) -#define MCF_I2C_I2SR_IBB (0x20) -#define MCF_I2C_I2SR_IAAS (0x40) -#define MCF_I2C_I2SR_ICF (0x80) - -/* Bit definitions and macros for MCF_I2C_I2DR */ -#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) - -/********************************************************************* -* -* Queued Serial Peripheral Interface (QSPI) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_QSPI_QMR (*(vuint16*)(0xFC05C000)) -#define MCF_QSPI_QDLYR (*(vuint16*)(0xFC05C004)) -#define MCF_QSPI_QWR (*(vuint16*)(0xFC05C008)) -#define MCF_QSPI_QIR (*(vuint16*)(0xFC05C00C)) -#define MCF_QSPI_QAR (*(vuint16*)(0xFC05C010)) -#define MCF_QSPI_QDR (*(vuint16*)(0xFC05C014)) - -/* Bit definitions and macros for MCF_QSPI_QMR */ -#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QMR_CPHA (0x0100) -#define MCF_QSPI_QMR_CPOL (0x0200) -#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) -#define MCF_QSPI_QMR_DOHIE (0x4000) -#define MCF_QSPI_QMR_MSTR (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QDLYR */ -#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define MCF_QSPI_QDLYR_SPE (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QWR */ -#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) -#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define MCF_QSPI_QWR_CSIV (0x1000) -#define MCF_QSPI_QWR_WRTO (0x2000) -#define MCF_QSPI_QWR_WREN (0x4000) -#define MCF_QSPI_QWR_HALT (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QIR */ -#define MCF_QSPI_QIR_SPIF (0x0001) -#define MCF_QSPI_QIR_ABRT (0x0004) -#define MCF_QSPI_QIR_WCEF (0x0008) -#define MCF_QSPI_QIR_SPIFE (0x0100) -#define MCF_QSPI_QIR_ABRTE (0x0400) -#define MCF_QSPI_QIR_WCEFE (0x0800) -#define MCF_QSPI_QIR_ABRTL (0x1000) -#define MCF_QSPI_QIR_ABRTB (0x4000) -#define MCF_QSPI_QIR_WCEFB (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QAR */ -#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) -#define MCF_QSPI_QAR_TRANS (0x0000) -#define MCF_QSPI_QAR_RECV (0x0010) -#define MCF_QSPI_QAR_CMD (0x0020) - -/* Bit definitions and macros for MCF_QSPI_QDR */ -#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0) -#define MCF_QSPI_QDR_CONT (0x8000) -#define MCF_QSPI_QDR_BITSE (0x4000) -#define MCF_QSPI_QDR_DT (0x2000) -#define MCF_QSPI_QDR_DSCK (0x1000) -#define MCF_QSPI_QDR_QSPI_CS3 (0x0800) -#define MCF_QSPI_QDR_QSPI_CS2 (0x0400) -#define MCF_QSPI_QDR_QSPI_CS1 (0x0200) -#define MCF_QSPI_QDR_QSPI_CS0 (0x0100) - -/********************************************************************* -* -* Universal Asynchronous Receiver Transmitter (UART) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_UART0_UMR (*(vuint8 *)(0xFC060000)) -#define MCF_UART0_USR (*(vuint8 *)(0xFC060004)) -#define MCF_UART0_UCSR (*(vuint8 *)(0xFC060004)) -#define MCF_UART0_UCR (*(vuint8 *)(0xFC060008)) -#define MCF_UART0_URB (*(vuint8 *)(0xFC06000C)) -#define MCF_UART0_UTB (*(vuint8 *)(0xFC06000C)) -#define MCF_UART0_UIPCR (*(vuint8 *)(0xFC060010)) -#define MCF_UART0_UACR (*(vuint8 *)(0xFC060010)) -#define MCF_UART0_UISR (*(vuint8 *)(0xFC060014)) -#define MCF_UART0_UIMR (*(vuint8 *)(0xFC060014)) -#define MCF_UART0_UBG1 (*(vuint8 *)(0xFC060018)) -#define MCF_UART0_UBG2 (*(vuint8 *)(0xFC06001C)) -#define MCF_UART0_UIP (*(vuint8 *)(0xFC060034)) -#define MCF_UART0_UOP1 (*(vuint8 *)(0xFC060038)) -#define MCF_UART0_UOP0 (*(vuint8 *)(0xFC06003C)) -#define MCF_UART1_UMR (*(vuint8 *)(0xFC064000)) -#define MCF_UART1_USR (*(vuint8 *)(0xFC064004)) -#define MCF_UART1_UCSR (*(vuint8 *)(0xFC064004)) -#define MCF_UART1_UCR (*(vuint8 *)(0xFC064008)) -#define MCF_UART1_URB (*(vuint8 *)(0xFC06400C)) -#define MCF_UART1_UTB (*(vuint8 *)(0xFC06400C)) -#define MCF_UART1_UIPCR (*(vuint8 *)(0xFC064010)) -#define MCF_UART1_UACR (*(vuint8 *)(0xFC064010)) -#define MCF_UART1_UISR (*(vuint8 *)(0xFC064014)) -#define MCF_UART1_UIMR (*(vuint8 *)(0xFC064014)) -#define MCF_UART1_UBG1 (*(vuint8 *)(0xFC064018)) -#define MCF_UART1_UBG2 (*(vuint8 *)(0xFC06401C)) -#define MCF_UART1_UIP (*(vuint8 *)(0xFC064034)) -#define MCF_UART1_UOP1 (*(vuint8 *)(0xFC064038)) -#define MCF_UART1_UOP0 (*(vuint8 *)(0xFC06403C)) -#define MCF_UART2_UMR (*(vuint8 *)(0xFC068000)) -#define MCF_UART2_USR (*(vuint8 *)(0xFC068004)) -#define MCF_UART2_UCSR (*(vuint8 *)(0xFC068004)) -#define MCF_UART2_UCR (*(vuint8 *)(0xFC068008)) -#define MCF_UART2_URB (*(vuint8 *)(0xFC06800C)) -#define MCF_UART2_UTB (*(vuint8 *)(0xFC06800C)) -#define MCF_UART2_UIPCR (*(vuint8 *)(0xFC068010)) -#define MCF_UART2_UACR (*(vuint8 *)(0xFC068010)) -#define MCF_UART2_UISR (*(vuint8 *)(0xFC068014)) -#define MCF_UART2_UIMR (*(vuint8 *)(0xFC068014)) -#define MCF_UART2_UBG1 (*(vuint8 *)(0xFC068018)) -#define MCF_UART2_UBG2 (*(vuint8 *)(0xFC06801C)) -#define MCF_UART2_UIP (*(vuint8 *)(0xFC068034)) -#define MCF_UART2_UOP1 (*(vuint8 *)(0xFC068038)) -#define MCF_UART2_UOP0 (*(vuint8 *)(0xFC06803C)) -#define MCF_UART_UMR(x) (*(vuint8 *)(0xFC060000+((x)*0x4000))) -#define MCF_UART_USR(x) (*(vuint8 *)(0xFC060004+((x)*0x4000))) -#define MCF_UART_UCSR(x) (*(vuint8 *)(0xFC060004+((x)*0x4000))) -#define MCF_UART_UCR(x) (*(vuint8 *)(0xFC060008+((x)*0x4000))) -#define MCF_UART_URB(x) (*(vuint8 *)(0xFC06000C+((x)*0x4000))) -#define MCF_UART_UTB(x) (*(vuint8 *)(0xFC06000C+((x)*0x4000))) -#define MCF_UART_UIPCR(x) (*(vuint8 *)(0xFC060010+((x)*0x4000))) -#define MCF_UART_UACR(x) (*(vuint8 *)(0xFC060010+((x)*0x4000))) -#define MCF_UART_UISR(x) (*(vuint8 *)(0xFC060014+((x)*0x4000))) -#define MCF_UART_UIMR(x) (*(vuint8 *)(0xFC060014+((x)*0x4000))) -#define MCF_UART_UBG1(x) (*(vuint8 *)(0xFC060018+((x)*0x4000))) -#define MCF_UART_UBG2(x) (*(vuint8 *)(0xFC06001C+((x)*0x4000))) -#define MCF_UART_UIP(x) (*(vuint8 *)(0xFC060034+((x)*0x4000))) -#define MCF_UART_UOP1(x) (*(vuint8 *)(0xFC060038+((x)*0x4000))) -#define MCF_UART_UOP0(x) (*(vuint8 *)(0xFC06003C+((x)*0x4000))) - -/* Bit definitions and macros for MCF_UART_UMR */ -#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) -#define MCF_UART_UMR_PT (0x04) -#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) -#define MCF_UART_UMR_ERR (0x20) -#define MCF_UART_UMR_RXIRQ (0x40) -#define MCF_UART_UMR_RXRTS (0x80) -#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) -#define MCF_UART_UMR_TXCTS (0x10) -#define MCF_UART_UMR_TXRTS (0x20) -#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) -#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) -#define MCF_UART_UMR_PM_MULTI_DATA (0x18) -#define MCF_UART_UMR_PM_NONE (0x10) -#define MCF_UART_UMR_PM_FORCE_HI (0x0C) -#define MCF_UART_UMR_PM_FORCE_LO (0x08) -#define MCF_UART_UMR_PM_ODD (0x04) -#define MCF_UART_UMR_PM_EVEN (0x00) -#define MCF_UART_UMR_BC_5 (0x00) -#define MCF_UART_UMR_BC_6 (0x01) -#define MCF_UART_UMR_BC_7 (0x02) -#define MCF_UART_UMR_BC_8 (0x03) -#define MCF_UART_UMR_CM_NORMAL (0x00) -#define MCF_UART_UMR_CM_ECHO (0x40) -#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) -#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) -#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) -#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) -#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF_UART_USR */ -#define MCF_UART_USR_RXRDY (0x01) -#define MCF_UART_USR_FFULL (0x02) -#define MCF_UART_USR_TXRDY (0x04) -#define MCF_UART_USR_TXEMP (0x08) -#define MCF_UART_USR_OE (0x10) -#define MCF_UART_USR_PE (0x20) -#define MCF_UART_USR_FE (0x40) -#define MCF_UART_USR_RB (0x80) - -/* Bit definitions and macros for MCF_UART_UCSR */ -#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) -#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) -#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) -#define MCF_UART_UCSR_RCS_CTM16 (0xE0) -#define MCF_UART_UCSR_RCS_CTM (0xF0) -#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) -#define MCF_UART_UCSR_TCS_CTM16 (0x0E) -#define MCF_UART_UCSR_TCS_CTM (0x0F) - -/* Bit definitions and macros for MCF_UART_UCR */ -#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) -#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) -#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) -#define MCF_UART_UCR_NONE (0x00) -#define MCF_UART_UCR_STOP_BREAK (0x70) -#define MCF_UART_UCR_START_BREAK (0x60) -#define MCF_UART_UCR_BKCHGINT (0x50) -#define MCF_UART_UCR_RESET_ERROR (0x40) -#define MCF_UART_UCR_RESET_TX (0x30) -#define MCF_UART_UCR_RESET_RX (0x20) -#define MCF_UART_UCR_RESET_MR (0x10) -#define MCF_UART_UCR_TX_DISABLED (0x08) -#define MCF_UART_UCR_TX_ENABLED (0x04) -#define MCF_UART_UCR_RX_DISABLED (0x02) -#define MCF_UART_UCR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF_UART_UIPCR */ -#define MCF_UART_UIPCR_CTS (0x01) -#define MCF_UART_UIPCR_COS (0x10) - -/* Bit definitions and macros for MCF_UART_UACR */ -#define MCF_UART_UACR_IEC (0x01) - -/* Bit definitions and macros for MCF_UART_UISR */ -#define MCF_UART_UISR_TXRDY (0x01) -#define MCF_UART_UISR_RXRDY_FU (0x02) -#define MCF_UART_UISR_DB (0x04) -#define MCF_UART_UISR_RXFTO (0x08) -#define MCF_UART_UISR_TXFIFO (0x10) -#define MCF_UART_UISR_RXFIFO (0x20) -#define MCF_UART_UISR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIMR */ -#define MCF_UART_UIMR_TXRDY (0x01) -#define MCF_UART_UIMR_RXRDY_FU (0x02) -#define MCF_UART_UIMR_DB (0x04) -#define MCF_UART_UIMR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIP */ -#define MCF_UART_UIP_CTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP1 */ -#define MCF_UART_UOP1_RTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP0 */ -#define MCF_UART_UOP0_RTS (0x01) - -/********************************************************************* -* -* DMA Timers (DTIM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_DTIM0_DTMR (*(vuint16*)(0xFC070000)) -#define MCF_DTIM0_DTXMR (*(vuint8 *)(0xFC070002)) -#define MCF_DTIM0_DTER (*(vuint8 *)(0xFC070003)) -#define MCF_DTIM0_DTRR (*(vuint32*)(0xFC070004)) -#define MCF_DTIM0_DTCR (*(vuint32*)(0xFC070008)) -#define MCF_DTIM0_DTCN (*(vuint32*)(0xFC07000C)) -#define MCF_DTIM1_DTMR (*(vuint16*)(0xFC074000)) -#define MCF_DTIM1_DTXMR (*(vuint8 *)(0xFC074002)) -#define MCF_DTIM1_DTER (*(vuint8 *)(0xFC074003)) -#define MCF_DTIM1_DTRR (*(vuint32*)(0xFC074004)) -#define MCF_DTIM1_DTCR (*(vuint32*)(0xFC074008)) -#define MCF_DTIM1_DTCN (*(vuint32*)(0xFC07400C)) -#define MCF_DTIM2_DTMR (*(vuint16*)(0xFC078000)) -#define MCF_DTIM2_DTXMR (*(vuint8 *)(0xFC078002)) -#define MCF_DTIM2_DTER (*(vuint8 *)(0xFC078003)) -#define MCF_DTIM2_DTRR (*(vuint32*)(0xFC078004)) -#define MCF_DTIM2_DTCR (*(vuint32*)(0xFC078008)) -#define MCF_DTIM2_DTCN (*(vuint32*)(0xFC07800C)) -#define MCF_DTIM3_DTMR (*(vuint16*)(0xFC07C000)) -#define MCF_DTIM3_DTXMR (*(vuint8 *)(0xFC07C002)) -#define MCF_DTIM3_DTER (*(vuint8 *)(0xFC07C003)) -#define MCF_DTIM3_DTRR (*(vuint32*)(0xFC07C004)) -#define MCF_DTIM3_DTCR (*(vuint32*)(0xFC07C008)) -#define MCF_DTIM3_DTCN (*(vuint32*)(0xFC07C00C)) -#define MCF_DTIM_DTMR(x) (*(vuint16*)(0xFC070000+((x)*0x4000))) -#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(0xFC070002+((x)*0x4000))) -#define MCF_DTIM_DTER(x) (*(vuint8 *)(0xFC070003+((x)*0x4000))) -#define MCF_DTIM_DTRR(x) (*(vuint32*)(0xFC070004+((x)*0x4000))) -#define MCF_DTIM_DTCR(x) (*(vuint32*)(0xFC070008+((x)*0x4000))) -#define MCF_DTIM_DTCN(x) (*(vuint32*)(0xFC07000C+((x)*0x4000))) - -/* Bit definitions and macros for MCF_DTIM_DTMR */ -#define MCF_DTIM_DTMR_RST (0x0001) -#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) -#define MCF_DTIM_DTMR_FRR (0x0008) -#define MCF_DTIM_DTMR_ORRI (0x0010) -#define MCF_DTIM_DTMR_OM (0x0020) -#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) -#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) -#define MCF_DTIM_DTMR_CE_ANY (0x00C0) -#define MCF_DTIM_DTMR_CE_FALL (0x0080) -#define MCF_DTIM_DTMR_CE_RISE (0x0040) -#define MCF_DTIM_DTMR_CE_NONE (0x0000) -#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) -#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) -#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) -#define MCF_DTIM_DTMR_CLK_STOP (0x0000) - -/* Bit definitions and macros for MCF_DTIM_DTXMR */ -#define MCF_DTIM_DTXMR_MODE16 (0x01) -#define MCF_DTIM_DTXMR_DMAEN (0x80) - -/* Bit definitions and macros for MCF_DTIM_DTER */ -#define MCF_DTIM_DTER_CAP (0x01) -#define MCF_DTIM_DTER_REF (0x02) - -/* Bit definitions and macros for MCF_DTIM_DTRR */ -#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DTIM_DTCR */ -#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DTIM_DTCN */ -#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* -* -* Programmable Interrupt Timer Modules (PIT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PIT0_PCSR (*(vuint16*)(0xFC080000)) -#define MCF_PIT0_PMR (*(vuint16*)(0xFC080002)) -#define MCF_PIT0_PCNTR (*(vuint16*)(0xFC080004)) -#define MCF_PIT1_PCSR (*(vuint16*)(0xFC084000)) -#define MCF_PIT1_PMR (*(vuint16*)(0xFC084002)) -#define MCF_PIT1_PCNTR (*(vuint16*)(0xFC084004)) -#define MCF_PIT2_PCSR (*(vuint16*)(0xFC088000)) -#define MCF_PIT2_PMR (*(vuint16*)(0xFC088002)) -#define MCF_PIT2_PCNTR (*(vuint16*)(0xFC088004)) -#define MCF_PIT3_PCSR (*(vuint16*)(0xFC08C000)) -#define MCF_PIT3_PMR (*(vuint16*)(0xFC08C002)) -#define MCF_PIT3_PCNTR (*(vuint16*)(0xFC08C004)) -#define MCF_PIT_PCSR(x) (*(vuint16*)(0xFC080000+((x)*0x4000))) -#define MCF_PIT_PMR(x) (*(vuint16*)(0xFC080002+((x)*0x4000))) -#define MCF_PIT_PCNTR(x) (*(vuint16*)(0xFC080004+((x)*0x4000))) - -/* Bit definitions and macros for MCF_PIT_PCSR */ -#define MCF_PIT_PCSR_EN (0x0001) -#define MCF_PIT_PCSR_RLD (0x0002) -#define MCF_PIT_PCSR_PIF (0x0004) -#define MCF_PIT_PCSR_PIE (0x0008) -#define MCF_PIT_PCSR_OVW (0x0010) -#define MCF_PIT_PCSR_HALTED (0x0020) -#define MCF_PIT_PCSR_DOZE (0x0040) -#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) - -/* Bit definitions and macros for MCF_PIT_PMR */ -#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_PIT_PCNTR */ -#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0) - -/********************************************************************* -* -* Pulse Width Modulation (PWM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PWM_PWME (*(vuint8 *)(0xFC090020)) -#define MCF_PWM_PWMPOL (*(vuint8 *)(0xFC090021)) -#define MCF_PWM_PWMCLK (*(vuint8 *)(0xFC090022)) -#define MCF_PWM_PWMPRCLK (*(vuint8 *)(0xFC090023)) -#define MCF_PWM_PWMCAE (*(vuint8 *)(0xFC090024)) -#define MCF_PWM_PWMCTL (*(vuint8 *)(0xFC090025)) -#define MCF_PWM_PWMSCLA (*(vuint8 *)(0xFC090028)) -#define MCF_PWM_PWMSCLB (*(vuint8 *)(0xFC090029)) -#define MCF_PWM_PWMCNT0 (*(vuint8 *)(0xFC09002C)) -#define MCF_PWM_PWMCNT1 (*(vuint8 *)(0xFC09002D)) -#define MCF_PWM_PWMCNT2 (*(vuint8 *)(0xFC09002E)) -#define MCF_PWM_PWMCNT3 (*(vuint8 *)(0xFC09002F)) -#define MCF_PWM_PWMCNT4 (*(vuint8 *)(0xFC090030)) -#define MCF_PWM_PWMCNT5 (*(vuint8 *)(0xFC090031)) -#define MCF_PWM_PWMCNT6 (*(vuint8 *)(0xFC090032)) -#define MCF_PWM_PWMCNT7 (*(vuint8 *)(0xFC090033)) -#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(0xFC09002C+((x)*0x001))) -#define MCF_PWM_PWMPER0 (*(vuint8 *)(0xFC090034)) -#define MCF_PWM_PWMPER1 (*(vuint8 *)(0xFC090035)) -#define MCF_PWM_PWMPER2 (*(vuint8 *)(0xFC090036)) -#define MCF_PWM_PWMPER3 (*(vuint8 *)(0xFC090037)) -#define MCF_PWM_PWMPER4 (*(vuint8 *)(0xFC090038)) -#define MCF_PWM_PWMPER5 (*(vuint8 *)(0xFC090039)) -#define MCF_PWM_PWMPER6 (*(vuint8 *)(0xFC09003A)) -#define MCF_PWM_PWMPER7 (*(vuint8 *)(0xFC09003B)) -#define MCF_PWM_PWMPER(x) (*(vuint8 *)(0xFC090034+((x)*0x001))) -#define MCF_PWM_PWMDTY0 (*(vuint8 *)(0xFC09003C)) -#define MCF_PWM_PWMDTY1 (*(vuint8 *)(0xFC09003D)) -#define MCF_PWM_PWMDTY2 (*(vuint8 *)(0xFC09003E)) -#define MCF_PWM_PWMDTY3 (*(vuint8 *)(0xFC09003F)) -#define MCF_PWM_PWMDTY4 (*(vuint8 *)(0xFC090040)) -#define MCF_PWM_PWMDTY5 (*(vuint8 *)(0xFC090041)) -#define MCF_PWM_PWMDTY6 (*(vuint8 *)(0xFC090042)) -#define MCF_PWM_PWMDTY7 (*(vuint8 *)(0xFC090043)) -#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(0xFC09003C+((x)*0x001))) -#define MCF_PWM_PWMSDN (*(vuint8 *)(0xFC090044)) - -/* Bit definitions and macros for MCF_PWM_PWME */ -#define MCF_PWM_PWME_PWME0 (0x01) -#define MCF_PWM_PWME_PWME1 (0x02) -#define MCF_PWM_PWME_PWME2 (0x04) -#define MCF_PWM_PWME_PWME3 (0x08) -#define MCF_PWM_PWME_PWME4 (0x10) -#define MCF_PWM_PWME_PWME5 (0x20) -#define MCF_PWM_PWME_PWME6 (0x40) -#define MCF_PWM_PWME_PWME7 (0x80) - -/* Bit definitions and macros for MCF_PWM_PWMPOL */ -#define MCF_PWM_PWMPOL_PPOL0 (0x01) -#define MCF_PWM_PWMPOL_PPOL1 (0x02) -#define MCF_PWM_PWMPOL_PPOL2 (0x04) -#define MCF_PWM_PWMPOL_PPOL3 (0x08) -#define MCF_PWM_PWMPOL_PPOL4 (0x10) -#define MCF_PWM_PWMPOL_PPOL5 (0x20) -#define MCF_PWM_PWMPOL_PPOL6 (0x40) -#define MCF_PWM_PWMPOL_PPOL7 (0x80) - -/* Bit definitions and macros for MCF_PWM_PWMCLK */ -#define MCF_PWM_PWMCLK_PCLK0 (0x01) -#define MCF_PWM_PWMCLK_PCLK1 (0x02) -#define MCF_PWM_PWMCLK_PCLK2 (0x04) -#define MCF_PWM_PWMCLK_PCLK3 (0x08) -#define MCF_PWM_PWMCLK_PCLK4 (0x10) -#define MCF_PWM_PWMCLK_PCLK5 (0x20) -#define MCF_PWM_PWMCLK_PCLK6 (0x40) -#define MCF_PWM_PWMCLK_PCLK7 (0x80) - -/* Bit definitions and macros for MCF_PWM_PWMPRCLK */ -#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x07)<<0) -#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_PWM_PWMCAE */ -#define MCF_PWM_PWMCAE_CAE0 (0x01) -#define MCF_PWM_PWMCAE_CAE1 (0x02) -#define MCF_PWM_PWMCAE_CAE2 (0x04) -#define MCF_PWM_PWMCAE_CAE3 (0x08) -#define MCF_PWM_PWMCAE_CAE4 (0x10) -#define MCF_PWM_PWMCAE_CAE5 (0x20) -#define MCF_PWM_PWMCAE_CAE6 (0x40) -#define MCF_PWM_PWMCAE_CAE7 (0x80) - -/* Bit definitions and macros for MCF_PWM_PWMCTL */ -#define MCF_PWM_PWMCTL_PFRZ (0x04) -#define MCF_PWM_PWMCTL_PSWAI (0x08) -#define MCF_PWM_PWMCTL_CON01 (0x10) -#define MCF_PWM_PWMCTL_CON23 (0x20) -#define MCF_PWM_PWMCTL_CON45 (0x40) -#define MCF_PWM_PWMCTL_CON67 (0x80) - -/* Bit definitions and macros for MCF_PWM_PWMSCLA */ -#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMSCLB */ -#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMCNT */ -#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMPER */ -#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMDTY */ -#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMSDN */ -#define MCF_PWM_PWMSDN_SDNEN (0x01) -#define MCF_PWM_PWMSDN_PWM7IL (0x02) -#define MCF_PWM_PWMSDN_PWM7IN (0x04) -#define MCF_PWM_PWMSDN_LVL (0x10) -#define MCF_PWM_PWMSDN_RESTART (0x20) -#define MCF_PWM_PWMSDN_IE (0x40) -#define MCF_PWM_PWMSDN_IF (0x80) - -/********************************************************************* -* -* Edge Port Module (EPORT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_EPORT_EPPAR (*(vuint16*)(0xFC094000)) -#define MCF_EPORT_EPDDR (*(vuint8 *)(0xFC094002)) -#define MCF_EPORT_EPIER (*(vuint8 *)(0xFC094003)) -#define MCF_EPORT_EPDR (*(vuint8 *)(0xFC094004)) -#define MCF_EPORT_EPPDR (*(vuint8 *)(0xFC094005)) -#define MCF_EPORT_EPFR (*(vuint8 *)(0xFC094006)) - -/* Bit definitions and macros for MCF_EPORT_EPPAR */ -#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_LEVEL (0) -#define MCF_EPORT_EPPAR_RISING (1) -#define MCF_EPORT_EPPAR_FALLING (2) -#define MCF_EPORT_EPPAR_BOTH (3) -#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) -#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) -#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) -#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) -#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) -#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) -#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) -#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) -#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) -#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) -#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) -#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) -#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) -#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) -#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) -#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) -#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) -#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) -#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) -#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) -#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) - -/* Bit definitions and macros for MCF_EPORT_EPDDR */ -#define MCF_EPORT_EPDDR_EPDD1 (0x02) -#define MCF_EPORT_EPDDR_EPDD2 (0x04) -#define MCF_EPORT_EPDDR_EPDD3 (0x08) -#define MCF_EPORT_EPDDR_EPDD4 (0x10) -#define MCF_EPORT_EPDDR_EPDD5 (0x20) -#define MCF_EPORT_EPDDR_EPDD6 (0x40) -#define MCF_EPORT_EPDDR_EPDD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPIER */ -#define MCF_EPORT_EPIER_EPIE1 (0x02) -#define MCF_EPORT_EPIER_EPIE2 (0x04) -#define MCF_EPORT_EPIER_EPIE3 (0x08) -#define MCF_EPORT_EPIER_EPIE4 (0x10) -#define MCF_EPORT_EPIER_EPIE5 (0x20) -#define MCF_EPORT_EPIER_EPIE6 (0x40) -#define MCF_EPORT_EPIER_EPIE7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPDR */ -#define MCF_EPORT_EPDR_EPD1 (0x02) -#define MCF_EPORT_EPDR_EPD2 (0x04) -#define MCF_EPORT_EPDR_EPD3 (0x08) -#define MCF_EPORT_EPDR_EPD4 (0x10) -#define MCF_EPORT_EPDR_EPD5 (0x20) -#define MCF_EPORT_EPDR_EPD6 (0x40) -#define MCF_EPORT_EPDR_EPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPPDR */ -#define MCF_EPORT_EPPDR_EPPD1 (0x02) -#define MCF_EPORT_EPPDR_EPPD2 (0x04) -#define MCF_EPORT_EPPDR_EPPD3 (0x08) -#define MCF_EPORT_EPPDR_EPPD4 (0x10) -#define MCF_EPORT_EPPDR_EPPD5 (0x20) -#define MCF_EPORT_EPPDR_EPPD6 (0x40) -#define MCF_EPORT_EPPDR_EPPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPFR */ -#define MCF_EPORT_EPFR_EPF1 (0x02) -#define MCF_EPORT_EPFR_EPF2 (0x04) -#define MCF_EPORT_EPFR_EPF3 (0x08) -#define MCF_EPORT_EPFR_EPF4 (0x10) -#define MCF_EPORT_EPFR_EPF5 (0x20) -#define MCF_EPORT_EPFR_EPF6 (0x40) -#define MCF_EPORT_EPFR_EPF7 (0x80) - -/********************************************************************* -* -* Watchdog Timer Modules (WTM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_WTM_WCR (*(vuint16*)(0xFC098000)) -#define MCF_WTM_WMR (*(vuint16*)(0xFC098002)) -#define MCF_WTM_WCNTR (*(vuint16*)(0xFC098004)) -#define MCF_WTM_WSR (*(vuint16*)(0xFC098006)) - -/* Bit definitions and macros for MCF_WTM_WCR */ -#define MCF_WTM_WCR_EN (0x0001) -#define MCF_WTM_WCR_HALTED (0x0002) -#define MCF_WTM_WCR_DOZE (0x0004) -#define MCF_WTM_WCR_WAIT (0x0008) - -/* Bit definitions and macros for MCF_WTM_WMR */ -#define MCF_WTM_WMR_WM(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_WTM_WCNTR */ -#define MCF_WTM_WCNTR_WC(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_WTM_WSR */ -#define MCF_WTM_WSR_WS(x) (((x)&0xFFFF)<<0) - -/********************************************************************* -* -* Chip Configuration Module (CCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CCM_CCR (*(vuint16*)(0xFC0A0004)) -#define MCF_CCM_RCON (*(vuint16*)(0xFC0A0008)) -#define MCF_CCM_CIR (*(vuint16*)(0xFC0A000A)) -#define MCF_CCM_MISCCR (*(vuint16*)(0xFC0A0010)) -#define MCF_CCM_CDR (*(vuint16*)(0xFC0A0012)) -#define MCF_CCM_UHCSR (*(vuint16*)(0xFC0A0014)) -#define MCF_CCM_UOCSR (*(vuint16*)(0xFC0A0016)) - -/* Bit definitions and macros for MCF_CCM_CCR */ -#define MCF_CCM_CCR_RESERVED (0x0001) -#define MCF_CCM_CCR_PLL_MODE (0x0003) -#define MCF_CCM_CCR_OSC_MODE (0x0005) -#define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) -#define MCF_CCM_CCR_LOAD (0x0021) -#define MCF_CCM_CCR_LIMP (0x0041) -#define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) - -/* Bit definitions and macros for MCF_CCM_RCON */ -#define MCF_CCM_RCON_RESERVED (0x0001) -#define MCF_CCM_RCON_PLL_MODE (0x0003) -#define MCF_CCM_RCON_OSC_MODE (0x0005) -#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) -#define MCF_CCM_RCON_LOAD (0x0021) -#define MCF_CCM_RCON_LIMP (0x0041) -#define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) - -/* Bit definitions and macros for MCF_CCM_CIR */ -#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) -#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) - -/* Bit definitions and macros for MCF_CCM_MISCCR */ -#define MCF_CCM_MISCCR_USBSRC (0x0001) -#define MCF_CCM_MISCCR_USBDIV (0x0002) -#define MCF_CCM_MISCCR_SSI_SRC (0x0010) -#define MCF_CCM_MISCCR_TIM_DMA (0x0020) -#define MCF_CCM_MISCCR_SSI_PUS (0x0040) -#define MCF_CCM_MISCCR_SSI_PUE (0x0080) -#define MCF_CCM_MISCCR_LCD_CHEN (0x0100) -#define MCF_CCM_MISCCR_LIMP (0x1000) -#define MCF_CCM_MISCCR_PLL_LOCK (0x2000) - -/* Bit definitions and macros for MCF_CCM_CDR */ -#define MCF_CCM_CDR_SSIDIV(x) (((x)&0x003F)<<0) -#define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) - -/* Bit definitions and macros for MCF_CCM_UHCSR */ -#define MCF_CCM_UHCSR_XPDE (0x0001) -#define MCF_CCM_UHCSR_UHMIE (0x0002) -#define MCF_CCM_UHCSR_WKUP (0x0004) -#define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) - -/* Bit definitions and macros for MCF_CCM_UOCSR */ -#define MCF_CCM_UOCSR_XPDE (0x0001) -#define MCF_CCM_UOCSR_UOMIE (0x0002) -#define MCF_CCM_UOCSR_WKUP (0x0004) -#define MCF_CCM_UOCSR_PWRFLT (0x0008) -#define MCF_CCM_UOCSR_SEND (0x0010) -#define MCF_CCM_UOCSR_VVLD (0x0020) -#define MCF_CCM_UOCSR_BVLD (0x0040) -#define MCF_CCM_UOCSR_AVLD (0x0080) -#define MCF_CCM_UOCSR_DPPU (0x0100) -#define MCF_CCM_UOCSR_DCR_VBUS (0x0200) -#define MCF_CCM_UOCSR_CRG_VBUS (0x0400) -#define MCF_CCM_UOCSR_DRV_VBUS (0x0800) -#define MCF_CCM_UOCSR_DMPD (0x1000) -#define MCF_CCM_UOCSR_DPPD (0x2000) -#define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) - -/********************************************************************* -* -* Reset Controller Module (RCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RCM_RCR (*(vuint8 *)(0xFC0A0000)) -#define MCF_RCM_RSR (*(vuint8 *)(0xFC0A0001)) - -/* Bit definitions and macros for MCF_RCM_RCR */ -#define MCF_RCM_RCR_FRCRSTOUT (0x40) -#define MCF_RCM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for MCF_RCM_RSR */ -#define MCF_RCM_RSR_LOL (0x01) -#define MCF_RCM_RSR_WDR_CORE (0x02) -#define MCF_RCM_RSR_EXT (0x04) -#define MCF_RCM_RSR_POR (0x08) -#define MCF_RCM_RSR_WDR_CHIP (0x10) -#define MCF_RCM_RSR_SOFT (0x20) - -/********************************************************************* -* -* General Purpose I/O (GPIO) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPIO_PODR_FECH (*(vuint8 *)(0xFC0A4000)) -#define MCF_GPIO_PODR_FECL (*(vuint8 *)(0xFC0A4001)) -#define MCF_GPIO_PODR_SSI (*(vuint8 *)(0xFC0A4002)) -#define MCF_GPIO_PODR_BUSCTL (*(vuint8 *)(0xFC0A4003)) -#define MCF_GPIO_PODR_BE (*(vuint8 *)(0xFC0A4004)) -#define MCF_GPIO_PODR_CS (*(vuint8 *)(0xFC0A4005)) -#define MCF_GPIO_PODR_PWM (*(vuint8 *)(0xFC0A4006)) -#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(0xFC0A4007)) -#define MCF_GPIO_PODR_UART (*(vuint8 *)(0xFC0A4009)) -#define MCF_GPIO_PODR_QSPI (*(vuint8 *)(0xFC0A400A)) -#define MCF_GPIO_PODR_TIMER (*(vuint8 *)(0xFC0A400B)) -#define MCF_GPIO_PODR_LCDDATAH (*(vuint8 *)(0xFC0A400D)) -#define MCF_GPIO_PODR_LCDDATAM (*(vuint8 *)(0xFC0A400E)) -#define MCF_GPIO_PODR_LCDDATAL (*(vuint8 *)(0xFC0A400F)) -#define MCF_GPIO_PODR_LCDCTLH (*(vuint8 *)(0xFC0A4010)) -#define MCF_GPIO_PODR_LCDCTLL (*(vuint8 *)(0xFC0A4011)) -#define MCF_GPIO_PDDR_FECH (*(vuint8 *)(0xFC0A4014)) -#define MCF_GPIO_PDDR_FECL (*(vuint8 *)(0xFC0A4015)) -#define MCF_GPIO_PDDR_SSI (*(vuint8 *)(0xFC0A4016)) -#define MCF_GPIO_PDDR_BUSCTL (*(vuint8 *)(0xFC0A4017)) -#define MCF_GPIO_PDDR_BE (*(vuint8 *)(0xFC0A4018)) -#define MCF_GPIO_PDDR_CS (*(vuint8 *)(0xFC0A4019)) -#define MCF_GPIO_PDDR_PWM (*(vuint8 *)(0xFC0A401A)) -#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(0xFC0A401B)) -#define MCF_GPIO_PDDR_UART (*(vuint8 *)(0xFC0A401D)) -#define MCF_GPIO_PDDR_QSPI (*(vuint8 *)(0xFC0A401E)) -#define MCF_GPIO_PDDR_TIMER (*(vuint8 *)(0xFC0A401F)) -#define MCF_GPIO_PDDR_LCDDATAH (*(vuint8 *)(0xFC0A4021)) -#define MCF_GPIO_PDDR_LCDDATAM (*(vuint8 *)(0xFC0A4022)) -#define MCF_GPIO_PDDR_LCDDATAL (*(vuint8 *)(0xFC0A4023)) -#define MCF_GPIO_PDDR_LCDCTLH (*(vuint8 *)(0xFC0A4024)) -#define MCF_GPIO_PDDR_LCDCTLL (*(vuint8 *)(0xFC0A4025)) -#define MCF_GPIO_PPDSDR_FECH (*(vuint8 *)(0xFC0A4028)) -#define MCF_GPIO_PPDSDR_FECL (*(vuint8 *)(0xFC0A4029)) -#define MCF_GPIO_PPDSDR_SSI (*(vuint8 *)(0xFC0A402A)) -#define MCF_GPIO_PPDSDR_BUSCTL (*(vuint8 *)(0xFC0A402B)) -#define MCF_GPIO_PPDSDR_BE (*(vuint8 *)(0xFC0A402C)) -#define MCF_GPIO_PPDSDR_CS (*(vuint8 *)(0xFC0A402D)) -#define MCF_GPIO_PPDSDR_PWM (*(vuint8 *)(0xFC0A402E)) -#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(0xFC0A402F)) -#define MCF_GPIO_PPDSDR_UART (*(vuint8 *)(0xFC0A4031)) -#define MCF_GPIO_PPDSDR_QSPI (*(vuint8 *)(0xFC0A4032)) -#define MCF_GPIO_PPDSDR_TIMER (*(vuint8 *)(0xFC0A4033)) -#define MCF_GPIO_PPDSDR_LCDDATAH (*(vuint8 *)(0xFC0A4035)) -#define MCF_GPIO_PPDSDR_LCDDATAM (*(vuint8 *)(0xFC0A4036)) -#define MCF_GPIO_PPDSDR_LCDDATAL (*(vuint8 *)(0xFC0A4037)) -#define MCF_GPIO_PPDSDR_LCDCTLH (*(vuint8 *)(0xFC0A4038)) -#define MCF_GPIO_PPDSDR_LCDCTLL (*(vuint8 *)(0xFC0A4039)) -#define MCF_GPIO_PCLRR_FECH (*(vuint8 *)(0xFC0A403C)) -#define MCF_GPIO_PCLRR_FECL (*(vuint8 *)(0xFC0A403D)) -#define MCF_GPIO_PCLRR_SSI (*(vuint8 *)(0xFC0A403E)) -#define MCF_GPIO_PCLRR_BUSCTL (*(vuint8 *)(0xFC0A403F)) -#define MCF_GPIO_PCLRR_BE (*(vuint8 *)(0xFC0A4040)) -#define MCF_GPIO_PCLRR_CS (*(vuint8 *)(0xFC0A4041)) -#define MCF_GPIO_PCLRR_PWM (*(vuint8 *)(0xFC0A4042)) -#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(0xFC0A4043)) -#define MCF_GPIO_PCLRR_UART (*(vuint8 *)(0xFC0A4045)) -#define MCF_GPIO_PCLRR_QSPI (*(vuint8 *)(0xFC0A4046)) -#define MCF_GPIO_PCLRR_TIMER (*(vuint8 *)(0xFC0A4047)) -#define MCF_GPIO_PCLRR_LCDDATAH (*(vuint8 *)(0xFC0A4049)) -#define MCF_GPIO_PCLRR_LCDDATAM (*(vuint8 *)(0xFC0A404A)) -#define MCF_GPIO_PCLRR_LCDDATAL (*(vuint8 *)(0xFC0A404B)) -#define MCF_GPIO_PCLRR_LCDCTLH (*(vuint8 *)(0xFC0A404C)) -#define MCF_GPIO_PCLRR_LCDCTLL (*(vuint8 *)(0xFC0A404D)) -#define MCF_GPIO_PAR_FEC (*(vuint8 *)(0xFC0A4050)) -#define MCF_GPIO_PAR_PWM (*(vuint8 *)(0xFC0A4051)) -#define MCF_GPIO_PAR_BUSCTL (*(vuint8 *)(0xFC0A4052)) -#define MCF_GPIO_PAR_FECI2C (*(vuint8 *)(0xFC0A4053)) -#define MCF_GPIO_PAR_BE (*(vuint8 *)(0xFC0A4054)) -#define MCF_GPIO_PAR_CS (*(vuint8 *)(0xFC0A4055)) -#define MCF_GPIO_PAR_SSI (*(vuint16*)(0xFC0A4056)) -#define MCF_GPIO_PAR_UART (*(vuint16*)(0xFC0A4058)) -#define MCF_GPIO_PAR_QSPI (*(vuint16*)(0xFC0A405A)) -#define MCF_GPIO_PAR_TIMER (*(vuint8 *)(0xFC0A405C)) -#define MCF_GPIO_PAR_LCDDATA (*(vuint8 *)(0xFC0A405D)) -#define MCF_GPIO_PAR_LCDCTL (*(vuint16*)(0xFC0A405E)) -#define MCF_GPIO_PAR_IRQ (*(vuint16*)(0xFC0A4060)) -#define MCF_GPIO_MSCR_FLEXBUS (*(vuint8 *)(0xFC0A4064)) -#define MCF_GPIO_MSCR_SDRAM (*(vuint8 *)(0xFC0A4065)) -#define MCF_GPIO_DSCR_I2C (*(vuint8 *)(0xFC0A4068)) -#define MCF_GPIO_DSCR_PWM (*(vuint8 *)(0xFC0A4069)) -#define MCF_GPIO_DSCR_FEC (*(vuint8 *)(0xFC0A406A)) -#define MCF_GPIO_DSCR_UART (*(vuint8 *)(0xFC0A406B)) -#define MCF_GPIO_DSCR_QSPI (*(vuint8 *)(0xFC0A406C)) -#define MCF_GPIO_DSCR_TIMER (*(vuint8 *)(0xFC0A406D)) -#define MCF_GPIO_DSCR_SSI (*(vuint8 *)(0xFC0A406E)) -#define MCF_GPIO_DSCR_LCD (*(vuint8 *)(0xFC0A406F)) -#define MCF_GPIO_DSCR_DEBUG (*(vuint8 *)(0xFC0A4070)) -#define MCF_GPIO_DSCR_CLKRST (*(vuint8 *)(0xFC0A4071)) -#define MCF_GPIO_DSCR_IRQ (*(vuint8 *)(0xFC0A4072)) - -/* Bit definitions and macros for MCF_GPIO_PODR_FECH */ -#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01) -#define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02) -#define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04) -#define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08) -#define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10) -#define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20) -#define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40) -#define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FECL */ -#define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01) -#define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02) -#define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04) -#define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08) -#define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10) -#define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20) -#define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40) -#define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_SSI */ -#define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01) -#define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02) -#define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04) -#define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08) -#define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */ -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_BE */ -#define MCF_GPIO_PODR_BE_PODR_BE0 (0x01) -#define MCF_GPIO_PODR_BE_PODR_BE1 (0x02) -#define MCF_GPIO_PODR_BE_PODR_BE2 (0x04) -#define MCF_GPIO_PODR_BE_PODR_BE3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_CS */ -#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02) -#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04) -#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08) -#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10) -#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PODR_PWM */ -#define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04) -#define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08) -#define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10) -#define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_UART */ -#define MCF_GPIO_PODR_UART_PODR_UART0 (0x01) -#define MCF_GPIO_PODR_UART_PODR_UART1 (0x02) -#define MCF_GPIO_PODR_UART_PODR_UART2 (0x04) -#define MCF_GPIO_PODR_UART_PODR_UART3 (0x08) -#define MCF_GPIO_PODR_UART_PODR_UART4 (0x10) -#define MCF_GPIO_PODR_UART_PODR_UART5 (0x20) -#define MCF_GPIO_PODR_UART_PODR_UART6 (0x40) -#define MCF_GPIO_PODR_UART_PODR_UART7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */ -#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */ -#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */ -#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01) -#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */ -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */ -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */ -#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01) - -/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */ -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */ -#define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */ -#define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */ -#define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01) -#define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02) -#define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04) -#define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08) -#define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */ -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_BE */ -#define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01) -#define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02) -#define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04) -#define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_CS */ -#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02) -#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04) -#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08) -#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10) -#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */ -#define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04) -#define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08) -#define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10) -#define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_UART */ -#define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01) -#define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02) -#define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04) -#define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08) -#define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10) -#define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20) -#define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40) -#define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */ -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */ -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */ -#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01) -#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */ -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */ -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */ -#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01) - -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */ -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */ -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */ -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */ -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01) -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02) -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04) -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08) -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */ -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */ -#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01) -#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02) -#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04) -#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */ -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */ -#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04) -#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08) -#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10) -#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */ -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */ -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */ -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */ -#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01) -#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */ -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */ -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */ -#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */ -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */ -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */ -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */ -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01) -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02) -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04) -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08) -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */ -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */ -#define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01) -#define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02) -#define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04) -#define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */ -#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */ -#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04) -#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08) -#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10) -#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */ -#define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */ -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */ -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */ -#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01) -#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */ -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */ -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */ -#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */ -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PAR_FEC */ -#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00) -#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04) -#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C) -#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00) -#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01) -#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_PWM */ -#define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10) -#define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */ -#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3) -#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20) -#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40) -#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80) -#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00) -#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80) -#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00) -#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40) -#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00) -#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18) - -/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */ -#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40) -#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80) -#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0) -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10) -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20) -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x01) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_BE */ -#define MCF_GPIO_PAR_BE_PAR_BE0 (0x01) -#define MCF_GPIO_PAR_BE_PAR_BE1 (0x02) -#define MCF_GPIO_PAR_BE_PAR_BE2 (0x04) -#define MCF_GPIO_PAR_BE_PAR_BE3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PAR_CS */ -#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02) -#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04) -#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08) -#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10) -#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20) -#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00) -#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01) -#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_SSI */ -#define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080) -#define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12) -#define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14) - -/* Bit definitions and macros for MCF_GPIO_PAR_UART */ -#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001) -#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002) -#define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004) -#define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008) -#define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800) -#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400) -#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00) -#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200) -#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100) -#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300) -#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080) -#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040) -#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0) -#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020) -#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010) -#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030) - -/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */ -#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12) -#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14) - -/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ -#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30) -#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08) -#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04) -#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C) -#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02) -#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01) -#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */ -#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6) - -/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */ -#define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001) -#define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002) -#define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004) -#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008) -#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010) -#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020) -#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040) -#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080) -#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100) - -/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */ -#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12) - -/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */ -#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0) -#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2) -#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4) - -/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */ -#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0) -#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2) -#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4) - -/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */ -#define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */ -#define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */ -#define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_UART */ -#define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0) -#define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2) - -/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */ -#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */ -#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */ -#define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */ -#define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */ -#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */ -#define MCF_GPIO_DSCR_CLKRST_MSCR_FBCLK(x) (((x)&0x03)<<0) -#define MCF_GPIO_DSCR_CLKRST_RSTOUT_DSE(x) (((x)&0x03)<<2) - -/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */ -#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0) - -/********************************************************************* -* -* Real-time Clock (RTC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RTC_HOURMIN (*(vuint32*)(0xFC0A8000)) -#define MCF_RTC_SECONDS (*(vuint32*)(0xFC0A8004)) -#define MCF_RTC_ALRM_HM (*(vuint32*)(0xFC0A8008)) -#define MCF_RTC_ALRM_SEC (*(vuint32*)(0xFC0A800C)) -#define MCF_RTC_CR (*(vuint32*)(0xFC0A8010)) -#define MCF_RTC_ISR (*(vuint32*)(0xFC0A8014)) -#define MCF_RTC_IER (*(vuint32*)(0xFC0A8018)) -#define MCF_RTC_STPWCH (*(vuint32*)(0xFC0A801C)) -#define MCF_RTC_DAYS (*(vuint32*)(0xFC0A8020)) -#define MCF_RTC_ALRM_DAY (*(vuint32*)(0xFC0A8024)) - -/* Bit definitions and macros for MCF_RTC_HOURMIN */ -#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F)<<0) -#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8) - -/* Bit definitions and macros for MCF_RTC_SECONDS */ -#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x0000003F)<<0) - -/* Bit definitions and macros for MCF_RTC_ALRM_HM */ -#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F)<<0) -#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8) - -/* Bit definitions and macros for MCF_RTC_ALRM_SEC */ -#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F)<<0) - -/* Bit definitions and macros for MCF_RTC_CR */ -#define MCF_RTC_CR_SWR (0x00000001) -#define MCF_RTC_CR_XTL(x) (((x)&0x00000003)<<5) -#define MCF_RTC_CR_EN (0x00000080) -#define MCF_RTC_CR_32768 (0x0) -#define MCF_RTC_CR_32000 (0x1) -#define MCF_RTC_CR_38400 (0x2) - -/* Bit definitions and macros for MCF_RTC_ISR */ -#define MCF_RTC_ISR_SW (0x00000001) -#define MCF_RTC_ISR_MIN (0x00000002) -#define MCF_RTC_ISR_ALM (0x00000004) -#define MCF_RTC_ISR_DAY (0x00000008) -#define MCF_RTC_ISR_1HZ (0x00000010) -#define MCF_RTC_ISR_HR (0x00000020) -#define MCF_RTC_ISR_2HZ (0x00000080) -#define MCF_RTC_ISR_SAM0 (0x00000100) -#define MCF_RTC_ISR_SAM1 (0x00000200) -#define MCF_RTC_ISR_SAM2 (0x00000400) -#define MCF_RTC_ISR_SAM3 (0x00000800) -#define MCF_RTC_ISR_SAM4 (0x00001000) -#define MCF_RTC_ISR_SAM5 (0x00002000) -#define MCF_RTC_ISR_SAM6 (0x00004000) -#define MCF_RTC_ISR_SAM7 (0x00008000) - -/* Bit definitions and macros for MCF_RTC_IER */ -#define MCF_RTC_IER_SW (0x00000001) -#define MCF_RTC_IER_MIN (0x00000002) -#define MCF_RTC_IER_ALM (0x00000004) -#define MCF_RTC_IER_DAY (0x00000008) -#define MCF_RTC_IER_1HZ (0x00000010) -#define MCF_RTC_IER_HR (0x00000020) -#define MCF_RTC_IER_2HZ (0x00000080) -#define MCF_RTC_IER_SAM0 (0x00000100) -#define MCF_RTC_IER_SAM1 (0x00000200) -#define MCF_RTC_IER_SAM2 (0x00000400) -#define MCF_RTC_IER_SAM3 (0x00000800) -#define MCF_RTC_IER_SAM4 (0x00001000) -#define MCF_RTC_IER_SAM5 (0x00002000) -#define MCF_RTC_IER_SAM6 (0x00004000) -#define MCF_RTC_IER_SAM7 (0x00008000) - -/* Bit definitions and macros for MCF_RTC_STPWCH */ -#define MCF_RTC_STPWCH_CNT(x) (((x)&0x0000003F)<<0) - -/* Bit definitions and macros for MCF_RTC_DAYS */ -#define MCF_RTC_DAYS_DAYS(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_RTC_ALRM_DAY */ -#define MCF_RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF)<<0) - -/********************************************************************* -* -* LCD Controller (LCDC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_LCDC_LSSAR (*(vuint32*)(0xFC0AC000)) -#define MCF_LCDC_LSR (*(vuint32*)(0xFC0AC004)) -#define MCF_LCDC_LVPWR (*(vuint32*)(0xFC0AC008)) -#define MCF_LCDC_LCPR (*(vuint32*)(0xFC0AC00C)) -#define MCF_LCDC_LCWHBR (*(vuint32*)(0xFC0AC010)) -#define MCF_LCDC_LCCMR (*(vuint32*)(0xFC0AC014)) -#define MCF_LCDC_LPCR (*(vuint32*)(0xFC0AC018)) -#define MCF_LCDC_LHCR (*(vuint32*)(0xFC0AC01C)) -#define MCF_LCDC_LVCR (*(vuint32*)(0xFC0AC020)) -#define MCF_LCDC_LPOR (*(vuint32*)(0xFC0AC024)) -#define MCF_LCDC_LSCR (*(vuint32*)(0xFC0AC028)) -#define MCF_LCDC_LPCCR (*(vuint32*)(0xFC0AC02C)) -#define MCF_LCDC_LDCR (*(vuint32*)(0xFC0AC030)) -#define MCF_LCDC_LRMCR (*(vuint32*)(0xFC0AC034)) -#define MCF_LCDC_LICR (*(vuint32*)(0xFC0AC038)) -#define MCF_LCDC_LIER (*(vuint32*)(0xFC0AC03C)) -#define MCF_LCDC_LISR (*(vuint32*)(0xFC0AC040)) -#define MCF_LCDC_LGWSAR (*(vuint32*)(0xFC0AC050)) -#define MCF_LCDC_LGWSR (*(vuint32*)(0xFC0AC054)) -#define MCF_LCDC_LGWVPWR (*(vuint32*)(0xFC0AC058)) -#define MCF_LCDC_LGWPOR (*(vuint32*)(0xFC0AC05C)) -#define MCF_LCDC_LGWPR (*(vuint32*)(0xFC0AC060)) -#define MCF_LCDC_LGWCR (*(vuint32*)(0xFC0AC064)) -#define MCF_LCDC_LGWDCR (*(vuint32*)(0xFC0AC068)) -#define MCF_LCDC_BPLUT_BASE (*(vuint32*)(0xFC0AC800)) -#define MCF_LCDC_GWLUT_BASE (*(vuint32*)(0xFC0ACC00)) - -/* Bit definitions and macros for MCF_LCDC_LSSAR */ -#define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_LCDC_LSR */ -#define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0) -#define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20) - -/* Bit definitions and macros for MCF_LCDC_LVPWR */ -#define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0) - -/* Bit definitions and macros for MCF_LCDC_LCPR */ -#define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0) -#define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16) -#define MCF_LCDC_LCPR_OP (0x10000000) -#define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30) -#define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000) -#define MCF_LCDC_LCPR_CC_OR (0x40000000) -#define MCF_LCDC_LCPR_CC_XOR (0x80000000) -#define MCF_LCDC_LCPR_CC_AND (0xC0000000) -#define MCF_LCDC_LCPR_OP_ON (0x10000000) -#define MCF_LCDC_LCPR_OP_OFF (0x00000000) - -/* Bit definitions and macros for MCF_LCDC_LCWHBR */ -#define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0) -#define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16) -#define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24) -#define MCF_LCDC_LCWHBR_BK_EN (0x80000000) -#define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000) -#define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000) - -/* Bit definitions and macros for MCF_LCDC_LCCMR */ -#define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0) -#define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6) -#define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12) - -/* Bit definitions and macros for MCF_LCDC_LPCR */ -#define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0) -#define MCF_LCDC_LPCR_SHARP (0x00000040) -#define MCF_LCDC_LPCR_SCLKSEL (0x00000080) -#define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8) -#define MCF_LCDC_LPCR_ACDSEL (0x00008000) -#define MCF_LCDC_LPCR_REV_VS (0x00010000) -#define MCF_LCDC_LPCR_SWAP_SEL (0x00020000) -#define MCF_LCDC_LPCR_ENDSEL (0x00040000) -#define MCF_LCDC_LPCR_SCLKIDLE (0x00080000) -#define MCF_LCDC_LPCR_OEPOL (0x00100000) -#define MCF_LCDC_LPCR_CLKPOL (0x00200000) -#define MCF_LCDC_LPCR_LPPOL (0x00400000) -#define MCF_LCDC_LPCR_FLM (0x00800000) -#define MCF_LCDC_LPCR_PIXPOL (0x01000000) -#define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25) -#define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28) -#define MCF_LCDC_LPCR_COLOR (0x40000000) -#define MCF_LCDC_LPCR_TFT (0x80000000) -#define MCF_LCDC_LPCR_MODE_MONOCHROME (0x00000000) -#define MCF_LCDC_LPCR_MODE_CSTN (0x40000000) -#define MCF_LCDC_LPCR_MODE_TFT (0xC0000000) -#define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000) -#define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000) -#define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000) -#define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000) -#define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000) -#define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000) -#define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000) -#define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000) -#define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000) -#define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000) -#define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000) - -/* Bit definitions and macros for MCF_LCDC_LHCR */ -#define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0) -#define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8) -#define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26) - -/* Bit definitions and macros for MCF_LCDC_LVCR */ -#define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0) -#define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8) -#define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26) - -/* Bit definitions and macros for MCF_LCDC_LPOR */ -#define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0) - -/* Bit definitions and macros for MCF_LCDC_LPCCR */ -#define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0) -#define MCF_LCDC_LPCCR_CC_EN (0x00000100) -#define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9) -#define MCF_LCDC_LPCCR_LDMSK (0x00008000) -#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16) -#define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000) -#define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000) -#define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000) - -/* Bit definitions and macros for MCF_LCDC_LDCR */ -#define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0) -#define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16) -#define MCF_LCDC_LDCR_BURST (0x80000000) - -/* Bit definitions and macros for MCF_LCDC_LRMCR */ -#define MCF_LCDC_LRMCR_SEL_REF (0x00000001) - -/* Bit definitions and macros for MCF_LCDC_LICR */ -#define MCF_LCDC_LICR_INTCON (0x00000001) -#define MCF_LCDC_LICR_INTSYN (0x00000004) -#define MCF_LCDC_LICR_GW_INT_CON (0x00000010) - -/* Bit definitions and macros for MCF_LCDC_LIER */ -#define MCF_LCDC_LIER_BOF_EN (0x00000001) -#define MCF_LCDC_LIER_EOF_EN (0x00000002) -#define MCF_LCDC_LIER_ERR_RES_EN (0x00000004) -#define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008) -#define MCF_LCDC_LIER_GW_BOF_EN (0x00000010) -#define MCF_LCDC_LIER_GW_EOF_EN (0x00000020) -#define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040) -#define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080) - -/* Bit definitions and macros for MCF_LCDC_LISR */ -#define MCF_LCDC_LISR_BOF (0x00000001) -#define MCF_LCDC_LISR_EOF (0x00000002) -#define MCF_LCDC_LISR_ERR_RES (0x00000004) -#define MCF_LCDC_LISR_UDR_ERR (0x00000008) -#define MCF_LCDC_LISR_GW_BOF (0x00000010) -#define MCF_LCDC_LISR_GW_EOF (0x00000020) -#define MCF_LCDC_LISR_GW_ERR_RES (0x00000040) -#define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080) - -/* Bit definitions and macros for MCF_LCDC_LGWSAR */ -#define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_LCDC_LGWSR */ -#define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0) -#define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20) - -/* Bit definitions and macros for MCF_LCDC_LGWVPWR */ -#define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0) - -/* Bit definitions and macros for MCF_LCDC_LGWPOR */ -#define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0) - -/* Bit definitions and macros for MCF_LCDC_LGWPR */ -#define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0) -#define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16) - -/* Bit definitions and macros for MCF_LCDC_LGWCR */ -#define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0) -#define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6) -#define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12) -#define MCF_LCDC_LGWCR_GW_RVS (0x00200000) -#define MCF_LCDC_LGWCR_GWE (0x00400000) -#define MCF_LCDC_LGWCR_GWCKE (0x00800000) -#define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_LCDC_LGWDCR */ -#define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0) -#define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16) -#define MCF_LCDC_LGWDCR_GWBT (0x80000000) - -/* Bit definitions and macros for MCF_LCDC_LSCR */ -#define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26) -#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16) -#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8) -#define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4) -#define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0) - -/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */ -#define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */ -#define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* -* -* USB Controller (USB) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_USB0_ID (*(vuint32*)(0xFC0B0000)) -#define MCF_USB0_HWGENERAL (*(vuint32*)(0xFC0B0004)) -#define MCF_USB0_HWHOST (*(vuint32*)(0xFC0B0008)) -#define MCF_USB0_HWDEVICE (*(vuint32*)(0xFC0B000C)) -#define MCF_USB0_HWTXBUF (*(vuint32*)(0xFC0B0010)) -#define MCF_USB0_HWRXBUF (*(vuint32*)(0xFC0B0014)) -#define MCF_USB0_CAPLENGTH (*(vuint8 *)(0xFC0B0100)) -#define MCF_USB0_HCIVERSION (*(vuint16*)(0xFC0B0102)) -#define MCF_USB0_HCSPARAMS (*(vuint32*)(0xFC0B0104)) -#define MCF_USB0_HCCPARAMS (*(vuint32*)(0xFC0B0108)) -#define MCF_USB0_DCIVERSION (*(vuint16*)(0xFC0B0120)) -#define MCF_USB0_DCCPARAMS (*(vuint32*)(0xFC0B0124)) -#define MCF_USB0_USBCMD (*(vuint32*)(0xFC0B0140)) -#define MCF_USB0_USBSTS (*(vuint32*)(0xFC0B0144)) -#define MCF_USB0_USBINTR (*(vuint32*)(0xFC0B0148)) -#define MCF_USB0_FRINDEX (*(vuint32*)(0xFC0B014C)) -#define MCF_USB0_PERIODICLISTBASE (*(vuint32*)(0xFC0B0154)) -#define MCF_USB0_DEVICEADDR (*(vuint32*)(0xFC0B0154)) -#define MCF_USB0_ASYNCLISTADDR (*(vuint32*)(0xFC0B0158)) -#define MCF_USB0_EPLISTADDR (*(vuint32*)(0xFC0B0158)) -#define MCF_USB0_ASYNCTTSTS (*(vuint32*)(0xFC0B015C)) -#define MCF_USB0_BURSTSIZE (*(vuint32*)(0xFC0B0160)) -#define MCF_USB0_TXFILLTUNING (*(vuint32*)(0xFC0B0164)) -#define MCF_USB0_TXTTFILLTUNING (*(vuint32*)(0xFC0B0168)) -#define MCF_USB_ULPI0_VIEWPORT (*(vuint32*)(0xFC0B0170)) -#define MCF_USB0_CONFIGFLAG (*(vuint32*)(0xFC0B0180)) -#define MCF_USB0_PORTSC (*(vuint32*)(0xFC0B0184)) -#define MCF_USB0_OTGSC (*(vuint32*)(0xFC0B01A4)) -#define MCF_USB0_USBMODE (*(vuint32*)(0xFC0B01A8)) -#define MCF_USB0_EPSETUPSR (*(vuint32*)(0xFC0B01AC)) -#define MCF_USB0_EPPRIME (*(vuint32*)(0xFC0B01B0)) -#define MCF_USB0_EPFLUSH (*(vuint32*)(0xFC0B01B4)) -#define MCF_USB0_EPSR (*(vuint32*)(0xFC0B01B8)) -#define MCF_USB0_EPCOMPLETE (*(vuint32*)(0xFC0B01BC)) -#define MCF_USB0_EPCR0 (*(vuint32*)(0xFC0B01C0)) -#define MCF_USB0_EPCR1 (*(vuint32*)(0xFC0B01C4)) -#define MCF_USB0_EPCR2 (*(vuint32*)(0xFC0B01C8)) -#define MCF_USB0_EPCR3 (*(vuint32*)(0xFC0B01CC)) -#define MCF_USB0_EPCR(x) (*(vuint32*)(0xFC0B01C4+((x-1)*0x004))) -#define MCF_USB1_ID (*(vuint32*)(0xFC0B4000)) -#define MCF_USB1_HWGENERAL (*(vuint32*)(0xFC0B4004)) -#define MCF_USB1_HWHOST (*(vuint32*)(0xFC0B4008)) -#define MCF_USB1_HWDEVICE (*(vuint32*)(0xFC0B400C)) -#define MCF_USB1_HWTXBUF (*(vuint32*)(0xFC0B4010)) -#define MCF_USB1_HWRXBUF (*(vuint32*)(0xFC0B4014)) -#define MCF_USB1_CAPLENGTH (*(vuint8 *)(0xFC0B4100)) -#define MCF_USB1_HCIVERSION (*(vuint16*)(0xFC0B4102)) -#define MCF_USB1_HCSPARAMS (*(vuint32*)(0xFC0B4104)) -#define MCF_USB1_HCCPARAMS (*(vuint32*)(0xFC0B4108)) -#define MCF_USB1_DCIVERSION (*(vuint16*)(0xFC0B4120)) -#define MCF_USB1_DCCPARAMS (*(vuint32*)(0xFC0B4124)) -#define MCF_USB1_USBCMD (*(vuint32*)(0xFC0B4140)) -#define MCF_USB1_USBSTS (*(vuint32*)(0xFC0B4144)) -#define MCF_USB1_USBINTR (*(vuint32*)(0xFC0B4148)) -#define MCF_USB1_FRINDEX (*(vuint32*)(0xFC0B414C)) -#define MCF_USB1_PERIODICLISTBASE (*(vuint32*)(0xFC0B4154)) -#define MCF_USB1_DEVICEADDR (*(vuint32*)(0xFC0B4154)) -#define MCF_USB1_ASYNCLISTADDR (*(vuint32*)(0xFC0B4158)) -#define MCF_USB1_EPLISTADDR (*(vuint32*)(0xFC0B4158)) -#define MCF_USB1_ASYNCTTSTS (*(vuint32*)(0xFC0B415C)) -#define MCF_USB1_BURSTSIZE (*(vuint32*)(0xFC0B4160)) -#define MCF_USB1_TXFILLTUNING (*(vuint32*)(0xFC0B4164)) -#define MCF_USB1_TXTTFILLTUNING (*(vuint32*)(0xFC0B4168)) -#define MCF_USB_ULPI1_VIEWPORT (*(vuint32*)(0xFC0B4170)) -#define MCF_USB1_CONFIGFLAG (*(vuint32*)(0xFC0B4180)) -#define MCF_USB1_PORTSC (*(vuint32*)(0xFC0B4184)) -#define MCF_USB1_OTGSC (*(vuint32*)(0xFC0B41A4)) -#define MCF_USB1_USBMODE (*(vuint32*)(0xFC0B41A8)) -#define MCF_USB1_EPSETUPSR (*(vuint32*)(0xFC0B41AC)) -#define MCF_USB1_EPPRIME (*(vuint32*)(0xFC0B41B0)) -#define MCF_USB1_EPFLUSH (*(vuint32*)(0xFC0B41B4)) -#define MCF_USB1_EPSR (*(vuint32*)(0xFC0B41B8)) -#define MCF_USB1_EPCOMPLETE (*(vuint32*)(0xFC0B41BC)) -#define MCF_USB1_EPCR0 (*(vuint32*)(0xFC0B41C0)) -#define MCF_USB1_EPCR1 (*(vuint32*)(0xFC0B41C4)) -#define MCF_USB1_EPCR2 (*(vuint32*)(0xFC0B41C8)) -#define MCF_USB1_EPCR3 (*(vuint32*)(0xFC0B41CC)) -#define MCF_USB1_EPCR(x) (*(vuint32*)(0xFC0B41C4+((x-1)*0x004))) -#define MCF_USB_ID(x) (*(vuint32*)(0xFC0B0000+((x)*0x4000))) -#define MCF_USB_HWGENERAL(x) (*(vuint32*)(0xFC0B0004+((x)*0x4000))) -#define MCF_USB_HWHOST(x) (*(vuint32*)(0xFC0B0008+((x)*0x4000))) -#define MCF_USB_HWDEVICE(x) (*(vuint32*)(0xFC0B000C+((x)*0x4000))) -#define MCF_USB_HWTXBUF(x) (*(vuint32*)(0xFC0B0010+((x)*0x4000))) -#define MCF_USB_HWRXBUF(x) (*(vuint32*)(0xFC0B0014+((x)*0x4000))) -#define MCF_USB_CAPLENGTH(x) (*(vuint8 *)(0xFC0B0100+((x)*0x4000))) -#define MCF_USB_HCIVERSION(x) (*(vuint16*)(0xFC0B0102+((x)*0x4000))) -#define MCF_USB_HCSPARAMS(x) (*(vuint32*)(0xFC0B0104+((x)*0x4000))) -#define MCF_USB_HCCPARAMS(x) (*(vuint32*)(0xFC0B0108+((x)*0x4000))) -#define MCF_USB_DCIVERSION(x) (*(vuint16*)(0xFC0B0120+((x)*0x4000))) -#define MCF_USB_DCCPARAMS(x) (*(vuint32*)(0xFC0B0124+((x)*0x4000))) -#define MCF_USB_USBCMD(x) (*(vuint32*)(0xFC0B0140+((x)*0x4000))) -#define MCF_USB_USBSTS(x) (*(vuint32*)(0xFC0B0144+((x)*0x4000))) -#define MCF_USB_USBINTR(x) (*(vuint32*)(0xFC0B0148+((x)*0x4000))) -#define MCF_USB_FRINDEX(x) (*(vuint32*)(0xFC0B014C+((x)*0x4000))) -#define MCF_USB_PERIODICLISTBASE(x) (*(vuint32*)(0xFC0B0154+((x)*0x4000))) -#define MCF_USB_DEVICEADDR(x) (*(vuint32*)(0xFC0B0154+((x)*0x4000))) -#define MCF_USB_ASYNCLISTADDR(x) (*(vuint32*)(0xFC0B0158+((x)*0x4000))) -#define MCF_USB_EPLISTADDR(x) (*(vuint32*)(0xFC0B0158+((x)*0x4000))) -#define MCF_USB_ASYNCTTSTS(x) (*(vuint32*)(0xFC0B015C+((x)*0x4000))) -#define MCF_USB_BURSTSIZE(x) (*(vuint32*)(0xFC0B0160+((x)*0x4000))) -#define MCF_USB_TXFILLTUNING(x) (*(vuint32*)(0xFC0B0164+((x)*0x4000))) -#define MCF_USB_TXTTFILLTUNING(x) (*(vuint32*)(0xFC0B0168+((x)*0x4000))) -#define MCF_USB_ULPI_VIEWPORT(x) (*(vuint32*)(0xFC0B0170+((x)*0x4000))) -#define MCF_USB_CONFIGFLAG(x) (*(vuint32*)(0xFC0B0180+((x)*0x4000))) -#define MCF_USB_PORTSC(x) (*(vuint32*)(0xFC0B0184+((x)*0x4000))) -#define MCF_USB_OTGSC(x) (*(vuint32*)(0xFC0B01A4+((x)*0x4000))) -#define MCF_USB_USBMODE(x) (*(vuint32*)(0xFC0B01A8+((x)*0x4000))) -#define MCF_USB_EPSETUPSR(x) (*(vuint32*)(0xFC0B01AC+((x)*0x4000))) -#define MCF_USB_EPPRIME(x) (*(vuint32*)(0xFC0B01B0+((x)*0x4000))) -#define MCF_USB_EPFLUSH(x) (*(vuint32*)(0xFC0B01B4+((x)*0x4000))) -#define MCF_USB_EPSR(x) (*(vuint32*)(0xFC0B01B8+((x)*0x4000))) -#define MCF_USB_EPCOMPLETE(x) (*(vuint32*)(0xFC0B01BC+((x)*0x4000))) -#define MCF_USB_EPCR0(x) (*(vuint32*)(0xFC0B01C0+((x)*0x4000))) -#define MCF_USB_EPCR1(x) (*(vuint32*)(0xFC0B01C4+((x)*0x4000))) -#define MCF_USB_EPCR2(x) (*(vuint32*)(0xFC0B01C8+((x)*0x4000))) -#define MCF_USB_EPCR3(x) (*(vuint32*)(0xFC0B01CC+((x)*0x4000))) - -/* Bit definitions and macros for MCF_USB_ID */ -#define MCF_USB_ID_RESERVED (0x0000C000) -#define MCF_USB_ID_ID(x) (((x)&0x0000003F)<<0|0x0000C000) -#define MCF_USB_ID_NID(x) (((x)&0x0000003F)<<8|0x0000C000) -#define MCF_USB_ID_REVISION(x) (((x)&0x000000FF)<<16|0x0000C000) - -/* Bit definitions and macros for MCF_USB_HWGENERAL */ -#define MCF_USB_HWGENERAL_RT (0x00000001) -#define MCF_USB_HWGENERAL_CLKC(x) (((x)&0x00000003)<<1) -#define MCF_USB_HWGENERAL_BWT (0x00000008) -#define MCF_USB_HWGENERAL_PHYW(x) (((x)&0x00000003)<<4) -#define MCF_USB_HWGENERAL_PHYM(x) (((x)&0x00000007)<<6) -#define MCF_USB_HWGENERAL_SM(x) (((x)&0x00000003)<<9) - -/* Bit definitions and macros for MCF_USB_HWHOST */ -#define MCF_USB_HWHOST_HC (0x00000001) -#define MCF_USB_HWHOST_NPORT(x) (((x)&0x00000007)<<1) -#define MCF_USB_HWHOST_TTASY(x) (((x)&0x000000FF)<<16) -#define MCF_USB_HWHOST_TTPER(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_USB_HWDEVICE */ -#define MCF_USB_HWDEVICE_DC (0x00000001) -#define MCF_USB_HWDEVICE_DEVEP(x) (((x)&0x0000001F)<<1) - -/* Bit definitions and macros for MCF_USB_HWTXBUF */ -#define MCF_USB_HWTXBUF_TXBURST(x) (((x)&0x000000FF)<<0) -#define MCF_USB_HWTXBUF_TXADD(x) (((x)&0x000000FF)<<8) -#define MCF_USB_HWTXBUF_TXCHANADD(x) (((x)&0x000000FF)<<16) -#define MCF_USB_HWTXBUF_TXLC (0x80000000) - -/* Bit definitions and macros for MCF_USB_HWRXBUF */ -#define MCF_USB_HWRXBUF_RXBURST(x) (((x)&0x000000FF)<<0) -#define MCF_USB_HWRXBUF_RXADD(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for MCF_USB_CAPLENGTH */ -#define MCF_USB_CAPLENGTH_CAPLENGTH(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_USB_HCIVERSION */ -#define MCF_USB_HCIVERSION_HCIVERSION(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_USB_HCSPARAMS */ -#define MCF_USB_HCSPARAMS_N_PORTS(x) (((x)&0x0000000F)<<0) -#define MCF_USB_HCSPARAMS_PPC (0x00000010) -#define MCF_USB_HCSPARAMS_N_PCC(x) (((x)&0x0000000F)<<8) -#define MCF_USB_HCSPARAMS_N_CC(x) (((x)&0x0000000F)<<12) -#define MCF_USB_HCSPARAMS_PI (0x00010000) -#define MCF_USB_HCSPARAMS_N_PTT(x) (((x)&0x0000000F)<<20) -#define MCF_USB_HCSPARAMS_N_TT(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_USB_HCCPARAMS */ -#define MCF_USB_HCCPARAMS_ADC (0x00000001) -#define MCF_USB_HCCPARAMS_PFL (0x00000002) -#define MCF_USB_HCCPARAMS_ASP (0x00000004) -#define MCF_USB_HCCPARAMS_IST(x) (((x)&0x0000000F)<<4) -#define MCF_USB_HCCPARAMS_EECP(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for MCF_USB_DCIVERSION */ -#define MCF_USB_DCIVERSION_DCIVERSION(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_USB_DCCPARAMS */ -#define MCF_USB_DCCPARAMS_DEN(x) (((x)&0x0000001F)<<0) -#define MCF_USB_DCCPARAMS_DC (0x00000080) -#define MCF_USB_DCCPARAMS_HC (0x00000100) - -/* Bit definitions and macros for MCF_USB_USBCMD */ -#define MCF_USB_USBCMD_RS (0x00000001) -#define MCF_USB_USBCMD_RST (0x00000002) -#define MCF_USB_USBCMD_FS0 (0x00000004) -#define MCF_USB_USBCMD_FS1 (0x00000008) -#define MCF_USB_USBCMD_PSE (0x00000010) -#define MCF_USB_USBCMD_ASE (0x00000020) -#define MCF_USB_USBCMD_IAA (0x00000040) -#define MCF_USB_USBCMD_LR (0x00000080) -#define MCF_USB_USBCMD_ASP(x) (((x)&0x00000003)<<8) -#define MCF_USB_USBCMD_ASPE (0x00000800) -#define MCF_USB_USBCMD_SUTW (0x00002000) -#define MCF_USB_USBCMD_ATDTW (0x00004000) -#define MCF_USB_USBCMD_FS2 (0x00008000) -#define MCF_USB_USBCMD_ITC(x) (((x)&0x000000FF)<<16) -#define MCF_USB_USBCMD_ITC_IMM (0x00000000) -#define MCF_USB_USBCMD_ITC_1 (0x00010000) -#define MCF_USB_USBCMD_ITC_2 (0x00020000) -#define MCF_USB_USBCMD_ITC_4 (0x00040000) -#define MCF_USB_USBCMD_ITC_8 (0x00080000) -#define MCF_USB_USBCMD_ITC_16 (0x00100000) -#define MCF_USB_USBCMD_ITC_32 (0x00200000) -#define MCF_USB_USBCMD_ITC_40 (0x00400000) -#define MCF_USB_USBCMD_FS_1024 (0x00000000) -#define MCF_USB_USBCMD_FS_512 (0x00000004) -#define MCF_USB_USBCMD_FS_256 (0x00000008) -#define MCF_USB_USBCMD_FS_128 (0x0000000C) -#define MCF_USB_USBCMD_FS_64 (0x00008000) -#define MCF_USB_USBCMD_FS_32 (0x00008004) -#define MCF_USB_USBCMD_FS_16 (0x00008008) -#define MCF_USB_USBCMD_FS_8 (0x0000800C) - -/* Bit definitions and macros for MCF_USB_USBSTS */ -#define MCF_USB_USBSTS_UI (0x00000001) -#define MCF_USB_USBSTS_UEI (0x00000002) -#define MCF_USB_USBSTS_PCI (0x00000004) -#define MCF_USB_USBSTS_FRI (0x00000008) -#define MCF_USB_USBSTS_SEI (0x00000010) -#define MCF_USB_USBSTS_AAI (0x00000020) -#define MCF_USB_USBSTS_URI (0x00000040) -#define MCF_USB_USBSTS_SRI (0x00000080) -#define MCF_USB_USBSTS_SLI (0x00000100) -#define MCF_USB_USBSTS_HCH (0x00001000) -#define MCF_USB_USBSTS_RCL (0x00002000) -#define MCF_USB_USBSTS_PS (0x00004000) -#define MCF_USB_USBSTS_AS (0x00008000) - -/* Bit definitions and macros for MCF_USB_USBINTR */ -#define MCF_USB_USBINTR_UE (0x00000001) -#define MCF_USB_USBINTR_UEE (0x00000002) -#define MCF_USB_USBINTR_PCE (0x00000004) -#define MCF_USB_USBINTR_FRE (0x00000008) -#define MCF_USB_USBINTR_SEE (0x00000010) -#define MCF_USB_USBINTR_AAE (0x00000020) -#define MCF_USB_USBINTR_URE (0x00000040) -#define MCF_USB_USBINTR_SRE (0x00000080) -#define MCF_USB_USBINTR_SLE (0x00000100) - -/* Bit definitions and macros for MCF_USB_FRINDEX */ -#define MCF_USB_FRINDEX_FRINDEX(x) (((x)&0x00003FFF)<<0) - -/* Bit definitions and macros for MCF_USB_PERIODICLISTBASE */ -#define MCF_USB_PERIODICLISTBASE_PERBASE(x) (((x)&0x000FFFFF)<<12) - -/* Bit definitions and macros for MCF_USB_DEVICEADDR */ -#define MCF_USB_DEVICEADDR_USBADR(x) (((x)&0x0000007F)<<25) - -/* Bit definitions and macros for MCF_USB_ASYNCLISTADDR */ -#define MCF_USB_ASYNCLISTADDR_ASYBASE(x) (((x)&0x07FFFFFF)<<5) - -/* Bit definitions and macros for MCF_USB_EPLISTADDR */ -#define MCF_USB_EPLISTADDR_EPBASE(x) (((x)&0x001FFFFF)<<11) - -/* Bit definitions and macros for MCF_USB_ASYNCTTSTS */ -#define MCF_USB_ASYNCTTSTS_TTAS (0x00000001) -#define MCF_USB_ASYNCTTSTS_TTAC (0x00000002) - -/* Bit definitions and macros for MCF_USB_BURSTSIZE */ -#define MCF_USB_BURSTSIZE_RXPBURST(x) (((x)&0x000000FF)<<0) -#define MCF_USB_BURSTSIZE_TXPBURST(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for MCF_USB_TXFILLTUNING */ -#define MCF_USB_TXFILLTUNING_TXSCHOH(x) (((x)&0x000000FF)<<0) -#define MCF_USB_TXFILLTUNING_TXSCHHEALTH(x) (((x)&0x0000001F)<<8) -#define MCF_USB_TXFILLTUNING_TXFIFOTHRES(x) (((x)&0x0000003F)<<16) - -/* Bit definitions and macros for MCF_USB_TXTTFILLTUNING */ -#define MCF_USB_TXTTFILLTUNING_TXTTSCHOH(x) (((x)&0x0000001F)<<0) -#define MCF_USB_TXTTFILLTUNING_TXTTSCHHEALTH(x) (((x)&0x0000001F)<<8) - -/* Bit definitions and macros for MCF_USB_CONFIGFLAG */ -#define MCF_USB_CONFIGFLAG_CONFIGFLAG(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_USB_PORTSC */ -#define MCF_USB_PORTSC_CCS (0x00000001) -#define MCF_USB_PORTSC_CSC (0x00000002) -#define MCF_USB_PORTSC_PE (0x00000004) -#define MCF_USB_PORTSC_PEC (0x00000008) -#define MCF_USB_PORTSC_OCA (0x00000010) -#define MCF_USB_PORTSC_OCC (0x00000020) -#define MCF_USB_PORTSC_FPR (0x00000040) -#define MCF_USB_PORTSC_SUSP (0x00000080) -#define MCF_USB_PORTSC_PR (0x00000100) -#define MCF_USB_PORTSC_LS(x) (((x)&0x00000003)<<10) -#define MCF_USB_PORTSC_PP (0x00001000) -#define MCF_USB_PORTSC_PO (0x00002000) -#define MCF_USB_PORTSC_PIC(x) (((x)&0x00000003)<<14) -#define MCF_USB_PORTSC_PTC(x) (((x)&0x0000000F)<<16) -#define MCF_USB_PORTSC_WLCN (0x00100000) -#define MCF_USB_PORTSC_WKDS (0x00200000) -#define MCF_USB_PORTSC_WKOC (0x00400000) -#define MCF_USB_PORTSC_PHCD (0x00800000) -#define MCF_USB_PORTSC_PFSC (0x01000000) -#define MCF_USB_PORTSC_PSPD(x) (((x)&0x00000003)<<26) -#define MCF_USB_PORTSC_PTS(x) (((x)&0x00000003)<<30) -#define MCF_USB_PORTSC_PTS_ULPI (0x80000000) -#define MCF_USB_PORTSC_PTS_FS_LS (0xC0000000) -#define MCF_USB_PORTSC_PSPD_FULL (0x00000000) -#define MCF_USB_PORTSC_PSPD_LOW (0x04000000) -#define MCF_USB_PORTSC_PSPD_HIGH (0x08000000) -#define MCF_USB_PORTSC_PTC_DISBALE (0x00000000) -#define MCF_USB_PORTSC_PTC_JSTATE (0x00010000) -#define MCF_USB_PORTSC_PTC_KSTATE (0x00020000) -#define MCF_USB_PORTSC_PTC_SEQ_NAK (0x00030000) -#define MCF_USB_PORTSC_PTC_PACKET (0x00040000) -#define MCF_USB_PORTSC_PTC_FORCE_ENABLE (0x00050000) -#define MCF_USB_PORTSC_PIC_OFF (0x00000000) -#define MCF_USB_PORTSC_PIC_AMBER (0x00004000) -#define MCF_USB_PORTSC_PIC_GREEN (0x00008000) -#define MCF_USB_PORTSC_LS_SE0 (0x00000000) -#define MCF_USB_PORTSC_LS_JSTATE (0x00000400) -#define MCF_USB_PORTSC_LS_KSTATE (0x00000800) - -/* Bit definitions and macros for MCF_USB_OTGSC */ -#define MCF_USB_OTGSC_VD (0x00000001) -#define MCF_USB_OTGSC_VC (0x00000002) -#define MCF_USB_OTGSC_OT (0x00000008) -#define MCF_USB_OTGSC_DP (0x00000010) -#define MCF_USB_OTGSC_ID (0x00000100) -#define MCF_USB_OTGSC_AVV (0x00000200) -#define MCF_USB_OTGSC_ASV (0x00000400) -#define MCF_USB_OTGSC_BSV (0x00000800) -#define MCF_USB_OTGSC_BSE (0x00001000) -#define MCF_USB_OTGSC_1MST (0x00002000) -#define MCF_USB_OTGSC_DPS (0x00004000) -#define MCF_USB_OTGSC_IDIS (0x00010000) -#define MCF_USB_OTGSC_AVVIS (0x00020000) -#define MCF_USB_OTGSC_ASVIS (0x00040000) -#define MCF_USB_OTGSC_BSVIS (0x00080000) -#define MCF_USB_OTGSC_BSEIS (0x00100000) -#define MCF_USB_OTGSC_1MSS (0x00200000) -#define MCF_USB_OTGSC_DPIS (0x00400000) -#define MCF_USB_OTGSC_IDIE (0x01000000) -#define MCF_USB_OTGSC_AVVIE (0x02000000) -#define MCF_USB_OTGSC_ASVIE (0x04000000) -#define MCF_USB_OTGSC_BSVIE (0x08000000) -#define MCF_USB_OTGSC_BSEIE (0x10000000) -#define MCF_USB_OTGSC_1MSE (0x20000000) -#define MCF_USB_OTGSC_DPIE (0x40000000) -#define MCF_USB_OTGSC_CLEAR (0x007F0000) -#define MCF_USB_OTGSC_ENABLE_ALL (0x7F000000) - -/* Bit definitions and macros for MCF_USB_USBMODE */ -#define MCF_USB_USBMODE_CM(x) (((x)&0x00000003)<<0) -#define MCF_USB_USBMODE_ES (0x00000004) -#define MCF_USB_USBMODE_SLOM (0x00000008) -#define MCF_USB_USBMODE_SDIS (0x00000010) -#define MCF_USB_USBMODE_CM_IDLE (0x00000000) -#define MCF_USB_USBMODE_CM_DEVICE (0x00000002) -#define MCF_USB_USBMODE_CM_HOST (0x00000003) - -/* Bit definitions and macros for MCF_USB_EPSETUPSR */ -#define MCF_USB_EPSETUPSR_EPSETUPSTAT(x) (((x)&0x0000003F)<<0) - -/* Bit definitions and macros for MCF_USB_EPPRIME */ -#define MCF_USB_EPPRIME_PERB(x) (((x)&0x0000003F)<<0) -#define MCF_USB_EPPRIME_PETB(x) (((x)&0x0000003F)<<16) -#define MCF_USB_EPPRIME_PETB0 (0x00010000) -#define MCF_USB_EPPRIME_PETB1 (0x00020000) -#define MCF_USB_EPPRIME_PETB2 (0x00040000) -#define MCF_USB_EPPRIME_PETB3 (0x00080000) -#define MCF_USB_EPPRIME_PETB4 (0x00100000) -#define MCF_USB_EPPRIME_PETB5 (0x00200000) -#define MCF_USB_EPPRIME_PERB0 (0x00000001) -#define MCF_USB_EPPRIME_PERB1 (0x00000002) -#define MCF_USB_EPPRIME_PERB2 (0x00000004) -#define MCF_USB_EPPRIME_PERB3 (0x00000008) -#define MCF_USB_EPPRIME_PERB4 (0x00000010) -#define MCF_USB_EPPRIME_PERB5 (0x00000020) - -/* Bit definitions and macros for MCF_USB_EPFLUSH */ -#define MCF_USB_EPFLUSH_FERB(x) (((x)&0x0000003F)<<0) -#define MCF_USB_EPFLUSH_FETB(x) (((x)&0x0000003F)<<16) -#define MCF_USB_EPFLUSH_FETB0 (0x00010000) -#define MCF_USB_EPFLUSH_FETB1 (0x00020000) -#define MCF_USB_EPFLUSH_FETB2 (0x00040000) -#define MCF_USB_EPFLUSH_FETB3 (0x00080000) -#define MCF_USB_EPFLUSH_FETB4 (0x00100000) -#define MCF_USB_EPFLUSH_FETB5 (0x00200000) -#define MCF_USB_EPFLUSH_FERB0 (0x00000001) -#define MCF_USB_EPFLUSH_FERB1 (0x00000002) -#define MCF_USB_EPFLUSH_FERB2 (0x00000004) -#define MCF_USB_EPFLUSH_FERB3 (0x00000008) -#define MCF_USB_EPFLUSH_FERB4 (0x00000010) -#define MCF_USB_EPFLUSH_FERB5 (0x00000020) - -/* Bit definitions and macros for MCF_USB_EPSR */ -#define MCF_USB_EPSR_ERBR(x) (((x)&0x0000003F)<<0) -#define MCF_USB_EPSR_ETBR(x) (((x)&0x0000003F)<<16) -#define MCF_USB_EPSR_ETBR0 (0x00010000) -#define MCF_USB_EPSR_ETBR1 (0x00020000) -#define MCF_USB_EPSR_ETBR2 (0x00040000) -#define MCF_USB_EPSR_ETBR3 (0x00080000) -#define MCF_USB_EPSR_ETBR4 (0x00100000) -#define MCF_USB_EPSR_ETBR5 (0x00200000) -#define MCF_USB_EPSR_ERBR0 (0x00000001) -#define MCF_USB_EPSR_ERBR1 (0x00000002) -#define MCF_USB_EPSR_ERBR2 (0x00000004) -#define MCF_USB_EPSR_ERBR3 (0x00000008) -#define MCF_USB_EPSR_ERBR4 (0x00000010) -#define MCF_USB_EPSR_ERBR5 (0x00000020) - -/* Bit definitions and macros for MCF_USB_EPCOMPLETE */ -#define MCF_USB_EPCOMPLETE_ERCE(x) (((x)&0x0000003F)<<0) -#define MCF_USB_EPCOMPLETE_ETCE(x) (((x)&0x0000003F)<<16) -#define MCF_USB_EPCOMPLETE_ETCE0 (0x00010000) -#define MCF_USB_EPCOMPLETE_ETCE1 (0x00020000) -#define MCF_USB_EPCOMPLETE_ETCE2 (0x00040000) -#define MCF_USB_EPCOMPLETE_ETCE3 (0x00080000) -#define MCF_USB_EPCOMPLETE_ETCE4 (0x00100000) -#define MCF_USB_EPCOMPLETE_ETCE5 (0x00200000) -#define MCF_USB_EPCOMPLETE_ERCE0 (0x00000001) -#define MCF_USB_EPCOMPLETE_ERCE1 (0x00000002) -#define MCF_USB_EPCOMPLETE_ERCE2 (0x00000004) -#define MCF_USB_EPCOMPLETE_ERCE3 (0x00000008) -#define MCF_USB_EPCOMPLETE_ERCE4 (0x00000010) -#define MCF_USB_EPCOMPLETE_ERCE5 (0x00000020) - -/* Bit definitions and macros for MCF_USB_EPCR0 */ -#define MCF_USB_EPCR0_RXS (0x00000001) -#define MCF_USB_EPCR0_RXT(x) (((x)&0x00000003)<<2) -#define MCF_USB_EPCR0_RXE (0x00000080) -#define MCF_USB_EPCR0_TXS (0x00010000) -#define MCF_USB_EPCR0_TXT(x) (((x)&0x00000003)<<18) -#define MCF_USB_EPCR0_TXE (0x00800000) - -/* Bit definitions and macros for MCF_USB_EPCR */ -#define MCF_USB_EPCR_RXS (0x00000001) -#define MCF_USB_EPCR_RXD (0x00000002) -#define MCF_USB_EPCR_RXT(x) (((x)&0x00000003)<<2) -#define MCF_USB_EPCR_RXI (0x00000020) -#define MCF_USB_EPCR_RXR (0x00000040) -#define MCF_USB_EPCR_RXE (0x00000080) -#define MCF_USB_EPCR_TXS (0x00010000) -#define MCF_USB_EPCR_TXD (0x00020000) -#define MCF_USB_EPCR_TXT(x) (((x)&0x00000003)<<18) -#define MCF_USB_EPCR_TXI (0x00200000) -#define MCF_USB_EPCR_TXR (0x00400000) -#define MCF_USB_EPCR_TXE (0x00800000) -#define MCF_USB_EPCR_TXT_CONTROL (0x00000000) -#define MCF_USB_EPCR_TXT_ISO (0x00040000) -#define MCF_USB_EPCR_TXT_BULK (0x00080000) -#define MCF_USB_EPCR_TXT_INT (0x000C0000) -#define MCF_USB_EPCR_RXT_CONTROL (0x00000000) -#define MCF_USB_EPCR_RXT_ISO (0x00000004) -#define MCF_USB_EPCR_RXT_BULK (0x00000008) -#define MCF_USB_EPCR_RXT_INT (0x0000000C) - -/********************************************************************* -* -* SDRAM Controller (SDRAMC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SDRAMC_SDMR (*(vuint32*)(0xFC0B8000)) -#define MCF_SDRAMC_SDCR (*(vuint32*)(0xFC0B8004)) -#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(0xFC0B8008)) -#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(0xFC0B800C)) -#define MCF_SDRAMC_SDDS (*(vuint32*)(0xFC0B8100)) -#define MCF_SDRAMC_SDCS0 (*(vuint32*)(0xFC0B8110)) -#define MCF_SDRAMC_SDCS1 (*(vuint32*)(0xFC0B8114)) -#define MCF_SDRAMC_SDCS2 (*(vuint32*)(0xFC0B8118)) -#define MCF_SDRAMC_SDCS3 (*(vuint32*)(0xFC0B811C)) -#define MCF_SDRAMC_SDCS(x) (*(vuint32*)(0xFC0B8110+((x)*0x004))) - -/* Bit definitions and macros for MCF_SDRAMC_SDMR */ -#define MCF_SDRAMC_SDMR_CMD (0x00010000) -#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) -#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) -#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) -#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) - -/* Bit definitions and macros for MCF_SDRAMC_SDCR */ -#define MCF_SDRAMC_SDCR_IPALL (0x00000002) -#define MCF_SDRAMC_SDCR_IREF (0x00000004) -#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) -#define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12) -#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) -#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) -#define MCF_SDRAMC_SDCR_REF (0x10000000) -#define MCF_SDRAMC_SDCR_DDR (0x20000000) -#define MCF_SDRAMC_SDCR_CKE (0x40000000) -#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) -#define MCF_SDRAMC_SDCR_PS_16 (0x00002000) -#define MCF_SDRAMC_SDCR_PS_32 (0x00000000) - -/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ -#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) -#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) -#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) -#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) -#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) -#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) -#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ -#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) -#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) -#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) -#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SDRAMC_SDDS */ -#define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0) -#define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) -#define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) -#define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) -#define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) - -/* Bit definitions and macros for MCF_SDRAMC_SDCS */ -#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0) -#define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) -#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) -#define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) -#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) -#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) -#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) -#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) -#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) -#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) -#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) -#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) -#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) -#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) -#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) -#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) -#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) - -/********************************************************************* -* -* Synchronous Serial Interface (SSI) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SSI_TX0 (*(vuint32*)(0xFC0BC000)) -#define MCF_SSI_TX1 (*(vuint32*)(0xFC0BC004)) -#define MCF_SSI_RX0 (*(vuint32*)(0xFC0BC008)) -#define MCF_SSI_RX1 (*(vuint32*)(0xFC0BC00C)) -#define MCF_SSI_CR (*(vuint32*)(0xFC0BC010)) -#define MCF_SSI_ISR (*(vuint32*)(0xFC0BC014)) -#define MCF_SSI_IER (*(vuint32*)(0xFC0BC018)) -#define MCF_SSI_TCR (*(vuint32*)(0xFC0BC01C)) -#define MCF_SSI_RCR (*(vuint32*)(0xFC0BC020)) -#define MCF_SSI_CCR (*(vuint32*)(0xFC0BC024)) -#define MCF_SSI_FCSR (*(vuint32*)(0xFC0BC02C)) -#define MCF_SSI_ACR (*(vuint32*)(0xFC0BC038)) -#define MCF_SSI_ACADD (*(vuint32*)(0xFC0BC03C)) -#define MCF_SSI_ACDAT (*(vuint32*)(0xFC0BC040)) -#define MCF_SSI_ATAG (*(vuint32*)(0xFC0BC044)) -#define MCF_SSI_TMASK (*(vuint32*)(0xFC0BC048)) -#define MCF_SSI_RMASK (*(vuint32*)(0xFC0BC04C)) - -/* Bit definitions and macros for MCF_SSI_TX */ -#define MCF_SSI_TX_SSI_TX(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_SSI_RX */ -#define MCF_SSI_RX_SSI_RX(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_SSI_CR */ -#define MCF_SSI_CR_SSI_EN (0x00000001) -#define MCF_SSI_CR_TE (0x00000002) -#define MCF_SSI_CR_RE (0x00000004) -#define MCF_SSI_CR_NET (0x00000008) -#define MCF_SSI_CR_SYN (0x00000010) -#define MCF_SSI_CR_I2S(x) (((x)&0x00000003)<<5) -#define MCF_SSI_CR_MCE (0x00000080) -#define MCF_SSI_CR_TCH (0x00000100) -#define MCF_SSI_CR_CIS (0x00000200) -#define MCF_SSI_CR_I2S_NORMAL (0x00000000) -#define MCF_SSI_CR_I2S_MASTER (0x00000020) -#define MCF_SSI_CR_I2S_SLAVE (0x00000040) - -/* Bit definitions and macros for MCF_SSI_ISR */ -#define MCF_SSI_ISR_TFE0 (0x00000001) -#define MCF_SSI_ISR_TFE1 (0x00000002) -#define MCF_SSI_ISR_RFF0 (0x00000004) -#define MCF_SSI_ISR_RFF1 (0x00000008) -#define MCF_SSI_ISR_RLS (0x00000010) -#define MCF_SSI_ISR_TLS (0x00000020) -#define MCF_SSI_ISR_RFS (0x00000040) -#define MCF_SSI_ISR_TFS (0x00000080) -#define MCF_SSI_ISR_TUE0 (0x00000100) -#define MCF_SSI_ISR_TUE1 (0x00000200) -#define MCF_SSI_ISR_ROE0 (0x00000400) -#define MCF_SSI_ISR_ROE1 (0x00000800) -#define MCF_SSI_ISR_TDE0 (0x00001000) -#define MCF_SSI_ISR_TDE1 (0x00002000) -#define MCF_SSI_ISR_RDR0 (0x00004000) -#define MCF_SSI_ISR_RDR1 (0x00008000) -#define MCF_SSI_ISR_RXT (0x00010000) -#define MCF_SSI_ISR_CMDDU (0x00020000) -#define MCF_SSI_ISR_CMDAU (0x00040000) - -/* Bit definitions and macros for MCF_SSI_IER */ -#define MCF_SSI_IER_TFE0 (0x00000001) -#define MCF_SSI_IER_TFE1 (0x00000002) -#define MCF_SSI_IER_RFF0 (0x00000004) -#define MCF_SSI_IER_RFF1 (0x00000008) -#define MCF_SSI_IER_RLS (0x00000010) -#define MCF_SSI_IER_TLS (0x00000020) -#define MCF_SSI_IER_RFS (0x00000040) -#define MCF_SSI_IER_TFS (0x00000080) -#define MCF_SSI_IER_TUE0 (0x00000100) -#define MCF_SSI_IER_TUE1 (0x00000200) -#define MCF_SSI_IER_ROE0 (0x00000400) -#define MCF_SSI_IER_ROE1 (0x00000800) -#define MCF_SSI_IER_TDE0 (0x00001000) -#define MCF_SSI_IER_TDE1 (0x00002000) -#define MCF_SSI_IER_RDR0 (0x00004000) -#define MCF_SSI_IER_RDR1 (0x00008000) -#define MCF_SSI_IER_RXT (0x00010000) -#define MCF_SSI_IER_CMDU (0x00020000) -#define MCF_SSI_IER_CMDAU (0x00040000) -#define MCF_SSI_IER_TIE (0x00080000) -#define MCF_SSI_IER_TDMAE (0x00100000) -#define MCF_SSI_IER_RIE (0x00200000) -#define MCF_SSI_IER_RDMAE (0x00400000) - -/* Bit definitions and macros for MCF_SSI_TCR */ -#define MCF_SSI_TCR_TEFS (0x00000001) -#define MCF_SSI_TCR_TFSL (0x00000002) -#define MCF_SSI_TCR_TFSI (0x00000004) -#define MCF_SSI_TCR_TSCKP (0x00000008) -#define MCF_SSI_TCR_TSHFD (0x00000010) -#define MCF_SSI_TCR_TXDIR (0x00000020) -#define MCF_SSI_TCR_TFDIR (0x00000040) -#define MCF_SSI_TCR_TFEN0 (0x00000080) -#define MCF_SSI_TCR_TFEN1 (0x00000100) -#define MCF_SSI_TCR_TXBIT0 (0x00000200) - -/* Bit definitions and macros for MCF_SSI_RCR */ -#define MCF_SSI_RCR_REFS (0x00000001) -#define MCF_SSI_RCR_RFSL (0x00000002) -#define MCF_SSI_RCR_RFSI (0x00000004) -#define MCF_SSI_RCR_RSCKP (0x00000008) -#define MCF_SSI_RCR_RSHFD (0x00000010) -#define MCF_SSI_RCR_RFEN0 (0x00000080) -#define MCF_SSI_RCR_RFEN1 (0x00000100) -#define MCF_SSI_RCR_RXBIT0 (0x00000200) -#define MCF_SSI_RCR_RXEXT (0x00000400) - -/* Bit definitions and macros for MCF_SSI_CCR */ -#define MCF_SSI_CCR_PM(x) (((x)&0x000000FF)<<0) -#define MCF_SSI_CCR_DC(x) (((x)&0x0000001F)<<8) -#define MCF_SSI_CCR_WL(x) (((x)&0x0000000F)<<13) -#define MCF_SSI_CCR_PSR (0x00020000) -#define MCF_SSI_CCR_DIV2 (0x00040000) - -/* Bit definitions and macros for MCF_SSI_FCSR */ -#define MCF_SSI_FCSR_TFWM0(x) (((x)&0x0000000F)<<0) -#define MCF_SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) -#define MCF_SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) -#define MCF_SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) -#define MCF_SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) -#define MCF_SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) -#define MCF_SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) -#define MCF_SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SSI_ACR */ -#define MCF_SSI_ACR_AC97EN (0x00000001) -#define MCF_SSI_ACR_FV (0x00000002) -#define MCF_SSI_ACR_TIF (0x00000004) -#define MCF_SSI_ACR_RD (0x00000008) -#define MCF_SSI_ACR_WR (0x00000010) -#define MCF_SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) - -/* Bit definitions and macros for MCF_SSI_ACADD */ -#define MCF_SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF)<<0) - -/* Bit definitions and macros for MCF_SSI_ACDAT */ -#define MCF_SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF)<<0) - -/* Bit definitions and macros for MCF_SSI_ATAG */ -#define MCF_SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_SSI_TMASK */ -#define MCF_SSI_TMASK_SSI_TMASK(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_SSI_RMASK */ -#define MCF_SSI_RMASK_SSI_RMASK(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* -* -* Phase Locked Loop (PLL) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PLL_PODR (*(vuint8 *)(0xFC0C0000)) -#define MCF_PLL_PLLCR (*(vuint8 *)(0xFC0C0004)) -#define MCF_PLL_PMDR (*(vuint8 *)(0xFC0C0008)) -#define MCF_PLL_PFDR (*(vuint8 *)(0xFC0C000C)) - -/* Bit definitions and macros for MCF_PLL_PODR */ -#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0) -#define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) - -/* Bit definitions and macros for MCF_PLL_PLLCR */ -#define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0) -#define MCF_PLL_PLLCR_DITHEN (0x80) - -/* Bit definitions and macros for MCF_PLL_PMDR */ -#define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PLL_PFDR */ -#define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0) - -/********************************************************************/ - -#endif /* __MCF532X_H__ */ diff --git a/c/src/lib/libcpu/m68k/mcf548x/include/mcf548x.h b/c/src/lib/libcpu/m68k/mcf548x/include/mcf548x.h deleted file mode 100644 index 7a9dc73698..0000000000 --- a/c/src/lib/libcpu/m68k/mcf548x/include/mcf548x.h +++ /dev/null @@ -1,4056 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS generic mcf548x BSP | -+-----------------------------------------------------------------+ -| File: mcf548x.h | -+-----------------------------------------------------------------+ -| The file contains all register an bit definitions of the | -| generic MCF548x BSP. | -+-----------------------------------------------------------------+ -| Copyright (c) 2007 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| | -| Parts of the code has been derived from the "dBUG source code" | -| package Freescale is providing for M548X EVBs. The usage of | -| the modified or unmodified code and it's integration into the | -| generic mcf548x BSP has been done according to the Freescale | -| license terms. | -| | -| The Freescale license terms can be reviewed in the file | -| | -| Freescale_license.txt | -| | -+-----------------------------------------------------------------+ -| | -| The generic mcf548x BSP has been developed on the basic | -| structures and modules of the av5282 BSP. | -| | -+-----------------------------------------------------------------+ -| | -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| | -| date history ID | -| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | -| 12.11.07 1.0 ras | -| | -\*===============================================================*/ - -#ifndef __MCF548X_H__ -#define __MCF548X_H__ - -#include <stdint.h> - -/*********************************************************************/ -extern char __MBAR[]; - -/********************************************************************* -* -* Cache Control Register (CACR) -* -*********************************************************************/ - -/* Bit definitions and macros for MCF548X_CACR */ -#define MCF548X_CACR_DEC (0x80000000) -#define MCF548X_CACR_DW (0x40000000) -#define MCF548X_CACR_DESB (0x20000000) -#define MCF548X_CACR_DDPI (0x10000000) -#define MCF548X_CACR_DHLCK (0x08000000) -#define MCF548X_CACR_DDCM(x) (((x)<<25)&0x06000000) -#define MCF548X_CACR_DCINVA (0x01000000) -#define MCF548X_CACR_DDSP (0x00800000) -#define MCF548X_CACR_BEC (0x00080000) -#define MCF548X_CACR_BCINVA (0x00040000) -#define MCF548X_CACR_IEC (0x00008000) -#define MCF548X_CACR_DNFB (0x00002000) -#define MCF548X_CACR_IDPI (0x00001000) -#define MCF548X_CACR_IHLCK (0x00000800) -#define MCF548X_CACR_IDCM (0x00000400) -#define MCF548X_CACR_ICINVA (0x00000100) -#define MCF548X_CACR_IDSP (0x00000080) -#define MCF548X_CACR_EUSP (0x00000020) -#define MCF548X_CACR_DF (0x00000010) - -/* Bit definitions and macros for MCF548X_CACR_DDCM (data cache mode) */ -#define DCACHE_ON_WRIGHTTHROUGH 0 -#define DCACHE_ON_COPYBACK 1 -#define DCACHE_OFF_PRECISE 2 -#define DCACHE_OFF_IMPRECISE 3 - -/********************************************************************* -* -* Access Control Registers (ACR0-3) -* -*********************************************************************/ - -/* Bit definitions and macros for MCF548X_ACRn */ -#define MCF548X_ACR_BA(x) ((x)&0xFF000000) -#define MCF548X_ACR_ADMSK_AMM(x) (((x)>=0x1000000) ? (((x)&0xFF000000)>>8) : (((x)&0x00FF0000)|0x00000400)) -#define MCF548X_ACR_E (0x00008000) -#define MCF548X_ACR_S(x) (((x)<<13)&0x00006000) -#define MCF548X_ACR_CM(x) (((x)<<5)&0x00000060) -#define MCF548X_ACR_SP (0x00000008) -#define MCF548X_ACR_W (0x00000004) - -/* Bit definitions and macros for MCF548X_ACR_S (supervisor/user access) */ -#define S_ACCESS_USER 0 -#define S_ACCESS_SUPV 1 -#define S_ACCESS_BOTH 2 - -/* Bit definitions and macros for MCF548X_ACR_CM (cache mode) */ -#define CM_ON_WRIGHTTHROUGH 0 -#define CM_ON_COPYBACK 1 -#define CM_OFF_PRECISE 2 -#define CM_OFF_IMPRECISE 3 - -/********************************************************************* -* -* System PLL Control Register (SPCR) -* -*********************************************************************/ - -/* Register read/write macro */ -#define MCF548X_PLL_SPCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000300))) - -/* Bit definitions and macros for MCF548X_PLL_SPCR (supervisor/user access) */ -#define MCF548X_PLL_SPCR_PLLK 0x80000000 -#define MCF548X_PLL_SPCR_COREN 0x00004000 -#define MCF548X_PLL_SPCR_CRYENB 0x00002000 -#define MCF548X_PLL_SPCR_CRYENA 0x00001000 -#define MCF548X_PLL_SPCR_CAN1EN 0x00000800 -#define MCF548X_PLL_SPCR_PSCEN 0x00000200 -#define MCF548X_PLL_SPCR_USBEN 0x00000080 -#define MCF548X_PLL_SPCR_FEC1EN 0x00000040 -#define MCF548X_PLL_SPCR_FEC0EN 0x00000020 -#define MCF548X_PLL_SPCR_DMAEN 0x00000010 -#define MCF548X_PLL_SPCR_CAN0EN 0x00000008 -#define MCF548X_PLL_SPCR_FBEN 0x00000004 -#define MCF548X_PLL_SPCR_PCIEN 0x00000002 -#define MCF548X_PLL_SPCR_MEMEN 0x00000001 - -/********************************************************************* -* -* XLB Arbiter Control (XLB) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_XLB_CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000240))) -#define MCF548X_XLB_ADRTO (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000258))) -#define MCF548X_XLB_DATTO (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00025C))) -#define MCF548X_XLB_BUSTO (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000260))) - -/********************************************************************* -* -* Fast Ethernet Controller (FEC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_FEC_EIR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009004))) -#define MCF548X_FEC_EIMR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009008))) -#define MCF548X_FEC_ECR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009024))) -#define MCF548X_FEC_MMFR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009040))) -#define MCF548X_FEC_MSCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009044))) -#define MCF548X_FEC_MIBC0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009064))) -#define MCF548X_FEC_RCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009084))) -#define MCF548X_FEC_R_HASH0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009088))) -#define MCF548X_FEC_TCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090C4))) -#define MCF548X_FEC_PALR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090E4))) -#define MCF548X_FEC_PAUR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090E8))) -#define MCF548X_FEC_OPD0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090EC))) -#define MCF548X_FEC_IAUR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009118))) -#define MCF548X_FEC_IALR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00911C))) -#define MCF548X_FEC_GAUR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009120))) -#define MCF548X_FEC_GALR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009124))) -#define MCF548X_FEC_FECTFWR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009144))) -#define MCF548X_FEC_FECRFDR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009184))) -#define MCF548X_FEC_FECRFSR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009188))) -#define MCF548X_FEC_FECRFCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00918C))) -#define MCF548X_FEC_FECRLRFP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009190))) -#define MCF548X_FEC_FECRLWFP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009194))) -#define MCF548X_FEC_FECRFAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009198))) -#define MCF548X_FEC_FECRFRP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00919C))) -#define MCF548X_FEC_FECRFWP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A0))) -#define MCF548X_FEC_FECTFDR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A4))) -#define MCF548X_FEC_FECTFSR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A8))) -#define MCF548X_FEC_FECTFCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091AC))) -#define MCF548X_FEC_FECTLRFP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B0))) -#define MCF548X_FEC_FECTLWFP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B4))) -#define MCF548X_FEC_FECTFAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B8))) -#define MCF548X_FEC_FECTFRP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091BC))) -#define MCF548X_FEC_FECTFWP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C0))) -#define MCF548X_FEC_FRST0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C4))) -#define MCF548X_FEC_CTCWR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C8))) -#define MCF548X_FEC_RMON_T_DROP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009200))) -#define MCF548X_FEC_RMON_T_PACKETS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009204))) -#define MCF548X_FEC_RMON_T_BC_PKT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009208))) -#define MCF548X_FEC_RMON_T_MC_PKT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00920C))) -#define MCF548X_FEC_RMON_T_CRC_ALIGN0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009210))) -#define MCF548X_FEC_RMON_T_UNDERSIZE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009214))) -#define MCF548X_FEC_RMON_T_OVERSIZE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009218))) -#define MCF548X_FEC_RMON_T_FRAG0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00921C))) -#define MCF548X_FEC_RMON_T_JAB0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009220))) -#define MCF548X_FEC_RMON_T_COL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009224))) -#define MCF548X_FEC_RMON_T_P640 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009228))) -#define MCF548X_FEC_RMON_T_P65TO1270 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00922C))) -#define MCF548X_FEC_RMON_T_P128TO2550 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009230))) -#define MCF548X_FEC_RMON_T_P256TO5110 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009234))) -#define MCF548X_FEC_RMON_T_P512TO10230 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009238))) -#define MCF548X_FEC_RMON_T_P1024TO20470 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00923C))) -#define MCF548X_FEC_RMON_T_P_GTE20480 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009240))) -#define MCF548X_FEC_RMON_T_OCTETS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009244))) -#define MCF548X_FEC_IEEE_T_DROP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009248))) -#define MCF548X_FEC_IEEE_T_FRAME_OK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00924C))) -#define MCF548X_FEC_IEEE_T_1COL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009250))) -#define MCF548X_FEC_IEEE_T_MCOL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009254))) -#define MCF548X_FEC_IEEE_T_DEF0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009258))) -#define MCF548X_FEC_IEEE_T_LCOL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00925C))) -#define MCF548X_FEC_IEEE_T_EXCOL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009260))) -#define MCF548X_FEC_IEEE_T_MACERR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009264))) -#define MCF548X_FEC_IEEE_T_CSERR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009268))) -#define MCF548X_FEC_IEEE_T_SQE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00926C))) -#define MCF548X_FEC_IEEE_T_FDXFC0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009270))) -#define MCF548X_FEC_IEEE_T_OCTETS_OK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009274))) -#define MCF548X_FEC_RMON_R_PACKETS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009284))) -#define MCF548X_FEC_RMON_R_BC_PKT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009288))) -#define MCF548X_FEC_RMON_R_MC_PKT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00928C))) -#define MCF548X_FEC_RMON_R_CRC_ALIGN0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009290))) -#define MCF548X_FEC_RMON_R_UNDERSIZE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009294))) -#define MCF548X_FEC_RMON_R_OVERSIZE0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009298))) -#define MCF548X_FEC_RMON_R_FRAG0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00929C))) -#define MCF548X_FEC_RMON_R_JAB0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A0))) -#define MCF548X_FEC_RMON_R_RESVD_00 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A4))) -#define MCF548X_FEC_RMON_R_P640 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A8))) -#define MCF548X_FEC_RMON_R_P65TO1270 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092AC))) -#define MCF548X_FEC_RMON_R_P128TO2550 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B0))) -#define MCF548X_FEC_RMON_R_P256TO5110 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B4))) -#define MCF548X_FEC_RMON_R_512TO10230 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B8))) -#define MCF548X_FEC_RMON_R_1024TO20470 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092BC))) -#define MCF548X_FEC_RMON_R_P_GTE20480 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C0))) -#define MCF548X_FEC_RMON_R_OCTETS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C4))) -#define MCF548X_FEC_IEEE_R_DROP0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C8))) -#define MCF548X_FEC_IEEE_R_FRAME_OK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092CC))) -#define MCF548X_FEC_IEEE_R_CRC0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D0))) -#define MCF548X_FEC_IEEE_R_ALIGN0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D4))) -#define MCF548X_FEC_IEEE_R_MACERR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D8))) -#define MCF548X_FEC_IEEE_R_FDXFC0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092DC))) -#define MCF548X_FEC_IEEE_R_OCTETS_OK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092E0))) -#define MCF548X_FEC_EIR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009804))) -#define MCF548X_FEC_EIMR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009808))) -#define MCF548X_FEC_ECR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009824))) -#define MCF548X_FEC_MMFR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009840))) -#define MCF548X_FEC_MSCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009844))) -#define MCF548X_FEC_MIBC1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009864))) -#define MCF548X_FEC_RCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009884))) -#define MCF548X_FEC_R_HASH1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009888))) -#define MCF548X_FEC_TCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0098C4))) -#define MCF548X_FEC_PALR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0098E4))) -#define MCF548X_FEC_PAUR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0098E8))) -#define MCF548X_FEC_OPD1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0098EC))) -#define MCF548X_FEC_IAUR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009918))) -#define MCF548X_FEC_IALR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00991C))) -#define MCF548X_FEC_GAUR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009920))) -#define MCF548X_FEC_GALR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009924))) -#define MCF548X_FEC_FECTFWR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009944))) -#define MCF548X_FEC_FECRFDR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009984))) -#define MCF548X_FEC_FECRFSR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009988))) -#define MCF548X_FEC_FECRFCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00998C))) -#define MCF548X_FEC_FECRLRFP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009990))) -#define MCF548X_FEC_FECRLWFP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009994))) -#define MCF548X_FEC_FECRFAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009998))) -#define MCF548X_FEC_FECRFRP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00999C))) -#define MCF548X_FEC_FECRFWP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099A0))) -#define MCF548X_FEC_FECTFDR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099A4))) -#define MCF548X_FEC_FECTFSR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099A8))) -#define MCF548X_FEC_FECTFCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099AC))) -#define MCF548X_FEC_FECTLRFP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099B0))) -#define MCF548X_FEC_FECTLWFP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099B4))) -#define MCF548X_FEC_FECTFAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099B8))) -#define MCF548X_FEC_FECTFRP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099BC))) -#define MCF548X_FEC_FECTFWP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099C0))) -#define MCF548X_FEC_FRST1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099C4))) -#define MCF548X_FEC_CTCWR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0099C8))) -#define MCF548X_FEC_RMON_T_DROP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A00))) -#define MCF548X_FEC_RMON_T_PACKETS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A04))) -#define MCF548X_FEC_RMON_T_BC_PKT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A08))) -#define MCF548X_FEC_RMON_T_MC_PKT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A0C))) -#define MCF548X_FEC_RMON_T_CRC_ALIGN1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A10))) -#define MCF548X_FEC_RMON_T_UNDERSIZE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A14))) -#define MCF548X_FEC_RMON_T_OVERSIZE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A18))) -#define MCF548X_FEC_RMON_T_FRAG1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A1C))) -#define MCF548X_FEC_RMON_T_JAB1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A20))) -#define MCF548X_FEC_RMON_T_COL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A24))) -#define MCF548X_FEC_RMON_T_P641 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A28))) -#define MCF548X_FEC_RMON_T_P65TO1271 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A2C))) -#define MCF548X_FEC_RMON_T_P128TO2551 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A30))) -#define MCF548X_FEC_RMON_T_P256TO5111 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A34))) -#define MCF548X_FEC_RMON_T_P512TO10231 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A38))) -#define MCF548X_FEC_RMON_T_P1024TO20471 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A3C))) -#define MCF548X_FEC_RMON_T_P_GTE20481 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A40))) -#define MCF548X_FEC_RMON_T_OCTETS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A44))) -#define MCF548X_FEC_IEEE_T_DROP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A48))) -#define MCF548X_FEC_IEEE_T_FRAME_OK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A4C))) -#define MCF548X_FEC_IEEE_T_1COL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A50))) -#define MCF548X_FEC_IEEE_T_MCOL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A54))) -#define MCF548X_FEC_IEEE_T_DEF1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A58))) -#define MCF548X_FEC_IEEE_T_LCOL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A5C))) -#define MCF548X_FEC_IEEE_T_EXCOL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A60))) -#define MCF548X_FEC_IEEE_T_MACERR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A64))) -#define MCF548X_FEC_IEEE_T_CSERR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A68))) -#define MCF548X_FEC_IEEE_T_SQE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A6C))) -#define MCF548X_FEC_IEEE_T_FDXFC1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A70))) -#define MCF548X_FEC_IEEE_T_OCTETS_OK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A74))) -#define MCF548X_FEC_RMON_R_PACKETS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A84))) -#define MCF548X_FEC_RMON_R_BC_PKT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A88))) -#define MCF548X_FEC_RMON_R_MC_PKT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A8C))) -#define MCF548X_FEC_RMON_R_CRC_ALIGN1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A90))) -#define MCF548X_FEC_RMON_R_UNDERSIZE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A94))) -#define MCF548X_FEC_RMON_R_OVERSIZE1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A98))) -#define MCF548X_FEC_RMON_R_FRAG1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009A9C))) -#define MCF548X_FEC_RMON_R_JAB1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AA0))) -#define MCF548X_FEC_RMON_R_RESVD_01 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AA4))) -#define MCF548X_FEC_RMON_R_P641 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AA8))) -#define MCF548X_FEC_RMON_R_P65TO1271 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AAC))) -#define MCF548X_FEC_RMON_R_P128TO2551 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AB0))) -#define MCF548X_FEC_RMON_R_P256TO5111 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AB4))) -#define MCF548X_FEC_RMON_R_512TO10231 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AB8))) -#define MCF548X_FEC_RMON_R_1024TO20471 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009ABC))) -#define MCF548X_FEC_RMON_R_P_GTE20481 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AC0))) -#define MCF548X_FEC_RMON_R_OCTETS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AC4))) -#define MCF548X_FEC_IEEE_R_DROP1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AC8))) -#define MCF548X_FEC_IEEE_R_FRAME_OK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009ACC))) -#define MCF548X_FEC_IEEE_R_CRC1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AD0))) -#define MCF548X_FEC_IEEE_R_ALIGN1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AD4))) -#define MCF548X_FEC_IEEE_R_MACERR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AD8))) -#define MCF548X_FEC_IEEE_R_FDXFC1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009ADC))) -#define MCF548X_FEC_IEEE_R_OCTETS_OK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009AE0))) -#define MCF548X_FEC_EIR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009004U+((x)*0x800)))) -#define MCF548X_FEC_EIMR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009008U+((x)*0x800)))) -#define MCF548X_FEC_ECR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009024U+((x)*0x800)))) -#define MCF548X_FEC_MMFR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009040U+((x)*0x800)))) -#define MCF548X_FEC_MSCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009044U+((x)*0x800)))) -#define MCF548X_FEC_MIBC(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009064U+((x)*0x800)))) -#define MCF548X_FEC_RCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009084U+((x)*0x800)))) -#define MCF548X_FEC_R_HASH(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009088U+((x)*0x800)))) -#define MCF548X_FEC_TCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090C4U+((x)*0x800)))) -#define MCF548X_FEC_PALR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090E4U+((x)*0x800)))) -#define MCF548X_FEC_PAUR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090E8U+((x)*0x800)))) -#define MCF548X_FEC_OPD(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0090ECU+((x)*0x800)))) -#define MCF548X_FEC_IAUR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009118U+((x)*0x800)))) -#define MCF548X_FEC_IALR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00911CU+((x)*0x800)))) -#define MCF548X_FEC_GAUR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009120U+((x)*0x800)))) -#define MCF548X_FEC_GALR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009124U+((x)*0x800)))) -#define MCF548X_FEC_FECTFWR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009144U+((x)*0x800)))) -#define MCF548X_FEC_FECRFDR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009184U+((x)*0x800)))) -#define MCF548X_FEC_FECRFSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009188U+((x)*0x800)))) -#define MCF548X_FEC_FECRFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00918CU+((x)*0x800)))) -#define MCF548X_FEC_FECRLRFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009190U+((x)*0x800)))) -#define MCF548X_FEC_FECRLWFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009194U+((x)*0x800)))) -#define MCF548X_FEC_FECRFAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009198U+((x)*0x800)))) -#define MCF548X_FEC_FECRFRP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00919CU+((x)*0x800)))) -#define MCF548X_FEC_FECRFWP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A0U+((x)*0x800)))) -#define MCF548X_FEC_FECTFDR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A4U+((x)*0x800)))) -#define MCF548X_FEC_FECTFSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091A8U+((x)*0x800)))) -#define MCF548X_FEC_FECTFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091ACU+((x)*0x800)))) -#define MCF548X_FEC_FECTLRFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B0U+((x)*0x800)))) -#define MCF548X_FEC_FECTLWFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B4U+((x)*0x800)))) -#define MCF548X_FEC_FECTFAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091B8U+((x)*0x800)))) -#define MCF548X_FEC_FECTFRP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091BCU+((x)*0x800)))) -#define MCF548X_FEC_FECTFWP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C0U+((x)*0x800)))) -#define MCF548X_FEC_FRST(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C4U+((x)*0x800)))) -#define MCF548X_FEC_CTCWR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0091C8U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009200U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009204U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009208U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00920CU+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009210U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009214U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009218U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00921CU+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009220U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_COL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009224U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_P64(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009228U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00922CU+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009230U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009234U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009238U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00923CU+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009240U+((x)*0x800)))) -#define MCF548X_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009244U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009248U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00924CU+((x)*0x800)))) -#define MCF548X_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009250U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009254U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009258U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00925CU+((x)*0x800)))) -#define MCF548X_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009260U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009264U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009268U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00926CU+((x)*0x800)))) -#define MCF548X_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009270U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009274U+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009284U+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009288U+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00928CU+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009290U+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009294U+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x009298U+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00929CU+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A0U+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A4U+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_P64(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092A8U+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092ACU+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B0U+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B4U+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_512TO1023(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092B8U+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_1024TO2047(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092BCU+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C0U+((x)*0x800)))) -#define MCF548X_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C4U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092C8U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092CCU+((x)*0x800)))) -#define MCF548X_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D0U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D4U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092D8U+((x)*0x800)))) -#define MCF548X_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092DCU+((x)*0x800)))) -#define MCF548X_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0092E0U+((x)*0x800)))) - -/* Bit definitions and macros for MCF548X_FEC_EIR */ -#define MCF548X_FEC_EIR_RFERR (0x00020000) -#define MCF548X_FEC_EIR_XFERR (0x00040000) -#define MCF548X_FEC_EIR_XFUN (0x00080000) -#define MCF548X_FEC_EIR_RL (0x00100000) -#define MCF548X_FEC_EIR_LC (0x00200000) -#define MCF548X_FEC_EIR_MII (0x00800000) -#define MCF548X_FEC_EIR_TXF (0x08000000) -#define MCF548X_FEC_EIR_GRA (0x10000000) -#define MCF548X_FEC_EIR_BABT (0x20000000) -#define MCF548X_FEC_EIR_BABR (0x40000000) -#define MCF548X_FEC_EIR_HBERR (0x80000000) -#define MCF548X_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) - -/* Bit definitions and macros for MCF548X_FEC_EIMR */ -#define MCF548X_FEC_EIMR_RFERR (0x00020000) -#define MCF548X_FEC_EIMR_XFERR (0x00040000) -#define MCF548X_FEC_EIMR_XFUN (0x00080000) -#define MCF548X_FEC_EIMR_RL (0x00100000) -#define MCF548X_FEC_EIMR_LC (0x00200000) -#define MCF548X_FEC_EIMR_MII (0x00800000) -#define MCF548X_FEC_EIMR_TXF (0x08000000) -#define MCF548X_FEC_EIMR_GRA (0x10000000) -#define MCF548X_FEC_EIMR_BABT (0x20000000) -#define MCF548X_FEC_EIMR_BABR (0x40000000) -#define MCF548X_FEC_EIMR_HBERR (0x80000000) -#define MCF548X_FEC_EIMR_MASK_ALL (0x00000000) -#define MCF548X_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) - -/* Bit definitions and macros for MCF548X_FEC_ECR */ -#define MCF548X_FEC_ECR_RESET (0x00000001) -#define MCF548X_FEC_ECR_ETHER_EN (0x00000002) - -/* Bit definitions and macros for MCF548X_FEC_MMFR */ -#define MCF548X_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) -#define MCF548X_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) -#define MCF548X_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) -#define MCF548X_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) -#define MCF548X_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) -#define MCF548X_FEC_MMFR_ST_01 (0x40000000) -#define MCF548X_FEC_MMFR_OP_READ (0x20000000) -#define MCF548X_FEC_MMFR_OP_WRITE (0x10000000) -#define MCF548X_FEC_MMFR_TA_10 (0x00020000) - -/* Bit definitions and macros for MCF548X_FEC_MSCR */ -#define MCF548X_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) -#define MCF548X_FEC_MSCR_DIS_PREAMBLE (0x00000080) -#define MCF548X_FEC_MSCR_MII_SPEED_133 (0x1B<<1) -#define MCF548X_FEC_MSCR_MII_SPEED_120 (0x18<<1) -#define MCF548X_FEC_MSCR_MII_SPEED_66 (0xE<<1) -#define MCF548X_FEC_MSCR_MII_SPEED_60 (0xC<<1) - -/* Bit definitions and macros for MCF548X_FEC_MIBC */ -#define MCF548X_FEC_MIBC_MIB_IDLE (0x40000000) -#define MCF548X_FEC_MIBC_MIB_DISABLE (0x80000000) - -/* Bit definitions and macros for MCF548X_FEC_RCR */ -#define MCF548X_FEC_RCR_LOOP (0x00000001) -#define MCF548X_FEC_RCR_DRT (0x00000002) -#define MCF548X_FEC_RCR_MII_MODE (0x00000004) -#define MCF548X_FEC_RCR_PROM (0x00000008) -#define MCF548X_FEC_RCR_BC_REJ (0x00000010) -#define MCF548X_FEC_RCR_FCE (0x00000020) -#define MCF548X_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) - -/* Bit definitions and macros for MCF548X_FEC_R_HASH */ -#define MCF548X_FEC_R_HASH_HASH(x) (((x)&0x0000003F)<<24) -#define MCF548X_FEC_R_HASH_MULTCAST (0x40000000) -#define MCF548X_FEC_R_HASH_FCE_DC (0x80000000) - -/* Bit definitions and macros for MCF548X_FEC_TCR */ -#define MCF548X_FEC_TCR_GTS (0x00000001) -#define MCF548X_FEC_TCR_HBC (0x00000002) -#define MCF548X_FEC_TCR_FDEN (0x00000004) -#define MCF548X_FEC_TCR_TFC_PAUSE (0x00000008) -#define MCF548X_FEC_TCR_RFC_PAUSE (0x00000010) - -/* Bit definitions and macros for MCF548X_FEC_PAUR */ -#define MCF548X_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF548X_FEC_OPD */ -#define MCF548X_FEC_OPD_OP_PAUSE(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF548X_FEC_FECTFWR */ -#define MCF548X_FEC_FECTFWR_X_WMRK(x) (((x)&0x0000000F)<<0) -#define MCF548X_FEC_FECTFWR_X_WMRK_64 (0x00000000) -#define MCF548X_FEC_FECTFWR_X_WMRK_128 (0x00000001) -#define MCF548X_FEC_FECTFWR_X_WMRK_192 (0x00000002) -#define MCF548X_FEC_FECTFWR_X_WMRK_256 (0x00000003) -#define MCF548X_FEC_FECTFWR_X_WMRK_320 (0x00000004) -#define MCF548X_FEC_FECTFWR_X_WMRK_384 (0x00000005) -#define MCF548X_FEC_FECTFWR_X_WMRK_448 (0x00000006) -#define MCF548X_FEC_FECTFWR_X_WMRK_512 (0x00000007) -#define MCF548X_FEC_FECTFWR_X_WMRK_576 (0x00000008) -#define MCF548X_FEC_FECTFWR_X_WMRK_640 (0x00000009) -#define MCF548X_FEC_FECTFWR_X_WMRK_704 (0x0000000A) -#define MCF548X_FEC_FECTFWR_X_WMRK_768 (0x0000000B) -#define MCF548X_FEC_FECTFWR_X_WMRK_832 (0x0000000C) -#define MCF548X_FEC_FECTFWR_X_WMRK_896 (0x0000000D) -#define MCF548X_FEC_FECTFWR_X_WMRK_960 (0x0000000E) -#define MCF548X_FEC_FECTFWR_X_WMRK_1024 (0x0000000F) - -/* Bit definitions and macros for MCF548X_FEC_FECRFDR */ -#define MCF548X_FEC_FECRFDR_ADDR0 (((uintptr_t)__MBAR + (0x009184))) -#define MCF548X_FEC_FECRFDR_ADDR1 (((uintptr_t)__MBAR + (0x009984))) -#define MCF548X_FEC_FECRFDR_ADDR(x) (((uintptr_t)__MBAR + (0x009184U+(0x800*x)))) - -/* Bit definitions and macros for MCF548X_FEC_FECRFSR */ -#define MCF548X_FEC_FECRFSR_EMT (0x00010000) -#define MCF548X_FEC_FECRFSR_ALARM (0x00020000) -#define MCF548X_FEC_FECRFSR_FU (0x00040000) -#define MCF548X_FEC_FECRFSR_FR (0x00080000) -#define MCF548X_FEC_FECRFSR_OF (0x00100000) -#define MCF548X_FEC_FECRFSR_UF (0x00200000) -#define MCF548X_FEC_FECRFSR_RXW (0x00400000) -#define MCF548X_FEC_FECRFSR_FAE (0x00800000) -#define MCF548X_FEC_FECRFSR_FRM(x) (((x)&0x0000000F)<<24) -#define MCF548X_FEC_FECRFSR_IP (0x80000000) - -/* Bit definitions and macros for MCF548X_FEC_FECRFCR */ -#define MCF548X_FEC_FECRFCR_COUNTER(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_FEC_FECRFCR_OF_MSK (0x00080000) -#define MCF548X_FEC_FECRFCR_UF_MSK (0x00100000) -#define MCF548X_FEC_FECRFCR_RXW_MSK (0x00200000) -#define MCF548X_FEC_FECRFCR_FAE_MSK (0x00400000) -#define MCF548X_FEC_FECRFCR_IP_MSK (0x00800000) -#define MCF548X_FEC_FECRFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF548X_FEC_FECRFCR_FRM (0x08000000) -#define MCF548X_FEC_FECRFCR_TIMER (0x10000000) -#define MCF548X_FEC_FECRFCR_WFR (0x20000000) -#define MCF548X_FEC_FECRFCR_WCTL (0x40000000) - -/* Bit definitions and macros for MCF548X_FEC_FECRLRFP */ -#define MCF548X_FEC_FECRLRFP_LRFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_FEC_FECRLWFP */ -#define MCF548X_FEC_FECRLWFP_LWFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_FEC_FECRFAR */ -#define MCF548X_FEC_FECRFAR_ALARM(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_FEC_FECRFRP */ -#define MCF548X_FEC_FECRFRP_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_FEC_FECRFWP */ -#define MCF548X_FEC_FECRFWP_WRITE(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_FEC_FECTFDR */ -#define MCF548X_FEC_FECTFDR_TFCW_TC (0x04000000) -#define MCF548X_FEC_FECTFDR_TFCW_ABC (0x02000000) -#define MCF548X_FEC_FECTFDR_ADDR0 (((uintptr_t)__MBAR + (0x0091A4))) -#define MCF548X_FEC_FECTFDR_ADDR1 (((uintptr_t)__MBAR + (0x0099A4))) -#define MCF548X_FEC_FECTFDR_ADDR(x) (((uintptr_t)__MBAR + (0x0091A4U+(0x800*x)))) - -/* Bit definitions and macros for MCF548X_FEC_FECTFSR */ -#define MCF548X_FEC_FECTFSR_EMT (0x00010000) -#define MCF548X_FEC_FECTFSR_ALARM (0x00020000) -#define MCF548X_FEC_FECTFSR_FU (0x00040000) -#define MCF548X_FEC_FECTFSR_FR (0x00080000) -#define MCF548X_FEC_FECTFSR_OF (0x00100000) -#define MCF548X_FEC_FECTFSR_UP (0x00200000) -#define MCF548X_FEC_FECTFSR_FAE (0x00800000) -#define MCF548X_FEC_FECTFSR_FRM(x) (((x)&0x0000000F)<<24) -#define MCF548X_FEC_FECTFSR_TXW (0x40000000) -#define MCF548X_FEC_FECTFSR_IP (0x80000000) - -/* Bit definitions and macros for MCF548X_FEC_FECTFCR */ -#define MCF548X_FEC_FECTFCR_RESERVED (0x00200000) -#define MCF548X_FEC_FECTFCR_COUNTER(x) (((x)&0x0000FFFF)<<0|0x00200000) -#define MCF548X_FEC_FECTFCR_TXW_MSK (0x00240000) -#define MCF548X_FEC_FECTFCR_OF_MSK (0x00280000) -#define MCF548X_FEC_FECTFCR_UF_MSK (0x00300000) -#define MCF548X_FEC_FECTFCR_FAE_MSK (0x00600000) -#define MCF548X_FEC_FECTFCR_IP_MSK (0x00A00000) -#define MCF548X_FEC_FECTFCR_GR(x) (((x)&0x00000007)<<24|0x00200000) -#define MCF548X_FEC_FECTFCR_FRM (0x08200000) -#define MCF548X_FEC_FECTFCR_TIMER (0x10200000) -#define MCF548X_FEC_FECTFCR_WFR (0x20200000) -#define MCF548X_FEC_FECTFCR_WCTL (0x40200000) - -/* Bit definitions and macros for MCF548X_FEC_FECTLRFP */ -#define MCF548X_FEC_FECTLRFP_LRFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_FEC_FECTLWFP */ -#define MCF548X_FEC_FECTLWFP_LWFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_FEC_FECTFAR */ -#define MCF548X_FEC_FECTFAR_ALARM(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_FEC_FECTFRP */ -#define MCF548X_FEC_FECTFRP_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_FEC_FECTFWP */ -#define MCF548X_FEC_FECTFWP_WRITE(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_FEC_FRST */ -#define MCF548X_FEC_FRST_RST_CTL (0x01000000) -#define MCF548X_FEC_FRST_SW_RST (0x02000000) - -/* Bit definitions and macros for MCF548X_FEC_CTCWR */ -#define MCF548X_FEC_CTCWR_TFCW (0x01000000) -#define MCF548X_FEC_CTCWR_CRC (0x02000000) - - -/********************************************************************* -* -* System Integration Unit (SIU) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_SIU_SBCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000010))) -#define MCF548X_SIU_SECSACR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000038))) -#define MCF548X_SIU_RSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000044))) -#define MCF548X_SIU_JTAGID (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000050))) - -/* Bit definitions and macros for MCF548X_SIU_SBCR */ -#define MCF548X_SIU_SBCR_PIN2DSPI (0x08000000) -#define MCF548X_SIU_SBCR_DMA2CPU (0x10000000) -#define MCF548X_SIU_SBCR_CPU2DMA (0x20000000) -#define MCF548X_SIU_SBCR_PIN2DMA (0x40000000) -#define MCF548X_SIU_SBCR_PIN2CPU (0x80000000) - -/* Bit definitions and macros for MCF548X_SIU_SECSACR */ -#define MCF548X_SIU_SECSACR_SEQEN (0x00000001) - -/* Bit definitions and macros for MCF548X_SIU_RSR */ -#define MCF548X_SIU_RSR_RST (0x00000001) -#define MCF548X_SIU_RSR_RSTWD (0x00000002) -#define MCF548X_SIU_RSR_RSTJTG (0x00000008) - -/* Bit definitions and macros for MCF548X_SIU_JTAGID */ -#define MCF548X_SIU_JTAGID_REV (0xF0000000) -#define MCF548X_SIU_JTAGID_PROCESSOR (0x0FFFFFFF) -#define MCF548X_SIU_JTAGID_MCF5485 (0x0800C01D) -#define MCF548X_SIU_JTAGID_MCF5484 (0x0800D01D) -#define MCF548X_SIU_JTAGID_MCF5483 (0x0800E01D) -#define MCF548X_SIU_JTAGID_MCF5482 (0x0800F01D) -#define MCF548X_SIU_JTAGID_MCF5481 (0x0801001D) -#define MCF548X_SIU_JTAGID_MCF5480 (0x0801101D) -#define MCF548X_SIU_JTAGID_MCF5475 (0x0801201D) -#define MCF548X_SIU_JTAGID_MCF5474 (0x0801301D) -#define MCF548X_SIU_JTAGID_MCF5473 (0x0801401D) -#define MCF548X_SIU_JTAGID_MCF5472 (0x0801501D) -#define MCF548X_SIU_JTAGID_MCF5471 (0x0801601D) -#define MCF548X_SIU_JTAGID_MCF5470 (0x0801701D) - -/********************************************************************* -* -* Comm Timer Module (CTM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_CTM_CTCRF0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F00))) -#define MCF548X_CTM_CTCRF1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F04))) -#define MCF548X_CTM_CTCRF2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F08))) -#define MCF548X_CTM_CTCRF3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F0C))) -#define MCF548X_CTM_CTCRFn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F00U+((x)*0x004)))) -#define MCF548X_CTM_CTCRV4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F10))) -#define MCF548X_CTM_CTCRV5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F14))) -#define MCF548X_CTM_CTCRV6 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F18))) -#define MCF548X_CTM_CTCRV7 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F1C))) -#define MCF548X_CTM_CTCRVn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x007F10U+((x)*0x004)))) - -/* Bit definitions and macros for MCF548X_CTM_CTCRFn */ -#define MCF548X_CTM_CTCRFn_CRV(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_CTM_CTCRFn_S(x) (((x)&0x0000000F)<<16) -#define MCF548X_CTM_CTCRFn_PCT(x) (((x)&0x00000007)<<20) -#define MCF548X_CTM_CTCRFn_M (0x00800000) -#define MCF548X_CTM_CTCRFn_IM (0x01000000) -#define MCF548X_CTM_CTCRFn_I (0x80000000) -#define MCF548X_CTM_CTCRFn_PCT_100 (0x00000000) -#define MCF548X_CTM_CTCRFn_PCT_50 (0x00100000) -#define MCF548X_CTM_CTCRFn_PCT_25 (0x00200000) -#define MCF548X_CTM_CTCRFn_PCT_12p5 (0x00300000) -#define MCF548X_CTM_CTCRFn_PCT_6p25 (0x00400000) -#define MCF548X_CTM_CTCRFn_PCT_OFF (0x00500000) -#define MCF548X_CTM_CTCRFn_S_CLK_1 (0x00000000) -#define MCF548X_CTM_CTCRFn_S_CLK_2 (0x00010000) -#define MCF548X_CTM_CTCRFn_S_CLK_4 (0x00020000) -#define MCF548X_CTM_CTCRFn_S_CLK_8 (0x00030000) -#define MCF548X_CTM_CTCRFn_S_CLK_16 (0x00040000) -#define MCF548X_CTM_CTCRFn_S_CLK_32 (0x00050000) -#define MCF548X_CTM_CTCRFn_S_CLK_64 (0x00060000) -#define MCF548X_CTM_CTCRFn_S_CLK_128 (0x00070000) -#define MCF548X_CTM_CTCRFn_S_CLK_256 (0x00080000) - -/* Bit definitions and macros for MCF548X_CTM_CTCRVn */ -#define MCF548X_CTM_CTCRVn_CRV(x) (((x)&0x00FFFFFF)<<0) -#define MCF548X_CTM_CTCRVn_PCT(x) (((x)&0x00000007)<<24) -#define MCF548X_CTM_CTCRVn_M (0x08000000) -#define MCF548X_CTM_CTCRVn_S(x) (((x)&0x0000000F)<<28) -#define MCF548X_CTM_CTCRVn_S_CLK_1 (0x00000000) -#define MCF548X_CTM_CTCRVn_S_CLK_2 (0x10000000) -#define MCF548X_CTM_CTCRVn_S_CLK_4 (0x20000000) -#define MCF548X_CTM_CTCRVn_S_CLK_8 (0x30000000) -#define MCF548X_CTM_CTCRVn_S_CLK_16 (0x40000000) -#define MCF548X_CTM_CTCRVn_S_CLK_32 (0x50000000) -#define MCF548X_CTM_CTCRVn_S_CLK_64 (0x60000000) -#define MCF548X_CTM_CTCRVn_S_CLK_128 (0x70000000) -#define MCF548X_CTM_CTCRVn_S_CLK_256 (0x80000000) -#define MCF548X_CTM_CTCRVn_PCT_100 (0x00000000) -#define MCF548X_CTM_CTCRVn_PCT_50 (0x01000000) -#define MCF548X_CTM_CTCRVn_PCT_25 (0x02000000) -#define MCF548X_CTM_CTCRVn_PCT_12p5 (0x03000000) -#define MCF548X_CTM_CTCRVn_PCT_6p25 (0x04000000) -#define MCF548X_CTM_CTCRVn_PCT_OFF (0x05000000) - -/********************************************************************* -* -* DMA Serial Peripheral Interface (DSPI) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_DSPI_DMCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A00))) -#define MCF548X_DSPI_DTCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A08))) -#define MCF548X_DSPI_DCTAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A0C))) -#define MCF548X_DSPI_DCTAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A10))) -#define MCF548X_DSPI_DCTAR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A14))) -#define MCF548X_DSPI_DCTAR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A18))) -#define MCF548X_DSPI_DCTAR4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A1C))) -#define MCF548X_DSPI_DCTAR5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A20))) -#define MCF548X_DSPI_DCTAR6 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A24))) -#define MCF548X_DSPI_DCTAR7 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A28))) -#define MCF548X_DSPI_DCTARn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A0CU+((x)*0x004)))) -#define MCF548X_DSPI_DSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A2C))) -#define MCF548X_DSPI_DIRSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A30))) -#define MCF548X_DSPI_DTFR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A34))) -#define MCF548X_DSPI_DRFR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A38))) -#define MCF548X_DSPI_DTFDR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A3C))) -#define MCF548X_DSPI_DTFDR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A40))) -#define MCF548X_DSPI_DTFDR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A44))) -#define MCF548X_DSPI_DTFDR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A48))) -#define MCF548X_DSPI_DTFDRn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A3CU+((x)*0x004)))) -#define MCF548X_DSPI_DRFDR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A7C))) -#define MCF548X_DSPI_DRFDR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A80))) -#define MCF548X_DSPI_DRFDR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A84))) -#define MCF548X_DSPI_DRFDR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A88))) -#define MCF548X_DSPI_DRFDRn(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008A7CU+((x)*0x004)))) - -/* Bit definitions and macros for MCF548X_DSPI_DMCR */ -#define MCF548X_DSPI_DMCR_HALT (0x00000001) -#define MCF548X_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) -#define MCF548X_DSPI_DMCR_CRXF (0x00000400) -#define MCF548X_DSPI_DMCR_CTXF (0x00000800) -#define MCF548X_DSPI_DMCR_DRXF (0x00001000) -#define MCF548X_DSPI_DMCR_DTXF (0x00002000) -#define MCF548X_DSPI_DMCR_CSIS0 (0x00010000) -#define MCF548X_DSPI_DMCR_CSIS2 (0x00040000) -#define MCF548X_DSPI_DMCR_CSIS3 (0x00080000) -#define MCF548X_DSPI_DMCR_CSIS5 (0x00200000) -#define MCF548X_DSPI_DMCR_ROOE (0x01000000) -#define MCF548X_DSPI_DMCR_PCSSE (0x02000000) -#define MCF548X_DSPI_DMCR_MTFE (0x04000000) -#define MCF548X_DSPI_DMCR_FRZ (0x08000000) -#define MCF548X_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) -#define MCF548X_DSPI_DMCR_CSCK (0x40000000) -#define MCF548X_DSPI_DMCR_MSTR (0x80000000) - -/* Bit definitions and macros for MCF548X_DSPI_DTCR */ -#define MCF548X_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF548X_DSPI_DCTARn */ -#define MCF548X_DSPI_DCTARn_BR(x) (((x)&0x0000000F)<<0) -#define MCF548X_DSPI_DCTARn_DT(x) (((x)&0x0000000F)<<4) -#define MCF548X_DSPI_DCTARn_ASC(x) (((x)&0x0000000F)<<8) -#define MCF548X_DSPI_DCTARn_CSSCK(x) (((x)&0x0000000F)<<12) -#define MCF548X_DSPI_DCTARn_PBR(x) (((x)&0x00000003)<<16) -#define MCF548X_DSPI_DCTARn_PDT(x) (((x)&0x00000003)<<18) -#define MCF548X_DSPI_DCTARn_PASC(x) (((x)&0x00000003)<<20) -#define MCF548X_DSPI_DCTARn_PCSSCK(x) (((x)&0x00000003)<<22) -#define MCF548X_DSPI_DCTARn_LSBFE (0x01000000) -#define MCF548X_DSPI_DCTARn_CPHA (0x02000000) -#define MCF548X_DSPI_DCTARn_CPOL (0x04000000) -#define MCF548X_DSPI_DCTARn_TRSZ(x) (((x)&0x0000000F)<<27) -#define MCF548X_DSPI_DCTARn_PCSSCK_1CLK (0x00000000) -#define MCF548X_DSPI_DCTARn_PCSSCK_3CLK (0x00400000) -#define MCF548X_DSPI_DCTARn_PCSSCK_5CLK (0x00800000) -#define MCF548X_DSPI_DCTARn_PCSSCK_7CLK (0x00A00000) -#define MCF548X_DSPI_DCTARn_PASC_1CLK (0x00000000) -#define MCF548X_DSPI_DCTARn_PASC_3CLK (0x00100000) -#define MCF548X_DSPI_DCTARn_PASC_5CLK (0x00200000) -#define MCF548X_DSPI_DCTARn_PASC_7CLK (0x00300000) -#define MCF548X_DSPI_DCTARn_PDT_1CLK (0x00000000) -#define MCF548X_DSPI_DCTARn_PDT_3CLK (0x00040000) -#define MCF548X_DSPI_DCTARn_PDT_5CLK (0x00080000) -#define MCF548X_DSPI_DCTARn_PDT_7CLK (0x000A0000) -#define MCF548X_DSPI_DCTARn_PBR_1CLK (0x00000000) -#define MCF548X_DSPI_DCTARn_PBR_3CLK (0x00010000) -#define MCF548X_DSPI_DCTARn_PBR_5CLK (0x00020000) -#define MCF548X_DSPI_DCTARn_PBR_7CLK (0x00030000) - -/* Bit definitions and macros for MCF548X_DSPI_DSR */ -#define MCF548X_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0) -#define MCF548X_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) -#define MCF548X_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) -#define MCF548X_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) -#define MCF548X_DSPI_DSR_RFDF (0x00020000) -#define MCF548X_DSPI_DSR_RFOF (0x00080000) -#define MCF548X_DSPI_DSR_TFFF (0x02000000) -#define MCF548X_DSPI_DSR_TFUF (0x08000000) -#define MCF548X_DSPI_DSR_EOQF (0x10000000) -#define MCF548X_DSPI_DSR_TXRXS (0x40000000) -#define MCF548X_DSPI_DSR_TCF (0x80000000) - -/* Bit definitions and macros for MCF548X_DSPI_DIRSR */ -#define MCF548X_DSPI_DIRSR_RFDFS (0x00010000) -#define MCF548X_DSPI_DIRSR_RFDFE (0x00020000) -#define MCF548X_DSPI_DIRSR_RFOFE (0x00080000) -#define MCF548X_DSPI_DIRSR_TFFFS (0x01000000) -#define MCF548X_DSPI_DIRSR_TFFFE (0x02000000) -#define MCF548X_DSPI_DIRSR_TFUFE (0x08000000) -#define MCF548X_DSPI_DIRSR_EOQFE (0x10000000) -#define MCF548X_DSPI_DIRSR_TCFE (0x80000000) - -/* Bit definitions and macros for MCF548X_DSPI_DTFR */ -#define MCF548X_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_DSPI_DTFR_CS0 (0x00010000) -#define MCF548X_DSPI_DTFR_CS2 (0x00040000) -#define MCF548X_DSPI_DTFR_CS3 (0x00080000) -#define MCF548X_DSPI_DTFR_CS5 (0x00200000) -#define MCF548X_DSPI_DTFR_CTCNT (0x04000000) -#define MCF548X_DSPI_DTFR_EOQ (0x08000000) -#define MCF548X_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) -#define MCF548X_DSPI_DTFR_CONT (0x80000000) - -/* Bit definitions and macros for MCF548X_DSPI_DRFR */ -#define MCF548X_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF548X_DSPI_DTFDRn */ -#define MCF548X_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF548X_DSPI_DRFDRn */ -#define MCF548X_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0) - - -/********************************************************************* -* -* Edge Port Module (EPORT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_EPORT_EPPAR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000F00))) -#define MCF548X_EPORT_EPDDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F04))) -#define MCF548X_EPORT_EPIER (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F05))) -#define MCF548X_EPORT_EPDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F08))) -#define MCF548X_EPORT_EPPDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F09))) -#define MCF548X_EPORT_EPFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000F0C))) - -/* Bit definitions and macros for MCF548X_EPORT_EPPAR */ -#define MCF548X_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define MCF548X_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define MCF548X_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define MCF548X_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define MCF548X_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define MCF548X_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define MCF548X_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define MCF548X_EPORT_EPPAR_EPPAx_LEVEL (0) -#define MCF548X_EPORT_EPPAR_EPPAx_RISING (1) -#define MCF548X_EPORT_EPPAR_EPPAx_FALLING (2) -#define MCF548X_EPORT_EPPAR_EPPAx_BOTH (3) - -/* Bit definitions and macros for MCF548X_EPORT_EPDDR */ -#define MCF548X_EPORT_EPDDR_EPDD1 (0x02) -#define MCF548X_EPORT_EPDDR_EPDD2 (0x04) -#define MCF548X_EPORT_EPDDR_EPDD3 (0x08) -#define MCF548X_EPORT_EPDDR_EPDD4 (0x10) -#define MCF548X_EPORT_EPDDR_EPDD5 (0x20) -#define MCF548X_EPORT_EPDDR_EPDD6 (0x40) -#define MCF548X_EPORT_EPDDR_EPDD7 (0x80) - -/* Bit definitions and macros for MCF548X_EPORT_EPIER */ -#define MCF548X_EPORT_EPIER_EPIE1 (0x02) -#define MCF548X_EPORT_EPIER_EPIE2 (0x04) -#define MCF548X_EPORT_EPIER_EPIE3 (0x08) -#define MCF548X_EPORT_EPIER_EPIE4 (0x10) -#define MCF548X_EPORT_EPIER_EPIE5 (0x20) -#define MCF548X_EPORT_EPIER_EPIE6 (0x40) -#define MCF548X_EPORT_EPIER_EPIE7 (0x80) - -/* Bit definitions and macros for MCF548X_EPORT_EPDR */ -#define MCF548X_EPORT_EPDR_EPD1 (0x02) -#define MCF548X_EPORT_EPDR_EPD2 (0x04) -#define MCF548X_EPORT_EPDR_EPD3 (0x08) -#define MCF548X_EPORT_EPDR_EPD4 (0x10) -#define MCF548X_EPORT_EPDR_EPD5 (0x20) -#define MCF548X_EPORT_EPDR_EPD6 (0x40) -#define MCF548X_EPORT_EPDR_EPD7 (0x80) - -/* Bit definitions and macros for MCF548X_EPORT_EPPDR */ -#define MCF548X_EPORT_EPPDR_EPPD1 (0x02) -#define MCF548X_EPORT_EPPDR_EPPD2 (0x04) -#define MCF548X_EPORT_EPPDR_EPPD3 (0x08) -#define MCF548X_EPORT_EPPDR_EPPD4 (0x10) -#define MCF548X_EPORT_EPPDR_EPPD5 (0x20) -#define MCF548X_EPORT_EPPDR_EPPD6 (0x40) -#define MCF548X_EPORT_EPPDR_EPPD7 (0x80) - -/* Bit definitions and macros for MCF548X_EPORT_EPFR */ -#define MCF548X_EPORT_EPFR_EPF1 (0x02) -#define MCF548X_EPORT_EPFR_EPF2 (0x04) -#define MCF548X_EPORT_EPFR_EPF3 (0x08) -#define MCF548X_EPORT_EPFR_EPF4 (0x10) -#define MCF548X_EPORT_EPFR_EPF5 (0x20) -#define MCF548X_EPORT_EPFR_EPF6 (0x40) -#define MCF548X_EPORT_EPFR_EPF7 (0x80) - -/********************************************************************* -* -* FlexBus Chip Selects (FBCS) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_FBCS_CSAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000500))) -#define MCF548X_FBCS_CSMR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000504))) -#define MCF548X_FBCS_CSCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000508))) -#define MCF548X_FBCS_CSAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00050C))) -#define MCF548X_FBCS_CSMR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000510))) -#define MCF548X_FBCS_CSCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000514))) -#define MCF548X_FBCS_CSAR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000518))) -#define MCF548X_FBCS_CSMR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00051C))) -#define MCF548X_FBCS_CSCR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000520))) -#define MCF548X_FBCS_CSAR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000524))) -#define MCF548X_FBCS_CSMR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000528))) -#define MCF548X_FBCS_CSCR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00052C))) -#define MCF548X_FBCS_CSAR4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000530))) -#define MCF548X_FBCS_CSMR4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000534))) -#define MCF548X_FBCS_CSCR4 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000538))) -#define MCF548X_FBCS_CSAR5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00053C))) -#define MCF548X_FBCS_CSMR5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000540))) -#define MCF548X_FBCS_CSCR5 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000544))) -#define MCF548X_FBCS_CSAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000500U+((x)*0x00C)))) -#define MCF548X_FBCS_CSMR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000504U+((x)*0x00C)))) -#define MCF548X_FBCS_CSCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000508U+((x)*0x00C)))) - -/* Bit definitions and macros for MCF548X_FBCS_CSAR */ -#define MCF548X_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) - -/* Bit definitions and macros for MCF548X_FBCS_CSMR */ -#define MCF548X_FBCS_CSMR_V (0x00000001) -#define MCF548X_FBCS_CSMR_WP (0x00000100) -#define MCF548X_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) -#define MCF548X_FBCS_CSMR_BAM_4G (0xFFFF0000) -#define MCF548X_FBCS_CSMR_BAM_2G (0x7FFF0000) -#define MCF548X_FBCS_CSMR_BAM_1G (0x3FFF0000) -#define MCF548X_FBCS_CSMR_BAM_1024M (0x3FFF0000) -#define MCF548X_FBCS_CSMR_BAM_512M (0x1FFF0000) -#define MCF548X_FBCS_CSMR_BAM_256M (0x0FFF0000) -#define MCF548X_FBCS_CSMR_BAM_128M (0x07FF0000) -#define MCF548X_FBCS_CSMR_BAM_64M (0x03FF0000) -#define MCF548X_FBCS_CSMR_BAM_32M (0x01FF0000) -#define MCF548X_FBCS_CSMR_BAM_16M (0x00FF0000) -#define MCF548X_FBCS_CSMR_BAM_8M (0x007F0000) -#define MCF548X_FBCS_CSMR_BAM_4M (0x003F0000) -#define MCF548X_FBCS_CSMR_BAM_2M (0x001F0000) -#define MCF548X_FBCS_CSMR_BAM_1M (0x000F0000) -#define MCF548X_FBCS_CSMR_BAM_1024K (0x000F0000) -#define MCF548X_FBCS_CSMR_BAM_512K (0x00070000) -#define MCF548X_FBCS_CSMR_BAM_256K (0x00030000) -#define MCF548X_FBCS_CSMR_BAM_128K (0x00010000) -#define MCF548X_FBCS_CSMR_BAM_64K (0x00000000) - -/* Bit definitions and macros for MCF548X_FBCS_CSCR */ -#define MCF548X_FBCS_CSCR_BSTW (0x00000008) -#define MCF548X_FBCS_CSCR_BSTR (0x00000010) -#define MCF548X_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) -#define MCF548X_FBCS_CSCR_AA (0x00000100) -#define MCF548X_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) -#define MCF548X_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) -#define MCF548X_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) -#define MCF548X_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) -#define MCF548X_FBCS_CSCR_SWSEN (0x00800000) -#define MCF548X_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) -#define MCF548X_FBCS_CSCR_PS_8 (0x00000040) -#define MCF548X_FBCS_CSCR_PS_16 (0x00000080) -#define MCF548X_FBCS_CSCR_PS_32 (0x00000000) - - -/********************************************************************* -* -* General Purpose I/O (GPIO) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_GPIO_PODR_FBCTL (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A00))) -#define MCF548X_GPIO_PODR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A01))) -#define MCF548X_GPIO_PODR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A02))) -#define MCF548X_GPIO_PODR_FEC0H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A04))) -#define MCF548X_GPIO_PODR_FEC0L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A05))) -#define MCF548X_GPIO_PODR_FEC1H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A06))) -#define MCF548X_GPIO_PODR_FEC1L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A07))) -#define MCF548X_GPIO_PODR_FECI2C (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A08))) -#define MCF548X_GPIO_PODR_PCIBG (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A09))) -#define MCF548X_GPIO_PODR_PCIBR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A0A))) -#define MCF548X_GPIO_PODR_PSC3PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A0C))) -#define MCF548X_GPIO_PODR_PSC1PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A0D))) -#define MCF548X_GPIO_PODR_DSPI (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A0E))) -#define MCF548X_GPIO_PDDR_FBCTL (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A10))) -#define MCF548X_GPIO_PDDR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A11))) -#define MCF548X_GPIO_PDDR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A12))) -#define MCF548X_GPIO_PDDR_FEC0H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A14))) -#define MCF548X_GPIO_PDDR_FEC0L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A15))) -#define MCF548X_GPIO_PDDR_FEC1H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A16))) -#define MCF548X_GPIO_PDDR_FEC1L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A17))) -#define MCF548X_GPIO_PDDR_FECI2C (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A18))) -#define MCF548X_GPIO_PDDR_PCIBG (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A19))) -#define MCF548X_GPIO_PDDR_PCIBR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A1A))) -#define MCF548X_GPIO_PDDR_PSC3PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A1C))) -#define MCF548X_GPIO_PDDR_PSC1PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A1D))) -#define MCF548X_GPIO_PDDR_DSPI (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A1E))) -#define MCF548X_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A20))) -#define MCF548X_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A21))) -#define MCF548X_GPIO_PPDSDR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A22))) -#define MCF548X_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A24))) -#define MCF548X_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A25))) -#define MCF548X_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A26))) -#define MCF548X_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A27))) -#define MCF548X_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A28))) -#define MCF548X_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A29))) -#define MCF548X_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A2A))) -#define MCF548X_GPIO_PPDSDR_PSC3PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A2C))) -#define MCF548X_GPIO_PPDSDR_PSC1PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A2D))) -#define MCF548X_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A2E))) -#define MCF548X_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A30))) -#define MCF548X_GPIO_PCLRR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A31))) -#define MCF548X_GPIO_PCLRR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A32))) -#define MCF548X_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A34))) -#define MCF548X_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A35))) -#define MCF548X_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A36))) -#define MCF548X_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A37))) -#define MCF548X_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A38))) -#define MCF548X_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A39))) -#define MCF548X_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A3A))) -#define MCF548X_GPIO_PCLRR_PSC3PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A3C))) -#define MCF548X_GPIO_PCLRR_PSC1PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A3D))) -#define MCF548X_GPIO_PCLRR_DSPI (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A3E))) -#define MCF548X_GPIO_PAR_FBCTL (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A40))) -#define MCF548X_GPIO_PAR_FBCS (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A42))) -#define MCF548X_GPIO_PAR_DMA (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A43))) -#define MCF548X_GPIO_PAR_FECI2CIRQ (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A44))) -#define MCF548X_GPIO_PAR_PCIBG (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A48))) -#define MCF548X_GPIO_PAR_PCIBR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A4A))) -#define MCF548X_GPIO_PAR_PSC3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A4C))) -#define MCF548X_GPIO_PAR_PSC2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A4D))) -#define MCF548X_GPIO_PAR_PSC1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A4E))) -#define MCF548X_GPIO_PAR_PSC0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A4F))) -#define MCF548X_GPIO_PAR_DSPI (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x000A50))) -#define MCF548X_GPIO_PAR_TIMER (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000A52))) - -/* Bit definitions and macros for MCF548X_GPIO_PODR_FBCTL */ -#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x01) -#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x02) -#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x04) -#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x08) -#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) -#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) -#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) -#define MCF548X_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PODR_FBCS */ -#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS1 (0x02) -#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS2 (0x04) -#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS3 (0x08) -#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) -#define MCF548X_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) - -/* Bit definitions and macros for MCF548X_GPIO_PODR_DMA */ -#define MCF548X_GPIO_PODR_DMA_PODR_DMA0 (0x01) -#define MCF548X_GPIO_PODR_DMA_PODR_DMA1 (0x02) -#define MCF548X_GPIO_PODR_DMA_PODR_DMA2 (0x04) -#define MCF548X_GPIO_PODR_DMA_PODR_DMA3 (0x08) - -/* Bit definitions and macros for MCF548X_GPIO_PODR_FEC0H */ -#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x01) -#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x02) -#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x04) -#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x08) -#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) -#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) -#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) -#define MCF548X_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PODR_FEC0L */ -#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x01) -#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x02) -#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x04) -#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x08) -#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) -#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) -#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) -#define MCF548X_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PODR_FEC1H */ -#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x01) -#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x02) -#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x04) -#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x08) -#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) -#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) -#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) -#define MCF548X_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PODR_FEC1L */ -#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x01) -#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x02) -#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x04) -#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x08) -#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) -#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) -#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) -#define MCF548X_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PODR_FECI2C */ -#define MCF548X_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) -#define MCF548X_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) -#define MCF548X_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) -#define MCF548X_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF548X_GPIO_PODR_PCIBG */ -#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x01) -#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x02) -#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x04) -#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x08) -#define MCF548X_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) - -/* Bit definitions and macros for MCF548X_GPIO_PODR_PCIBR */ -#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x01) -#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x02) -#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x04) -#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x08) -#define MCF548X_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) - -/* Bit definitions and macros for MCF548X_GPIO_PODR_PSC3PSC2 */ -#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC20 (0x01) -#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC21 (0x02) -#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC22 (0x04) -#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC23 (0x08) -#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC24 (0x10) -#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC25 (0x20) -#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC26 (0x40) -#define MCF548X_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PODR_PSC1PSC0 */ -#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC00 (0x01) -#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC01 (0x02) -#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC02 (0x04) -#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC03 (0x08) -#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC04 (0x10) -#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC05 (0x20) -#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC06 (0x40) -#define MCF548X_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PODR_DSPI */ -#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI0 (0x01) -#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI1 (0x02) -#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI2 (0x04) -#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI3 (0x08) -#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) -#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) -#define MCF548X_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) - -/* Bit definitions and macros for MCF548X_GPIO_PDDR_FBCTL */ -#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x01) -#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x02) -#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x04) -#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x08) -#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) -#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) -#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) -#define MCF548X_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PDDR_FBCS */ -#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x02) -#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x04) -#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x08) -#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) -#define MCF548X_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) - -/* Bit definitions and macros for MCF548X_GPIO_PDDR_DMA */ -#define MCF548X_GPIO_PDDR_DMA_PDDR_DMA0 (0x01) -#define MCF548X_GPIO_PDDR_DMA_PDDR_DMA1 (0x02) -#define MCF548X_GPIO_PDDR_DMA_PDDR_DMA2 (0x04) -#define MCF548X_GPIO_PDDR_DMA_PDDR_DMA3 (0x08) - -/* Bit definitions and macros for MCF548X_GPIO_PDDR_FEC0H */ -#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x01) -#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x02) -#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x04) -#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x08) -#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) -#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) -#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) -#define MCF548X_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PDDR_FEC0L */ -#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x01) -#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x02) -#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x04) -#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x08) -#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) -#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) -#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) -#define MCF548X_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PDDR_FEC1H */ -#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x01) -#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x02) -#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x04) -#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x08) -#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) -#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) -#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) -#define MCF548X_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PDDR_FEC1L */ -#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x01) -#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x02) -#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x04) -#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x08) -#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) -#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) -#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) -#define MCF548X_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PDDR_FECI2C */ -#define MCF548X_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) -#define MCF548X_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) -#define MCF548X_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) -#define MCF548X_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF548X_GPIO_PDDR_PCIBG */ -#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x01) -#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x02) -#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x04) -#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x08) -#define MCF548X_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) - -/* Bit definitions and macros for MCF548X_GPIO_PDDR_PCIBR */ -#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x01) -#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x02) -#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x04) -#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x08) -#define MCF548X_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) - -/* Bit definitions and macros for MCF548X_GPIO_PDDR_PSC3PSC2 */ -#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC20 (0x01) -#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC21 (0x02) -#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC22 (0x04) -#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC23 (0x08) -#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10) -#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20) -#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC26 (0x40) -#define MCF548X_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PDDR_PSC1PSC0 */ -#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC00 (0x01) -#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02) -#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC02 (0x04) -#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08) -#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC04 (0x10) -#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC05 (0x20) -#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC06 (0x40) -#define MCF548X_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PDDR_DSPI */ -#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x01) -#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x02) -#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x04) -#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x08) -#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) -#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) -#define MCF548X_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) - -/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FBCTL */ -#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x01) -#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x02) -#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x04) -#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x08) -#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) -#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) -#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) -#define MCF548X_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FBCS */ -#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x02) -#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x04) -#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x08) -#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) -#define MCF548X_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) - -/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_DMA */ -#define MCF548X_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x01) -#define MCF548X_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x02) -#define MCF548X_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x04) -#define MCF548X_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x08) - -/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FEC0H */ -#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x01) -#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x02) -#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x04) -#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x08) -#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) -#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) -#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) -#define MCF548X_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FEC0L */ -#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x01) -#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x02) -#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x04) -#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x08) -#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) -#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) -#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) -#define MCF548X_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FEC1H */ -#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x01) -#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x02) -#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x04) -#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x08) -#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) -#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) -#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) -#define MCF548X_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FEC1L */ -#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x01) -#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x02) -#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x04) -#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x08) -#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) -#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) -#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) -#define MCF548X_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_FECI2C */ -#define MCF548X_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) -#define MCF548X_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) -#define MCF548X_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) -#define MCF548X_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_PCIBG */ -#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x01) -#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x02) -#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x04) -#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x08) -#define MCF548X_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) - -/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_PCIBR */ -#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x01) -#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x02) -#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x04) -#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x08) -#define MCF548X_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) - -/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_PSC3PSC2 */ -#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC20 (0x01) -#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC21 (0x02) -#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC22 (0x04) -#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC23 (0x08) -#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10) -#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20) -#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC26 (0x40) -#define MCF548X_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_PSC1PSC0 */ -#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC00 (0x01) -#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02) -#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC02 (0x04) -#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08) -#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC04 (0x10) -#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC05 (0x20) -#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC06 (0x40) -#define MCF548X_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PPDSDR_DSPI */ -#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x01) -#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x02) -#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x04) -#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x08) -#define MCF548X_GPIO_PPDSDR_DSPI_PDDR_DSPI4 (0x10) -#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) -#define MCF548X_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) - -/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FBCTL */ -#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x01) -#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x02) -#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x04) -#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x08) -#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) -#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) -#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) -#define MCF548X_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FBCS */ -#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x02) -#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x04) -#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x08) -#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) -#define MCF548X_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) - -/* Bit definitions and macros for MCF548X_GPIO_PCLRR_DMA */ -#define MCF548X_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x01) -#define MCF548X_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x02) -#define MCF548X_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x04) -#define MCF548X_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x08) - -/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FEC0H */ -#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x01) -#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x02) -#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x04) -#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x08) -#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) -#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) -#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) -#define MCF548X_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FEC0L */ -#define MCF548X_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x01) -#define MCF548X_GPIO_PCLRR_FEC0L_PODR_FEC0L1 (0x02) -#define MCF548X_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x04) -#define MCF548X_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x08) -#define MCF548X_GPIO_PCLRR_FEC0L_PODR_FEC0L4 (0x10) -#define MCF548X_GPIO_PCLRR_FEC0L_PODR_FEC0L5 (0x20) -#define MCF548X_GPIO_PCLRR_FEC0L_PODR_FEC0L6 (0x40) -#define MCF548X_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FEC1H */ -#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x01) -#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x02) -#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x04) -#define MCF548X_GPIO_PCLRR_FEC1H_PODR_FEC1H3 (0x08) -#define MCF548X_GPIO_PCLRR_FEC1H_PODR_FEC1H4 (0x10) -#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) -#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) -#define MCF548X_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FEC1L */ -#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x01) -#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x02) -#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x04) -#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x08) -#define MCF548X_GPIO_PCLRR_FEC1L_PODR_FEC1L4 (0x10) -#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) -#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) -#define MCF548X_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PCLRR_FECI2C */ -#define MCF548X_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) -#define MCF548X_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) -#define MCF548X_GPIO_PCLRR_FECI2C_PODR_FECI2C2 (0x04) -#define MCF548X_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF548X_GPIO_PCLRR_PCIBG */ -#define MCF548X_GPIO_PCLRR_PCIBG_PODR_PCIBG0 (0x01) -#define MCF548X_GPIO_PCLRR_PCIBG_PODR_PCIBG1 (0x02) -#define MCF548X_GPIO_PCLRR_PCIBG_PODR_PCIBG2 (0x04) -#define MCF548X_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x08) -#define MCF548X_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) - -/* Bit definitions and macros for MCF548X_GPIO_PCLRR_PCIBR */ -#define MCF548X_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x01) -#define MCF548X_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x02) -#define MCF548X_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x04) -#define MCF548X_GPIO_PCLRR_PCIBR_PODR_PCIBR3 (0x08) -#define MCF548X_GPIO_PCLRR_PCIBR_PODR_PCIBR4 (0x10) - -/* Bit definitions and macros for MCF548X_GPIO_PCLRR_PSC3PSC2 */ -#define MCF548X_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC20 (0x01) -#define MCF548X_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC21 (0x02) -#define MCF548X_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC22 (0x04) -#define MCF548X_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC23 (0x08) -#define MCF548X_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC24 (0x10) -#define MCF548X_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC25 (0x20) -#define MCF548X_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC26 (0x40) -#define MCF548X_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PCLRR_PSC1PSC0 */ -#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC00 (0x01) -#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC01 (0x02) -#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC02 (0x04) -#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC03 (0x08) -#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC04 (0x10) -#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC05 (0x20) -#define MCF548X_GPIO_PCLRR_PSC1PSC0_PODR_PSC1PSC06 (0x40) -#define MCF548X_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF548X_GPIO_PCLRR_DSPI */ -#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x01) -#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x02) -#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x04) -#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x08) -#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) -#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) -#define MCF548X_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) - -/* Bit definitions and macros for MCF548X_GPIO_PAR_FBCTL */ -#define MCF548X_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0) -#define MCF548X_GPIO_PAR_FBCTL_PAR_TA (0x0004) -#define MCF548X_GPIO_PAR_FBCTL_PAR_RWB(x) (((x)&0x0003)<<4) -#define MCF548X_GPIO_PAR_FBCTL_PAR_OE (0x0040) -#define MCF548X_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100) -#define MCF548X_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400) -#define MCF548X_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000) -#define MCF548X_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000) -#define MCF548X_GPIO_PAR_FBCTL_PAR_TS_GPIO (0) -#define MCF548X_GPIO_PAR_FBCTL_PAR_TS_TBST (2) -#define MCF548X_GPIO_PAR_FBCTL_PAR_TS_TS (3) -#define MCF548X_GPIO_PAR_FBCTL_PAR_RWB_GPIO (0x0000) -#define MCF548X_GPIO_PAR_FBCTL_PAR_RWB_TBST (0x0020) -#define MCF548X_GPIO_PAR_FBCTL_PAR_RWB_RWB (0x0030) - -/* Bit definitions and macros for MCF548X_GPIO_PAR_FBCS */ -#define MCF548X_GPIO_PAR_FBCS_PAR_CS1 (0x02) -#define MCF548X_GPIO_PAR_FBCS_PAR_CS2 (0x04) -#define MCF548X_GPIO_PAR_FBCS_PAR_CS3 (0x08) -#define MCF548X_GPIO_PAR_FBCS_PAR_CS4 (0x10) -#define MCF548X_GPIO_PAR_FBCS_PAR_CS5 (0x20) - -/* Bit definitions and macros for MCF548X_GPIO_PAR_DMA */ -#define MCF548X_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0) -#define MCF548X_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2) -#define MCF548X_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4) -#define MCF548X_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6) -#define MCF548X_GPIO_PAR_DMA_PAR_DACKx_GPIO (0) -#define MCF548X_GPIO_PAR_DMA_PAR_DACKx_TOUT (2) -#define MCF548X_GPIO_PAR_DMA_PAR_DACKx_DACK (3) -#define MCF548X_GPIO_PAR_DMA_PAR_DREQx_GPIO (0) -#define MCF548X_GPIO_PAR_DMA_PAR_DREQx_TIN (2) -#define MCF548X_GPIO_PAR_DMA_PAR_DREQx_DREQ (3) - -/* Bit definitions and macros for MCF548X_GPIO_PAR_FECI2CIRQ */ -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080) -#define MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0) - -/* Bit definitions and macros for MCF548X_GPIO_PAR_PCIBG */ -#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0) -#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2) -#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4) -#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6) -#define MCF548X_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8) - -/* Bit definitions and macros for MCF548X_GPIO_PAR_PCIBR */ -#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBG0(x) (((x)&0x0003)<<0) -#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBG1(x) (((x)&0x0003)<<2) -#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBG2(x) (((x)&0x0003)<<4) -#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBG3(x) (((x)&0x0003)<<6) -#define MCF548X_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8) - -/* Bit definitions and macros for MCF548X_GPIO_PAR_PSC3 */ -#define MCF548X_GPIO_PAR_PSC3_PAR_TXD3 (0x04) -#define MCF548X_GPIO_PAR_PSC3_PAR_RXD3 (0x08) -#define MCF548X_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4) -#define MCF548X_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6) -#define MCF548X_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00) -#define MCF548X_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80) -#define MCF548X_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0) -#define MCF548X_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00) -#define MCF548X_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20) -#define MCF548X_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30) -#define MCF548X_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40) - -/* Bit definitions and macros for MCF548X_GPIO_PAR_PSC2 */ -#define MCF548X_GPIO_PAR_PSC2_PAR_TXD2 (0x04) -#define MCF548X_GPIO_PAR_PSC2_PAR_RXD2 (0x08) -#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4) -#define MCF548X_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6) -#define MCF548X_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00) -#define MCF548X_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80) -#define MCF548X_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0) -#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00) -#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10) -#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20) -#define MCF548X_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30) - -/* Bit definitions and macros for MCF548X_GPIO_PAR_PSC1 */ -#define MCF548X_GPIO_PAR_PSC1_PAR_TXD1 (0x04) -#define MCF548X_GPIO_PAR_PSC1_PAR_RXD1 (0x08) -#define MCF548X_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4) -#define MCF548X_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6) -#define MCF548X_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00) -#define MCF548X_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80) -#define MCF548X_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0) -#define MCF548X_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00) -#define MCF548X_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20) -#define MCF548X_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30) - -/* Bit definitions and macros for MCF548X_GPIO_PAR_PSC0 */ -#define MCF548X_GPIO_PAR_PSC0_PAR_TXD0 (0x04) -#define MCF548X_GPIO_PAR_PSC0_PAR_RXD0 (0x08) -#define MCF548X_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4) -#define MCF548X_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6) -#define MCF548X_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00) -#define MCF548X_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80) -#define MCF548X_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0) -#define MCF548X_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00) -#define MCF548X_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20) -#define MCF548X_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30) - -/* Bit definitions and macros for MCF548X_GPIO_PAR_DSPI */ -#define MCF548X_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0) -#define MCF548X_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2) -#define MCF548X_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS5 (0x1000) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080) -#define MCF548X_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0) -#define MCF548X_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000) -#define MCF548X_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010) -#define MCF548X_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020) -#define MCF548X_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030) -#define MCF548X_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000) -#define MCF548X_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008) -#define MCF548X_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C) -#define MCF548X_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000) -#define MCF548X_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002) -#define MCF548X_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003) - -/* Bit definitions and macros for MCF548X_GPIO_PAR_TIMER */ -#define MCF548X_GPIO_PAR_TIMER_PAR_TOUT2 (0x01) -#define MCF548X_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1) -#define MCF548X_GPIO_PAR_TIMER_PAR_TOUT3 (0x08) -#define MCF548X_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4) -#define MCF548X_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00) -#define MCF548X_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20) -#define MCF548X_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30) -#define MCF548X_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00) -#define MCF548X_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04) -#define MCF548X_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06) - -/********************************************************************* -* -* General Purpose Timers (GPT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_GPT_GMS0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000800))) -#define MCF548X_GPT_GCIR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000804))) -#define MCF548X_GPT_GPWM0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000808))) -#define MCF548X_GPT_GSR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00080C))) -#define MCF548X_GPT_GMS1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000810))) -#define MCF548X_GPT_GCIR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000814))) -#define MCF548X_GPT_GPWM1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000818))) -#define MCF548X_GPT_GSR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00081C))) -#define MCF548X_GPT_GMS2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000820))) -#define MCF548X_GPT_GCIR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000824))) -#define MCF548X_GPT_GPWM2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000828))) -#define MCF548X_GPT_GSR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00082C))) -#define MCF548X_GPT_GMS3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000830))) -#define MCF548X_GPT_GCIR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000834))) -#define MCF548X_GPT_GPWM3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000838))) -#define MCF548X_GPT_GSR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00083C))) -#define MCF548X_GPT_GMS(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000800U+((x)*0x010)))) -#define MCF548X_GPT_GCIR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000804U+((x)*0x010)))) -#define MCF548X_GPT_GPWM(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000808U+((x)*0x010)))) -#define MCF548X_GPT_GSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00080CU+((x)*0x010)))) - -/* Bit definitions and macros for MCF548X_GPT_GMS */ -#define MCF548X_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) -#define MCF548X_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) -#define MCF548X_GPT_GMS_IEN (0x00000100) -#define MCF548X_GPT_GMS_OD (0x00000200) -#define MCF548X_GPT_GMS_SC (0x00000400) -#define MCF548X_GPT_GMS_CE (0x00001000) -#define MCF548X_GPT_GMS_WDEN (0x00008000) -#define MCF548X_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) -#define MCF548X_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) -#define MCF548X_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) -#define MCF548X_GPT_GMS_OCT_FRCLOW (0x00000000) -#define MCF548X_GPT_GMS_OCT_PULSEHI (0x00100000) -#define MCF548X_GPT_GMS_OCT_PULSELO (0x00200000) -#define MCF548X_GPT_GMS_OCT_TOGGLE (0x00300000) -#define MCF548X_GPT_GMS_ICT_ANY (0x00000000) -#define MCF548X_GPT_GMS_ICT_RISE (0x00010000) -#define MCF548X_GPT_GMS_ICT_FALL (0x00020000) -#define MCF548X_GPT_GMS_ICT_PULSE (0x00030000) -#define MCF548X_GPT_GMS_GPIO_INPUT (0x00000000) -#define MCF548X_GPT_GMS_GPIO_OUTLO (0x00000020) -#define MCF548X_GPT_GMS_GPIO_OUTHI (0x00000030) -#define MCF548X_GPT_GMS_TMS_DISABLE (0x00000000) -#define MCF548X_GPT_GMS_TMS_INCAPT (0x00000001) -#define MCF548X_GPT_GMS_TMS_OUTCAPT (0x00000002) -#define MCF548X_GPT_GMS_TMS_PWM (0x00000003) -#define MCF548X_GPT_GMS_TMS_GPIO (0x00000004) - -/* Bit definitions and macros for MCF548X_GPT_GCIR */ -#define MCF548X_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF548X_GPT_GPWM */ -#define MCF548X_GPT_GPWM_LOAD (0x00000001) -#define MCF548X_GPT_GPWM_PWMOP (0x00000100) -#define MCF548X_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF548X_GPT_GSR */ -#define MCF548X_GPT_GSR_CAPT (0x00000001) -#define MCF548X_GPT_GSR_COMP (0x00000002) -#define MCF548X_GPT_GSR_PWMP (0x00000004) -#define MCF548X_GPT_GSR_TEXP (0x00000008) -#define MCF548X_GPT_GSR_PIN (0x00000100) -#define MCF548X_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) -#define MCF548X_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) - - -/********************************************************************* -* -* I2C Module (I2C) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_I2C_I2AR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F00))) -#define MCF548X_I2C_I2FDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F04))) -#define MCF548X_I2C_I2CR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F08))) -#define MCF548X_I2C_I2SR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F0C))) -#define MCF548X_I2C_I2DR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F10))) -#define MCF548X_I2C_I2ICR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008F20))) - -/* Bit definitions and macros for MCF548X_I2C_I2AR */ -#define MCF548X_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF548X_I2C_I2FDR */ -#define MCF548X_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) - -/* Bit definitions and macros for MCF548X_I2C_I2CR */ -#define MCF548X_I2C_I2CR_RSTA (0x04) -#define MCF548X_I2C_I2CR_TXAK (0x08) -#define MCF548X_I2C_I2CR_MTX (0x10) -#define MCF548X_I2C_I2CR_MSTA (0x20) -#define MCF548X_I2C_I2CR_IIEN (0x40) -#define MCF548X_I2C_I2CR_IEN (0x80) - -/* Bit definitions and macros for MCF548X_I2C_I2SR */ -#define MCF548X_I2C_I2SR_RXAK (0x01) -#define MCF548X_I2C_I2SR_IIF (0x02) -#define MCF548X_I2C_I2SR_SRW (0x04) -#define MCF548X_I2C_I2SR_IAL (0x10) -#define MCF548X_I2C_I2SR_IBB (0x20) -#define MCF548X_I2C_I2SR_IAAS (0x40) -#define MCF548X_I2C_I2SR_ICF (0x80) - -/* Bit definitions and macros for MCF548X_I2C_I2ICR */ -#define MCF548X_I2C_I2ICR_IE (0x01) -#define MCF548X_I2C_I2ICR_RE (0x02) -#define MCF548X_I2C_I2ICR_TE (0x04) -#define MCF548X_I2C_I2ICR_BNBE (0x08) - -/********************************************************************* -* -* Interrupt Controller (INTC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_INTC_IPRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000700))) -#define MCF548X_INTC_IPRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000704))) -#define MCF548X_INTC_IMRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000708))) -#define MCF548X_INTC_IMRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00070C))) -#define MCF548X_INTC_INTFRCH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000710))) -#define MCF548X_INTC_INTFRCL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000714))) -#define MCF548X_INTC_IRLR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000718))) -#define MCF548X_INTC_IACKLPR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000719))) -#define MCF548X_INTC_ICR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000740))) -#define MCF548X_INTC_ICR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000741))) -#define MCF548X_INTC_ICR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000742))) -#define MCF548X_INTC_ICR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000743))) -#define MCF548X_INTC_ICR4 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000744))) -#define MCF548X_INTC_ICR5 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000745))) -#define MCF548X_INTC_ICR6 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000746))) -#define MCF548X_INTC_ICR7 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000747))) -#define MCF548X_INTC_ICR8 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000748))) -#define MCF548X_INTC_ICR9 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000749))) -#define MCF548X_INTC_ICR10 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074A))) -#define MCF548X_INTC_ICR11 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074B))) -#define MCF548X_INTC_ICR12 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074C))) -#define MCF548X_INTC_ICR13 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074D))) -#define MCF548X_INTC_ICR14 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074E))) -#define MCF548X_INTC_ICR15 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00074F))) -#define MCF548X_INTC_ICR16 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000750))) -#define MCF548X_INTC_ICR17 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000751))) -#define MCF548X_INTC_ICR18 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000752))) -#define MCF548X_INTC_ICR19 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000753))) -#define MCF548X_INTC_ICR20 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000754))) -#define MCF548X_INTC_ICR21 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000755))) -#define MCF548X_INTC_ICR22 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000756))) -#define MCF548X_INTC_ICR23 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000757))) -#define MCF548X_INTC_ICR24 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000758))) -#define MCF548X_INTC_ICR25 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000759))) -#define MCF548X_INTC_ICR26 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075A))) -#define MCF548X_INTC_ICR27 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075B))) -#define MCF548X_INTC_ICR28 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075C))) -#define MCF548X_INTC_ICR29 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075D))) -#define MCF548X_INTC_ICR30 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075E))) -#define MCF548X_INTC_ICR31 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00075F))) -#define MCF548X_INTC_ICR32 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000760))) -#define MCF548X_INTC_ICR33 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000761))) -#define MCF548X_INTC_ICR34 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000762))) -#define MCF548X_INTC_ICR35 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000763))) -#define MCF548X_INTC_ICR36 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000764))) -#define MCF548X_INTC_ICR37 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000765))) -#define MCF548X_INTC_ICR38 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000766))) -#define MCF548X_INTC_ICR39 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000767))) -#define MCF548X_INTC_ICR40 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000768))) -#define MCF548X_INTC_ICR41 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000769))) -#define MCF548X_INTC_ICR42 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076A))) -#define MCF548X_INTC_ICR43 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076B))) -#define MCF548X_INTC_ICR44 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076C))) -#define MCF548X_INTC_ICR45 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076D))) -#define MCF548X_INTC_ICR46 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076E))) -#define MCF548X_INTC_ICR47 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00076F))) -#define MCF548X_INTC_ICR48 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000770))) -#define MCF548X_INTC_ICR49 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000771))) -#define MCF548X_INTC_ICR50 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000772))) -#define MCF548X_INTC_ICR51 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000773))) -#define MCF548X_INTC_ICR52 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000774))) -#define MCF548X_INTC_ICR53 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000775))) -#define MCF548X_INTC_ICR54 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000776))) -#define MCF548X_INTC_ICR55 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000777))) -#define MCF548X_INTC_ICR56 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000778))) -#define MCF548X_INTC_ICR57 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000779))) -#define MCF548X_INTC_ICR58 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077A))) -#define MCF548X_INTC_ICR59 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077B))) -#define MCF548X_INTC_ICR60 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077C))) -#define MCF548X_INTC_ICR61 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077D))) -#define MCF548X_INTC_ICR62 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077E))) -#define MCF548X_INTC_ICR63 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00077F))) -#define MCF548X_INTC_ICRn(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x000740U+((x)*0x001)))) -#define MCF548X_INTC_SWIACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007E0))) -#define MCF548X_INTC_L1IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007E4))) -#define MCF548X_INTC_L2IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007E8))) -#define MCF548X_INTC_L3IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007EC))) -#define MCF548X_INTC_L4IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007F0))) -#define MCF548X_INTC_L5IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007F4))) -#define MCF548X_INTC_L6IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007F8))) -#define MCF548X_INTC_L7IACK (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007FC))) -#define MCF548X_INTC_LnIACK(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x0007E4U+((x)*0x004)))) - -/* Bit definitions and macros for MCF548X_INTC_IPRH */ -#define MCF548X_INTC_IPRH_INT32 (0x00000001) -#define MCF548X_INTC_IPRH_INT33 (0x00000002) -#define MCF548X_INTC_IPRH_INT34 (0x00000004) -#define MCF548X_INTC_IPRH_INT35 (0x00000008) -#define MCF548X_INTC_IPRH_INT36 (0x00000010) -#define MCF548X_INTC_IPRH_INT37 (0x00000020) -#define MCF548X_INTC_IPRH_INT38 (0x00000040) -#define MCF548X_INTC_IPRH_INT39 (0x00000080) -#define MCF548X_INTC_IPRH_INT40 (0x00000100) -#define MCF548X_INTC_IPRH_INT41 (0x00000200) -#define MCF548X_INTC_IPRH_INT42 (0x00000400) -#define MCF548X_INTC_IPRH_INT43 (0x00000800) -#define MCF548X_INTC_IPRH_INT44 (0x00001000) -#define MCF548X_INTC_IPRH_INT45 (0x00002000) -#define MCF548X_INTC_IPRH_INT46 (0x00004000) -#define MCF548X_INTC_IPRH_INT47 (0x00008000) -#define MCF548X_INTC_IPRH_INT48 (0x00010000) -#define MCF548X_INTC_IPRH_INT49 (0x00020000) -#define MCF548X_INTC_IPRH_INT50 (0x00040000) -#define MCF548X_INTC_IPRH_INT51 (0x00080000) -#define MCF548X_INTC_IPRH_INT52 (0x00100000) -#define MCF548X_INTC_IPRH_INT53 (0x00200000) -#define MCF548X_INTC_IPRH_INT54 (0x00400000) -#define MCF548X_INTC_IPRH_INT55 (0x00800000) -#define MCF548X_INTC_IPRH_INT56 (0x01000000) -#define MCF548X_INTC_IPRH_INT57 (0x02000000) -#define MCF548X_INTC_IPRH_INT58 (0x04000000) -#define MCF548X_INTC_IPRH_INT59 (0x08000000) -#define MCF548X_INTC_IPRH_INT60 (0x10000000) -#define MCF548X_INTC_IPRH_INT61 (0x20000000) -#define MCF548X_INTC_IPRH_INT62 (0x40000000) -#define MCF548X_INTC_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF548X_INTC_IPRL */ -#define MCF548X_INTC_IPRL_INT1 (0x00000002) -#define MCF548X_INTC_IPRL_INT2 (0x00000004) -#define MCF548X_INTC_IPRL_INT3 (0x00000008) -#define MCF548X_INTC_IPRL_INT4 (0x00000010) -#define MCF548X_INTC_IPRL_INT5 (0x00000020) -#define MCF548X_INTC_IPRL_INT6 (0x00000040) -#define MCF548X_INTC_IPRL_INT7 (0x00000080) -#define MCF548X_INTC_IPRL_INT8 (0x00000100) -#define MCF548X_INTC_IPRL_INT9 (0x00000200) -#define MCF548X_INTC_IPRL_INT10 (0x00000400) -#define MCF548X_INTC_IPRL_INT11 (0x00000800) -#define MCF548X_INTC_IPRL_INT12 (0x00001000) -#define MCF548X_INTC_IPRL_INT13 (0x00002000) -#define MCF548X_INTC_IPRL_INT14 (0x00004000) -#define MCF548X_INTC_IPRL_INT15 (0x00008000) -#define MCF548X_INTC_IPRL_INT16 (0x00010000) -#define MCF548X_INTC_IPRL_INT17 (0x00020000) -#define MCF548X_INTC_IPRL_INT18 (0x00040000) -#define MCF548X_INTC_IPRL_INT19 (0x00080000) -#define MCF548X_INTC_IPRL_INT20 (0x00100000) -#define MCF548X_INTC_IPRL_INT21 (0x00200000) -#define MCF548X_INTC_IPRL_INT22 (0x00400000) -#define MCF548X_INTC_IPRL_INT23 (0x00800000) -#define MCF548X_INTC_IPRL_INT24 (0x01000000) -#define MCF548X_INTC_IPRL_INT25 (0x02000000) -#define MCF548X_INTC_IPRL_INT26 (0x04000000) -#define MCF548X_INTC_IPRL_INT27 (0x08000000) -#define MCF548X_INTC_IPRL_INT28 (0x10000000) -#define MCF548X_INTC_IPRL_INT29 (0x20000000) -#define MCF548X_INTC_IPRL_INT30 (0x40000000) -#define MCF548X_INTC_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF548X_INTC_IMRH */ -#define MCF548X_INTC_IMRH_INT_MASK32 (0x00000001) -#define MCF548X_INTC_IMRH_INT_MASK33 (0x00000002) -#define MCF548X_INTC_IMRH_INT_MASK34 (0x00000004) -#define MCF548X_INTC_IMRH_INT_MASK35 (0x00000008) -#define MCF548X_INTC_IMRH_INT_MASK36 (0x00000010) -#define MCF548X_INTC_IMRH_INT_MASK37 (0x00000020) -#define MCF548X_INTC_IMRH_INT_MASK38 (0x00000040) -#define MCF548X_INTC_IMRH_INT_MASK39 (0x00000080) -#define MCF548X_INTC_IMRH_INT_MASK40 (0x00000100) -#define MCF548X_INTC_IMRH_INT_MASK41 (0x00000200) -#define MCF548X_INTC_IMRH_INT_MASK42 (0x00000400) -#define MCF548X_INTC_IMRH_INT_MASK43 (0x00000800) -#define MCF548X_INTC_IMRH_INT_MASK44 (0x00001000) -#define MCF548X_INTC_IMRH_INT_MASK45 (0x00002000) -#define MCF548X_INTC_IMRH_INT_MASK46 (0x00004000) -#define MCF548X_INTC_IMRH_INT_MASK47 (0x00008000) -#define MCF548X_INTC_IMRH_INT_MASK48 (0x00010000) -#define MCF548X_INTC_IMRH_INT_MASK49 (0x00020000) -#define MCF548X_INTC_IMRH_INT_MASK50 (0x00040000) -#define MCF548X_INTC_IMRH_INT_MASK51 (0x00080000) -#define MCF548X_INTC_IMRH_INT_MASK52 (0x00100000) -#define MCF548X_INTC_IMRH_INT_MASK53 (0x00200000) -#define MCF548X_INTC_IMRH_INT_MASK54 (0x00400000) -#define MCF548X_INTC_IMRH_INT_MASK55 (0x00800000) -#define MCF548X_INTC_IMRH_INT_MASK56 (0x01000000) -#define MCF548X_INTC_IMRH_INT_MASK57 (0x02000000) -#define MCF548X_INTC_IMRH_INT_MASK58 (0x04000000) -#define MCF548X_INTC_IMRH_INT_MASK59 (0x08000000) -#define MCF548X_INTC_IMRH_INT_MASK60 (0x10000000) -#define MCF548X_INTC_IMRH_INT_MASK61 (0x20000000) -#define MCF548X_INTC_IMRH_INT_MASK62 (0x40000000) -#define MCF548X_INTC_IMRH_INT_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF548X_INTC_IMRL */ -#define MCF548X_INTC_IMRL_MASKALL (0x00000001) -#define MCF548X_INTC_IMRL_INT_MASK1 (0x00000002) -#define MCF548X_INTC_IMRL_INT_MASK2 (0x00000004) -#define MCF548X_INTC_IMRL_INT_MASK3 (0x00000008) -#define MCF548X_INTC_IMRL_INT_MASK4 (0x00000010) -#define MCF548X_INTC_IMRL_INT_MASK5 (0x00000020) -#define MCF548X_INTC_IMRL_INT_MASK6 (0x00000040) -#define MCF548X_INTC_IMRL_INT_MASK7 (0x00000080) -#define MCF548X_INTC_IMRL_INT_MASK8 (0x00000100) -#define MCF548X_INTC_IMRL_INT_MASK9 (0x00000200) -#define MCF548X_INTC_IMRL_INT_MASK10 (0x00000400) -#define MCF548X_INTC_IMRL_INT_MASK11 (0x00000800) -#define MCF548X_INTC_IMRL_INT_MASK12 (0x00001000) -#define MCF548X_INTC_IMRL_INT_MASK13 (0x00002000) -#define MCF548X_INTC_IMRL_INT_MASK14 (0x00004000) -#define MCF548X_INTC_IMRL_INT_MASK15 (0x00008000) -#define MCF548X_INTC_IMRL_INT_MASK16 (0x00010000) -#define MCF548X_INTC_IMRL_INT_MASK17 (0x00020000) -#define MCF548X_INTC_IMRL_INT_MASK18 (0x00040000) -#define MCF548X_INTC_IMRL_INT_MASK19 (0x00080000) -#define MCF548X_INTC_IMRL_INT_MASK20 (0x00100000) -#define MCF548X_INTC_IMRL_INT_MASK21 (0x00200000) -#define MCF548X_INTC_IMRL_INT_MASK22 (0x00400000) -#define MCF548X_INTC_IMRL_INT_MASK23 (0x00800000) -#define MCF548X_INTC_IMRL_INT_MASK24 (0x01000000) -#define MCF548X_INTC_IMRL_INT_MASK25 (0x02000000) -#define MCF548X_INTC_IMRL_INT_MASK26 (0x04000000) -#define MCF548X_INTC_IMRL_INT_MASK27 (0x08000000) -#define MCF548X_INTC_IMRL_INT_MASK28 (0x10000000) -#define MCF548X_INTC_IMRL_INT_MASK29 (0x20000000) -#define MCF548X_INTC_IMRL_INT_MASK30 (0x40000000) -#define MCF548X_INTC_IMRL_INT_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF548X_INTC_INTFRCH */ -#define MCF548X_INTC_INTFRCH_INTFRC32 (0x00000001) -#define MCF548X_INTC_INTFRCH_INTFRC33 (0x00000002) -#define MCF548X_INTC_INTFRCH_INTFRC34 (0x00000004) -#define MCF548X_INTC_INTFRCH_INTFRC35 (0x00000008) -#define MCF548X_INTC_INTFRCH_INTFRC36 (0x00000010) -#define MCF548X_INTC_INTFRCH_INTFRC37 (0x00000020) -#define MCF548X_INTC_INTFRCH_INTFRC38 (0x00000040) -#define MCF548X_INTC_INTFRCH_INTFRC39 (0x00000080) -#define MCF548X_INTC_INTFRCH_INTFRC40 (0x00000100) -#define MCF548X_INTC_INTFRCH_INTFRC41 (0x00000200) -#define MCF548X_INTC_INTFRCH_INTFRC42 (0x00000400) -#define MCF548X_INTC_INTFRCH_INTFRC43 (0x00000800) -#define MCF548X_INTC_INTFRCH_INTFRC44 (0x00001000) -#define MCF548X_INTC_INTFRCH_INTFRC45 (0x00002000) -#define MCF548X_INTC_INTFRCH_INTFRC46 (0x00004000) -#define MCF548X_INTC_INTFRCH_INTFRC47 (0x00008000) -#define MCF548X_INTC_INTFRCH_INTFRC48 (0x00010000) -#define MCF548X_INTC_INTFRCH_INTFRC49 (0x00020000) -#define MCF548X_INTC_INTFRCH_INTFRC50 (0x00040000) -#define MCF548X_INTC_INTFRCH_INTFRC51 (0x00080000) -#define MCF548X_INTC_INTFRCH_INTFRC52 (0x00100000) -#define MCF548X_INTC_INTFRCH_INTFRC53 (0x00200000) -#define MCF548X_INTC_INTFRCH_INTFRC54 (0x00400000) -#define MCF548X_INTC_INTFRCH_INTFRC55 (0x00800000) -#define MCF548X_INTC_INTFRCH_INTFRC56 (0x01000000) -#define MCF548X_INTC_INTFRCH_INTFRC57 (0x02000000) -#define MCF548X_INTC_INTFRCH_INTFRC58 (0x04000000) -#define MCF548X_INTC_INTFRCH_INTFRC59 (0x08000000) -#define MCF548X_INTC_INTFRCH_INTFRC60 (0x10000000) -#define MCF548X_INTC_INTFRCH_INTFRC61 (0x20000000) -#define MCF548X_INTC_INTFRCH_INTFRC62 (0x40000000) -#define MCF548X_INTC_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF548X_INTC_INTFRCL */ -#define MCF548X_INTC_INTFRCL_INTFRC1 (0x00000002) -#define MCF548X_INTC_INTFRCL_INTFRC2 (0x00000004) -#define MCF548X_INTC_INTFRCL_INTFRC3 (0x00000008) -#define MCF548X_INTC_INTFRCL_INTFRC4 (0x00000010) -#define MCF548X_INTC_INTFRCL_INTFRC5 (0x00000020) -#define MCF548X_INTC_INTFRCL_INT6 (0x00000040) -#define MCF548X_INTC_INTFRCL_INT7 (0x00000080) -#define MCF548X_INTC_INTFRCL_INT8 (0x00000100) -#define MCF548X_INTC_INTFRCL_INT9 (0x00000200) -#define MCF548X_INTC_INTFRCL_INT10 (0x00000400) -#define MCF548X_INTC_INTFRCL_INTFRC11 (0x00000800) -#define MCF548X_INTC_INTFRCL_INTFRC12 (0x00001000) -#define MCF548X_INTC_INTFRCL_INTFRC13 (0x00002000) -#define MCF548X_INTC_INTFRCL_INTFRC14 (0x00004000) -#define MCF548X_INTC_INTFRCL_INT15 (0x00008000) -#define MCF548X_INTC_INTFRCL_INTFRC16 (0x00010000) -#define MCF548X_INTC_INTFRCL_INTFRC17 (0x00020000) -#define MCF548X_INTC_INTFRCL_INTFRC18 (0x00040000) -#define MCF548X_INTC_INTFRCL_INTFRC19 (0x00080000) -#define MCF548X_INTC_INTFRCL_INTFRC20 (0x00100000) -#define MCF548X_INTC_INTFRCL_INTFRC21 (0x00200000) -#define MCF548X_INTC_INTFRCL_INTFRC22 (0x00400000) -#define MCF548X_INTC_INTFRCL_INTFRC23 (0x00800000) -#define MCF548X_INTC_INTFRCL_INTFRC24 (0x01000000) -#define MCF548X_INTC_INTFRCL_INTFRC25 (0x02000000) -#define MCF548X_INTC_INTFRCL_INTFRC26 (0x04000000) -#define MCF548X_INTC_INTFRCL_INTFRC27 (0x08000000) -#define MCF548X_INTC_INTFRCL_INTFRC28 (0x10000000) -#define MCF548X_INTC_INTFRCL_INTFRC29 (0x20000000) -#define MCF548X_INTC_INTFRCL_INTFRC30 (0x40000000) -#define MCF548X_INTC_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF548X_INTC_IRLR */ -#define MCF548X_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF548X_INTC_IACKLPR */ -#define MCF548X_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF548X_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF548X_INTC_ICRn */ -#define MCF548X_INTC_ICRn_IP(x) (((x)&0x07)<<0) -#define MCF548X_INTC_ICRn_IL(x) (((x)&0x07)<<3) - - -/********************************************************************* -* -* SDRAM Controller (SDRAMC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_SDRAMC_SDRAMDS (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000004))) -#define MCF548X_SDRAMC_CS0CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000020))) -#define MCF548X_SDRAMC_CS1CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000024))) -#define MCF548X_SDRAMC_CS2CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000028))) -#define MCF548X_SDRAMC_CS3CFG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00002C))) -#define MCF548X_SDRAMC_CSnCFG(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000020U+((x)*0x004)))) -#define MCF548X_SDRAMC_SDMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000100))) -#define MCF548X_SDRAMC_SDCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000104))) -#define MCF548X_SDRAMC_SDCFG1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000108))) -#define MCF548X_SDRAMC_SDCFG2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00010C))) - -/* Bit definitions and macros for MCF548X_SDRAMC_SDRAMDS */ -#define MCF548X_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x00000003)<<0) -#define MCF548X_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x00000003)<<2) -#define MCF548X_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x00000003)<<4) -#define MCF548X_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x00000003)<<6) -#define MCF548X_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x00000003)<<8) -#define MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA (0x02) -#define MCF548X_SDRAMC_SDRAMDS_DRIVE_16MA (0x01) -#define MCF548X_SDRAMC_SDRAMDS_DRIVE_24MA (0x00) -#define MCF548X_SDRAMC_SDRAMDS_DRIVE_NONE (0x03) - -/* Bit definitions and macros for MCF548X_SDRAMC_CSnCFG */ -#define MCF548X_SDRAMC_CSnCFG_CSSZ(x) (((x)&0x0000001F)<<0) -#define MCF548X_SDRAMC_CSnCFG_CSBA(x) (((x)&0x00000FFF)<<20) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_DIABLE (0x00000000) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_1MBYTE (0x00000013) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_2MBYTE (0x00000014) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_4MBYTE (0x00000015) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_8MBYTE (0x00000016) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_16MBYTE (0x00000017) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_32MBYTE (0x00000018) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_64MBYTE (0x00000019) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_128MBYTE (0x0000001A) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_256MBYTE (0x0000001B) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_512MBYTE (0x0000001C) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_1GBYTE (0x0000001D) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_2GBYTE (0x0000001E) -#define MCF548X_SDRAMC_CSnCFG_CSSZ_4GBYTE (0x0000001F) - -/* Bit definitions and macros for MCF548X_SDRAMC_SDMR */ -#define MCF548X_SDRAMC_SDMR_CMD (0x00010000) -#define MCF548X_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) -#define MCF548X_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) -#define MCF548X_SDRAMC_SDMR_BNKAD_LMR (0x00000000) -#define MCF548X_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) - -/* Bit definitions and macros for MCF548X_SDRAMC_SDCR */ -#define MCF548X_SDRAMC_SDCR_IPALL (0x00000002) -#define MCF548X_SDRAMC_SDCR_IREF (0x00000004) -#define MCF548X_SDRAMC_SDCR_BUFF (0x00000010) -#define MCF548X_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) -#define MCF548X_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) -#define MCF548X_SDRAMC_SDCR_DRIVE (0x00400000) -#define MCF548X_SDRAMC_SDCR_AP (0x00800000) -#define MCF548X_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) -#define MCF548X_SDRAMC_SDCR_REF (0x10000000) -#define MCF548X_SDRAMC_SDCR_DDR (0x20000000) -#define MCF548X_SDRAMC_SDCR_CKE (0x40000000) -#define MCF548X_SDRAMC_SDCR_MODE_EN (0x80000000) - -/* Bit definitions and macros for MCF548X_SDRAMC_SDCFG1 */ -#define MCF548X_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) -#define MCF548X_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) -#define MCF548X_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) -#define MCF548X_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) -#define MCF548X_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) -#define MCF548X_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) -#define MCF548X_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF548X_SDRAMC_SDCFG2 */ -#define MCF548X_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) -#define MCF548X_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) -#define MCF548X_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) -#define MCF548X_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) - -/********************************************************************* -* -* Integrated Security Engine (SEC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_SEC_EUACRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021000))) -#define MCF548X_SEC_EUACRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021004))) -#define MCF548X_SEC_EUASRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021028))) -#define MCF548X_SEC_EUASRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02102C))) -#define MCF548X_SEC_SIMRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021008))) -#define MCF548X_SEC_SIMRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02100C))) -#define MCF548X_SEC_SISRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021010))) -#define MCF548X_SEC_SISRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021014))) -#define MCF548X_SEC_SICRH (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021018))) -#define MCF548X_SEC_SICRL (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02101C))) -#define MCF548X_SEC_SIDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021020))) -#define MCF548X_SEC_SMCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021030))) -#define MCF548X_SEC_MEAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x021038))) -#define MCF548X_SEC_CCCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02200C))) -#define MCF548X_SEC_CCCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02300C))) -#define MCF548X_SEC_CCPSRH0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x022010))) -#define MCF548X_SEC_CCPSRH1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x023010))) -#define MCF548X_SEC_CCPSRL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x022014))) -#define MCF548X_SEC_CCPSRL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x023014))) -#define MCF548X_SEC_CDPR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x022044))) -#define MCF548X_SEC_CDPR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x023044))) -#define MCF548X_SEC_FR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02204C))) -#define MCF548X_SEC_FR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02304C))) -#define MCF548X_SEC_AFRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x028018))) -#define MCF548X_SEC_AFSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x028028))) -#define MCF548X_SEC_AFISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x028030))) -#define MCF548X_SEC_AFIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x028038))) -#define MCF548X_SEC_DRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02A018))) -#define MCF548X_SEC_DSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02A028))) -#define MCF548X_SEC_DISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02A030))) -#define MCF548X_SEC_DIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02A038))) -#define MCF548X_SEC_MDRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02C018))) -#define MCF548X_SEC_MDSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02C028))) -#define MCF548X_SEC_MDISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02C030))) -#define MCF548X_SEC_MDIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02C038))) -#define MCF548X_SEC_RNGRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02E018))) -#define MCF548X_SEC_RNGSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02E028))) -#define MCF548X_SEC_RNGISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02E030))) -#define MCF548X_SEC_RNGIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x02E038))) -#define MCF548X_SEC_AESRCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x032018))) -#define MCF548X_SEC_AESSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x032028))) -#define MCF548X_SEC_AESISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x032030))) -#define MCF548X_SEC_AESIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x032038))) - -/* Bit definitions and macros for MCF548X_SEC_EUACRH */ -#define MCF548X_SEC_EUACRH_AFEU(x) (((x)&0x0000000F)<<0) -#define MCF548X_SEC_EUACRH_MDEU(x) (((x)&0x0000000F)<<8) -#define MCF548X_SEC_EUACRH_RNG(x) (((x)&0x0000000F)<<24) -#define MCF548X_SEC_EUACRH_RNG_NOASSIGN (0x00000000) -#define MCF548X_SEC_EUACRH_RNG_CHA0 (0x01000000) -#define MCF548X_SEC_EUACRH_RNG_CHA1 (0x02000000) -#define MCF548X_SEC_EUACRH_MDEU_NOASSIGN (0x00000000) -#define MCF548X_SEC_EUACRH_MDEU_CHA0 (0x00000100) -#define MCF548X_SEC_EUACRH_MDEU_CHA1 (0x00000200) -#define MCF548X_SEC_EUACRH_AFEU_NOASSIGN (0x00000000) -#define MCF548X_SEC_EUACRH_AFEU_CHA0 (0x00000001) -#define MCF548X_SEC_EUACRH_AFEU_CHA1 (0x00000002) - -/* Bit definitions and macros for MCF548X_SEC_EUACRL */ -#define MCF548X_SEC_EUACRL_AESU(x) (((x)&0x0000000F)<<16) -#define MCF548X_SEC_EUACRL_DEU(x) (((x)&0x0000000F)<<24) -#define MCF548X_SEC_EUACRL_DEU_NOASSIGN (0x00000000) -#define MCF548X_SEC_EUACRL_DEU_CHA0 (0x01000000) -#define MCF548X_SEC_EUACRL_DEU_CHA1 (0x02000000) -#define MCF548X_SEC_EUACRL_AESU_NOASSIGN (0x00000000) -#define MCF548X_SEC_EUACRL_AESU_CHA0 (0x00010000) -#define MCF548X_SEC_EUACRL_AESU_CHA1 (0x00020000) - -/* Bit definitions and macros for MCF548X_SEC_EUASRH */ -#define MCF548X_SEC_EUASRH_AFEU(x) (((x)&0x0000000F)<<0) -#define MCF548X_SEC_EUASRH_MDEU(x) (((x)&0x0000000F)<<8) -#define MCF548X_SEC_EUASRH_RNG(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF548X_SEC_EUASRL */ -#define MCF548X_SEC_EUASRL_AESU(x) (((x)&0x0000000F)<<16) -#define MCF548X_SEC_EUASRL_DEU(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF548X_SEC_SIMRH */ -#define MCF548X_SEC_SIMRH_AERR (0x08000000) -#define MCF548X_SEC_SIMRH_CHA0DN (0x10000000) -#define MCF548X_SEC_SIMRH_CHA0ERR (0x20000000) -#define MCF548X_SEC_SIMRH_CHA1DN (0x40000000) -#define MCF548X_SEC_SIMRH_CHA1ERR (0x80000000) - -/* Bit definitions and macros for MCF548X_SEC_SIMRL */ -#define MCF548X_SEC_SIMRL_TEA (0x00000040) -#define MCF548X_SEC_SIMRL_DEUDN (0x00000100) -#define MCF548X_SEC_SIMRL_DEUERR (0x00000200) -#define MCF548X_SEC_SIMRL_AESUDN (0x00001000) -#define MCF548X_SEC_SIMRL_AESUERR (0x00002000) -#define MCF548X_SEC_SIMRL_MDEUDN (0x00010000) -#define MCF548X_SEC_SIMRL_MDEUERR (0x00020000) -#define MCF548X_SEC_SIMRL_AFEUDN (0x00100000) -#define MCF548X_SEC_SIMRL_AFEUERR (0x00200000) -#define MCF548X_SEC_SIMRL_RNGDN (0x01000000) -#define MCF548X_SEC_SIMRL_RNGERR (0x02000000) - -/* Bit definitions and macros for MCF548X_SEC_SISRH */ -#define MCF548X_SEC_SISRH_AERR (0x08000000) -#define MCF548X_SEC_SISRH_CHA0DN (0x10000000) -#define MCF548X_SEC_SISRH_CHA0ERR (0x20000000) -#define MCF548X_SEC_SISRH_CHA1DN (0x40000000) -#define MCF548X_SEC_SISRH_CHA1ERR (0x80000000) - -/* Bit definitions and macros for MCF548X_SEC_SISRL */ -#define MCF548X_SEC_SISRL_TEA (0x00000040) -#define MCF548X_SEC_SISRL_DEUDN (0x00000100) -#define MCF548X_SEC_SISRL_DEUERR (0x00000200) -#define MCF548X_SEC_SISRL_AESUDN (0x00001000) -#define MCF548X_SEC_SISRL_AESUERR (0x00002000) -#define MCF548X_SEC_SISRL_MDEUDN (0x00010000) -#define MCF548X_SEC_SISRL_MDEUERR (0x00020000) -#define MCF548X_SEC_SISRL_AFEUDN (0x00100000) -#define MCF548X_SEC_SISRL_AFEUERR (0x00200000) -#define MCF548X_SEC_SISRL_RNGDN (0x01000000) -#define MCF548X_SEC_SISRL_RNGERR (0x02000000) - -/* Bit definitions and macros for MCF548X_SEC_SICRH */ -#define MCF548X_SEC_SICRH_AERR (0x08000000) -#define MCF548X_SEC_SICRH_CHA0DN (0x10000000) -#define MCF548X_SEC_SICRH_CHA0ERR (0x20000000) -#define MCF548X_SEC_SICRH_CHA1DN (0x40000000) -#define MCF548X_SEC_SICRH_CHA1ERR (0x80000000) - -/* Bit definitions and macros for MCF548X_SEC_SICRL */ -#define MCF548X_SEC_SICRL_TEA (0x00000040) -#define MCF548X_SEC_SICRL_DEUDN (0x00000100) -#define MCF548X_SEC_SICRL_DEUERR (0x00000200) -#define MCF548X_SEC_SICRL_AESUDN (0x00001000) -#define MCF548X_SEC_SICRL_AESUERR (0x00002000) -#define MCF548X_SEC_SICRL_MDEUDN (0x00010000) -#define MCF548X_SEC_SICRL_MDEUERR (0x00020000) -#define MCF548X_SEC_SICRL_AFEUDN (0x00100000) -#define MCF548X_SEC_SICRL_AFEUERR (0x00200000) -#define MCF548X_SEC_SICRL_RNGDN (0x01000000) -#define MCF548X_SEC_SICRL_RNGERR (0x02000000) - -/* Bit definitions and macros for MCF548X_SEC_SMCR */ -#define MCF548X_SEC_SMCR_CURR_CHAN(x) (((x)&0x0000000F)<<4) -#define MCF548X_SEC_SMCR_SWR (0x01000000) -#define MCF548X_SEC_SMCR_CURR_CHAN_1 (0x00000010) -#define MCF548X_SEC_SMCR_CURR_CHAN_2 (0x00000020) - -/* Bit definitions and macros for MCF548X_SEC_CCCRn */ -#define MCF548X_SEC_CCCRn_RST (0x00000001) -#define MCF548X_SEC_CCCRn_CDIE (0x00000002) -#define MCF548X_SEC_CCCRn_NT (0x00000004) -#define MCF548X_SEC_CCCRn_NE (0x00000008) -#define MCF548X_SEC_CCCRn_WE (0x00000010) -#define MCF548X_SEC_CCCRn_BURST_SIZE(x) (((x)&0x00000007)<<8) -#define MCF548X_SEC_CCCRn_BURST_SIZE_2 (0x00000000) -#define MCF548X_SEC_CCCRn_BURST_SIZE_8 (0x00000100) -#define MCF548X_SEC_CCCRn_BURST_SIZE_16 (0x00000200) -#define MCF548X_SEC_CCCRn_BURST_SIZE_24 (0x00000300) -#define MCF548X_SEC_CCCRn_BURST_SIZE_32 (0x00000400) -#define MCF548X_SEC_CCCRn_BURST_SIZE_40 (0x00000500) -#define MCF548X_SEC_CCCRn_BURST_SIZE_48 (0x00000600) -#define MCF548X_SEC_CCCRn_BURST_SIZE_56 (0x00000700) - -/* Bit definitions and macros for MCF548X_SEC_CCPSRHn */ -#define MCF548X_SEC_CCPSRHn_STATE(x) (((x)&0x000000FF)<<0) - -/* Bit definitions and macros for MCF548X_SEC_CCPSRLn */ -#define MCF548X_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0x000000FF)<<0) -#define MCF548X_SEC_CCPSRLn_EUERR (0x00000100) -#define MCF548X_SEC_CCPSRLn_SERR (0x00000200) -#define MCF548X_SEC_CCPSRLn_DERR (0x00000400) -#define MCF548X_SEC_CCPSRLn_PERR (0x00001000) -#define MCF548X_SEC_CCPSRLn_TEA (0x00002000) -#define MCF548X_SEC_CCPSRLn_SD (0x00010000) -#define MCF548X_SEC_CCPSRLn_PD (0x00020000) -#define MCF548X_SEC_CCPSRLn_SRD (0x00040000) -#define MCF548X_SEC_CCPSRLn_PRD (0x00080000) -#define MCF548X_SEC_CCPSRLn_SG (0x00100000) -#define MCF548X_SEC_CCPSRLn_PG (0x00200000) -#define MCF548X_SEC_CCPSRLn_SR (0x00400000) -#define MCF548X_SEC_CCPSRLn_PR (0x00800000) -#define MCF548X_SEC_CCPSRLn_MO (0x01000000) -#define MCF548X_SEC_CCPSRLn_MI (0x02000000) -#define MCF548X_SEC_CCPSRLn_STAT (0x04000000) - -/* Bit definitions and macros for MCF548X_SEC_AFRCR */ -#define MCF548X_SEC_AFRCR_SR (0x01000000) -#define MCF548X_SEC_AFRCR_MI (0x02000000) -#define MCF548X_SEC_AFRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF548X_SEC_AFSR */ -#define MCF548X_SEC_AFSR_RD (0x01000000) -#define MCF548X_SEC_AFSR_ID (0x02000000) -#define MCF548X_SEC_AFSR_IE (0x04000000) -#define MCF548X_SEC_AFSR_OFE (0x08000000) -#define MCF548X_SEC_AFSR_IFW (0x10000000) -#define MCF548X_SEC_AFSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF548X_SEC_AFISR */ -#define MCF548X_SEC_AFISR_DSE (0x00010000) -#define MCF548X_SEC_AFISR_KSE (0x00020000) -#define MCF548X_SEC_AFISR_CE (0x00040000) -#define MCF548X_SEC_AFISR_ERE (0x00080000) -#define MCF548X_SEC_AFISR_IE (0x00100000) -#define MCF548X_SEC_AFISR_OFU (0x02000000) -#define MCF548X_SEC_AFISR_IFO (0x04000000) -#define MCF548X_SEC_AFISR_IFE (0x10000000) -#define MCF548X_SEC_AFISR_OFE (0x20000000) -#define MCF548X_SEC_AFISR_AE (0x40000000) -#define MCF548X_SEC_AFISR_ME (0x80000000) - -/* Bit definitions and macros for MCF548X_SEC_AFIMR */ -#define MCF548X_SEC_AFIMR_DSE (0x00010000) -#define MCF548X_SEC_AFIMR_KSE (0x00020000) -#define MCF548X_SEC_AFIMR_CE (0x00040000) -#define MCF548X_SEC_AFIMR_ERE (0x00080000) -#define MCF548X_SEC_AFIMR_IE (0x00100000) -#define MCF548X_SEC_AFIMR_OFU (0x02000000) -#define MCF548X_SEC_AFIMR_IFO (0x04000000) -#define MCF548X_SEC_AFIMR_IFE (0x10000000) -#define MCF548X_SEC_AFIMR_OFE (0x20000000) -#define MCF548X_SEC_AFIMR_AE (0x40000000) -#define MCF548X_SEC_AFIMR_ME (0x80000000) - -/* Bit definitions and macros for MCF548X_SEC_DRCR */ -#define MCF548X_SEC_DRCR_SR (0x01000000) -#define MCF548X_SEC_DRCR_MI (0x02000000) -#define MCF548X_SEC_DRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF548X_SEC_DSR */ -#define MCF548X_SEC_DSR_RD (0x01000000) -#define MCF548X_SEC_DSR_ID (0x02000000) -#define MCF548X_SEC_DSR_IE (0x04000000) -#define MCF548X_SEC_DSR_OFR (0x08000000) -#define MCF548X_SEC_DSR_IFW (0x10000000) -#define MCF548X_SEC_DSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF548X_SEC_DISR */ -#define MCF548X_SEC_DISR_DSE (0x00010000) -#define MCF548X_SEC_DISR_KSE (0x00020000) -#define MCF548X_SEC_DISR_CE (0x00040000) -#define MCF548X_SEC_DISR_ERE (0x00080000) -#define MCF548X_SEC_DISR_IE (0x00100000) -#define MCF548X_SEC_DISR_KPE (0x00200000) -#define MCF548X_SEC_DISR_OFU (0x02000000) -#define MCF548X_SEC_DISR_IFO (0x04000000) -#define MCF548X_SEC_DISR_IFE (0x10000000) -#define MCF548X_SEC_DISR_OFE (0x20000000) -#define MCF548X_SEC_DISR_AE (0x40000000) -#define MCF548X_SEC_DISR_ME (0x80000000) - -/* Bit definitions and macros for MCF548X_SEC_DIMR */ -#define MCF548X_SEC_DIMR_DSE (0x00010000) -#define MCF548X_SEC_DIMR_KSE (0x00020000) -#define MCF548X_SEC_DIMR_CE (0x00040000) -#define MCF548X_SEC_DIMR_ERE (0x00080000) -#define MCF548X_SEC_DIMR_IE (0x00100000) -#define MCF548X_SEC_DIMR_KPE (0x00200000) -#define MCF548X_SEC_DIMR_OFU (0x02000000) -#define MCF548X_SEC_DIMR_IFO (0x04000000) -#define MCF548X_SEC_DIMR_IFE (0x10000000) -#define MCF548X_SEC_DIMR_OFE (0x20000000) -#define MCF548X_SEC_DIMR_AE (0x40000000) -#define MCF548X_SEC_DIMR_ME (0x80000000) - -/* Bit definitions and macros for MCF548X_SEC_MDRCR */ -#define MCF548X_SEC_MDRCR_SR (0x01000000) -#define MCF548X_SEC_MDRCR_MI (0x02000000) -#define MCF548X_SEC_MDRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF548X_SEC_MDSR */ -#define MCF548X_SEC_MDSR_RD (0x01000000) -#define MCF548X_SEC_MDSR_ID (0x02000000) -#define MCF548X_SEC_MDSR_IE (0x04000000) -#define MCF548X_SEC_MDSR_IFW (0x10000000) -#define MCF548X_SEC_MDSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF548X_SEC_MDISR */ -#define MCF548X_SEC_MDISR_DSE (0x00010000) -#define MCF548X_SEC_MDISR_KSE (0x00020000) -#define MCF548X_SEC_MDISR_CE (0x00040000) -#define MCF548X_SEC_MDISR_ERE (0x00080000) -#define MCF548X_SEC_MDISR_IE (0x00100000) -#define MCF548X_SEC_MDISR_IFO (0x04000000) -#define MCF548X_SEC_MDISR_AE (0x40000000) -#define MCF548X_SEC_MDISR_ME (0x80000000) - -/* Bit definitions and macros for MCF548X_SEC_MDIMR */ -#define MCF548X_SEC_MDIMR_DSE (0x00010000) -#define MCF548X_SEC_MDIMR_KSE (0x00020000) -#define MCF548X_SEC_MDIMR_CE (0x00040000) -#define MCF548X_SEC_MDIMR_ERE (0x00080000) -#define MCF548X_SEC_MDIMR_IE (0x00100000) -#define MCF548X_SEC_MDIMR_IFO (0x04000000) -#define MCF548X_SEC_MDIMR_AE (0x40000000) -#define MCF548X_SEC_MDIMR_ME (0x80000000) - -/* Bit definitions and macros for MCF548X_SEC_RNGRCR */ -#define MCF548X_SEC_RNGRCR_SR (0x01000000) -#define MCF548X_SEC_RNGRCR_MI (0x02000000) -#define MCF548X_SEC_RNGRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF548X_SEC_RNGSR */ -#define MCF548X_SEC_RNGSR_RD (0x01000000) -#define MCF548X_SEC_RNGSR_O (0x02000000) -#define MCF548X_SEC_RNGSR_IE (0x04000000) -#define MCF548X_SEC_RNGSR_OFR (0x08000000) -#define MCF548X_SEC_RNGSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF548X_SEC_RNGISR */ -#define MCF548X_SEC_RNGISR_IE (0x00100000) -#define MCF548X_SEC_RNGISR_OFU (0x02000000) -#define MCF548X_SEC_RNGISR_AE (0x40000000) -#define MCF548X_SEC_RNGISR_ME (0x80000000) - -/* Bit definitions and macros for MCF548X_SEC_RNGIMR */ -#define MCF548X_SEC_RNGIMR_IE (0x00100000) -#define MCF548X_SEC_RNGIMR_OFU (0x02000000) -#define MCF548X_SEC_RNGIMR_AE (0x40000000) -#define MCF548X_SEC_RNGIMR_ME (0x80000000) - -/* Bit definitions and macros for MCF548X_SEC_AESRCR */ -#define MCF548X_SEC_AESRCR_SR (0x01000000) -#define MCF548X_SEC_AESRCR_MI (0x02000000) -#define MCF548X_SEC_AESRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF548X_SEC_AESSR */ -#define MCF548X_SEC_AESSR_RD (0x01000000) -#define MCF548X_SEC_AESSR_ID (0x02000000) -#define MCF548X_SEC_AESSR_IE (0x04000000) -#define MCF548X_SEC_AESSR_OFR (0x08000000) -#define MCF548X_SEC_AESSR_IFW (0x10000000) -#define MCF548X_SEC_AESSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF548X_SEC_AESISR */ -#define MCF548X_SEC_AESISR_DSE (0x00010000) -#define MCF548X_SEC_AESISR_KSE (0x00020000) -#define MCF548X_SEC_AESISR_CE (0x00040000) -#define MCF548X_SEC_AESISR_ERE (0x00080000) -#define MCF548X_SEC_AESISR_IE (0x00100000) -#define MCF548X_SEC_AESISR_OFU (0x02000000) -#define MCF548X_SEC_AESISR_IFO (0x04000000) -#define MCF548X_SEC_AESISR_IFE (0x10000000) -#define MCF548X_SEC_AESISR_OFE (0x20000000) -#define MCF548X_SEC_AESISR_AE (0x40000000) -#define MCF548X_SEC_AESISR_ME (0x80000000) - -/* Bit definitions and macros for MCF548X_SEC_AESIMR */ -#define MCF548X_SEC_AESIMR_DSE (0x00010000) -#define MCF548X_SEC_AESIMR_KSE (0x00020000) -#define MCF548X_SEC_AESIMR_CE (0x00040000) -#define MCF548X_SEC_AESIMR_ERE (0x00080000) -#define MCF548X_SEC_AESIMR_IE (0x00100000) -#define MCF548X_SEC_AESIMR_OFU (0x02000000) -#define MCF548X_SEC_AESIMR_IFO (0x04000000) -#define MCF548X_SEC_AESIMR_IFE (0x10000000) -#define MCF548X_SEC_AESIMR_OFE (0x20000000) -#define MCF548X_SEC_AESIMR_AE (0x40000000) -#define MCF548X_SEC_AESIMR_ME (0x80000000) - - -/********************************************************************* -* -* Slice Timers (SLT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_SLT_SLTCNT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000900))) -#define MCF548X_SLT_SCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000904))) -#define MCF548X_SLT_SCNT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000908))) -#define MCF548X_SLT_SSR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00090C))) -#define MCF548X_SLT_SLTCNT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000910))) -#define MCF548X_SLT_SCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000914))) -#define MCF548X_SLT_SCNT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000918))) -#define MCF548X_SLT_SSR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00091C))) -#define MCF548X_SLT_SLTCNT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000900U+((x)*0x010)))) -#define MCF548X_SLT_SCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000904U+((x)*0x010)))) -#define MCF548X_SLT_SCNT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000908U+((x)*0x010)))) -#define MCF548X_SLT_SSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00090CU+((x)*0x010)))) - -/* Bit definitions and macros for MCF548X_SLT_SCR */ -#define MCF548X_SLT_SCR_TEN (0x01000000) -#define MCF548X_SLT_SCR_IEN (0x02000000) -#define MCF548X_SLT_SCR_RUN (0x04000000) - -/* Bit definitions and macros for MCF548X_SLT_SSR */ -#define MCF548X_SLT_SSR_ST (0x01000000) -#define MCF548X_SLT_SSR_BE (0x02000000) - - -/********************************************************************* -* -* Universal Serial Bus (USB) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_USB_USBAISR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B000))) -#define MCF548X_USB_USBAIMR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B001))) -#define MCF548X_USB_EPINFO (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B003))) -#define MCF548X_USB_CFGR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B004))) -#define MCF548X_USB_CFGAR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B005))) -#define MCF548X_USB_SPEEDR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B006))) -#define MCF548X_USB_FRMNUMR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B00E))) -#define MCF548X_USB_EPTNR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B010))) -#define MCF548X_USB_IFUR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B014))) -#define MCF548X_USB_IFR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B040))) -#define MCF548X_USB_IFR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B042))) -#define MCF548X_USB_IFR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B044))) -#define MCF548X_USB_IFR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B046))) -#define MCF548X_USB_IFR4 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B048))) -#define MCF548X_USB_IFR5 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B04A))) -#define MCF548X_USB_IFR6 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B04C))) -#define MCF548X_USB_IFR7 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B04E))) -#define MCF548X_USB_IFR8 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B050))) -#define MCF548X_USB_IFR9 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B052))) -#define MCF548X_USB_IFR10 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B054))) -#define MCF548X_USB_IFR11 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B056))) -#define MCF548X_USB_IFR12 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B058))) -#define MCF548X_USB_IFR13 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B05A))) -#define MCF548X_USB_IFR14 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B05C))) -#define MCF548X_USB_IFR15 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B05E))) -#define MCF548X_USB_IFR16 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B060))) -#define MCF548X_USB_IFR17 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B062))) -#define MCF548X_USB_IFR18 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B064))) -#define MCF548X_USB_IFR19 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B066))) -#define MCF548X_USB_IFR20 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B068))) -#define MCF548X_USB_IFR21 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B06A))) -#define MCF548X_USB_IFR22 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B06C))) -#define MCF548X_USB_IFR23 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B06E))) -#define MCF548X_USB_IFR24 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B070))) -#define MCF548X_USB_IFR25 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B072))) -#define MCF548X_USB_IFR26 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B074))) -#define MCF548X_USB_IFR27 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B076))) -#define MCF548X_USB_IFR28 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B078))) -#define MCF548X_USB_IFR29 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B07A))) -#define MCF548X_USB_IFR30 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B07C))) -#define MCF548X_USB_IFR31 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B07E))) -#define MCF548X_USB_IFRn(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B040U+((x)*0x002)))) -#define MCF548X_USB_PPCNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B080))) -#define MCF548X_USB_DPCNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B082))) -#define MCF548X_USB_CRCECNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B084))) -#define MCF548X_USB_BSECNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B086))) -#define MCF548X_USB_PIDECNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B088))) -#define MCF548X_USB_FRMECNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B08A))) -#define MCF548X_USB_TXPCNT (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B08C))) -#define MCF548X_USB_CNTOVR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B08E))) -#define MCF548X_USB_EP0ACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B101))) -#define MCF548X_USB_EP0MPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B102))) -#define MCF548X_USB_EP0IFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B104))) -#define MCF548X_USB_EP0SR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B105))) -#define MCF548X_USB_BMRTR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B106))) -#define MCF548X_USB_BRTR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B107))) -#define MCF548X_USB_WVALUER (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B108))) -#define MCF548X_USB_WINDEXR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B10A))) -#define MCF548X_USB_WLENGTH (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B10C))) -#define MCF548X_USB_EP1OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B131))) -#define MCF548X_USB_EP2OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B161))) -#define MCF548X_USB_EP3OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B191))) -#define MCF548X_USB_EP4OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1C1))) -#define MCF548X_USB_EP5OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1F1))) -#define MCF548X_USB_EP6OUTACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B221))) -#define MCF548X_USB_EPnOUTACR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B131U+((x)*0x030)))) -#define MCF548X_USB_EP1OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B132))) -#define MCF548X_USB_EP2OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B162))) -#define MCF548X_USB_EP3OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B192))) -#define MCF548X_USB_EP4OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1C2))) -#define MCF548X_USB_EP5OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1F2))) -#define MCF548X_USB_EP6OUTMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B222))) -#define MCF548X_USB_EPnOUTMPSR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B132U+((x)*0x030)))) -#define MCF548X_USB_EP1OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B134))) -#define MCF548X_USB_EP2OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B164))) -#define MCF548X_USB_EP3OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B194))) -#define MCF548X_USB_EP4OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1C4))) -#define MCF548X_USB_EP5OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1F4))) -#define MCF548X_USB_EP6OUTIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B224))) -#define MCF548X_USB_EPnOUTIFR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B134U+((x)*0x030)))) -#define MCF548X_USB_EP1OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B135))) -#define MCF548X_USB_EP2OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B165))) -#define MCF548X_USB_EP3OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B195))) -#define MCF548X_USB_EP4OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1C5))) -#define MCF548X_USB_EP5OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1F5))) -#define MCF548X_USB_EP6OUTSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B225))) -#define MCF548X_USB_EPnOUTSR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B135U+((x)*0x030)))) -#define MCF548X_USB_EP1OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B13E))) -#define MCF548X_USB_EP2OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B16E))) -#define MCF548X_USB_EP3OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B19E))) -#define MCF548X_USB_EP4OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1CE))) -#define MCF548X_USB_EP5OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1FE))) -#define MCF548X_USB_EP6OUTSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B22E))) -#define MCF548X_USB_EPnOUTSFR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B13EU+((x)*0x030)))) -#define MCF548X_USB_EP1INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B149))) -#define MCF548X_USB_EP2INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B179))) -#define MCF548X_USB_EP3INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1A9))) -#define MCF548X_USB_EP4INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1D9))) -#define MCF548X_USB_EP5INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B209))) -#define MCF548X_USB_EP6INACR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B239))) -#define MCF548X_USB_EPnINACR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B149U+((x)*0x030)))) -#define MCF548X_USB_EP1INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B14A))) -#define MCF548X_USB_EP2INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B17A))) -#define MCF548X_USB_EP3INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1AA))) -#define MCF548X_USB_EP4INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1DA))) -#define MCF548X_USB_EP5INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B20A))) -#define MCF548X_USB_EP6INMPSR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B23A))) -#define MCF548X_USB_EPnINMPSR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B14AU+((x)*0x030)))) -#define MCF548X_USB_EP1INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B14C))) -#define MCF548X_USB_EP2INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B17C))) -#define MCF548X_USB_EP3INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1AC))) -#define MCF548X_USB_EP4INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1DC))) -#define MCF548X_USB_EP5INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B20C))) -#define MCF548X_USB_EP6INIFR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B23C))) -#define MCF548X_USB_EPnINIFR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B14CU+((x)*0x030)))) -#define MCF548X_USB_EP1INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B14D))) -#define MCF548X_USB_EP2INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B17D))) -#define MCF548X_USB_EP3INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1AD))) -#define MCF548X_USB_EP4INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B1DD))) -#define MCF548X_USB_EP5INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B20D))) -#define MCF548X_USB_EP6INSR (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B23D))) -#define MCF548X_USB_EPnINSR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00B14DU+((x)*0x030)))) -#define MCF548X_USB_EP1INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B15A))) -#define MCF548X_USB_EP2INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B18A))) -#define MCF548X_USB_EP3INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1BA))) -#define MCF548X_USB_EP4INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B1EA))) -#define MCF548X_USB_EP5INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B21A))) -#define MCF548X_USB_EP6INSFR (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B24A))) -#define MCF548X_USB_EPnINSFR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00B15AU+((x)*0x030)))) -#define MCF548X_USB_USBSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B400))) -#define MCF548X_USB_USBCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B404))) -#define MCF548X_USB_DRAMCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B408))) -#define MCF548X_USB_DRAMDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B40C))) -#define MCF548X_USB_USBISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B410))) -#define MCF548X_USB_USBIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B414))) -#define MCF548X_USB_EP0STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B440))) -#define MCF548X_USB_EP1STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B470))) -#define MCF548X_USB_EP2STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4A0))) -#define MCF548X_USB_EP3STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4D0))) -#define MCF548X_USB_EP4STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B500))) -#define MCF548X_USB_EP5STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B530))) -#define MCF548X_USB_EP6STAT (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B560))) -#define MCF548X_USB_EPnSTAT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B440U+((x)*0x030)))) -#define MCF548X_USB_EP0ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B444))) -#define MCF548X_USB_EP1ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B474))) -#define MCF548X_USB_EP2ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4A4))) -#define MCF548X_USB_EP3ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4D4))) -#define MCF548X_USB_EP4ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B504))) -#define MCF548X_USB_EP5ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B534))) -#define MCF548X_USB_EP6ISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B564))) -#define MCF548X_USB_EPnISR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B444U+((x)*0x030)))) -#define MCF548X_USB_EP0IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B448))) -#define MCF548X_USB_EP1IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B478))) -#define MCF548X_USB_EP2IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4A8))) -#define MCF548X_USB_EP3IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4D8))) -#define MCF548X_USB_EP4IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B508))) -#define MCF548X_USB_EP5IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B538))) -#define MCF548X_USB_EP6IMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B568))) -#define MCF548X_USB_EPnIMR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B448U+((x)*0x030)))) -#define MCF548X_USB_EP0FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B44C))) -#define MCF548X_USB_EP1FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B47C))) -#define MCF548X_USB_EP2FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4AC))) -#define MCF548X_USB_EP3FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4DC))) -#define MCF548X_USB_EP4FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B50C))) -#define MCF548X_USB_EP5FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B53C))) -#define MCF548X_USB_EP6FRCFGR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B56C))) -#define MCF548X_USB_EPnFRCFGR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B44CU+((x)*0x030)))) -#define MCF548X_USB_EP0FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B450))) -#define MCF548X_USB_EP1FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B480))) -#define MCF548X_USB_EP2FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4B0))) -#define MCF548X_USB_EP3FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4E0))) -#define MCF548X_USB_EP4FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B510))) -#define MCF548X_USB_EP5FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B540))) -#define MCF548X_USB_EP6FDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B570))) -#define MCF548X_USB_EPnFDR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B450U+((x)*0x030)))) -#define MCF548X_USB_EP0FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B454))) -#define MCF548X_USB_EP1FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B484))) -#define MCF548X_USB_EP2FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4B4))) -#define MCF548X_USB_EP3FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4E4))) -#define MCF548X_USB_EP4FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B514))) -#define MCF548X_USB_EP5FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B544))) -#define MCF548X_USB_EP6FSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B574))) -#define MCF548X_USB_EPnFSR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B454U+((x)*0x030)))) -#define MCF548X_USB_EP0FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B458))) -#define MCF548X_USB_EP1FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B488))) -#define MCF548X_USB_EP2FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4B8))) -#define MCF548X_USB_EP3FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4E8))) -#define MCF548X_USB_EP4FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B518))) -#define MCF548X_USB_EP5FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B548))) -#define MCF548X_USB_EP6FCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B578))) -#define MCF548X_USB_EPnFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B458U+((x)*0x030)))) -#define MCF548X_USB_EP0FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B45C))) -#define MCF548X_USB_EP1FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B48C))) -#define MCF548X_USB_EP2FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4BC))) -#define MCF548X_USB_EP3FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4EC))) -#define MCF548X_USB_EP4FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B51C))) -#define MCF548X_USB_EP5FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B54C))) -#define MCF548X_USB_EP6FAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B57C))) -#define MCF548X_USB_EPnFAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B45CU+((x)*0x030)))) -#define MCF548X_USB_EP0FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B460))) -#define MCF548X_USB_EP1FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B490))) -#define MCF548X_USB_EP2FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4C0))) -#define MCF548X_USB_EP3FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4F0))) -#define MCF548X_USB_EP4FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B520))) -#define MCF548X_USB_EP5FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B550))) -#define MCF548X_USB_EP6FRP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B580))) -#define MCF548X_USB_EPnFRP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B460U+((x)*0x030)))) -#define MCF548X_USB_EP0FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B464))) -#define MCF548X_USB_EP1FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B494))) -#define MCF548X_USB_EP2FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4C4))) -#define MCF548X_USB_EP3FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4F4))) -#define MCF548X_USB_EP4FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B524))) -#define MCF548X_USB_EP5FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B554))) -#define MCF548X_USB_EP6FWP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B584))) -#define MCF548X_USB_EPnFWP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B464U+((x)*0x030)))) -#define MCF548X_USB_EP0LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B468))) -#define MCF548X_USB_EP1LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B498))) -#define MCF548X_USB_EP2LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4C8))) -#define MCF548X_USB_EP3LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4F8))) -#define MCF548X_USB_EP4LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B528))) -#define MCF548X_USB_EP5LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B558))) -#define MCF548X_USB_EP6LRFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B588))) -#define MCF548X_USB_EPnLRFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B468U+((x)*0x030)))) -#define MCF548X_USB_EP0LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B46C))) -#define MCF548X_USB_EP1LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B49C))) -#define MCF548X_USB_EP2LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4CC))) -#define MCF548X_USB_EP3LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B4FC))) -#define MCF548X_USB_EP4LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B52C))) -#define MCF548X_USB_EP5LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B55C))) -#define MCF548X_USB_EP6LWFP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B58C))) -#define MCF548X_USB_EPnLWFP(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00B46CU+((x)*0x030)))) - -/* Bit definitions and macros for MCF548X_USB_USBAISR */ -#define MCF548X_USB_USBAISR_SETUP (0x01) -#define MCF548X_USB_USBAISR_IN (0x02) -#define MCF548X_USB_USBAISR_OUT (0x04) -#define MCF548X_USB_USBAISR_EPHALT (0x08) -#define MCF548X_USB_USBAISR_TRANSERR (0x10) -#define MCF548X_USB_USBAISR_ACK (0x20) -#define MCF548X_USB_USBAISR_CTROVFL (0x40) -#define MCF548X_USB_USBAISR_EPSTALL (0x80) - -/* Bit definitions and macros for MCF548X_USB_USBAIMR */ -#define MCF548X_USB_USBAIMR_SETUPEN (0x01) -#define MCF548X_USB_USBAIMR_INEN (0x02) -#define MCF548X_USB_USBAIMR_OUTEN (0x04) -#define MCF548X_USB_USBAIMR_EPHALTEN (0x08) -#define MCF548X_USB_USBAIMR_TRANSERREN (0x10) -#define MCF548X_USB_USBAIMR_ACKEN (0x20) -#define MCF548X_USB_USBAIMR_CTROVFLEN (0x40) -#define MCF548X_USB_USBAIMR_EPSTALLEN (0x80) - -/* Bit definitions and macros for MCF548X_USB_EPINFO */ -#define MCF548X_USB_EPINFO_EPDIR (0x01) -#define MCF548X_USB_EPINFO_EPNUM(x) (((x)&0x07)<<1) - -/* Bit definitions and macros for MCF548X_USB_CFGAR */ -#define MCF548X_USB_CFGAR_RESERVED (0xA0) -#define MCF548X_USB_CFGAR_RMTWKEUP (0xE0) - -/* Bit definitions and macros for MCF548X_USB_SPEEDR */ -#define MCF548X_USB_SPEEDR_HS (0x01) -#define MCF548X_USB_SPEEDR_FS (0x02) - -/* Bit definitions and macros for MCF548X_USB_FRMNUMR */ -#define MCF548X_USB_FRMNUMR_FRMNUM(x) (((x)&0x0FFF)<<0) - -/* Bit definitions and macros for MCF548X_USB_EPTNR */ -#define MCF548X_USB_EPTNR_EP1T(x) (((x)&0x0003)<<0) -#define MCF548X_USB_EPTNR_EP2T(x) (((x)&0x0003)<<2) -#define MCF548X_USB_EPTNR_EP3T(x) (((x)&0x0003)<<4) -#define MCF548X_USB_EPTNR_EP4T(x) (((x)&0x0003)<<6) -#define MCF548X_USB_EPTNR_EP5T(x) (((x)&0x0003)<<8) -#define MCF548X_USB_EPTNR_EP6T(x) (((x)&0x0003)<<10) -#define MCF548X_USB_EPTNR_EPnT1 (0) -#define MCF548X_USB_EPTNR_EPnT2 (1) -#define MCF548X_USB_EPTNR_EPnT3 (2) - -/* Bit definitions and macros for MCF548X_USB_IFUR */ -#define MCF548X_USB_IFUR_ALTSET(x) (((x)&0x00FF)<<0) -#define MCF548X_USB_IFUR_IFNUM(x) (((x)&0x00FF)<<8) - -/* Bit definitions and macros for MCF548X_USB_IFRn */ -#define MCF548X_USB_IFRn_ALTSET(x) (((x)&0x00FF)<<0) -#define MCF548X_USB_IFRn_IFNUM(x) (((x)&0x00FF)<<8) - -/* Bit definitions and macros for MCF548X_USB_CNTOVR */ -#define MCF548X_USB_CNTOVR_PPCNT (0x01) -#define MCF548X_USB_CNTOVR_DPCNT (0x02) -#define MCF548X_USB_CNTOVR_CRCECNT (0x04) -#define MCF548X_USB_CNTOVR_BSECNT (0x08) -#define MCF548X_USB_CNTOVR_PIDECNT (0x10) -#define MCF548X_USB_CNTOVR_FRMECNT (0x20) -#define MCF548X_USB_CNTOVR_TXPCNT (0x40) - -/* Bit definitions and macros for MCF548X_USB_EP0ACR */ -#define MCF548X_USB_EP0ACR_TTYPE(x) (((x)&0x03)<<0) -#define MCF548X_USB_EP0ACR_TTYPE_CTRL (0) -#define MCF548X_USB_EP0ACR_TTYPE_ISOC (1) -#define MCF548X_USB_EP0ACR_TTYPE_BULK (2) -#define MCF548X_USB_EP0ACR_TTYPE_INT (3) - -/* Bit definitions and macros for MCF548X_USB_EP0MPSR */ -#define MCF548X_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) -#define MCF548X_USB_EP0MPSR_ADDTRANS(x) (((x)&0x0003)<<11) - -/* Bit definitions and macros for MCF548X_USB_EP0SR */ -#define MCF548X_USB_EP0SR_HALT (0x01) -#define MCF548X_USB_EP0SR_ACTIVE (0x02) -#define MCF548X_USB_EP0SR_PSTALL (0x04) -#define MCF548X_USB_EP0SR_CCOMP (0x08) -#define MCF548X_USB_EP0SR_TXZERO (0x20) -#define MCF548X_USB_EP0SR_INT (0x80) - -/* Bit definitions and macros for MCF548X_USB_BMRTR */ -#define MCF548X_USB_BMRTR_DIR (0x80) -#define MCF548X_USB_BMRTR_TYPE_STANDARD (0x00) -#define MCF548X_USB_BMRTR_TYPE_CLASS (0x20) -#define MCF548X_USB_BMRTR_TYPE_VENDOR (0x40) -#define MCF548X_USB_BMRTR_REC_DEVICE (0x00) -#define MCF548X_USB_BMRTR_REC_INTERFACE (0x01) -#define MCF548X_USB_BMRTR_REC_ENDPOINT (0x02) -#define MCF548X_USB_BMRTR_REC_OTHER (0x03) - -/* Bit definitions and macros for MCF548X_USB_EPnOUTACR */ -#define MCF548X_USB_EPnOUTACR_TTYPE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF548X_USB_EPnOUTMPSR */ -#define MCF548X_USB_EPnOUTMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) -#define MCF548X_USB_EPnOUTMPSR_ADDTRANS(x) (((x)&0x0003)<<11) - -/* Bit definitions and macros for MCF548X_USB_EPnOUTSR */ -#define MCF548X_USB_EPnOUTSR_HALT (0x01) -#define MCF548X_USB_EPnOUTSR_ACTIVE (0x02) -#define MCF548X_USB_EPnOUTSR_PSTALL (0x04) -#define MCF548X_USB_EPnOUTSR_CCOMP (0x08) -#define MCF548X_USB_EPnOUTSR_TXZERO (0x20) -#define MCF548X_USB_EPnOUTSR_INT (0x80) - -/* Bit definitions and macros for MCF548X_USB_EPnOUTSFR */ -#define MCF548X_USB_EPnOUTSFR_FRMNUM(x) (((x)&0x07FF)<<0) - -/* Bit definitions and macros for MCF548X_USB_EPnINACR */ -#define MCF548X_USB_EPnINACR_TTYPE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF548X_USB_EPnINMPSR */ -#define MCF548X_USB_EPnINMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) -#define MCF548X_USB_EPnINMPSR_ADDTRANS(x) (((x)&0x0003)<<11) - -/* Bit definitions and macros for MCF548X_USB_EPnINSR */ -#define MCF548X_USB_EPnINSR_HALT (0x01) -#define MCF548X_USB_EPnINSR_ACTIVE (0x02) -#define MCF548X_USB_EPnINSR_PSTALL (0x04) -#define MCF548X_USB_EPnINSR_CCOMP (0x08) -#define MCF548X_USB_EPnINSR_TXZERO (0x20) -#define MCF548X_USB_EPnINSR_INT (0x80) - -/* Bit definitions and macros for MCF548X_USB_EPnINSFR */ -#define MCF548X_USB_EPnINSFR_FRMNUM(x) (((x)&0x07FF)<<0) - -/* Bit definitions and macros for MCF548X_USB_USBSR */ -#define MCF548X_USB_USBSR_SUSP (0x00000080) -#define MCF548X_USB_USBSR_ISOERREP (0x0000000F) - -/* Bit definitions and macros for MCF548X_USB_USBCR */ -#define MCF548X_USB_USBCR_RESUME (0x00000001) -#define MCF548X_USB_USBCR_APPLOCK (0x00000002) -#define MCF548X_USB_USBCR_RST (0x00000004) -#define MCF548X_USB_USBCR_RAMEN (0x00000008) -#define MCF548X_USB_USBCR_RAMSPLIT (0x00000020) - -/* Bit definitions and macros for MCF548X_USB_DRAMCR */ -#define MCF548X_USB_DRAMCR_DADR(x) (((x)&0x000003FF)<<0) -#define MCF548X_USB_DRAMCR_DSIZE(x) (((x)&0x000007FF)<<16) -#define MCF548X_USB_DRAMCR_BSY (0x40000000) -#define MCF548X_USB_DRAMCR_START (0x80000000) - -/* Bit definitions and macros for MCF548X_USB_DRAMDR */ -#define MCF548X_USB_DRAMDR_DDAT(x) (((x)&0x000000FF)<<0) - -/* Bit definitions and macros for MCF548X_USB_USBISR */ -#define MCF548X_USB_USBISR_ISOERR (0x00000001) -#define MCF548X_USB_USBISR_FTUNLCK (0x00000002) -#define MCF548X_USB_USBISR_SUSP (0x00000004) -#define MCF548X_USB_USBISR_RES (0x00000008) -#define MCF548X_USB_USBISR_UPDSOF (0x00000010) -#define MCF548X_USB_USBISR_RSTSTOP (0x00000020) -#define MCF548X_USB_USBISR_SOF (0x00000040) -#define MCF548X_USB_USBISR_MSOF (0x00000080) - -/* Bit definitions and macros for MCF548X_USB_USBIMR */ -#define MCF548X_USB_USBIMR_ISOERR (0x00000001) -#define MCF548X_USB_USBIMR_FTUNLCK (0x00000002) -#define MCF548X_USB_USBIMR_SUSP (0x00000004) -#define MCF548X_USB_USBIMR_RES (0x00000008) -#define MCF548X_USB_USBIMR_UPDSOF (0x00000010) -#define MCF548X_USB_USBIMR_RSTSTOP (0x00000020) -#define MCF548X_USB_USBIMR_SOF (0x00000040) -#define MCF548X_USB_USBIMR_MSOF (0x00000080) - -/* Bit definitions and macros for MCF548X_USB_EPnSTAT */ -#define MCF548X_USB_EPnSTAT_RST (0x00000001) -#define MCF548X_USB_EPnSTAT_FLUSH (0x00000002) -#define MCF548X_USB_EPnSTAT_DIR (0x00000080) -#define MCF548X_USB_EPnSTAT_BYTECNT(x) (((x)&0x00000FFF)<<16) - -/* Bit definitions and macros for MCF548X_USB_EPnISR */ -#define MCF548X_USB_EPnISR_EOF (0x00000001) -#define MCF548X_USB_EPnISR_EOT (0x00000004) -#define MCF548X_USB_EPnISR_FIFOLO (0x00000010) -#define MCF548X_USB_EPnISR_FIFOHI (0x00000020) -#define MCF548X_USB_EPnISR_ERR (0x00000040) -#define MCF548X_USB_EPnISR_EMT (0x00000080) -#define MCF548X_USB_EPnISR_FU (0x00000100) - -/* Bit definitions and macros for MCF548X_USB_EPnIMR */ -#define MCF548X_USB_EPnIMR_EOF (0x00000001) -#define MCF548X_USB_EPnIMR_EOT (0x00000004) -#define MCF548X_USB_EPnIMR_FIFOLO (0x00000010) -#define MCF548X_USB_EPnIMR_FIFOHI (0x00000020) -#define MCF548X_USB_EPnIMR_ERR (0x00000040) -#define MCF548X_USB_EPnIMR_EMT (0x00000080) -#define MCF548X_USB_EPnIMR_FU (0x00000100) - -/* Bit definitions and macros for MCF548X_USB_EPnFRCFGR */ -#define MCF548X_USB_EPnFRCFGR_DEPTH(x) (((x)&0x00001FFF)<<0) -#define MCF548X_USB_EPnFRCFGR_BASE(x) (((x)&0x00000FFF)<<16) - -/* Bit definitions and macros for MCF548X_USB_EPnFSR */ -#define MCF548X_USB_EPnFSR_EMT (0x00010000) -#define MCF548X_USB_EPnFSR_ALRM (0x00020000) -#define MCF548X_USB_EPnFSR_FR (0x00040000) -#define MCF548X_USB_EPnFSR_FU (0x00080000) -#define MCF548X_USB_EPnFSR_OF (0x00100000) -#define MCF548X_USB_EPnFSR_UF (0x00200000) -#define MCF548X_USB_EPnFSR_RXW (0x00400000) -#define MCF548X_USB_EPnFSR_FAE (0x00800000) -#define MCF548X_USB_EPnFSR_FRM(x) (((x)&0x0000000F)<<24) -#define MCF548X_USB_EPnFSR_TXW (0x40000000) -#define MCF548X_USB_EPnFSR_IP (0x80000000) - -/* Bit definitions and macros for MCF548X_USB_EPnFCR */ -#define MCF548X_USB_EPnFCR_COUNTER(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_USB_EPnFCR_TXWMSK (0x00040000) -#define MCF548X_USB_EPnFCR_OFMSK (0x00080000) -#define MCF548X_USB_EPnFCR_UFMSK (0x00100000) -#define MCF548X_USB_EPnFCR_RXWMSK (0x00200000) -#define MCF548X_USB_EPnFCR_FAEMSK (0x00400000) -#define MCF548X_USB_EPnFCR_IPMSK (0x00800000) -#define MCF548X_USB_EPnFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF548X_USB_EPnFCR_FRM (0x08000000) -#define MCF548X_USB_EPnFCR_TMR (0x10000000) -#define MCF548X_USB_EPnFCR_WFR (0x20000000) -#define MCF548X_USB_EPnFCR_SHAD (0x80000000) - -/* Bit definitions and macros for MCF548X_USB_EPnFAR */ -#define MCF548X_USB_EPnFAR_ALRMP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_USB_EPnFRP */ -#define MCF548X_USB_EPnFRP_RP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_USB_EPnFWP */ -#define MCF548X_USB_EPnFWP_WP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_USB_EPnLRFP */ -#define MCF548X_USB_EPnLRFP_LRFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_USB_EPnLWFP */ -#define MCF548X_USB_EPnLWFP_LWFP(x) (((x)&0x00000FFF)<<0) - - -/********************************************************************* -* -* Programmable Serial Controller (PSC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_PSC_MR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008600))) -#define MCF548X_PSC_SR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008604))) -#define MCF548X_PSC_CSR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008604))) -#define MCF548X_PSC_CR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008608))) -#define MCF548X_PSC_RB0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) -#define MCF548X_PSC_TB0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) -#define MCF548X_PSC_TB_8BIT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) -#define MCF548X_PSC_TB_16BIT0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) -#define MCF548X_PSC_TB_AC970 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860C))) -#define MCF548X_PSC_IPCR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008610))) -#define MCF548X_PSC_ACR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008610))) -#define MCF548X_PSC_ISR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008614))) -#define MCF548X_PSC_IMR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008614))) -#define MCF548X_PSC_CTUR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008618))) -#define MCF548X_PSC_CTLR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00861C))) -#define MCF548X_PSC_IP0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008634))) -#define MCF548X_PSC_OPSET0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008638))) -#define MCF548X_PSC_OPRESET0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00863C))) -#define MCF548X_PSC_SICR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008640))) -#define MCF548X_PSC_IRCR10 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008644))) -#define MCF548X_PSC_IRCR20 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008648))) -#define MCF548X_PSC_IRSDR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00864C))) -#define MCF548X_PSC_IRMDR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008650))) -#define MCF548X_PSC_IRFDR0 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008654))) -#define MCF548X_PSC_RFCNT0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008658))) -#define MCF548X_PSC_TFCNT0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00865C))) -#define MCF548X_PSC_RFSR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008664))) -#define MCF548X_PSC_TFSR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008684))) -#define MCF548X_PSC_RFCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008668))) -#define MCF548X_PSC_TFCR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008688))) -#define MCF548X_PSC_RFAR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00866E))) -#define MCF548X_PSC_TFAR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00868E))) -#define MCF548X_PSC_RFRP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008672))) -#define MCF548X_PSC_TFRP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008692))) -#define MCF548X_PSC_RFWP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008676))) -#define MCF548X_PSC_TFWP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008696))) -#define MCF548X_PSC_RLRFP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00867A))) -#define MCF548X_PSC_TLRFP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00869A))) -#define MCF548X_PSC_RLWFP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00867E))) -#define MCF548X_PSC_TLWFP0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00869E))) -#define MCF548X_PSC_MR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008700))) -#define MCF548X_PSC_SR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008704))) -#define MCF548X_PSC_CSR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008704))) -#define MCF548X_PSC_CR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008708))) -#define MCF548X_PSC_RB1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) -#define MCF548X_PSC_TB1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) -#define MCF548X_PSC_TB_8BIT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) -#define MCF548X_PSC_TB_16BIT1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) -#define MCF548X_PSC_TB_AC971 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00870C))) -#define MCF548X_PSC_IPCR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008710))) -#define MCF548X_PSC_ACR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008710))) -#define MCF548X_PSC_ISR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008714))) -#define MCF548X_PSC_IMR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008714))) -#define MCF548X_PSC_CTUR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008718))) -#define MCF548X_PSC_CTLR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00871C))) -#define MCF548X_PSC_IP1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008734))) -#define MCF548X_PSC_OPSET1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008738))) -#define MCF548X_PSC_OPRESET1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00873C))) -#define MCF548X_PSC_SICR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008740))) -#define MCF548X_PSC_IRCR11 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008744))) -#define MCF548X_PSC_IRCR21 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008748))) -#define MCF548X_PSC_IRSDR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00874C))) -#define MCF548X_PSC_IRMDR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008750))) -#define MCF548X_PSC_IRFDR1 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008754))) -#define MCF548X_PSC_RFCNT1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008758))) -#define MCF548X_PSC_TFCNT1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00875C))) -#define MCF548X_PSC_RFSR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008764))) -#define MCF548X_PSC_TFSR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008784))) -#define MCF548X_PSC_RFCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008768))) -#define MCF548X_PSC_TFCR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008788))) -#define MCF548X_PSC_RFAR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00876E))) -#define MCF548X_PSC_TFAR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00878E))) -#define MCF548X_PSC_RFRP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008772))) -#define MCF548X_PSC_TFRP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008792))) -#define MCF548X_PSC_RFWP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008776))) -#define MCF548X_PSC_TFWP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008796))) -#define MCF548X_PSC_RLRFP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00877A))) -#define MCF548X_PSC_TLRFP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00879A))) -#define MCF548X_PSC_RLWFP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00877E))) -#define MCF548X_PSC_TLWFP1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00879E))) -#define MCF548X_PSC_MR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008800))) -#define MCF548X_PSC_SR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008804))) -#define MCF548X_PSC_CSR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008804))) -#define MCF548X_PSC_CR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008808))) -#define MCF548X_PSC_RB2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) -#define MCF548X_PSC_TB2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) -#define MCF548X_PSC_TB_8BIT2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) -#define MCF548X_PSC_TB_16BIT2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) -#define MCF548X_PSC_TB_AC972 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00880C))) -#define MCF548X_PSC_IPCR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008810))) -#define MCF548X_PSC_ACR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008810))) -#define MCF548X_PSC_ISR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008814))) -#define MCF548X_PSC_IMR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008814))) -#define MCF548X_PSC_CTUR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008818))) -#define MCF548X_PSC_CTLR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00881C))) -#define MCF548X_PSC_IP2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008834))) -#define MCF548X_PSC_OPSET2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008838))) -#define MCF548X_PSC_OPRESET2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00883C))) -#define MCF548X_PSC_SICR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008840))) -#define MCF548X_PSC_IRCR12 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008844))) -#define MCF548X_PSC_IRCR22 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008848))) -#define MCF548X_PSC_IRSDR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00884C))) -#define MCF548X_PSC_IRMDR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008850))) -#define MCF548X_PSC_IRFDR2 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008854))) -#define MCF548X_PSC_RFCNT2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008858))) -#define MCF548X_PSC_TFCNT2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00885C))) -#define MCF548X_PSC_RFSR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008864))) -#define MCF548X_PSC_TFSR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008884))) -#define MCF548X_PSC_RFCR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008868))) -#define MCF548X_PSC_TFCR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008888))) -#define MCF548X_PSC_RFAR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00886E))) -#define MCF548X_PSC_TFAR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00888E))) -#define MCF548X_PSC_RFRP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008872))) -#define MCF548X_PSC_TFRP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008892))) -#define MCF548X_PSC_RFWP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008876))) -#define MCF548X_PSC_TFWP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008896))) -#define MCF548X_PSC_RLRFP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00887A))) -#define MCF548X_PSC_TLRFP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00889A))) -#define MCF548X_PSC_RLWFP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00887E))) -#define MCF548X_PSC_TLWFP2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00889E))) -#define MCF548X_PSC_MR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008900))) -#define MCF548X_PSC_SR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008904))) -#define MCF548X_PSC_CSR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008904))) -#define MCF548X_PSC_CR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008908))) -#define MCF548X_PSC_RB3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) -#define MCF548X_PSC_TB3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) -#define MCF548X_PSC_TB_8BIT3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) -#define MCF548X_PSC_TB_16BIT3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) -#define MCF548X_PSC_TB_AC973 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00890C))) -#define MCF548X_PSC_IPCR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008910))) -#define MCF548X_PSC_ACR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008910))) -#define MCF548X_PSC_ISR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008914))) -#define MCF548X_PSC_IMR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008914))) -#define MCF548X_PSC_CTUR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008918))) -#define MCF548X_PSC_CTLR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00891C))) -#define MCF548X_PSC_IP3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008934))) -#define MCF548X_PSC_OPSET3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008938))) -#define MCF548X_PSC_OPRESET3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00893C))) -#define MCF548X_PSC_SICR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008940))) -#define MCF548X_PSC_IRCR13 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008944))) -#define MCF548X_PSC_IRCR23 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008948))) -#define MCF548X_PSC_IRSDR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00894C))) -#define MCF548X_PSC_IRMDR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008950))) -#define MCF548X_PSC_IRFDR3 (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008954))) -#define MCF548X_PSC_RFCNT3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008958))) -#define MCF548X_PSC_TFCNT3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00895C))) -#define MCF548X_PSC_RFSR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008964))) -#define MCF548X_PSC_TFSR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008984))) -#define MCF548X_PSC_RFCR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008968))) -#define MCF548X_PSC_TFCR3 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008988))) -#define MCF548X_PSC_RFAR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00896E))) -#define MCF548X_PSC_TFAR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00898E))) -#define MCF548X_PSC_RFRP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008972))) -#define MCF548X_PSC_TFRP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008992))) -#define MCF548X_PSC_RFWP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008976))) -#define MCF548X_PSC_TFWP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008996))) -#define MCF548X_PSC_RLRFP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00897A))) -#define MCF548X_PSC_TLRFP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00899A))) -#define MCF548X_PSC_RLWFP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00897E))) -#define MCF548X_PSC_TLWFP3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00899E))) -#define MCF548X_PSC_MR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008600U+((x)*0x100)))) -#define MCF548X_PSC_SR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008604U+((x)*0x100)))) -#define MCF548X_PSC_CSR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008604U+((x)*0x100)))) -#define MCF548X_PSC_CR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008608U+((x)*0x100)))) -#define MCF548X_PSC_RB(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) -#define MCF548X_PSC_TB(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) -#define MCF548X_PSC_TB_8BIT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) -#define MCF548X_PSC_TB_16BIT(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) -#define MCF548X_PSC_TB_AC97(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00860CU+((x)*0x100)))) -#define MCF548X_PSC_IPCR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008610U+((x)*0x100)))) -#define MCF548X_PSC_ACR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008610U+((x)*0x100)))) -#define MCF548X_PSC_ISR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008614U+((x)*0x100)))) -#define MCF548X_PSC_IMR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008614U+((x)*0x100)))) -#define MCF548X_PSC_CTUR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008618U+((x)*0x100)))) -#define MCF548X_PSC_CTLR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00861CU+((x)*0x100)))) -#define MCF548X_PSC_IP(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008634U+((x)*0x100)))) -#define MCF548X_PSC_OPSET(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008638U+((x)*0x100)))) -#define MCF548X_PSC_OPRESET(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00863CU+((x)*0x100)))) -#define MCF548X_PSC_SICR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008640U+((x)*0x100)))) -#define MCF548X_PSC_IRCR1(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008644U+((x)*0x100)))) -#define MCF548X_PSC_IRCR2(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008648U+((x)*0x100)))) -#define MCF548X_PSC_IRSDR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x00864CU+((x)*0x100)))) -#define MCF548X_PSC_IRMDR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008650U+((x)*0x100)))) -#define MCF548X_PSC_IRFDR(x) (*(volatile uint8_t *)((uintptr_t)__MBAR + (0x008654U+((x)*0x100)))) -#define MCF548X_PSC_RFCNT(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008658U+((x)*0x100)))) -#define MCF548X_PSC_TFCNT(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00865CU+((x)*0x100)))) -#define MCF548X_PSC_RFSR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008664U+((x)*0x100)))) -#define MCF548X_PSC_TFSR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008684U+((x)*0x100)))) -#define MCF548X_PSC_RFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008668U+((x)*0x100)))) -#define MCF548X_PSC_TFCR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008688U+((x)*0x100)))) -#define MCF548X_PSC_RFAR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00866EU+((x)*0x100)))) -#define MCF548X_PSC_TFAR(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00868EU+((x)*0x100)))) -#define MCF548X_PSC_RFRP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008672U+((x)*0x100)))) -#define MCF548X_PSC_TFRP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008692U+((x)*0x100)))) -#define MCF548X_PSC_RFWP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008676U+((x)*0x100)))) -#define MCF548X_PSC_TFWP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008696U+((x)*0x100)))) -#define MCF548X_PSC_RLRFP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00867AU+((x)*0x100)))) -#define MCF548X_PSC_TLRFP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00869AU+((x)*0x100)))) -#define MCF548X_PSC_RLWFP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00867EU+((x)*0x100)))) -#define MCF548X_PSC_TLWFP(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00869EU+((x)*0x100)))) - -/* Bit definitions and macros for MCF548X_PSC_MR */ -#define MCF548X_PSC_MR_BC(x) (((x)&0x03)<<0) -#define MCF548X_PSC_MR_PT (0x04) -#define MCF548X_PSC_MR_PM(x) (((x)&0x03)<<3) -#define MCF548X_PSC_MR_ERR (0x20) -#define MCF548X_PSC_MR_RXIRQ (0x40) -#define MCF548X_PSC_MR_RXRTS (0x80) -#define MCF548X_PSC_MR_SB(x) (((x)&0x0F)<<0) -#define MCF548X_PSC_MR_TXCTS (0x10) -#define MCF548X_PSC_MR_TXRTS (0x20) -#define MCF548X_PSC_MR_CM(x) (((x)&0x03)<<6) -#define MCF548X_PSC_MR_PM_MULTI_ADDR (0x1C) -#define MCF548X_PSC_MR_PM_MULTI_DATA (0x18) -#define MCF548X_PSC_MR_PM_NONE (0x10) -#define MCF548X_PSC_MR_PM_FORCE_HI (0x0C) -#define MCF548X_PSC_MR_PM_FORCE_LO (0x08) -#define MCF548X_PSC_MR_PM_ODD (0x04) -#define MCF548X_PSC_MR_PM_EVEN (0x00) -#define MCF548X_PSC_MR_BC_5 (0x00) -#define MCF548X_PSC_MR_BC_6 (0x01) -#define MCF548X_PSC_MR_BC_7 (0x02) -#define MCF548X_PSC_MR_BC_8 (0x03) -#define MCF548X_PSC_MR_CM_NORMAL (0x00) -#define MCF548X_PSC_MR_CM_ECHO (0x40) -#define MCF548X_PSC_MR_CM_LOCAL_LOOP (0x80) -#define MCF548X_PSC_MR_CM_REMOTE_LOOP (0xC0) -#define MCF548X_PSC_MR_SB_STOP_BITS_1 (0x07) -#define MCF548X_PSC_MR_SB_STOP_BITS_15 (0x08) -#define MCF548X_PSC_MR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF548X_PSC_SR */ -#define MCF548X_PSC_SR_ERR (0x0040) -#define MCF548X_PSC_SR_CDE_DEOF (0x0080) -#define MCF548X_PSC_SR_RXRDY (0x0100) -#define MCF548X_PSC_SR_FU (0x0200) -#define MCF548X_PSC_SR_TXRDY (0x0400) -#define MCF548X_PSC_SR_TXEMP_URERR (0x0800) -#define MCF548X_PSC_SR_OE (0x1000) -#define MCF548X_PSC_SR_PE_CRCERR (0x2000) -#define MCF548X_PSC_SR_FE_PHYERR (0x4000) -#define MCF548X_PSC_SR_RB_NEOF (0x8000) - -/* Bit definitions and macros for MCF548X_PSC_CSR */ -#define MCF548X_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0) -#define MCF548X_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4) -#define MCF548X_PSC_CSR_RCSEL_SYS_CLK (0xD0) -#define MCF548X_PSC_CSR_RCSEL_CTM16 (0xE0) -#define MCF548X_PSC_CSR_RCSEL_CTM (0xF0) -#define MCF548X_PSC_CSR_TCSEL_SYS_CLK (0x0D) -#define MCF548X_PSC_CSR_TCSEL_CTM16 (0x0E) -#define MCF548X_PSC_CSR_TCSEL_CTM (0x0F) - -/* Bit definitions and macros for MCF548X_PSC_CR */ -#define MCF548X_PSC_CR_RXC(x) (((x)&0x03)<<0) -#define MCF548X_PSC_CR_TXC(x) (((x)&0x03)<<2) -#define MCF548X_PSC_CR_MISC(x) (((x)&0x07)<<4) -#define MCF548X_PSC_CR_NONE (0x00) -#define MCF548X_PSC_CR_STOP_BREAK (0x70) -#define MCF548X_PSC_CR_START_BREAK (0x60) -#define MCF548X_PSC_CR_BKCHGINT (0x50) -#define MCF548X_PSC_CR_RESET_ERROR (0x40) -#define MCF548X_PSC_CR_RESET_TX (0x30) -#define MCF548X_PSC_CR_RESET_RX (0x20) -#define MCF548X_PSC_CR_RESET_MR (0x10) -#define MCF548X_PSC_CR_TX_DISABLED (0x08) -#define MCF548X_PSC_CR_TX_ENABLED (0x04) -#define MCF548X_PSC_CR_RX_DISABLED (0x02) -#define MCF548X_PSC_CR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF548X_PSC_TB_8BIT */ -#define MCF548X_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0) -#define MCF548X_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8) -#define MCF548X_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16) -#define MCF548X_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF548X_PSC_TB_16BIT */ -#define MCF548X_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF548X_PSC_TB_AC97 */ -#define MCF548X_PSC_TB_AC97_SOF (0x00000800) -#define MCF548X_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12) - -/* Bit definitions and macros for MCF548X_PSC_IPCR */ -#define MCF548X_PSC_IPCR_RESERVED (0x0C) -#define MCF548X_PSC_IPCR_CTS (0x0D) -#define MCF548X_PSC_IPCR_D_CTS (0x1C) -#define MCF548X_PSC_IPCR_SYNC (0x8C) - -/* Bit definitions and macros for MCF548X_PSC_ACR */ -#define MCF548X_PSC_ACR_IEC0 (0x01) -#define MCF548X_PSC_ACR_CTMS(x) (((x)&0x07)<<4) -#define MCF548X_PSC_ACR_BRG (0x80) - -/* Bit definitions and macros for MCF548X_PSC_ISR */ -#define MCF548X_PSC_ISR_ERR (0x0040) -#define MCF548X_PSC_ISR_DEOF (0x0080) -#define MCF548X_PSC_ISR_TXRDY (0x0100) -#define MCF548X_PSC_ISR_RXRDY_FU (0x0200) -#define MCF548X_PSC_ISR_DB (0x0400) -#define MCF548X_PSC_ISR_IPC (0x8000) - -/* Bit definitions and macros for MCF548X_PSC_IMR */ -#define MCF548X_PSC_IMR_ERR (0x0040) -#define MCF548X_PSC_IMR_DEOF (0x0080) -#define MCF548X_PSC_IMR_TXRDY (0x0100) -#define MCF548X_PSC_IMR_RXRDY_FU (0x0200) -#define MCF548X_PSC_IMR_DB (0x0400) -#define MCF548X_PSC_IMR_IPC (0x8000) - -/* Bit definitions and macros for MCF548X_PSC_IP */ -#define MCF548X_PSC_IP_CTS (0x01) -#define MCF548X_PSC_IP_TGL (0x40) -#define MCF548X_PSC_IP_LWPR_B (0x80) - -/* Bit definitions and macros for MCF548X_PSC_OPSET */ -#define MCF548X_PSC_OPSET_RTS (0x01) - -/* Bit definitions and macros for MCF548X_PSC_OPRESET */ -#define MCF548X_PSC_OPRESET_RTS (0x01) - -/* Bit definitions and macros for MCF548X_PSC_SICR */ -#define MCF548X_PSC_SICR_SIM(x) (((x)&0x07)<<0) -#define MCF548X_PSC_SICR_SHDIR (0x10) -#define MCF548X_PSC_SICR_DTS (0x20) -#define MCF548X_PSC_SICR_AWR (0x40) -#define MCF548X_PSC_SICR_ACRB (0x80) -#define MCF548X_PSC_SICR_SIM_UART (0x00) -#define MCF548X_PSC_SICR_SIM_MODEM8 (0x01) -#define MCF548X_PSC_SICR_SIM_MODEM16 (0x02) -#define MCF548X_PSC_SICR_SIM_AC97 (0x03) -#define MCF548X_PSC_SICR_SIM_SIR (0x04) -#define MCF548X_PSC_SICR_SIM_MIR (0x05) -#define MCF548X_PSC_SICR_SIM_FIR (0x06) - -/* Bit definitions and macros for MCF548X_PSC_IRCR1 */ -#define MCF548X_PSC_IRCR1_SPUL (0x01) -#define MCF548X_PSC_IRCR1_SIPEN (0x02) -#define MCF548X_PSC_IRCR1_FD (0x04) - -/* Bit definitions and macros for MCF548X_PSC_IRCR2 */ -#define MCF548X_PSC_IRCR2_NXTEOF (0x01) -#define MCF548X_PSC_IRCR2_ABORT (0x02) -#define MCF548X_PSC_IRCR2_SIPREQ (0x04) - -/* Bit definitions and macros for MCF548X_PSC_IRMDR */ -#define MCF548X_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0) -#define MCF548X_PSC_IRMDR_FREQ (0x80) - -/* Bit definitions and macros for MCF548X_PSC_IRFDR */ -#define MCF548X_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF548X_PSC_RFCNT */ -#define MCF548X_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF548X_PSC_TFCNT */ -#define MCF548X_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF548X_PSC_RFSR */ -#define MCF548X_PSC_RFSR_EMT (0x0001) -#define MCF548X_PSC_RFSR_ALARM (0x0002) -#define MCF548X_PSC_RFSR_FU (0x0004) -#define MCF548X_PSC_RFSR_FRMRY (0x0008) -#define MCF548X_PSC_RFSR_OF (0x0010) -#define MCF548X_PSC_RFSR_UF (0x0020) -#define MCF548X_PSC_RFSR_RXW (0x0040) -#define MCF548X_PSC_RFSR_FAE (0x0080) -#define MCF548X_PSC_RFSR_FRM(x) (((x)&0x000F)<<8) -#define MCF548X_PSC_RFSR_TAG (0x1000) -#define MCF548X_PSC_RFSR_TXW (0x4000) -#define MCF548X_PSC_RFSR_IP (0x8000) -#define MCF548X_PSC_RFSR_FRM_BYTE0 (0x0800) -#define MCF548X_PSC_RFSR_FRM_BYTE1 (0x0400) -#define MCF548X_PSC_RFSR_FRM_BYTE2 (0x0200) -#define MCF548X_PSC_RFSR_FRM_BYTE3 (0x0100) - -/* Bit definitions and macros for MCF548X_PSC_TFSR */ -#define MCF548X_PSC_TFSR_EMT (0x0001) -#define MCF548X_PSC_TFSR_ALARM (0x0002) -#define MCF548X_PSC_TFSR_FU (0x0004) -#define MCF548X_PSC_TFSR_FRMRY (0x0008) -#define MCF548X_PSC_TFSR_OF (0x0010) -#define MCF548X_PSC_TFSR_UF (0x0020) -#define MCF548X_PSC_TFSR_RXW (0x0040) -#define MCF548X_PSC_TFSR_FAE (0x0080) -#define MCF548X_PSC_TFSR_FRM(x) (((x)&0x000F)<<8) -#define MCF548X_PSC_TFSR_TAG (0x1000) -#define MCF548X_PSC_TFSR_TXW (0x4000) -#define MCF548X_PSC_TFSR_IP (0x8000) -#define MCF548X_PSC_TFSR_FRM_BYTE0 (0x0800) -#define MCF548X_PSC_TFSR_FRM_BYTE1 (0x0400) -#define MCF548X_PSC_TFSR_FRM_BYTE2 (0x0200) -#define MCF548X_PSC_TFSR_FRM_BYTE3 (0x0100) - -/* Bit definitions and macros for MCF548X_PSC_RFCR */ -#define MCF548X_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_PSC_RFCR_TXW_MSK (0x00040000) -#define MCF548X_PSC_RFCR_OF_MSK (0x00080000) -#define MCF548X_PSC_RFCR_UF_MSK (0x00100000) -#define MCF548X_PSC_RFCR_RXW_MSK (0x00200000) -#define MCF548X_PSC_RFCR_FAE_MSK (0x00400000) -#define MCF548X_PSC_RFCR_IP_MSK (0x00800000) -#define MCF548X_PSC_RFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF548X_PSC_RFCR_FRMEN (0x08000000) -#define MCF548X_PSC_RFCR_TIMER (0x10000000) -#define MCF548X_PSC_RFCR_WRITETAG (0x20000000) -#define MCF548X_PSC_RFCR_SHADOW (0x80000000) - -/* Bit definitions and macros for MCF548X_PSC_TFCR */ -#define MCF548X_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_PSC_TFCR_TXW_MSK (0x00040000) -#define MCF548X_PSC_TFCR_OF_MSK (0x00080000) -#define MCF548X_PSC_TFCR_UF_MSK (0x00100000) -#define MCF548X_PSC_TFCR_RXW_MSK (0x00200000) -#define MCF548X_PSC_TFCR_FAE_MSK (0x00400000) -#define MCF548X_PSC_TFCR_IP_MSK (0x00800000) -#define MCF548X_PSC_TFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF548X_PSC_TFCR_FRMEN (0x08000000) -#define MCF548X_PSC_TFCR_TIMER (0x10000000) -#define MCF548X_PSC_TFCR_WRITETAG (0x20000000) -#define MCF548X_PSC_TFCR_SHADOW (0x80000000) - -/* Bit definitions and macros for MCF548X_PSC_RFAR */ -#define MCF548X_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF548X_PSC_TFAR */ -#define MCF548X_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF548X_PSC_RFRP */ -#define MCF548X_PSC_RFRP_READ(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF548X_PSC_TFRP */ -#define MCF548X_PSC_TFRP_READ(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF548X_PSC_RFWP */ -#define MCF548X_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF548X_PSC_TFWP */ -#define MCF548X_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF548X_PSC_RLRFP */ -#define MCF548X_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF548X_PSC_TLRFP */ -#define MCF548X_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF548X_PSC_RLWFP */ -#define MCF548X_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF548X_PSC_TLWFP */ -#define MCF548X_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0) - - -/********************************************************************* -* -* 32KByte System SRAM (SRAM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_SRAM_SSCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFC0))) -#define MCF548X_SRAM_TCCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFC4))) -#define MCF548X_SRAM_TCCRDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFC8))) -#define MCF548X_SRAM_TCCRDW (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFCC))) -#define MCF548X_SRAM_TCCRSEC (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x01FFD0))) - -/* Bit definitions and macros for MCF548X_SRAM_SSCR */ -#define MCF548X_SRAM_SSCR_INLV (0x00010000) - -/* Bit definitions and macros for MCF548X_SRAM_TCCR */ -#define MCF548X_SRAM_TCCR_BANK0_TC(x) (((x)&0x0000000F)<<0) -#define MCF548X_SRAM_TCCR_BANK1_TC(x) (((x)&0x0000000F)<<8) -#define MCF548X_SRAM_TCCR_BANK2_TC(x) (((x)&0x0000000F)<<16) -#define MCF548X_SRAM_TCCR_BANK3_TC(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF548X_SRAM_TCCRDR */ -#define MCF548X_SRAM_TCCRDR_BANK0_TC(x) (((x)&0x0000000F)<<0) -#define MCF548X_SRAM_TCCRDR_BANK1_TC(x) (((x)&0x0000000F)<<8) -#define MCF548X_SRAM_TCCRDR_BANK2_TC(x) (((x)&0x0000000F)<<16) -#define MCF548X_SRAM_TCCRDR_BANK3_TC(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF548X_SRAM_TCCRDW */ -#define MCF548X_SRAM_TCCRDW_BANK0_TC(x) (((x)&0x0000000F)<<0) -#define MCF548X_SRAM_TCCRDW_BANK1_TC(x) (((x)&0x0000000F)<<8) -#define MCF548X_SRAM_TCCRDW_BANK2_TC(x) (((x)&0x0000000F)<<16) -#define MCF548X_SRAM_TCCRDW_BANK3_TC(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF548X_SRAM_TCCRSEC */ -#define MCF548X_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0x0000000F)<<0) -#define MCF548X_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0x0000000F)<<8) -#define MCF548X_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0x0000000F)<<16) -#define MCF548X_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0x0000000F)<<24) - - -/********************************************************************* -* -* PCI Bus Controller (PCI) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_PCI_PCIIDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B00))) -#define MCF548X_PCI_PCISCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B04))) -#define MCF548X_PCI_PCICCRIR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B08))) -#define MCF548X_PCI_PCICR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B0C))) -#define MCF548X_PCI_PCIBAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B10))) -#define MCF548X_PCI_PCIBAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B14))) -#define MCF548X_PCI_PCICR2 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B3C))) -#define MCF548X_PCI_PCIGSCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B60))) -#define MCF548X_PCI_PCITBATR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B64))) -#define MCF548X_PCI_PCITBATR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B68))) -#define MCF548X_PCI_PCITCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B6C))) -#define MCF548X_PCI_PCIIW0BTAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B70))) -#define MCF548X_PCI_PCIIW1BTAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B74))) -#define MCF548X_PCI_PCIIW2BTAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B78))) -#define MCF548X_PCI_PCIIWCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B80))) -#define MCF548X_PCI_PCIICR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B84))) -#define MCF548X_PCI_PCIISR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000B88))) -#define MCF548X_PCI_PCICAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000BF8))) -#define MCF548X_PCI_PCITPSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008400))) -#define MCF548X_PCI_PCITSAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008404))) -#define MCF548X_PCI_PCITTCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008408))) -#define MCF548X_PCI_PCITER (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00840C))) -#define MCF548X_PCI_PCITNAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008410))) -#define MCF548X_PCI_PCITLWR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008414))) -#define MCF548X_PCI_PCITDCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008418))) -#define MCF548X_PCI_PCITSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00841C))) -#define MCF548X_PCI_PCITFDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008440))) -#define MCF548X_PCI_PCITFSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008444))) -#define MCF548X_PCI_PCITFCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008448))) -#define MCF548X_PCI_PCITFAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00844C))) -#define MCF548X_PCI_PCITFRPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008450))) -#define MCF548X_PCI_PCITFWPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008454))) -#define MCF548X_PCI_PCIRPSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008480))) -#define MCF548X_PCI_PCIRSAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008484))) -#define MCF548X_PCI_PCIRTCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008488))) -#define MCF548X_PCI_PCIRER (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00848C))) -#define MCF548X_PCI_PCIRNAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008490))) -#define MCF548X_PCI_PCIRDCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008498))) -#define MCF548X_PCI_PCIRSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00849C))) -#define MCF548X_PCI_PCIRFDR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084C0))) -#define MCF548X_PCI_PCIRFSR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084C4))) -#define MCF548X_PCI_PCIRFCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084C8))) -#define MCF548X_PCI_PCIRFAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084CC))) -#define MCF548X_PCI_PCIRFRPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084D0))) -#define MCF548X_PCI_PCIRFWPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x0084D4))) - -/* Bit definitions and macros for MCF548X_PCI_PCIIDR */ -#define MCF548X_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF548X_PCI_PCISCR */ -#define MCF548X_PCI_PCISCR_M (0x00000002) -#define MCF548X_PCI_PCISCR_B (0x00000004) -#define MCF548X_PCI_PCISCR_SP (0x00000008) -#define MCF548X_PCI_PCISCR_MW (0x00000010) -#define MCF548X_PCI_PCISCR_PER (0x00000040) -#define MCF548X_PCI_PCISCR_S (0x00000100) -#define MCF548X_PCI_PCISCR_F (0x00000200) -#define MCF548X_PCI_PCISCR_C (0x00100000) -#define MCF548X_PCI_PCISCR_66M (0x00200000) -#define MCF548X_PCI_PCISCR_R (0x00400000) -#define MCF548X_PCI_PCISCR_FC (0x00800000) -#define MCF548X_PCI_PCISCR_DP (0x01000000) -#define MCF548X_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25) -#define MCF548X_PCI_PCISCR_TS (0x08000000) -#define MCF548X_PCI_PCISCR_TR (0x10000000) -#define MCF548X_PCI_PCISCR_MA (0x20000000) -#define MCF548X_PCI_PCISCR_SE (0x40000000) -#define MCF548X_PCI_PCISCR_PE (0x80000000) - -/* Bit definitions and macros for MCF548X_PCI_PCICCRIR */ -#define MCF548X_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0) -#define MCF548X_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8) - -/* Bit definitions and macros for MCF548X_PCI_PCICR1 */ -#define MCF548X_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0) -#define MCF548X_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8) -#define MCF548X_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16) -#define MCF548X_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF548X_PCI_PCIBAR0 */ -#define MCF548X_PCI_PCIBAR0_IO (0x00000001) -#define MCF548X_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1) -#define MCF548X_PCI_PCIBAR0_PREF (0x00000008) -#define MCF548X_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF548X_PCI_PCIBAR1 */ -#define MCF548X_PCI_PCIBAR1_IO (0x00000001) -#define MCF548X_PCI_PCIBAR1_PREF (0x00000008) -#define MCF548X_PCI_PCIBAR1_BAR1(x) (((x)&0x00000003)<<30) - -/* Bit definitions and macros for MCF548X_PCI_PCICR2 */ -#define MCF548X_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0) -#define MCF548X_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8) -#define MCF548X_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16) -#define MCF548X_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF548X_PCI_PCIGSCR */ -#define MCF548X_PCI_PCIGSCR_PR (0x00000001) -#define MCF548X_PCI_PCIGSCR_SEE (0x00001000) -#define MCF548X_PCI_PCIGSCR_PEE (0x00002000) -#define MCF548X_PCI_PCIGSCR_SE (0x10000000) -#define MCF548X_PCI_PCIGSCR_PE (0x20000000) - -/* Bit definitions and macros for MCF548X_PCI_PCITBATR0 */ -#define MCF548X_PCI_PCITBATR0_EN (0x00000001) -#define MCF548X_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF548X_PCI_PCITBATR1 */ -#define MCF548X_PCI_PCITBATR1_EN (0x00000001) -#define MCF548X_PCI_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30) - -/* Bit definitions and macros for MCF548X_PCI_PCITCR */ -#define MCF548X_PCI_PCITCR_P (0x00010000) -#define MCF548X_PCI_PCITCR_LD (0x01000000) - -/* Bit definitions and macros for MCF548X_PCI_PCIIW0BTAR */ -#define MCF548X_PCI_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8) -#define MCF548X_PCI_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16) -#define MCF548X_PCI_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF548X_PCI_PCIIW1BTAR */ -#define MCF548X_PCI_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8) -#define MCF548X_PCI_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16) -#define MCF548X_PCI_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF548X_PCI_PCIIW2BTAR */ -#define MCF548X_PCI_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8) -#define MCF548X_PCI_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16) -#define MCF548X_PCI_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF548X_PCI_PCIIWCR */ -#define MCF548X_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8) -#define MCF548X_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16) -#define MCF548X_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24) -#define MCF548X_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000) -#define MCF548X_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000) -#define MCF548X_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000) -#define MCF548X_PCI_PCIIWCR_WINCTRL0_IO (0x09000000) -#define MCF548X_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000) -#define MCF548X_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000) -#define MCF548X_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000) -#define MCF548X_PCI_PCIIWCR_WINCTRL1_IO (0x00090000) -#define MCF548X_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100) -#define MCF548X_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300) -#define MCF548X_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500) -#define MCF548X_PCI_PCIIWCR_WINCTRL2_IO (0x00000900) - -/* Bit definitions and macros for MCF548X_PCI_PCIICR */ -#define MCF548X_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0) -#define MCF548X_PCI_PCIICR_TAE (0x01000000) -#define MCF548X_PCI_PCIICR_IAE (0x02000000) -#define MCF548X_PCI_PCIICR_REE (0x04000000) - -/* Bit definitions and macros for MCF548X_PCI_PCIISR */ -#define MCF548X_PCI_PCIISR_TA (0x01000000) -#define MCF548X_PCI_PCIISR_IA (0x02000000) -#define MCF548X_PCI_PCIISR_RE (0x04000000) - -/* Bit definitions and macros for MCF548X_PCI_PCICAR */ -#define MCF548X_PCI_PCICAR_DWORD(x) (((x)&0x0000003F)<<2) -#define MCF548X_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8) -#define MCF548X_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11) -#define MCF548X_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16) -#define MCF548X_PCI_PCICAR_E (0x80000000) - -/* Bit definitions and macros for MCF548X_PCI_PCITPSR */ -#define MCF548X_PCI_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF548X_PCI_PCITTCR */ -#define MCF548X_PCI_PCITTCR_DI (0x00000001) -#define MCF548X_PCI_PCITTCR_W (0x00000010) -#define MCF548X_PCI_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8) -#define MCF548X_PCI_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) -#define MCF548X_PCI_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF548X_PCI_PCITER */ -#define MCF548X_PCI_PCITER_NE (0x00010000) -#define MCF548X_PCI_PCITER_IAE (0x00020000) -#define MCF548X_PCI_PCITER_TAE (0x00040000) -#define MCF548X_PCI_PCITER_RE (0x00080000) -#define MCF548X_PCI_PCITER_SE (0x00100000) -#define MCF548X_PCI_PCITER_FEE (0x00200000) -#define MCF548X_PCI_PCITER_ME (0x01000000) -#define MCF548X_PCI_PCITER_BE (0x08000000) -#define MCF548X_PCI_PCITER_CM (0x10000000) -#define MCF548X_PCI_PCITER_RF (0x40000000) -#define MCF548X_PCI_PCITER_RC (0x80000000) - -/* Bit definitions and macros for MCF548X_PCI_PCITDCR */ -#define MCF548X_PCI_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_PCI_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF548X_PCI_PCITSR */ -#define MCF548X_PCI_PCITSR_IA (0x00010000) -#define MCF548X_PCI_PCITSR_TA (0x00020000) -#define MCF548X_PCI_PCITSR_RE (0x00040000) -#define MCF548X_PCI_PCITSR_SE (0x00080000) -#define MCF548X_PCI_PCITSR_FE (0x00100000) -#define MCF548X_PCI_PCITSR_BE1 (0x00200000) -#define MCF548X_PCI_PCITSR_BE2 (0x00400000) -#define MCF548X_PCI_PCITSR_BE3 (0x00800000) -#define MCF548X_PCI_PCITSR_NT (0x01000000) - -/* Bit definitions and macros for MCF548X_PCI_PCITFSR */ -#define MCF548X_PCI_PCITFSR_EMT (0x00010000) -#define MCF548X_PCI_PCITFSR_ALARM (0x00020000) -#define MCF548X_PCI_PCITFSR_FU (0x00040000) -#define MCF548X_PCI_PCITFSR_FR (0x00080000) -#define MCF548X_PCI_PCITFSR_OF (0x00100000) -#define MCF548X_PCI_PCITFSR_UF (0x00200000) -#define MCF548X_PCI_PCITFSR_RXW (0x00400000) - -/* Bit definitions and macros for MCF548X_PCI_PCITFCR */ -#define MCF548X_PCI_PCITFCR_OF_MSK (0x00080000) -#define MCF548X_PCI_PCITFCR_UF_MSK (0x00100000) -#define MCF548X_PCI_PCITFCR_RXW_MSK (0x00200000) -#define MCF548X_PCI_PCITFCR_FAE_MSK (0x00400000) -#define MCF548X_PCI_PCITFCR_IP_MSK (0x00800000) -#define MCF548X_PCI_PCITFCR_GR(x) (((x)&0x00000007)<<24) - -/* Bit definitions and macros for MCF548X_PCI_PCITFAR */ -#define MCF548X_PCI_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0) - -/* Bit definitions and macros for MCF548X_PCI_PCITFRPR */ -#define MCF548X_PCI_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_PCI_PCITFWPR */ -#define MCF548X_PCI_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_PCI_PCIRPSR */ -#define MCF548X_PCI_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF548X_PCI_PCIRTCR */ -#define MCF548X_PCI_PCIRTCR_DI (0x00000001) -#define MCF548X_PCI_PCIRTCR_W (0x00000010) -#define MCF548X_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8) -#define MCF548X_PCI_PCIRTCR_FB (0x00001000) -#define MCF548X_PCI_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) -#define MCF548X_PCI_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF548X_PCI_PCIRER */ -#define MCF548X_PCI_PCIRER_NE (0x00010000) -#define MCF548X_PCI_PCIRER_IAE (0x00020000) -#define MCF548X_PCI_PCIRER_TAE (0x00040000) -#define MCF548X_PCI_PCIRER_RE (0x00080000) -#define MCF548X_PCI_PCIRER_SE (0x00100000) -#define MCF548X_PCI_PCIRER_FEE (0x00200000) -#define MCF548X_PCI_PCIRER_ME (0x01000000) -#define MCF548X_PCI_PCIRER_BE (0x08000000) -#define MCF548X_PCI_PCIRER_CM (0x10000000) -#define MCF548X_PCI_PCIRER_FE (0x20000000) -#define MCF548X_PCI_PCIRER_RF (0x40000000) -#define MCF548X_PCI_PCIRER_RC (0x80000000) - -/* Bit definitions and macros for MCF548X_PCI_PCIRDCR */ -#define MCF548X_PCI_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) -#define MCF548X_PCI_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF548X_PCI_PCIRSR */ -#define MCF548X_PCI_PCIRSR_IA (0x00010000) -#define MCF548X_PCI_PCIRSR_TA (0x00020000) -#define MCF548X_PCI_PCIRSR_RE (0x00040000) -#define MCF548X_PCI_PCIRSR_SE (0x00080000) -#define MCF548X_PCI_PCIRSR_FE (0x00100000) -#define MCF548X_PCI_PCIRSR_BE1 (0x00200000) -#define MCF548X_PCI_PCIRSR_BE2 (0x00400000) -#define MCF548X_PCI_PCIRSR_BE3 (0x00800000) -#define MCF548X_PCI_PCIRSR_NT (0x01000000) - -/* Bit definitions and macros for MCF548X_PCI_PCIRFSR */ -#define MCF548X_PCI_PCIRFSR_EMT (0x00010000) -#define MCF548X_PCI_PCIRFSR_ALARM (0x00020000) -#define MCF548X_PCI_PCIRFSR_FU (0x00040000) -#define MCF548X_PCI_PCIRFSR_FR (0x00080000) -#define MCF548X_PCI_PCIRFSR_OF (0x00100000) -#define MCF548X_PCI_PCIRFSR_UF (0x00200000) -#define MCF548X_PCI_PCIRFSR_RXW (0x00400000) - -/* Bit definitions and macros for MCF548X_PCI_PCIRFCR */ -#define MCF548X_PCI_PCIRFCR_OF_MSK (0x00080000) -#define MCF548X_PCI_PCIRFCR_UF_MSK (0x00100000) -#define MCF548X_PCI_PCIRFCR_RXW_MSK (0x00200000) -#define MCF548X_PCI_PCIRFCR_FAE_MSK (0x00400000) -#define MCF548X_PCI_PCIRFCR_IP_MSK (0x00800000) -#define MCF548X_PCI_PCIRFCR_GR(x) (((x)&0x00000007)<<24) - -/* Bit definitions and macros for MCF548X_PCI_PCIRFAR */ -#define MCF548X_PCI_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0) - -/* Bit definitions and macros for MCF548X_PCI_PCIRFRPR */ -#define MCF548X_PCI_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF548X_PCI_PCIRFWPR */ -#define MCF548X_PCI_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0) - - -/********************************************************************* -* -* PCI Arbiter Module (PCIARB) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_PCIARB_PACR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000C00))) -#define MCF548X_PCIARB_PASR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000C04))) - -/* Bit definitions and macros for MCF548X_PCIARB_PACR */ -#define MCF548X_PCIARB_PACR_INTMPRI (0x00000001) -#define MCF548X_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1) -#define MCF548X_PCIARB_PACR_INTMINTEN (0x00010000) -#define MCF548X_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17) -#define MCF548X_PCIARB_PACR_PKMD (0x40000000) -#define MCF548X_PCIARB_PACR_DS (0x80000000) - -/* Bit definitions and macros for MCF548X_PCIARB_PASR */ -#define MCF548X_PCIARB_PASR_ITLMBK (0x00010000) -#define MCF548X_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17) - - -/********************************************************************* -* -* Multi-Channel DMA (DMA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_DMA_TASKBAR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008000))) -#define MCF548X_DMA_CP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008004))) -#define MCF548X_DMA_EP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008008))) -#define MCF548X_DMA_VP (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00800C))) -#define MCF548X_DMA_DIPR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008014))) -#define MCF548X_DMA_DIMR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008018))) -#define MCF548X_DMA_TCR0 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00801C))) -#define MCF548X_DMA_TCR1 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00801E))) -#define MCF548X_DMA_TCR2 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008020))) -#define MCF548X_DMA_TCR3 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008022))) -#define MCF548X_DMA_TCR4 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008024))) -#define MCF548X_DMA_TCR5 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008026))) -#define MCF548X_DMA_TCR6 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008028))) -#define MCF548X_DMA_TCR7 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00802A))) -#define MCF548X_DMA_TCR8 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00802C))) -#define MCF548X_DMA_TCR9 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00802E))) -#define MCF548X_DMA_TCR10 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008030))) -#define MCF548X_DMA_TCR11 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008032))) -#define MCF548X_DMA_TCR12 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008034))) -#define MCF548X_DMA_TCR13 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008036))) -#define MCF548X_DMA_TCR14 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x008038))) -#define MCF548X_DMA_TCR15 (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00803A))) -#define MCF548X_DMA_TCRn(x) (*(volatile uint16_t*)((uintptr_t)__MBAR + (0x00801CU+((x)*0x002)))) -#define MCF548X_DMA_IMCR (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x00805C))) -#define MCF548X_DMA_PTDDBG (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x008080))) - -/* Bit definitions and macros for MCF548X_DMA_DIPR */ -#define MCF548X_DMA_DIPR_TASK0 (0x00000001) -#define MCF548X_DMA_DIPR_TASK1 (0x00000002) -#define MCF548X_DMA_DIPR_TASK2 (0x00000004) -#define MCF548X_DMA_DIPR_TASK3 (0x00000008) -#define MCF548X_DMA_DIPR_TASK4 (0x00000010) -#define MCF548X_DMA_DIPR_TASK5 (0x00000020) -#define MCF548X_DMA_DIPR_TASK6 (0x00000040) -#define MCF548X_DMA_DIPR_TASK7 (0x00000080) -#define MCF548X_DMA_DIPR_TASK8 (0x00000100) -#define MCF548X_DMA_DIPR_TASK9 (0x00000200) -#define MCF548X_DMA_DIPR_TASK10 (0x00000400) -#define MCF548X_DMA_DIPR_TASK11 (0x00000800) -#define MCF548X_DMA_DIPR_TASK12 (0x00001000) -#define MCF548X_DMA_DIPR_TASK13 (0x00002000) -#define MCF548X_DMA_DIPR_TASK14 (0x00004000) -#define MCF548X_DMA_DIPR_TASK15 (0x00008000) - -/* Bit definitions and macros for MCF548X_DMA_DIMR */ -#define MCF548X_DMA_DIMR_TASK0 (0x00000001) -#define MCF548X_DMA_DIMR_TASK1 (0x00000002) -#define MCF548X_DMA_DIMR_TASK2 (0x00000004) -#define MCF548X_DMA_DIMR_TASK3 (0x00000008) -#define MCF548X_DMA_DIMR_TASK4 (0x00000010) -#define MCF548X_DMA_DIMR_TASK5 (0x00000020) -#define MCF548X_DMA_DIMR_TASK6 (0x00000040) -#define MCF548X_DMA_DIMR_TASK7 (0x00000080) -#define MCF548X_DMA_DIMR_TASK8 (0x00000100) -#define MCF548X_DMA_DIMR_TASK9 (0x00000200) -#define MCF548X_DMA_DIMR_TASK10 (0x00000400) -#define MCF548X_DMA_DIMR_TASK11 (0x00000800) -#define MCF548X_DMA_DIMR_TASK12 (0x00001000) -#define MCF548X_DMA_DIMR_TASK13 (0x00002000) -#define MCF548X_DMA_DIMR_TASK14 (0x00004000) -#define MCF548X_DMA_DIMR_TASK15 (0x00008000) - -/* Bit definitions and macros for MCF548X_DMA_IMCR */ -#define MCF548X_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0) -#define MCF548X_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2) -#define MCF548X_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4) -#define MCF548X_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6) -#define MCF548X_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8) -#define MCF548X_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10) -#define MCF548X_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12) -#define MCF548X_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14) -#define MCF548X_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16) -#define MCF548X_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18) -#define MCF548X_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20) -#define MCF548X_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22) -#define MCF548X_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24) -#define MCF548X_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26) -#define MCF548X_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28) -#define MCF548X_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30) -#define MCF548X_DMA_IMCR_SRC16_FEC0RX (0x00000000) -#define MCF548X_DMA_IMCR_SRC17_FEC0TX (0x00000000) -#define MCF548X_DMA_IMCR_SRC18_FEC0RX (0x00000020) -#define MCF548X_DMA_IMCR_SRC19_FEC0TX (0x00000080) -#define MCF548X_DMA_IMCR_SRC20_FEC1RX (0x00000100) -#define MCF548X_DMA_IMCR_SRC21_DREQ1 (0x00000000) -#define MCF548X_DMA_IMCR_SRC21_FEC1TX (0x00000400) -#define MCF548X_DMA_IMCR_SRC22_FEC0RX (0x00001000) -#define MCF548X_DMA_IMCR_SRC23_FEC0TX (0x00004000) -#define MCF548X_DMA_IMCR_SRC24_CTM0 (0x00010000) -#define MCF548X_DMA_IMCR_SRC24_FEC1RX (0x00020000) -#define MCF548X_DMA_IMCR_SRC25_CTM1 (0x00040000) -#define MCF548X_DMA_IMCR_SRC25_FEC1TX (0x00080000) -#define MCF548X_DMA_IMCR_SRC26_USBEP4 (0x00000000) -#define MCF548X_DMA_IMCR_SRC26_CTM2 (0x00200000) -#define MCF548X_DMA_IMCR_SRC27_USBEP5 (0x00000000) -#define MCF548X_DMA_IMCR_SRC27_CTM3 (0x00800000) -#define MCF548X_DMA_IMCR_SRC28_USBEP6 (0x00000000) -#define MCF548X_DMA_IMCR_SRC28_CTM4 (0x01000000) -#define MCF548X_DMA_IMCR_SRC28_DREQ1 (0x02000000) -#define MCF548X_DMA_IMCR_SRC28_PSC2RX (0x03000000) -#define MCF548X_DMA_IMCR_SRC29_DREQ1 (0x04000000) -#define MCF548X_DMA_IMCR_SRC29_CTM5 (0x08000000) -#define MCF548X_DMA_IMCR_SRC29_PSC2TX (0x0C000000) -#define MCF548X_DMA_IMCR_SRC30_FEC1RX (0x00000000) -#define MCF548X_DMA_IMCR_SRC30_CTM6 (0x10000000) -#define MCF548X_DMA_IMCR_SRC30_PSC3RX (0x30000000) -#define MCF548X_DMA_IMCR_SRC31_FEC1TX (0x00000000) -#define MCF548X_DMA_IMCR_SRC31_CTM7 (0x80000000) -#define MCF548X_DMA_IMCR_SRC31_PSC3TX (0xC0000000) - - -/********************************************************************* -* -* Multi-Channel DMA External Requests (DMA_EREQ) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF548X_DMA_EREQ_EREQBAR0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D00))) -#define MCF548X_DMA_EREQ_EREQMASK0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D04))) -#define MCF548X_DMA_EREQ_EREQCTRL0 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D08))) -#define MCF548X_DMA_EREQ_EREQBAR1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D10))) -#define MCF548X_DMA_EREQ_EREQMASK1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D14))) -#define MCF548X_DMA_EREQ_EREQCTRL1 (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D18))) -#define MCF548X_DMA_EREQ_EREQBAR(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D00U+((x)*0x010)))) -#define MCF548X_DMA_EREQ_EREQMASK(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D04U+((x)*0x010)))) -#define MCF548X_DMA_EREQ_EREQCTRL(x) (*(volatile uint32_t*)((uintptr_t)__MBAR + (0x000D08U+((x)*0x010)))) - -/* Bit definitions and macros for MCF548X_DMA_EREQ_EREQCTRL */ -#define MCF548X_DMA_EREQ_EREQCTRL_EN (0x00000001) -#define MCF548X_DMA_EREQ_EREQCTRL_SYNC (0x00000002) -#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID(x) (((x)&0x00000003)<<2) -#define MCF548X_DMA_EREQ_EREQCTRL_BSEL(x) (((x)&0x00000003)<<4) -#define MCF548X_DMA_EREQ_EREQCTRL_MD(x) (((x)&0x00000003)<<6) -#define MCF548X_DMA_EREQ_EREQCTRL_MD_IDLE (0x00000000) -#define MCF548X_DMA_EREQ_EREQCTRL_MD_LEVEL (0x00000040) -#define MCF548X_DMA_EREQ_EREQCTRL_MD_EDGE (0x00000080) -#define MCF548X_DMA_EREQ_EREQCTRL_MD_PIPED (0x000000C0) -#define MCF548X_DMA_EREQ_EREQCTRL_BSEL_MEM_WRITE (0x00000000) -#define MCF548X_DMA_EREQ_EREQCTRL_BSEL_MEM_READ (0x00000010) -#define MCF548X_DMA_EREQ_EREQCTRL_BSEL_PERIPH_WRITE (0x00000020) -#define MCF548X_DMA_EREQ_EREQCTRL_BSEL_PERIPH_READ (0x00000030) -#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID_ONE (0x00000000) -#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID_TWO (0x00000004) -#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID_THREE (0x00000008) -#define MCF548X_DMA_EREQ_EREQCTRL_DACKWID_FOUR (0x0000000C) - -/*********************************************************************/ - -#endif /* __MCF548X_H__ */ diff --git a/c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_dma.h b/c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_dma.h deleted file mode 100644 index ea6f8863cb..0000000000 --- a/c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_dma.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - * File: MCD_dma.h - * Purpose: Main header file for multi-channel DMA API. - * - * Notes: - */ -#ifndef _MCD_API_H -#define _MCD_API_H - -/* - * Turn Execution Unit tasks ON (#define) or OFF (#undef) - */ -#define MCD_INCLUDE_EU - -/* - * Number of DMA channels - */ -#define NCHANNELS 16 - -/* - * Total number of variants - */ -#ifdef MCD_INCLUDE_EU -#define NUMOFVARIANTS 6 -#else -#define NUMOFVARIANTS 4 -#endif - -/* - * Define sizes of the various tables - */ -#define TASK_TABLE_SIZE (NCHANNELS*32) -#define VAR_TAB_SIZE (128) -#define CONTEXT_SAVE_SIZE (128) -#define FUNCDESC_TAB_SIZE (256) - -#ifdef MCD_INCLUDE_EU -#define FUNCDESC_TAB_NUM 16 -#else -#define FUNCDESC_TAB_NUM 1 -#endif - - -#ifndef DEFINESONLY - -/* - * Portability typedefs - */ -typedef int s32; -typedef unsigned int u32; -typedef short s16; -typedef unsigned short u16; -typedef char s8; -typedef unsigned char u8; - -/* - * These structures represent the internal registers of the - * multi-channel DMA - */ -struct dmaRegs_s { - u32 taskbar; /* task table base address register */ - u32 currPtr; - u32 endPtr; - u32 varTablePtr; - u16 dma_rsvd0; - u16 ptdControl; /* ptd control */ - u32 intPending; /* interrupt pending register */ - u32 intMask; /* interrupt mask register */ - u16 taskControl[16]; /* task control registers */ - u8 priority[32]; /* priority registers */ - u32 initiatorMux; /* initiator mux control */ - u32 taskSize0; /* task size control register 0. */ - u32 taskSize1; /* task size control register 1. */ - u32 dma_rsvd1; /* reserved */ - u32 dma_rsvd2; /* reserved */ - u32 debugComp1; /* debug comparator 1 */ - u32 debugComp2; /* debug comparator 2 */ - u32 debugControl; /* debug control */ - u32 debugStatus; /* debug status */ - u32 ptdDebug; /* priority task decode debug */ - u32 dma_rsvd3[31]; /* reserved */ -}; -typedef volatile struct dmaRegs_s dmaRegs; - -#endif - -/* - * PTD contrl reg bits - */ -#define PTD_CTL_TSK_PRI 0x8000 -#define PTD_CTL_COMM_PREFETCH 0x0001 - -/* - * Task Control reg bits and field masks - */ -#define TASK_CTL_EN 0x8000 -#define TASK_CTL_VALID 0x4000 -#define TASK_CTL_ALWAYS 0x2000 -#define TASK_CTL_INIT_MASK 0x1f00 -#define TASK_CTL_ASTRT 0x0080 -#define TASK_CTL_HIPRITSKEN 0x0040 -#define TASK_CTL_HLDINITNUM 0x0020 -#define TASK_CTL_ASTSKNUM_MASK 0x000f - -/* - * Priority reg bits and field masks - */ -#define PRIORITY_HLD 0x80 -#define PRIORITY_PRI_MASK 0x07 - -/* - * Debug Control reg bits and field masks - */ -#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 -#define DBG_CTL_AUTO_ARM 0x00008000 -#define DBG_CTL_BREAK 0x00004000 -#define DBG_CTL_COMP1_TYP_MASK 0x00003800 -#define DBG_CTL_COMP2_TYP_MASK 0x00000070 -#define DBG_CTL_EXT_BREAK 0x00000004 -#define DBG_CTL_INT_BREAK 0x00000002 - -/* - * PTD Debug reg selector addresses - * This reg must be written with a value to show the contents of - * one of the desired internal register. - */ -#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */ -#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and - have initiators asserted */ - - -/* - * General return values - */ -#define MCD_OK 0 -#define MCD_ERROR -1 -#define MCD_TABLE_UNALIGNED -2 -#define MCD_CHANNEL_INVALID -3 - -/* - * MCD_initDma input flags - */ -#define MCD_RELOC_TASKS 0x00000001 -#define MCD_NO_RELOC_TASKS 0x00000000 -#define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */ - -/* - * MCD_dmaStatus Status Values for each channel - */ -#define MCD_NO_DMA 1 /* No DMA has been requested since reset */ -#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */ -#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */ -#define MCD_PAUSED 4 /* DMA active but it is currently paused */ -#define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */ -#define MCD_DONE 6 /* the most recent DMA has completed. */ - - -/* - * MCD_startDma parameter defines - */ - -/* - * Constants for the funcDesc parameter - */ -/* Byte swapping: */ -#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */ -#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */ -#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of - each 32-bit data value being DMAed.*/ -#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each - 16-bit half of each 32-bit data value DMAed */ -#define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */ -#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */ -/* CRCing: */ -#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */ -#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */ -#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */ -#define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/ -#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */ - -#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM) -#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) - -/* - * Constants for the flags parameter - */ -#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ -#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ -#define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */ -#define MCD_TT_FLAGS_MASK 0x000000ff -#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) - -#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ -#define MCD_CHAIN_DMA /* TBD */ -#define MCD_EU_DMA /* TBD */ -#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ -#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ - - -/* these flags are valid for MCD_startDma and the chained buffer descriptors */ -#define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */ -#define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */ -#define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */ -#define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring - last byte of data in buffer */ -#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum - prior to performing the DMA. */ - -/* Defines for the FEC buffer descriptor control/status word*/ -#define MCD_FEC_BUF_READY 0x8000 -#define MCD_FEC_WRAP 0x2000 -#define MCD_FEC_INTERRUPT 0x1000 -#define MCD_FEC_END_FRAME 0x0800 - - -/* - * Defines for general intuitiveness - */ - -#define MCD_TRUE 1 -#define MCD_FALSE 0 - -/* - * Three different cases for destination and source. - */ -#define MINUS1 -1 -#define ZERO 0 -#define PLUS1 1 - -#ifndef DEFINESONLY - -/* Task Table Entry struct*/ -typedef struct { - u32 TDTstart; /* task descriptor table start */ - u32 TDTend; /* task descriptor table end */ - u32 varTab; /* variable table start */ - u32 FDTandFlags; /* function descriptor table start and flags */ - volatile u32 descAddrAndStatus; - volatile u32 modifiedVarTab; - u32 contextSaveSpace; /* context save space start */ - u32 literalBases; -} TaskTableEntry; - - -/* Chained buffer descriptor */ -typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; -struct MCD_bufDesc_struct { - u32 flags; /* flags describing the DMA */ - u32 csumResult; /* checksum from checksumming performed since last checksum reset */ - s8 *srcAddr; /* the address to move data from */ - s8 *destAddr; /* the address to move data to */ - s8 *lastDestAddr; /* the last address written to */ - u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */ - MCD_bufDesc *next; /* next buffer descriptor in chain */ - u32 info; /* private information about this descriptor; DMA does not affect it */ -}; - -/* Progress Query struct */ -typedef volatile struct MCD_XferProg_struct { - s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */ - s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */ - u32 dmaSize; /* the amount of data transferred for the current buffer */ - MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */ -} MCD_XferProg; - - -/* FEC buffer descriptor */ -typedef volatile struct MCD_bufDescFec_struct { - u16 statCtrl; - u16 length; - u32 dataPointer; -} MCD_bufDescFec; - - -/*************************************************************************/ -/* - * API function Prototypes - see MCD_dmaApi.c for further notes - */ - -/* - * MCD_startDma starts a particular kind of DMA . - */ -int MCD_startDma ( - int channel, /* the channel on which to run the DMA */ - s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */ - s16 srcIncr, /* the amount to increment the source address per transfer */ - s8 *destAddr, /* the address to move data to */ - s16 destIncr, /* the amount to increment the destination address per transfer */ - u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */ - u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ - u32 initiator, /* what device initiates the DMA */ - int priority, /* priority of the DMA */ - u32 flags, /* flags describing the DMA */ - u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ -); - -/* - * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA - * registers, relocating and creating the appropriate task structures, and - * setting up some global settings - */ -int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags); - -/* - * MCD_dmaStatus() returns the status of the DMA on the requested channel. - */ -int MCD_dmaStatus (int channel); - -/* - * MCD_XferProgrQuery() returns progress of DMA on requested channel - */ -int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep); - -/* - * MCD_killDma() halts the DMA on the requested channel, without any - * intention of resuming the DMA. - */ -int MCD_killDma (int channel); - -/* - * MCD_continDma() continues a DMA which as stopped due to encountering an - * unready buffer descriptor. - */ -int MCD_continDma (int channel); - -/* - * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is - * running on that channel). - */ -int MCD_pauseDma (int channel); - -/* - * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is - * running on that channel). - */ -int MCD_resumeDma (int channel); - -/* - * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA - */ -int MCD_csumQuery (int channel, u32 *csum); - -/* - * MCD_getCodeSize provides the packed size required by the microcoded task - * and structures. - */ -int MCD_getCodeSize(void); - -/* - * MCD_getVersion provides a pointer to a version string and returns a - * version number. - */ -int MCD_getVersion(char **longVersion); - -/* macro for setting a location in the variable table */ -#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value - /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, - so I'm avoiding surrounding it with "do {} while(0)" */ - -#endif /* DEFINESONLY */ - -#endif /* _MCD_API_H */ diff --git a/c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_progCheck.h b/c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_progCheck.h deleted file mode 100644 index e0f578fdaf..0000000000 --- a/c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_progCheck.h +++ /dev/null @@ -1,5 +0,0 @@ - /* This file is autogenerated. Do not change */ -#define CURRBD 4 -#define DCOUNT 6 -#define DESTPTR 5 -#define SRCPTR 7 diff --git a/c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_tasksInit.h b/c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_tasksInit.h deleted file mode 100644 index daf871cd6d..0000000000 --- a/c/src/lib/libcpu/m68k/mcf548x/mcdma/MCD_tasksInit.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef MCD_TSK_INIT_H -#define MCD_TSK_INIT_H 1 - -/* - * Do not edit! - */ - - -/* - * Task 0 - */ -void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 1 - */ -void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 2 - */ -void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 3 - */ -void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 4 - */ -void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 5 - */ -void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel); - -#endif /* MCD_TSK_INIT_H */ diff --git a/c/src/lib/libcpu/m68k/mcf548x/mcdma/mcdma_glue.h b/c/src/lib/libcpu/m68k/mcf548x/mcdma/mcdma_glue.h deleted file mode 100644 index de0621120f..0000000000 --- a/c/src/lib/libcpu/m68k/mcf548x/mcdma/mcdma_glue.h +++ /dev/null @@ -1,106 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS generic MFC548x BSP | -+-----------------------------------------------------------------+ -| Copyright (c) 2004-2009 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file declares glue functions to the Freescale Mcdma API | -\*===============================================================*/ -#ifndef _MCDMA_GLUE_H -#define _MCDMA_GLUE_H - -#include <rtems.h> -#include <mcf548x/mcf548x.h> - -#define MCDMA_CLR_PENDING(chan) (MCF548X_DMA_DIPR = (1 << (chan))) -#define MCDMA_GET_PENDING(chan) (MCF548X_DMA_DIPR & (1 << (chan))) - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -void mcdma_glue_irq_enable -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| enable interrupt for given task number | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - int mcdma_taskno /* task number to enable */ - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| none | -\*=========================================================================*/ - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -void mcdma_glue_irq_disable -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| disable interrupt for given task number | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - int mcdma_taskno /* task number to disable */ - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| none | -\*=========================================================================*/ - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -void mcdma_glue_irq_install -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| install given function as mcdma interrupt handler | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - int mcdma_taskno, /* task number for handler */ - void (*the_handler)(rtems_irq_hdl_param), /* function to call */ - void *the_param - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| none | -\*=========================================================================*/ - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -void mcdma_glue_init -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| initialize the mcdma module (if not yet done): | -| - load code | -| - initialize registers | -| - initialize bus arbiter | -| - initialize interrupt control | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - void *sram_base /* base address for SRAM, to be used for DMA task */ - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| none | -\*=========================================================================*/ - -#endif /* _MCDMA_GLUE_H */ diff --git a/c/src/lib/libcpu/m68k/preinstall.am b/c/src/lib/libcpu/m68k/preinstall.am deleted file mode 100644 index 258f0cb6ca..0000000000 --- a/c/src/lib/libcpu/m68k/preinstall.am +++ /dev/null @@ -1,127 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -if shared -endif -if mcf5206 -$(PROJECT_INCLUDE)/mcf5206/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/mcf5206 - @: > $(PROJECT_INCLUDE)/mcf5206/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mcf5206/$(dirstamp) - -$(PROJECT_INCLUDE)/mcf5206/mcf5206e.h: mcf5206/include/mcf5206e.h $(PROJECT_INCLUDE)/mcf5206/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf5206/mcf5206e.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf5206/mcf5206e.h - -$(PROJECT_INCLUDE)/mcf5206/mcfmbus.h: mcf5206/include/mcfmbus.h $(PROJECT_INCLUDE)/mcf5206/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf5206/mcfmbus.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf5206/mcfmbus.h - -$(PROJECT_INCLUDE)/mcf5206/mcfuart.h: mcf5206/include/mcfuart.h $(PROJECT_INCLUDE)/mcf5206/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf5206/mcfuart.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf5206/mcfuart.h -endif -if mcf5223x -$(PROJECT_INCLUDE)/mcf5223x/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/mcf5223x - @: > $(PROJECT_INCLUDE)/mcf5223x/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mcf5223x/$(dirstamp) - -$(PROJECT_INCLUDE)/mcf5223x/mcf5223x.h: mcf5223x/include/mcf5223x.h $(PROJECT_INCLUDE)/mcf5223x/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf5223x/mcf5223x.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf5223x/mcf5223x.h -endif -if mcf5225x -$(PROJECT_INCLUDE)/mcf5225x/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/mcf5225x - @: > $(PROJECT_INCLUDE)/mcf5225x/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mcf5225x/$(dirstamp) - -$(PROJECT_INCLUDE)/mcf5225x/mcf5225x.h: mcf5225x/include/mcf5225x.h $(PROJECT_INCLUDE)/mcf5225x/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf5225x/mcf5225x.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf5225x/mcf5225x.h - -if HAS_NETWORKING -$(PROJECT_INCLUDE)/mcf5225x/fec.h: mcf5225x/include/fec.h $(PROJECT_INCLUDE)/mcf5225x/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf5225x/fec.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf5225x/fec.h -endif ## HAS_NETWORKING -endif -if mcf5235 -$(PROJECT_INCLUDE)/mcf5235/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/mcf5235 - @: > $(PROJECT_INCLUDE)/mcf5235/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mcf5235/$(dirstamp) - -$(PROJECT_INCLUDE)/mcf5235/mcf5235.h: mcf5235/include/mcf5235.h $(PROJECT_INCLUDE)/mcf5235/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf5235/mcf5235.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf5235/mcf5235.h -endif -if mcf532x -$(PROJECT_INCLUDE)/mcf532x/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/mcf532x - @: > $(PROJECT_INCLUDE)/mcf532x/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mcf532x/$(dirstamp) - -$(PROJECT_INCLUDE)/mcf532x/mcf532x.h: mcf532x/include/mcf532x.h $(PROJECT_INCLUDE)/mcf532x/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf532x/mcf532x.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf532x/mcf532x.h -endif -if mcf5272 -$(PROJECT_INCLUDE)/mcf5272/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/mcf5272 - @: > $(PROJECT_INCLUDE)/mcf5272/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mcf5272/$(dirstamp) - -$(PROJECT_INCLUDE)/mcf5272/mcf5272.h: mcf5272/include/mcf5272.h $(PROJECT_INCLUDE)/mcf5272/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf5272/mcf5272.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf5272/mcf5272.h -endif -if mcf5282 -$(PROJECT_INCLUDE)/mcf5282/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/mcf5282 - @: > $(PROJECT_INCLUDE)/mcf5282/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mcf5282/$(dirstamp) - -$(PROJECT_INCLUDE)/mcf5282/mcf5282.h: mcf5282/include/mcf5282.h $(PROJECT_INCLUDE)/mcf5282/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf5282/mcf5282.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf5282/mcf5282.h -endif -if mcf548x -$(PROJECT_INCLUDE)/mcf548x/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/mcf548x - @: > $(PROJECT_INCLUDE)/mcf548x/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mcf548x/$(dirstamp) - -$(PROJECT_INCLUDE)/mcf548x/mcf548x.h: mcf548x/include/mcf548x.h $(PROJECT_INCLUDE)/mcf548x/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf548x/mcf548x.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf548x/mcf548x.h - -$(PROJECT_INCLUDE)/mcf548x/MCD_progCheck.h: mcf548x/mcdma/MCD_progCheck.h $(PROJECT_INCLUDE)/mcf548x/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf548x/MCD_progCheck.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf548x/MCD_progCheck.h - -$(PROJECT_INCLUDE)/mcf548x/MCD_dma.h: mcf548x/mcdma/MCD_dma.h $(PROJECT_INCLUDE)/mcf548x/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf548x/MCD_dma.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf548x/MCD_dma.h - -$(PROJECT_INCLUDE)/mcf548x/MCD_tasksInit.h: mcf548x/mcdma/MCD_tasksInit.h $(PROJECT_INCLUDE)/mcf548x/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf548x/MCD_tasksInit.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf548x/MCD_tasksInit.h - -$(PROJECT_INCLUDE)/mcf548x/mcdma_glue.h: mcf548x/mcdma/mcdma_glue.h $(PROJECT_INCLUDE)/mcf548x/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf548x/mcdma_glue.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf548x/mcdma_glue.h -endif diff --git a/c/src/lib/libcpu/mips/Makefile.am b/c/src/lib/libcpu/mips/Makefile.am index 2630fc29d7..84dc521fac 100644 --- a/c/src/lib/libcpu/mips/Makefile.am +++ b/c/src/lib/libcpu/mips/Makefile.am @@ -7,10 +7,6 @@ EXTRA_DIST = noinst_PROGRAMS = ## cache -include_libcpudir = $(includedir)/libcpu - -include_libcpu_HEADERS = - noinst_PROGRAMS += shared/cache.rel shared_cache_rel_SOURCES = shared/cache/cache.c \ ../shared/src/cache_manager.c shared/cache/cache_.h @@ -36,15 +32,10 @@ shared_interrupts_rel_SOURCES = shared/interrupts/installisrentries.c \ shared/interrupts/isr_entries.S shared/interrupts/isr_entries.h shared_interrupts_rel_CPPFLAGS = $(AM_CPPFLAGS) $(interrupts_CPPFLAGS) shared_interrupts_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -include_libcpu_HEADERS += shared/interrupts/isr_entries.h - if tx39 -include_libcpu_HEADERS += tx39/include/tx3904.h endif if tx49 -include_libcpu_HEADERS += tx49/include/tx4925.h tx49/include/tx4938.h - noinst_PROGRAMS += tx49/timer.rel tx49_timer_rel_SOURCES = timer/timer.c timer/gettime.S tx49_timer_rel_CPPFLAGS = $(AM_CPPFLAGS) @@ -52,18 +43,13 @@ tx49_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif if au1x00 -include_libcpu_HEADERS += au1x00/include/au1x00.h - endif if rm52xx -include_libcpu_HEADERS += rm52xx/include/rm5231.h - noinst_PROGRAMS += rm52xx/timer.rel rm52xx_timer_rel_SOURCES = timer/timer.c timer/gettime.S rm52xx_timer_rel_CPPFLAGS = $(AM_CPPFLAGS) rm52xx_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/mips/au1x00/include/au1x00.h b/c/src/lib/libcpu/mips/au1x00/include/au1x00.h deleted file mode 100644 index a85a39ed48..0000000000 --- a/c/src/lib/libcpu/mips/au1x00/include/au1x00.h +++ /dev/null @@ -1,445 +0,0 @@ -/** - * @file - * - * AMD AU1X00 specific information - */ - -/* - * Copyright (c) 2005 by Cogent Computer Systems - * Written by Jay Monkman <jtm@lopingdog.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __AU1X00_H__ -#define __AU1X00_H__ - -#define bit(x) (1 << (x)) - -/* Au1x00 CP0 registers - */ -#define CP0_Index $0 -#define CP0_Random $1 -#define CP0_EntryLo0 $2 -#define CP0_EntryLo1 $3 -#define CP0_Context $4 -#define CP0_PageMask $5 -#define CP0_Wired $6 -#define CP0_BadVAddr $8 -#define CP0_Count $9 -#define CP0_EntryHi $10 -#define CP0_Compare $11 -#define CP0_Status $12 -#define CP0_Cause $13 -#define CP0_EPC $14 -#define CP0_PRId $15 -#define CP0_Config $16 -#define CP0_Config0 $16 -#define CP0_Config1 $16,1 -#define CP0_LLAddr $17 -#define CP0_WatchLo $18 -#define CP0_IWatchLo $18,1 -#define CP0_WatchHi $19 -#define CP0_IWatchHi $19,1 -#define CP0_Scratch $22 -#define CP0_Debug $23 -#define CP0_DEPC $24 -#define CP0_PerfCnt $25 -#define CP0_PerfCtrl $25,1 -#define CP0_DTag $28 -#define CP0_DData $28,1 -#define CP0_ITag $29 -#define CP0_IData $29,1 -#define CP0_ErrorEPC $30 -#define CP0_DESave $31 - -/* Addresses common to all AU1x00 CPUs */ -#define AU1X00_MEM_ADDR 0xB4000000 -#define AU1X00_AC97_ADDR 0xB0000000 -#define AU1X00_USBH_ADDR 0xB0100000 -#define AU1X00_USBD_ADDR 0xB0200000 -#define AU1X00_MACDMA0_ADDR 0xB4004000 -#define AU1X00_MACDMA1_ADDR 0xB4004200 -#define AU1X00_UART0_ADDR 0xB1100000 -#define AU1X00_UART3_ADDR 0xB1400000 -#define AU1X00_SYS_ADDR 0xB1900000 -#define AU1X00_GPIO2_ADDR 0xB1700000 -#define AU1X00_IC0_ADDR 0xB0400000 -#define AU1X00_IC1_ADDR 0xB1800000 - -/* Au1100 base addresses (in KSEG1 region) */ -#define AU1100_MAC0_ADDR 0xB0500000 -#define AU1100_MACEN_ADDR 0xB0520000 - -/* Au1500 base addresses (in KSEG1 region) */ -#define AU1500_MAC0_ADDR 0xB1500000 -#define AU1500_MAC1_ADDR 0xB1510000 -#define AU1500_MACEN_ADDR 0xB1520000 -#define AU1500_PCI_ADDR 0xB4005000 - -/* Au1x00 gpio2 register offsets - */ -#define gpio2_dir 0x0000 -#define gpio2_output 0x0008 -#define gpio2_pinstate 0x000c -#define gpio2_inten 0x0010 -#define gpio2_enable 0x0014 - -/* Au1x00 memory controller register offsets - */ -#define mem_sdmode0 0x0000 -#define mem_sdmode1 0x0004 -#define mem_sdmode2 0x0008 -#define mem_sdaddr0 0x000C -#define mem_sdaddr1 0x0010 -#define mem_sdaddr2 0x0014 -#define mem_sdrefcfg 0x0018 -#define mem_sdprecmd 0x001C -#define mem_sdautoref 0x0020 -#define mem_sdwrmd0 0x0024 -#define mem_sdwrmd1 0x0028 -#define mem_sdwrmd2 0x002C -#define mem_sdsleep 0x0030 -#define mem_sdsmcke 0x0034 - -#define mem_stcfg0 0x1000 -#define mem_sttime0 0x1004 -#define mem_staddr0 0x1008 -#define mem_stcfg1 0x1010 -#define mem_sttime1 0x1014 -#define mem_staddr1 0x1018 -#define mem_stcfg2 0x1020 -#define mem_sttime2 0x1024 -#define mem_staddr2 0x1028 -#define mem_stcfg3 0x1030 -#define mem_sttime3 0x1034 -#define mem_staddr3 0x1038 - -/* - * Au1x00 peripheral register offsets - */ -#define ac97_enable 0x0010 -#define usbh_enable 0x0007FFFC -#define usbd_enable 0x0058 -#define irda_enable 0x0040 -#define macen_mac0 0x0000 -#define macen_mac1 0x0004 -#define i2s_enable 0x0008 -#define uart_enable 0x0100 -#define ssi_enable 0x0100 - -#define sys_scratch0 0x0018 -#define sys_scratch1 0x001c -#define sys_cntctrl 0x0014 -#define sys_freqctrl0 0x0020 -#define sys_freqctrl1 0x0024 -#define sys_clksrc 0x0028 -#define sys_pinfunc 0x002C -#define sys_powerctrl 0x003C -#define sys_endian 0x0038 -#define sys_wakesrc 0x005C -#define sys_cpupll 0x0060 -#define sys_auxpll 0x0064 -#define sys_pininputen 0x0110 - -#define pci_cmem 0x0000 -#define pci_config 0x0004 -#define pci_b2bmask_cch 0x0008 -#define pci_b2bbase0_venid 0x000C -#define pci_b2bbase1_id 0x0010 -#define pci_mwmask_dev 0x0014 -#define pci_mwbase_rev_ccl 0x0018 -#define pci_err_addr 0x001C -#define pci_spec_intack 0x0020 -#define pci_id 0x0100 -#define pci_statcmd 0x0104 -#define pci_classrev 0x0108 -#define pci_hdrtype 0x010C -#define pci_mbar 0x0110 - -/* - * CSB250-specific values - */ - -#define SYS_CPUPLL 33 -#define SYS_POWERCTRL 1 -#define SYS_AUXPLL 8 -#define SYS_CNTCTRL 256 - -/* RCE0: */ -#define MEM_STCFG0 0x00000203 -#define MEM_STTIME0 0x22080b20 -#define MEM_STADDR0 0x11f03fc0 - -/* RCE1: */ -#define MEM_STCFG1 0x00000203 -#define MEM_STTIME1 0x22080b20 -#define MEM_STADDR1 0x11e03fc0 - -/* RCE2: */ -#define MEM_STCFG2 0x00000244 -#define MEM_STTIME2 0x22080a20 -#define MEM_STADDR2 0x11803f00 - -/* RCE3: */ -#define MEM_STCFG3 0x00000201 -#define MEM_STTIME3 0x22080b20 -#define MEM_STADDR3 0x11003f00 - -/* - * SDCS0 - - * SDCS1 - - * SDCS2 - - */ -#define MEM_SDMODE0 0x00552229 -#define MEM_SDMODE1 0x00552229 -#define MEM_SDMODE2 0x00552229 - -#define MEM_SDADDR0 0x001003F8 -#define MEM_SDADDR1 0x001023F8 -#define MEM_SDADDR2 0x001043F8 - -#define MEM_SDREFCFG_D 0x74000c30 /* disable */ -#define MEM_SDREFCFG_E 0x76000c30 /* enable */ -#define MEM_SDWRMD0 0x00000023 -#define MEM_SDWRMD1 0x00000023 -#define MEM_SDWRMD2 0x00000023 - -#define MEM_1MS ((396000000/1000000) * 1000) - -#define AU1X00_IC_CFG0RD(x) (*(volatile uint32_t*)(x + 0x40)) -#define AU1X00_IC_CFG0SET(x) (*(volatile uint32_t*)(x + 0x40)) -#define AU1X00_IC_CFG0CLR(x) (*(volatile uint32_t*)(x + 0x44)) -#define AU1X00_IC_CFG1RD(x) (*(volatile uint32_t*)(x + 0x48)) -#define AU1X00_IC_CFG1SET(x) (*(volatile uint32_t*)(x + 0x48)) -#define AU1X00_IC_CFG1CLR(x) (*(volatile uint32_t*)(x + 0x4c)) -#define AU1X00_IC_CFG2RD(x) (*(volatile uint32_t*)(x + 0x50)) -#define AU1X00_IC_CFG2SET(x) (*(volatile uint32_t*)(x + 0x50)) -#define AU1X00_IC_CFG2CLR(x) (*(volatile uint32_t*)(x + 0x54)) -#define AU1X00_IC_REQ0INT(x) (*(volatile uint32_t*)(x + 0x54)) -#define AU1X00_IC_SRCRD(x) (*(volatile uint32_t*)(x + 0x58)) -#define AU1X00_IC_SRCSET(x) (*(volatile uint32_t*)(x + 0x58)) -#define AU1X00_IC_SRCCLR(x) (*(volatile uint32_t*)(x + 0x5c)) -#define AU1X00_IC_REQ1INT(x) (*(volatile uint32_t*)(x + 0x5c)) -#define AU1X00_IC_ASSIGNRD(x) (*(volatile uint32_t*)(x + 0x60)) -#define AU1X00_IC_ASSIGNSET(x) (*(volatile uint32_t*)(x + 0x60)) -#define AU1X00_IC_ASSIGNCLR(x) (*(volatile uint32_t*)(x + 0x64)) -#define AU1X00_IC_WAKERD(x) (*(volatile uint32_t*)(x + 0x68)) -#define AU1X00_IC_WAKESET(x) (*(volatile uint32_t*)(x + 0x68)) -#define AU1X00_IC_WAKECLR(x) (*(volatile uint32_t*)(x + 0x6c)) -#define AU1X00_IC_MASKRD(x) (*(volatile uint32_t*)(x + 0x70)) -#define AU1X00_IC_MASKSET(x) (*(volatile uint32_t*)(x + 0x70)) -#define AU1X00_IC_MASKCLR(x) (*(volatile uint32_t*)(x + 0x74)) -#define AU1X00_IC_RISINGRD(x) (*(volatile uint32_t*)(x + 0x78)) -#define AU1X00_IC_RISINGCLR(x) (*(volatile uint32_t*)(x + 0x78)) -#define AU1X00_IC_FALLINGRD(x) (*(volatile uint32_t*)(x + 0x7c)) -#define AU1X00_IC_FALLINGCLR(x) (*(volatile uint32_t*)(x + 0x7c)) -#define AU1X00_IC_TESTBIT(x) (*(volatile uint32_t*)(x + 0x80)) -#define AU1X00_IC_IRQ_MAC0 (bit(28)) -#define AU1X00_IC_IRQ_MAC1 (bit(29)) -#define AU1X00_IC_IRQ_TOY_MATCH0 (bit(15)) -#define AU1X00_IC_IRQ_TOY_MATCH1 (bit(16)) -#define AU1X00_IC_IRQ_TOY_MATCH2 (bit(17)) - - - -#define AU1X00_SYS_TOYTRIM(x) (*(volatile uint32_t*)(x + 0x00)) -#define AU1X00_SYS_TOYWRITE(x) (*(volatile uint32_t*)(x + 0x04)) -#define AU1X00_SYS_TOYMATCH0(x) (*(volatile uint32_t*)(x + 0x08)) -#define AU1X00_SYS_TOYMATCH1(x) (*(volatile uint32_t*)(x + 0x0c)) -#define AU1X00_SYS_TOYMATCH2(x) (*(volatile uint32_t*)(x + 0x10)) -#define AU1X00_SYS_CNTCTRL(x) (*(volatile uint32_t*)(x + 0x14)) -#define AU1X00_SYS_SCRATCH0(x) (*(volatile uint32_t*)(x + 0x18)) -#define AU1X00_SYS_SCRATCH1(x) (*(volatile uint32_t*)(x + 0x1c)) -#define AU1X00_SYS_WAKEMSK(x) (*(volatile uint32_t*)(x + 0x34)) -#define AU1X00_SYS_ENDIAN(x) (*(volatile uint32_t*)(x + 0x38)) -#define AU1X00_SYS_POWERCTRL(x) (*(volatile uint32_t*)(x + 0x3c)) -#define AU1X00_SYS_TOYREAD(x) (*(volatile uint32_t*)(x + 0x40)) -#define AU1X00_SYS_RTCTRIM(x) (*(volatile uint32_t*)(x + 0x44)) -#define AU1X00_SYS_RTCWRITE(x) (*(volatile uint32_t*)(x + 0x48)) -#define AU1X00_SYS_RTCMATCH0(x) (*(volatile uint32_t*)(x + 0x4c)) -#define AU1X00_SYS_RTCMATCH1(x) (*(volatile uint32_t*)(x + 0x50)) -#define AU1X00_SYS_RTCMATCH2(x) (*(volatile uint32_t*)(x + 0x54)) -#define AU1X00_SYS_RTCREAD(x) (*(volatile uint32_t*)(x + 0x58)) -#define AU1X00_SYS_WAKESRC(x) (*(volatile uint32_t*)(x + 0x5c)) -#define AU1X00_SYS_SLPPWR(x) (*(volatile uint32_t*)(x + 0x78)) -#define AU1X00_SYS_SLEEP(x) (*(volatile uint32_t*)(x + 0x7c)) - -#define AU1X00_SYS_CNTCTRL_ERS (bit(23)) -#define AU1X00_SYS_CNTCTRL_RTS (bit(20)) -#define AU1X00_SYS_CNTCTRL_RM2 (bit(19)) -#define AU1X00_SYS_CNTCTRL_RM1 (bit(18)) -#define AU1X00_SYS_CNTCTRL_RM0 (bit(17)) -#define AU1X00_SYS_CNTCTRL_RS (bit(16)) -#define AU1X00_SYS_CNTCTRL_BP (bit(14)) -#define AU1X00_SYS_CNTCTRL_REN (bit(13)) -#define AU1X00_SYS_CNTCTRL_BRT (bit(12)) -#define AU1X00_SYS_CNTCTRL_TEN (bit(11)) -#define AU1X00_SYS_CNTCTRL_BTT (bit(10)) -#define AU1X00_SYS_CNTCTRL_E0 (bit(8)) -#define AU1X00_SYS_CNTCTRL_ETS (bit(7)) -#define AU1X00_SYS_CNTCTRL_32S (bit(5)) -#define AU1X00_SYS_CNTCTRL_TTS (bit(4)) -#define AU1X00_SYS_CNTCTRL_TM2 (bit(3)) -#define AU1X00_SYS_CNTCTRL_TM1 (bit(2)) -#define AU1X00_SYS_CNTCTRL_TM0 (bit(1)) -#define AU1X00_SYS_CNTCTRL_TS (bit(0)) -#define AU1X00_SYS_WAKEMSK_M20 (bit(8)) - -#define AU1X00_MAC_CONTROL(x) (*(volatile uint32_t*)(x + 0x00)) -#define AU1X00_MAC_ADDRHIGH(x) (*(volatile uint32_t*)(x + 0x04)) -#define AU1X00_MAC_ADDRLOW(x) (*(volatile uint32_t*)(x + 0x08)) -#define AU1X00_MAC_HASHHIGH(x) (*(volatile uint32_t*)(x + 0x0c)) -#define AU1X00_MAC_HASHLOW(x) (*(volatile uint32_t*)(x + 0x10)) -#define AU1X00_MAC_MIICTRL(x) (*(volatile uint32_t*)(x + 0x14)) -#define AU1X00_MAC_MIIDATA(x) (*(volatile uint32_t*)(x + 0x18)) -#define AU1X00_MAC_FLOWCTRL(x) (*(volatile uint32_t*)(x + 0x1c)) -#define AU1X00_MAC_VLAN1(x) (*(volatile uint32_t*)(x + 0x20)) -#define AU1X00_MAC_VLAN2(x) (*(volatile uint32_t*)(x + 0x24)) -#define AU1X00_MAC_EN0 (*(volatile uint32_t*)(AU1X00_MACEN_ADDR + 0x0)) -#define AU1X00_MAC_EN1 (*(volatile uint32_t*)(AU1X00_MACEN_ADDR + 0x4)) -#define AU1X00_MAC_DMA_TX0_ADDR(x) (*(volatile uint32_t*)(x + 0x000)) -#define AU1X00_MAC_DMA_TX1_ADDR(x) (*(volatile uint32_t*)(x + 0x010)) -#define AU1X00_MAC_DMA_TX2_ADDR(x) (*(volatile uint32_t*)(x + 0x020)) -#define AU1X00_MAC_DMA_TX3_ADDR(x) (*(volatile uint32_t*)(x + 0x030)) -#define AU1X00_MAC_DMA_RX0_ADDR(x) (*(volatile uint32_t*)(x + 0x100)) -#define AU1X00_MAC_DMA_RX1_ADDR(x) (*(volatile uint32_t*)(x + 0x110)) -#define AU1X00_MAC_DMA_RX2_ADDR(x) (*(volatile uint32_t*)(x + 0x120)) -#define AU1X00_MAC_DMA_RX3_ADDR(x) (*(volatile uint32_t*)(x + 0x130)) - -typedef struct { - volatile uint32_t stat; - volatile uint32_t addr; - uint32_t _rsv0; - uint32_t _rsv1; -} au1x00_macdma_rx_t; - - -typedef struct { - volatile uint32_t stat; - volatile uint32_t addr; - volatile uint32_t len; - uint32_t _rsv0; -} au1x00_macdma_tx_t; - -#define AU1X00_MAC_CTRL_RA (bit(31)) -#define AU1X00_MAC_CTRL_EM (bit(30)) -#define AU1X00_MAC_CTRL_DO (bit(23)) -#define AU1X00_MAC_CTRL_LM(x) ((x) << 21) -#define AU1X00_MAC_CTRL_LM_NORMAL ((0) << 21) -#define AU1X00_MAC_CTRL_LM_INTERNAL ((1) << 21) -#define AU1X00_MAC_CTRL_LM_EXTERNAL ((2) << 21) -#define AU1X00_MAC_CTRL_F (bit(20)) -#define AU1X00_MAC_CTRL_PM (bit(19)) -#define AU1X00_MAC_CTRL_PR (bit(18)) -#define AU1X00_MAC_CTRL_IF (bit(17)) -#define AU1X00_MAC_CTRL_PB (bit(16)) -#define AU1X00_MAC_CTRL_HO (bit(15)) -#define AU1X00_MAC_CTRL_HP (bit(13)) -#define AU1X00_MAC_CTRL_LC (bit(12)) -#define AU1X00_MAC_CTRL_DB (bit(11)) -#define AU1X00_MAC_CTRL_DR (bit(10)) -#define AU1X00_MAC_CTRL_AP (bit(8)) -#define AU1X00_MAC_CTRL_BL(x) ((x) << 6) -#define AU1X00_MAC_CTRL_DC (bit(5)) -#define AU1X00_MAC_CTRL_TE (bit(3)) -#define AU1X00_MAC_CTRL_RE (bit(2)) - -#define AU1X00_MAC_EN_JP (bit(6)) -#define AU1X00_MAC_EN_E2 (bit(5)) -#define AU1X00_MAC_EN_E1 (bit(4)) -#define AU1X00_MAC_EN_C (bit(3)) -#define AU1X00_MAC_EN_TS (bit(2)) -#define AU1X00_MAC_EN_E0 (bit(1)) -#define AU1X00_MAC_EN_CE (bit(0)) - -#define AU1X00_MAC_ADDRHIGH_MASK (0xffff)_ -#define AU1X00_MAC_MIICTRL_PHYADDR(x) ((x & 0x1f) << 11) -#define AU1X00_MAC_MIICTRL_MIIREG(x) ((x & 0x1f) << 6) -#define AU1X00_MAC_MIICTRL_MW (bit(1)) -#define AU1X00_MAC_MIICTRL_MB (bit(0)) -#define AU1X00_MAC_MIIDATA_MASK (0xffff) -#define AU1X00_MAC_FLOWCTRL_PT(x) (((x) & 0xffff) << 16) -#define AU1X00_MAC_FLOWCTRL_PC (bit(2)) -#define AU1X00_MAC_FLOWCTRL_FE (bit(1)) -#define AU1X00_MAC_FLOWCTRL_FB (bit(0)) - -#define AU1X00_MAC_DMA_RXSTAT_MI (bit(31)) -#define AU1X00_MAC_DMA_RXSTAT_PF (bit(30)) -#define AU1X00_MAC_DMA_RXSTAT_FF (bit(29)) -#define AU1X00_MAC_DMA_RXSTAT_BF (bit(28)) -#define AU1X00_MAC_DMA_RXSTAT_MF (bit(27)) -#define AU1X00_MAC_DMA_RXSTAT_UC (bit(26)) -#define AU1X00_MAC_DMA_RXSTAT_CF (bit(25)) -#define AU1X00_MAC_DMA_RXSTAT_LE (bit(24)) -#define AU1X00_MAC_DMA_RXSTAT_V2 (bit(23)) -#define AU1X00_MAC_DMA_RXSTAT_V1 (bit(22)) -#define AU1X00_MAC_DMA_RXSTAT_CR (bit(21)) -#define AU1X00_MAC_DMA_RXSTAT_DB (bit(20)) -#define AU1X00_MAC_DMA_RXSTAT_ME (bit(19)) -#define AU1X00_MAC_DMA_RXSTAT_FT (bit(18)) -#define AU1X00_MAC_DMA_RXSTAT_CS (bit(17)) -#define AU1X00_MAC_DMA_RXSTAT_FL (bit(16)) -#define AU1X00_MAC_DMA_RXSTAT_RF (bit(15)) -#define AU1X00_MAC_DMA_RXSTAT_WT (bit(14)) -#define AU1X00_MAC_DMA_RXSTAT_LEN(x) ((x) & 0x3fff) -#define AU1X00_MAC_DMA_RXADDR_ADDR(x) ((x) & ~0x1f) -#define AU1X00_MAC_DMA_RXADDR_CB_MASK (0x3 << 0x2) -#define AU1X00_MAC_DMA_RXADDR_DN (bit(1)) -#define AU1X00_MAC_DMA_RXADDR_EN (bit(0)) - - -#define AU1X00_MAC_DMA_TXSTAT_PR (bit(31)) -#define AU1X00_MAC_DMA_TXSTAT_CC_MASK (0xf << 10) -#define AU1X00_MAC_DMA_TXSTAT_LO (bit(9)) -#define AU1X00_MAC_DMA_TXSTAT_DF (bit(8)) -#define AU1X00_MAC_DMA_TXSTAT_UR (bit(7)) -#define AU1X00_MAC_DMA_TXSTAT_EC (bit(6)) -#define AU1X00_MAC_DMA_TXSTAT_LC (bit(5)) -#define AU1X00_MAC_DMA_TXSTAT_ED (bit(4)) -#define AU1X00_MAC_DMA_TXSTAT_LS (bit(3)) -#define AU1X00_MAC_DMA_TXSTAT_NC (bit(2)) -#define AU1X00_MAC_DMA_TXSTAT_JT (bit(1)) -#define AU1X00_MAC_DMA_TXSTAT_FA (bit(0)) -#define AU1X00_MAC_DMA_TXADDR_ADDR(x) ((x) & ~0x1f) -#define AU1X00_MAC_DMA_TXADDR_CB_MASK (0x3 << 0x2) -#define AU1X00_MAC_DMA_TXADDR_DN (bit(1)) -#define AU1X00_MAC_DMA_TXADDR_EN (bit(0)) - - - -typedef struct { - volatile uint32_t rxdata; - volatile uint32_t txdata; - volatile uint32_t inten; - volatile uint32_t intcause; - volatile uint32_t fifoctrl; - volatile uint32_t linectrl; - volatile uint32_t mdmctrl; - volatile uint32_t linestat; - volatile uint32_t mdmstat; - volatile uint32_t clkdiv; - volatile uint32_t _resv[54]; - volatile uint32_t enable; -} au1x00_uart_t; - -extern au1x00_uart_t *uart0; -extern au1x00_uart_t *uart3; - -void static inline au_sync(void) -{ - __asm__ volatile ("sync"); -} - - -extern void mips_default_isr( int vector ); - -/* Generate a software interrupt */ -extern int assert_sw_irq(uint32_t irqnum); - -/* Clear a software interrupt */ -extern int negate_sw_irq(uint32_t irqnum); - -#endif diff --git a/c/src/lib/libcpu/mips/configure.ac b/c/src/lib/libcpu/mips/configure.ac index 324dd312f7..6a9e2665d9 100644 --- a/c/src/lib/libcpu/mips/configure.ac +++ b/c/src/lib/libcpu/mips/configure.ac @@ -4,6 +4,8 @@ AC_PREREQ([2.69]) AC_INIT([rtems-c-src-lib-libcpu-mips],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([timer]) RTEMS_TOP([../../../../..],[../../..]) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP RTEMS_CANONICAL_TARGET_CPU diff --git a/c/src/lib/libcpu/mips/preinstall.am b/c/src/lib/libcpu/mips/preinstall.am deleted file mode 100644 index 6d302e501b..0000000000 --- a/c/src/lib/libcpu/mips/preinstall.am +++ /dev/null @@ -1,48 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/libcpu/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu - @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - -$(PROJECT_INCLUDE)/libcpu/isr_entries.h: shared/interrupts/isr_entries.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/isr_entries.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/isr_entries.h - -if tx39 -$(PROJECT_INCLUDE)/libcpu/tx3904.h: tx39/include/tx3904.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/tx3904.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/tx3904.h -endif -if tx49 -$(PROJECT_INCLUDE)/libcpu/tx4925.h: tx49/include/tx4925.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/tx4925.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/tx4925.h - -$(PROJECT_INCLUDE)/libcpu/tx4938.h: tx49/include/tx4938.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/tx4938.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/tx4938.h -endif -if au1x00 -$(PROJECT_INCLUDE)/libcpu/au1x00.h: au1x00/include/au1x00.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/au1x00.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/au1x00.h -endif -if rm52xx -$(PROJECT_INCLUDE)/libcpu/rm5231.h: rm52xx/include/rm5231.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/rm5231.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/rm5231.h -endif diff --git a/c/src/lib/libcpu/mips/rm52xx/include/rm5231.h b/c/src/lib/libcpu/mips/rm52xx/include/rm5231.h deleted file mode 100644 index c9ad3f9861..0000000000 --- a/c/src/lib/libcpu/mips/rm52xx/include/rm5231.h +++ /dev/null @@ -1,19 +0,0 @@ -/** - * @file - * - * MIPS RM5231 specific information - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __RM5231_h -#define __RM5231_h - -#endif diff --git a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h deleted file mode 100644 index e142018be7..0000000000 --- a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h +++ /dev/null @@ -1,39 +0,0 @@ -/** - * @file - * - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _ISR_ENTRIES_H -#define _ISR_ENTRIES_H 1 - -#include <rtems/score/cpuimpl.h> - -extern void mips_install_isr_entries( void ); -extern void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ); - -#if __mips == 1 -extern void exc_utlb_code(void); -extern void exc_dbg_code(void); -extern void exc_norm_code(void); -#elif __mips == 32 -extern void exc_tlb_code(void); -extern void exc_xtlb_code(void); -extern void exc_cache_code(void); -extern void exc_norm_code(void); -#elif __mips == 3 -extern void exc_tlb_code(void); -extern void exc_xtlb_code(void); -extern void exc_cache_code(void); -extern void exc_norm_code(void); -#endif - -#endif diff --git a/c/src/lib/libcpu/mips/tx39/include/tx3904.h b/c/src/lib/libcpu/mips/tx39/include/tx3904.h deleted file mode 100644 index b573d3c7d9..0000000000 --- a/c/src/lib/libcpu/mips/tx39/include/tx3904.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file - * - * MIPS Tx3904 specific information - * - * NOTE: This is far from complete. --joel (13 Dec 2000) - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __TX3904_h -#define __TX3904_h - -/* - * Timer Base Addresses and Offsets - */ - -#define TX3904_TIMER0_BASE 0xFFFFF000 -#define TX3904_TIMER1_BASE 0xFFFFF100 -#define TX3904_TIMER2_BASE 0xFFFFF200 - -#define TX3904_TIMER_TCR 0x00 -#define TX3904_TIMER_TISR 0x04 -#define TX3904_TIMER_CPRA 0x08 -#define TX3904_TIMER_CPRB 0x0C -#define TX3904_TIMER_ITMR 0x10 -#define TX3904_TIMER_CCDR 0x20 -#define TX3904_TIMER_PGMR 0x30 -#define TX3904_TIMER_WTMR 0x40 -#define TX3904_TIMER_TRR 0xF0 - -#define TX3904_TIMER_READ( _base, _register ) \ - *((volatile uint32_t*)((_base) + (_register))) - -#define TX3904_TIMER_WRITE( _base, _register, _value ) \ - *((volatile uint32_t*)((_base) + (_register))) = (_value) - -#endif diff --git a/c/src/lib/libcpu/mips/tx49/include/tx4925.h b/c/src/lib/libcpu/mips/tx49/include/tx4925.h deleted file mode 100644 index 56f58d9bf3..0000000000 --- a/c/src/lib/libcpu/mips/tx49/include/tx4925.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * @file - * - * MIPS Tx4925 specific information - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __TX4925_h -#define __TX4925_h - -#define TX4925_REG_BASE 0xFF1F0000 - - -/* - * Configuration Registers - */ -#define TX4925_CFG_CCFG 0xE000 /* Chip Configuration Register */ -#define TX4925_CFG_REVID 0xE004 /* Chip Revision ID Register */ -#define TX4925_CFG_PCFG 0xE008 /* Pin Configuration Register */ -#define TX4925_CFG_TOEA 0xE00C /* TimeOut Error Access Address Register */ -#define TX4925_CFG_PDNCTR 0xE010 /* Power Down Control Register */ -#define TX4925_CFG_GARBP 0xE018 /* GBUS Arbiter Priority Register */ -#define TX4925_CFG_TOCNT 0xE020 /* Timeout Count Register */ -#define TX4925_CFG_DRQCTR 0xE024 /* DMA Request Control Register */ -#define TX4925_CFG_CLKCTR 0xE028 /* Clock Control Register */ -#define TX4925_CFG_GARBC 0xE02C /* GBUS Arbiter Control Register */ -#define TX4925_CFG_RAMP 0xE030 /* Register Address Mapping Register */ - -/* Pin Configuration register bits */ -#define SELCHI 0x00100000 -#define SELTMR0 0x00000200 - - -/* - * Timer Registers - */ - -#define TX4925_TIMER0_BASE 0xF000 -#define TX4925_TIMER1_BASE 0xF100 -#define TX4925_TIMER2_BASE 0xF200 - -#define TX4925_TIMER_TCR 0x00 /* Timer Control Register */ -#define TX4925_TIMER_TISR 0x04 /* Timer Interrupt Status Register */ -#define TX4925_TIMER_CPRA 0x08 /* Compare Register A */ -#define TX4925_TIMER_CPRB 0x0C /* Compare Register B */ -#define TX4925_TIMER_ITMR 0x10 /* Interval Timer Mode Register */ -#define TX4925_TIMER_CCDR 0x20 /* Divide Cycle Register */ -#define TX4925_TIMER_PGMR 0x30 /* Pulse Generator Mode Register */ -#define TX4925_TIMER_WTMR 0x40 /* Reserved Register */ -#define TX4925_TIMER_TRR 0xF0 /* Timer Read Register */ - -/* ITMR register bits */ -#define TIMER_CLEAR_ENABLE_MASK 0x1 -#define TIMER_INT_ENABLE_MASK 0x8000 - -/* PGMR register bits */ -#define FFI 0x1 -#define TPIAE 0x4000 -#define TPIBE 0x8000 - -/* TISR register bits */ -#define TIIS 0x1 -#define TPIAS 0x2 -#define TPIBS 0x4 -#define TWIS 0x8 - - -/* - * Interrupt Controller Registers - */ -#define TX4925_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */ -#define TX4925_IRQCTL_DM0 0xF604 /* Interrupt Detection Mode Register 0 */ -#define TX4925_IRQCTL_DM1 0xF608 /* Interrupt Detection Mode Register 1 */ -#define TX4925_IRQCTL_LVL0 0xF610 /* Interrupt Level Register 0 */ -#define TX4925_IRQCTL_LVL1 0xF614 /* Interrupt Level Register 1 */ -#define TX4925_IRQCTL_LVL2 0xF618 /* Interrupt Level Register 2 */ -#define TX4925_IRQCTL_LVL3 0xF61C /* Interrupt Level Register 3 */ -#define TX4925_IRQCTL_LVL4 0xF620 /* Interrupt Level Register 4 */ -#define TX4925_IRQCTL_LVL5 0xF624 /* Interrupt Level Register 5 */ -#define TX4925_IRQCTL_LVL6 0xF628 /* Interrupt Level Register 6 */ -#define TX4925_IRQCTL_LVL7 0xF62C /* Interrupt Level Register 7 */ -#define TX4925_IRQCTL_MSK 0xF640 /* Interrupt Mask Register */ -#define TX4925_IRQCTL_EDC 0xF660 /* Interrupt Edge Detection Clear Register */ -#define TX4925_IRQCTL_PND 0xF680 /* Interrupt Pending Register */ -#define TX4925_IRQCTL_CS 0xF6A0 /* Interrupt Current Status Register */ -#define TX4925_IRQCTL_FLAG0 0xF510 /* Interrupt Request Flag Register 0 */ -#define TX4925_IRQCTL_FLAG1 0xF514 /* Interrupt Request Flag Register 1 */ -#define TX4925_IRQCTL_POL 0xF518 /* Interrupt Request Polarity Control Register */ -#define TX4925_IRQCTL_RCNT 0xF51C /* Interrupt Request Control Register */ -#define TX4925_IRQCTL_MASKINT 0xF520 /* Interrupt Request Internal Interrupt Mask Register */ -#define TX4925_IRQCTL_MASKEXT 0xF524 /* Interrupt Request External Interrupt Mask Register */ - -#define TX4925_REG_READ( _base, _register ) \ - *((volatile uint32_t *)((_base) + (_register))) - -#define TX4925_REG_WRITE( _base, _register, _value ) \ - *((volatile uint32_t *)((_base) + (_register))) = (_value) - -#endif diff --git a/c/src/lib/libcpu/mips/tx49/include/tx4938.h b/c/src/lib/libcpu/mips/tx49/include/tx4938.h deleted file mode 100644 index 5005cc4149..0000000000 --- a/c/src/lib/libcpu/mips/tx49/include/tx4938.h +++ /dev/null @@ -1,191 +0,0 @@ -/** - * @file - * - * MIPS Tx4938 specific information - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __TX4938_h -#define __TX4938_h - -#define TX4938_REG_BASE 0xFF1F0000 - -/* PCI1 Registers */ -#define TX4938_PCI1_PCIID 0x7000 -#define TX4938_PCI1_PCISTATUS 0x7004 -#define TX4938_PCI1_PCICFG1 0x700c -#define TX4938_PCI1_P2GM1PLBASE 0x7018 -#define TX4938_PCI1_P2GCFG 0x7090 -#define TX4938_PCI1_PBAREQPORT 0x7100 -#define TX4938_PCI1_PBACFG 0x7104 -#define TX4938_PCI1_G2PM0GBASE 0x7120 -#define TX4938_PCI1_G2PIOGBASE 0x7138 -#define TX4938_PCI1_G2PM0MASK 0x7140 -#define TX4938_PCI1_G2PIOMASK 0x714c -#define TX4938_PCI1_G2PM0PBASE 0x7150 -#define TX4938_PCI1_G2PIOPBASE 0x7168 -#define TX4938_PCI1_PCICCFG 0x7170 -#define TX4938_PCI1_PCICSTATUS 0x7174 -#define TX4938_PCI1_P2GM1GBASE 0x7188 -#define TX4938_PCI1_G2PCFGADRS 0x71a0 -#define TX4938_PCI1_G2PCFGDATA 0x71a4 - -/* - * Configuration Registers - */ -#define TX4938_CFG_CCFG 0xE000 /* Chip Configuration Register */ -#define TX4938_CFG_REVID 0xE008 /* Chip Revision ID Register */ -#define TX4938_CFG_PCFG 0xE010 /* Pin Configuration Register */ -#define TX4938_CFG_TOEA 0xE018 /* TimeOut Error Access Address Register */ -#define TX4938_CFG_CLKCTR 0xE020 /* Clock Control Register */ -#define TX4938_CFG_GARBC 0xE030 /* GBUS Arbiter Control Register */ -#define TX4938_CFG_RAMP 0xE048 /* Register Address Mapping Register */ - -/* Pin Configuration register bits */ -#define SELCHI 0x00100000 -#define SELTMR0 0x00000200 - - -/* - * Timer Registers - */ - -#define TX4938_TIMER0_BASE 0xF000 -#define TX4938_TIMER1_BASE 0xF100 -#define TX4938_TIMER2_BASE 0xF200 - -#define TX4938_TIMER_TCR 0x00 /* Timer Control Register */ -#define TX4938_TIMER_TISR 0x04 /* Timer Interrupt Status Register */ -#define TX4938_TIMER_CPRA 0x08 /* Compare Register A */ -#define TX4938_TIMER_CPRB 0x0C /* Compare Register B */ -#define TX4938_TIMER_ITMR 0x10 /* Interval Timer Mode Register */ -#define TX4938_TIMER_CCDR 0x20 /* Divide Cycle Register */ -#define TX4938_TIMER_PGMR 0x30 /* Pulse Generator Mode Register */ -#define TX4938_TIMER_WTMR 0x40 /* Reserved Register */ -#define TX4938_TIMER_TRR 0xF0 /* Timer Read Register */ - -/* ITMR register bits */ -#define TIMER_CLEAR_ENABLE_MASK 0x1 -#define TIMER_INT_ENABLE_MASK 0x8000 - -/* PGMR register bits */ -#define FFI 0x1 -#define TPIAE 0x4000 -#define TPIBE 0x8000 - -/* TISR register bits */ -#define TIIS 0x1 -#define TPIAS 0x2 -#define TPIBS 0x4 -#define TWIS 0x8 - - -/* - * Interrupt Controller Registers - */ -#define TX4938_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */ -#define TX4938_IRQCTL_DM0 0xF604 /* Interrupt Detection Mode Register 0 */ -#define TX4938_IRQCTL_DM1 0xF608 /* Interrupt Detection Mode Register 1 */ -#define TX4938_IRQCTL_LVL0 0xF610 /* Interrupt Level Register 0 */ -#define TX4938_IRQCTL_LVL1 0xF614 /* Interrupt Level Register 1 */ -#define TX4938_IRQCTL_LVL2 0xF618 /* Interrupt Level Register 2 */ -#define TX4938_IRQCTL_LVL3 0xF61C /* Interrupt Level Register 3 */ -#define TX4938_IRQCTL_LVL4 0xF620 /* Interrupt Level Register 4 */ -#define TX4938_IRQCTL_LVL5 0xF624 /* Interrupt Level Register 5 */ -#define TX4938_IRQCTL_LVL6 0xF628 /* Interrupt Level Register 6 */ -#define TX4938_IRQCTL_LVL7 0xF62C /* Interrupt Level Register 7 */ -#define TX4938_IRQCTL_MSK 0xF640 /* Interrupt Mask Register */ -#define TX4938_IRQCTL_EDC 0xF660 /* Interrupt Edge Detection Clear Register */ -#define TX4938_IRQCTL_PND 0xF680 /* Interrupt Pending Register */ -#define TX4938_IRQCTL_CS 0xF6A0 /* Interrupt Current Status Register */ -#define TX4938_IRQCTL_FLAG0 0xF510 /* Interrupt Request Flag Register 0 */ -#define TX4938_IRQCTL_FLAG1 0xF514 /* Interrupt Request Flag Register 1 */ -#define TX4938_IRQCTL_POL 0xF518 /* Interrupt Request Polarity Control Register */ -#define TX4938_IRQCTL_RCNT 0xF51C /* Interrupt Request Control Register */ -#define TX4938_IRQCTL_MASKINT 0xF520 /* Interrupt Request Internal Interrupt Mask Register */ -#define TX4938_IRQCTL_MASKEXT 0xF524 /* Interrupt Request External Interrupt Mask Register */ - -#define TX4938_REG_READ( _base, _register ) \ - *((volatile uint32_t *)((_base) + (_register))) - -#define TX4938_REG_WRITE( _base, _register, _value ) \ - *((volatile uint32_t *)((_base) + (_register))) = (_value) - -/************************************************************************ - * TX49 Register field encodings -*************************************************************************/ -/******** reg: CCFG ********/ -/* field: PCIDIVMODE */ -#define TX4938_CCFG_SYSSP_SHF 6 -#define TX4938_CCFG_SYSSP_MSK (MSK(2) << TX4938_CCFG_SYSSP_SHF) - -/* field: PCI1DMD */ -#define TX4938_CCFG_PCI1DMD_SHF 8 -#define TX4938_CCFG_PCI1DMD_MSK (MSK(1) << TX4938_CCFG_PCI1DMD_SHF) - -/* field: PCIDIVMODE */ -#define TX4938_CCFG_PCIDIVMODE_SHF 10 -#define TX4938_CCFG_PCIDIVMODE_MSK (MSK(3) << TX4938_CCFG_PCIDIVMODE_SHF) - -/* field: PCI1-66 */ -#define TX4938_CCFG_PCI166_SHF 21 -#define TX4938_CCFG_PCI166_MSK ((UINT64)MSK(1) << TX4938_CCFG_PCI166_SHF) - -/* field: PCIMODE */ -#define TX4938_CCFG_PCIMODE_SHF 22 -#define TX4938_CCFG_PCIMODE_MSK ((UINT64)MSK(1) << TX4938_CCFG_PCIMODE_SHF) - -/* field: BRDTY */ -#define TX4938_CCFG_BRDTY_SHF 36 -#define TX4938_CCFG_RRDTY_MSK ((UINT64)MSK(4) << TX4938_CCFG_BRDTY_SHF) - -/* field: BRDRV */ -#define TX4938_CCFG_BRDRV_SHF 32 -#define TX4938_CCFG_BRDRV_MSK ((UINT64)MSK(4) << TX4938_CCFG_BRDRV_SHF) - -/******** reg: CLKCTR ********/ -/* field: PCIC1RST */ -#define TX4938_CLKCTR_PCIC1RST_SHF 11 -#define TX4938_CLKCTR_PCIC1RST_MSK (MSK(1) << TX4938_CLKCTR_PCIC1RST_SHF) - -/******** reg: PCISTATUS ********/ -/* field: MEMSP */ -#define TX4938_PCI_PCISTATUS_MEMSP_SHF 1 -#define TX4938_PCI_PCISTATUS_MEMSP_MSK (MSK(1) << TX4938_PCI_PCISTATUS_MEMSP_SHF) - -/* field: BM */ -#define TX4938_PCI_PCISTATUS_BM_SHF 2 -#define TX4938_PCI_PCISTATUS_BM_MSK (MSK(1) << TX4938_PCI_PCISTATUS_BM_SHF) - -/******** reg: PBACFG ********/ -/* field: RPBA */ -#define TX4938_PCI_PBACFG_RPBA_SHF 2 -#define TX4938_PCI_PBACFG_RPBA_MSK (MSK(1) << TX4938_PCI_PBACFG_RPBA_SHF) - -/* field: PBAEN */ -#define TX4938_PCI_PBACFG_PBAEN_SHF 1 -#define TX4938_PCI_PBACFG_PBAEN_MSK (MSK(1) << TX4938_PCI_PBACFG_PBAEN_SHF) - -/******** reg: PCICFG ********/ -/* field: G2PM0EN */ -#define TX4938_PCI_PCICFG_G2PM0EN_SHF 6 -#define TX4938_PCI_PCICFG_G2PM0EN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PM0EN_SHF) - -/* field: G2PIOEN */ -#define TX4938_PCI_PCICFG_G2PIOEN_SHF 5 -#define TX4938_PCI_PCICFG_G2PIOEN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PIOEN_SHF) - -/* field: TCAR */ -#define TX4938_PCI_PCICFG_TCAR_SHF 4 -#define TX4938_PCI_PCICFG_TCAR_MSK (MSK(1) << TX4938_PCI_PCICFG_TCAR_SHF) - - -#endif diff --git a/c/src/lib/libcpu/nios2/Makefile.am b/c/src/lib/libcpu/nios2/Makefile.am index fee88258c7..7641afb335 100644 --- a/c/src/lib/libcpu/nios2/Makefile.am +++ b/c/src/lib/libcpu/nios2/Makefile.am @@ -22,6 +22,5 @@ shared_misc_rel_CPPFLAGS = $(AM_CPPFLAGS) $(NIOS2_CPPFLAGS) shared_misc_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/nios2/configure.ac b/c/src/lib/libcpu/nios2/configure.ac index c37ad5509e..ce7fe1b4e9 100644 --- a/c/src/lib/libcpu/nios2/configure.ac +++ b/c/src/lib/libcpu/nios2/configure.ac @@ -3,6 +3,8 @@ AC_PREREQ([2.69]) AC_INIT([rtems-c-src-lib-libcpu-nios2],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) RTEMS_TOP([../../../../..],[../../..]) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP RTEMS_CANONICAL_TARGET_CPU diff --git a/c/src/lib/libcpu/nios2/preinstall.am b/c/src/lib/libcpu/nios2/preinstall.am deleted file mode 100644 index dba6cc4d81..0000000000 --- a/c/src/lib/libcpu/nios2/preinstall.am +++ /dev/null @@ -1,7 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - diff --git a/c/src/lib/libcpu/or1k/Makefile.am b/c/src/lib/libcpu/or1k/Makefile.am index 9c9921a100..e34d580982 100644 --- a/c/src/lib/libcpu/or1k/Makefile.am +++ b/c/src/lib/libcpu/or1k/Makefile.am @@ -12,6 +12,5 @@ shared_cache_rel_SOURCES = shared/cache/cache.c ../shared/src/cache_manager.c shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/or1k/configure.ac b/c/src/lib/libcpu/or1k/configure.ac index a089a82838..80c67b63c3 100644 --- a/c/src/lib/libcpu/or1k/configure.ac +++ b/c/src/lib/libcpu/or1k/configure.ac @@ -3,6 +3,8 @@ AC_PREREQ([2.69]) AC_INIT([rtems-c-src-lib-libcpu-or1k],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) RTEMS_TOP([../../../../..],[../../..]) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP RTEMS_CANONICAL_TARGET_CPU diff --git a/c/src/lib/libcpu/or1k/preinstall.am b/c/src/lib/libcpu/or1k/preinstall.am deleted file mode 100644 index dba6cc4d81..0000000000 --- a/c/src/lib/libcpu/or1k/preinstall.am +++ /dev/null @@ -1,7 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - diff --git a/c/src/lib/libcpu/powerpc/Makefile.am b/c/src/lib/libcpu/powerpc/Makefile.am index 5f8ee9f6c6..b56ce691bf 100644 --- a/c/src/lib/libcpu/powerpc/Makefile.am +++ b/c/src/lib/libcpu/powerpc/Makefile.am @@ -2,26 +2,6 @@ ACLOCAL_AMFLAGS = -I ../../../aclocal include $(top_srcdir)/../../../automake/compile.am -include_rtems_powerpcdir = $(includedir)/rtems/powerpc -include_rtems_powerpc_HEADERS = rtems/powerpc/cache.h \ - rtems/powerpc/debugmod.h rtems/powerpc/powerpc.h - -include_rtems_scoredir = $(includedir)/rtems/score -include_libcpudir = $(includedir)/libcpu - -include_libcpu_HEADERS = shared/include/powerpc-utility.h - -include_bspdir = $(includedir)/bsp - -include_bsp_HEADERS = -include_bsp_HEADERS += new-exceptions/bspsupport/irq_supp.h -include_bsp_HEADERS += new-exceptions/bspsupport/vectors.h - -include_mpc83xxdir = $(includedir)/mpc83xx - -include_mpc83xx_HEADERS = -include_mpc83xx_HEADERS += mpc83xx/i2c/mpc83xx_i2cdrv.h - EXTRA_DIST = noinst_PROGRAMS = new-exceptions/rtems-cpu.rel @@ -66,17 +46,11 @@ EXTRA_DIST += new-exceptions/bspsupport/ppc_exc_test.c # shared/include if shared -include_libcpu_HEADERS += shared/include/io.h shared/include/mmu.h \ - shared/include/page.h \ - shared/include/byteorder.h shared/include/pgtable.h - noinst_PROGRAMS += shared/cpuIdent.rel shared_cpuIdent_rel_SOURCES = shared/include/cpuIdent.c shared/include/cpuIdent.h shared_cpuIdent_rel_CPPFLAGS = $(AM_CPPFLAGS) shared_cpuIdent_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -include_libcpu_HEADERS += shared/include/cpuIdent.h - # shared/cache noinst_PROGRAMS += shared/cache.rel shared_cache_rel_SOURCES = shared/src/cache_.h \ @@ -91,8 +65,6 @@ shared_stack_rel_SOURCES = shared/src/stack.c shared/include/spr.h shared/src/st shared_stack_rel_CPPFLAGS = $(AM_CPPFLAGS) shared_stack_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -include_libcpu_HEADERS += shared/include/spr.h -include_libcpu_HEADERS += shared/src/stackTrace.h endif EXTRA_DIST += ppc403/README ppc403/vectors/README @@ -113,7 +85,6 @@ endif ppc403_console_rel_CPPFLAGS = $(AM_CPPFLAGS) ppc403_console_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -include_HEADERS = shared_cpuIdent_rel_SOURCES = shared/include/cpuIdent.c shared_cpuIdent_rel_CPPFLAGS = $(AM_CPPFLAGS) shared_cpuIdent_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) @@ -126,8 +97,6 @@ ppc403_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # ppc403/tty_drv if ppc405 -include_HEADERS += ppc403/tty_drv/tty_drv.h - noinst_PROGRAMS += ppc403/tty_drv.rel ppc403_tty_drv_rel_SOURCES = ppc403/tty_drv/tty_drv.c ppc403/tty_drv/tty_drv.h ppc403_tty_drv_rel_CPPFLAGS = $(AM_CPPFLAGS) @@ -139,20 +108,12 @@ endif # ppc4xx if ppc405 ## ppc4xx/include -include_ppc4xxdir = $(includedir)/ppc4xx -include_ppc4xx_HEADERS = ppc403/include/ppc405gp.h \ - ppc403/include/ppc405ex.h - endif # ppc405 ## mpc5xx EXTRA_DIST += mpc5xx/README if mpc5xx -include_mpc5xxdir = $(includedir)/mpc5xx - -include_HEADERS = mpc5xx/include/mpc5xx.h - # mpc5xx/clock noinst_PROGRAMS += mpc5xx/clock.rel mpc5xx_clock_rel_SOURCES = mpc5xx/clock/clock.c @@ -160,24 +121,18 @@ mpc5xx_clock_rel_CPPFLAGS = $(AM_CPPFLAGS) mpc5xx_clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # mpc5xx/console-generic -include_mpc5xx_HEADERS = mpc5xx/include/console.h - noinst_PROGRAMS += mpc5xx/console-generic.rel mpc5xx_console_generic_rel_SOURCES = mpc5xx/console-generic/console-generic.c mpc5xx_console_generic_rel_CPPFLAGS = $(AM_CPPFLAGS) mpc5xx_console_generic_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # mpc5xx/exceptions -include_libcpu_HEADERS += mpc5xx/exceptions/raw_exception.h - noinst_PROGRAMS += mpc5xx/exceptions.rel mpc5xx_exceptions_rel_SOURCES = mpc5xx/exceptions/raw_exception.c mpc5xx_exceptions_rel_CPPFLAGS = $(AM_CPPFLAGS) mpc5xx_exceptions_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # mpc5xx/irq -include_libcpu_HEADERS += mpc5xx/irq/irq.h - noinst_PROGRAMS += mpc5xx/irq.rel mpc5xx_irq_rel_SOURCES = mpc5xx/irq/irq.c mpc5xx/irq/irq_init.c mpc5xx/irq/irq_asm.S mpc5xx_irq_rel_CPPFLAGS = $(AM_CPPFLAGS) @@ -190,8 +145,6 @@ mpc5xx_timer_rel_CPPFLAGS = $(AM_CPPFLAGS) mpc5xx_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # mpc5xx/vectors -include_libcpu_HEADERS += mpc5xx/vectors/vectors.h - noinst_PROGRAMS += mpc5xx/vectors.rel mpc5xx_vectors_rel_SOURCES = mpc5xx/vectors/vectors_init.c mpc5xx/vectors/vectors.S \ new-exceptions/bspsupport/ppc_exc_print.c @@ -201,8 +154,6 @@ endif if mpc505 # mpc505/ictrl -include_HEADERS = mpc505/ictrl/ictrl.h - noinst_PROGRAMS += mpc505/ictrl.rel mpc505_ictrl_rel_SOURCES = mpc505/ictrl/ictrl.c mpc505_ictrl_rel_CPPFLAGS = $(AM_CPPFLAGS) @@ -224,8 +175,6 @@ endif if mpc6xx # mpc6xx/mmu -include_libcpu_HEADERS += mpc6xx/mmu/bat.h mpc6xx/mmu/pte121.h - noinst_PROGRAMS += mpc6xx/mmu.rel mpc6xx_mmu_rel_SOURCES = mpc6xx/mmu/bat.c mpc6xx/mmu/bat.h \ mpc6xx/mmu/pte121.c mpc6xx/mmu/pte121.h \ @@ -234,8 +183,6 @@ mpc6xx_mmu_rel_CPPFLAGS = $(AM_CPPFLAGS) mpc6xx_mmu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # mpc6xx/clock -include_libcpu_HEADERS += mpc6xx/clock/c_clock.h - noinst_PROGRAMS += mpc6xx/clock.rel mpc6xx_clock_rel_SOURCES = mpc6xx/clock/c_clock.c mpc6xx/clock/c_clock.h mpc6xx_clock_rel_CPPFLAGS = $(AM_CPPFLAGS) @@ -257,8 +204,6 @@ EXTRA_DIST += mpc6xx/altivec/README # e500/clock if e500_clock -include_libcpu_HEADERS += mpc6xx/clock/c_clock.h - noinst_PROGRAMS += e500/clock.rel e500_clock_rel_SOURCES = mpc6xx/clock/c_clock.c mpc6xx/clock/c_clock.h e500_clock_rel_CPPFLAGS = $(AM_CPPFLAGS) @@ -275,7 +220,6 @@ endif # e500/mmu if e500_mmu -include_libcpu_HEADERS += e500/mmu/e500_mmu.h noinst_PROGRAMS += e500/mmu.rel e500_mmu_rel_SOURCES = e500/mmu/mmu.c e500/mmu/e500_mmu.h e500_mmu_rel_CPPFLAGS = $(AM_CPPFLAGS) @@ -284,10 +228,6 @@ endif EXTRA_DIST += mpc8xx/README if mpc8xx -include_mpc8xxdir = $(includedir)/mpc8xx - -include_HEADERS = mpc8xx/include/mpc8xx.h - # mpc8xx/clock noinst_PROGRAMS += mpc8xx/clock.rel mpc8xx_clock_rel_SOURCES = mpc8xx/clock/clock.c @@ -295,24 +235,18 @@ mpc8xx_clock_rel_CPPFLAGS = $(AM_CPPFLAGS) mpc8xx_clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # mpc8xx/console-generic -include_mpc8xx_HEADERS = mpc8xx/include/console.h - noinst_PROGRAMS += mpc8xx/console-generic.rel mpc8xx_console_generic_rel_SOURCES = mpc8xx/console-generic/console-generic.c mpc8xx_console_generic_rel_CPPFLAGS = $(AM_CPPFLAGS) mpc8xx_console_generic_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # mpc8xx/cpm -include_mpc8xx_HEADERS += mpc8xx/include/cpm.h - noinst_PROGRAMS += mpc8xx/cpm.rel mpc8xx_cpm_rel_SOURCES = mpc8xx/cpm/cp.c mpc8xx/cpm/dpram.c mpc8xx_cpm_rel_CPPFLAGS = $(AM_CPPFLAGS) mpc8xx_cpm_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # mpc8xx/mmu -include_mpc8xx_HEADERS += mpc8xx/include/mmu.h - noinst_PROGRAMS += mpc8xx/mmu.rel mpc8xx_mmu_rel_SOURCES = mpc8xx/mmu/mmu.c mpc8xx_mmu_rel_CPPFLAGS = $(AM_CPPFLAGS) @@ -327,13 +261,7 @@ endif EXTRA_DIST += mpc8260/README if mpc8260 -include_mpc8260dir = $(includedir)/mpc8260 - -include_HEADERS = mpc8260/include/mpc8260.h - # mpc8260/console-generic -include_mpc8260_HEADERS = mpc8260/include/console.h - noinst_PROGRAMS += mpc8260/console-generic.rel mpc8260_console_generic_rel_SOURCES = mpc8260/console-generic/console-generic.c \ mpc8260/include/console.h @@ -341,8 +269,6 @@ mpc8260_console_generic_rel_CPPFLAGS = $(AM_CPPFLAGS) mpc8260_console_generic_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # mpc8260/cpm -include_mpc8260_HEADERS += mpc8260/include/cpm.h - noinst_PROGRAMS += mpc8260/cpm.rel mpc8260_cpm_rel_SOURCES = mpc8260/cpm/cp.c mpc8260/cpm/dpram.c mpc8260/cpm/brg.c \ mpc8260/include/cpm.h @@ -350,8 +276,6 @@ mpc8260_cpm_rel_CPPFLAGS = $(AM_CPPFLAGS) mpc8260_cpm_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # mpc8260/mmu -include_mpc8260_HEADERS += mpc8260/include/mmu.h - noinst_PROGRAMS += mpc8260/mmu.rel mpc8260_mmu_rel_SOURCES = mpc8260/mmu/mmu.c \ mpc8260/include/mmu.h @@ -372,10 +296,7 @@ if mpc83xx # Includes -include_mpc83xx_HEADERS += mpc83xx/include/mpc83xx.h - # Network -include_bsp_HEADERS += mpc83xx/network/tsec.h if HAS_NETWORKING noinst_PROGRAMS += mpc83xx/tsec.rel mpc83xx_tsec_rel_SOURCES = mpc83xx/network/tsec.c @@ -390,14 +311,12 @@ mpc83xx_i2c_rel_SOURCES = mpc83xx/i2c/mpc83xx_i2cdrv.c \ mpc83xx_i2c_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # SPI -include_mpc83xx_HEADERS += mpc83xx/spi/mpc83xx_spidrv.h noinst_PROGRAMS += mpc83xx/spi.rel mpc83xx_spi_rel_SOURCES = mpc83xx/spi/mpc83xx_spidrv.c \ mpc83xx/spi/mpc83xx_spidrv.h mpc83xx_spi_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # GTM -include_mpc83xx_HEADERS += mpc83xx/include/gtm.h noinst_PROGRAMS += mpc83xx/gtm.rel mpc83xx_gtm_rel_SOURCES = mpc83xx/gtm/gtm.c \ mpc83xx/include/gtm.h @@ -413,27 +332,6 @@ endif ############################################################################## if mpc55xx -# Includes -include_mpc55xxdir = $(includedir)/mpc55xx - -include_mpc55xx_HEADERS = -include_mpc55xx_HEADERS += mpc55xx/include/regs.h -include_mpc55xx_HEADERS += mpc55xx/include/reg-defs.h -include_mpc55xx_HEADERS += mpc55xx/include/dspi.h -include_mpc55xx_HEADERS += mpc55xx/include/edma.h -include_mpc55xx_HEADERS += mpc55xx/include/emios.h -include_mpc55xx_HEADERS += mpc55xx/include/mpc55xx.h -include_mpc55xx_HEADERS += mpc55xx/include/siu.h -include_mpc55xx_HEADERS += mpc55xx/include/watchdog.h -include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc551x.h -include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc555x.h -include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc556x.h -include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc564xL.h -include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc5668.h -include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc567x.h -include_mpc55xx_HEADERS += mpc55xx/include/regs-edma.h -include_mpc55xx_HEADERS += mpc55xx/include/regs-mmu.h - # IRQ noinst_PROGRAMS += mpc55xx/irq.rel mpc55xx_irq_rel_SOURCES = mpc55xx/irq/irq.c @@ -487,7 +385,6 @@ endif if qoriq # Network -include_bsp_HEADERS += mpc83xx/network/tsec.h if HAS_NETWORKING noinst_PROGRAMS += tsec.rel tsec_rel_SOURCES = mpc83xx/network/tsec.c @@ -500,5 +397,4 @@ endif # END: QorIQ # ############################################################################## -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/configure.ac b/c/src/lib/libcpu/powerpc/configure.ac index 81e6bfab2c..ba654372f1 100644 --- a/c/src/lib/libcpu/powerpc/configure.ac +++ b/c/src/lib/libcpu/powerpc/configure.ac @@ -4,6 +4,8 @@ AC_PREREQ([2.69]) AC_INIT([rtems-c-src-lib-libcpu-powerpc],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([mpc6xx]) RTEMS_TOP([../../../../..],[../../..]) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP RTEMS_CANONICAL_TARGET_CPU diff --git a/c/src/lib/libcpu/powerpc/e500/mmu/e500_mmu.h b/c/src/lib/libcpu/powerpc/e500/mmu/e500_mmu.h deleted file mode 100644 index 84920e0d14..0000000000 --- a/c/src/lib/libcpu/powerpc/e500/mmu/e500_mmu.h +++ /dev/null @@ -1,230 +0,0 @@ -#ifndef RTEMS_E500_MMU_DRIVER_H -#define RTEMS_E500_MMU_DRIVER_H - -/* - * Routines to manipulate e500 TLBs; TLB0 (fixed 4k page size) - * is not very useful so we mostly focus on TLB1 (variable page size) - */ - -/* - * Authorship - * ---------- - * This software was created by - * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, - * Stanford Linear Accelerator Center, Stanford University. - * - * Acknowledgement of sponsorship - * ------------------------------ - * This software was produced by - * the Stanford Linear Accelerator Center, Stanford University, - * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * - * Government disclaimer of liability - * ---------------------------------- - * Neither the United States nor the United States Department of Energy, - * nor any of their employees, makes any warranty, express or implied, or - * assumes any legal liability or responsibility for the accuracy, - * completeness, or usefulness of any data, apparatus, product, or process - * disclosed, or represents that its use would not infringe privately owned - * rights. - * - * Stanford disclaimer of liability - * -------------------------------- - * Stanford University makes no representations or warranties, express or - * implied, nor assumes any liability for the use of this software. - * - * Stanford disclaimer of copyright - * -------------------------------- - * Stanford University, owner of the copyright, hereby disclaims its - * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * - * Maintenance of notices - * ---------------------- - * In the interest of clarity regarding the origin and status of this - * SLAC software, this and all the preceding Stanford University notices - * are to remain affixed to any copy or derivative of this software made - * or distributed by the recipient and are to be affixed to any copy of - * software made or distributed by the recipient that contains a copy or - * derivative of this software. - * - * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 - */ - -#include <rtems.h> -#include <inttypes.h> -#include <stdio.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Some routines require or return a index 'key'. This - * is simply the TLB entry # ORed with E500_SELTLB_0 - * or E500_SELTLB_1 specifying an entry in TLB0 or TLB1, - * respectively. - */ -typedef int rtems_e500_tlb_idx; -#define E500_SELTLB_0 0x0000 -#define E500_SELTLB_1 0x1000 - -/* Cache the relevant TLB1 entries so that we can - * make sure the user cannot create conflicting - * (overlapping) entries. - * Keep them public for informational purposes. - */ -typedef struct { - struct { - uint32_t va_epn: 20; - uint32_t va_tid: 12; - } va; - uint32_t rpn; - struct { - uint32_t sz: 4; - uint32_t ts: 1; - uint32_t v: 1; - uint32_t perm: 10; - uint32_t wimge: 7; - } att; -} E500_tlb_va_cache_t; - -extern E500_tlb_va_cache_t rtems_e500_tlb_va_cache[16]; - -/* - * Dump (cleartext) content info from cached TLB entries - * to a file (stdout if f==NULL). - */ -void -rtems_e500_dmptlbc(FILE *f); - -/* - * Read a TLB entry from the hardware; if it is a TLB1 entry - * then the current settings are stored in the - * rtems_e500_tlb_va_cache[] structure. - * - * The routine can perform this operation quietly or - * print information to a file. - * - * 'key': TLB entry index ORed with selector bit - * (E500_SELTLB_0 for TLB0, E500_SELTLB_1 for TLB1). - * 'quiet': perform operation silently (no info printed) - * if nonzero. - * 'f': open FILE where to print information. May be - * NULL in which case 'stdout' is used. - * - * RETURNS: - * 0: success; TLB entry is VALID - * +1: success but TLB entry is INVALID - * < 0: error (-1: invalid argument) - */ -int -rtems_e500_prtlb(rtems_e500_tlb_idx key, int quiet, FILE *f); - -/* Initialize cache; verify that TLB0 is unused; - * - * RETURNS: zero on success, nonzero on error (TLB0 - * seems to be in use); in this case the - * driver will refuse to change TLB1 entries - * (other than disabling them). - */ -int -rtems_e500_initlb(void); - -/* - * Write TLB1 entry (can also be used to disable an entry). - * - * The routine checks against the cached data in - * rtems_e500_tlb_va[] to prevent the user from generating - * overlapping entries. - * - * 'idx': TLB 1 entry # to manipulate - * 'ea': Effective address (must be page aligned) - * 'pa': Physical address (must be page aligned) - * 'sz': Page size selector; page size is - * 1024 * 2^(2*sz) bytes. - * 'sz' may also be one of the following: - * - page size in bytes ( >= 1024 ); the selector - * value is then computed by this routine. - * However, 'sz' must be a valid page size - * or -1 will be returned. - * - a value < 0 to invalidate/disable the - * TLB entry. - * 'attr': Page attributes; ORed combination of WIMGE, - * PERMissions, TID and TS. Use ATTR_xxx macros - * - * RETURNS: 0 on success, nonzero on error: - * - * >0: requested mapping would overlap with - * existing mapping in other entry. Return - * value gives conflicting entry + 1; i.e., - * if a value of 4 is returned then the request - * conflicts with existing mapping in entry 3. - * -1: invalid argument - * -3: driver not initialized (or initialization - * failed because TLB0 is in use). - * <0: other error - * - */ -#define E500_TLB_ATTR_WIMGE(x) ((x)&0x7f) /* includes user bits */ -#define E500_TLB_ATTR_WIMGE_GET(x) ((x)&0x7f) -#define E500_TLB_ATTR_TS (1<<7) -#define E500_TLB_ATTR_PERM(x) (((x)&0x3ff)<<8) -#define E500_TLB_ATTR_PERM_GET(x) (((x)>>8)&0x3ff) -#define E500_TLB_ATTR_TID(x) (((x)&0xfff)<<20) -#define E500_TLB_ATTR_TID_GET(x) (((x)>>20)&0xfff) - -int -rtems_e500_wrtlb(int idx, uint32_t ea, uint32_t pa, int sz, uint32_t attr); - -/* - * Check if a ts/tid/ea/sz mapping overlaps - * with an existing entry. - * - * ASSUMPTION: all TLB0 (fixed 4k pages) are invalid and always unused. - * - * NOTE: 'sz' is the 'logarithmic' size selector; the page size - * is 1024*2^(2*sz). - * - * RETURNS: - * >= 0: index of TLB1 entry that already provides a mapping - * which overlaps within the ea range. - * -1: SUCCESS (no conflicting entry found) - * <=-2: ERROR (invalid input) - */ -int -rtems_e500_matchtlb(uint32_t ea, uint32_t tid, int ts, int sz); - -/* Find TLB index that maps 'ea/as' combination - * - * RETURNS: index 'key'; i.e., the index number plus - * a bit (E500_SELTLB_1) which indicates whether - * the mapping was found in TLB0 (4k fixed page - * size) or in TLB1 (variable page size). - * - * On error (no mapping) -1 is returned. - */ -rtems_e500_tlb_idx -rtems_e500_ftlb(uint32_t ea, int as); - -/* Mark TLB entry as invalid ('disabled'). Unlike - * rtems_e500_wrtlb() with a negative size argument - * this routine also can disable TLB0 entries. - * - * 'key': TLB entry index ORed with selector bit - * (E500_SELTLB_0 for TLB0, E500_SELTLB_1 for TLB1). - * - * RETURNS: zero on success, nonzero on error (TLB - * unchanged). - * - * NOTE: If a TLB1 entry is disabled the associated - * entry in rtems_e500_va_cache[] is also - * marked as disabled. - */ -int -rtems_e500_clrtlb(rtems_e500_tlb_idx key); - -#ifdef __cplusplus -}; -#endif - -#endif diff --git a/c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.h b/c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.h deleted file mode 100644 index 303ece825d..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.h +++ /dev/null @@ -1,75 +0,0 @@ -#ifndef _ICTRL_H -#define _ICTRL_H - -/* - * mpc505/509 external interrupt controller management. - * - * FIXME: should be somehow merged into general RTEMS interrupt - * management code. - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#define _SIU_IRQENABLE ((unsigned long volatile *const)0x8007EFA8) -#define _SIU_IRQPEND ((unsigned long volatile *const)0x8007EFA0) - -/* Interrupt masks. */ -enum { - IMASK_EXT0 = 0x80000000, - IMASK_EXT1 = 0x20000000, - IMASK_EXT2 = 0x08000000, - IMASK_EXT3 = 0x02000000, - IMASK_EXT4 = 0x00800000, - IMASK_EXT5 = 0x00200000, - IMASK_EXT6 = 0x00080000, - IMASK_ALL = IMASK_EXT0 | IMASK_EXT1 | IMASK_EXT2 | IMASK_EXT3 | - IMASK_EXT4 | IMASK_EXT5 | IMASK_EXT6 -}; - -/* Interrupt numbers. */ -typedef enum { - IRQ_EXT0, - IRQ_EXT1, - IRQ_EXT2, - IRQ_EXT3, - IRQ_EXT4, - IRQ_EXT5, - IRQ_EXT6, - NUM_IRQS -} ExtInt; - -/* Type of external interrupt handlers */ -typedef void (*ExtIsrHandler) (void); - -/* Initialization. Must be called once after RTEMS interrupts sybsystem - is initiailized. 'predriver_hook' is one of such places. */ -extern void extIsrInit( void ); - -/* Set interrupt handler 'handler' for external interrupt number - 'interrupt'. */ -extern void extIrqSetHandler(ExtInt interrupt, ExtIsrHandler handler); - -/* Check is external interrupt 'irq' (IMASK_XXXX) is pended. */ -#define extIrqIsSet(irq) \ - (*_SIU_IRQPEND & (irq)) - -/* Enable external interrupt 'irq' (IMASK_XXXX) processing. */ -#define extIrqEnable(irq) \ - (*_SIU_IRQENABLE |= (irq)) - -/* Disable external interrupt 'irq' (IMASK_XXXX) processing. */ -#define extIrqDisable(irq) \ - (*_SIU_IRQENABLE &= ~(irq)) - -/* Check if external interrupt 'irq' (IMASK_XXXX) processing is - enabled. */ -#define extIrqGetEnable \ - (*_SIU_IRQENABLE) - -#ifdef __cplusplus -} -#endif - -#endif /* _ICTRL_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/dspi.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/dspi.h deleted file mode 100644 index 8ad98274ef..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/dspi.h +++ /dev/null @@ -1,128 +0,0 @@ -/** - * @file - * - * @ingroup mpc55xx_dspi - * - * @brief Header file for the LibI2C bus driver for the Deserial Serial Peripheral Interface (DSPI). - */ - -/* - * Copyright (c) 2008 - * Embedded Brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * rtems@embedded-brains.de - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/** - * @defgroup mpc55xx_dspi Deserial Serial Peripheral Interface (DSPI) - * - * @ingroup mpc55xx - */ - -#ifndef LIBCPU_POWERPC_MPC55XX_DSPI_H -#define LIBCPU_POWERPC_MPC55XX_DSPI_H - -#include <rtems/libi2c.h> - -#include <mpc55xx/edma.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -struct DSPI_tag; - -typedef struct { - edma_channel_context edma; - rtems_id id; -} mpc55xx_dspi_edma_entry; - -/** - * @brief LibI2C bus driver entry. - */ -typedef struct { - /** - * @brief Standard bus driver fields. - */ - rtems_libi2c_bus_t bus; - - /** - * @brief Index in the bus table: @ref mpc55xx_dspi_bus_table. - */ - unsigned table_index; - - /** - * @brief Bus number (available after rtems_libi2c_register_bus()). - * - * @note You must set it in the initialization code after the bus registration. - */ - unsigned bus_number; - - /** - * @brief Hardware registers. - */ - volatile struct DSPI_tag *regs; - - /** - * @brief Selects SPI master or slave mode. - */ - bool master; - - /** - * @brief Data for the Push Register. - */ - union DSPI_PUSHR_tag push_data; - - /** - * @brief eDMA entry for transmission. - * - * The channel is fixed to a particular DSPI. - */ - mpc55xx_dspi_edma_entry edma_transmit; - - /** - * @brief eDMA entry for push data generation. - * - * You can choose every available channel. - */ - mpc55xx_dspi_edma_entry edma_push; - - /** - * @brief eDMA entry for receiving. - * - * The channel is fixed to a particular DSPI. - */ - mpc55xx_dspi_edma_entry edma_receive; - - /** - * @brief Idle character transmitted in read only mode. - */ - uint32_t idle_char; - - /** - * @brief Current baud. - */ - uint32_t baud; -} mpc55xx_dspi_bus_entry; - -/** - * @brief Number of DSPIs. - */ -#define MPC55XX_DSPI_NUMBER 4 - -/** - * @brief Table with bus driver entries. - */ -extern mpc55xx_dspi_bus_entry mpc55xx_dspi_bus_table [ /* MPC55XX_DSPI_NUMBER */ ]; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBCPU_POWERPC_MPC55XX_DSPI_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/edma.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/edma.h deleted file mode 100644 index 281cdf1c28..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/edma.h +++ /dev/null @@ -1,329 +0,0 @@ -/** - * @file - * - * @ingroup mpc55xx - * - * @brief Enhanced Direct Memory Access (eDMA). - */ - -/* - * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBCPU_POWERPC_MPC55XX_EDMA_H -#define LIBCPU_POWERPC_MPC55XX_EDMA_H - -#include <mpc55xx/regs.h> - -#include <rtems.h> -#include <rtems/chain.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#if MPC55XX_CHIP_FAMILY == 551 - #define EDMA_CHANNEL_COUNT 16U -#elif MPC55XX_CHIP_FAMILY == 564 - #define EDMA_CHANNEL_COUNT 16U -#elif MPC55XX_CHIP_FAMILY == 567 - #define EDMA_CHANNEL_COUNT 96U -#else - #define EDMA_CHANNEL_COUNT 64U -#endif - -#define EDMA_MODULE_COUNT ((EDMA_CHANNEL_COUNT + 63U) / 64U) - -#define EDMA_CHANNELS_PER_MODULE 64U - -#if EDMA_MODULE_COUNT == 1 - #define EDMA_TCD_BY_CHANNEL_INDEX(channel_index) \ - (&EDMA.TCD[(channel_index)]) -#elif EDMA_MODULE_COUNT == 2 - #define EDMA_TCD_BY_CHANNEL_INDEX(channel_index) \ - ((channel_index) < EDMA_CHANNELS_PER_MODULE ? \ - &EDMA_A.TCD[(channel_index)] \ - : &EDMA_B.TCD[(channel_index) - EDMA_CHANNELS_PER_MODULE]) -#else - #error "unsupported module count" -#endif - -/* FIXME: These values are only valid for the MPC5566 and MPC5674F */ -typedef enum { - EDMA_EQADC_A_FISR0_CFFF0 = 0, - EDMA_EQADC_A_FISR0_RFDF0 = 1, - EDMA_EQADC_A_FISR1_CFFF1 = 2, - EDMA_EQADC_A_FISR1_RFDF1 = 3, - EDMA_EQADC_A_FISR2_CFFF2 = 4, - EDMA_EQADC_A_FISR2_RFDF2 = 5, - EDMA_EQADC_A_FISR3_CFFF3 = 6, - EDMA_EQADC_A_FISR3_RFDF3 = 7, - EDMA_EQADC_A_FISR4_CFFF4 = 8, - EDMA_EQADC_A_FISR4_RFDF4 = 9, - EDMA_EQADC_A_FISR5_CFFF5 = 10, - EDMA_EQADC_A_FISR5_RFDF5 = 11, - EDMA_DSPI_B_SR_TFFF = 12, - EDMA_DSPI_B_SR_RFDF = 13, - EDMA_DSPI_C_SR_TFFF = 14, - EDMA_DSPI_C_SR_RFDF = 15, - EDMA_DSPI_D_SR_TFFF = 16, - EDMA_DSPI_D_SR_RFDF = 17, - EDMA_ESCI_A_COMBTX = 18, - EDMA_ESCI_A_COMBRX = 19, - EDMA_EMIOS_GFR_F0 = 20, - EDMA_EMIOS_GFR_F1 = 21, - EDMA_EMIOS_GFR_F2 = 22, - EDMA_EMIOS_GFR_F3 = 23, - EDMA_EMIOS_GFR_F4 = 24, - EDMA_EMIOS_GFR_F8 = 25, - EDMA_EMIOS_GFR_F9 = 26, - EDMA_ETPU_CDTRSR_A_DTRS0 = 27, - EDMA_ETPU_CDTRSR_A_DTRS1 = 28, - EDMA_ETPU_CDTRSR_A_DTRS2 = 29, - EDMA_ETPU_CDTRSR_A_DTRS14 = 30, - EDMA_ETPU_CDTRSR_A_DTRS15 = 31, - EDMA_DSPI_A_SR_TFFF = 32, - EDMA_DSPI_A_SR_RFDF = 33, - EDMA_ESCI_B_COMBTX = 34, - EDMA_ESCI_B_COMBRX = 35, - EDMA_EMIOS_GFR_F6 = 36, - EDMA_EMIOS_GFR_F7 = 37, - EDMA_EMIOS_GFR_F10 = 38, - EDMA_EMIOS_GFR_F11 = 39, - EDMA_EMIOS_GFR_F16 = 40, - EDMA_EMIOS_GFR_F17 = 41, - EDMA_EMIOS_GFR_F18 = 42, - EDMA_EMIOS_GFR_F19 = 43, - EDMA_ETPU_CDTRSR_A_DTRS12 = 44, - EDMA_ETPU_CDTRSR_A_DTRS13 = 45, - EDMA_ETPU_CDTRSR_A_DTRS28 = 46, - EDMA_ETPU_CDTRSR_A_DTRS29 = 47, - EDMA_SIU_EISR_EIF0 = 48, - EDMA_SIU_EISR_EIF1 = 49, - EDMA_SIU_EISR_EIF2 = 50, - EDMA_SIU_EISR_EIF3 = 51, - EDMA_ETPU_CDTRSR_B_DTRS0 = 52, - EDMA_ETPU_CDTRSR_B_DTRS1 = 53, - EDMA_ETPU_CDTRSR_B_DTRS2 = 54, - EDMA_ETPU_CDTRSR_B_DTRS3 = 55, - EDMA_ETPU_CDTRSR_B_DTRS12 = 56, - EDMA_ETPU_CDTRSR_B_DTRS13 = 57, - EDMA_ETPU_CDTRSR_B_DTRS14 = 58, - EDMA_ETPU_CDTRSR_B_DTRS15 = 59, - EDMA_ETPU_CDTRSR_B_DTRS28 = 60, - EDMA_ETPU_CDTRSR_B_DTRS29 = 61, - EDMA_ETPU_CDTRSR_B_DTRS30 = 62, - EDMA_ETPU_CDTRSR_B_DTRS31 = 63 - #if MPC55XX_CHIP_FAMILY == 567 - , - EDMA_EQADC_B_FISR0_CFFF0 = 64 + 0, - EDMA_EQADC_B_FISR0_RFDF0 = 64 + 1, - EDMA_EQADC_B_FISR1_CFFF1 = 64 + 2, - EDMA_EQADC_B_FISR1_RFDF1 = 64 + 3, - EDMA_EQADC_B_FISR2_CFFF2 = 64 + 4, - EDMA_EQADC_B_FISR2_RFDF2 = 64 + 5, - EDMA_EQADC_B_FISR3_CFFF3 = 64 + 6, - EDMA_EQADC_B_FISR3_RFDF3 = 64 + 7, - EDMA_EQADC_B_FISR4_CFFF4 = 64 + 8, - EDMA_EQADC_B_FISR4_RFDF4 = 64 + 9, - EDMA_EQADC_B_FISR5_CFFF5 = 64 + 10, - EDMA_EQADC_B_FISR5_RFDF5 = 64 + 11, - EDMA_DECFILTER_A_IB = 64 + 12, - EDMA_DECFILTER_A_OB = 64 + 13, - EDMA_DECFILTER_B_IB = 64 + 14, - EDMA_DECFILTER_B_OB = 64 + 15, - EDMA_DECFILTER_C_IB = 64 + 16, - EDMA_DECFILTER_C_OB = 64 + 17, - EDMA_DECFILTER_D_IB = 64 + 18, - EDMA_DECFILTER_D_OB = 64 + 19, - EDMA_DECFILTER_E_IB = 64 + 20, - EDMA_DECFILTER_E_OB = 64 + 21, - EDMA_DECFILTER_F_IB = 64 + 22, - EDMA_DECFILTER_F_OB = 64 + 23, - EDMA_DECFILTER_G_IB = 64 + 24, - EDMA_DECFILTER_G_OB = 64 + 25, - EDMA_DECFILTER_H_IB = 64 + 26, - EDMA_DECFILTER_H_OB = 64 + 27 - #endif -} edma_channel; - -typedef struct edma_channel_context { - rtems_chain_node node; - volatile struct tcd_t *edma_tcd; - void (*done)(struct edma_channel_context *, uint32_t); -} edma_channel_context; - -void mpc55xx_edma_init(void); - -/** - * @brief Obtains an eDMA channel. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_RESOURCE_IN_USE The channel is already in use. - */ -rtems_status_code mpc55xx_edma_obtain_channel_by_tcd( - volatile struct tcd_t *edma_tcd -); - -void mpc55xx_edma_release_channel_by_tcd(volatile struct tcd_t *edma_tcd); - -/** - * @brief Obtains an eDMA channel and registers the channel context. - * - * The done handler of the channel context will be called - * - during minor or major loop completions if interrupts are enabled in the - * corresponding TCD, or - * - in case a channel error occurs. - * - * An error status value not equal to zero indicates an error. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_RESOURCE_IN_USE The channel is already in use. - * @retval RTEMS_IO_ERROR Unable to install interrupt handler for this channel. - */ -rtems_status_code mpc55xx_edma_obtain_channel( - edma_channel_context *ctx, - unsigned irq_priority -); - -void mpc55xx_edma_release_channel(edma_channel_context *ctx); - -/** - * @brief Copies a source TCD to an eDMA TCD. - * - * The DONE flag of the eDMA TCD is cleared before the actual copy operation. - * This enables the setting of channel link or scatter/gather options. - * - * This function can be used to start the channel if the START flags is - * set in the source TCD. - */ -void mpc55xx_edma_copy( - volatile struct tcd_t *edma_tcd, - const struct tcd_t *source_tcd -); - -/** - * @brief Copies a source TCD to an eDMA TCD and enables hardware requests. - * - * The DONE flag of the eDMA TCD is cleared before the actual copy operation. - * This enables the setting of channel link or scatter/gather options. - */ -void mpc55xx_edma_copy_and_enable_hardware_requests( - volatile struct tcd_t *edma_tcd, - const struct tcd_t *source_tcd -); - -void mpc55xx_edma_sg_link( - volatile struct tcd_t *edma_tcd, - const struct tcd_t *source_tcd -); - -static inline volatile struct EDMA_tag *mpc55xx_edma_by_tcd( - volatile struct tcd_t *edma_tcd -) -{ - return (volatile struct EDMA_tag *) - ((uintptr_t) edma_tcd & ~(uintptr_t) 0x1fff); -} - -static inline unsigned mpc55xx_edma_channel_by_tcd( - volatile struct tcd_t *edma_tcd -) -{ - volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); - - return edma_tcd - &edma->TCD[0]; -} - -static inline void mpc55xx_edma_enable_hardware_requests( - volatile struct tcd_t *edma_tcd -) -{ - volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); - unsigned channel = edma_tcd - &edma->TCD[0]; - - edma->SERQR.R = (uint8_t) channel; -} - -static inline void mpc55xx_edma_disable_hardware_requests( - volatile struct tcd_t *edma_tcd -) -{ - volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); - unsigned channel = edma_tcd - &edma->TCD[0]; - - edma->CERQR.R = (uint8_t) channel; -} - -static inline void mpc55xx_edma_enable_error_interrupts( - volatile struct tcd_t *edma_tcd -) -{ - volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); - unsigned channel = edma_tcd - &edma->TCD[0]; - - edma->SEEIR.R = (uint8_t) channel; -} - -static inline void mpc55xx_edma_disable_error_interrupts( - volatile struct tcd_t *edma_tcd -) -{ - volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); - unsigned channel = edma_tcd - &edma->TCD[0]; - - edma->CEEIR.R = (uint8_t) channel; -} - -static inline void mpc55xx_edma_set_start( - volatile struct tcd_t *edma_tcd -) -{ - volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); - unsigned channel = edma_tcd - &edma->TCD[0]; - - edma->SSBR.R = (uint8_t) channel; -} - -static inline void mpc55xx_edma_clear_done( - volatile struct tcd_t *edma_tcd -) -{ - volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); - unsigned channel = edma_tcd - &edma->TCD[0]; - - edma->CDSBR.R = (uint8_t) channel; -} - -static inline void mpc55xx_edma_clear_interrupts( - volatile struct tcd_t *edma_tcd -) -{ - volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); - unsigned channel = edma_tcd - &edma->TCD[0]; - - edma->CIRQR.R = (uint8_t) channel; -} - -static inline bool mpc55xx_edma_is_done( - volatile struct tcd_t *edma_tcd -) -{ - return edma_tcd->BMF.B.DONE; -} - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBCPU_POWERPC_MPC55XX_EDMA_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/emios.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/emios.h deleted file mode 100644 index d6ccadc07b..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/emios.h +++ /dev/null @@ -1,197 +0,0 @@ -/** - * @file - * - * @ingroup mpc55xx - * - * @brief Enhanced Modular Input Output Subsystem (eMIOS). - */ - -/* - * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBCPU_POWERPC_MPC55XX_EMIOS_H -#define LIBCPU_POWERPC_MPC55XX_EMIOS_H - -#include <mpc55xx/regs.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifdef MPC55XX_HAS_EMIOS - -/** - * @name eMIOS - Modes - * - * @{ - */ - -#define MPC55XX_EMIOS_MODE_GPIO_INPUT 0U -#define MPC55XX_EMIOS_MODE_GPIO_OUTPUT 1U -#define MPC55XX_EMIOS_MODE_SAIC 2U -#define MPC55XX_EMIOS_MODE_SAOC 3U -#define MPC55XX_EMIOS_MODE_IPWM 4U -#define MPC55XX_EMIOS_MODE_IPM 5U -#define MPC55XX_EMIOS_MODE_DAOC_SECOND 6U -#define MPC55XX_EMIOS_MODE_DAOC_BOTH 7U -#define MPC55XX_EMIOS_MODE_PEA_ACCU_CONT 8U -#define MPC55XX_EMIOS_MODE_PEA_ACCU_SINGLE 9U -#define MPC55XX_EMIOS_MODE_PEA_COUNT_CONT 10U -#define MPC55XX_EMIOS_MODE_PEA_COUNT_SINGLE 11U -#define MPC55XX_EMIOS_MODE_QDEC_COUNT_DIR 12U -#define MPC55XX_EMIOS_MODE_QDEC_PHASE 13U -#define MPC55XX_EMIOS_MODE_WPTA 14U -#define MPC55XX_EMIOS_MODE_RESERVED_15 15U -#define MPC55XX_EMIOS_MODE_MC_UP_INT_CLK 16U -#define MPC55XX_EMIOS_MODE_MC_UP_EXT_CLK 17U -#define MPC55XX_EMIOS_MODE_RESERVED_18 18U -#define MPC55XX_EMIOS_MODE_RESERVED_19 19U -#define MPC55XX_EMIOS_MODE_MC_UP_DOWN_INT_CLK 20U -#define MPC55XX_EMIOS_MODE_MC_UP_DOWN_EXT_CLK 21U -#define MPC55XX_EMIOS_MODE_MC_UP_DOWN_CHANGE_INT_CLK 22U -#define MPC55XX_EMIOS_MODE_MC_UP_DOWN_CHANGE_EXT_CLK 23U -#define MPC55XX_EMIOS_MODE_OPWFM_B_IMMEDIATE 24U -#define MPC55XX_EMIOS_MODE_OPWFM_B_NEXT_PERIOD 25U -#define MPC55XX_EMIOS_MODE_OPWFM_AB_IMMEDIATE 26U -#define MPC55XX_EMIOS_MODE_OPWFM_AB_NEXT_PERIOD 27U -#define MPC55XX_EMIOS_MODE_OPWMC_TRAIL_TRAIL 28U -#define MPC55XX_EMIOS_MODE_OPWMC_TRAIL_LEAD 29U -#define MPC55XX_EMIOS_MODE_OPWMC_BOTH_TRAIL 30U -#define MPC55XX_EMIOS_MODE_OPWMC_BOTH_LEAD 31U -#define MPC55XX_EMIOS_MODE_OPWM_B_IMMEDIATE 32U -#define MPC55XX_EMIOS_MODE_OPWM_B_NEXT_PERIOD 33U -#define MPC55XX_EMIOS_MODE_OPWM_AB_IMMEDIATE 34U -#define MPC55XX_EMIOS_MODE_OPWM_AB_NEXT_PERIOD 35U -#define MPC55XX_EMIOS_MODE_RESERVED_36 36U -#define MPC55XX_EMIOS_MODE_RESERVED_37 37U -#define MPC55XX_EMIOS_MODE_RESERVED_38 38U -#define MPC55XX_EMIOS_MODE_RESERVED_39 39U -#define MPC55XX_EMIOS_MODE_RESERVED_40 40U -#define MPC55XX_EMIOS_MODE_RESERVED_41 41U -#define MPC55XX_EMIOS_MODE_RESERVED_42 42U -#define MPC55XX_EMIOS_MODE_RESERVED_43 43U -#define MPC55XX_EMIOS_MODE_RESERVED_44 44U -#define MPC55XX_EMIOS_MODE_RESERVED_45 45U -#define MPC55XX_EMIOS_MODE_RESERVED_46 46U -#define MPC55XX_EMIOS_MODE_RESERVED_47 47U -#define MPC55XX_EMIOS_MODE_RESERVED_48 48U -#define MPC55XX_EMIOS_MODE_RESERVED_49 49U -#define MPC55XX_EMIOS_MODE_RESERVED_50 50U -#define MPC55XX_EMIOS_MODE_RESERVED_51 51U -#define MPC55XX_EMIOS_MODE_RESERVED_52 52U -#define MPC55XX_EMIOS_MODE_RESERVED_53 53U -#define MPC55XX_EMIOS_MODE_RESERVED_54 54U -#define MPC55XX_EMIOS_MODE_RESERVED_55 55U -#define MPC55XX_EMIOS_MODE_RESERVED_56 56U -#define MPC55XX_EMIOS_MODE_RESERVED_57 57U -#define MPC55XX_EMIOS_MODE_RESERVED_58 58U -#define MPC55XX_EMIOS_MODE_RESERVED_59 59U -#define MPC55XX_EMIOS_MODE_RESERVED_60 60U -#define MPC55XX_EMIOS_MODE_RESERVED_61 61U -#define MPC55XX_EMIOS_MODE_RESERVED_62 62U -#define MPC55XX_EMIOS_MODE_RESERVED_63 63U -#define MPC55XX_EMIOS_MODE_RESERVED_64 64U -#define MPC55XX_EMIOS_MODE_RESERVED_65 65U -#define MPC55XX_EMIOS_MODE_RESERVED_66 66U -#define MPC55XX_EMIOS_MODE_RESERVED_67 67U -#define MPC55XX_EMIOS_MODE_RESERVED_68 68U -#define MPC55XX_EMIOS_MODE_RESERVED_69 69U -#define MPC55XX_EMIOS_MODE_RESERVED_70 70U -#define MPC55XX_EMIOS_MODE_RESERVED_71 71U -#define MPC55XX_EMIOS_MODE_RESERVED_72 72U -#define MPC55XX_EMIOS_MODE_RESERVED_73 73U -#define MPC55XX_EMIOS_MODE_RESERVED_74 74U -#define MPC55XX_EMIOS_MODE_RESERVED_75 75U -#define MPC55XX_EMIOS_MODE_RESERVED_76 76U -#define MPC55XX_EMIOS_MODE_RESERVED_77 77U -#define MPC55XX_EMIOS_MODE_RESERVED_78 78U -#define MPC55XX_EMIOS_MODE_RESERVED_79 79U -#define MPC55XX_EMIOS_MODE_MCB_UP_INT_CLK 80U -#define MPC55XX_EMIOS_MODE_MCB_UP_EXT_CLK 81U -#define MPC55XX_EMIOS_MODE_RESERVED_82 82U -#define MPC55XX_EMIOS_MODE_RESERVED_83 83U -#define MPC55XX_EMIOS_MODE_MCB_UP_DOWN_ONE_INT_CLK 84U -#define MPC55XX_EMIOS_MODE_MCB_UP_DOWN_ONE_EXT_CLK 85U -#define MPC55XX_EMIOS_MODE_MCB_UP_DOWN_BOTH_INT_CLK 86U -#define MPC55XX_EMIOS_MODE_MCB_UP_DOWN_BOTH_EXT_CLK 87U -#define MPC55XX_EMIOS_MODE_OPWFMB_B 88U -#define MPC55XX_EMIOS_MODE_RESERVED_89 89U -#define MPC55XX_EMIOS_MODE_OPWFMB_AB 90U -#define MPC55XX_EMIOS_MODE_RESERVED_91 91U -#define MPC55XX_EMIOS_MODE_OPWMCB_TRAIL_TRAIL 92U -#define MPC55XX_EMIOS_MODE_OPWMCB_TRAIL_LEAD 93U -#define MPC55XX_EMIOS_MODE_OPWMCB_BOTH_TRAIL 94U -#define MPC55XX_EMIOS_MODE_OPWMCB_BOTH_LEAD 95U -#define MPC55XX_EMIOS_MODE_OPWMB_SECOND 96U -#define MPC55XX_EMIOS_MODE_RESERVED_97 97U -#define MPC55XX_EMIOS_MODE_OPWMB_BOTH 98U -#define MPC55XX_EMIOS_MODE_RESERVED_99 99U -#define MPC55XX_EMIOS_MODE_RESERVED_100 100U -#define MPC55XX_EMIOS_MODE_RESERVED_101 101U -#define MPC55XX_EMIOS_MODE_RESERVED_102 102U -#define MPC55XX_EMIOS_MODE_RESERVED_103 103U -#define MPC55XX_EMIOS_MODE_RESERVED_104 104U -#define MPC55XX_EMIOS_MODE_RESERVED_105 105U -#define MPC55XX_EMIOS_MODE_RESERVED_106 106U -#define MPC55XX_EMIOS_MODE_RESERVED_107 107U -#define MPC55XX_EMIOS_MODE_RESERVED_108 108U -#define MPC55XX_EMIOS_MODE_RESERVED_109 109U -#define MPC55XX_EMIOS_MODE_RESERVED_110 110U -#define MPC55XX_EMIOS_MODE_RESERVED_111 111U -#define MPC55XX_EMIOS_MODE_RESERVED_112 112U -#define MPC55XX_EMIOS_MODE_RESERVED_113 113U -#define MPC55XX_EMIOS_MODE_RESERVED_114 114U -#define MPC55XX_EMIOS_MODE_RESERVED_115 115U -#define MPC55XX_EMIOS_MODE_RESERVED_116 116U -#define MPC55XX_EMIOS_MODE_RESERVED_117 117U -#define MPC55XX_EMIOS_MODE_RESERVED_118 118U -#define MPC55XX_EMIOS_MODE_RESERVED_119 119U -#define MPC55XX_EMIOS_MODE_RESERVED_120 120U -#define MPC55XX_EMIOS_MODE_RESERVED_121 121U -#define MPC55XX_EMIOS_MODE_RESERVED_122 122U -#define MPC55XX_EMIOS_MODE_RESERVED_123 123U -#define MPC55XX_EMIOS_MODE_RESERVED_124 124U -#define MPC55XX_EMIOS_MODE_RESERVED_125 125U -#define MPC55XX_EMIOS_MODE_RESERVED_126 126U -#define MPC55XX_EMIOS_MODE_RESERVED_127 127U - -/** @} */ - -#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 - #define MPC55XX_EMIOS_CHANNEL_NUMBER 32U -#else - #define MPC55XX_EMIOS_CHANNEL_NUMBER 24U -#endif - -#define MPC55XX_EMIOS_VALUE_MAX 0x00ffffffU - -#define MPC55XX_EMIOS_IS_CHANNEL_VALID( c) \ - ((unsigned) (c) < MPC55XX_EMIOS_CHANNEL_NUMBER) - -#define MPC55XX_EMIOS_IS_CHANNEL_INVALID( c) \ - (!MPC55XX_EMIOS_IS_CHANNEL_VALID( c)) - -void mpc55xx_emios_initialize( unsigned prescaler); - -unsigned mpc55xx_emios_global_prescaler( void); - -void mpc55xx_emios_set_global_prescaler( unsigned prescaler); - -#endif /* MPC55XX_HAS_EMIOS */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBCPU_POWERPC_MPC55XX_EMIOS_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc551x.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc551x.h deleted file mode 100644 index dec0b4cf73..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc551x.h +++ /dev/null @@ -1,4005 +0,0 @@ -/* - * Modifications of the original file provided by Freescale are: - * - * Copyright (c) 2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/**************************************************************************/ -/* FILE NAME: mpc5510.h COPYRIGHT (c) Freescale 2008 */ -/* REVISION: 2.2 All Rights Reserved */ -/* */ -/* DESCRIPTION: */ -/* This file contain all of the register and bit field definitions for */ -/* MPC5510. */ -/**************************************************************************/ -/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ - -/*************************************************/ -/* Example register & bit field write: */ -/* */ -/* <MODULE>.<REGISTER>.B.<BIT> = 1; */ -/* <MODULE>.<REGISTER>.R = 0x10000000; */ -/* */ -/*************************************************/ - -#ifndef _MPC5510_H_ -#define _MPC5510_H_ - -#ifndef ASM - -#include <stdint.h> - -#include <mpc55xx/regs-edma.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __MWERKS__ -#pragma push -#pragma ANSI_strict off -#endif - -/****************************************************************************/ -/* MODULE : CRP */ -/****************************************************************************/ - struct CRP_tag { - - union { - uint32_t R; - struct { - uint32_t:12; - uint32_t IRC32KEN:1; - uint32_t XOSCEN:1; - uint32_t:1; - uint32_t OSC32KEN:1; - uint32_t TRIM32IRC:8; - uint32_t TRIMIRC:8; - } B; - } CLKSRC; /* Clock Source Register */ - - uint32_t crp_reserved1[3]; - - union { - uint32_t R; - struct { - uint32_t CNTEN:1; - uint32_t RTCIE:1; - uint32_t RTCF:1; - uint32_t ROVRF:1; - uint32_t RTCVAL:12; - uint32_t APIEN:1; - uint32_t APIIE:1; - uint32_t APIF:1; - uint32_t CLKSEL:2; - uint32_t ROVREN:1; - uint32_t APIVAL:10; - } B; - } RTCSC; /* RTC Status and Control Register */ - - union { - uint32_t R; - struct { - uint32_t RTCCNT:32; - } B; - } RTCCNT; /* RTC Counter Register */ - - uint32_t crp_reserved2[10]; - - union { - uint32_t R; - struct { - uint32_t:1; - uint32_t WKPSEL7:3; - uint32_t:1; - uint32_t WKPSEL6:3; - uint32_t:1; - uint32_t WKPSEL5:3; - uint32_t:1; - uint32_t WKPSEL4:3; - uint32_t:1; - uint32_t WKPSEL3:3; - uint32_t:1; - uint32_t WKPSEL2:3; - uint32_t:1; - uint32_t WKPSEL1:3; - uint32_t:1; - uint32_t WKPSEL0:3; - } B; - } WKPINSEL; /* Wakeup Pin Source Select Register */ - - union { - uint32_t R; - struct { - uint32_t WKPDET7:2; - uint32_t WKPDET6:2; - uint32_t WKPDET5:2; - uint32_t WKPDET4:2; - uint32_t WKPDET3:2; - uint32_t WKPDET2:2; - uint32_t WKPDET1:2; - uint32_t WKPDET0:2; - uint32_t:5; - uint32_t RTCOVREN:1; - uint32_t RTCWKEN:1; - uint32_t APIWKEN:1; - uint32_t:7; - uint32_t WKCLKSEL:1; - } B; - } WKSE; /* Wakeup Source Enable Register */ - - uint32_t crp_reserved3[2]; - - union { - uint32_t R; - struct { - uint32_t Z1VEC:30; - uint32_t Z1RST:1; - uint32_t VLE:1; - } B; - } Z1VEC; /* Z1 Reset Vector Register */ - - union { - uint32_t R; - struct { - uint32_t Z0VEC:30; - uint32_t Z0RST:1; - uint32_t:1; - } B; - } Z0VEC; /* Z0 Reset Vector Register */ - - union { - uint32_t R; - struct { - uint32_t RECPTR:30; - uint32_t FASTREC:1; - uint32_t:1; - } B; - } RECPTR; /* Reset Recovery Pointer Register */ - - uint32_t crp_reserved4; - - union { - uint32_t R; - struct { - uint32_t SLEEPF:1; - uint32_t STOPF:1; - uint32_t:3; - uint32_t WKRLLOVRF:1; - uint32_t WKAPIF:1; - uint32_t WKRTCF:1; - uint32_t PWKSCRF:8; - uint32_t SLEEP:1; - uint32_t STOP:1; - uint32_t:1; - uint32_t PKREL:1; - uint32_t SLP12EN:1; - uint32_t RAMSEL:3; - uint32_t PWKSRIE:8; - } B; - } PSCR; /* Power Status and Control Register */ - - uint32_t crp_reserved5[3]; - - union { - uint32_t R; - struct { - uint32_t LVI5IE:1; - uint32_t LVI5HIE:1; - uint32_t LVI5F:1; - uint32_t LVI5HF:1; - uint32_t LVI5LOCK:1; - uint32_t LVI5RE:1; - uint32_t:9; - uint32_t BYPDIS:1; - uint32_t:16; - } B; - } SOCSC; /* LVI Status and Control Register */ - - }; -/****************************************************************************/ -/* MODULE : DMAMUX */ -/****************************************************************************/ - struct DMAMUX_tag { - union { - uint8_t R; - struct { - uint8_t ENBL:1; - uint8_t TRIG:1; - uint8_t SOURCE:6; - } B; - } CHCONFIG[16]; /* DMA Channel Configuration Register */ - - }; -/****************************************************************************/ -/* MODULE : DSPI */ -/****************************************************************************/ - struct DSPI_tag { - union DSPI_MCR_tag { - uint32_t R; - struct { - uint32_t MSTR:1; - uint32_t CONT_SCKE:1; - uint32_t DCONF:2; - uint32_t FRZ:1; - uint32_t MTFE:1; - uint32_t PCSSE:1; - uint32_t ROOE:1; - uint32_t:2; - uint32_t PCSIS5:1; - uint32_t PCSIS4:1; - uint32_t PCSIS3:1; - uint32_t PCSIS2:1; - uint32_t PCSIS1:1; - uint32_t PCSIS0:1; - uint32_t:1; - uint32_t MDIS:1; - uint32_t DIS_TXF:1; - uint32_t DIS_RXF:1; - uint32_t CLR_TXF:1; - uint32_t CLR_RXF:1; - uint32_t SMPL_PT:2; - uint32_t:7; - uint32_t HALT:1; - } B; - } MCR; /* Module Configuration Register */ - - uint32_t dspi_reserved1; - - union { - uint32_t R; - struct { - uint32_t SPI_TCNT:16; - uint32_t:16; - } B; - } TCR; - - union DSPI_CTAR_tag { - uint32_t R; - struct { - uint32_t DBR:1; - uint32_t FMSZ:4; - uint32_t CPOL:1; - uint32_t CPHA:1; - uint32_t LSBFE:1; - uint32_t PCSSCK:2; - uint32_t PASC:2; - uint32_t PDT:2; - uint32_t PBR:2; - uint32_t CSSCK:4; - uint32_t ASC:4; - uint32_t DT:4; - uint32_t BR:4; - } B; - } CTAR[8]; /* Clock and Transfer Attributes Registers */ - - union DSPI_SR_tag { - uint32_t R; - struct { - uint32_t TCF:1; - uint32_t TXRXS:1; - uint32_t:1; - uint32_t EOQF:1; - uint32_t TFUF:1; - uint32_t:1; - uint32_t TFFF:1; - uint32_t:5; - uint32_t RFOF:1; - uint32_t:1; - uint32_t RFDF:1; - uint32_t:1; - uint32_t TXCTR:4; - uint32_t TXNXTPTR:4; - uint32_t RXCTR:4; - uint32_t POPNXTPTR:4; - } B; - } SR; /* Status Register */ - - union DSPI_RSER_tag { - uint32_t R; - struct { - uint32_t TCF_RE:1; - uint32_t:2; - uint32_t EOQFRE:1; - uint32_t TFUFRE:1; - uint32_t:1; - uint32_t TFFFRE:1; - uint32_t TFFFDIRS:1; - uint32_t:4; - uint32_t RFOFRE:1; - uint32_t:1; - uint32_t RFDFRE:1; - uint32_t RFDFDIRS:1; - uint32_t:16; - } B; - } RSER; /* DMA/Interrupt Request Select and Enable Register */ - - union DSPI_PUSHR_tag { - uint32_t R; - struct { - uint32_t CONT:1; - uint32_t CTAS:3; - uint32_t EOQ:1; - uint32_t CTCNT:1; - uint32_t:4; - uint32_t PCS5:1; - uint32_t PCS4:1; - uint32_t PCS3:1; - uint32_t PCS2:1; - uint32_t PCS1:1; - uint32_t PCS0:1; - uint32_t TXDATA:16; - } B; - } PUSHR; /* PUSH TX FIFO Register */ - - union DSPI_POPR_tag { - uint32_t R; - struct { - uint32_t:16; - uint32_t RXDATA:16; - } B; - } POPR; /* POP RX FIFO Register */ - - union { - uint32_t R; - struct { - uint32_t TXCMD:16; - uint32_t TXDATA:16; - } B; - } TXFR[4]; /* Transmit FIFO Registers */ - - uint32_t DSPI_reserved_txf[12]; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t RXDATA:16; - } B; - } RXFR[4]; /* Transmit FIFO Registers */ - - uint32_t DSPI_reserved_rxf[12]; - - union { - uint32_t R; - struct { - uint32_t:12; - uint32_t TXSS:1; - uint32_t:2; - uint32_t CID:1; - uint32_t DCONT:1; - uint32_t DSICTAS:3; - uint32_t:6; - uint32_t DPCS5:1; - uint32_t DPCS4:1; - uint32_t DPCS3:1; - uint32_t DPCS2:1; - uint32_t DPCS1:1; - uint32_t DPCS0:1; - } B; - } DSICR; /* DSI Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t SER_DATA:16; - } B; - } SDR; /* DSI Serialization Data Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t ASER_DATA:16; - } B; - } ASDR; /* DSI Alternate Serialization Data Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t COMP_DATA:16; - } B; - } COMPR; /* DSI Transmit Comparison Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t DESER_DATA:16; - } B; - } DDR; /* DSI deserialization Data Register */ - - }; -/****************************************************************************/ -/* MODULE : External Bus Interface (EBI) */ -/****************************************************************************/ - -/* CS_tag instantiated within EBI_tag */ - struct EBI_CS_tag { - union { /* Base Register Bank */ - uint32_t R; - struct { - uint32_t BA:17; - uint32_t:3; - uint32_t PS:1; - uint32_t:3; - uint32_t AD_MUX:1; - uint32_t BL:1; - uint32_t WEBS:1; - uint32_t TBDIP:1; - uint32_t:1; - uint32_t SETA:1; - uint32_t BI:1; - uint32_t V:1; - } B; - } BR; - - union { /* Option Register Bank */ - uint32_t R; - struct { - uint32_t AM:17; - uint32_t:7; - uint32_t SCY:4; - uint32_t:1; - uint32_t BSCY:2; - uint32_t:1; - } B; - } OR; - }; - - struct EBI_CAL_CS_tag { - uint32_t ebi_cal_cs_reserved [2]; - }; - - struct EBI_tag { - union EBI_MCR_tag { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t ACGE:1; - uint32_t EXTM:1; - uint32_t EARB:1; - uint32_t:6; - uint32_t MDIS:1; - uint32_t:3; - uint32_t D16_31:1; - uint32_t AD_MUX:1; - uint32_t DBM:1; - } B; - } MCR; - - uint32_t EBI_reserved1; - - union { /* Transfer Error Status Register */ - uint32_t R; - struct { - uint32_t:30; - uint32_t TEAF:1; - uint32_t BMTF:1; - } B; - } TESR; - - union { /* Bus Monitor Control Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t BMT:8; - uint32_t BME:1; - uint32_t:7; - } B; - } BMCR; - - /* Roll in 3x CS registers */ - struct EBI_CS_tag CS[4]; - - uint32_t EBI_reserved2[4]; - - struct EBI_CAL_CS_tag CAL_CS[4]; - }; -/****************************************************************************/ -/* MODULE : EMIOS */ -/****************************************************************************/ - struct EMIOS_tag { - union EMIOS_MCR_tag { - uint32_t R; - struct { - uint32_t:1; - uint32_t MDIS:1; - uint32_t FRZ:1; - uint32_t GTBE:1; - uint32_t:1; - uint32_t GPREN:1; - uint32_t:10; - uint32_t GPRE:8; - uint32_t:8; - } B; - } MCR; /* Module Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t:8; - uint32_t F23:1; - uint32_t F22:1; - uint32_t F21:1; - uint32_t F20:1; - uint32_t F19:1; - uint32_t F18:1; - uint32_t F17:1; - uint32_t F16:1; - uint32_t F15:1; - uint32_t F14:1; - uint32_t F13:1; - uint32_t F12:1; - uint32_t F11:1; - uint32_t F10:1; - uint32_t F9:1; - uint32_t F8:1; - uint32_t F7:1; - uint32_t F6:1; - uint32_t F5:1; - uint32_t F4:1; - uint32_t F3:1; - uint32_t F2:1; - uint32_t F1:1; - uint32_t F0:1; - } B; - } GFG; /* Global FLAG Register */ - - union { - uint32_t R; - struct { - uint32_t:8; - uint32_t OU23:1; - uint32_t OU22:1; - uint32_t OU21:1; - uint32_t OU20:1; - uint32_t OU19:1; - uint32_t OU18:1; - uint32_t OU17:1; - uint32_t OU16:1; - uint32_t OU15:1; - uint32_t OU14:1; - uint32_t OU13:1; - uint32_t OU12:1; - uint32_t OU11:1; - uint32_t OU10:1; - uint32_t OU9:1; - uint32_t OU8:1; - uint32_t OU7:1; - uint32_t OU6:1; - uint32_t OU5:1; - uint32_t OU4:1; - uint32_t OU3:1; - uint32_t OU2:1; - uint32_t OU1:1; - uint32_t OU0:1; - } B; - } OUDR; /* Output Update Disable Register */ - - union { - uint32_t R; - struct { - uint32_t:8; - uint32_t UC23:1; - uint32_t UC22:1; - uint32_t UC21:1; - uint32_t UC20:1; - uint32_t UC19:1; - uint32_t UC18:1; - uint32_t UC17:1; - uint32_t UC16:1; - uint32_t UC15:1; - uint32_t UC14:1; - uint32_t UC13:1; - uint32_t UC12:1; - uint32_t UC11:1; - uint32_t UC10:1; - uint32_t UC9:1; - uint32_t UC8:1; - uint32_t UC7:1; - uint32_t UC6:1; - uint32_t UC5:1; - uint32_t UC4:1; - uint32_t UC3:1; - uint32_t UC2:1; - uint32_t UC1:1; - uint32_t UC0:1; - } B; - } UCDIS; /* Disable Channel Register */ - - uint32_t emios_reserved1[4]; - - struct EMIOS_CH_tag { - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t A:16; /* Channel A Data Register */ - } B; - } CADR; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t B:16; /* Channel B Data Register */ - } B; - } CBDR; - - union { - uint32_t R; /* Channel Counter Register */ - struct { - uint32_t:16; - uint32_t C:16; /* Channel C Data Register */ - } B; - } CCNTR; - - union EMIOS_CCR_tag { - uint32_t R; - struct { - uint32_t FREN:1; - uint32_t ODIS:1; - uint32_t ODISSL:2; - uint32_t UCPRE:2; - uint32_t UCPREN:1; - uint32_t DMA:1; - uint32_t:1; - uint32_t IF:4; - uint32_t FCK:1; - uint32_t FEN:1; - uint32_t:3; - uint32_t FORCMA:1; - uint32_t FORCMB:1; - uint32_t:1; - uint32_t BSL:2; - uint32_t EDSEL:1; - uint32_t EDPOL:1; - uint32_t MODE:7; - } B; - } CCR; /* Channel Control Register */ - - union EMIOS_CSR_tag { - uint32_t R; - struct { - uint32_t OVR:1; - uint32_t:15; - uint32_t OVFL:1; - uint32_t:12; - uint32_t UCIN:1; - uint32_t UCOUT:1; - uint32_t FLAG:1; - } B; - } CSR; /* Channel Status Register */ - - union { - uint32_t R; /* Alternate Channel A Data Register */ - } ALTA; - - uint32_t emios_channel_reserved[2]; - - } CH[24]; - - }; -/****************************************************************************/ -/* MODULE : EQADC */ -/****************************************************************************/ - struct EQADC_tag { - union { - uint32_t R; - struct { - uint32_t:30; - uint32_t DBG:2; - } B; - } MCR; /* Module Configuration Register */ - - uint32_t eqadc_reserved0; - - union { - uint32_t R; - struct { - uint32_t:6; - uint32_t NMF:26; - } B; - } NMSFR; /* Null Message Send Format Register */ - - union { - uint32_t R; - struct { - uint32_t:28; - uint32_t DFL:4; - } B; - } ETDFR; /* External Trigger Digital Filter Register */ - - union { - uint32_t R; - struct { - uint32_t CF_PUSH:32; - } B; - } CFPR[6]; /* CFIFO Push Registers */ - - uint32_t eqadc_reserved1; - - uint32_t eqadc_reserved2; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t RF_POP:16; - } B; - } RFPR[6]; /* Result FIFO Pop Registers */ - - uint32_t eqadc_reserved3; - - uint32_t eqadc_reserved4; - - union { - uint16_t R; - struct { - uint16_t:5; - uint16_t SSE:1; - uint16_t CFINV:1; - uint16_t:1; - uint16_t MODE:4; - uint16_t:4; - } B; - } CFCR[6]; /* CFIFO Control Registers */ - - uint32_t eqadc_reserved5; - - union { - uint16_t R; - struct { - uint16_t NCIE:1; - uint16_t TORIE:1; - uint16_t PIE:1; - uint16_t EOQIE:1; - uint16_t CFUIE:1; - uint16_t:1; - uint16_t CFFE:1; - uint16_t CFFS:1; - uint16_t:4; - uint16_t RFOIE:1; - uint16_t:1; - uint16_t RFDE:1; - uint16_t RFDS:1; - } B; - } IDCR[6]; /* Interrupt and DMA Control Registers */ - - uint32_t eqadc_reserved6; - - union { - uint32_t R; - struct { - uint32_t NCF:1; - uint32_t TORF:1; - uint32_t PF:1; - uint32_t EOQF:1; - uint32_t CFUF:1; - uint32_t SSS:1; - uint32_t CFFF:1; - uint32_t:5; - uint32_t RFOF:1; - uint32_t:1; - uint32_t RFDF:1; - uint32_t:1; - uint32_t CFCTR:4; - uint32_t TNXTPTR:4; - uint32_t RFCTR:4; - uint32_t POPNXTPTR:4; - } B; - } FISR[6]; /* FIFO and Interrupt Status Registers */ - - uint32_t eqadc_reserved7; - - uint32_t eqadc_reserved8; - - union { - uint16_t R; - struct { - uint16_t:5; - uint16_t TC_CF:11; - } B; - } CFTCR[6]; /* CFIFO Transfer Counter Registers */ - - uint32_t eqadc_reserved9; - - union { - uint32_t R; - struct { - uint32_t CFS0_T0:2; - uint32_t CFS1_T0:2; - uint32_t CFS2_T0:2; - uint32_t CFS3_T0:2; - uint32_t CFS4_T0:2; - uint32_t CFS5_T0:2; - uint32_t:5; - uint32_t LCFT0:4; - uint32_t TC_LCFT0:11; - } B; - } CFSSR0; /* CFIFO Status Register 0 */ - - uint32_t eqadc_reserved10[2]; - - union { - uint32_t R; - struct { - uint32_t CFS0:2; - uint32_t CFS1:2; - uint32_t CFS2:2; - uint32_t CFS3:2; - uint32_t CFS4:2; - uint32_t CFS5:2; - uint32_t:20; - } B; - } CFSR; - - uint32_t eqadc_reserved11[20]; - - struct { - union { - uint32_t R; - struct { - uint32_t:32; - } B; - } R[4]; - - uint32_t eqadc_reserved12[12]; - - } CF[6]; - - uint32_t eqadc_reserved13[32]; - - struct { - union { - uint32_t R; - struct { - uint32_t:32; - } B; - } R[4]; - - uint32_t eqadc_reserved14[12]; - - } RF[6]; - - }; -/****************************************************************************/ -/* MODULE : eSCI */ -/****************************************************************************/ - struct ESCI_tag { - union ESCI_CR1_tag { - uint32_t R; - struct { - uint32_t:3; - uint32_t SBR:13; - uint32_t LOOPS:1; - uint32_t:1; - uint32_t RSRC:1; - uint32_t M:1; - uint32_t WAKE:1; - uint32_t ILT:1; - uint32_t PE:1; - uint32_t PT:1; - uint32_t TIE:1; - uint32_t TCIE:1; - uint32_t RIE:1; - uint32_t ILIE:1; - uint32_t TE:1; - uint32_t RE:1; - uint32_t RWU:1; - uint32_t SBK:1; - } B; - } CR1; /* Control Register 1 */ - - union ESCI_CR2_tag { - uint16_t R; - struct { - uint16_t MDIS:1; - uint16_t FBR:1; - uint16_t BSTP:1; - uint16_t IEBERR:1; - uint16_t RXDMA:1; - uint16_t TXDMA:1; - uint16_t BRK13:1; - uint16_t TXDIR:1; - uint16_t BESM13:1; - uint16_t SBSTP:1; - uint16_t:1; - uint16_t PMSK:1; - uint16_t ORIE:1; - uint16_t NFIE:1; - uint16_t FEIE:1; - uint16_t PFIE:1; - } B; - } CR2; /* Control Register 2 */ - - union ESCI_DR_tag { - uint16_t R; - struct { - uint16_t R8:1; - uint16_t T8:1; - uint16_t:6; - uint8_t D; - } B; - } DR; /* Data Register */ - - union ESCI_SR_tag { - uint32_t R; - struct { - uint32_t TDRE:1; - uint32_t TC:1; - uint32_t RDRF:1; - uint32_t IDLE:1; - uint32_t OR:1; - uint32_t NF:1; - uint32_t FE:1; - uint32_t PF:1; - uint32_t:3; - uint32_t BERR:1; - uint32_t:3; - uint32_t RAF:1; - uint32_t RXRDY:1; - uint32_t TXRDY:1; - uint32_t LWAKE:1; - uint32_t STO:1; - uint32_t PBERR:1; - uint32_t CERR:1; - uint32_t CKERR:1; - uint32_t FRC:1; - uint32_t:6; - uint32_t UREQ:1; - uint32_t OVFL:1; - } B; - } SR; /* Status Register */ - - union { - uint32_t R; - struct { - uint32_t LRES:1; - uint32_t WU:1; - uint32_t WUD0:1; - uint32_t WUD1:1; - uint32_t LDBG:1; - uint32_t DSF:1; - uint32_t PRTY:1; - uint32_t LIN:1; - uint32_t RXIE:1; - uint32_t TXIE:1; - uint32_t WUIE:1; - uint32_t STIE:1; - uint32_t PBIE:1; - uint32_t CIE:1; - uint32_t CKIE:1; - uint32_t FCIE:1; - uint32_t:6; - uint32_t UQIE:1; - uint32_t OFIE:1; - uint32_t:8; - } B; - } LCR; /* LIN Control Register */ - - union { - uint32_t R; - } LTR; /* LIN Transmit Register */ - - union { - uint32_t R; - } LRR; /* LIN Recieve Register */ - - union { - uint32_t R; - } LPR; /* LIN CRC Polynom Register */ - - }; -/****************************************************************************/ -/* MODULE : FLASH */ -/****************************************************************************/ - struct FLASH_tag { - union { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t:3; - uint32_t SFS:1; - uint32_t SIZE:4; - uint32_t:1; - uint32_t LAS:3; - uint32_t:3; - uint32_t MAS:1; - uint32_t EER:1; - uint32_t RWE:1; - uint32_t BBEPE:1; - uint32_t EPE:1; - uint32_t PEAS:1; - uint32_t DONE:1; - uint32_t PEG:1; - uint32_t:1; - uint32_t PRD:1; - uint32_t STOP:1; - uint32_t:1; - uint32_t PGM:1; - uint32_t PSUS:1; - uint32_t ERS:1; - uint32_t ESUS:1; - uint32_t EHV:1; - } B; - } MCR; - - union LMLR_tag { /* Low/Mid Address Space Block Locking Register */ - uint32_t R; - struct { - uint32_t LME:1; - uint32_t:10; - uint32_t SLOCK:1; - uint32_t:2; - uint32_t MLOCK:2; - uint32_t:6; - uint32_t LLOCK:10; - } B; - } LMLR; /* Legacy naming - refer to LML in Reference Manual */ - - union HLR_tag { /* High Address Space Block Locking Register */ - uint32_t R; - struct { - uint32_t HBE:1; - uint32_t:23; - uint32_t HBLOCK:8; - } B; - } HLR; /* Legacy naming - refer to HBL in Reference Manual */ - - union SLMLR_tag { /* Secondary Low/Mid Block Locking Register */ - uint32_t R; - struct { - uint32_t SLE:1; - uint32_t:10; - uint32_t SSLOCK:1; - uint32_t:2; - uint32_t SMLOCK:2; - uint32_t:6; - uint32_t SLLOCK:10; - } B; - } SLMLR; /* Legacy naming - refer to SLL in Reference Manual */ - - union { /* Low/Mid Address Space Block Select Register */ - uint32_t R; - struct { - uint32_t:14; - uint32_t MSEL:2; - uint32_t:6; - uint32_t LSEL:10; - } B; - } LMSR; /* Legacy naming - refer to LMS in Reference Manual */ - - union { /* High Address Space Block Select Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t HBSEL:4; - } B; - } HSR; /* Legacy naming - refer to HBS in Reference Manual */ - - union { /* Address Register */ - uint32_t R; - struct { - uint32_t:10; - uint32_t ADDR:19; - uint32_t:3; - } B; - } AR; /* Legacy naming - refer to ADR in Reference Manual */ - - union { /* Platform Flash Configuration Register for Port 0 */ - uint32_t R; - struct { - uint32_t LBCFG:4; - uint32_t ARB:1; - uint32_t PRI:1; - uint32_t:5; - uint32_t M4PFE:1; - uint32_t M3PFE:1; - uint32_t M2PFE:1; - uint32_t M1PFE:1; - uint32_t M0PFE:1; - uint32_t APC:3; - uint32_t WWSC:2; - uint32_t RWSC:3; - uint32_t:1; - uint32_t DPFEN:1; - uint32_t:1; - uint32_t IPFEN:1; - uint32_t:1; - uint32_t PFLIM:2; - uint32_t BFEN:1; - } B; - } PFCRP0; - - union { /* Platform Flash Configuration Register for Port 1 */ - uint32_t R; - struct { - uint32_t LBCFG:4; - uint32_t:7; - uint32_t M4PFE:1; - uint32_t M3PFE:1; - uint32_t M2PFE:1; - uint32_t M1PFE:1; - uint32_t M0PFE:1; - uint32_t APC:3; - uint32_t WWSC:2; - uint32_t RWSC:3; - uint32_t:1; - uint32_t DPFEN:1; - uint32_t:1; - uint32_t IPFEN:1; - uint32_t:1; - uint32_t PFLIM:2; - uint32_t BFEN:1; - } B; - } PFCRP1; - - }; -/****************************************************************************/ -/* MODULE : FlexCAN */ -/****************************************************************************/ - struct FLEXCAN_tag { - union { - uint32_t R; - struct { - uint32_t MDIS:1; - uint32_t FRZ:1; - uint32_t FEN:1; - uint32_t HALT:1; - uint32_t NOTRDY:1; - uint32_t WAKMSK:1; - uint32_t SOFTRST:1; - uint32_t FRZACK:1; - uint32_t SUPV:1; - uint32_t SLFWAK:1; - uint32_t WRNEN:1; - uint32_t LPMACK:1; - uint32_t WAKSRC:1; - uint32_t DOZE:1; - uint32_t SRXDIS:1; - uint32_t BCC:1; - uint32_t:2; - uint32_t LPRIO_EN:1; - uint32_t AEN:1; - uint32_t:2; - uint32_t IDAM:2; - uint32_t:2; - uint32_t MAXMB:6; - } B; - } MCR; /* Module Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t PRESDIV:8; - uint32_t RJW:2; - uint32_t PSEG1:3; - uint32_t PSEG2:3; - uint32_t BOFFMSK:1; - uint32_t ERRMSK:1; - uint32_t CLKSRC:1; - uint32_t LPB:1; - uint32_t TWRNMSK:1; - uint32_t RWRNMSK:1; - uint32_t:2; - uint32_t SMP:1; - uint32_t BOFFREC:1; - uint32_t TSYN:1; - uint32_t LBUF:1; - uint32_t LOM:1; - uint32_t PROPSEG:3; - } B; - } CTRL; /* Control Register */ - - union { - uint32_t R; - } TIMER; /* Free Running Timer */ - - uint32_t FLEXCAN_reserved1; - - union { - uint32_t R; - struct { - uint32_t MI:32; - } B; - } RXGMASK; /* RX Global Mask */ - - union { - uint32_t R; - struct { - uint32_t MI:32; - } B; - } RX14MASK; /* RX 14 Mask */ - - union { - uint32_t R; - struct { - uint32_t MI:32; - } B; - } RX15MASK; /* RX 15 Mask */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t RXECNT:8; - uint32_t TXECNT:8; - } B; - } ECR; /* Error Counter Register */ - - union { - uint32_t R; - struct { - uint32_t:14; - uint32_t TWRNINT:1; - uint32_t RWRNINT:1; - uint32_t BIT1ERR:1; - uint32_t BIT0ERR:1; - uint32_t ACKERR:1; - uint32_t CRCERR:1; - uint32_t FRMERR:1; - uint32_t STFERR:1; - uint32_t TXWRN:1; - uint32_t RXWRN:1; - uint32_t IDLE:1; - uint32_t TXRX:1; - uint32_t FLTCONF:2; - uint32_t:1; - uint32_t BOFFINT:1; - uint32_t ERRINT:1; - uint32_t WAKINT:1; - } B; - } ESR; /* Error and Status Register */ - - union { - uint32_t R; - struct { - uint32_t BUF63M:1; - uint32_t BUF62M:1; - uint32_t BUF61M:1; - uint32_t BUF60M:1; - uint32_t BUF59M:1; - uint32_t BUF58M:1; - uint32_t BUF57M:1; - uint32_t BUF56M:1; - uint32_t BUF55M:1; - uint32_t BUF54M:1; - uint32_t BUF53M:1; - uint32_t BUF52M:1; - uint32_t BUF51M:1; - uint32_t BUF50M:1; - uint32_t BUF49M:1; - uint32_t BUF48M:1; - uint32_t BUF47M:1; - uint32_t BUF46M:1; - uint32_t BUF45M:1; - uint32_t BUF44M:1; - uint32_t BUF43M:1; - uint32_t BUF42M:1; - uint32_t BUF41M:1; - uint32_t BUF40M:1; - uint32_t BUF39M:1; - uint32_t BUF38M:1; - uint32_t BUF37M:1; - uint32_t BUF36M:1; - uint32_t BUF35M:1; - uint32_t BUF34M:1; - uint32_t BUF33M:1; - uint32_t BUF32M:1; - } B; - } IMASK2; /* Interruput Masks Register */ - - union { - uint32_t R; - struct { - uint32_t BUF31M:1; - uint32_t BUF30M:1; - uint32_t BUF29M:1; - uint32_t BUF28M:1; - uint32_t BUF27M:1; - uint32_t BUF26M:1; - uint32_t BUF25M:1; - uint32_t BUF24M:1; - uint32_t BUF23M:1; - uint32_t BUF22M:1; - uint32_t BUF21M:1; - uint32_t BUF20M:1; - uint32_t BUF19M:1; - uint32_t BUF18M:1; - uint32_t BUF17M:1; - uint32_t BUF16M:1; - uint32_t BUF15M:1; - uint32_t BUF14M:1; - uint32_t BUF13M:1; - uint32_t BUF12M:1; - uint32_t BUF11M:1; - uint32_t BUF10M:1; - uint32_t BUF09M:1; - uint32_t BUF08M:1; - uint32_t BUF07M:1; - uint32_t BUF06M:1; - uint32_t BUF05M:1; - uint32_t BUF04M:1; - uint32_t BUF03M:1; - uint32_t BUF02M:1; - uint32_t BUF01M:1; - uint32_t BUF00M:1; - } B; - } IMASK1; /* Interruput Masks Register */ - - union { - uint32_t R; - struct { - uint32_t BUF63I:1; - uint32_t BUF62I:1; - uint32_t BUF61I:1; - uint32_t BUF60I:1; - uint32_t BUF59I:1; - uint32_t BUF58I:1; - uint32_t BUF57I:1; - uint32_t BUF56I:1; - uint32_t BUF55I:1; - uint32_t BUF54I:1; - uint32_t BUF53I:1; - uint32_t BUF52I:1; - uint32_t BUF51I:1; - uint32_t BUF50I:1; - uint32_t BUF49I:1; - uint32_t BUF48I:1; - uint32_t BUF47I:1; - uint32_t BUF46I:1; - uint32_t BUF45I:1; - uint32_t BUF44I:1; - uint32_t BUF43I:1; - uint32_t BUF42I:1; - uint32_t BUF41I:1; - uint32_t BUF40I:1; - uint32_t BUF39I:1; - uint32_t BUF38I:1; - uint32_t BUF37I:1; - uint32_t BUF36I:1; - uint32_t BUF35I:1; - uint32_t BUF34I:1; - uint32_t BUF33I:1; - uint32_t BUF32I:1; - } B; - } IFLAG2; /* Interruput Flag Register */ - - union { - uint32_t R; - struct { - uint32_t BUF31I:1; - uint32_t BUF30I:1; - uint32_t BUF29I:1; - uint32_t BUF28I:1; - uint32_t BUF27I:1; - uint32_t BUF26I:1; - uint32_t BUF25I:1; - uint32_t BUF24I:1; - uint32_t BUF23I:1; - uint32_t BUF22I:1; - uint32_t BUF21I:1; - uint32_t BUF20I:1; - uint32_t BUF19I:1; - uint32_t BUF18I:1; - uint32_t BUF17I:1; - uint32_t BUF16I:1; - uint32_t BUF15I:1; - uint32_t BUF14I:1; - uint32_t BUF13I:1; - uint32_t BUF12I:1; - uint32_t BUF11I:1; - uint32_t BUF10I:1; - uint32_t BUF09I:1; - uint32_t BUF08I:1; - uint32_t BUF07I:1; - uint32_t BUF06I:1; - uint32_t BUF05I:1; - uint32_t BUF04I:1; - uint32_t BUF03I:1; - uint32_t BUF02I:1; - uint32_t BUF01I:1; - uint32_t BUF00I:1; - } B; - } IFLAG1; /* Interruput Flag Register */ - - uint32_t FLEXCAN_reserved2[19]; - - struct canbuf_t { - union { - uint32_t R; - struct { - uint32_t:4; - uint32_t CODE:4; - uint32_t:1; - uint32_t SRR:1; - uint32_t IDE:1; - uint32_t RTR:1; - uint32_t LENGTH:4; - uint32_t TIMESTAMP:16; - } B; - } CS; - - union { - uint32_t R; - struct { - uint32_t PRIO:3; - uint32_t STD_ID:11; - uint32_t EXT_ID:18; - } B; - } ID; - - union { - uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ - uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ - uint32_t W[2]; /* Data buffer in words (32 bits) */ - uint32_t R[2]; /* Data buffer in words (32 bits) */ - } DATA; - - } BUF[64]; - - uint32_t FLEXCAN_reserved3[256]; - - union { - uint32_t R; - struct { - uint32_t MI:32; - } B; - } RXIMR[64]; /* RX Individual Mask Registers */ - - }; -/****************************************************************************/ -/* MODULE : FMPLL */ -/****************************************************************************/ - struct FMPLL_tag { - - uint32_t FMPLL_reserved0; - - union FMPLL_SYNSR_tag { /* Synthesiser Status Register */ - uint32_t R; - struct { - uint32_t:22; - uint32_t LOLF:1; - uint32_t LOC:1; - uint32_t MODE:1; - uint32_t PLLSEL:1; - uint32_t PLLREF:1; - uint32_t LOCKS:1; - uint32_t LOCK:1; - uint32_t LOCF:1; - uint32_t CALDONE:1; - uint32_t CALPASS:1; - } B; - } SYNSR; - - union FMPLL_ESYNCR1_tag { - uint32_t R; - struct { - uint32_t:1; - uint32_t CLKCFG:3; - uint32_t:8; - uint32_t EPREDIV:4; - uint32_t:8; - uint32_t EMFD:8; - } B; - } ESYNCR1; - - union FMPLL_ESYNCR2_tag { - uint32_t R; - struct { - uint32_t:8; - uint32_t LOCEN:1; - uint32_t LOLRE:1; - uint32_t LOCRE:1; - uint32_t LOLIRQ:1; - uint32_t LOCIRQ:1; - uint32_t:1; - uint32_t ERATE:2; - uint32_t:5; - uint32_t EDEPTH:3; - uint32_t:2; - uint32_t ERFD:6; - } B; - } ESYNCR2; - - }; -/****************************************************************************/ -/* MODULE : i2c */ -/****************************************************************************/ - struct I2C_tag { - union { - uint8_t R; - struct { - uint8_t AD:7; - uint8_t:1; - } B; - } IBAD; /* Module Bus Address Register */ - - union { - uint8_t R; - struct { - uint8_t MULT:2; - uint8_t ICR:6; - } B; - } IBFD; /* Module Bus Frequency Register */ - - union { - uint8_t R; - struct { - uint8_t MDIS:1; - uint8_t IBIE:1; - uint8_t MS:1; - uint8_t TX:1; - uint8_t NOACK:1; - uint8_t RSTA:1; - uint8_t DMAEN:1; - uint8_t:1; - } B; - } IBCR; /* Module Bus Control Register */ - - union { - uint8_t R; - struct { - uint8_t TCF:1; - uint8_t IAAS:1; - uint8_t IBB:1; - uint8_t IBAL:1; - uint8_t:1; - uint8_t SRW:1; - uint8_t IBIF:1; - uint8_t RXAK:1; - } B; - } IBSR; /* Module Status Register */ - - union { - uint8_t R; - struct { - uint8_t DATA:8; - } B; - } IBDR; /* Module Data Register */ - - union { - uint8_t R; - struct { - uint8_t BIIE:1; - uint8_t:7; - } B; - } IBIC; /* Module Interrupt Configuration Register */ - - }; -/****************************************************************************/ -/* MODULE : INTC */ -/****************************************************************************/ - struct INTC_tag { - union { - uint32_t R; - struct { - uint32_t:18; - uint32_t VTES_PRC1:1; - uint32_t:4; - uint32_t HVEN_PRC1:1; - uint32_t:2; - uint32_t VTES:1; - uint32_t:4; - uint32_t HVEN:1; - } B; - } MCR; /* Module Configuration Register */ - - int32_t INTC_reserved1; - - union { - uint32_t R; - struct { - uint32_t:28; - uint32_t PRI:4; - } B; - } CPR; /* Processor 0 Current Priority Register */ - - union { - uint32_t R; - struct { - uint32_t:28; - uint32_t PRI:4; - } B; - } CPR_PRC1; /* Processor 1 Current Priority Register */ - - union { - uint32_t R; - struct { - uint32_t VTBA:21; - uint32_t INTVEC:9; - uint32_t:2; - } B; - } IACKR; /* Processor 0 Interrupt Acknowledge Register */ - - union { - uint32_t R; - struct { - uint32_t VTBA_PRC1:21; - uint32_t INTVEC_PRC1:9; - uint32_t:2; - } B; - } IACKR_PRC1; /* Processor 1 Interrupt Acknowledge Register */ - - union { - uint32_t R; - struct { - uint32_t:32; - } B; - } EOIR; /* Processor 0 End of Interrupt Register */ - - union { - uint32_t R; - struct { - uint32_t:32; - } B; - } EOIR_PRC1; /* Processor 1 End of Interrupt Register */ - - union { - uint8_t R; - struct { - uint8_t:6; - uint8_t SET:1; - uint8_t CLR:1; - } B; - } SSCIR[8]; /* Software Set/Clear Interruput Register */ - - uint32_t intc_reserved2[6]; - - union { - uint8_t R; - struct { - uint8_t PRC_SEL:2; - uint8_t:2; - uint8_t PRI:4; - } B; - } PSR[294]; /* Software Set/Clear Interrupt Register */ - - }; -/****************************************************************************/ -/* MODULE : MCM */ -/****************************************************************************/ - struct MCM_tag { - - uint32_t mcm_reserved1[5]; - - uint16_t mcm_reserved2; - - union { - uint16_t R; - struct { - uint16_t RO:1; - uint16_t:6; - uint16_t SWRWH:1; - uint16_t SWE:1; - uint16_t SWRI:2; - uint16_t SWT:5; - } B; - } SWTCR; /* Software Watchdog Timer Control */ - - uint8_t mcm_reserved3[3]; - - union { - uint8_t R; - } SWTSR; /* SWT Service Register */ - - uint8_t mcm_reserved4[3]; - - union { - uint8_t R; - struct { - uint8_t:7; - uint8_t SWTIC:1; - } B; - } SWTIR; /* SWT Interrupt Register */ - - uint32_t mcm_reserved5[1]; - - union { - uint32_t R; - struct { - uint32_t PRI:1; - uint32_t:31; - } B; - } MUDCR; /* Misc. User Defined Control Register */ - - uint32_t mcm_reserved6[6]; - uint8_t mcm_reserved7[3]; - - union { - uint8_t R; - struct { - uint8_t:6; - uint8_t ERNCR:1; - uint8_t EFNCR:1; - } B; - } ECR; /* ECC Configuration Register */ - - uint8_t mcm_reserved8[3]; - - union { - uint8_t R; - struct { - uint8_t:6; - uint8_t RNCE:1; - uint8_t FNCE:1; - } B; - } ESR; /* ECC Status Register */ - - uint16_t mcm_reserved9; - - union { - uint16_t R; - struct { - uint16_t:6; - uint16_t FRCNCI:1; - uint16_t FR1NCI:1; - uint16_t:1; - uint16_t ERRBIT:7; - } B; - } EEGR; /* ECC Error Generation Register */ - - uint32_t mcm_reserved10; - - union { - uint32_t R; - } FEAR; /* Flash ECC Address Register */ - - uint16_t mcm_reserved11; - - union { - uint8_t R; - struct { - uint8_t:4; - uint8_t FEMR:4; - } B; - } FEMR; /* Flash ECC Master Register */ - - union { - uint8_t R; - struct { - uint8_t WRITE:1; - uint8_t SIZE:3; - uint8_t PROTECTION:4; - } B; - } FEAT; /* Flash ECC Attributes Register */ - - union { - uint32_t R; - } FEDRH; /* Flash ECC Data High Register */ - - union { - uint32_t R; - } FEDRL; /* Flash ECC Data Low Register */ - - union { - uint32_t R; - struct { - uint32_t REAR:32; - } B; - } REAR; /* RAM ECC Address */ - - uint16_t mcm_reserved12; - - union { - uint8_t R; - struct { - uint8_t:4; - uint8_t REMR:4; - } B; - } REMR; /* RAM ECC Master */ - - union { - uint8_t R; - struct { - uint8_t WRITE:1; - uint8_t SIZE:3; - uint8_t PROTECTION:4; - } B; - } REAT; /* RAM ECC Attributes Register */ - - union { - uint32_t R; - } REDRH; /* RAM ECC Data High Register */ - - union { - uint32_t R; - } REDRL; /* RAMECC Data Low Register */ - - }; -/****************************************************************************/ -/* MODULE : MPU */ -/****************************************************************************/ - struct MPU_tag { - union { - uint32_t R; - struct { - uint32_t SPERR:8; - uint32_t:4; - uint32_t HRL:4; - uint32_t NSP:4; - uint32_t NGRD:4; - uint32_t:7; - uint32_t VLD:1; - } B; - } CESR; /* Module Control/Error Status Register */ - - uint32_t mpu_reserved1[3]; - - union { - uint32_t R; - struct { - uint32_t EADDR:32; - } B; - } EAR0; - - union { - uint32_t R; - struct { - uint32_t EACD:16; - uint32_t EPID:8; - uint32_t EMN:4; - uint32_t EATTR:3; - uint32_t ERW:1; - } B; - } EDR0; - - union { - uint32_t R; - struct { - uint32_t EADDR:32; - } B; - } EAR1; - - union { - uint32_t R; - struct { - uint32_t EACD:16; - uint32_t EPID:8; - uint32_t EMN:4; - uint32_t EATTR:3; - uint32_t ERW:1; - } B; - } EDR1; - - union { - uint32_t R; - struct { - uint32_t EADDR:32; - } B; - } EAR2; - - union { - uint32_t R; - struct { - uint32_t EACD:16; - uint32_t EPID:8; - uint32_t EMN:4; - uint32_t EATTR:3; - uint32_t ERW:1; - } B; - } EDR2; - - uint32_t mpu_reserved2[246]; - - struct { - union { - uint32_t R; - struct { - uint32_t SRTADDR:27; - uint32_t:5; - } B; - } WORD0; /* Region Descriptor n Word 0 */ - - union { - uint32_t R; - struct { - uint32_t ENDADDR:27; - uint32_t:5; - } B; - } WORD1; /* Region Descriptor n Word 1 */ - - union { - uint32_t R; - struct { - uint32_t:6; - uint32_t M4RE0:1; - uint32_t M4WE:1; - uint32_t M3PE:1; - uint32_t M3SM:2; - uint32_t M3UM:3; - uint32_t M2PE:1; - uint32_t M2SM:2; - uint32_t M2UM:3; - uint32_t M1PE:1; - uint32_t M1SM:2; - uint32_t M1UM:3; - uint32_t M0PE:1; - uint32_t M0SM:2; - uint32_t M0UM:3; - } B; - } WORD2; /* Region Descriptor n Word 2 */ - - union { - uint32_t R; - struct { - uint32_t PID:8; - uint32_t PIDMASK:8; - uint32_t:15; - uint32_t VLD:1; - } B; - } WORD3; /* Region Descriptor n Word 3 */ - - } RGD[16]; - - uint32_t mpu_reserved3[192]; - - union { - uint32_t R; - struct { - uint32_t:6; - uint32_t M4RE:1; - uint32_t M4WE:1; - uint32_t M3PE:1; - uint32_t M3SM:2; - uint32_t M3UM:3; - uint32_t M2PE:1; - uint32_t M2SM:2; - uint32_t M2UM:3; - uint32_t M1PE:1; - uint32_t M1SM:2; - uint32_t M1UM:3; - uint32_t M0PE:1; - uint32_t M0SM:2; - uint32_t M0UM:3; - } B; - } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */ - }; -/****************************************************************************/ -/* MODULE : pit */ -/****************************************************************************/ - struct PIT_tag { - union { - uint32_t R; - struct { - uint32_t TSV:32; - } B; - } TLVAL[9]; - - uint32_t pit_reserved1[23]; - - union { - uint32_t R; - struct { - uint32_t TVL:32; - } B; - } TVAL[9]; - - uint32_t pit_reserved2[23]; - - union { - uint32_t R; - struct { - uint32_t:23; - uint32_t TIF8:1; - uint32_t TIF7:1; - uint32_t TIF6:1; - uint32_t TIF5:1; - uint32_t TIF4:1; - uint32_t TIF3:1; - uint32_t TIF2:1; - uint32_t TIF1:1; - uint32_t RTIF:1; - } B; - } PITFLG; - - union { - uint32_t R; - struct { - uint32_t:23; - uint32_t TIE8:1; - uint32_t TIE7:1; - uint32_t TIE6:1; - uint32_t TIE5:1; - uint32_t TIE4:1; - uint32_t TIE3:1; - uint32_t TIE2:1; - uint32_t TIE1:1; - uint32_t RTIE:1; - } B; - } PITINTEN; - - union { - uint32_t R; - struct { - uint32_t:23; - uint32_t ISEL8:1; - uint32_t ISEL7:1; - uint32_t ISEL6:1; - uint32_t ISEL5:1; - uint32_t ISEL4:1; - uint32_t ISEL3:1; - uint32_t ISEL2:1; - uint32_t ISEL1:1; - uint32_t:1; - } B; - } PITINTSEL; - - union { - uint32_t R; - struct { - uint32_t:23; - uint32_t PEN8:1; - uint32_t PEN7:1; - uint32_t PEN6:1; - uint32_t PEN5:1; - uint32_t PEN4:1; - uint32_t PEN3:1; - uint32_t PEN2:1; - uint32_t PEN1:1; - uint32_t PEN0:1; - } B; - } PITEN; - - union { - uint32_t R; - struct { - uint32_t:7; - uint32_t MDIS:1; - uint32_t:24; - } B; - } PITCTRL; - - }; -/****************************************************************************/ -/* MODULE : sem4 */ -/****************************************************************************/ - struct SEMA4_tag { - union { - uint8_t R; - struct { - uint8_t:6; - uint8_t GTFSM:2; - } B; - } GATE[16]; /* Gate n Register */ - - uint32_t sema4_reserved1[12]; /* {0x40-0x10}/4 = 0x0C */ - - union { - uint16_t R; - struct { - uint16_t INE0:1; - uint16_t INE1:1; - uint16_t INE2:1; - uint16_t INE3:1; - uint16_t INE4:1; - uint16_t INE5:1; - uint16_t INE6:1; - uint16_t INE7:1; - uint16_t INE8:1; - uint16_t INE9:1; - uint16_t INE10:1; - uint16_t INE11:1; - uint16_t INE12:1; - uint16_t INE13:1; - uint16_t INE14:1; - uint16_t INE15:1; - } B; - } CP0INE; - - uint16_t sema4_reserved2[3]; /* {0x48-0x42}/2 = 0x03 */ - - union { - uint16_t R; - struct { - uint16_t INE0:1; - uint16_t INE1:1; - uint16_t INE2:1; - uint16_t INE3:1; - uint16_t INE4:1; - uint16_t INE5:1; - uint16_t INE6:1; - uint16_t INE7:1; - uint16_t INE8:1; - uint16_t INE9:1; - uint16_t INE10:1; - uint16_t INE11:1; - uint16_t INE12:1; - uint16_t INE13:1; - uint16_t INE14:1; - uint16_t INE15:1; - } B; - } CP1INE; - - uint16_t sema4_reserved3[27]; /* {0x80-0x4A}/2 = 0x1B */ - - union { - uint16_t R; - struct { - uint16_t GN0:1; - uint16_t GN1:1; - uint16_t GN2:1; - uint16_t GN3:1; - uint16_t GN4:1; - uint16_t GN5:1; - uint16_t GN6:1; - uint16_t GN7:1; - uint16_t GN8:1; - uint16_t GN9:1; - uint16_t GN10:1; - uint16_t GN11:1; - uint16_t GN12:1; - uint16_t GN13:1; - uint16_t GN14:1; - uint16_t GN15:1; - } B; - } CP0NTF; - - uint16_t sema4_reserved4[3]; /* {0x88-0x82}/2 = 0x03 */ - - union { - uint16_t R; - struct { - uint16_t GN0:1; - uint16_t GN1:1; - uint16_t GN2:1; - uint16_t GN3:1; - uint16_t GN4:1; - uint16_t GN5:1; - uint16_t GN6:1; - uint16_t GN7:1; - uint16_t GN8:1; - uint16_t GN9:1; - uint16_t GN10:1; - uint16_t GN11:1; - uint16_t GN12:1; - uint16_t GN13:1; - uint16_t GN14:1; - uint16_t GN15:1; - } B; - } CP1NTF; - - uint16_t sema4_reserved5[59]; /* {0x100-0x8A}/2 = 0x3B */ - - union { - uint16_t R; - struct { - uint16_t:2; - uint16_t RSTGSM:2; - uint16_t:1; - uint16_t RSTGMS:3; - uint16_t RSTGTN:8; - } B; - } RSTGT; - - uint16_t sema4_reserved6; - - union { - uint16_t R; - struct { - uint16_t:2; - uint16_t RSTNSM:2; - uint16_t:1; - uint16_t RSTNMS:3; - uint16_t RSTNTN:8; - } B; - } RSTNTF; - }; -/****************************************************************************/ -/* MODULE : SIU */ -/****************************************************************************/ - struct SIU_tag { - - int32_t SIU_reserved0; - - union { /* MCU ID Register */ - uint32_t R; - struct { - uint32_t PARTNUM:16; - uint32_t CSP:1; - uint32_t PKG:5; - uint32_t:2; - uint32_t MASKNUM_MAJOR:4; - uint32_t MASKNUM_MINOR:4; - } B; - } MIDR; - - int32_t SIU_reserved1; - - union { /* Reset Status Register */ - uint32_t R; - struct { - uint32_t PORS:1; - uint32_t ERS:1; - uint32_t LLRS:1; - uint32_t LCRS:1; - uint32_t WDRS:1; - uint32_t CRS:1; - uint32_t:8; - uint32_t SSRS:1; - uint32_t:15; - uint32_t BOOTCFG:1; - uint32_t:1; - } B; - } RSR; - - union { /* System Reset Control Register */ - uint32_t R; - struct { - uint32_t SSR:1; - uint32_t:15; - uint32_t CRE0:1; - uint32_t CRE1:1; - uint32_t:6; - uint32_t SSRL:1; - uint32_t:7; - } B; - } SRCR; - - union SIU_EISR_tag { /* External Interrupt Status Register */ - uint32_t R; - struct { - uint32_t NMI0:1; - uint32_t NMI1:1; - uint32_t:14; - uint32_t EIF15:1; - uint32_t EIF14:1; - uint32_t EIF13:1; - uint32_t EIF12:1; - uint32_t EIF11:1; - uint32_t EIF10:1; - uint32_t EIF9:1; - uint32_t EIF8:1; - uint32_t EIF7:1; - uint32_t EIF6:1; - uint32_t EIF5:1; - uint32_t EIF4:1; - uint32_t EIF3:1; - uint32_t EIF2:1; - uint32_t EIF1:1; - uint32_t EIF0:1; - } B; - } EISR; - - union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t EIRE15:1; - uint32_t EIRE14:1; - uint32_t EIRE13:1; - uint32_t EIRE12:1; - uint32_t EIRE11:1; - uint32_t EIRE10:1; - uint32_t EIRE9:1; - uint32_t EIRE8:1; - uint32_t EIRE7:1; - uint32_t EIRE6:1; - uint32_t EIRE5:1; - uint32_t EIRE4:1; - uint32_t EIRE3:1; - uint32_t EIRE2:1; - uint32_t EIRE1:1; - uint32_t EIRE0:1; - } B; - } DIRER; - - union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */ - uint32_t R; - struct { - uint32_t:27; - uint32_t DIRS4:1; - uint32_t DIRS3:1; - uint32_t DIRS2:1; - uint32_t DIRS1:1; - uint32_t:1; - } B; - } DIRSR; - - union { /* Overrun Status Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t OVF15:1; - uint32_t OVF14:1; - uint32_t OVF13:1; - uint32_t OVF12:1; - uint32_t OVF11:1; - uint32_t OVF10:1; - uint32_t OVF9:1; - uint32_t OVF8:1; - uint32_t OVF7:1; - uint32_t OVF6:1; - uint32_t OVF5:1; - uint32_t OVF4:1; - uint32_t OVF3:1; - uint32_t OVF2:1; - uint32_t OVF1:1; - uint32_t OVF0:1; - } B; - } OSR; - - union SIU_ORER_tag { /* Overrun Request Enable Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t ORE15:1; - uint32_t ORE14:1; - uint32_t ORE13:1; - uint32_t ORE12:1; - uint32_t ORE11:1; - uint32_t ORE10:1; - uint32_t ORE9:1; - uint32_t ORE8:1; - uint32_t ORE7:1; - uint32_t ORE6:1; - uint32_t ORE5:1; - uint32_t ORE4:1; - uint32_t ORE3:1; - uint32_t ORE2:1; - uint32_t ORE1:1; - uint32_t ORE0:1; - } B; - } ORER; - - union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */ - uint32_t R; - struct { - uint32_t NREE0:1; - uint32_t NREE1:1; - uint32_t:14; - uint32_t IREE15:1; - uint32_t IREE14:1; - uint32_t IREE13:1; - uint32_t IREE12:1; - uint32_t IREE11:1; - uint32_t IREE10:1; - uint32_t IREE9:1; - uint32_t IREE8:1; - uint32_t IREE7:1; - uint32_t IREE6:1; - uint32_t IREE5:1; - uint32_t IREE4:1; - uint32_t IREE3:1; - uint32_t IREE2:1; - uint32_t IREE1:1; - uint32_t IREE0:1; - } B; - } IREER; - - union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */ - uint32_t R; - struct { - uint32_t NFEE0:1; - uint32_t NFEE1:1; - uint32_t:14; - uint32_t IFEE15:1; - uint32_t IFEE14:1; - uint32_t IFEE13:1; - uint32_t IFEE12:1; - uint32_t IFEE11:1; - uint32_t IFEE10:1; - uint32_t IFEE9:1; - uint32_t IFEE8:1; - uint32_t IFEE7:1; - uint32_t IFEE6:1; - uint32_t IFEE5:1; - uint32_t IFEE4:1; - uint32_t IFEE3:1; - uint32_t IFEE2:1; - uint32_t IFEE1:1; - uint32_t IFEE0:1; - } B; - } IFEER; - - union SIU_IDFR_tag { /* External IRQ Digital Filter Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t DFL:4; - } B; - } IDFR; - - union { /* External IRQ Filtered Input Register */ - uint32_t R; - struct { - uint32_t FNMI0:1; - uint32_t FNMI1:1; - uint32_t:14; - uint32_t FI15:1; - uint32_t FI14:1; - uint32_t FI13:1; - uint32_t FI12:1; - uint32_t FI11:1; - uint32_t FI10:1; - uint32_t FI9:1; - uint32_t FI8:1; - uint32_t FI7:1; - uint32_t FI6:1; - uint32_t FI5:1; - uint32_t FI4:1; - uint32_t FI3:1; - uint32_t FI2:1; - uint32_t FI1:1; - uint32_t FI0:1; - } B; - } IFIR; - - int32_t SIU_reserved2[2]; - - union SIU_PCR_tag { /* Pad Configuration Registers */ - uint16_t R; - struct { - uint16_t:4; - uint16_t PA:2; - uint16_t OBE:1; - uint16_t IBE:1; - uint16_t:2; - uint16_t ODE:1; - uint16_t HYS:1; - uint16_t SRC:2; - uint16_t WPE:1; - uint16_t WPS:1; - } B; - } PCR[146]; - - int32_t SIU_reserved3[295]; - - union { /* GPIO Pin Data Output Registers */ - uint8_t R; - struct { - uint8_t:7; - uint8_t PDO:1; - } B; - } GPDO[146]; - - int32_t SIU_reserved4[91]; - - union { /* GPIO Pin Data Input Registers */ - uint8_t R; - struct { - uint8_t:7; - uint8_t PDI:1; - } B; - } GPDI[146]; - - int32_t SIU_reserved5[27]; - - union { /* IMUX Register */ - uint32_t R; - struct { - uint32_t TSEL3:2; - uint32_t TSEL2:2; - uint32_t TSEL1:2; - uint32_t TSEL0:2; - uint32_t:24; - } B; - } ISEL0; - - union { /* IMUX Register */ - uint32_t R; - struct { - uint32_t ESEL15:2; - uint32_t ESEL14:2; - uint32_t ESEL13:2; - uint32_t ESEL12:2; - uint32_t ESEL11:2; - uint32_t ESEL10:2; - uint32_t ESEL9:2; - uint32_t ESEL8:2; - uint32_t ESEL7:2; - uint32_t ESEL6:2; - uint32_t ESEL5:2; - uint32_t ESEL4:2; - uint32_t ESEL3:2; - uint32_t ESEL2:2; - uint32_t ESEL1:2; - uint32_t ESEL0:2; - } B; - } ISEL1; - - union { /* IMUX Register */ - uint32_t R; - struct { - uint32_t SELEMIOS15:2; - uint32_t SELEMIOS14:2; - uint32_t SELEMIOS13:2; - uint32_t SELEMIOS12:2; - uint32_t SELEMIOS11:2; - uint32_t SELEMIOS10:2; - uint32_t SELEMIOS9:2; - uint32_t SELEMIOS8:2; - uint32_t SELEMIOS7:2; - uint32_t SELEMIOS6:2; - uint32_t SELEMIOS5:2; - uint32_t SELEMIOS4:2; - uint32_t SELEMIOS3:2; - uint32_t SELEMIOS2:2; - uint32_t SELEMIOS1:2; - uint32_t SELEMIOS0:2; - } B; - } ISEL2; - - int32_t SIU_reserved6[29]; - - union { /* Chip Configuration Register Register */ - uint32_t R; - struct { - uint32_t:14; - uint32_t MATCH:1; - uint32_t DISNEX:1; - uint32_t:16; - } B; - } CCR; - - union { /* External Clock Configuration Register Register */ - uint32_t R; - struct { - uint32_t:30; - uint32_t EBDF:2; - } B; - } ECCR; - - union { /* Compare A High Register */ - uint32_t R; - } CMPAH; - - union { /* Compare A Low Register */ - uint32_t R; - } CMPAL; - - union { /* Compare B High Register */ - uint32_t R; - } CMPBH; - - union { /* Compare B Low Register */ - uint32_t R; - } CMPBL; - - int32_t SIU_reserved7[2]; - - union { /* System CLock Register */ - uint32_t R; - struct { - uint32_t SYSCLKSEL:2; - uint32_t SYSCLKDIV:2; - uint32_t SWTCLKSEL:1; - uint32_t:11; - uint32_t LPCLKDIV7:2; - uint32_t LPCLKDIV6:2; - uint32_t LPCLKDIV5:2; - uint32_t LPCLKDIV4:2; - uint32_t LPCLKDIV3:2; - uint32_t LPCLKDIV2:2; - uint32_t LPCLKDIV1:2; - uint32_t LPCLKDIV0:2; - } B; - } SYSCLK; - - union { /* Halt Register */ - uint32_t R; - } HLT; - - union { /* Halt Acknowledge Register */ - uint32_t R; - } HLTACK; - - int32_t SIU_reserved8[149]; - - union { /* Parallel GPIO Pin Data Output Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t PB:16; - } B; - } PGPDO0; - - union { /* Parallel GPIO Pin Data Output Register */ - uint32_t R; - struct { - uint32_t PC:16; - uint32_t PD:16; - } B; - } PGPDO1; - - union { /* Parallel GPIO Pin Data Output Register */ - uint32_t R; - struct { - uint32_t PE:16; - uint32_t PF:16; - } B; - } PGPDO2; - - union { /* Parallel GPIO Pin Data Output Register */ - uint32_t R; - struct { - uint32_t PG:16; - uint32_t PH:16; - } B; - } PGPDO3; - - union { /* Parallel GPIO Pin Data Output Register */ - uint32_t R; - struct { - uint32_t PJ:16; - uint32_t:16; - } B; - } PGPDO4; - - int32_t SIU_reserved9[11]; - - union { /* Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PA:16; - uint32_t PB:16; - } B; - } PGPDI0; - - union { /* Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PC:16; - uint32_t PD:16; - } B; - } PGPDI1; - - union { /* Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PE:16; - uint32_t PF:16; - } B; - } PGPDI2; - - union { /* Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PG:16; - uint32_t PH:16; - } B; - } PGPDI3; - - union { /* Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PJ:16; - uint32_t PK:2; - uint32_t:14; - } B; - } PGPDI4; - - int32_t SIU_reserved10[12]; - - union { /* Masked Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PB_MASK:16; - uint32_t PB:16; - } B; - } MPGPDO1; - - union { /* Masked Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PC_MASK:16; - uint32_t PC:16; - } B; - } MPGPDO2; - - union { /* Masked Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PD_MASK:16; - uint32_t PD:16; - } B; - } MPGPDO3; - - union { /* Masked Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PE_MASK:16; - uint32_t PE:16; - } B; - } MPGPDO4; - - union { /* Masked Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PF_MASK:16; - uint32_t PF:16; - } B; - } MPGPDO5; - - union { /* Masked Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PG_MASK:16; - uint32_t PG:16; - } B; - } MPGPDO6; - - union { /* Masked Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PH_MASK:16; - uint32_t PH:16; - } B; - } MPGPDO7; - - union { /* Masked Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PJ_MASK:16; - uint32_t PJ:16; - } B; - } MPGPDO8; - - }; -/****************************************************************************/ -/* MODULE : FlexRay */ -/****************************************************************************/ - - typedef union uMVR { - uint16_t R; - struct { - uint16_t CHIVER:8; /* CHI Version Number */ - uint16_t PEVER:8; /* PE Version Number */ - } B; - } MVR_t; - - typedef union uMCR { - uint16_t R; - struct { - uint16_t MEN:1; /* module enable */ - uint16_t:1; - uint16_t SCMD:1; /* single channel mode */ - uint16_t CHB:1; /* channel B enable */ - uint16_t CHA:1; /* channel A enable */ - uint16_t SFFE:1; /* synchronization frame filter enable */ - uint16_t:5; - uint16_t CLKSEL:1; /* protocol engine clock source select */ - uint16_t PRESCALE:3; /* protocol engine clock prescaler */ - uint16_t:1; - } B; - } MCR_t; - typedef union uSTBSCR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t STBSSEL:7; /* strobe signal select */ - uint16_t:3; - uint16_t ENB:1; /* strobe signal enable */ - uint16_t:2; - uint16_t STBPSEL:2; /* strobe port select */ - } B; - } STBSCR_t; - typedef union uMBDSR { - uint16_t R; - struct { - uint16_t:1; - uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ - uint16_t:1; - uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ - } B; - } MBDSR_t; - - typedef union uMBSSUTR { - uint16_t R; - struct { - - uint16_t:2; - uint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */ - uint16_t:2; - uint16_t LAST_MB_UTIL:6; /* last message buffer utilized */ - } B; - } MBSSUTR_t; - - typedef union uPOCR { - uint16_t R; - uint8_t byte[2]; - struct { - uint16_t WME:1; /* write mode external correction command */ - uint16_t:3; - uint16_t EOC_AP:2; /* external offset correction application */ - uint16_t ERC_AP:2; /* external rate correction application */ - uint16_t BSY:1; /* command write busy / write mode command */ - uint16_t:3; - uint16_t POCCMD:4; /* protocol command */ - } B; - } POCR_t; -/* protocol commands */ - typedef union uGIFER { - uint16_t R; - struct { - uint16_t MIF:1; /* module interrupt flag */ - uint16_t PRIF:1; /* protocol interrupt flag */ - uint16_t CHIF:1; /* CHI interrupt flag */ - uint16_t WKUPIF:1; /* wakeup interrupt flag */ - uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ - uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ - uint16_t RBIF:1; /* receive message buffer interrupt flag */ - uint16_t TBIF:1; /* transmit buffer interrupt flag */ - uint16_t MIE:1; /* module interrupt enable */ - uint16_t PRIE:1; /* protocol interrupt enable */ - uint16_t CHIE:1; /* CHI interrupt enable */ - uint16_t WKUPIE:1; /* wakeup interrupt enable */ - uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ - uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ - uint16_t RBIE:1; /* receive message buffer interrupt enable */ - uint16_t TBIE:1; /* transmit buffer interrupt enable */ - } B; - } GIFER_t; - typedef union uPIFR0 { - uint16_t R; - struct { - uint16_t FATLIF:1; /* fatal protocol error interrupt flag */ - uint16_t INTLIF:1; /* internal protocol error interrupt flag */ - uint16_t ILCFIF:1; /* illegal protocol configuration flag */ - uint16_t CSAIF:1; /* cold start abort interrupt flag */ - uint16_t MRCIF:1; /* missing rate correctio interrupt flag */ - uint16_t MOCIF:1; /* missing offset correctio interrupt flag */ - uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ - uint16_t MXSIF:1; /* max sync frames detected interrupt flag */ - uint16_t MTXIF:1; /* media access test symbol received flag */ - uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ - uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ - uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ - uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ - uint16_t TI2IF:1; /* timer 2 expired interrupt flag */ - uint16_t TI1IF:1; /* timer 1 expired interrupt flag */ - uint16_t CYSIF:1; /* cycle start interrupt flag */ - } B; - } PIFR0_t; - typedef union uPIFR1 { - uint16_t R; - struct { - uint16_t EMCIF:1; /* error mode changed interrupt flag */ - uint16_t IPCIF:1; /* illegal protocol command interrupt flag */ - uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ - uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ - uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ - uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ - uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ - uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ - uint16_t:2; - uint16_t EVTIF:1; /* even cycle table written interrupt flag */ - uint16_t ODTIF:1; /* odd cycle table written interrupt flag */ - uint16_t:4; - } B; - } PIFR1_t; - typedef union uPIER0 { - uint16_t R; - struct { - uint16_t FATLIE:1; /* fatal protocol error interrupt enable */ - uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ - uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ - uint16_t CSAIE:1; /* cold start abort interrupt enable */ - uint16_t MRCIE:1; /* missing rate correctio interrupt enable */ - uint16_t MOCIE:1; /* missing offset correctio interrupt enable */ - uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ - uint16_t MXSIE:1; /* max sync frames detected interrupt enable */ - uint16_t MTXIE:1; /* media access test symbol received interrupt enable */ - uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ - uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ - uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ - uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ - uint16_t TI2IE:1; /* timer 2 expired interrupt enable */ - uint16_t TI1IE:1; /* timer 1 expired interrupt enable */ - uint16_t CYSIE:1; /* cycle start interrupt enable */ - } B; - } PIER0_t; - typedef union uPIER1 { - uint16_t R; - struct { - uint16_t EMCIE:1; /* error mode changed interrupt enable */ - uint16_t IPCIE:1; /* illegal protocol command interrupt enable */ - uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ - uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ - uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ - uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ - uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ - uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ - uint16_t:2; - uint16_t EVTIE:1; /* even cycle table written interrupt enable */ - uint16_t ODTIE:1; /* odd cycle table written interrupt enable */ - uint16_t:4; - } B; - } PIER1_t; - typedef union uCHIERFR { - uint16_t R; - struct { - uint16_t FRLBEF:1; /* flame lost channel B error flag */ - uint16_t FRLAEF:1; /* frame lost channel A error flag */ - uint16_t PCMIEF:1; /* command ignored error flag */ - uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ - uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ - uint16_t MSBEF:1; /* message buffer search error flag */ - uint16_t MBUEF:1; /* message buffer utilization error flag */ - uint16_t LCKEF:1; /* lock error flag */ - uint16_t DBLEF:1; /* double transmit message buffer lock error flag */ - uint16_t SBCFEF:1; /* system bus communication failure error flag */ - uint16_t FIDEF:1; /* frame ID error flag */ - uint16_t DPLEF:1; /* dynamic payload length error flag */ - uint16_t SPLEF:1; /* static payload length error flag */ - uint16_t NMLEF:1; /* network management length error flag */ - uint16_t NMFEF:1; /* network management frame error flag */ - uint16_t ILSAEF:1; /* illegal access error flag */ - } B; - } CHIERFR_t; - typedef union uMBIVEC { - uint16_t R; - struct { - - uint16_t:2; - uint16_t TBIVEC:6; /* transmit buffer interrupt vector */ - uint16_t:2; - uint16_t RBIVEC:6; /* receive buffer interrupt vector */ - } B; - } MBIVEC_t; - - typedef union uPSR0 { - uint16_t R; - struct { - uint16_t ERRMODE:2; /* error mode */ - uint16_t SLOTMODE:2; /* slot mode */ - uint16_t:1; - uint16_t PROTSTATE:3; /* protocol state */ - uint16_t SUBSTATE:4; /* protocol sub state */ - uint16_t:1; - uint16_t WAKEUPSTATUS:3; /* wakeup status */ - } B; - } PSR0_t; - -/* protocol states */ -/* protocol sub-states */ -/* wakeup status */ - typedef union uPSR1 { - uint16_t R; - struct { - uint16_t CSAA:1; /* cold start attempt abort flag */ - uint16_t SCP:1; /* cold start path */ - uint16_t:1; - uint16_t REMCSAT:5; /* remanining coldstart attempts */ - uint16_t CPN:1; /* cold start noise path */ - uint16_t HHR:1; /* host halt request pending */ - uint16_t FRZ:1; /* freeze occured */ - uint16_t APTAC:5; /* allow passive to active counter */ - } B; - } PSR1_t; - typedef union uPSR2 { - uint16_t R; - struct { - uint16_t NBVB:1; /* NIT boundary violation on channel B */ - uint16_t NSEB:1; /* NIT syntax error on channel B */ - uint16_t STCB:1; /* symbol window transmit conflict on channel B */ - uint16_t SBVB:1; /* symbol window boundary violation on channel B */ - uint16_t SSEB:1; /* symbol window syntax error on channel B */ - uint16_t MTB:1; /* media access test symbol MTS received on channel B */ - uint16_t NBVA:1; /* NIT boundary violation on channel A */ - uint16_t NSEA:1; /* NIT syntax error on channel A */ - uint16_t STCA:1; /* symbol window transmit conflict on channel A */ - uint16_t SBVA:1; /* symbol window boundary violation on channel A */ - uint16_t SSEA:1; /* symbol window syntax error on channel A */ - uint16_t MTA:1; /* media access test symbol MTS received on channel A */ - uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ - } B; - } PSR2_t; - typedef union uPSR3 { - uint16_t R; - struct { - uint16_t:2; - uint16_t WUB:1; /* wakeup symbol received on channel B */ - uint16_t ABVB:1; /* aggregated boundary violation on channel B */ - uint16_t AACB:1; /* aggregated additional communication on channel B */ - uint16_t ACEB:1; /* aggregated content error on channel B */ - uint16_t ASEB:1; /* aggregated syntax error on channel B */ - uint16_t AVFB:1; /* aggregated valid frame on channel B */ - uint16_t:2; - uint16_t WUA:1; /* wakeup symbol received on channel A */ - uint16_t ABVA:1; /* aggregated boundary violation on channel A */ - uint16_t AACA:1; /* aggregated additional communication on channel A */ - uint16_t ACEA:1; /* aggregated content error on channel A */ - uint16_t ASEA:1; /* aggregated syntax error on channel A */ - uint16_t AVFA:1; /* aggregated valid frame on channel A */ - } B; - } PSR3_t; - typedef union uCIFRR { - uint16_t R; - struct { - uint16_t:8; - uint16_t MIFR:1; /* module interrupt flag */ - uint16_t PRIFR:1; /* protocol interrupt flag */ - uint16_t CHIFR:1; /* CHI interrupt flag */ - uint16_t WUPIFR:1; /* wakeup interrupt flag */ - uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ - uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ - uint16_t RBIFR:1; /* receive message buffer interrupt flag */ - uint16_t TBIFR:1; /* transmit buffer interrupt flag */ - } B; - } CIFRR_t; - typedef union uSYMATOR { - uint16_t R; - struct { - uint16_t:11; - uint16_t TIMEOUT:5; /* system memory time out value */ - } B; - } SYMATOR_t; - - typedef union uSFCNTR { - uint16_t R; - struct { - uint16_t SFEVB:4; /* sync frames channel B, even cycle */ - uint16_t SFEVA:4; /* sync frames channel A, even cycle */ - uint16_t SFODB:4; /* sync frames channel B, odd cycle */ - uint16_t SFODA:4; /* sync frames channel A, odd cycle */ - } B; - } SFCNTR_t; - - typedef union uSFTCCSR { - uint16_t R; - struct { - uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ - uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ - uint16_t CYCNUM:6; /* cycle number */ - uint16_t ELKS:1; /* even cycle tables lock status */ - uint16_t OLKS:1; /* odd cycle tables lock status */ - uint16_t EVAL:1; /* even cycle tables valid */ - uint16_t OVAL:1; /* odd cycle tables valid */ - uint16_t:1; - uint16_t OPT:1; /*one pair trigger */ - uint16_t SDVEN:1; /* sync frame deviation table enable */ - uint16_t SIDEN:1; /* sync frame ID table enable */ - } B; - } SFTCCSR_t; - typedef union uSFIDRFR { - uint16_t R; - struct { - uint16_t:6; - uint16_t SYNFRID:10; /* sync frame rejection ID */ - } B; - } SFIDRFR_t; - - typedef union uTICCR { - uint16_t R; - struct { - uint16_t:2; - uint16_t T2CFG:1; /* timer 2 configuration */ - uint16_t T2REP:1; /* timer 2 repetitive mode */ - uint16_t:1; - uint16_t T2SP:1; /* timer 2 stop */ - uint16_t T2TR:1; /* timer 2 trigger */ - uint16_t T2ST:1; /* timer 2 state */ - uint16_t:3; - uint16_t T1REP:1; /* timer 1 repetitive mode */ - uint16_t:1; - uint16_t T1SP:1; /* timer 1 stop */ - uint16_t T1TR:1; /* timer 1 trigger */ - uint16_t T1ST:1; /* timer 1 state */ - - } B; - } TICCR_t; - typedef union uTI1CYSR { - uint16_t R; - struct { - uint16_t:2; - uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ - uint16_t:2; - uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ - - } B; - } TI1CYSR_t; - - typedef union uSSSR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t:1; - uint16_t SEL:2; /* static slot number */ - uint16_t:1; - uint16_t SLOTNUMBER:11; /* selector */ - } B; - } SSSR_t; - - typedef union uSSCCR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t:1; - uint16_t SEL:2; /* selector */ - uint16_t:1; - uint16_t CNTCFG:2; /* counter configuration */ - uint16_t MCY:1; /* multi cycle selection */ - uint16_t VFR:1; /* valid frame selection */ - uint16_t SYF:1; /* sync frame selection */ - uint16_t NUF:1; /* null frame selection */ - uint16_t SUF:1; /* startup frame selection */ - uint16_t STATUSMASK:4; /* slot status mask */ - } B; - } SSCCR_t; - typedef union uSSR { - uint16_t R; - struct { - uint16_t VFB:1; /* valid frame on channel B */ - uint16_t SYB:1; /* valid sync frame on channel B */ - uint16_t NFB:1; /* valid null frame on channel B */ - uint16_t SUB:1; /* valid startup frame on channel B */ - uint16_t SEB:1; /* syntax error on channel B */ - uint16_t CEB:1; /* content error on channel B */ - uint16_t BVB:1; /* boundary violation on channel B */ - uint16_t TCB:1; /* tx conflict on channel B */ - uint16_t VFA:1; /* valid frame on channel A */ - uint16_t SYA:1; /* valid sync frame on channel A */ - uint16_t NFA:1; /* valid null frame on channel A */ - uint16_t SUA:1; /* valid startup frame on channel A */ - uint16_t SEA:1; /* syntax error on channel A */ - uint16_t CEA:1; /* content error on channel A */ - uint16_t BVA:1; /* boundary violation on channel A */ - uint16_t TCA:1; /* tx conflict on channel A */ - } B; - } SSR_t; - typedef union uMTSCFR { - uint16_t R; - struct { - uint16_t MTE:1; /* media access test symbol transmission enable */ - uint16_t:1; - uint16_t CYCCNTMSK:6; /* cycle counter mask */ - uint16_t:2; - uint16_t CYCCNTVAL:6; /* cycle counter value */ - } B; - } MTSCFR_t; - - typedef union uRSBIR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t:1; - uint16_t SEL:2; /* selector */ - uint16_t:5; - uint16_t RSBIDX:7; /* receive shadow buffer index */ - } B; - } RSBIR_t; - - typedef union uRFDSR { - uint16_t R; - struct { - uint16_t FIFODEPTH:8; /* fifo depth */ - uint16_t:1; - uint16_t ENTRYSIZE:7; /* entry size */ - } B; - } RFDSR_t; - - typedef union uRFRFCFR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t IBD:1; /* interval boundary */ - uint16_t SEL:2; /* filter number */ - uint16_t:1; - uint16_t SID:11; /* slot ID */ - } B; - } RFRFCFR_t; - - typedef union uRFRFCTR { - uint16_t R; - struct { - uint16_t:4; - uint16_t F3MD:1; /* filter mode */ - uint16_t F2MD:1; /* filter mode */ - uint16_t F1MD:1; /* filter mode */ - uint16_t F0MD:1; /* filter mode */ - uint16_t:4; - uint16_t F3EN:1; /* filter enable */ - uint16_t F2EN:1; /* filter enable */ - uint16_t F1EN:1; /* filter enable */ - uint16_t F0EN:1; /* filter enable */ - } B; - } RFRFCTR_t; - typedef union uPCR0 { - uint16_t R; - struct { - uint16_t ACTION_POINT_OFFSET:6; - uint16_t STATIC_SLOT_LENGTH:10; - } B; - } PCR0_t; - - typedef union uPCR1 { - uint16_t R; - struct { - uint16_t:2; - uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; - } B; - } PCR1_t; - - typedef union uPCR2 { - uint16_t R; - struct { - uint16_t MINISLOT_AFTER_ACTION_POINT:6; - uint16_t NUMBER_OF_STATIC_SLOTS:10; - } B; - } PCR2_t; - - typedef union uPCR3 { - uint16_t R; - struct { - uint16_t WAKEUP_SYMBOL_RX_LOW:6; - uint16_t MINISLOT_ACTION_POINT_OFFSET:5; - uint16_t COLDSTART_ATTEMPTS:5; - } B; - } PCR3_t; - - typedef union uPCR4 { - uint16_t R; - struct { - uint16_t CAS_RX_LOW_MAX:7; - uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; - } B; - } PCR4_t; - - typedef union uPCR5 { - uint16_t R; - struct { - uint16_t TSS_TRANSMITTER:4; - uint16_t WAKEUP_SYMBOL_TX_LOW:6; - uint16_t WAKEUP_SYMBOL_RX_IDLE:6; - } B; - } PCR5_t; - - typedef union uPCR6 { - uint16_t R; - struct { - uint16_t:1; - uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; - uint16_t MACRO_INITIAL_OFFSET_A:7; - } B; - } PCR6_t; - - typedef union uPCR7 { - uint16_t R; - struct { - uint16_t DECODING_CORRECTION_B:9; - uint16_t MICRO_PER_MACRO_NOM_HALF:7; - } B; - } PCR7_t; - - typedef union uPCR8 { - uint16_t R; - struct { - uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; - uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; - uint16_t WAKEUP_SYMBOL_TX_IDLE:8; - } B; - } PCR8_t; - - typedef union uPCR9 { - uint16_t R; - struct { - uint16_t MINISLOT_EXISTS:1; - uint16_t SYMBOL_WINDOW_EXISTS:1; - uint16_t OFFSET_CORRECTION_OUT:14; - } B; - } PCR9_t; - - typedef union uPCR10 { - uint16_t R; - struct { - uint16_t SINGLE_SLOT_ENABLED:1; - uint16_t WAKEUP_CHANNEL:1; - uint16_t MACRO_PER_CYCLE:14; - } B; - } PCR10_t; - - typedef union uPCR11 { - uint16_t R; - struct { - uint16_t KEY_SLOT_USED_FOR_STARTUP:1; - uint16_t KEY_SLOT_USED_FOR_SYNC:1; - uint16_t OFFSET_CORRECTION_START:14; - } B; - } PCR11_t; - - typedef union uPCR12 { - uint16_t R; - struct { - uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; - uint16_t KEY_SLOT_HEADER_CRC:11; - } B; - } PCR12_t; - - typedef union uPCR13 { - uint16_t R; - struct { - uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; - uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; - } B; - } PCR13_t; - - typedef union uPCR14 { - uint16_t R; - struct { - uint16_t RATE_CORRECTION_OUT:11; - uint16_t LISTEN_TIMEOUT_H:5; - } B; - } PCR14_t; - - typedef union uPCR15 { - uint16_t R; - struct { - uint16_t LISTEN_TIMEOUT_L:16; - } B; - } PCR15_t; - - typedef union uPCR16 { - uint16_t R; - struct { - uint16_t MACRO_INITIAL_OFFSET_B:7; - uint16_t NOISE_LISTEN_TIMEOUT_H:9; - } B; - } PCR16_t; - - typedef union uPCR17 { - uint16_t R; - struct { - uint16_t NOISE_LISTEN_TIMEOUT_L:16; - } B; - } PCR17_t; - - typedef union uPCR18 { - uint16_t R; - struct { - uint16_t WAKEUP_PATTERN:6; - uint16_t KEY_SLOT_ID:10; - } B; - } PCR18_t; - - typedef union uPCR19 { - uint16_t R; - struct { - uint16_t DECODING_CORRECTION_A:9; - uint16_t PAYLOAD_LENGTH_STATIC:7; - } B; - } PCR19_t; - - typedef union uPCR20 { - uint16_t R; - struct { - uint16_t MICRO_INITIAL_OFFSET_B:8; - uint16_t MICRO_INITIAL_OFFSET_A:8; - } B; - } PCR20_t; - - typedef union uPCR21 { - uint16_t R; - struct { - uint16_t EXTERN_RATE_CORRECTION:3; - uint16_t LATEST_TX:13; - } B; - } PCR21_t; - - typedef union uPCR22 { - uint16_t R; - struct { - uint16_t:1; - uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; - uint16_t MICRO_PER_CYCLE_H:4; - } B; - } PCR22_t; - - typedef union uPCR23 { - uint16_t R; - struct { - uint16_t micro_per_cycle_l:16; - } B; - } PCR23_t; - - typedef union uPCR24 { - uint16_t R; - struct { - uint16_t CLUSTER_DRIFT_DAMPING:5; - uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; - uint16_t MICRO_PER_CYCLE_MIN_H:4; - } B; - } PCR24_t; - - typedef union uPCR25 { - uint16_t R; - struct { - uint16_t MICRO_PER_CYCLE_MIN_L:16; - } B; - } PCR25_t; - - typedef union uPCR26 { - uint16_t R; - struct { - uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; - uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; - uint16_t MICRO_PER_CYCLE_MAX_H:4; - } B; - } PCR26_t; - - typedef union uPCR27 { - uint16_t R; - struct { - uint16_t MICRO_PER_CYCLE_MAX_L:16; - } B; - } PCR27_t; - - typedef union uPCR28 { - uint16_t R; - struct { - uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; - uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; - } B; - } PCR28_t; - - typedef union uPCR29 { - uint16_t R; - struct { - uint16_t EXTERN_OFFSET_CORRECTION:3; - uint16_t MINISLOTS_MAX:13; - } B; - } PCR29_t; - - typedef union uPCR30 { - uint16_t R; - struct { - uint16_t:12; - uint16_t SYNC_NODE_MAX:4; - } B; - } PCR30_t; - - typedef struct uMSG_BUFF_CCS { - union { - uint16_t R; - struct { - uint16_t:1; - uint16_t MCM:1; /* message buffer commit mode */ - uint16_t MBT:1; /* message buffer type */ - uint16_t MTD:1; /* message buffer direction */ - uint16_t CMT:1; /* commit for transmission */ - uint16_t EDT:1; /* enable / disable trigger */ - uint16_t LCKT:1; /* lock request trigger */ - uint16_t MBIE:1; /* message buffer interrupt enable */ - uint16_t:3; - uint16_t DUP:1; /* data updated */ - uint16_t DVAL:1; /* data valid */ - uint16_t EDS:1; /* lock status */ - uint16_t LCKS:1; /* enable / disable status */ - uint16_t MBIF:1; /* message buffer interrupt flag */ - } B; - } MBCCSR; - union { - uint16_t R; - struct { - uint16_t MTM:1; /* message buffer transmission mode */ - uint16_t CHNLA:1; /* channel assignement */ - uint16_t CHNLB:1; /* channel assignement */ - uint16_t CCFE:1; /* cycle counter filter enable */ - uint16_t CCFMSK:6; /* cycle counter filter mask */ - uint16_t CCFVAL:6; /* cycle counter filter value */ - } B; - } MBCCFR; - union { - uint16_t R; - struct { - uint16_t:5; - uint16_t FID:11; /* frame ID */ - } B; - } MBFIDR; - - union { - uint16_t R; - struct { - uint16_t:9; - uint16_t MBIDX:7; /* message buffer index */ - } B; - } MBIDXR; - } MSG_BUFF_CCS_t; - typedef union uSYSBADHR { - uint16_t R; - } SYSBADHR_t; - typedef union uSYSBADLR { - uint16_t R; - } SYSBADLR_t; - typedef union uPADR { - uint16_t R; - } PADR_t; - typedef union uPDAR { - uint16_t R; - } PDAR_t; - typedef union uCASERCR { - uint16_t R; - } CASERCR_t; - typedef union uCBSERCR { - uint16_t R; - } CBSERCR_t; - typedef union uCYCTR { - uint16_t R; - } CYCTR_t; - typedef union uMTCTR { - uint16_t R; - } MTCTR_t; - typedef union uSLTCTAR { - uint16_t R; - } SLTCTAR_t; - typedef union uSLTCTBR { - uint16_t R; - } SLTCTBR_t; - typedef union uRTCORVR { - uint16_t R; - } RTCORVR_t; - typedef union uOFCORVR { - uint16_t R; - } OFCORVR_t; - typedef union uSFTOR { - uint16_t R; - } SFTOR_t; - typedef union uSFIDAFVR { - uint16_t R; - } SFIDAFVR_t; - typedef union uSFIDAFMR { - uint16_t R; - } SFIDAFMR_t; - typedef union uNMVR { - uint16_t R; - } NMVR_t; - typedef union uNMVLR { - uint16_t R; - } NMVLR_t; - typedef union uT1MTOR { - uint16_t R; - } T1MTOR_t; - typedef union uTI2CR0 { - uint16_t R; - } TI2CR0_t; - typedef union uTI2CR1 { - uint16_t R; - } TI2CR1_t; - typedef union uSSCR { - uint16_t R; - } SSCR_t; - typedef union uRFSR { - uint16_t R; - } RFSR_t; - typedef union uRFSIR { - uint16_t R; - } RFSIR_t; - typedef union uRFARIR { - uint16_t R; - } RFARIR_t; - typedef union uRFBRIR { - uint16_t R; - } RFBRIR_t; - typedef union uRFMIDAFVR { - uint16_t R; - } RFMIDAFVR_t; - typedef union uRFMIAFMR { - uint16_t R; - } RFMIAFMR_t; - typedef union uRFFIDRFVR { - uint16_t R; - } RFFIDRFVR_t; - typedef union uRFFIDRFMR { - uint16_t R; - } RFFIDRFMR_t; - typedef union uLDTXSLAR { - uint16_t R; - } LDTXSLAR_t; - typedef union uLDTXSLBR { - uint16_t R; - } LDTXSLBR_t; - - typedef struct FR_tag { - volatile MVR_t MVR; /*module version register *//*0 */ - volatile MCR_t MCR; /*module configuration register *//*2 */ - volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ - volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ - volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ - uint16_t reserved0[1]; /*A */ - volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ - volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ - uint16_t reserved1[1]; /*10 */ - uint16_t reserved2[1]; /*12 */ - volatile POCR_t POCR; /*Protocol operation control register *//*14 */ - volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ - volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ - volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ - volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ - volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ - volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ - volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ - volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ - volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ - volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ - volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ - volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ - volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ - volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ - volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ - volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ - volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ - volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ - volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ - volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ - volatile SYMATOR_t SYMATOR; /*system memory acess time-out register *//*3E */ - volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ - volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ - volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ - volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ - volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ - volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ - volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ - volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ - volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ - volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ - volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ - volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ - volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ - volatile SSSR_t SSSR; /*slot status selection register *//*64 */ - volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ - volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ - volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ - volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ - volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ - volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ - volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ - volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ - volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ - volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ - volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ - volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ - volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ - volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ - volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ - volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ - volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ - volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ - volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ - volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ - volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ - volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ - volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ - volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ - volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ - volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ - volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ - volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ - volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ - volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ - volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ - volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ - volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ - volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ - volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ - volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ - volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ - volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ - volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ - volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ - volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ - volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ - volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ - volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ - volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ - volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ - volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ - volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ - volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ - volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ - uint16_t reserved3[17]; - volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ - } FR_tag_t; - - typedef union uF_HEADER /* frame header */ - { - struct { - uint16_t:5; - uint16_t HDCRC:11; /* Header CRC */ - uint16_t:2; - uint16_t CYCCNT:6; /* Cycle Count */ - uint16_t:1; - uint16_t PLDLEN:7; /* Payload Length */ - uint16_t:1; - uint16_t PPI:1; /* Payload Preamble Indicator */ - uint16_t NUF:1; /* Null Frame Indicator */ - uint16_t SYF:1; /* Sync Frame Indicator */ - uint16_t SUF:1; /* Startup Frame Indicator */ - uint16_t FID:11; /* Frame ID */ - } B; - uint16_t WORDS[3]; - } F_HEADER_t; - typedef union uS_STSTUS /* slot status */ - { - struct { - uint16_t VFB:1; /* Valid Frame on channel B */ - uint16_t SYB:1; /* Sync Frame Indicator channel B */ - uint16_t NFB:1; /* Null Frame Indicator channel B */ - uint16_t SUB:1; /* Startup Frame Indicator channel B */ - uint16_t SEB:1; /* Syntax Error on channel B */ - uint16_t CEB:1; /* Content Error on channel B */ - uint16_t BVB:1; /* Boundary Violation on channel B */ - uint16_t CH:1; /* Channel */ - uint16_t VFA:1; /* Valid Frame on channel A */ - uint16_t SYA:1; /* Sync Frame Indicator channel A */ - uint16_t NFA:1; /* Null Frame Indicator channel A */ - uint16_t SUA:1; /* Startup Frame Indicator channel A */ - uint16_t SEA:1; /* Syntax Error on channel A */ - uint16_t CEA:1; /* Content Error on channel A */ - uint16_t BVA:1; /* Boundary Violation on channel A */ - uint16_t:1; - } RX; - struct { - uint16_t VFB:1; /* Valid Frame on channel B */ - uint16_t SYB:1; /* Sync Frame Indicator channel B */ - uint16_t NFB:1; /* Null Frame Indicator channel B */ - uint16_t SUB:1; /* Startup Frame Indicator channel B */ - uint16_t SEB:1; /* Syntax Error on channel B */ - uint16_t CEB:1; /* Content Error on channel B */ - uint16_t BVB:1; /* Boundary Violation on channel B */ - uint16_t TCB:1; /* Tx Conflict on channel B */ - uint16_t VFA:1; /* Valid Frame on channel A */ - uint16_t SYA:1; /* Sync Frame Indicator channel A */ - uint16_t NFA:1; /* Null Frame Indicator channel A */ - uint16_t SUA:1; /* Startup Frame Indicator channel A */ - uint16_t SEA:1; /* Syntax Error on channel A */ - uint16_t CEA:1; /* Content Error on channel A */ - uint16_t BVA:1; /* Boundary Violation on channel A */ - uint16_t TCA:1; /* Tx Conflict on channel A */ - } TX; - uint16_t R; - } S_STATUS_t; - - typedef struct uMB_HEADER /* message buffer header */ - { - F_HEADER_t FRAME_HEADER; - uint16_t DATA_OFFSET; - S_STATUS_t SLOT_STATUS; - } MB_HEADER_t; -/****************************************************************************/ -/* MODULE : MLB */ -/****************************************************************************/ - struct MLB_tag { - - union { /* MLB Module Configuration Register */ - uint32_t R; - struct { - uint32_t MDIS:1; - uint32_t:15; - uint32_t MDATOBSE:1; - uint32_t MSIGOBS:1; - uint32_t MSLOTE:1; - uint32_t:2; - uint32_t MSVRQIE:1; - uint32_t MDATRQE:1; - uint32_t:2; - uint32_t MSVRQDL:3; - uint32_t MSVRQCIE:1; - uint32_t MIFSEL:1; - uint32_t MSBFEPOL:1; - uint32_t MDBFEPOL:1; - } B; - } MCR; - - union { /* MLB Blank Register */ - uint32_t R; - struct { - uint32_t:31; - uint32_t BLANK:1; - } B; - } MBR; - - union { /* MLB Status Register */ - uint32_t R; - struct { - uint32_t:29; - uint32_t MDATRQS:1; - uint32_t MSYSS:1; - uint32_t MSVRQS:1; - } B; - } MSR; - - union { /* RX Control Channel Address Register */ - uint32_t R; - struct { - uint32_t RXCCHA_ACEN:1; - uint32_t:25; - uint32_t RXCCHA:5; - uint32_t:1; - } B; - } RXCCHAR; - - union { /* RX Async Channel Address Register */ - uint32_t R; - struct { - uint32_t RXACHA_ACEN:1; - uint32_t:25; - uint32_t RXACHA:5; - uint32_t:1; - } B; - } RXACHAR; - - union { /* TX Control Channel Address Register */ - uint32_t R; - struct { - uint32_t TXCCHA_ACEN:1; - uint32_t:25; - uint32_t TXCCHA:5; - uint32_t:1; - } B; - } TXCCHAR; - - union { /* TX Async Channel Address Register */ - uint32_t R; - struct { - uint32_t TXACHA_ACEN:1; - uint32_t:25; - uint32_t TXACHA:5; - uint32_t:1; - } B; - } TXACHAR; - - union { /* TX Sync Channel Address Register */ - uint32_t R; - struct { - uint32_t TXSCHA_ACEN:1; - uint32_t:25; - uint32_t TXSCHA:5; - uint32_t:1; - } B; - } TXSCHAR; - - union { /* TX Sync Channel Address Mask Register */ - uint32_t R; - struct { - uint32_t:26; - uint32_t TXSCHAM:5; - uint32_t:1; - } B; - } TXSCHAMR; - - union { /* Clock Adjust Control Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t PDLY:16; - } B; - } CLKACR; - - union { /* RX Isochronous Channel Address Register */ - uint32_t R; - struct { - uint32_t RXICHA_ACEN:1; - uint32_t:25; - uint32_t RXICHA:5; - uint32_t:1; - } B; - } RXICHAR; - - union { /* TX Isochronous Channel Address Register */ - uint32_t R; - struct { - uint32_t TXICHA_ACEN:1; - uint32_t:25; - uint32_t TXICHA:5; - uint32_t:1; - } B; - } TXICHAR; - - }; - -/* Define memories */ - -#define SRAM_START 0x40000000UL -#define SRAM_SIZE 0x14000UL -#define SRAM_END 0x40013FFFUL - -#define FLASH_START 0x0UL -#define FLASH_SIZE 0x180000UL -#define FLASH_END 0x17FFFFUL - -/* Define instances of modules */ -#define SEMA4 (*(volatile struct SEMA4_tag *) 0xFFF10000UL) -#define MPU (*(volatile struct MPU_tag *) 0xFFF14000UL) -#define MCM (*(volatile struct MCM_tag *) 0xFFF40000UL) -#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) -#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL) -#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000UL) -#define MLB (*(volatile struct MLB_tag *) 0xFFF84000UL) -#define I2C (*(volatile struct I2C_tag *) 0xFFF88000UL) -#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000UL) -#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000UL) -#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000UL) -#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000UL) -#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFA0000UL) -#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFA4000UL) -#define ESCI_C (*(volatile struct ESCI_tag *) 0xFFFA8000UL) -#define ESCI_D (*(volatile struct ESCI_tag *) 0xFFFAC000UL) -#define ESCI_E (*(volatile struct ESCI_tag *) 0xFFFB0000UL) -#define ESCI_F (*(volatile struct ESCI_tag *) 0xFFFB4000UL) -#define ESCI_G (*(volatile struct ESCI_tag *) 0xFFFB8000UL) -#define ESCI_H (*(volatile struct ESCI_tag *) 0xFFFBC000UL) -#define CAN_A (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL) -#define CAN_B (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL) -#define CAN_C (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL) -#define CAN_D (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL) -#define CAN_E (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL) -#define CAN_F (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL) -#define FR (*(volatile struct FR_tag *) 0xFFFD8000UL) -#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL) -#define PIT (*(volatile struct PIT_tag *) 0xFFFE0000UL) -#define EMIOS (*(volatile struct EMIOS_tag *) 0xFFFE4000UL) -#define SIU (*(volatile struct SIU_tag *) 0xFFFE8000UL) -#define CRP (*(volatile struct CRP_tag *) 0xFFFEC000UL) -#define FMPLL (*(volatile struct FMPLL_tag *) 0xFFFF0000UL) -#define EBI (*(volatile struct EBI_tag *) 0xFFFF4000UL) -#define FLASH (*(volatile struct FLASH_tag *) 0xFFFF8000UL) - -#ifdef __MWERKS__ -#pragma pop -#endif - -#ifdef __cplusplus -} -#endif -#endif /* ASM */ -#endif /* ifdef _MPC5510_H */ -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - * - ********************************************************************/ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc555x.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc555x.h deleted file mode 100644 index 0dea1957cf..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc555x.h +++ /dev/null @@ -1,3383 +0,0 @@ -/* - * Modifications of the original file provided by Freescale are: - * - * Copyright (c) 2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/**************************************************************************/ -/* FILE NAME: mpc5554.h COPYRIGHT (c) Freescale 2007 */ -/* VERSION: 1.7 All Rights Reserved */ -/* */ -/* DESCRIPTION: */ -/* This file contain all of the register and bit field definitions for */ -/* MPC5554. */ -/*========================================================================*/ -/* UPDATE HISTORY */ -/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ -/* --- ----------- --------- --------------------- */ -/* 0.01 J. Loeliger 03/Mar/03 Initial version of file for MPC5554. */ -/* Based on SoC version 0.7. */ -/* 0.02 J. Loeliger 05/Mar/03 All registers and bit fields now */ -/* defined. */ -/* 0.03 J. Loeliger 05/May/03 Updated to current spec., fixed several*/ -/* bugs and naming/formating issues. */ -/* 0.04 J. Loeliger 16/May/03 More fixes and naming/formating issues.*/ -/* 0.05 J. Loeliger 19/Aug/03 Updated for latest documentation. */ -/* 0.06 J. Loeliger 03/Sep/03 Changed to include motint.h */ -/* Updated many register names. */ -/* 0.07 J. Loeliger 04/Nov/03 Changed to include typedefs.h and more */ -/* register name updates. */ -/* 0.08 J. Loeliger 25/Feb/04 Added MetroWerks #pragmas. */ -/* Updated for user manual 1.0 */ -/* 0.09 J. Loeliger 27/Feb/04 Updated eDMA tcd section and some more */ -/* bit field names to match user's man. */ -/* 0.10 J. Loeliger 01/Apr/04 Fixed register spacing in ADC and eTPU */ -/* 0.11 J. Loeliger 16/Jun/04 Many fixes and updated to user's */ -/* manual, also some testing done. */ -/* 0.12 J. Loeliger 25/Jun/04 Fixed problems in edma and eTPU. */ -/* 0.13 J. Loeliger 16/Jul/04 Fixed mistake in FlexCAN TIMER size and*/ -/* changed eTPU memory defs to start with*/ -/* ETPU_ */ -/* 0.14 J. Loeliger 17/Nov/04 Added ETPU_CODE_RAM definition. */ -/* All code moved to CVS repository. */ -/* Updated copyright to Freescale. */ -/* Added new SCMOFFDATAR register to eTPU*/ -/* Fixed REDCR_A&B bit fields in eTPU. */ -/* Added new DBR bit in CTAR for DSPI. */ -/* 0.15 J. Loeliger 29/Nov/04 Added support for new eTPU util funcs. */ -/* Added bit fields for FlexCAN buffer ID*/ -/* 0.16 J. Loeliger 01/Dec/04 Corrected comments in release 0.16. */ -/* 0.17 J. Loeliger 02/Dec/04 Moved eTPU variable definitions to a */ -/* seperate new file. */ -/* Removed SIU variable the GPIO */ -/* routines do not need it. */ -/* 1.0 G.Emerson 22/Feb/05 No real changes to this file. */ -/* Joint generation with mpc5553.h */ -/* 1.1 G. Emerson 6/Jun/05 Changes to SIU to allow for upward */ -/* expansion of PCR/GPDI/GPDO */ -/* Added #defines for memory sizes etc */ -/* 1.2 G. Emerson 21/Sep/05 PBRIDGES fixes */ -/* 1.3 G. Emerson 03/Jan/06 Pbridge MPCR/PACR/OPACR now generic */ -/* XBAR MPR now generic */ -/* ECSM has FSBMCR on all integrations */ -/* 1.4 G. Emerson 24/Jan/06 Make Pbridges, XBAR, Flash BIU */ -/* integration specific */ -/* 1.5 S. Mathieson 28/Jul/06 Split out unused bit to support build */ -/* process. No real change. */ -/* 1.6 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */ -/* to DPB to align with documentation. */ -/* 1.7 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */ -/* alternate configuration. INTC, */ -/* correction to the number of PSR */ -/* registers. */ -/**************************************************************************/ -/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ - -#ifndef _MPC5554_H_ -#define _MPC5554_H_ - -#ifndef ASM - -#include <stdint.h> - -#include <mpc55xx/regs-edma.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __MWERKS__ -#pragma push -#pragma ANSI_strict off -#endif - -/****************************************************************************/ -/* MODULE : PBRIDGE_A Peripheral Bridge */ -/****************************************************************************/ - struct PBRIDGE_A_tag { - union { - uint32_t R; - struct { - uint32_t MBW0:1; - uint32_t MTR0:1; - uint32_t MTW0:1; - uint32_t MPL0:1; - uint32_t MBW1:1; - uint32_t MTR1:1; - uint32_t MTW1:1; - uint32_t MPL1:1; - uint32_t MBW2:1; - uint32_t MTR2:1; - uint32_t MTW2:1; - uint32_t MPL2:1; - uint32_t MBW3:1; - uint32_t MTR3:1; - uint32_t MTW3:1; - uint32_t MPL3:1; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - } B; - } MPCR; /* Master Privilege Control Register */ - - uint32_t pbridge_a_reserved2[7]; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t:28; - } B; - } PACR0; - - uint32_t pbridge_a_reserved3[7]; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t BW1:1; - uint32_t SP1:1; - uint32_t WP1:1; - uint32_t TP1:1; - uint32_t BW2:1; - uint32_t SP2:1; - uint32_t WP2:1; - uint32_t TP2:1; - uint32_t:4; - uint32_t BW4:1; - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - uint32_t:12; - } B; - } OPACR0; - - union { - uint32_t R; - struct { - - uint32_t BW0:1; /* EMIOS */ - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - - uint32_t:28; - } B; - } OPACR1; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t:4; - uint32_t BW2:1; - uint32_t SP2:1; - uint32_t WP2:1; - uint32_t TP2:1; - uint32_t BW3:1; - uint32_t SP3:1; - uint32_t WP3:1; - uint32_t TP3:1; - uint32_t BW4:1; - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - uint32_t:12; - } B; - } OPACR2; - - }; - -/****************************************************************************/ -/* MODULE : PBRIDGE_B Peripheral Bridge */ -/****************************************************************************/ - struct PBRIDGE_B_tag { - union { - uint32_t R; - struct { - uint32_t MBW0:1; - uint32_t MTR0:1; - uint32_t MTW0:1; - uint32_t MPL0:1; - uint32_t MBW1:1; - uint32_t MTR1:1; - uint32_t MTW1:1; - uint32_t MPL1:1; - uint32_t MBW2:1; - uint32_t MTR2:1; - uint32_t MTW2:1; - uint32_t MPL2:1; - uint32_t MBW3:1; - uint32_t MTR3:1; - uint32_t MTW3:1; - uint32_t MPL3:1; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - } B; - } MPCR; /* Master Privilege Control Register */ - - uint32_t pbridge_b_reserved2[7]; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t BW1:1; - uint32_t SP1:1; - uint32_t WP1:1; - uint32_t TP1:1; - uint32_t:24; - } B; - } PACR0; - - uint32_t pbridge_b_reserved3; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t BW1:1; - uint32_t SP1:1; - uint32_t WP1:1; - uint32_t TP1:1; - uint32_t BW2:1; - uint32_t SP2:1; - uint32_t WP2:1; - uint32_t TP2:1; - - uint32_t:4; - - uint32_t:16; - - } B; - } PACR2; - - uint32_t pbridge_b_reserved4[5]; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t:12; - - uint32_t BW4:1; /* DSPI_A */ - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - - uint32_t BW5:1; /* DSPI_B */ - uint32_t SP5:1; - uint32_t WP5:1; - uint32_t TP5:1; - - uint32_t BW6:1; - uint32_t SP6:1; - uint32_t WP6:1; - uint32_t TP6:1; - uint32_t BW7:1; - uint32_t SP7:1; - uint32_t WP7:1; - uint32_t TP7:1; - } B; - } OPACR0; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t BW4:1; - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - - uint32_t BW5:1; /* ESCI_B */ - uint32_t SP5:1; - uint32_t WP5:1; - uint32_t TP5:1; - - uint32_t:8; - } B; - } OPACR1; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - - uint32_t BW1:1; /* CAN_B */ - uint32_t SP1:1; - uint32_t WP1:1; - uint32_t TP1:1; - - uint32_t BW2:1; - uint32_t SP2:1; - uint32_t WP2:1; - uint32_t TP2:1; - - uint32_t:4; - - uint32_t:4; - - uint32_t:12; - } B; - } OPACR2; - - union { - uint32_t R; - struct { - - uint32_t:4; - - uint32_t:24; - uint32_t BW7:1; - uint32_t SP7:1; - uint32_t WP7:1; - uint32_t TP7:1; - } B; - } OPACR3; - - }; -/****************************************************************************/ -/* MODULE : FMPLL */ -/****************************************************************************/ - struct FMPLL_tag { - union FMPLL_SYNCR_tag { - uint32_t R; - struct { - uint32_t:1; - uint32_t PREDIV:3; - uint32_t MFD:5; - uint32_t:1; - uint32_t RFD:3; - uint32_t LOCEN:1; - uint32_t LOLRE:1; - uint32_t LOCRE:1; - uint32_t DISCLK:1; - uint32_t LOLIRQ:1; - uint32_t LOCIRQ:1; - uint32_t RATE:1; - uint32_t DEPTH:2; - uint32_t EXP:10; - } B; - } SYNCR; - - union FMPLL_SYNSR_tag { - uint32_t R; - struct { - uint32_t:22; - uint32_t LOLF:1; - uint32_t LOC:1; - uint32_t MODE:1; - uint32_t PLLSEL:1; - uint32_t PLLREF:1; - uint32_t LOCKS:1; - uint32_t LOCK:1; - uint32_t LOCF:1; - uint32_t CALDONE:1; - uint32_t CALPASS:1; - } B; - } SYNSR; - - }; -/****************************************************************************/ -/* MODULE : External Bus Interface (EBI) */ -/****************************************************************************/ - struct EBI_CS_tag { - union { /* Base Register Bank */ - uint32_t R; - struct { - uint32_t BA:17; - uint32_t:3; - uint32_t PS:1; - uint32_t:4; - uint32_t BL:1; - uint32_t WEBS:1; - uint32_t TBDIP:1; - uint32_t:2; - uint32_t BI:1; - uint32_t V:1; - } B; - } BR; - - union { /* Option Register Bank */ - uint32_t R; - struct { - uint32_t AM:17; - uint32_t:7; - uint32_t SCY:4; - uint32_t:1; - uint32_t BSCY:2; - uint32_t:1; - } B; - } OR; - }; - - struct EBI_CAL_CS_tag { - uint32_t ebi_cal_cs_reserved [2]; - }; - - struct EBI_tag { - union EBI_MCR_tag { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t:5; - uint32_t SIZEEN:1; - uint32_t SIZE:2; - uint32_t:8; - uint32_t ACGE:1; - uint32_t EXTM:1; - uint32_t EARB:1; - uint32_t EARP:2; - uint32_t:4; - uint32_t MDIS:1; - uint32_t:5; - uint32_t DBM:1; - } B; - } MCR; - - uint32_t EBI_reserved1; - - union { /* Transfer Error Status Register */ - uint32_t R; - struct { - uint32_t:30; - uint32_t TEAF:1; - uint32_t BMTF:1; - } B; - } TESR; - - union { /* Bus Monitor Control Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t BMT:8; - uint32_t BME:1; - uint32_t:7; - } B; - } BMCR; - - struct EBI_CS_tag CS[4]; - - uint32_t EBI_reserved2[4]; - - struct EBI_CAL_CS_tag CAL_CS[4]; - }; -/****************************************************************************/ -/* MODULE : FLASH */ -/****************************************************************************/ - struct FLASH_tag { - union { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t:4; - uint32_t SIZE:4; - uint32_t:1; - uint32_t LAS:3; - uint32_t:3; - uint32_t MAS:1; - uint32_t EER:1; - uint32_t RWE:1; - uint32_t BBEPE:1; - uint32_t EPE:1; - uint32_t PEAS:1; - uint32_t DONE:1; - uint32_t PEG:1; - - uint32_t:2; - - uint32_t STOP:1; - uint32_t:1; - uint32_t PGM:1; - uint32_t PSUS:1; - uint32_t ERS:1; - uint32_t ESUS:1; - uint32_t EHV:1; - } B; - } MCR; - - union LMLR_tag { /* LML Register */ - uint32_t R; - struct { - uint32_t LME:1; - uint32_t:10; - uint32_t SLOCK:1; - uint32_t MLOCK:4; - uint32_t LLOCK:16; - } B; - } LMLR; - - union HLR_tag { /* HL Register */ - uint32_t R; - struct { - uint32_t HBE:1; - uint32_t:3; - uint32_t HBLOCK:28; - } B; - } HLR; - - union SLMLR_tag { /* SLML Register */ - uint32_t R; - struct { - uint32_t SLE:1; - uint32_t:10; - uint32_t SSLOCK:1; - uint32_t SMLOCK:4; - uint32_t SLLOCK:16; - } B; - } SLMLR; - - union { /* LMS Register */ - uint32_t R; - struct { - uint32_t:12; - uint32_t MSEL:4; - uint32_t LSEL:16; - } B; - } LMSR; - - union { - uint32_t R; - struct { - uint32_t:4; - uint32_t HBSEL:28; - } B; - } HSR; - - union { - uint32_t R; - struct { - uint32_t:10; - uint32_t ADDR:19; - uint32_t:3; - } B; - } AR; - - union { - uint32_t R; - struct { - - uint32_t:11; - - uint32_t:1; - - uint32_t M3PFE:1; - uint32_t M2PFE:1; - uint32_t M1PFE:1; - uint32_t M0PFE:1; - uint32_t APC:3; - uint32_t WWSC:2; - uint32_t RWSC:3; - - uint32_t DPFEN:2; - uint32_t IPFEN:2; - - uint32_t PFLIM:3; - uint32_t BFEN:1; - } B; - } BIUCR; - - union { - uint32_t R; - struct { - - uint32_t:22; - - uint32_t:2; - - uint32_t M3AP:2; - uint32_t M2AP:2; - uint32_t M1AP:2; - uint32_t M0AP:2; - } B; - } BIUAPR; - }; -/****************************************************************************/ -/* MODULE : SIU */ -/****************************************************************************/ - struct SIU_tag { - int32_t SIU_reserved0; - - union { /* MCU ID Register */ - uint32_t R; - struct { - uint32_t PARTNUM:16; - uint32_t MASKNUM:16; - } B; - } MIDR; - int32_t SIU_reserved00; - - union { /* Reset Status Register */ - uint32_t R; - struct { - uint32_t PORS:1; - uint32_t ERS:1; - uint32_t LLRS:1; - uint32_t LCRS:1; - uint32_t WDRS:1; - uint32_t CRS:1; - uint32_t:8; - uint32_t SSRS:1; - uint32_t SERF:1; - uint32_t WKPCFG:1; - uint32_t:12; - uint32_t BOOTCFG:2; - uint32_t RGF:1; - } B; - } RSR; - - union { /* System Reset Control Register */ - uint32_t R; - struct { - uint32_t SSR:1; - uint32_t SER:1; - uint32_t:14; - uint32_t CRE:1; - uint32_t:15; - } B; - } SRCR; - - union SIU_EISR_tag { /* External Interrupt Status Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t EIF15:1; - uint32_t EIF14:1; - uint32_t EIF13:1; - uint32_t EIF12:1; - uint32_t EIF11:1; - uint32_t EIF10:1; - uint32_t EIF9:1; - uint32_t EIF8:1; - uint32_t EIF7:1; - uint32_t EIF6:1; - uint32_t EIF5:1; - uint32_t EIF4:1; - uint32_t EIF3:1; - uint32_t EIF2:1; - uint32_t EIF1:1; - uint32_t EIF0:1; - } B; - } EISR; - - union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t EIRE15:1; - uint32_t EIRE14:1; - uint32_t EIRE13:1; - uint32_t EIRE12:1; - uint32_t EIRE11:1; - uint32_t EIRE10:1; - uint32_t EIRE9:1; - uint32_t EIRE8:1; - uint32_t EIRE7:1; - uint32_t EIRE6:1; - uint32_t EIRE5:1; - uint32_t EIRE4:1; - uint32_t EIRE3:1; - uint32_t EIRE2:1; - uint32_t EIRE1:1; - uint32_t EIRE0:1; - } B; - } DIRER; - - union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t DIRS3:1; - uint32_t DIRS2:1; - uint32_t DIRS1:1; - uint32_t DIRS0:1; - } B; - } DIRSR; - - union { /* Overrun Status Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t OVF15:1; - uint32_t OVF14:1; - uint32_t OVF13:1; - uint32_t OVF12:1; - uint32_t OVF11:1; - uint32_t OVF10:1; - uint32_t OVF9:1; - uint32_t OVF8:1; - uint32_t OVF7:1; - uint32_t OVF6:1; - uint32_t OVF5:1; - uint32_t OVF4:1; - uint32_t OVF3:1; - uint32_t OVF2:1; - uint32_t OVF1:1; - uint32_t OVF0:1; - } B; - } OSR; - - union SIU_ORER_tag { /* Overrun Request Enable Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t ORE15:1; - uint32_t ORE14:1; - uint32_t ORE13:1; - uint32_t ORE12:1; - uint32_t ORE11:1; - uint32_t ORE10:1; - uint32_t ORE9:1; - uint32_t ORE8:1; - uint32_t ORE7:1; - uint32_t ORE6:1; - uint32_t ORE5:1; - uint32_t ORE4:1; - uint32_t ORE3:1; - uint32_t ORE2:1; - uint32_t ORE1:1; - uint32_t ORE0:1; - } B; - } ORER; - - union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t IREE15:1; - uint32_t IREE14:1; - uint32_t IREE13:1; - uint32_t IREE12:1; - uint32_t IREE11:1; - uint32_t IREE10:1; - uint32_t IREE9:1; - uint32_t IREE8:1; - uint32_t IREE7:1; - uint32_t IREE6:1; - uint32_t IREE5:1; - uint32_t IREE4:1; - uint32_t IREE3:1; - uint32_t IREE2:1; - uint32_t IREE1:1; - uint32_t IREE0:1; - } B; - } IREER; - - union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t IFEE15:1; - uint32_t IFEE14:1; - uint32_t IFEE13:1; - uint32_t IFEE12:1; - uint32_t IFEE11:1; - uint32_t IFEE10:1; - uint32_t IFEE9:1; - uint32_t IFEE8:1; - uint32_t IFEE7:1; - uint32_t IFEE6:1; - uint32_t IFEE5:1; - uint32_t IFEE4:1; - uint32_t IFEE3:1; - uint32_t IFEE2:1; - uint32_t IFEE1:1; - uint32_t IFEE0:1; - } B; - } IFEER; - - union SIU_IDFR_tag { /* External IRQ Digital Filter Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t DFL:4; - } B; - } IDFR; - - int32_t SIU_reserved1[3]; - - union SIU_PCR_tag { /* Pad Configuration Registers */ - uint16_t R; - struct { - uint16_t:3; - uint16_t PA:3; - uint16_t OBE:1; - uint16_t IBE:1; - uint16_t DSC:2; - uint16_t ODE:1; - uint16_t HYS:1; - uint16_t SRC:2; - uint16_t WPE:1; - uint16_t WPS:1; - } B; - } PCR[512]; - - int16_t SIU_reserved_0[224]; - - union { /* GPIO Pin Data Output Registers */ - uint8_t R; - struct { - uint8_t:7; - uint8_t PDO:1; - } B; - } GPDO[256]; - - int32_t SIU_reserved_3[64]; - - union { /* GPIO Pin Data Input Registers */ - uint8_t R; - struct { - uint8_t:7; - uint8_t PDI:1; - } B; - } GPDI[256]; - - union { /* IMUX Register */ - uint32_t R; - struct { - uint32_t TSEL5:2; - uint32_t TSEL4:2; - uint32_t TSEL3:2; - uint32_t TSEL2:2; - uint32_t TSEL1:2; - uint32_t TSEL0:2; - uint32_t:20; - } B; - } ETISR; - - union { /* IMUX Register */ - uint32_t R; - struct { - uint32_t ESEL15:2; - uint32_t ESEL14:2; - uint32_t ESEL13:2; - uint32_t ESEL12:2; - uint32_t ESEL11:2; - uint32_t ESEL10:2; - uint32_t ESEL9:2; - uint32_t ESEL8:2; - uint32_t ESEL7:2; - uint32_t ESEL6:2; - uint32_t ESEL5:2; - uint32_t ESEL4:2; - uint32_t ESEL3:2; - uint32_t ESEL2:2; - uint32_t ESEL1:2; - uint32_t ESEL0:2; - } B; - } EIISR; - - union { /* IMUX Register */ - uint32_t R; - struct { - uint32_t SINSELA:2; - uint32_t SSSELA:2; - uint32_t SCKSELA:2; - uint32_t TRIGSELA:2; - uint32_t SINSELB:2; - uint32_t SSSELB:2; - uint32_t SCKSELB:2; - uint32_t TRIGSELB:2; - uint32_t SINSELC:2; - uint32_t SSSELC:2; - uint32_t SCKSELC:2; - uint32_t TRIGSELC:2; - uint32_t SINSELD:2; - uint32_t SSSELD:2; - uint32_t SCKSELD:2; - uint32_t TRIGSELD:2; - } B; - } DISR; - - int32_t SIU_reserved2[29]; - - union { /* Chip Configuration Register Register */ - uint32_t R; - struct { - uint32_t:14; - uint32_t MATCH:1; - uint32_t DISNEX:1; - uint32_t:16; - } B; - } CCR; - - union { /* External Clock Configuration Register Register */ - uint32_t R; - struct { - uint32_t:18; - uint32_t ENGDIV:6; - uint32_t:4; - uint32_t EBTS:1; - uint32_t:1; - uint32_t EBDF:2; - } B; - } ECCR; - - union { - uint32_t R; - } CARH; - - union { - uint32_t R; - } CARL; - - union { - uint32_t R; - } CBRH; - - union { - uint32_t R; - } CBRL; - - }; -/****************************************************************************/ -/* MODULE : EMIOS */ -/****************************************************************************/ - struct EMIOS_tag { - union EMIOS_MCR_tag { - uint32_t R; - struct { - uint32_t:1; - uint32_t MDIS:1; - uint32_t FRZ:1; - uint32_t GTBE:1; - uint32_t ETB:1; - uint32_t GPREN:1; - uint32_t:6; - uint32_t SRV:4; - uint32_t GPRE:8; - uint32_t:8; - } B; - } MCR; /* Module Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t:8; - uint32_t F23:1; - uint32_t F22:1; - uint32_t F21:1; - uint32_t F20:1; - uint32_t F19:1; - uint32_t F18:1; - uint32_t F17:1; - uint32_t F16:1; - uint32_t F15:1; - uint32_t F14:1; - uint32_t F13:1; - uint32_t F12:1; - uint32_t F11:1; - uint32_t F10:1; - uint32_t F9:1; - uint32_t F8:1; - uint32_t F7:1; - uint32_t F6:1; - uint32_t F5:1; - uint32_t F4:1; - uint32_t F3:1; - uint32_t F2:1; - uint32_t F1:1; - uint32_t F0:1; - } B; - } GFR; /* Global FLAG Register */ - - union { - uint32_t R; - struct { - uint32_t:8; - uint32_t OU23:1; - uint32_t OU22:1; - uint32_t OU21:1; - uint32_t OU20:1; - uint32_t OU19:1; - uint32_t OU18:1; - uint32_t OU17:1; - uint32_t OU16:1; - uint32_t OU15:1; - uint32_t OU14:1; - uint32_t OU13:1; - uint32_t OU12:1; - uint32_t OU11:1; - uint32_t OU10:1; - uint32_t OU9:1; - uint32_t OU8:1; - uint32_t OU7:1; - uint32_t OU6:1; - uint32_t OU5:1; - uint32_t OU4:1; - uint32_t OU3:1; - uint32_t OU2:1; - uint32_t OU1:1; - uint32_t OU0:1; - } B; - } OUDR; /* Output Update Disable Register */ - - uint32_t emios_reserved[5]; - - struct EMIOS_CH_tag { - union { - uint32_t R; /* Channel A Data Register */ - } CADR; - - union { - uint32_t R; /* Channel B Data Register */ - } CBDR; - - union { - uint32_t R; /* Channel Counter Register */ - } CCNTR; - - union EMIOS_CCR_tag { - uint32_t R; - struct { - uint32_t FREN:1; - uint32_t ODIS:1; - uint32_t ODISSL:2; - uint32_t UCPRE:2; - uint32_t UCPREN:1; - uint32_t DMA:1; - uint32_t:1; - uint32_t IF:4; - uint32_t FCK:1; - uint32_t FEN:1; - uint32_t:3; - uint32_t FORCMA:1; - uint32_t FORCMB:1; - uint32_t:1; - uint32_t BSL:2; - uint32_t EDSEL:1; - uint32_t EDPOL:1; - uint32_t MODE:7; - } B; - } CCR; /* Channel Control Register */ - - union EMIOS_CSR_tag { - uint32_t R; - struct { - uint32_t OVR:1; - uint32_t:15; - uint32_t OVFL:1; - uint32_t:12; - uint32_t UCIN:1; - uint32_t UCOUT:1; - uint32_t FLAG:1; - } B; - } CSR; /* Channel Status Register */ - uint32_t emios_channel_reserved[3]; - - } CH[24]; - - }; -/****************************************************************************/ -/* MODULE :ETPU */ -/****************************************************************************/ - -/***************************Configuration Registers**************************/ - - struct ETPU_tag { - union { /* MODULE CONFIGURATION REGISTER */ - uint32_t R; - struct { - uint32_t GEC:1; /* Global Exception Clear */ - uint32_t:3; - uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */ - - uint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */ - - uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */ - - uint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */ - - uint32_t:3; - uint32_t SCMSIZE:5; /* Shared Code Memory size */ - uint32_t:5; - uint32_t SCMMISF:1; /* SCM MISC Flag */ - uint32_t SCMMISEN:1; /* SCM MISC Enable */ - uint32_t:2; - uint32_t VIS:1; /* SCM Visability */ - uint32_t:5; - uint32_t GTBE:1; /* Global Time Base Enable */ - } B; - } MCR; - - union { /* COHERENT DUAL-PARAMETER CONTROL */ - uint32_t R; - struct { - uint32_t STS:1; /* Start Status bit */ - uint32_t CTBASE:5; /* Channel Transfer Base */ - uint32_t PBASE:10; /* Parameter Buffer Base Address */ - uint32_t PWIDTH:1; /* Parameter Width */ - uint32_t PARAM0:7; /* Channel Parameter 0 */ - uint32_t WR:1; - uint32_t PARAM1:7; /* Channel Parameter 1 */ - } B; - } CDCR; - - uint32_t etpu_reserved1; - - union { /* MISC Compare Register */ - uint32_t R; - } MISCCMPR; - - union { /* SCM off-range Date Register */ - uint32_t R; - } SCMOFFDATAR; - - union { /* ETPU_A Configuration Register */ - uint32_t R; - struct { - uint32_t FEND:1; /* Force END */ - uint32_t MDIS:1; /* Low power Stop */ - uint32_t:1; - uint32_t STF:1; /* Stop Flag */ - uint32_t:4; - uint32_t HLTF:1; /* Halt Mode Flag */ - uint32_t:4; - uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ - uint32_t CDFC:2; - uint32_t:9; - uint32_t ETB:5; /* Entry Table Base */ - } B; - } ECR_A; - - union { /* ETPU_B Configuration Register */ - uint32_t R; - struct { - uint32_t FEND:1; /* Force END */ - uint32_t MDIS:1; /* Low power Stop */ - uint32_t:1; - uint32_t STF:1; /* Stop Flag */ - uint32_t:4; - uint32_t HLTF:1; /* Halt Mode Flag */ - uint32_t:4; - uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ - uint32_t CDFC:2; - uint32_t:9; - uint32_t ETB:5; /* Entry Table Base */ - } B; - } ECR_B; - - uint32_t etpu_reserved4; - - union { /* ETPU_A Timebase Configuration Register */ - uint32_t R; - struct { - uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ - uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ - uint32_t:1; - uint32_t AM:1; /* Angle Mode */ - uint32_t:3; - uint32_t TCR2P:6; /* TCR2 Prescaler Control */ - uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ - uint32_t:6; - uint32_t TCR1P:8; /* TCR1 Prescaler Control */ - } B; - } TBCR_A; - - union { /* ETPU_A TCR1 Visibility Register */ - uint32_t R; - } TB1R_A; - - union { /* ETPU_A TCR2 Visibility Register */ - uint32_t R; - } TB2R_A; - - union { /* ETPU_A STAC Configuration Register */ - uint32_t R; - struct { - uint32_t REN1:1; /* Resource Enable TCR1 */ - uint32_t RSC1:1; /* Resource Control TCR1 */ - uint32_t:2; - uint32_t SERVER_ID1:4; - uint32_t:4; - uint32_t SRV1:4; /* Resource Server Slot */ - uint32_t REN2:1; /* Resource Enable TCR2 */ - uint32_t RSC2:1; /* Resource Control TCR2 */ - uint32_t:2; - uint32_t SERVER_ID2:4; - uint32_t:4; - uint32_t SRV2:4; /* Resource Server Slot */ - } B; - } REDCR_A; - - uint32_t etpu_reserved5[4]; - - union { /* ETPU_B Timebase Configuration Register */ - uint32_t R; - struct { - uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ - uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ - uint32_t:1; - uint32_t AM:1; /* Angle Mode */ - uint32_t:3; - uint32_t TCR2P:6; /* TCR2 Prescaler Control */ - uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ - uint32_t:6; - uint32_t TCR1P:8; /* TCR1 Prescaler Control */ - } B; - } TBCR_B; - - union { /* ETPU_B TCR1 Visibility Register */ - uint32_t R; - } TB1R_B; - - union { /* ETPU_B TCR2 Visibility Register */ - uint32_t R; - } TB2R_B; - - union { /* ETPU_B STAC Configuration Register */ - uint32_t R; - struct { - uint32_t REN1:1; /* Resource Enable TCR1 */ - uint32_t RSC1:1; /* Resource Control TCR1 */ - uint32_t:2; - uint32_t SERVER_ID1:4; - uint32_t:4; - uint32_t SRV1:4; /* Resource Server Slot */ - uint32_t REN2:1; /* Resource Enable TCR2 */ - uint32_t RSC2:1; /* Resource Control TCR2 */ - uint32_t:2; - uint32_t SERVER_ID2:4; - uint32_t:4; - uint32_t SRV2:4; /* Resource Server Slot */ - } B; - } REDCR_B; - - uint32_t etpu_reserved7[108]; - -/*****************************Status and Control Registers**************************/ - - union { /* ETPU_A Channel Interrut Status */ - uint32_t R; - struct { - uint32_t CIS31:1; /* Channel 31 Interrut Status */ - uint32_t CIS30:1; /* Channel 30 Interrut Status */ - uint32_t CIS29:1; /* Channel 29 Interrut Status */ - uint32_t CIS28:1; /* Channel 28 Interrut Status */ - uint32_t CIS27:1; /* Channel 27 Interrut Status */ - uint32_t CIS26:1; /* Channel 26 Interrut Status */ - uint32_t CIS25:1; /* Channel 25 Interrut Status */ - uint32_t CIS24:1; /* Channel 24 Interrut Status */ - uint32_t CIS23:1; /* Channel 23 Interrut Status */ - uint32_t CIS22:1; /* Channel 22 Interrut Status */ - uint32_t CIS21:1; /* Channel 21 Interrut Status */ - uint32_t CIS20:1; /* Channel 20 Interrut Status */ - uint32_t CIS19:1; /* Channel 19 Interrut Status */ - uint32_t CIS18:1; /* Channel 18 Interrut Status */ - uint32_t CIS17:1; /* Channel 17 Interrut Status */ - uint32_t CIS16:1; /* Channel 16 Interrut Status */ - uint32_t CIS15:1; /* Channel 15 Interrut Status */ - uint32_t CIS14:1; /* Channel 14 Interrut Status */ - uint32_t CIS13:1; /* Channel 13 Interrut Status */ - uint32_t CIS12:1; /* Channel 12 Interrut Status */ - uint32_t CIS11:1; /* Channel 11 Interrut Status */ - uint32_t CIS10:1; /* Channel 10 Interrut Status */ - uint32_t CIS9:1; /* Channel 9 Interrut Status */ - uint32_t CIS8:1; /* Channel 8 Interrut Status */ - uint32_t CIS7:1; /* Channel 7 Interrut Status */ - uint32_t CIS6:1; /* Channel 6 Interrut Status */ - uint32_t CIS5:1; /* Channel 5 Interrut Status */ - uint32_t CIS4:1; /* Channel 4 Interrut Status */ - uint32_t CIS3:1; /* Channel 3 Interrut Status */ - uint32_t CIS2:1; /* Channel 2 Interrut Status */ - uint32_t CIS1:1; /* Channel 1 Interrut Status */ - uint32_t CIS0:1; /* Channel 0 Interrut Status */ - } B; - } CISR_A; - - union { /* ETPU_B Channel Interruput Status */ - uint32_t R; - struct { - uint32_t CIS31:1; /* Channel 31 Interrut Status */ - uint32_t CIS30:1; /* Channel 30 Interrut Status */ - uint32_t CIS29:1; /* Channel 29 Interrut Status */ - uint32_t CIS28:1; /* Channel 28 Interrut Status */ - uint32_t CIS27:1; /* Channel 27 Interrut Status */ - uint32_t CIS26:1; /* Channel 26 Interrut Status */ - uint32_t CIS25:1; /* Channel 25 Interrut Status */ - uint32_t CIS24:1; /* Channel 24 Interrut Status */ - uint32_t CIS23:1; /* Channel 23 Interrut Status */ - uint32_t CIS22:1; /* Channel 22 Interrut Status */ - uint32_t CIS21:1; /* Channel 21 Interrut Status */ - uint32_t CIS20:1; /* Channel 20 Interrut Status */ - uint32_t CIS19:1; /* Channel 19 Interrut Status */ - uint32_t CIS18:1; /* Channel 18 Interrut Status */ - uint32_t CIS17:1; /* Channel 17 Interrut Status */ - uint32_t CIS16:1; /* Channel 16 Interrut Status */ - uint32_t CIS15:1; /* Channel 15 Interrut Status */ - uint32_t CIS14:1; /* Channel 14 Interrut Status */ - uint32_t CIS13:1; /* Channel 13 Interrut Status */ - uint32_t CIS12:1; /* Channel 12 Interrut Status */ - uint32_t CIS11:1; /* Channel 11 Interrut Status */ - uint32_t CIS10:1; /* Channel 10 Interrut Status */ - uint32_t CIS9:1; /* Channel 9 Interrut Status */ - uint32_t CIS8:1; /* Channel 8 Interrut Status */ - uint32_t CIS7:1; /* Channel 7 Interrut Status */ - uint32_t CIS6:1; /* Channel 6 Interrut Status */ - uint32_t CIS5:1; /* Channel 5 Interrut Status */ - uint32_t CIS4:1; /* Channel 4 Interrut Status */ - uint32_t CIS3:1; /* Channel 3 Interrut Status */ - uint32_t CIS2:1; /* Channel 2 Interrut Status */ - uint32_t CIS1:1; /* Channel 1 Interrupt Status */ - uint32_t CIS0:1; /* Channel 0 Interrupt Status */ - } B; - } CISR_B; - - uint32_t etpu_reserved9[2]; - - union { /* ETPU_A Data Transfer Request Status */ - uint32_t R; - struct { - uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ - uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ - uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ - uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ - uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ - uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ - uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ - uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ - uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ - uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ - uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ - uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ - uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ - uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ - uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ - uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ - uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ - uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ - uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ - uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ - uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ - uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ - uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ - uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ - uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ - uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ - uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ - uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ - uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ - uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ - uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ - uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ - } B; - } CDTRSR_A; - - union { /* ETPU_B Data Transfer Request Status */ - uint32_t R; - struct { - uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ - uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ - uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ - uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ - uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ - uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ - uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ - uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ - uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ - uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ - uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ - uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ - uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ - uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ - uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ - uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ - uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ - uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ - uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ - uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ - uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ - uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ - uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ - uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ - uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ - uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ - uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ - uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ - uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ - uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ - uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ - uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ - } B; - } CDTRSR_B; - - uint32_t etpu_reserved11[2]; - - union { /* ETPU_A Interruput Overflow Status */ - uint32_t R; - struct { - uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ - uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ - uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ - uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ - uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ - uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ - uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ - uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ - uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ - uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ - uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ - uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ - uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ - uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ - uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ - uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ - uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ - uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ - uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ - uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ - uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ - uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ - uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ - uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ - uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ - uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ - uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ - uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ - uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ - uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ - uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ - uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ - } B; - } CIOSR_A; - - union { /* ETPU_B Interruput Overflow Status */ - uint32_t R; - struct { - uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ - uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ - uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ - uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ - uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ - uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ - uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ - uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ - uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ - uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ - uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ - uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ - uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ - uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ - uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ - uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ - uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ - uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ - uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ - uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ - uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ - uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ - uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ - uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ - uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ - uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ - uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ - uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ - uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ - uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ - uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ - uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ - } B; - } CIOSR_B; - - uint32_t etpu_reserved13[2]; - - union { /* ETPU_A Data Transfer Overflow Status */ - uint32_t R; - struct { - uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ - uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ - uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ - uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ - uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ - uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ - uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ - uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ - uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ - uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ - uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ - uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ - uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ - uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ - uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ - uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ - uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ - uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ - uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ - uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ - uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ - uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ - uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ - uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ - uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ - uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ - uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ - uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ - uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ - uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ - uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ - uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ - } B; - } CDTROSR_A; - - union { /* ETPU_B Data Transfer Overflow Status */ - uint32_t R; - struct { - uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ - uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ - uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ - uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ - uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ - uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ - uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ - uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ - uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ - uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ - uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ - uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ - uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ - uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ - uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ - uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ - uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ - uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ - uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ - uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ - uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ - uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ - uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ - uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ - uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ - uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ - uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ - uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ - uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ - uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ - uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ - uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ - } B; - } CDTROSR_B; - - uint32_t etpu_reserved15[2]; - - union { /* ETPU_A Channel Interruput Enable */ - uint32_t R; - struct { - uint32_t CIE31:1; /* Channel 31 Interruput Enable */ - uint32_t CIE30:1; /* Channel 30 Interruput Enable */ - uint32_t CIE29:1; /* Channel 29 Interruput Enable */ - uint32_t CIE28:1; /* Channel 28 Interruput Enable */ - uint32_t CIE27:1; /* Channel 27 Interruput Enable */ - uint32_t CIE26:1; /* Channel 26 Interruput Enable */ - uint32_t CIE25:1; /* Channel 25 Interruput Enable */ - uint32_t CIE24:1; /* Channel 24 Interruput Enable */ - uint32_t CIE23:1; /* Channel 23 Interruput Enable */ - uint32_t CIE22:1; /* Channel 22 Interruput Enable */ - uint32_t CIE21:1; /* Channel 21 Interruput Enable */ - uint32_t CIE20:1; /* Channel 20 Interruput Enable */ - uint32_t CIE19:1; /* Channel 19 Interruput Enable */ - uint32_t CIE18:1; /* Channel 18 Interruput Enable */ - uint32_t CIE17:1; /* Channel 17 Interruput Enable */ - uint32_t CIE16:1; /* Channel 16 Interruput Enable */ - uint32_t CIE15:1; /* Channel 15 Interruput Enable */ - uint32_t CIE14:1; /* Channel 14 Interruput Enable */ - uint32_t CIE13:1; /* Channel 13 Interruput Enable */ - uint32_t CIE12:1; /* Channel 12 Interruput Enable */ - uint32_t CIE11:1; /* Channel 11 Interruput Enable */ - uint32_t CIE10:1; /* Channel 10 Interruput Enable */ - uint32_t CIE9:1; /* Channel 9 Interruput Enable */ - uint32_t CIE8:1; /* Channel 8 Interruput Enable */ - uint32_t CIE7:1; /* Channel 7 Interruput Enable */ - uint32_t CIE6:1; /* Channel 6 Interruput Enable */ - uint32_t CIE5:1; /* Channel 5 Interruput Enable */ - uint32_t CIE4:1; /* Channel 4 Interruput Enable */ - uint32_t CIE3:1; /* Channel 3 Interruput Enable */ - uint32_t CIE2:1; /* Channel 2 Interruput Enable */ - uint32_t CIE1:1; /* Channel 1 Interruput Enable */ - uint32_t CIE0:1; /* Channel 0 Interruput Enable */ - } B; - } CIER_A; - - union { /* ETPU_B Channel Interruput Enable */ - uint32_t R; - struct { - uint32_t CIE31:1; /* Channel 31 Interruput Enable */ - uint32_t CIE30:1; /* Channel 30 Interruput Enable */ - uint32_t CIE29:1; /* Channel 29 Interruput Enable */ - uint32_t CIE28:1; /* Channel 28 Interruput Enable */ - uint32_t CIE27:1; /* Channel 27 Interruput Enable */ - uint32_t CIE26:1; /* Channel 26 Interruput Enable */ - uint32_t CIE25:1; /* Channel 25 Interruput Enable */ - uint32_t CIE24:1; /* Channel 24 Interruput Enable */ - uint32_t CIE23:1; /* Channel 23 Interruput Enable */ - uint32_t CIE22:1; /* Channel 22 Interruput Enable */ - uint32_t CIE21:1; /* Channel 21 Interruput Enable */ - uint32_t CIE20:1; /* Channel 20 Interruput Enable */ - uint32_t CIE19:1; /* Channel 19 Interruput Enable */ - uint32_t CIE18:1; /* Channel 18 Interruput Enable */ - uint32_t CIE17:1; /* Channel 17 Interruput Enable */ - uint32_t CIE16:1; /* Channel 16 Interruput Enable */ - uint32_t CIE15:1; /* Channel 15 Interruput Enable */ - uint32_t CIE14:1; /* Channel 14 Interruput Enable */ - uint32_t CIE13:1; /* Channel 13 Interruput Enable */ - uint32_t CIE12:1; /* Channel 12 Interruput Enable */ - uint32_t CIE11:1; /* Channel 11 Interruput Enable */ - uint32_t CIE10:1; /* Channel 10 Interruput Enable */ - uint32_t CIE9:1; /* Channel 9 Interruput Enable */ - uint32_t CIE8:1; /* Channel 8 Interruput Enable */ - uint32_t CIE7:1; /* Channel 7 Interruput Enable */ - uint32_t CIE6:1; /* Channel 6 Interruput Enable */ - uint32_t CIE5:1; /* Channel 5 Interruput Enable */ - uint32_t CIE4:1; /* Channel 4 Interruput Enable */ - uint32_t CIE3:1; /* Channel 3 Interruput Enable */ - uint32_t CIE2:1; /* Channel 2 Interruput Enable */ - uint32_t CIE1:1; /* Channel 1 Interruput Enable */ - uint32_t CIE0:1; /* Channel 0 Interruput Enable */ - } B; - } CIER_B; - - uint32_t etpu_reserved17[2]; - - union { /* ETPU_A Channel Data Transfer Request Enable */ - uint32_t R; - struct { - uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ - uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ - uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ - uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ - uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ - uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ - uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ - uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ - uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ - uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ - uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ - uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ - uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ - uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ - uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ - uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ - uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ - uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ - uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ - uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ - uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ - uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ - uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ - uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ - uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ - uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ - uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ - uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ - uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ - uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ - uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ - uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CDTRER_A; - - union { /* ETPU_B Channel Data Transfer Request Enable */ - uint32_t R; - struct { - uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ - uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ - uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ - uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ - uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ - uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ - uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ - uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ - uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ - uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ - uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ - uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ - uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ - uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ - uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ - uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ - uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ - uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ - uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ - uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ - uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ - uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ - uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ - uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ - uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ - uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ - uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ - uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ - uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ - uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ - uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ - uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CDTRER_B; - - uint32_t etpu_reserved20[10]; - union { /* ETPU_A Channel Pending Service Status */ - uint32_t R; - struct { - uint32_t SR31:1; /* Channel 31 Pending Service Status */ - uint32_t SR30:1; /* Channel 30 Pending Service Status */ - uint32_t SR29:1; /* Channel 29 Pending Service Status */ - uint32_t SR28:1; /* Channel 28 Pending Service Status */ - uint32_t SR27:1; /* Channel 27 Pending Service Status */ - uint32_t SR26:1; /* Channel 26 Pending Service Status */ - uint32_t SR25:1; /* Channel 25 Pending Service Status */ - uint32_t SR24:1; /* Channel 24 Pending Service Status */ - uint32_t SR23:1; /* Channel 23 Pending Service Status */ - uint32_t SR22:1; /* Channel 22 Pending Service Status */ - uint32_t SR21:1; /* Channel 21 Pending Service Status */ - uint32_t SR20:1; /* Channel 20 Pending Service Status */ - uint32_t SR19:1; /* Channel 19 Pending Service Status */ - uint32_t SR18:1; /* Channel 18 Pending Service Status */ - uint32_t SR17:1; /* Channel 17 Pending Service Status */ - uint32_t SR16:1; /* Channel 16 Pending Service Status */ - uint32_t SR15:1; /* Channel 15 Pending Service Status */ - uint32_t SR14:1; /* Channel 14 Pending Service Status */ - uint32_t SR13:1; /* Channel 13 Pending Service Status */ - uint32_t SR12:1; /* Channel 12 Pending Service Status */ - uint32_t SR11:1; /* Channel 11 Pending Service Status */ - uint32_t SR10:1; /* Channel 10 Pending Service Status */ - uint32_t SR9:1; /* Channel 9 Pending Service Status */ - uint32_t SR8:1; /* Channel 8 Pending Service Status */ - uint32_t SR7:1; /* Channel 7 Pending Service Status */ - uint32_t SR6:1; /* Channel 6 Pending Service Status */ - uint32_t SR5:1; /* Channel 5 Pending Service Status */ - uint32_t SR4:1; /* Channel 4 Pending Service Status */ - uint32_t SR3:1; /* Channel 3 Pending Service Status */ - uint32_t SR2:1; /* Channel 2 Pending Service Status */ - uint32_t SR1:1; /* Channel 1 Pending Service Status */ - uint32_t SR0:1; /* Channel 0 Pending Service Status */ - } B; - } CPSSR_A; - - union { /* ETPU_B Channel Pending Service Status */ - uint32_t R; - struct { - uint32_t SR31:1; /* Channel 31 Pending Service Status */ - uint32_t SR30:1; /* Channel 30 Pending Service Status */ - uint32_t SR29:1; /* Channel 29 Pending Service Status */ - uint32_t SR28:1; /* Channel 28 Pending Service Status */ - uint32_t SR27:1; /* Channel 27 Pending Service Status */ - uint32_t SR26:1; /* Channel 26 Pending Service Status */ - uint32_t SR25:1; /* Channel 25 Pending Service Status */ - uint32_t SR24:1; /* Channel 24 Pending Service Status */ - uint32_t SR23:1; /* Channel 23 Pending Service Status */ - uint32_t SR22:1; /* Channel 22 Pending Service Status */ - uint32_t SR21:1; /* Channel 21 Pending Service Status */ - uint32_t SR20:1; /* Channel 20 Pending Service Status */ - uint32_t SR19:1; /* Channel 19 Pending Service Status */ - uint32_t SR18:1; /* Channel 18 Pending Service Status */ - uint32_t SR17:1; /* Channel 17 Pending Service Status */ - uint32_t SR16:1; /* Channel 16 Pending Service Status */ - uint32_t SR15:1; /* Channel 15 Pending Service Status */ - uint32_t SR14:1; /* Channel 14 Pending Service Status */ - uint32_t SR13:1; /* Channel 13 Pending Service Status */ - uint32_t SR12:1; /* Channel 12 Pending Service Status */ - uint32_t SR11:1; /* Channel 11 Pending Service Status */ - uint32_t SR10:1; /* Channel 10 Pending Service Status */ - uint32_t SR9:1; /* Channel 9 Pending Service Status */ - uint32_t SR8:1; /* Channel 8 Pending Service Status */ - uint32_t SR7:1; /* Channel 7 Pending Service Status */ - uint32_t SR6:1; /* Channel 6 Pending Service Status */ - uint32_t SR5:1; /* Channel 5 Pending Service Status */ - uint32_t SR4:1; /* Channel 4 Pending Service Status */ - uint32_t SR3:1; /* Channel 3 Pending Service Status */ - uint32_t SR2:1; /* Channel 2 Pending Service Status */ - uint32_t SR1:1; /* Channel 1 Pending Service Status */ - uint32_t SR0:1; /* Channel 0 Pending Service Status */ - } B; - } CPSSR_B; - - uint32_t etpu_reserved20a[2]; - - union { /* ETPU_A Channel Service Status */ - uint32_t R; - struct { - uint32_t SS31:1; /* Channel 31 Service Status */ - uint32_t SS30:1; /* Channel 30 Service Status */ - uint32_t SS29:1; /* Channel 29 Service Status */ - uint32_t SS28:1; /* Channel 28 Service Status */ - uint32_t SS27:1; /* Channel 27 Service Status */ - uint32_t SS26:1; /* Channel 26 Service Status */ - uint32_t SS25:1; /* Channel 25 Service Status */ - uint32_t SS24:1; /* Channel 24 Service Status */ - uint32_t SS23:1; /* Channel 23 Service Status */ - uint32_t SS22:1; /* Channel 22 Service Status */ - uint32_t SS21:1; /* Channel 21 Service Status */ - uint32_t SS20:1; /* Channel 20 Service Status */ - uint32_t SS19:1; /* Channel 19 Service Status */ - uint32_t SS18:1; /* Channel 18 Service Status */ - uint32_t SS17:1; /* Channel 17 Service Status */ - uint32_t SS16:1; /* Channel 16 Service Status */ - uint32_t SS15:1; /* Channel 15 Service Status */ - uint32_t SS14:1; /* Channel 14 Service Status */ - uint32_t SS13:1; /* Channel 13 Service Status */ - uint32_t SS12:1; /* Channel 12 Service Status */ - uint32_t SS11:1; /* Channel 11 Service Status */ - uint32_t SS10:1; /* Channel 10 Service Status */ - uint32_t SS9:1; /* Channel 9 Service Status */ - uint32_t SS8:1; /* Channel 8 Service Status */ - uint32_t SS7:1; /* Channel 7 Service Status */ - uint32_t SS6:1; /* Channel 6 Service Status */ - uint32_t SS5:1; /* Channel 5 Service Status */ - uint32_t SS4:1; /* Channel 4 Service Status */ - uint32_t SS3:1; /* Channel 3 Service Status */ - uint32_t SS2:1; /* Channel 2 Service Status */ - uint32_t SS1:1; /* Channel 1 Service Status */ - uint32_t SS0:1; /* Channel 0 Service Status */ - } B; - } CSSR_A; - - union { /* ETPU_B Channel Service Status */ - uint32_t R; - struct { - uint32_t SS31:1; /* Channel 31 Service Status */ - uint32_t SS30:1; /* Channel 30 Service Status */ - uint32_t SS29:1; /* Channel 29 Service Status */ - uint32_t SS28:1; /* Channel 28 Service Status */ - uint32_t SS27:1; /* Channel 27 Service Status */ - uint32_t SS26:1; /* Channel 26 Service Status */ - uint32_t SS25:1; /* Channel 25 Service Status */ - uint32_t SS24:1; /* Channel 24 Service Status */ - uint32_t SS23:1; /* Channel 23 Service Status */ - uint32_t SS22:1; /* Channel 22 Service Status */ - uint32_t SS21:1; /* Channel 21 Service Status */ - uint32_t SS20:1; /* Channel 20 Service Status */ - uint32_t SS19:1; /* Channel 19 Service Status */ - uint32_t SS18:1; /* Channel 18 Service Status */ - uint32_t SS17:1; /* Channel 17 Service Status */ - uint32_t SS16:1; /* Channel 16 Service Status */ - uint32_t SS15:1; /* Channel 15 Service Status */ - uint32_t SS14:1; /* Channel 14 Service Status */ - uint32_t SS13:1; /* Channel 13 Service Status */ - uint32_t SS12:1; /* Channel 12 Service Status */ - uint32_t SS11:1; /* Channel 11 Service Status */ - uint32_t SS10:1; /* Channel 10 Service Status */ - uint32_t SS9:1; /* Channel 9 Service Status */ - uint32_t SS8:1; /* Channel 8 Service Status */ - uint32_t SS7:1; /* Channel 7 Service Status */ - uint32_t SS6:1; /* Channel 6 Service Status */ - uint32_t SS5:1; /* Channel 5 Service Status */ - uint32_t SS4:1; /* Channel 4 Service Status */ - uint32_t SS3:1; /* Channel 3 Service Status */ - uint32_t SS2:1; /* Channel 2 Service Status */ - uint32_t SS1:1; /* Channel 1 Service Status */ - uint32_t SS0:1; /* Channel 0 Service Status */ - } B; - } CSSR_B; - - uint32_t etpu_reserved23[90]; - -/*****************************Channels********************************/ - - struct { - union { - uint32_t R; /* Channel Configuration Register */ - struct { - uint32_t CIE:1; /* Channel Interruput Enable */ - uint32_t DTRE:1; /* Data Transfer Request Enable */ - uint32_t CPR:2; /* Channel Priority */ - uint32_t:3; - uint32_t ETCS:1; /* Entry Table Condition Select */ - uint32_t:3; - uint32_t CFS:5; /* Channel Function Select */ - uint32_t ODIS:1; /* Output disable */ - uint32_t OPOL:1; /* output polarity */ - uint32_t:3; - uint32_t CPBA:11; /* Channel Parameter Base Address */ - } B; - } CR; - union { - uint32_t R; /* Channel Status Control Register */ - struct { - uint32_t CIS:1; /* Channel Interruput Status */ - uint32_t CIOS:1; /* Channel Interruput Overflow Status */ - uint32_t:6; - uint32_t DTRS:1; /* Data Transfer Status */ - uint32_t DTROS:1; /* Data Transfer Overflow Status */ - uint32_t:6; - uint32_t IPS:1; /* Input Pin State */ - uint32_t OPS:1; /* Output Pin State */ - uint32_t OBE:1; /* Output Buffer Enable */ - uint32_t:11; - uint32_t FM1:1; /* Function mode */ - uint32_t FM0:1; /* Function mode */ - } B; - } SCR; - union { - uint32_t R; /* Channel Host Service Request Register */ - struct { - uint32_t:29; /* Host Service Request */ - uint32_t HSR:3; - } B; - } HSRR; - uint32_t etpu_reserved23; - } CHAN[127]; - - }; -/****************************************************************************/ -/* MODULE : XBAR CrossBar */ -/****************************************************************************/ - struct XBAR_tag { - union { - uint32_t R; - struct { - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:3; - } B; - } MPR0; /* Master Priority Register for Slave Port 0 */ - - uint32_t xbar_reserved1[3]; - - union { - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR0; /* General Purpose Control Register for Slave Port 0 */ - - uint32_t xbar_reserved2[59]; - - union { - uint32_t R; - struct { - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:3; - } B; - } MPR1; /* Master Priority Register for Slave Port 1 */ - - uint32_t xbar_reserved3[3]; - - union { - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR1; /* General Purpose Control Register for Slave Port 1 */ - - uint32_t xbar_reserved4[123]; - - union { - uint32_t R; - struct { - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:3; - } B; - } MPR3; /* Master Priority Register for Slave Port 3 */ - - uint32_t xbar_reserved5[3]; - - union { - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR3; /* General Purpose Control Register for Slave Port 3 */ - uint32_t xbar_reserved6[187]; - - union { - uint32_t R; - struct { - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:3; - } B; - } MPR6; /* Master Priority Register for Slave Port 6 */ - - uint32_t xbar_reserved7[3]; - - union { - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR6; /* General Purpose Control Register for Slave Port 6 */ - - uint32_t xbar_reserved8[59]; - - union { - uint32_t R; - struct { - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:4; - - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:3; - } B; - } MPR7; /* Master Priority Register for Slave Port 7 */ - - uint32_t xbar_reserved9[3]; - - union { - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR7; /* General Purpose Control Register for Slave Port 7 */ - - }; -/****************************************************************************/ -/* MODULE : ECSM */ -/****************************************************************************/ - struct ECSM_tag { - - uint32_t ecsm_reserved1[5]; - - uint16_t ecsm_reserved2; - - union { - uint16_t R; - } SWTCR; //Software Watchdog Timer Control - - uint8_t ecsm_reserved3[3]; - - union { - uint8_t R; - } SWTSR; //SWT Service Register - - uint8_t ecsm_reserved4[3]; - - union { - uint8_t R; - } SWTIR; //SWT Interrupt Register - - uint32_t ecsm_reserved5a[1]; - uint32_t ecsm_reserved5b[1]; - - uint32_t ecsm_reserved5c[6]; - - uint8_t ecsm_reserved6[3]; - - union { - uint8_t R; - struct { - uint8_t:6; - uint8_t ERNCR:1; - uint8_t EFNCR:1; - } B; - } ECR; //ECC Configuration Register - - uint8_t mcm_reserved8[3]; - - union { - uint8_t R; - struct { - uint8_t:6; - uint8_t RNCE:1; - uint8_t FNCE:1; - } B; - } ESR; //ECC Status Register - - uint16_t ecsm_reserved9; - - union { - uint16_t R; - struct { - uint16_t:6; - uint16_t FRCNCI:1; - uint16_t FR1NCI:1; - uint16_t:1; - uint16_t ERRBIT:7; - } B; - } EEGR; //ECC Error Generation Register - - uint32_t ecsm_reserved10; - - union { - uint32_t R; - struct { - uint32_t FEAR:32; - } B; - } FEAR; //Flash ECC Address Register - - uint16_t ecsm_reserved11; - - union { - uint8_t R; - struct { - uint8_t:4; - uint8_t FEMR:4; - } B; - } FEMR; //Flash ECC Master Register - - union { - uint8_t R; - struct { - uint8_t WRITE:1; - uint8_t SIZE:3; - uint8_t PROT0:1; - uint8_t PROT1:1; - uint8_t PROT2:1; - uint8_t PROT3:1; - } B; - } FEAT; //Flash ECC Attributes Register - - union { - uint32_t R; - struct { - uint32_t FEDH:32; - } B; - } FEDRH; //Flash ECC Data High Register - - union { - uint32_t R; - struct { - uint32_t FEDL:32; - } B; - } FEDRL; //Flash ECC Data Low Register - - union { - uint32_t R; - struct { - uint32_t REAR:32; - } B; - } REAR; //RAM ECC Address - - uint8_t ecsm_reserved12[2]; - - union { - uint8_t R; - struct { - uint8_t:4; - uint8_t REMR:4; - } B; - } REMR; //RAM ECC Master - - union { - uint8_t R; - struct { - uint8_t WRITE:1; - uint8_t SIZE:3; - uint8_t PROT0:1; - uint8_t PROT1:1; - uint8_t PROT2:1; - uint8_t PROT3:1; - } B; - } REAT; // RAM ECC Attributes Register - - union { - uint32_t R; - struct { - uint32_t REDH:32; - } B; - } REDRH; //RAM ECC Data High Register - - union { - uint32_t R; - struct { - uint32_t REDL:32; - } B; - } REDRL; //RAMECC Data Low Register - - }; -/****************************************************************************/ -/* MODULE : INTC */ -/****************************************************************************/ - struct INTC_tag { - union { - uint32_t R; - struct { - uint32_t:26; - uint32_t VTES:1; - uint32_t:4; - uint32_t HVEN:1; - } B; - } MCR; /* Module Configuration Register */ - - int32_t INTC_reserved00; - - union { - uint32_t R; - struct { - uint32_t:28; - uint32_t PRI:4; - } B; - } CPR; /* Current Priority Register */ - - uint32_t intc_reserved1; - - union { - uint32_t R; - struct { - uint32_t VTBA:21; - uint32_t INTVEC:9; - uint32_t:2; - } B; - } IACKR; /* Interrupt Acknowledge Register */ - - uint32_t intc_reserved2; - - union { - uint32_t R; - struct { - uint32_t:32; - } B; - } EOIR; /* End of Interrupt Register */ - - uint32_t intc_reserved3; - - union { - uint8_t R; - struct { - uint8_t:6; - uint8_t SET:1; - uint8_t CLR:1; - } B; - } SSCIR[8]; /* Software Set/Clear Interruput Register */ - - uint32_t intc_reserved4[6]; - - union { - uint8_t R; - struct { - uint8_t:4; - uint8_t PRI:4; - } B; - } PSR[358]; /* Software Set/Clear Interrupt Register */ - - }; -/****************************************************************************/ -/* MODULE : EQADC */ -/****************************************************************************/ - struct EQADC_tag { - union { - uint32_t R; - struct { - uint32_t:27; - uint32_t ESSIE:2; - uint32_t:1; - uint32_t DBG:2; - } B; - } MCR; /* Module Configuration Register */ - - int32_t EQADC_reserved00; - - union { - uint32_t R; - struct { - uint32_t:6; - uint32_t NMF:26; - } B; - } NMSFR; /* Null Message Send Format Register */ - - union { - uint32_t R; - struct { - uint32_t:28; - uint32_t DFL:4; - } B; - } ETDFR; /* External Trigger Digital Filter Register */ - - union { - uint32_t R; - struct { - uint32_t CFPUSH:32; - } B; - } CFPR[6]; /* CFIFO Push Registers */ - - uint32_t eqadc_reserved1; - - uint32_t eqadc_reserved2; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t RFPOP:16; - } B; - } RFPR[6]; /* Result FIFO Pop Registers */ - - uint32_t eqadc_reserved3; - - uint32_t eqadc_reserved4; - - union EQADC_CFCR_tag { - uint16_t R; - struct { - uint16_t:5; - uint16_t SSE:1; - uint16_t CFINV:1; - uint16_t:1; - uint16_t MODE:4; - uint16_t:4; - } B; - } CFCR[6]; /* CFIFO Control Registers */ - - uint32_t eqadc_reserved5; - - union EQADC_IDCR_tag { - uint16_t R; - struct { - uint16_t NCIE:1; - uint16_t TORIE:1; - uint16_t PIE:1; - uint16_t EOQIE:1; - uint16_t CFUIE:1; - uint16_t:1; - uint16_t CFFE:1; - uint16_t CFFS:1; - uint16_t:4; - uint16_t RFOIE:1; - uint16_t:1; - uint16_t RFDE:1; - uint16_t RFDS:1; - } B; - } IDCR[6]; /* Interrupt and DMA Control Registers */ - - uint32_t eqadc_reserved6; - - union EQADC_FISR_tag { - uint32_t R; - struct { - uint32_t NCF:1; - uint32_t TORF:1; - uint32_t PF:1; - uint32_t EOQF:1; - uint32_t CFUF:1; - uint32_t SSS:1; - uint32_t CFFF:1; - uint32_t:5; - uint32_t RFOF:1; - uint32_t:1; - uint32_t RFDF:1; - uint32_t:1; - uint32_t CFCTR:4; - uint32_t TNXTPTR:4; - uint32_t RFCTR:4; - uint32_t POPNXTPTR:4; - } B; - } FISR[6]; /* FIFO and Interrupt Status Registers */ - - uint32_t eqadc_reserved7; - - uint32_t eqadc_reserved8; - - union { - uint16_t R; - struct { - uint16_t:5; - uint16_t TCCF:11; - } B; - } CFTCR[6]; /* CFIFO Transfer Counter Registers */ - - uint32_t eqadc_reserved9; - - union { - uint32_t R; - struct { - uint32_t CFS0:2; - uint32_t CFS1:2; - uint32_t CFS2:2; - uint32_t CFS3:2; - uint32_t CFS4:2; - uint32_t CFS5:2; - uint32_t:5; - uint32_t LCFTCB0:4; - uint32_t TC_LCFTCB0:11; - } B; - } CFSSR0; /* CFIFO Status Register 0 */ - - union { - uint32_t R; - struct { - uint32_t CFS0:2; - uint32_t CFS1:2; - uint32_t CFS2:2; - uint32_t CFS3:2; - uint32_t CFS4:2; - uint32_t CFS5:2; - uint32_t:5; - uint32_t LCFTCB1:4; - uint32_t TC_LCFTCB1:11; - } B; - } CFSSR1; /* CFIFO Status Register 1 */ - - union { - uint32_t R; - struct { - uint32_t CFS0:2; - uint32_t CFS1:2; - uint32_t CFS2:2; - uint32_t CFS3:2; - uint32_t CFS4:2; - uint32_t CFS5:2; - uint32_t:4; - uint32_t ECBNI:1; - uint32_t LCFTSSI:4; - uint32_t TC_LCFTSSI:11; - } B; - } CFSSR2; /* CFIFO Status Register 2 */ - - union { - uint32_t R; - struct { - uint32_t CFS0:2; - uint32_t CFS1:2; - uint32_t CFS2:2; - uint32_t CFS3:2; - uint32_t CFS4:2; - uint32_t CFS5:2; - uint32_t:20; - } B; - } CFSR; - - uint32_t eqadc_reserved11; - - union { - uint32_t R; - struct { - uint32_t:21; - uint32_t MDT:3; - uint32_t:4; - uint32_t BR:4; - } B; - } SSICR; /* SSI Control Register */ - - union { - uint32_t R; - struct { - uint32_t RDV:1; - uint32_t:5; - uint32_t RDATA:26; - } B; - } SSIRDR; /* SSI Recieve Data Register */ - - uint32_t eqadc_reserved12[17]; - - struct { - union { - uint32_t R; - struct { - uint32_t:32; - } B; - } R[4]; - - uint32_t eqadc_reserved13[12]; - - } CF[6]; - - uint32_t eqadc_reserved14[32]; - - struct { - union { - uint32_t R; - struct { - uint32_t:32; - } B; - } R[4]; - - uint32_t eqadc_reserved15[12]; - - } RF[6]; - - }; - -/* Message Formats for On-Chip ADC Operation - */ -union EQADC_CONVERSION_COMMAND_tag { - uint32_t R; - struct { - uint32_t EOQ:1; - uint32_t PAUSE:1; - uint32_t:3; - uint32_t EB:1; - uint32_t BN:1; - uint32_t CAL:1; - uint32_t MESSAGE_TAG:4; - uint32_t LST:2; - uint32_t TSR:1; - uint32_t FMT:1; - uint32_t CHANNEL_NUMBER:8; - uint32_t:8; - } B; -}; /* Conversion command */ - -union EQADC_WRITE_CONFIGURATION_COMMAND_tag { - uint32_t R; - struct { - uint32_t EOQ:1; - uint32_t PAUSE:1; - uint32_t:3; - uint32_t EB:1; - uint32_t BN:1; - uint32_t RW:1; - uint32_t VALUE:16; - uint32_t ADDR:8; - } B; -}; /* Write configuration command */ - -/****************************************************************************/ -/* MODULE : DSPI */ -/****************************************************************************/ - struct DSPI_tag { - union DSPI_MCR_tag { - uint32_t R; - struct { - uint32_t MSTR:1; - uint32_t CONT_SCKE:1; - uint32_t DCONF:2; - uint32_t FRZ:1; - uint32_t MTFE:1; - uint32_t PCSSE:1; - uint32_t ROOE:1; - uint32_t:2; - uint32_t PCSIS5:1; - uint32_t PCSIS4:1; - uint32_t PCSIS3:1; - uint32_t PCSIS2:1; - uint32_t PCSIS1:1; - uint32_t PCSIS0:1; - uint32_t DOZE:1; - uint32_t MDIS:1; - uint32_t DIS_TXF:1; - uint32_t DIS_RXF:1; - uint32_t CLR_TXF:1; - uint32_t CLR_RXF:1; - uint32_t SMPL_PT:2; - uint32_t:7; - uint32_t HALT:1; - } B; - } MCR; /* Module Configuration Register */ - - uint32_t dspi_reserved1; - - union { - uint32_t R; - struct { - uint32_t TCNT:16; - uint32_t:16; - } B; - } TCR; - - union DSPI_CTAR_tag { - uint32_t R; - struct { - uint32_t DBR:1; - uint32_t FMSZ:4; - uint32_t CPOL:1; - uint32_t CPHA:1; - uint32_t LSBFE:1; - uint32_t PCSSCK:2; - uint32_t PASC:2; - uint32_t PDT:2; - uint32_t PBR:2; - uint32_t CSSCK:4; - uint32_t ASC:4; - uint32_t DT:4; - uint32_t BR:4; - } B; - } CTAR[8]; /* Clock and Transfer Attributes Registers */ - - union DSPI_SR_tag { - uint32_t R; - struct { - uint32_t TCF:1; - uint32_t TXRXS:1; - uint32_t:1; - uint32_t EOQF:1; - uint32_t TFUF:1; - uint32_t:1; - uint32_t TFFF:1; - uint32_t:5; - uint32_t RFOF:1; - uint32_t:1; - uint32_t RFDF:1; - uint32_t:1; - uint32_t TXCTR:4; - uint32_t TXNXTPTR:4; - uint32_t RXCTR:4; - uint32_t POPNXTPTR:4; - } B; - } SR; /* Status Register */ - - union DSPI_RSER_tag { - uint32_t R; - struct { - uint32_t TCFRE:1; - uint32_t:2; - uint32_t EOQFRE:1; - uint32_t TFUFRE:1; - uint32_t:1; - uint32_t TFFFRE:1; - uint32_t TFFFDIRS:1; - uint32_t:4; - uint32_t RFOFRE:1; - uint32_t:1; - uint32_t RFDFRE:1; - uint32_t RFDFDIRS:1; - uint32_t:16; - } B; - } RSER; /* DMA/Interrupt Request Select and Enable Register */ - - union DSPI_PUSHR_tag { - uint32_t R; - struct { - uint32_t CONT:1; - uint32_t CTAS:3; - uint32_t EOQ:1; - uint32_t CTCNT:1; - uint32_t:4; - uint32_t PCS5:1; - uint32_t PCS4:1; - uint32_t PCS3:1; - uint32_t PCS2:1; - uint32_t PCS1:1; - uint32_t PCS0:1; - uint32_t TXDATA:16; - } B; - } PUSHR; /* PUSH TX FIFO Register */ - - union DSPI_POPR_tag { - uint32_t R; - struct { - uint32_t:16; - uint32_t RXDATA:16; - } B; - } POPR; /* POP RX FIFO Register */ - - union { - uint32_t R; - struct { - uint32_t TXCMD:16; - uint32_t TXDATA:16; - } B; - } TXFR[4]; /* Transmit FIFO Registers */ - - uint32_t DSPI_reserved_txf[12]; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t RXDATA:16; - } B; - } RXFR[4]; /* Transmit FIFO Registers */ - - uint32_t DSPI_reserved_rxf[12]; - - union { - uint32_t R; - struct { - uint32_t MTOE:1; - uint32_t:1; - uint32_t MTOCNT:6; - uint32_t:4; - uint32_t TXSS:1; - uint32_t TPOL:1; - uint32_t TRRE:1; - uint32_t CID:1; - uint32_t DCONT:1; - uint32_t DSICTAS:3; - uint32_t:6; - uint32_t DPCS5:1; - uint32_t DPCS4:1; - uint32_t DPCS3:1; - uint32_t DPCS2:1; - uint32_t DPCS1:1; - uint32_t DPCS0:1; - } B; - } DSICR; /* DSI Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t SER_DATA:16; - } B; - } SDR; /* DSI Serialization Data Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t ASER_DATA:16; - } B; - } ASDR; /* DSI Alternate Serialization Data Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t COMP_DATA:16; - } B; - } COMPR; /* DSI Transmit Comparison Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t DESER_DATA:16; - } B; - } DDR; /* DSI deserialization Data Register */ - - }; -/****************************************************************************/ -/* MODULE : eSCI */ -/****************************************************************************/ - struct ESCI_tag { - union ESCI_CR1_tag { - uint32_t R; - struct { - uint32_t:3; - uint32_t SBR:13; - uint32_t LOOPS:1; - uint32_t SCISDOZ:1; - uint32_t RSRC:1; - uint32_t M:1; - uint32_t WAKE:1; - uint32_t ILT:1; - uint32_t PE:1; - uint32_t PT:1; - uint32_t TIE:1; - uint32_t TCIE:1; - uint32_t RIE:1; - uint32_t ILIE:1; - uint32_t TE:1; - uint32_t RE:1; - uint32_t RWU:1; - uint32_t SBK:1; - } B; - } CR1; /* Control Register 1 */ - - union ESCI_CR2_tag { - uint16_t R; - struct { - uint16_t MDIS:1; - uint16_t FBR:1; - uint16_t BSTP:1; - uint16_t IEBERR:1; - uint16_t RXDMA:1; - uint16_t TXDMA:1; - uint16_t BRK13:1; - uint16_t:1; - uint16_t BESM13:1; - uint16_t SBSTP:1; - uint16_t:2; - uint16_t ORIE:1; - uint16_t NFIE:1; - uint16_t FEIE:1; - uint16_t PFIE:1; - } B; - } CR2; /* Control Register 2 */ - - union ESCI_DR_tag { - uint16_t R; - struct { - uint16_t R8:1; - uint16_t T8:1; - uint16_t:6; - uint8_t D; - } B; - } DR; /* Data Register */ - - union ESCI_SR_tag { - uint32_t R; - struct { - uint32_t TDRE:1; - uint32_t TC:1; - uint32_t RDRF:1; - uint32_t IDLE:1; - uint32_t OR:1; - uint32_t NF:1; - uint32_t FE:1; - uint32_t PF:1; - uint32_t:3; - uint32_t BERR:1; - uint32_t:3; - uint32_t RAF:1; - uint32_t RXRDY:1; - uint32_t TXRDY:1; - uint32_t LWAKE:1; - uint32_t STO:1; - uint32_t PBERR:1; - uint32_t CERR:1; - uint32_t CKERR:1; - uint32_t FRC:1; - uint32_t:7; - uint32_t OVFL:1; - } B; - } SR; /* Status Register */ - - union { - uint32_t R; - struct { - uint32_t LRES:1; - uint32_t WU:1; - uint32_t WUD0:1; - uint32_t WUD1:1; - uint32_t LDBG:1; - uint32_t DSF:1; - uint32_t PRTY:1; - uint32_t LIN:1; - uint32_t RXIE:1; - uint32_t TXIE:1; - uint32_t WUIE:1; - uint32_t STIE:1; - uint32_t PBIE:1; - uint32_t CIE:1; - uint32_t CKIE:1; - uint32_t FCIE:1; - uint32_t:7; - uint32_t OFIE:1; - uint32_t:8; - } B; - } LCR; /* LIN Control Register */ - - union { - uint32_t R; - } LTR; /* LIN Transmit Register */ - - union { - uint32_t R; - } LRR; /* LIN Recieve Register */ - - union { - uint32_t R; - } LPR; /* LIN CRC Polynom Register */ - - }; -/****************************************************************************/ -/* MODULE : FlexCAN */ -/****************************************************************************/ - struct FLEXCAN2_tag { - union { - uint32_t R; - struct { - uint32_t MDIS:1; - uint32_t FRZ:1; - uint32_t:1; - uint32_t HALT:1; - uint32_t NOTRDY:1; - uint32_t:1; - uint32_t SOFTRST:1; - uint32_t FRZACK:1; - uint32_t:1; - uint32_t:1; - - uint32_t:1; - - uint32_t MDISACK:1; - uint32_t:1; - uint32_t:1; - - uint32_t:12; - - uint32_t MAXMB:6; - } B; - } MCR; /* Module Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t PRESDIV:8; - uint32_t RJW:2; - uint32_t PSEG1:3; - uint32_t PSEG2:3; - uint32_t BOFFMSK:1; - uint32_t ERRMSK:1; - uint32_t CLKSRC:1; - uint32_t LPB:1; - - uint32_t:4; - - uint32_t SMP:1; - uint32_t BOFFREC:1; - uint32_t TSYN:1; - uint32_t LBUF:1; - uint32_t LOM:1; - uint32_t PROPSEG:3; - } B; - } CR; /* Control Register */ - - union { - uint32_t R; - } TIMER; /* Free Running Timer */ - int32_t FLEXCAN_reserved00; - - union { - uint32_t R; - struct { - uint32_t:3; - uint32_t MI:29; - } B; - } RXGMASK; /* RX Global Mask */ - - union { - uint32_t R; - struct { - uint32_t:3; - uint32_t MI:29; - } B; - } RX14MASK; /* RX 14 Mask */ - - union { - uint32_t R; - struct { - uint32_t:3; - uint32_t MI:29; - } B; - } RX15MASK; /* RX 15 Mask */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t RXECNT:8; - uint32_t TXECNT:8; - } B; - } ECR; /* Error Counter Register */ - - union { - uint32_t R; - struct { - uint32_t:14; - - uint32_t:2; - - uint32_t BIT1ERR:1; - uint32_t BIT0ERR:1; - uint32_t ACKERR:1; - uint32_t CRCERR:1; - uint32_t FRMERR:1; - uint32_t STFERR:1; - uint32_t TXWRN:1; - uint32_t RXWRN:1; - uint32_t IDLE:1; - uint32_t TXRX:1; - uint32_t FLTCONF:2; - uint32_t:1; - uint32_t BOFFINT:1; - uint32_t ERRINT:1; - uint32_t:1; - } B; - } ESR; /* Error and Status Register */ - - union { - uint32_t R; - struct { - uint32_t BUF63M:1; - uint32_t BUF62M:1; - uint32_t BUF61M:1; - uint32_t BUF60M:1; - uint32_t BUF59M:1; - uint32_t BUF58M:1; - uint32_t BUF57M:1; - uint32_t BUF56M:1; - uint32_t BUF55M:1; - uint32_t BUF54M:1; - uint32_t BUF53M:1; - uint32_t BUF52M:1; - uint32_t BUF51M:1; - uint32_t BUF50M:1; - uint32_t BUF49M:1; - uint32_t BUF48M:1; - uint32_t BUF47M:1; - uint32_t BUF46M:1; - uint32_t BUF45M:1; - uint32_t BUF44M:1; - uint32_t BUF43M:1; - uint32_t BUF42M:1; - uint32_t BUF41M:1; - uint32_t BUF40M:1; - uint32_t BUF39M:1; - uint32_t BUF38M:1; - uint32_t BUF37M:1; - uint32_t BUF36M:1; - uint32_t BUF35M:1; - uint32_t BUF34M:1; - uint32_t BUF33M:1; - uint32_t BUF32M:1; - } B; - } IMRH; /* Interruput Masks Register */ - - union { - uint32_t R; - struct { - uint32_t BUF31M:1; - uint32_t BUF30M:1; - uint32_t BUF29M:1; - uint32_t BUF28M:1; - uint32_t BUF27M:1; - uint32_t BUF26M:1; - uint32_t BUF25M:1; - uint32_t BUF24M:1; - uint32_t BUF23M:1; - uint32_t BUF22M:1; - uint32_t BUF21M:1; - uint32_t BUF20M:1; - uint32_t BUF19M:1; - uint32_t BUF18M:1; - uint32_t BUF17M:1; - uint32_t BUF16M:1; - uint32_t BUF15M:1; - uint32_t BUF14M:1; - uint32_t BUF13M:1; - uint32_t BUF12M:1; - uint32_t BUF11M:1; - uint32_t BUF10M:1; - uint32_t BUF09M:1; - uint32_t BUF08M:1; - uint32_t BUF07M:1; - uint32_t BUF06M:1; - uint32_t BUF05M:1; - uint32_t BUF04M:1; - uint32_t BUF03M:1; - uint32_t BUF02M:1; - uint32_t BUF01M:1; - uint32_t BUF00M:1; - } B; - } IMRL; /* Interruput Masks Register */ - - union { - uint32_t R; - struct { - uint32_t BUF63I:1; - uint32_t BUF62I:1; - uint32_t BUF61I:1; - uint32_t BUF60I:1; - uint32_t BUF59I:1; - uint32_t BUF58I:1; - uint32_t BUF57I:1; - uint32_t BUF56I:1; - uint32_t BUF55I:1; - uint32_t BUF54I:1; - uint32_t BUF53I:1; - uint32_t BUF52I:1; - uint32_t BUF51I:1; - uint32_t BUF50I:1; - uint32_t BUF49I:1; - uint32_t BUF48I:1; - uint32_t BUF47I:1; - uint32_t BUF46I:1; - uint32_t BUF45I:1; - uint32_t BUF44I:1; - uint32_t BUF43I:1; - uint32_t BUF42I:1; - uint32_t BUF41I:1; - uint32_t BUF40I:1; - uint32_t BUF39I:1; - uint32_t BUF38I:1; - uint32_t BUF37I:1; - uint32_t BUF36I:1; - uint32_t BUF35I:1; - uint32_t BUF34I:1; - uint32_t BUF33I:1; - uint32_t BUF32I:1; - } B; - } IFRH; /* Interruput Flag Register */ - - union { - uint32_t R; - struct { - uint32_t BUF31I:1; - uint32_t BUF30I:1; - uint32_t BUF29I:1; - uint32_t BUF28I:1; - uint32_t BUF27I:1; - uint32_t BUF26I:1; - uint32_t BUF25I:1; - uint32_t BUF24I:1; - uint32_t BUF23I:1; - uint32_t BUF22I:1; - uint32_t BUF21I:1; - uint32_t BUF20I:1; - uint32_t BUF19I:1; - uint32_t BUF18I:1; - uint32_t BUF17I:1; - uint32_t BUF16I:1; - uint32_t BUF15I:1; - uint32_t BUF14I:1; - uint32_t BUF13I:1; - uint32_t BUF12I:1; - uint32_t BUF11I:1; - uint32_t BUF10I:1; - uint32_t BUF09I:1; - uint32_t BUF08I:1; - uint32_t BUF07I:1; - uint32_t BUF06I:1; - uint32_t BUF05I:1; - uint32_t BUF04I:1; - uint32_t BUF03I:1; - uint32_t BUF02I:1; - uint32_t BUF01I:1; - uint32_t BUF00I:1; - } B; - } IFRL; /* Interruput Flag Register */ - - uint32_t flexcan2_reserved2[19]; - - struct canbuf_t { - union { - uint32_t R; - struct { - uint32_t:4; - uint32_t CODE:4; - uint32_t:1; - uint32_t SRR:1; - uint32_t IDE:1; - uint32_t RTR:1; - uint32_t LENGTH:4; - uint32_t TIMESTAMP:16; - } B; - } CS; - - union { - uint32_t R; - struct { - uint32_t:3; - uint32_t STD_ID:11; - uint32_t EXT_ID:18; - } B; - } ID; - - union { - uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ - uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ - uint32_t W[2]; /* Data buffer in words (32 bits) */ - uint32_t R[2]; /* Data buffer in words (32 bits) */ - } DATA; - - } BUF[64]; - }; - -/* Define memories */ - -#define SRAM_START 0x40000000 -#define SRAM_SIZE 0x10000 -#define SRAM_END 0x4000FFFF - -#define FLASH_START 0x0 -#define FLASH_SIZE 0x200000 -#define FLASH_END 0x1FFFFF - -/* Define instances of modules */ -#define PBRIDGE_A (*(volatile struct PBRIDGE_A_tag *) 0xC3F00000) -#define FMPLL (*(volatile struct FMPLL_tag *) 0xC3F80000) -#define EBI (*(volatile struct EBI_tag *) 0xC3F84000) -#define FLASH (*(volatile struct FLASH_tag *) 0xC3F88000) -#define SIU (*(volatile struct SIU_tag *) 0xC3F90000) - -#define EMIOS (*(volatile struct EMIOS_tag *) 0xC3FA0000) -#define ETPU (*(volatile struct ETPU_tag *) 0xC3FC0000) -#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) -#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) -#define ETPU_DATA_RAM_END 0xC3FC8BFC -#define CODE_RAM (*( uint32_t *) 0xC3FD0000) -#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) - -#define PBRIDGE_B (*(volatile struct PBRIDGE_B_tag *) 0xFFF00000) -#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000) -#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000) -#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000) -#define INTC (*(volatile struct INTC_tag *) 0xFFF48000) - -#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000) - -#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000) -#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000) -#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000) -#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000) - -#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFB0000) -#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFB4000) - -#define CAN_A (*(volatile struct FLEXCAN2_tag *) 0xFFFC0000) -#define CAN_B (*(volatile struct FLEXCAN2_tag *) 0xFFFC4000) -#define CAN_C (*(volatile struct FLEXCAN2_tag *) 0xFFFC8000) - -#ifdef __MWERKS__ -#pragma pop -#endif - -#ifdef __cplusplus -} -#endif -#endif /* ASM */ -#endif /* ifdef _MPC5554_H */ -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - * - ********************************************************************/ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc556x.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc556x.h deleted file mode 100644 index 41ad83729a..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc556x.h +++ /dev/null @@ -1,4563 +0,0 @@ -/* - * Modifications of the original file provided by Freescale are: - * - * Copyright (c) 2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/**************************************************************************/ -/* FILE NAME: mpc5567.h COPYRIGHT (c) Freescale 2007 */ -/* VERSION: 1.5 All Rights Reserved */ -/* */ -/* DESCRIPTION: */ -/* This file contain all of the register and bit field definitions for */ -/* MPC5567. */ -/*========================================================================*/ -/* UPDATE HISTORY */ -/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ -/* --- ----------- --------- --------------------- */ -/* 1.0 G. Emerson 03/Jan/06 Initial version. */ -/* 1.1 G. Emerson 27/Mar/06 Fix issue with Flexcan BCC field. */ -/* 1.2 S. Mathieson 28/Jul/06 Change Flexcan BCC bit to MBFEN */ -/* Add Flexcan bits WRNEN, SRXDIS, */ -/* TWRNMSK, RWRNMSK,TWRNINT,RWRNINT */ -/* 1.3 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */ -/* to DPB to align with documentation. */ -/* 1.4 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */ -/* alternate configuration. */ -/* INTC, correction to the number of PSR */ -/* registers. */ -/* Updates to bitfield sizes in MBSSUTR, */ -/* MBIVEC, MBIDX & RSBIR. RSBIR, SELEC */ -/* changed to SEL & RFRFCFR, FNUM changed */ -/* to SEL to align with documentation. */ -/* Various register/ bitfield updates to */ -/* correct errors (MCR, TMODE bit removed.*/ -/* PADR register removed. PIER1, DRDIE bit*/ -/* removed & PIFR1, DRDIF removed. PCR1, */ -/* Filter bypass bit removed). */ -/* 1.5 S. Mathieson 25/Apr/07 SRAM size changed from 64K to 80K. */ -/* */ -/**************************************************************************/ -/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ - -#ifndef _MPC5567_H_ -#define _MPC5567_H_ - -#ifndef ASM - -#include <stdint.h> - -#include <mpc55xx/regs-edma.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __MWERKS__ -#pragma push -#pragma ANSI_strict off -#endif - -/****************************************************************************/ -/* MODULE : PBRIDGE_A Peripheral Bridge */ -/****************************************************************************/ - struct PBRIDGE_A_tag { - union { - uint32_t R; - struct { - uint32_t MBW0:1; - uint32_t MTR0:1; - uint32_t MTW0:1; - uint32_t MPL0:1; - uint32_t MBW1:1; - uint32_t MTR1:1; - uint32_t MTW1:1; - uint32_t MPL1:1; - uint32_t MBW2:1; - uint32_t MTR2:1; - uint32_t MTW2:1; - uint32_t MPL2:1; - uint32_t MBW3:1; - uint32_t MTR3:1; - uint32_t MTW3:1; - uint32_t MPL3:1; - - uint32_t MBW4:1; /* FEC */ - uint32_t MTR4:1; - uint32_t MTW4:1; - uint32_t MPL4:1; - - uint32_t:4; - - uint32_t MBW6:1; /* FLEXRAY */ - uint32_t MTR6:1; - uint32_t MTW6:1; - uint32_t MPL6:1; - - uint32_t:4; - } B; - } MPCR; /* Master Privilege Control Register */ - - uint32_t pbridge_a_reserved2[7]; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t:28; - } B; - } PACR0; - - uint32_t pbridge_a_reserved3[7]; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t BW1:1; - uint32_t SP1:1; - uint32_t WP1:1; - uint32_t TP1:1; - uint32_t BW2:1; - uint32_t SP2:1; - uint32_t WP2:1; - uint32_t TP2:1; - uint32_t:4; - uint32_t BW4:1; - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - uint32_t:12; - } B; - } OPACR0; - - union { - uint32_t R; - struct { - - uint32_t BW0:1; /* EMIOS */ - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - - uint32_t:28; - } B; - } OPACR1; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t:4; - uint32_t BW2:1; - uint32_t SP2:1; - uint32_t WP2:1; - uint32_t TP2:1; - uint32_t BW3:1; - uint32_t SP3:1; - uint32_t WP3:1; - uint32_t TP3:1; - uint32_t BW4:1; - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - uint32_t:12; - } B; - } OPACR2; - - }; - -/****************************************************************************/ -/* MODULE : PBRIDGE_B Peripheral Bridge */ -/****************************************************************************/ - struct PBRIDGE_B_tag { - union { - uint32_t R; - struct { - uint32_t MBW0:1; - uint32_t MTR0:1; - uint32_t MTW0:1; - uint32_t MPL0:1; - uint32_t MBW1:1; - uint32_t MTR1:1; - uint32_t MTW1:1; - uint32_t MPL1:1; - uint32_t MBW2:1; - uint32_t MTR2:1; - uint32_t MTW2:1; - uint32_t MPL2:1; - uint32_t MBW3:1; - uint32_t MTR3:1; - uint32_t MTW3:1; - uint32_t MPL3:1; - - uint32_t MBW4:1; /* FEC */ - uint32_t MTR4:1; - uint32_t MTW4:1; - uint32_t MPL4:1; - - uint32_t:4; - - uint32_t MBW6:1; /* FLEXRAY */ - uint32_t MTR6:1; - uint32_t MTW6:1; - uint32_t MPL6:1; - - uint32_t:4; - } B; - } MPCR; /* Master Privilege Control Register */ - - uint32_t pbridge_b_reserved2[7]; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t BW1:1; - uint32_t SP1:1; - uint32_t WP1:1; - uint32_t TP1:1; - uint32_t:24; - } B; - } PACR0; - - uint32_t pbridge_b_reserved3; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t BW1:1; - uint32_t SP1:1; - uint32_t WP1:1; - uint32_t TP1:1; - uint32_t BW2:1; - uint32_t SP2:1; - uint32_t WP2:1; - uint32_t TP2:1; - - uint32_t BW3:1; /* FEC */ - uint32_t SP3:1; - uint32_t WP3:1; - uint32_t TP3:1; - - uint32_t:16; - - } B; - } PACR2; - - uint32_t pbridge_b_reserved4[5]; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t:12; - - uint32_t:4; - - uint32_t BW5:1; /* DSPI_B */ - uint32_t SP5:1; - uint32_t WP5:1; - uint32_t TP5:1; - - uint32_t BW6:1; - uint32_t SP6:1; - uint32_t WP6:1; - uint32_t TP6:1; - uint32_t BW7:1; - uint32_t SP7:1; - uint32_t WP7:1; - uint32_t TP7:1; - } B; - } OPACR0; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t BW4:1; - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - - uint32_t BW5:1; /* ESCI_B */ - uint32_t SP5:1; - uint32_t WP5:1; - uint32_t TP5:1; - - uint32_t:8; - } B; - } OPACR1; - - union { - uint32_t R; - struct { - uint32_t BW0:1; - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - - uint32_t BW1:1; /* CAN_B */ - uint32_t SP1:1; - uint32_t WP1:1; - uint32_t TP1:1; - - uint32_t BW2:1; - uint32_t SP2:1; - uint32_t WP2:1; - uint32_t TP2:1; - - uint32_t BW3:1; /* CAN_D */ - uint32_t SP3:1; - uint32_t WP3:1; - uint32_t TP3:1; - - uint32_t BW4:1; /* CAN_E */ - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - - uint32_t:12; - } B; - } OPACR2; - - union { - uint32_t R; - struct { - - uint32_t BW0:1; /* FLEXRAY */ - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - - uint32_t:24; - uint32_t BW7:1; - uint32_t SP7:1; - uint32_t WP7:1; - uint32_t TP7:1; - } B; - } OPACR3; - - }; -/****************************************************************************/ -/* MODULE : FMPLL */ -/****************************************************************************/ - struct FMPLL_tag { - union FMPLL_SYNCR_tag { - uint32_t R; - struct { - uint32_t:1; - uint32_t PREDIV:3; - uint32_t MFD:5; - uint32_t:1; - uint32_t RFD:3; - uint32_t LOCEN:1; - uint32_t LOLRE:1; - uint32_t LOCRE:1; - uint32_t DISCLK:1; - uint32_t LOLIRQ:1; - uint32_t LOCIRQ:1; - uint32_t RATE:1; - uint32_t DEPTH:2; - uint32_t EXP:10; - } B; - } SYNCR; - - union FMPLL_SYNSR_tag { - uint32_t R; - struct { - uint32_t:22; - uint32_t LOLF:1; - uint32_t LOC:1; - uint32_t MODE:1; - uint32_t PLLSEL:1; - uint32_t PLLREF:1; - uint32_t LOCKS:1; - uint32_t LOCK:1; - uint32_t LOCF:1; - uint32_t CALDONE:1; - uint32_t CALPASS:1; - } B; - } SYNSR; - - }; -/****************************************************************************/ -/* MODULE : External Bus Interface (EBI) */ -/****************************************************************************/ - struct EBI_CS_tag { - union { /* Base Register Bank */ - uint32_t R; - struct { - uint32_t BA:17; - uint32_t:3; - uint32_t PS:1; - uint32_t:4; - uint32_t BL:1; - uint32_t WEBS:1; - uint32_t TBDIP:1; - uint32_t:2; - uint32_t BI:1; - uint32_t V:1; - } B; - } BR; - - union { /* Option Register Bank */ - uint32_t R; - struct { - uint32_t AM:17; - uint32_t:7; - uint32_t SCY:4; - uint32_t:1; - uint32_t BSCY:2; - uint32_t:1; - } B; - } OR; - }; - - struct EBI_CAL_CS_tag { - union { /* Calibration Base Register Bank */ - uint32_t R; - struct { - uint32_t BA:17; - uint32_t:3; - uint32_t PS:1; - uint32_t:4; - uint32_t BL:1; - uint32_t WEBS:1; - uint32_t TBDIP:1; - uint32_t:2; - uint32_t BI:1; - uint32_t V:1; - } B; - } BR; - - union { /* Calibration Option Register Bank */ - uint32_t R; - struct { - uint32_t AM:17; - uint32_t:7; - uint32_t SCY:4; - uint32_t:1; - uint32_t BSCY:2; - uint32_t:1; - } B; - } OR; - }; - - struct EBI_tag { - union EBI_MCR_tag { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t:5; - uint32_t SIZEEN:1; - uint32_t SIZE:2; - uint32_t:8; - uint32_t ACGE:1; - uint32_t EXTM:1; - uint32_t EARB:1; - uint32_t EARP:2; - uint32_t:4; - uint32_t MDIS:1; - uint32_t:5; - uint32_t DBM:1; - } B; - } MCR; - - uint32_t EBI_reserved1; - - union { /* Transfer Error Status Register */ - uint32_t R; - struct { - uint32_t:30; - uint32_t TEAF:1; - uint32_t BMTF:1; - } B; - } TESR; - - union { /* Bus Monitor Control Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t BMT:8; - uint32_t BME:1; - uint32_t:7; - } B; - } BMCR; - - struct EBI_CS_tag CS[4]; - -/* Calibration registers */ - uint32_t EBI_reserved2[4]; - struct EBI_CAL_CS_tag CAL_CS[4]; - - }; -/****************************************************************************/ -/* MODULE : FLASH */ -/****************************************************************************/ - struct FLASH_tag { - union { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t:4; - uint32_t SIZE:4; - uint32_t:1; - uint32_t LAS:3; - uint32_t:3; - uint32_t MAS:1; - uint32_t EER:1; - uint32_t RWE:1; - uint32_t BBEPE:1; - uint32_t EPE:1; - uint32_t PEAS:1; - uint32_t DONE:1; - uint32_t PEG:1; - - uint32_t:2; - - uint32_t STOP:1; - uint32_t:1; - uint32_t PGM:1; - uint32_t PSUS:1; - uint32_t ERS:1; - uint32_t ESUS:1; - uint32_t EHV:1; - } B; - } MCR; - - union LMLR_tag { /* LML Register */ - uint32_t R; - struct { - uint32_t LME:1; - uint32_t:10; - uint32_t SLOCK:1; - uint32_t MLOCK:4; - uint32_t LLOCK:16; - } B; - } LMLR; - - union HLR_tag { /* HL Register */ - uint32_t R; - struct { - uint32_t HBE:1; - uint32_t:3; - uint32_t HBLOCK:28; - } B; - } HLR; - - union SLMLR_tag { /* SLML Register */ - uint32_t R; - struct { - uint32_t SLE:1; - uint32_t:10; - uint32_t SSLOCK:1; - uint32_t SMLOCK:4; - uint32_t SLLOCK:16; - } B; - } SLMLR; - - union { /* LMS Register */ - uint32_t R; - struct { - uint32_t:12; - uint32_t MSEL:4; - uint32_t LSEL:16; - } B; - } LMSR; - - union { - uint32_t R; - struct { - uint32_t:4; - uint32_t HBSEL:28; - } B; - } HSR; - - union { - uint32_t R; - struct { - uint32_t:10; - uint32_t ADDR:19; - uint32_t:3; - } B; - } AR; - - union { - uint32_t R; - struct { - - uint32_t:9; - uint32_t M6PFE:1; /* Flexray */ - uint32_t:1; - - uint32_t M4PFE:1; /* FEC */ - - uint32_t M3PFE:1; - uint32_t M2PFE:1; - uint32_t M1PFE:1; - uint32_t M0PFE:1; - uint32_t APC:3; - uint32_t WWSC:2; - uint32_t RWSC:3; - - uint32_t DPFEN:2; - uint32_t IPFEN:2; - - uint32_t PFLIM:3; - uint32_t BFEN:1; - } B; - } BIUCR; - - union { - uint32_t R; - struct { - - uint32_t:18; - uint32_t M6AP:2; /* Flexray */ - uint32_t:2; - - uint32_t M4AP:2; /* FEC */ - - uint32_t M3AP:2; - uint32_t M2AP:2; - uint32_t M1AP:2; - uint32_t M0AP:2; - } B; - } BIUAPR; - }; -/****************************************************************************/ -/* MODULE : SIU */ -/****************************************************************************/ - struct SIU_tag { - int32_t SIU_reserved0; - - union { /* MCU ID Register */ - uint32_t R; - struct { - uint32_t PARTNUM:16; - uint32_t MASKNUM:16; - } B; - } MIDR; - int32_t SIU_reserved00; - - union { /* Reset Status Register */ - uint32_t R; - struct { - uint32_t PORS:1; - uint32_t ERS:1; - uint32_t LLRS:1; - uint32_t LCRS:1; - uint32_t WDRS:1; - uint32_t CRS:1; - uint32_t:8; - uint32_t SSRS:1; - uint32_t SERF:1; - uint32_t WKPCFG:1; - uint32_t:12; - uint32_t BOOTCFG:2; - uint32_t RGF:1; - } B; - } RSR; - - union { /* System Reset Control Register */ - uint32_t R; - struct { - uint32_t SSR:1; - uint32_t SER:1; - uint32_t:14; - uint32_t CRE:1; - uint32_t:15; - } B; - } SRCR; - - union SIU_EISR_tag { /* External Interrupt Status Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t EIF15:1; - uint32_t EIF14:1; - uint32_t EIF13:1; - uint32_t EIF12:1; - uint32_t EIF11:1; - uint32_t EIF10:1; - uint32_t EIF9:1; - uint32_t EIF8:1; - uint32_t EIF7:1; - uint32_t EIF6:1; - uint32_t EIF5:1; - uint32_t EIF4:1; - uint32_t EIF3:1; - uint32_t EIF2:1; - uint32_t EIF1:1; - uint32_t EIF0:1; - } B; - } EISR; - - union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t EIRE15:1; - uint32_t EIRE14:1; - uint32_t EIRE13:1; - uint32_t EIRE12:1; - uint32_t EIRE11:1; - uint32_t EIRE10:1; - uint32_t EIRE9:1; - uint32_t EIRE8:1; - uint32_t EIRE7:1; - uint32_t EIRE6:1; - uint32_t EIRE5:1; - uint32_t EIRE4:1; - uint32_t EIRE3:1; - uint32_t EIRE2:1; - uint32_t EIRE1:1; - uint32_t EIRE0:1; - } B; - } DIRER; - - union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t DIRS3:1; - uint32_t DIRS2:1; - uint32_t DIRS1:1; - uint32_t DIRS0:1; - } B; - } DIRSR; - - union { /* Overrun Status Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t OVF15:1; - uint32_t OVF14:1; - uint32_t OVF13:1; - uint32_t OVF12:1; - uint32_t OVF11:1; - uint32_t OVF10:1; - uint32_t OVF9:1; - uint32_t OVF8:1; - uint32_t OVF7:1; - uint32_t OVF6:1; - uint32_t OVF5:1; - uint32_t OVF4:1; - uint32_t OVF3:1; - uint32_t OVF2:1; - uint32_t OVF1:1; - uint32_t OVF0:1; - } B; - } OSR; - - union SIU_ORER_tag { /* Overrun Request Enable Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t ORE15:1; - uint32_t ORE14:1; - uint32_t ORE13:1; - uint32_t ORE12:1; - uint32_t ORE11:1; - uint32_t ORE10:1; - uint32_t ORE9:1; - uint32_t ORE8:1; - uint32_t ORE7:1; - uint32_t ORE6:1; - uint32_t ORE5:1; - uint32_t ORE4:1; - uint32_t ORE3:1; - uint32_t ORE2:1; - uint32_t ORE1:1; - uint32_t ORE0:1; - } B; - } ORER; - - union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t IREE15:1; - uint32_t IREE14:1; - uint32_t IREE13:1; - uint32_t IREE12:1; - uint32_t IREE11:1; - uint32_t IREE10:1; - uint32_t IREE9:1; - uint32_t IREE8:1; - uint32_t IREE7:1; - uint32_t IREE6:1; - uint32_t IREE5:1; - uint32_t IREE4:1; - uint32_t IREE3:1; - uint32_t IREE2:1; - uint32_t IREE1:1; - uint32_t IREE0:1; - } B; - } IREER; - - union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t IFEE15:1; - uint32_t IFEE14:1; - uint32_t IFEE13:1; - uint32_t IFEE12:1; - uint32_t IFEE11:1; - uint32_t IFEE10:1; - uint32_t IFEE9:1; - uint32_t IFEE8:1; - uint32_t IFEE7:1; - uint32_t IFEE6:1; - uint32_t IFEE5:1; - uint32_t IFEE4:1; - uint32_t IFEE3:1; - uint32_t IFEE2:1; - uint32_t IFEE1:1; - uint32_t IFEE0:1; - } B; - } IFEER; - - union SIU_IDFR_tag { /* External IRQ Digital Filter Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t DFL:4; - } B; - } IDFR; - - int32_t SIU_reserved1[3]; - - union SIU_PCR_tag { /* Pad Configuration Registers */ - uint16_t R; - struct { - uint16_t:3; - uint16_t PA:3; - uint16_t OBE:1; - uint16_t IBE:1; - uint16_t DSC:2; - uint16_t ODE:1; - uint16_t HYS:1; - uint16_t SRC:2; - uint16_t WPE:1; - uint16_t WPS:1; - } B; - } PCR[512]; - - int16_t SIU_reserved_0[224]; - - union { /* GPIO Pin Data Output Registers */ - uint8_t R; - struct { - uint8_t:7; - uint8_t PDO:1; - } B; - } GPDO[256]; - - int32_t SIU_reserved_3[64]; - - union { /* GPIO Pin Data Input Registers */ - uint8_t R; - struct { - uint8_t:7; - uint8_t PDI:1; - } B; - } GPDI[256]; - - union { /* IMUX Register */ - uint32_t R; - struct { - uint32_t TSEL5:2; - uint32_t TSEL4:2; - uint32_t TSEL3:2; - uint32_t TSEL2:2; - uint32_t TSEL1:2; - uint32_t TSEL0:2; - uint32_t:20; - } B; - } ETISR; - - union { /* IMUX Register */ - uint32_t R; - struct { - uint32_t ESEL15:2; - uint32_t ESEL14:2; - uint32_t ESEL13:2; - uint32_t ESEL12:2; - uint32_t ESEL11:2; - uint32_t ESEL10:2; - uint32_t ESEL9:2; - uint32_t ESEL8:2; - uint32_t ESEL7:2; - uint32_t ESEL6:2; - uint32_t ESEL5:2; - uint32_t ESEL4:2; - uint32_t ESEL3:2; - uint32_t ESEL2:2; - uint32_t ESEL1:2; - uint32_t ESEL0:2; - } B; - } EIISR; - - union { /* IMUX Register */ - uint32_t R; - struct { - uint32_t SINSELA:2; - uint32_t SSSELA:2; - uint32_t SCKSELA:2; - uint32_t TRIGSELA:2; - uint32_t SINSELB:2; - uint32_t SSSELB:2; - uint32_t SCKSELB:2; - uint32_t TRIGSELB:2; - uint32_t SINSELC:2; - uint32_t SSSELC:2; - uint32_t SCKSELC:2; - uint32_t TRIGSELC:2; - uint32_t SINSELD:2; - uint32_t SSSELD:2; - uint32_t SCKSELD:2; - uint32_t TRIGSELD:2; - } B; - } DISR; - - int32_t SIU_reserved2[29]; - - union { /* Chip Configuration Register Register */ - uint32_t R; - struct { - uint32_t:14; - uint32_t MATCH:1; - uint32_t DISNEX:1; - uint32_t:16; - } B; - } CCR; - - union { /* External Clock Configuration Register Register */ - uint32_t R; - struct { - uint32_t:18; - uint32_t ENGDIV:6; - uint32_t:4; - uint32_t EBTS:1; - uint32_t:1; - uint32_t EBDF:2; - } B; - } ECCR; - - union { - uint32_t R; - } CARH; - - union { - uint32_t R; - } CARL; - - union { - uint32_t R; - } CBRH; - - union { - uint32_t R; - } CBRL; - - }; -/****************************************************************************/ -/* MODULE : EMIOS */ -/****************************************************************************/ - struct EMIOS_tag { - union EMIOS_MCR_tag { - uint32_t R; - struct { - uint32_t:1; - uint32_t MDIS:1; - uint32_t FRZ:1; - uint32_t GTBE:1; - uint32_t ETB:1; - uint32_t GPREN:1; - uint32_t:6; - uint32_t SRV:4; - uint32_t GPRE:8; - uint32_t:8; - } B; - } MCR; /* Module Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t:8; - uint32_t F23:1; - uint32_t F22:1; - uint32_t F21:1; - uint32_t F20:1; - uint32_t F19:1; - uint32_t F18:1; - uint32_t F17:1; - uint32_t F16:1; - uint32_t F15:1; - uint32_t F14:1; - uint32_t F13:1; - uint32_t F12:1; - uint32_t F11:1; - uint32_t F10:1; - uint32_t F9:1; - uint32_t F8:1; - uint32_t F7:1; - uint32_t F6:1; - uint32_t F5:1; - uint32_t F4:1; - uint32_t F3:1; - uint32_t F2:1; - uint32_t F1:1; - uint32_t F0:1; - } B; - } GFR; /* Global FLAG Register */ - - union { - uint32_t R; - struct { - uint32_t:8; - uint32_t OU23:1; - uint32_t OU22:1; - uint32_t OU21:1; - uint32_t OU20:1; - uint32_t OU19:1; - uint32_t OU18:1; - uint32_t OU17:1; - uint32_t OU16:1; - uint32_t OU15:1; - uint32_t OU14:1; - uint32_t OU13:1; - uint32_t OU12:1; - uint32_t OU11:1; - uint32_t OU10:1; - uint32_t OU9:1; - uint32_t OU8:1; - uint32_t OU7:1; - uint32_t OU6:1; - uint32_t OU5:1; - uint32_t OU4:1; - uint32_t OU3:1; - uint32_t OU2:1; - uint32_t OU1:1; - uint32_t OU0:1; - } B; - } OUDR; /* Output Update Disable Register */ - - uint32_t emios_reserved[5]; - - struct EMIOS_CH_tag { - union { - uint32_t R; /* Channel A Data Register */ - } CADR; - - union { - uint32_t R; /* Channel B Data Register */ - } CBDR; - - union { - uint32_t R; /* Channel Counter Register */ - } CCNTR; - - union EMIOS_CCR_tag { - uint32_t R; - struct { - uint32_t FREN:1; - uint32_t ODIS:1; - uint32_t ODISSL:2; - uint32_t UCPRE:2; - uint32_t UCPREN:1; - uint32_t DMA:1; - uint32_t:1; - uint32_t IF:4; - uint32_t FCK:1; - uint32_t FEN:1; - uint32_t:3; - uint32_t FORCMA:1; - uint32_t FORCMB:1; - uint32_t:1; - uint32_t BSL:2; - uint32_t EDSEL:1; - uint32_t EDPOL:1; - uint32_t MODE:7; - } B; - } CCR; /* Channel Control Register */ - - union EMIOS_CSR_tag { - uint32_t R; - struct { - uint32_t OVR:1; - uint32_t:15; - uint32_t OVFL:1; - uint32_t:12; - uint32_t UCIN:1; - uint32_t UCOUT:1; - uint32_t FLAG:1; - } B; - } CSR; /* Channel Status Register */ - - union { - uint32_t R; /* Alternate Channel A Data Register */ - } ALTCADR; - - uint32_t emios_channel_reserved[2]; - - } CH[24]; - - }; -/****************************************************************************/ -/* MODULE :ETPU */ -/****************************************************************************/ - -/***************************Configuration Registers**************************/ - - struct ETPU_tag { - union { /* MODULE CONFIGURATION REGISTER */ - uint32_t R; - struct { - uint32_t GEC:1; /* Global Exception Clear */ - uint32_t:3; - uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */ - - uint32_t:1; /* For single ETPU implementations */ - - uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */ - - uint32_t:1; /* For single ETPU implementations */ - - uint32_t:3; - uint32_t SCMSIZE:5; /* Shared Code Memory size */ - uint32_t:5; - uint32_t SCMMISF:1; /* SCM MISC Flag */ - uint32_t SCMMISEN:1; /* SCM MISC Enable */ - uint32_t:2; - uint32_t VIS:1; /* SCM Visability */ - uint32_t:5; - uint32_t GTBE:1; /* Global Time Base Enable */ - } B; - } MCR; - - union { /* COHERENT DUAL-PARAMETER CONTROL */ - uint32_t R; - struct { - uint32_t STS:1; /* Start Status bit */ - uint32_t CTBASE:5; /* Channel Transfer Base */ - uint32_t PBASE:10; /* Parameter Buffer Base Address */ - uint32_t PWIDTH:1; /* Parameter Width */ - uint32_t PARAM0:7; /* Channel Parameter 0 */ - uint32_t WR:1; - uint32_t PARAM1:7; /* Channel Parameter 1 */ - } B; - } CDCR; - - uint32_t etpu_reserved1; - - union { /* MISC Compare Register */ - uint32_t R; - } MISCCMPR; - - union { /* SCM off-range Date Register */ - uint32_t R; - } SCMOFFDATAR; - - union { /* ETPU_A Configuration Register */ - uint32_t R; - struct { - uint32_t FEND:1; /* Force END */ - uint32_t MDIS:1; /* Low power Stop */ - uint32_t:1; - uint32_t STF:1; /* Stop Flag */ - uint32_t:4; - uint32_t HLTF:1; /* Halt Mode Flag */ - uint32_t:4; - uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ - uint32_t CDFC:2; - uint32_t:9; - uint32_t ETB:5; /* Entry Table Base */ - } B; - } ECR_A; - uint32_t etpu_reserved3; /* For single ETPU implementations */ - - uint32_t etpu_reserved4; - - union { /* ETPU_A Timebase Configuration Register */ - uint32_t R; - struct { - uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ - uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ - uint32_t:1; - uint32_t AM:1; /* Angle Mode */ - uint32_t:3; - uint32_t TCR2P:6; /* TCR2 Prescaler Control */ - uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ - uint32_t:6; - uint32_t TCR1P:8; /* TCR1 Prescaler Control */ - } B; - } TBCR_A; - - union { /* ETPU_A TCR1 Visibility Register */ - uint32_t R; - } TB1R_A; - - union { /* ETPU_A TCR2 Visibility Register */ - uint32_t R; - } TB2R_A; - - union { /* ETPU_A STAC Configuration Register */ - uint32_t R; - struct { - uint32_t REN1:1; /* Resource Enable TCR1 */ - uint32_t RSC1:1; /* Resource Control TCR1 */ - uint32_t:2; - uint32_t SERVER_ID1:4; - uint32_t:4; - uint32_t SRV1:4; /* Resource Server Slot */ - uint32_t REN2:1; /* Resource Enable TCR2 */ - uint32_t RSC2:1; /* Resource Control TCR2 */ - uint32_t:2; - uint32_t SERVER_ID2:4; - uint32_t:4; - uint32_t SRV2:4; /* Resource Server Slot */ - } B; - } REDCR_A; - - uint32_t etpu_reserved5[4]; - uint32_t etpu_reserved6[4]; /* For single ETPU implementations */ - - uint32_t etpu_reserved7[108]; - -/*****************************Status and Control Registers**************************/ - - union { /* ETPU_A Channel Interrut Status */ - uint32_t R; - struct { - uint32_t CIS31:1; /* Channel 31 Interrut Status */ - uint32_t CIS30:1; /* Channel 30 Interrut Status */ - uint32_t CIS29:1; /* Channel 29 Interrut Status */ - uint32_t CIS28:1; /* Channel 28 Interrut Status */ - uint32_t CIS27:1; /* Channel 27 Interrut Status */ - uint32_t CIS26:1; /* Channel 26 Interrut Status */ - uint32_t CIS25:1; /* Channel 25 Interrut Status */ - uint32_t CIS24:1; /* Channel 24 Interrut Status */ - uint32_t CIS23:1; /* Channel 23 Interrut Status */ - uint32_t CIS22:1; /* Channel 22 Interrut Status */ - uint32_t CIS21:1; /* Channel 21 Interrut Status */ - uint32_t CIS20:1; /* Channel 20 Interrut Status */ - uint32_t CIS19:1; /* Channel 19 Interrut Status */ - uint32_t CIS18:1; /* Channel 18 Interrut Status */ - uint32_t CIS17:1; /* Channel 17 Interrut Status */ - uint32_t CIS16:1; /* Channel 16 Interrut Status */ - uint32_t CIS15:1; /* Channel 15 Interrut Status */ - uint32_t CIS14:1; /* Channel 14 Interrut Status */ - uint32_t CIS13:1; /* Channel 13 Interrut Status */ - uint32_t CIS12:1; /* Channel 12 Interrut Status */ - uint32_t CIS11:1; /* Channel 11 Interrut Status */ - uint32_t CIS10:1; /* Channel 10 Interrut Status */ - uint32_t CIS9:1; /* Channel 9 Interrut Status */ - uint32_t CIS8:1; /* Channel 8 Interrut Status */ - uint32_t CIS7:1; /* Channel 7 Interrut Status */ - uint32_t CIS6:1; /* Channel 6 Interrut Status */ - uint32_t CIS5:1; /* Channel 5 Interrut Status */ - uint32_t CIS4:1; /* Channel 4 Interrut Status */ - uint32_t CIS3:1; /* Channel 3 Interrut Status */ - uint32_t CIS2:1; /* Channel 2 Interrut Status */ - uint32_t CIS1:1; /* Channel 1 Interrut Status */ - uint32_t CIS0:1; /* Channel 0 Interrut Status */ - } B; - } CISR_A; - uint32_t etpu_reserved8; /* For single ETPU implementations */ - - uint32_t etpu_reserved9[2]; - - union { /* ETPU_A Data Transfer Request Status */ - uint32_t R; - struct { - uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ - uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ - uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ - uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ - uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ - uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ - uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ - uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ - uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ - uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ - uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ - uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ - uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ - uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ - uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ - uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ - uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ - uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ - uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ - uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ - uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ - uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ - uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ - uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ - uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ - uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ - uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ - uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ - uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ - uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ - uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ - uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ - } B; - } CDTRSR_A; - uint32_t etpu_reserved10; /* For single ETPU implementations */ - - uint32_t etpu_reserved11[2]; - - union { /* ETPU_A Interruput Overflow Status */ - uint32_t R; - struct { - uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ - uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ - uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ - uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ - uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ - uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ - uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ - uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ - uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ - uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ - uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ - uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ - uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ - uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ - uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ - uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ - uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ - uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ - uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ - uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ - uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ - uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ - uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ - uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ - uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ - uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ - uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ - uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ - uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ - uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ - uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ - uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ - } B; - } CIOSR_A; - uint32_t etpu_reserved12; /* For single ETPU implementations */ - - uint32_t etpu_reserved13[2]; - - union { /* ETPU_A Data Transfer Overflow Status */ - uint32_t R; - struct { - uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ - uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ - uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ - uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ - uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ - uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ - uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ - uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ - uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ - uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ - uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ - uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ - uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ - uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ - uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ - uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ - uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ - uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ - uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ - uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ - uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ - uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ - uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ - uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ - uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ - uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ - uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ - uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ - uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ - uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ - uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ - uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ - } B; - } CDTROSR_A; - uint32_t etpu_reserved14; /* For single ETPU implementations */ - - uint32_t etpu_reserved15[2]; - - union { /* ETPU_A Channel Interruput Enable */ - uint32_t R; - struct { - uint32_t CIE31:1; /* Channel 31 Interruput Enable */ - uint32_t CIE30:1; /* Channel 30 Interruput Enable */ - uint32_t CIE29:1; /* Channel 29 Interruput Enable */ - uint32_t CIE28:1; /* Channel 28 Interruput Enable */ - uint32_t CIE27:1; /* Channel 27 Interruput Enable */ - uint32_t CIE26:1; /* Channel 26 Interruput Enable */ - uint32_t CIE25:1; /* Channel 25 Interruput Enable */ - uint32_t CIE24:1; /* Channel 24 Interruput Enable */ - uint32_t CIE23:1; /* Channel 23 Interruput Enable */ - uint32_t CIE22:1; /* Channel 22 Interruput Enable */ - uint32_t CIE21:1; /* Channel 21 Interruput Enable */ - uint32_t CIE20:1; /* Channel 20 Interruput Enable */ - uint32_t CIE19:1; /* Channel 19 Interruput Enable */ - uint32_t CIE18:1; /* Channel 18 Interruput Enable */ - uint32_t CIE17:1; /* Channel 17 Interruput Enable */ - uint32_t CIE16:1; /* Channel 16 Interruput Enable */ - uint32_t CIE15:1; /* Channel 15 Interruput Enable */ - uint32_t CIE14:1; /* Channel 14 Interruput Enable */ - uint32_t CIE13:1; /* Channel 13 Interruput Enable */ - uint32_t CIE12:1; /* Channel 12 Interruput Enable */ - uint32_t CIE11:1; /* Channel 11 Interruput Enable */ - uint32_t CIE10:1; /* Channel 10 Interruput Enable */ - uint32_t CIE9:1; /* Channel 9 Interruput Enable */ - uint32_t CIE8:1; /* Channel 8 Interruput Enable */ - uint32_t CIE7:1; /* Channel 7 Interruput Enable */ - uint32_t CIE6:1; /* Channel 6 Interruput Enable */ - uint32_t CIE5:1; /* Channel 5 Interruput Enable */ - uint32_t CIE4:1; /* Channel 4 Interruput Enable */ - uint32_t CIE3:1; /* Channel 3 Interruput Enable */ - uint32_t CIE2:1; /* Channel 2 Interruput Enable */ - uint32_t CIE1:1; /* Channel 1 Interruput Enable */ - uint32_t CIE0:1; /* Channel 0 Interruput Enable */ - } B; - } CIER_A; - uint32_t etpu_reserved16; /* For single ETPU implementations */ - - uint32_t etpu_reserved17[2]; - - union { /* ETPU_A Channel Data Transfer Request Enable */ - uint32_t R; - struct { - uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ - uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ - uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ - uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ - uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ - uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ - uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ - uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ - uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ - uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ - uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ - uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ - uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ - uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ - uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ - uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ - uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ - uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ - uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ - uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ - uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ - uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ - uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ - uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ - uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ - uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ - uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ - uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ - uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ - uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ - uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ - uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CDTRER_A; - uint32_t etpu_reserved19; /* For single ETPU implementations */ - - uint32_t etpu_reserved20[10]; - union { /* ETPU_A Channel Pending Service Status */ - uint32_t R; - struct { - uint32_t SR31:1; /* Channel 31 Pending Service Status */ - uint32_t SR30:1; /* Channel 30 Pending Service Status */ - uint32_t SR29:1; /* Channel 29 Pending Service Status */ - uint32_t SR28:1; /* Channel 28 Pending Service Status */ - uint32_t SR27:1; /* Channel 27 Pending Service Status */ - uint32_t SR26:1; /* Channel 26 Pending Service Status */ - uint32_t SR25:1; /* Channel 25 Pending Service Status */ - uint32_t SR24:1; /* Channel 24 Pending Service Status */ - uint32_t SR23:1; /* Channel 23 Pending Service Status */ - uint32_t SR22:1; /* Channel 22 Pending Service Status */ - uint32_t SR21:1; /* Channel 21 Pending Service Status */ - uint32_t SR20:1; /* Channel 20 Pending Service Status */ - uint32_t SR19:1; /* Channel 19 Pending Service Status */ - uint32_t SR18:1; /* Channel 18 Pending Service Status */ - uint32_t SR17:1; /* Channel 17 Pending Service Status */ - uint32_t SR16:1; /* Channel 16 Pending Service Status */ - uint32_t SR15:1; /* Channel 15 Pending Service Status */ - uint32_t SR14:1; /* Channel 14 Pending Service Status */ - uint32_t SR13:1; /* Channel 13 Pending Service Status */ - uint32_t SR12:1; /* Channel 12 Pending Service Status */ - uint32_t SR11:1; /* Channel 11 Pending Service Status */ - uint32_t SR10:1; /* Channel 10 Pending Service Status */ - uint32_t SR9:1; /* Channel 9 Pending Service Status */ - uint32_t SR8:1; /* Channel 8 Pending Service Status */ - uint32_t SR7:1; /* Channel 7 Pending Service Status */ - uint32_t SR6:1; /* Channel 6 Pending Service Status */ - uint32_t SR5:1; /* Channel 5 Pending Service Status */ - uint32_t SR4:1; /* Channel 4 Pending Service Status */ - uint32_t SR3:1; /* Channel 3 Pending Service Status */ - uint32_t SR2:1; /* Channel 2 Pending Service Status */ - uint32_t SR1:1; /* Channel 1 Pending Service Status */ - uint32_t SR0:1; /* Channel 0 Pending Service Status */ - } B; - } CPSSR_A; - uint32_t etpu_reserved22; /* For single ETPU implementations */ - - uint32_t etpu_reserved20a[2]; - - union { /* ETPU_A Channel Service Status */ - uint32_t R; - struct { - uint32_t SS31:1; /* Channel 31 Service Status */ - uint32_t SS30:1; /* Channel 30 Service Status */ - uint32_t SS29:1; /* Channel 29 Service Status */ - uint32_t SS28:1; /* Channel 28 Service Status */ - uint32_t SS27:1; /* Channel 27 Service Status */ - uint32_t SS26:1; /* Channel 26 Service Status */ - uint32_t SS25:1; /* Channel 25 Service Status */ - uint32_t SS24:1; /* Channel 24 Service Status */ - uint32_t SS23:1; /* Channel 23 Service Status */ - uint32_t SS22:1; /* Channel 22 Service Status */ - uint32_t SS21:1; /* Channel 21 Service Status */ - uint32_t SS20:1; /* Channel 20 Service Status */ - uint32_t SS19:1; /* Channel 19 Service Status */ - uint32_t SS18:1; /* Channel 18 Service Status */ - uint32_t SS17:1; /* Channel 17 Service Status */ - uint32_t SS16:1; /* Channel 16 Service Status */ - uint32_t SS15:1; /* Channel 15 Service Status */ - uint32_t SS14:1; /* Channel 14 Service Status */ - uint32_t SS13:1; /* Channel 13 Service Status */ - uint32_t SS12:1; /* Channel 12 Service Status */ - uint32_t SS11:1; /* Channel 11 Service Status */ - uint32_t SS10:1; /* Channel 10 Service Status */ - uint32_t SS9:1; /* Channel 9 Service Status */ - uint32_t SS8:1; /* Channel 8 Service Status */ - uint32_t SS7:1; /* Channel 7 Service Status */ - uint32_t SS6:1; /* Channel 6 Service Status */ - uint32_t SS5:1; /* Channel 5 Service Status */ - uint32_t SS4:1; /* Channel 4 Service Status */ - uint32_t SS3:1; /* Channel 3 Service Status */ - uint32_t SS2:1; /* Channel 2 Service Status */ - uint32_t SS1:1; /* Channel 1 Service Status */ - uint32_t SS0:1; /* Channel 0 Service Status */ - } B; - } CSSR_A; - uint32_t etpu_reserved22a; /* For single ETPU implementations */ - - uint32_t etpu_reserved23[90]; - -/*****************************Channels********************************/ - - struct { - union { - uint32_t R; /* Channel Configuration Register */ - struct { - uint32_t CIE:1; /* Channel Interruput Enable */ - uint32_t DTRE:1; /* Data Transfer Request Enable */ - uint32_t CPR:2; /* Channel Priority */ - uint32_t:3; - uint32_t ETCS:1; /* Entry Table Condition Select */ - uint32_t:3; - uint32_t CFS:5; /* Channel Function Select */ - uint32_t ODIS:1; /* Output disable */ - uint32_t OPOL:1; /* output polarity */ - uint32_t:3; - uint32_t CPBA:11; /* Channel Parameter Base Address */ - } B; - } CR; - union { - uint32_t R; /* Channel Status Control Register */ - struct { - uint32_t CIS:1; /* Channel Interruput Status */ - uint32_t CIOS:1; /* Channel Interruput Overflow Status */ - uint32_t:6; - uint32_t DTRS:1; /* Data Transfer Status */ - uint32_t DTROS:1; /* Data Transfer Overflow Status */ - uint32_t:6; - uint32_t IPS:1; /* Input Pin State */ - uint32_t OPS:1; /* Output Pin State */ - uint32_t OBE:1; /* Output Buffer Enable */ - uint32_t:11; - uint32_t FM1:1; /* Function mode */ - uint32_t FM0:1; /* Function mode */ - } B; - } SCR; - union { - uint32_t R; /* Channel Host Service Request Register */ - struct { - uint32_t:29; /* Host Service Request */ - uint32_t HSR:3; - } B; - } HSRR; - uint32_t etpu_reserved23; - } CHAN[127]; - - }; -/****************************************************************************/ -/* MODULE : XBAR CrossBar */ -/****************************************************************************/ - struct XBAR_tag { - union { - uint32_t R; - struct { - uint32_t:4; - - uint32_t:1; - uint32_t MSTR6:3; /* FLEXRAY */ - - uint32_t:4; - - uint32_t:4; - - uint32_t:1; - uint32_t MSTR3:3; /* FEC */ - - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:3; - } B; - } MPR0; /* Master Priority Register for Slave Port 0 */ - - uint32_t xbar_reserved1[3]; - - union { - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR0; /* General Purpose Control Register for Slave Port 0 */ - - uint32_t xbar_reserved2[59]; - - union { - uint32_t R; - struct { - uint32_t:4; - - uint32_t:1; - uint32_t MSTR6:3; /* FLEXRAY */ - - uint32_t:4; - - uint32_t:4; - - uint32_t:1; - uint32_t MSTR3:3; /* FEC */ - - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:3; - } B; - } MPR1; /* Master Priority Register for Slave Port 1 */ - - uint32_t xbar_reserved3[3]; - - union { - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR1; /* General Purpose Control Register for Slave Port 1 */ - - uint32_t xbar_reserved4[123]; - - union { - uint32_t R; - struct { - uint32_t:4; - - uint32_t:1; - uint32_t MSTR6:3; /* FLEXRAY */ - - uint32_t:4; - - uint32_t:4; - - uint32_t:1; - uint32_t MSTR3:3; /* FEC */ - - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:3; - } B; - } MPR3; /* Master Priority Register for Slave Port 3 */ - - uint32_t xbar_reserved5[3]; - - union { - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR3; /* General Purpose Control Register for Slave Port 3 */ - uint32_t xbar_reserved6[187]; - - union { - uint32_t R; - struct { - uint32_t:4; - - uint32_t:1; - uint32_t MSTR6:3; /* FLEXRAY */ - - uint32_t:4; - - uint32_t:4; - - uint32_t:1; - uint32_t MSTR3:3; /* FEC */ - - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:3; - } B; - } MPR6; /* Master Priority Register for Slave Port 6 */ - - uint32_t xbar_reserved7[3]; - - union { - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR6; /* General Purpose Control Register for Slave Port 6 */ - - uint32_t xbar_reserved8[59]; - - union { - uint32_t R; - struct { - uint32_t:4; - - uint32_t:1; - uint32_t MSTR6:3; /* FLEXRAY */ - - uint32_t:4; - - uint32_t:4; - - uint32_t:1; - uint32_t MSTR3:3; /* FEC */ - - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:3; - } B; - } MPR7; /* Master Priority Register for Slave Port 7 */ - - uint32_t xbar_reserved9[3]; - - union { - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR7; /* General Purpose Control Register for Slave Port 7 */ - - }; -/****************************************************************************/ -/* MODULE : ECSM */ -/****************************************************************************/ - struct ECSM_tag { - - uint32_t ecsm_reserved1[5]; - - uint16_t ecsm_reserved2; - - union { - uint16_t R; - } SWTCR; //Software Watchdog Timer Control - - uint8_t ecsm_reserved3[3]; - - union { - uint8_t R; - } SWTSR; //SWT Service Register - - uint8_t ecsm_reserved4[3]; - - union { - uint8_t R; - } SWTIR; //SWT Interrupt Register - - uint32_t ecsm_reserved5a[1]; - - union { - uint32_t R; - struct { - uint32_t FSBCR0:1; - uint32_t FSBCR1:1; - uint32_t FSBCR2:1; - uint32_t FSBCR3:1; - uint32_t FSBCR4:1; - uint32_t FSBCR5:1; - uint32_t FSBCR6:1; - uint32_t FSBCR7:1; - uint32_t RBEN:1; - uint32_t WBEN:1; - uint32_t ACCERR:1; - uint32_t:21; - } B; - } FSBMCR; /* FEC System Bus Master Control Register */ - - uint32_t ecsm_reserved5c[6]; - - uint8_t ecsm_reserved6[3]; - - union { - uint8_t R; - struct { - uint8_t:6; - uint8_t ERNCR:1; - uint8_t EFNCR:1; - } B; - } ECR; //ECC Configuration Register - - uint8_t mcm_reserved8[3]; - - union { - uint8_t R; - struct { - uint8_t:6; - uint8_t RNCE:1; - uint8_t FNCE:1; - } B; - } ESR; //ECC Status Register - - uint16_t ecsm_reserved9; - - union { - uint16_t R; - struct { - uint16_t:6; - uint16_t FRCNCI:1; - uint16_t FR1NCI:1; - uint16_t:1; - uint16_t ERRBIT:7; - } B; - } EEGR; //ECC Error Generation Register - - uint32_t ecsm_reserved10; - - union { - uint32_t R; - struct { - uint32_t FEAR:32; - } B; - } FEAR; //Flash ECC Address Register - - uint16_t ecsm_reserved11; - - union { - uint8_t R; - struct { - uint8_t:4; - uint8_t FEMR:4; - } B; - } FEMR; //Flash ECC Master Register - - union { - uint8_t R; - struct { - uint8_t WRITE:1; - uint8_t SIZE:3; - uint8_t PROT0:1; - uint8_t PROT1:1; - uint8_t PROT2:1; - uint8_t PROT3:1; - } B; - } FEAT; //Flash ECC Attributes Register - - union { - uint32_t R; - struct { - uint32_t FEDH:32; - } B; - } FEDRH; //Flash ECC Data High Register - - union { - uint32_t R; - struct { - uint32_t FEDL:32; - } B; - } FEDRL; //Flash ECC Data Low Register - - union { - uint32_t R; - struct { - uint32_t REAR:32; - } B; - } REAR; //RAM ECC Address - - uint8_t ecsm_reserved12[2]; - - union { - uint8_t R; - struct { - uint8_t:4; - uint8_t REMR:4; - } B; - } REMR; //RAM ECC Master - - union { - uint8_t R; - struct { - uint8_t WRITE:1; - uint8_t SIZE:3; - uint8_t PROT0:1; - uint8_t PROT1:1; - uint8_t PROT2:1; - uint8_t PROT3:1; - } B; - } REAT; // RAM ECC Attributes Register - - union { - uint32_t R; - struct { - uint32_t REDH:32; - } B; - } REDRH; //RAM ECC Data High Register - - union { - uint32_t R; - struct { - uint32_t REDL:32; - } B; - } REDRL; //RAMECC Data Low Register - - }; -/****************************************************************************/ -/* MODULE : INTC */ -/****************************************************************************/ - struct INTC_tag { - union { - uint32_t R; - struct { - uint32_t:26; - uint32_t VTES:1; - uint32_t:4; - uint32_t HVEN:1; - } B; - } MCR; /* Module Configuration Register */ - - int32_t INTC_reserved00; - - union { - uint32_t R; - struct { - uint32_t:28; - uint32_t PRI:4; - } B; - } CPR; /* Current Priority Register */ - - uint32_t intc_reserved1; - - union { - uint32_t R; - struct { - uint32_t VTBA:21; - uint32_t INTVEC:9; - uint32_t:2; - } B; - } IACKR; /* Interrupt Acknowledge Register */ - - uint32_t intc_reserved2; - - union { - uint32_t R; - struct { - uint32_t:32; - } B; - } EOIR; /* End of Interrupt Register */ - - uint32_t intc_reserved3; - - union { - uint8_t R; - struct { - uint8_t:6; - uint8_t SET:1; - uint8_t CLR:1; - } B; - } SSCIR[8]; /* Software Set/Clear Interruput Register */ - - uint32_t intc_reserved4[6]; - - union { - uint8_t R; - struct { - uint8_t:4; - uint8_t PRI:4; - } B; - } PSR[358]; /* Software Set/Clear Interrupt Register */ - - }; -/****************************************************************************/ -/* MODULE : EQADC */ -/****************************************************************************/ - struct EQADC_tag { - union { - uint32_t R; - struct { - uint32_t:27; - uint32_t ESSIE:2; - uint32_t:1; - uint32_t DBG:2; - } B; - } MCR; /* Module Configuration Register */ - - int32_t EQADC_reserved00; - - union { - uint32_t R; - struct { - uint32_t:6; - uint32_t NMF:26; - } B; - } NMSFR; /* Null Message Send Format Register */ - - union { - uint32_t R; - struct { - uint32_t:28; - uint32_t DFL:4; - } B; - } ETDFR; /* External Trigger Digital Filter Register */ - - union { - uint32_t R; - struct { - uint32_t CFPUSH:32; - } B; - } CFPR[6]; /* CFIFO Push Registers */ - - uint32_t eqadc_reserved1; - - uint32_t eqadc_reserved2; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t RFPOP:16; - } B; - } RFPR[6]; /* Result FIFO Pop Registers */ - - uint32_t eqadc_reserved3; - - uint32_t eqadc_reserved4; - - union { - uint16_t R; - struct { - uint16_t:5; - uint16_t SSE:1; - uint16_t CFINV:1; - uint16_t:1; - uint16_t MODE:4; - uint16_t:4; - } B; - } CFCR[6]; /* CFIFO Control Registers */ - - uint32_t eqadc_reserved5; - - union { - uint16_t R; - struct { - uint16_t NCIE:1; - uint16_t TORIE:1; - uint16_t PIE:1; - uint16_t EOQIE:1; - uint16_t CFUIE:1; - uint16_t:1; - uint16_t CFFE:1; - uint16_t CFFS:1; - uint16_t:4; - uint16_t RFOIE:1; - uint16_t:1; - uint16_t RFDE:1; - uint16_t RFDS:1; - } B; - } IDCR[6]; /* Interrupt and DMA Control Registers */ - - uint32_t eqadc_reserved6; - - union { - uint32_t R; - struct { - uint32_t NCF:1; - uint32_t TORF:1; - uint32_t PF:1; - uint32_t EOQF:1; - uint32_t CFUF:1; - uint32_t SSS:1; - uint32_t CFFF:1; - uint32_t:5; - uint32_t RFOF:1; - uint32_t:1; - uint32_t RFDF:1; - uint32_t:1; - uint32_t CFCTR:4; - uint32_t TNXTPTR:4; - uint32_t RFCTR:4; - uint32_t POPNXTPTR:4; - } B; - } FISR[6]; /* FIFO and Interrupt Status Registers */ - - uint32_t eqadc_reserved7; - - uint32_t eqadc_reserved8; - - union { - uint16_t R; - struct { - uint16_t:5; - uint16_t TCCF:11; - } B; - } CFTCR[6]; /* CFIFO Transfer Counter Registers */ - - uint32_t eqadc_reserved9; - - union { - uint32_t R; - struct { - uint32_t CFS0:2; - uint32_t CFS1:2; - uint32_t CFS2:2; - uint32_t CFS3:2; - uint32_t CFS4:2; - uint32_t CFS5:2; - uint32_t:5; - uint32_t LCFTCB0:4; - uint32_t TC_LCFTCB0:11; - } B; - } CFSSR0; /* CFIFO Status Register 0 */ - - union { - uint32_t R; - struct { - uint32_t CFS0:2; - uint32_t CFS1:2; - uint32_t CFS2:2; - uint32_t CFS3:2; - uint32_t CFS4:2; - uint32_t CFS5:2; - uint32_t:5; - uint32_t LCFTCB1:4; - uint32_t TC_LCFTCB1:11; - } B; - } CFSSR1; /* CFIFO Status Register 1 */ - - union { - uint32_t R; - struct { - uint32_t CFS0:2; - uint32_t CFS1:2; - uint32_t CFS2:2; - uint32_t CFS3:2; - uint32_t CFS4:2; - uint32_t CFS5:2; - uint32_t:4; - uint32_t ECBNI:1; - uint32_t LCFTSSI:4; - uint32_t TC_LCFTSSI:11; - } B; - } CFSSR2; /* CFIFO Status Register 2 */ - - union { - uint32_t R; - struct { - uint32_t CFS0:2; - uint32_t CFS1:2; - uint32_t CFS2:2; - uint32_t CFS3:2; - uint32_t CFS4:2; - uint32_t CFS5:2; - uint32_t:20; - } B; - } CFSR; - - uint32_t eqadc_reserved11; - - union { - uint32_t R; - struct { - uint32_t:21; - uint32_t MDT:3; - uint32_t:4; - uint32_t BR:4; - } B; - } SSICR; /* SSI Control Register */ - - union { - uint32_t R; - struct { - uint32_t RDV:1; - uint32_t:5; - uint32_t RDATA:26; - } B; - } SSIRDR; /* SSI Recieve Data Register */ - - uint32_t eqadc_reserved12[17]; - - struct { - union { - uint32_t R; - struct { - uint32_t:32; - } B; - } R[4]; - - uint32_t eqadc_reserved13[12]; - - } CF[6]; - - uint32_t eqadc_reserved14[32]; - - struct { - union { - uint32_t R; - struct { - uint32_t:32; - } B; - } R[4]; - - uint32_t eqadc_reserved15[12]; - - } RF[6]; - - }; -/****************************************************************************/ -/* MODULE : DSPI */ -/****************************************************************************/ - struct DSPI_tag { - union DSPI_MCR_tag { - uint32_t R; - struct { - uint32_t MSTR:1; - uint32_t CONT_SCKE:1; - uint32_t DCONF:2; - uint32_t FRZ:1; - uint32_t MTFE:1; - uint32_t PCSSE:1; - uint32_t ROOE:1; - uint32_t:2; - uint32_t PCSIS5:1; - uint32_t PCSIS4:1; - uint32_t PCSIS3:1; - uint32_t PCSIS2:1; - uint32_t PCSIS1:1; - uint32_t PCSIS0:1; - uint32_t DOZE:1; - uint32_t MDIS:1; - uint32_t DIS_TXF:1; - uint32_t DIS_RXF:1; - uint32_t CLR_TXF:1; - uint32_t CLR_RXF:1; - uint32_t SMPL_PT:2; - uint32_t:7; - uint32_t HALT:1; - } B; - } MCR; /* Module Configuration Register */ - - uint32_t dspi_reserved1; - - union { - uint32_t R; - struct { - uint32_t TCNT:16; - uint32_t:16; - } B; - } TCR; - - union DSPI_CTAR_tag { - uint32_t R; - struct { - uint32_t DBR:1; - uint32_t FMSZ:4; - uint32_t CPOL:1; - uint32_t CPHA:1; - uint32_t LSBFE:1; - uint32_t PCSSCK:2; - uint32_t PASC:2; - uint32_t PDT:2; - uint32_t PBR:2; - uint32_t CSSCK:4; - uint32_t ASC:4; - uint32_t DT:4; - uint32_t BR:4; - } B; - } CTAR[8]; /* Clock and Transfer Attributes Registers */ - - union DSPI_SR_tag { - uint32_t R; - struct { - uint32_t TCF:1; - uint32_t TXRXS:1; - uint32_t:1; - uint32_t EOQF:1; - uint32_t TFUF:1; - uint32_t:1; - uint32_t TFFF:1; - uint32_t:5; - uint32_t RFOF:1; - uint32_t:1; - uint32_t RFDF:1; - uint32_t:1; - uint32_t TXCTR:4; - uint32_t TXNXTPTR:4; - uint32_t RXCTR:4; - uint32_t POPNXTPTR:4; - } B; - } SR; /* Status Register */ - - union DSPI_RSER_tag { - uint32_t R; - struct { - uint32_t TCFRE:1; - uint32_t:2; - uint32_t EOQFRE:1; - uint32_t TFUFRE:1; - uint32_t:1; - uint32_t TFFFRE:1; - uint32_t TFFFDIRS:1; - uint32_t:4; - uint32_t RFOFRE:1; - uint32_t:1; - uint32_t RFDFRE:1; - uint32_t RFDFDIRS:1; - uint32_t:16; - } B; - } RSER; /* DMA/Interrupt Request Select and Enable Register */ - - union DSPI_PUSHR_tag { - uint32_t R; - struct { - uint32_t CONT:1; - uint32_t CTAS:3; - uint32_t EOQ:1; - uint32_t CTCNT:1; - uint32_t:4; - uint32_t PCS5:1; - uint32_t PCS4:1; - uint32_t PCS3:1; - uint32_t PCS2:1; - uint32_t PCS1:1; - uint32_t PCS0:1; - uint32_t TXDATA:16; - } B; - } PUSHR; /* PUSH TX FIFO Register */ - - union DSPI_POPR_tag { - uint32_t R; - struct { - uint32_t:16; - uint32_t RXDATA:16; - } B; - } POPR; /* POP RX FIFO Register */ - - union { - uint32_t R; - struct { - uint32_t TXCMD:16; - uint32_t TXDATA:16; - } B; - } TXFR[4]; /* Transmit FIFO Registers */ - - uint32_t DSPI_reserved_txf[12]; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t RXDATA:16; - } B; - } RXFR[4]; /* Transmit FIFO Registers */ - - uint32_t DSPI_reserved_rxf[12]; - - union { - uint32_t R; - struct { - uint32_t MTOE:1; - uint32_t:1; - uint32_t MTOCNT:6; - uint32_t:4; - uint32_t TXSS:1; - uint32_t TPOL:1; - uint32_t TRRE:1; - uint32_t CID:1; - uint32_t DCONT:1; - uint32_t DSICTAS:3; - uint32_t:6; - uint32_t DPCS5:1; - uint32_t DPCS4:1; - uint32_t DPCS3:1; - uint32_t DPCS2:1; - uint32_t DPCS1:1; - uint32_t DPCS0:1; - } B; - } DSICR; /* DSI Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t SER_DATA:16; - } B; - } SDR; /* DSI Serialization Data Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t ASER_DATA:16; - } B; - } ASDR; /* DSI Alternate Serialization Data Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t COMP_DATA:16; - } B; - } COMPR; /* DSI Transmit Comparison Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t DESER_DATA:16; - } B; - } DDR; /* DSI deserialization Data Register */ - - }; -/****************************************************************************/ -/* MODULE : eSCI */ -/****************************************************************************/ - struct ESCI_tag { - union ESCI_CR1_tag { - uint32_t R; - struct { - uint32_t:3; - uint32_t SBR:13; - uint32_t LOOPS:1; - uint32_t SCISDOZ:1; - uint32_t RSRC:1; - uint32_t M:1; - uint32_t WAKE:1; - uint32_t ILT:1; - uint32_t PE:1; - uint32_t PT:1; - uint32_t TIE:1; - uint32_t TCIE:1; - uint32_t RIE:1; - uint32_t ILIE:1; - uint32_t TE:1; - uint32_t RE:1; - uint32_t RWU:1; - uint32_t SBK:1; - } B; - } CR1; /* Control Register 1 */ - - union ESCI_CR2_tag { - uint16_t R; - struct { - uint16_t MDIS:1; - uint16_t FBR:1; - uint16_t BSTP:1; - uint16_t IEBERR:1; - uint16_t RXDMA:1; - uint16_t TXDMA:1; - uint16_t BRK13:1; - uint16_t:1; - uint16_t BESM13:1; - uint16_t SBSTP:1; - uint16_t:2; - uint16_t ORIE:1; - uint16_t NFIE:1; - uint16_t FEIE:1; - uint16_t PFIE:1; - } B; - } CR2; /* Control Register 2 */ - - union ESCI_DR_tag { - uint16_t R; - struct { - uint16_t R8:1; - uint16_t T8:1; - uint16_t:6; - uint8_t D; - } B; - } DR; /* Data Register */ - - union ESCI_SR_tag { - uint32_t R; - struct { - uint32_t TDRE:1; - uint32_t TC:1; - uint32_t RDRF:1; - uint32_t IDLE:1; - uint32_t OR:1; - uint32_t NF:1; - uint32_t FE:1; - uint32_t PF:1; - uint32_t:3; - uint32_t BERR:1; - uint32_t:3; - uint32_t RAF:1; - uint32_t RXRDY:1; - uint32_t TXRDY:1; - uint32_t LWAKE:1; - uint32_t STO:1; - uint32_t PBERR:1; - uint32_t CERR:1; - uint32_t CKERR:1; - uint32_t FRC:1; - uint32_t:7; - uint32_t OVFL:1; - } B; - } SR; /* Status Register */ - - union { - uint32_t R; - struct { - uint32_t LRES:1; - uint32_t WU:1; - uint32_t WUD0:1; - uint32_t WUD1:1; - uint32_t LDBG:1; - uint32_t DSF:1; - uint32_t PRTY:1; - uint32_t LIN:1; - uint32_t RXIE:1; - uint32_t TXIE:1; - uint32_t WUIE:1; - uint32_t STIE:1; - uint32_t PBIE:1; - uint32_t CIE:1; - uint32_t CKIE:1; - uint32_t FCIE:1; - uint32_t:7; - uint32_t OFIE:1; - uint32_t:8; - } B; - } LCR; /* LIN Control Register */ - - union { - uint32_t R; - } LTR; /* LIN Transmit Register */ - - union { - uint32_t R; - } LRR; /* LIN Recieve Register */ - - union { - uint32_t R; - } LPR; /* LIN CRC Polynom Register */ - - }; -/****************************************************************************/ -/* MODULE : FlexCAN */ -/****************************************************************************/ - struct FLEXCAN2_tag { - union { - uint32_t R; - struct { - uint32_t MDIS:1; - uint32_t FRZ:1; - uint32_t:1; - uint32_t HALT:1; - uint32_t NOTRDY:1; - uint32_t:1; - uint32_t SOFTRST:1; - uint32_t FRZACK:1; - uint32_t:1; - uint32_t:1; - - uint32_t WRNEN:1; - - uint32_t MDISACK:1; - uint32_t:1; - uint32_t:1; - - uint32_t SRXDIS:1; - uint32_t MBFEN:1; - uint32_t:10; - - uint32_t MAXMB:6; - } B; - } MCR; /* Module Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t PRESDIV:8; - uint32_t RJW:2; - uint32_t PSEG1:3; - uint32_t PSEG2:3; - uint32_t BOFFMSK:1; - uint32_t ERRMSK:1; - uint32_t CLKSRC:1; - uint32_t LPB:1; - - uint32_t TWRNMSK:1; - uint32_t RWRNMSK:1; - uint32_t:2; - - uint32_t SMP:1; - uint32_t BOFFREC:1; - uint32_t TSYN:1; - uint32_t LBUF:1; - uint32_t LOM:1; - uint32_t PROPSEG:3; - } B; - } CR; /* Control Register */ - - union { - uint32_t R; - } TIMER; /* Free Running Timer */ - int32_t FLEXCAN_reserved00; - - union { - uint32_t R; - struct { - uint32_t:3; - uint32_t MI:29; - } B; - } RXGMASK; /* RX Global Mask */ - - union { - uint32_t R; - struct { - uint32_t:3; - uint32_t MI:29; - } B; - } RX14MASK; /* RX 14 Mask */ - - union { - uint32_t R; - struct { - uint32_t:3; - uint32_t MI:29; - } B; - } RX15MASK; /* RX 15 Mask */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t RXECNT:8; - uint32_t TXECNT:8; - } B; - } ECR; /* Error Counter Register */ - - union { - uint32_t R; - struct { - uint32_t:14; - - uint32_t TWRNINT:1; - uint32_t RWRNINT:1; - - uint32_t BIT1ERR:1; - uint32_t BIT0ERR:1; - uint32_t ACKERR:1; - uint32_t CRCERR:1; - uint32_t FRMERR:1; - uint32_t STFERR:1; - uint32_t TXWRN:1; - uint32_t RXWRN:1; - uint32_t IDLE:1; - uint32_t TXRX:1; - uint32_t FLTCONF:2; - uint32_t:1; - uint32_t BOFFINT:1; - uint32_t ERRINT:1; - uint32_t:1; - } B; - } ESR; /* Error and Status Register */ - - union { - uint32_t R; - struct { - uint32_t BUF63M:1; - uint32_t BUF62M:1; - uint32_t BUF61M:1; - uint32_t BUF60M:1; - uint32_t BUF59M:1; - uint32_t BUF58M:1; - uint32_t BUF57M:1; - uint32_t BUF56M:1; - uint32_t BUF55M:1; - uint32_t BUF54M:1; - uint32_t BUF53M:1; - uint32_t BUF52M:1; - uint32_t BUF51M:1; - uint32_t BUF50M:1; - uint32_t BUF49M:1; - uint32_t BUF48M:1; - uint32_t BUF47M:1; - uint32_t BUF46M:1; - uint32_t BUF45M:1; - uint32_t BUF44M:1; - uint32_t BUF43M:1; - uint32_t BUF42M:1; - uint32_t BUF41M:1; - uint32_t BUF40M:1; - uint32_t BUF39M:1; - uint32_t BUF38M:1; - uint32_t BUF37M:1; - uint32_t BUF36M:1; - uint32_t BUF35M:1; - uint32_t BUF34M:1; - uint32_t BUF33M:1; - uint32_t BUF32M:1; - } B; - } IMRH; /* Interruput Masks Register */ - - union { - uint32_t R; - struct { - uint32_t BUF31M:1; - uint32_t BUF30M:1; - uint32_t BUF29M:1; - uint32_t BUF28M:1; - uint32_t BUF27M:1; - uint32_t BUF26M:1; - uint32_t BUF25M:1; - uint32_t BUF24M:1; - uint32_t BUF23M:1; - uint32_t BUF22M:1; - uint32_t BUF21M:1; - uint32_t BUF20M:1; - uint32_t BUF19M:1; - uint32_t BUF18M:1; - uint32_t BUF17M:1; - uint32_t BUF16M:1; - uint32_t BUF15M:1; - uint32_t BUF14M:1; - uint32_t BUF13M:1; - uint32_t BUF12M:1; - uint32_t BUF11M:1; - uint32_t BUF10M:1; - uint32_t BUF09M:1; - uint32_t BUF08M:1; - uint32_t BUF07M:1; - uint32_t BUF06M:1; - uint32_t BUF05M:1; - uint32_t BUF04M:1; - uint32_t BUF03M:1; - uint32_t BUF02M:1; - uint32_t BUF01M:1; - uint32_t BUF00M:1; - } B; - } IMRL; /* Interruput Masks Register */ - - union { - uint32_t R; - struct { - uint32_t BUF63I:1; - uint32_t BUF62I:1; - uint32_t BUF61I:1; - uint32_t BUF60I:1; - uint32_t BUF59I:1; - uint32_t BUF58I:1; - uint32_t BUF57I:1; - uint32_t BUF56I:1; - uint32_t BUF55I:1; - uint32_t BUF54I:1; - uint32_t BUF53I:1; - uint32_t BUF52I:1; - uint32_t BUF51I:1; - uint32_t BUF50I:1; - uint32_t BUF49I:1; - uint32_t BUF48I:1; - uint32_t BUF47I:1; - uint32_t BUF46I:1; - uint32_t BUF45I:1; - uint32_t BUF44I:1; - uint32_t BUF43I:1; - uint32_t BUF42I:1; - uint32_t BUF41I:1; - uint32_t BUF40I:1; - uint32_t BUF39I:1; - uint32_t BUF38I:1; - uint32_t BUF37I:1; - uint32_t BUF36I:1; - uint32_t BUF35I:1; - uint32_t BUF34I:1; - uint32_t BUF33I:1; - uint32_t BUF32I:1; - } B; - } IFRH; /* Interruput Flag Register */ - - union { - uint32_t R; - struct { - uint32_t BUF31I:1; - uint32_t BUF30I:1; - uint32_t BUF29I:1; - uint32_t BUF28I:1; - uint32_t BUF27I:1; - uint32_t BUF26I:1; - uint32_t BUF25I:1; - uint32_t BUF24I:1; - uint32_t BUF23I:1; - uint32_t BUF22I:1; - uint32_t BUF21I:1; - uint32_t BUF20I:1; - uint32_t BUF19I:1; - uint32_t BUF18I:1; - uint32_t BUF17I:1; - uint32_t BUF16I:1; - uint32_t BUF15I:1; - uint32_t BUF14I:1; - uint32_t BUF13I:1; - uint32_t BUF12I:1; - uint32_t BUF11I:1; - uint32_t BUF10I:1; - uint32_t BUF09I:1; - uint32_t BUF08I:1; - uint32_t BUF07I:1; - uint32_t BUF06I:1; - uint32_t BUF05I:1; - uint32_t BUF04I:1; - uint32_t BUF03I:1; - uint32_t BUF02I:1; - uint32_t BUF01I:1; - uint32_t BUF00I:1; - } B; - } IFRL; /* Interruput Flag Register */ - - uint32_t flexcan2_reserved2[19]; - - struct canbuf_t { - union { - uint32_t R; - struct { - uint32_t:4; - uint32_t CODE:4; - uint32_t:1; - uint32_t SRR:1; - uint32_t IDE:1; - uint32_t RTR:1; - uint32_t LENGTH:4; - uint32_t TIMESTAMP:16; - } B; - } CS; - - union { - uint32_t R; - struct { - uint32_t:3; - uint32_t STD_ID:11; - uint32_t EXT_ID:18; - } B; - } ID; - - union { - uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ - uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ - uint32_t W[2]; /* Data buffer in words (32 bits) */ - uint32_t R[2]; /* Data buffer in words (32 bits) */ - } DATA; - - } BUF[64]; - - uint32_t flexcan2_reserved3[256]; - - union { - uint32_t R; - struct { - uint32_t:3; - uint32_t MI:29; - } B; - } RXIMR[64]; /* RX Individual Mask Registers */ - - }; -/****************************************************************************/ -/* MODULE : FEC */ -/****************************************************************************/ - struct FEC_tag { - - uint32_t fec_reserved_start[0x1]; - - union { - uint32_t R; - struct { - uint32_t HBERR:1; - uint32_t BABR:1; - uint32_t BABT:1; - uint32_t GRA:1; - uint32_t TXF:1; - uint32_t TXB:1; - uint32_t RXF:1; - uint32_t RXB:1; - uint32_t MII:1; - uint32_t EBERR:1; - uint32_t LC:1; - uint32_t RL:1; - uint32_t UN:1; - uint32_t:19; - } B; - } EIR; /* Interrupt Event Register */ - - union { - uint32_t R; - struct { - uint32_t HBERRM:1; - uint32_t BABRM:1; - uint32_t BABTM:1; - uint32_t GRAM:1; - uint32_t TXFM:1; - uint32_t TXBM:1; - uint32_t RXFM:1; - uint32_t RXBM:1; - uint32_t MIIM:1; - uint32_t EBERRM:1; - uint32_t LCM:1; - uint32_t RLM:1; - uint32_t UNM:1; - uint32_t:19; - } B; - } EIMR; /* Interrupt Mask Register */ - - uint32_t fec_reserved_eimr; - - union { - uint32_t R; - struct { - uint32_t:7; - uint32_t R_DES_ACTIVE:1; - uint32_t:24; - } B; - } RDAR; /* Receive Descriptor Active Register */ - - union { - uint32_t R; - struct { - uint32_t:7; - uint32_t X_DES_ACTIVE:1; - uint32_t:24; - } B; - } TDAR; /* Transmit Descriptor Active Register */ - - uint32_t fec_reserved_tdar[3]; - - union { - uint32_t R; - struct { - uint32_t:30; - uint32_t ETHER_EN:1; - uint32_t RESET:1; - } B; - } ECR; /* Ethernet Control Register */ - - uint32_t fec_reserved_ecr[6]; - - union { - uint32_t R; - struct { - uint32_t ST:2; - uint32_t CP:2; - uint32_t PA:5; - uint32_t RA:5; - uint32_t TA:2; - uint32_t DATA:16; - } B; - } MDATA; /* MII Data Register */ - - union { - uint32_t R; - struct { - uint32_t:24; - uint32_t DIS_PREAMBLE:1; - uint32_t MII_SPEED:6; - uint32_t:1; - } B; - } MSCR; /* MII Speed Control Register */ - - uint32_t fec_reserved_mscr[7]; - - union { - uint32_t R; - struct { - uint32_t MIB_DISABLE:1; - uint32_t MIB_IDLE:1; - uint32_t:30; - } B; - } MIBC; /* MIB Control Register */ - - uint32_t fec_reserved_mibc[7]; - - union { - uint32_t R; - struct { - uint32_t:5; - uint32_t MAX_FL:11; - uint32_t:10; - uint32_t FCE:1; - uint32_t BC_REJ:1; - uint32_t PROM:1; - uint32_t MII_MODE:1; - uint32_t DRT:1; - uint32_t LOOP:1; - } B; - } RCR; /* Receive Control Register */ - - uint32_t fec_reserved_rcr[15]; - - union { - uint32_t R; - struct { - uint32_t:27; - uint32_t RFC_PAUSE:1; - uint32_t TFC_PAUSE:1; - uint32_t FDEN:1; - uint32_t HBC:1; - uint32_t GTS:1; - } B; - } TCR; /* Transmit Control Register */ - - uint32_t fec_reserved_tcr[7]; - - union { - uint32_t R; - struct { - uint32_t PADDR1:32; - } B; - } PALR; /* Physical Address Low Register */ - - union { - uint32_t R; - struct { - uint32_t PADDR2:16; - uint32_t TYPE:16; - } B; - } PAUR; /* Physical Address High + Type Register */ - - union { - uint32_t R; - struct { - uint32_t OPCODE:16; - uint32_t PAUSE_DUR:16; - } B; - } OPD; /* Opcode/Pause Duration Register */ - - uint32_t fec_reserved_opd[10]; - - union { - uint32_t R; - struct { - uint32_t IADDR1:32; - } B; - } IAUR; /* Descriptor Individual Upper Address Register */ - - union { - uint32_t R; - struct { - uint32_t IADDR2:32; - } B; - } IALR; /* Descriptor Individual Lower Address Register */ - - union { - uint32_t R; - struct { - uint32_t GADDR1:32; - } B; - } GAUR; /* Descriptor Group Upper Address Register */ - - union { - uint32_t R; - struct { - uint32_t GADDR2:32; - } B; - } GALR; /* Descriptor Group Lower Address Register */ - - uint32_t fec_reserved_galr[7]; - - union { - uint32_t R; - struct { - uint32_t:30; - uint32_t X_WMRK:2; - } B; - } TFWR; /* FIFO Transmit FIFO Watermark Register */ - - uint32_t fec_reserved_tfwr; - - union { - uint32_t R; - struct { - uint32_t:22; - uint32_t R_BOUND:8; - uint32_t:2; - } B; - } FRBR; /* FIFO Receive Bound Register */ - - union { - uint32_t R; - struct { - uint32_t:22; - uint32_t R_FSTART:8; - uint32_t:2; - } B; - } FRSR; /* FIFO Receive Start Register */ - - uint32_t fec_reserved_frsr[11]; - - union { - uint32_t R; - struct { - uint32_t R_DES_START:30; - uint32_t:2; - } B; - } ERDSR; /* Receive Descriptor Ring Start Register */ - - union { - uint32_t R; - struct { - uint32_t X_DES_START:30; - uint32_t:2; - } B; - } ETDSR; /* Transmit Descriptor Ring Start Register */ - - union { - uint32_t R; - struct { - uint32_t:21; - uint32_t R_BUF_SIZE:7; - uint32_t:4; - } B; - } EMRBR; /* Receive Buffer Size Register */ - - uint32_t fec_reserved_emrbr[29]; - - union { - uint32_t R; - } RMON_T_DROP; /* Count of frames not counted correctly */ - - union { - uint32_t R; - } RMON_T_PACKETS; /* RMON Tx packet count */ - - union { - uint32_t R; - } RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */ - - union { - uint32_t R; - } RMON_T_MC_PKT; /* RMON Tx Multicast Packets */ - - union { - uint32_t R; - } RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */ - - union { - uint32_t R; - } RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */ - - union { - uint32_t R; - } RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */ - - union { - uint32_t R; - } RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */ - - union { - uint32_t R; - } RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */ - - union { - uint32_t R; - } RMON_T_COL; /* RMON Tx collision count */ - - union { - uint32_t R; - } RMON_T_P64; /* RMON Tx 64 byte packets */ - - union { - uint32_t R; - } RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */ - - union { - uint32_t R; - } RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */ - - union { - uint32_t R; - } RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */ - - union { - uint32_t R; - } RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */ - - union { - uint32_t R; - } RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */ - - union { - uint32_t R; - } RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */ - - union { - uint32_t R; - } RMON_T_OCTETS; /* RMON Tx Octets */ - - union { - uint32_t R; - } IEEE_T_DROP; /* Count of frames not counted correctly */ - - union { - uint32_t R; - } IEEE_T_FRAME_OK; /* Frames Transmitted OK */ - - union { - uint32_t R; - } IEEE_T_1COL; /* Frames Transmitted with Single Collision */ - - union { - uint32_t R; - } IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */ - - union { - uint32_t R; - } IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */ - - union { - uint32_t R; - } IEEE_T_LCOL; /* Frames Transmitted with Late Collision */ - - union { - uint32_t R; - } IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */ - - union { - uint32_t R; - } IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */ - - union { - uint32_t R; - } IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */ - - union { - uint32_t R; - } IEEE_T_SQE; /* Frames Transmitted with SQE Error */ - - union { - uint32_t R; - } IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */ - - union { - uint32_t R; - } IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */ - - uint32_t fec_reserved_rmon_t_octets_ok[2]; - - union { - uint32_t R; - } RMON_R_DROP; /* Count of frames not counted correctly */ - - union { - uint32_t R; - } RMON_R_PACKETS; /* RMON Rx packet count */ - - union { - uint32_t R; - } RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */ - - union { - uint32_t R; - } RMON_R_MC_PKT; /* RMON Rx Multicast Packets */ - - union { - uint32_t R; - } RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */ - - union { - uint32_t R; - } RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */ - - union { - uint32_t R; - } RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */ - - union { - uint32_t R; - } RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */ - - union { - uint32_t R; - } RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */ - - uint32_t fec_reserved_rmon_r_jab; - - union { - uint32_t R; - } RMON_R_P64; /* RMON Rx 64 byte packets */ - - union { - uint32_t R; - } RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */ - - union { - uint32_t R; - } RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */ - - union { - uint32_t R; - } RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */ - - union { - uint32_t R; - } RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */ - - union { - uint32_t R; - } RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */ - - union { - uint32_t R; - } RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */ - - union { - uint32_t R; - } RMON_R_OCTETS; /* RMON Rx Octets */ - - union { - uint32_t R; - } IEEE_R_DROP; /* Count of frames not counted correctly */ - - union { - uint32_t R; - } IEEE_R_FRAME_OK; /* Frames Received OK */ - - union { - uint32_t R; - } IEEE_R_CRC; /* Frames Received with CRC Error */ - - union { - uint32_t R; - } IEEE_R_ALIGN; /* Frames Received with Alignment Error */ - - union { - uint32_t R; - } IEEE_R_MACERR; /* Receive Fifo Overflow count */ - - union { - uint32_t R; - } IEEE_R_FDXFC; /* Flow Control Pause frames received */ - - union { - uint32_t R; - } IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */ - - }; -/****************************************************************************/ -/* MODULE : FlexRay */ -/****************************************************************************/ - - typedef union uMVR { - uint16_t R; - struct { - uint16_t CHIVER:8; /* CHI Version Number */ - uint16_t PEVER:8; /* PE Version Number */ - } B; - } MVR_t; - - typedef union uMCR { - uint16_t R; - struct { - uint16_t MEN:1; /* module enable */ - uint16_t:1; - uint16_t SCMD:1; /* single channel mode */ - uint16_t CHB:1; /* channel B enable */ - uint16_t CHA:1; /* channel A enable */ - uint16_t SFFE:1; /* synchronization frame filter enable */ - uint16_t:5; - uint16_t CLKSEL:1; /* protocol engine clock source select */ - uint16_t PRESCALE:3; /* protocol engine clock prescaler */ - uint16_t:1; - } B; - } MCR_t; - typedef union uSTBSCR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t STBSSEL:7; /* strobe signal select */ - uint16_t:3; - uint16_t ENB:1; /* strobe signal enable */ - uint16_t:2; - uint16_t STBPSEL:2; /* strobe port select */ - } B; - } STBSCR_t; - typedef union uSTBPCR { - uint16_t R; - struct { - uint16_t:12; - uint16_t STB3EN:1; /* strobe port enable */ - uint16_t STB2EN:1; /* strobe port enable */ - uint16_t STB1EN:1; /* strobe port enable */ - uint16_t STB0EN:1; /* strobe port enable */ - } B; - } STBPCR_t; - - typedef union uMBDSR { - uint16_t R; - struct { - uint16_t:1; - uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ - uint16_t:1; - uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ - } B; - } MBDSR_t; - typedef union uMBSSUTR { - uint16_t R; - struct { - - uint16_t:1; - uint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */ - uint16_t:1; - uint16_t LAST_MB_UTIL:7; /* last message buffer utilized */ - } B; - } MBSSUTR_t; - - typedef union uPOCR { - uint16_t R; - uint8_t byte[2]; - struct { - uint16_t WME:1; /* write mode external correction command */ - uint16_t:3; - uint16_t EOC_AP:2; /* external offset correction application */ - uint16_t ERC_AP:2; /* external rate correction application */ - uint16_t BSY:1; /* command write busy / write mode command */ - uint16_t:3; - uint16_t POCCMD:4; /* protocol command */ - } B; - } POCR_t; -/* protocol commands */ - typedef union uGIFER { - uint16_t R; - struct { - uint16_t MIF:1; /* module interrupt flag */ - uint16_t PRIF:1; /* protocol interrupt flag */ - uint16_t CHIF:1; /* CHI interrupt flag */ - uint16_t WKUPIF:1; /* wakeup interrupt flag */ - uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ - uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ - uint16_t RBIF:1; /* receive message buffer interrupt flag */ - uint16_t TBIF:1; /* transmit buffer interrupt flag */ - uint16_t MIE:1; /* module interrupt enable */ - uint16_t PRIE:1; /* protocol interrupt enable */ - uint16_t CHIE:1; /* CHI interrupt enable */ - uint16_t WKUPIE:1; /* wakeup interrupt enable */ - uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ - uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ - uint16_t RBIE:1; /* receive message buffer interrupt enable */ - uint16_t TBIE:1; /* transmit buffer interrupt enable */ - } B; - } GIFER_t; - typedef union uPIFR0 { - uint16_t R; - struct { - uint16_t FATLIF:1; /* fatal protocol error interrupt flag */ - uint16_t INTLIF:1; /* internal protocol error interrupt flag */ - uint16_t ILCFIF:1; /* illegal protocol configuration flag */ - uint16_t CSAIF:1; /* cold start abort interrupt flag */ - uint16_t MRCIF:1; /* missing rate correctio interrupt flag */ - uint16_t MOCIF:1; /* missing offset correctio interrupt flag */ - uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ - uint16_t MXSIF:1; /* max sync frames detected interrupt flag */ - uint16_t MTXIF:1; /* media access test symbol received flag */ - uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ - uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ - uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ - uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ - uint16_t TI2IF:1; /* timer 2 expired interrupt flag */ - uint16_t TI1IF:1; /* timer 1 expired interrupt flag */ - uint16_t CYSIF:1; /* cycle start interrupt flag */ - } B; - } PIFR0_t; - typedef union uPIFR1 { - uint16_t R; - struct { - uint16_t EMCIF:1; /* error mode changed interrupt flag */ - uint16_t IPCIF:1; /* illegal protocol command interrupt flag */ - uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ - uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ - uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ - uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ - uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ - uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ - uint16_t:2; - uint16_t EVTIF:1; /* even cycle table written interrupt flag */ - uint16_t ODTIF:1; /* odd cycle table written interrupt flag */ - uint16_t:4; - } B; - } PIFR1_t; - typedef union uPIER0 { - uint16_t R; - struct { - uint16_t FATLIE:1; /* fatal protocol error interrupt enable */ - uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ - uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ - uint16_t CSAIE:1; /* cold start abort interrupt enable */ - uint16_t MRCIE:1; /* missing rate correctio interrupt enable */ - uint16_t MOCIE:1; /* missing offset correctio interrupt enable */ - uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ - uint16_t MXSIE:1; /* max sync frames detected interrupt enable */ - uint16_t MTXIE:1; /* media access test symbol received interrupt enable */ - uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ - uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ - uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ - uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ - uint16_t TI2IE:1; /* timer 2 expired interrupt enable */ - uint16_t TI1IE:1; /* timer 1 expired interrupt enable */ - uint16_t CYSIE:1; /* cycle start interrupt enable */ - } B; - } PIER0_t; - typedef union uPIER1 { - uint16_t R; - struct { - uint16_t EMCIE:1; /* error mode changed interrupt enable */ - uint16_t IPCIE:1; /* illegal protocol command interrupt enable */ - uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ - uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ - uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ - uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ - uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ - uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ - uint16_t:2; - uint16_t EVTIE:1; /* even cycle table written interrupt enable */ - uint16_t ODTIE:1; /* odd cycle table written interrupt enable */ - uint16_t:4; - } B; - } PIER1_t; - typedef union uCHIERFR { - uint16_t R; - struct { - uint16_t FRLBEF:1; /* flame lost channel B error flag */ - uint16_t FRLAEF:1; /* frame lost channel A error flag */ - uint16_t PCMIEF:1; /* command ignored error flag */ - uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ - uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ - uint16_t MSBEF:1; /* message buffer search error flag */ - uint16_t MBUEF:1; /* message buffer utilization error flag */ - uint16_t LCKEF:1; /* lock error flag */ - uint16_t DBLEF:1; /* double transmit message buffer lock error flag */ - uint16_t SBCFEF:1; /* system bus communication failure error flag */ - uint16_t FIDEF:1; /* frame ID error flag */ - uint16_t DPLEF:1; /* dynamic payload length error flag */ - uint16_t SPLEF:1; /* static payload length error flag */ - uint16_t NMLEF:1; /* network management length error flag */ - uint16_t NMFEF:1; /* network management frame error flag */ - uint16_t ILSAEF:1; /* illegal access error flag */ - } B; - } CHIERFR_t; - typedef union uMBIVEC { - uint16_t R; - struct { - - uint16_t:1; - uint16_t TBIVEC:7; /* transmit buffer interrupt vector */ - uint16_t:1; - uint16_t RBIVEC:7; /* receive buffer interrupt vector */ - } B; - } MBIVEC_t; - - typedef union uPSR0 { - uint16_t R; - struct { - uint16_t ERRMODE:2; /* error mode */ - uint16_t SLOTMODE:2; /* slot mode */ - uint16_t:1; - uint16_t PROTSTATE:3; /* protocol state */ - uint16_t SUBSTATE:4; /* protocol sub state */ - uint16_t:1; - uint16_t WAKEUPSTATUS:3; /* wakeup status */ - } B; - } PSR0_t; - -/* protocol states */ -/* protocol sub-states */ -/* wakeup status */ - typedef union uPSR1 { - uint16_t R; - struct { - uint16_t CSAA:1; /* cold start attempt abort flag */ - uint16_t SCP:1; /* cold start path */ - uint16_t:1; - uint16_t REMCSAT:5; /* remanining coldstart attempts */ - uint16_t CPN:1; /* cold start noise path */ - uint16_t HHR:1; /* host halt request pending */ - uint16_t FRZ:1; /* freeze occured */ - uint16_t APTAC:5; /* allow passive to active counter */ - } B; - } PSR1_t; - typedef union uPSR2 { - uint16_t R; - struct { - uint16_t NBVB:1; /* NIT boundary violation on channel B */ - uint16_t NSEB:1; /* NIT syntax error on channel B */ - uint16_t STCB:1; /* symbol window transmit conflict on channel B */ - uint16_t SBVB:1; /* symbol window boundary violation on channel B */ - uint16_t SSEB:1; /* symbol window syntax error on channel B */ - uint16_t MTB:1; /* media access test symbol MTS received on channel B */ - uint16_t NBVA:1; /* NIT boundary violation on channel A */ - uint16_t NSEA:1; /* NIT syntax error on channel A */ - uint16_t STCA:1; /* symbol window transmit conflict on channel A */ - uint16_t SBVA:1; /* symbol window boundary violation on channel A */ - uint16_t SSEA:1; /* symbol window syntax error on channel A */ - uint16_t MTA:1; /* media access test symbol MTS received on channel A */ - uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ - } B; - } PSR2_t; - typedef union uPSR3 { - uint16_t R; - struct { - uint16_t:2; - uint16_t WUB:1; /* wakeup symbol received on channel B */ - uint16_t ABVB:1; /* aggregated boundary violation on channel B */ - uint16_t AACB:1; /* aggregated additional communication on channel B */ - uint16_t ACEB:1; /* aggregated content error on channel B */ - uint16_t ASEB:1; /* aggregated syntax error on channel B */ - uint16_t AVFB:1; /* aggregated valid frame on channel B */ - uint16_t:2; - uint16_t WUA:1; /* wakeup symbol received on channel A */ - uint16_t ABVA:1; /* aggregated boundary violation on channel A */ - uint16_t AACA:1; /* aggregated additional communication on channel A */ - uint16_t ACEA:1; /* aggregated content error on channel A */ - uint16_t ASEA:1; /* aggregated syntax error on channel A */ - uint16_t AVFA:1; /* aggregated valid frame on channel A */ - } B; - } PSR3_t; - typedef union uCIFRR { - uint16_t R; - struct { - uint16_t:8; - uint16_t MIFR:1; /* module interrupt flag */ - uint16_t PRIFR:1; /* protocol interrupt flag */ - uint16_t CHIFR:1; /* CHI interrupt flag */ - uint16_t WUPIFR:1; /* wakeup interrupt flag */ - uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ - uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ - uint16_t RBIFR:1; /* receive message buffer interrupt flag */ - uint16_t TBIFR:1; /* transmit buffer interrupt flag */ - } B; - } CIFRR_t; - typedef union uSFCNTR { - uint16_t R; - struct { - uint16_t SFEVB:4; /* sync frames channel B, even cycle */ - uint16_t SFEVA:4; /* sync frames channel A, even cycle */ - uint16_t SFODB:4; /* sync frames channel B, odd cycle */ - uint16_t SFODA:4; /* sync frames channel A, odd cycle */ - } B; - } SFCNTR_t; - - typedef union uSFTCCSR { - uint16_t R; - struct { - uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ - uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ - uint16_t CYCNUM:6; /* cycle number */ - uint16_t ELKS:1; /* even cycle tables lock status */ - uint16_t OLKS:1; /* odd cycle tables lock status */ - uint16_t EVAL:1; /* even cycle tables valid */ - uint16_t OVAL:1; /* odd cycle tables valid */ - uint16_t:1; - uint16_t OPT:1; /*one pair trigger */ - uint16_t SDVEN:1; /* sync frame deviation table enable */ - uint16_t SIDEN:1; /* sync frame ID table enable */ - } B; - } SFTCCSR_t; - typedef union uSFIDRFR { - uint16_t R; - struct { - uint16_t:6; - uint16_t SYNFRID:10; /* sync frame rejection ID */ - } B; - } SFIDRFR_t; - - typedef union uTICCR { - uint16_t R; - struct { - uint16_t:2; - uint16_t T2CFG:1; /* timer 2 configuration */ - uint16_t T2REP:1; /* timer 2 repetitive mode */ - uint16_t:1; - uint16_t T2SP:1; /* timer 2 stop */ - uint16_t T2TR:1; /* timer 2 trigger */ - uint16_t T2ST:1; /* timer 2 state */ - uint16_t:3; - uint16_t T1REP:1; /* timer 1 repetitive mode */ - uint16_t:1; - uint16_t T1SP:1; /* timer 1 stop */ - uint16_t T1TR:1; /* timer 1 trigger */ - uint16_t T1ST:1; /* timer 1 state */ - - } B; - } TICCR_t; - typedef union uTI1CYSR { - uint16_t R; - struct { - uint16_t:2; - uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ - uint16_t:2; - uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ - - } B; - } TI1CYSR_t; - - typedef union uSSSR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t:1; - uint16_t SEL:2; /* static slot number */ - uint16_t:1; - uint16_t SLOTNUMBER:11; /* selector */ - } B; - } SSSR_t; - - typedef union uSSCCR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t:1; - uint16_t SEL:2; /* selector */ - uint16_t:1; - uint16_t CNTCFG:2; /* counter configuration */ - uint16_t MCY:1; /* multi cycle selection */ - uint16_t VFR:1; /* valid frame selection */ - uint16_t SYF:1; /* sync frame selection */ - uint16_t NUF:1; /* null frame selection */ - uint16_t SUF:1; /* startup frame selection */ - uint16_t STATUSMASK:4; /* slot status mask */ - } B; - } SSCCR_t; - typedef union uSSR { - uint16_t R; - struct { - uint16_t VFB:1; /* valid frame on channel B */ - uint16_t SYB:1; /* valid sync frame on channel B */ - uint16_t NFB:1; /* valid null frame on channel B */ - uint16_t SUB:1; /* valid startup frame on channel B */ - uint16_t SEB:1; /* syntax error on channel B */ - uint16_t CEB:1; /* content error on channel B */ - uint16_t BVB:1; /* boundary violation on channel B */ - uint16_t TCB:1; /* tx conflict on channel B */ - uint16_t VFA:1; /* valid frame on channel A */ - uint16_t SYA:1; /* valid sync frame on channel A */ - uint16_t NFA:1; /* valid null frame on channel A */ - uint16_t SUA:1; /* valid startup frame on channel A */ - uint16_t SEA:1; /* syntax error on channel A */ - uint16_t CEA:1; /* content error on channel A */ - uint16_t BVA:1; /* boundary violation on channel A */ - uint16_t TCA:1; /* tx conflict on channel A */ - } B; - } SSR_t; - typedef union uMTSCFR { - uint16_t R; - struct { - uint16_t MTE:1; /* media access test symbol transmission enable */ - uint16_t:1; - uint16_t CYCCNTMSK:6; /* cycle counter mask */ - uint16_t:2; - uint16_t CYCCNTVAL:6; /* cycle counter value */ - } B; - } MTSCFR_t; - typedef union uRSBIR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t:1; - uint16_t SEL:2; /* selector */ - uint16_t:4; - uint16_t RSBIDX:8; /* receive shadow buffer index */ - } B; - } RSBIR_t; - typedef union uRFDSR { - uint16_t R; - struct { - uint16_t FIFODEPTH:8; /* fifo depth */ - uint16_t:1; - uint16_t ENTRYSIZE:7; /* entry size */ - } B; - } RFDSR_t; - - typedef union uRFRFCFR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t IBD:1; /* interval boundary */ - uint16_t SEL:2; /* filter number */ - uint16_t:1; - uint16_t SID:11; /* slot ID */ - } B; - } RFRFCFR_t; - - typedef union uRFRFCTR { - uint16_t R; - struct { - uint16_t:4; - uint16_t F3MD:1; /* filter mode */ - uint16_t F2MD:1; /* filter mode */ - uint16_t F1MD:1; /* filter mode */ - uint16_t F0MD:1; /* filter mode */ - uint16_t:4; - uint16_t F3EN:1; /* filter enable */ - uint16_t F2EN:1; /* filter enable */ - uint16_t F1EN:1; /* filter enable */ - uint16_t F0EN:1; /* filter enable */ - } B; - } RFRFCTR_t; - typedef union uPCR0 { - uint16_t R; - struct { - uint16_t ACTION_POINT_OFFSET:6; - uint16_t STATIC_SLOT_LENGTH:10; - } B; - } PCR0_t; - - typedef union uPCR1 { - uint16_t R; - struct { - uint16_t:2; - uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; - } B; - } PCR1_t; - - typedef union uPCR2 { - uint16_t R; - struct { - uint16_t MINISLOT_AFTER_ACTION_POINT:6; - uint16_t NUMBER_OF_STATIC_SLOTS:10; - } B; - } PCR2_t; - - typedef union uPCR3 { - uint16_t R; - struct { - uint16_t WAKEUP_SYMBOL_RX_LOW:6; - uint16_t MINISLOT_ACTION_POINT_OFFSET:5; - uint16_t COLDSTART_ATTEMPTS:5; - } B; - } PCR3_t; - - typedef union uPCR4 { - uint16_t R; - struct { - uint16_t CAS_RX_LOW_MAX:7; - uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; - } B; - } PCR4_t; - - typedef union uPCR5 { - uint16_t R; - struct { - uint16_t TSS_TRANSMITTER:4; - uint16_t WAKEUP_SYMBOL_TX_LOW:6; - uint16_t WAKEUP_SYMBOL_RX_IDLE:6; - } B; - } PCR5_t; - - typedef union uPCR6 { - uint16_t R; - struct { - uint16_t:1; - uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; - uint16_t MACRO_INITIAL_OFFSET_A:7; - } B; - } PCR6_t; - - typedef union uPCR7 { - uint16_t R; - struct { - uint16_t DECODING_CORRECTION_B:9; - uint16_t MICRO_PER_MACRO_NOM_HALF:7; - } B; - } PCR7_t; - - typedef union uPCR8 { - uint16_t R; - struct { - uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; - uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; - uint16_t WAKEUP_SYMBOL_TX_IDLE:8; - } B; - } PCR8_t; - - typedef union uPCR9 { - uint16_t R; - struct { - uint16_t MINISLOT_EXISTS:1; - uint16_t SYMBOL_WINDOW_EXISTS:1; - uint16_t OFFSET_CORRECTION_OUT:14; - } B; - } PCR9_t; - - typedef union uPCR10 { - uint16_t R; - struct { - uint16_t SINGLE_SLOT_ENABLED:1; - uint16_t WAKEUP_CHANNEL:1; - uint16_t MACRO_PER_CYCLE:14; - } B; - } PCR10_t; - - typedef union uPCR11 { - uint16_t R; - struct { - uint16_t KEY_SLOT_USED_FOR_STARTUP:1; - uint16_t KEY_SLOT_USED_FOR_SYNC:1; - uint16_t OFFSET_CORRECTION_START:14; - } B; - } PCR11_t; - - typedef union uPCR12 { - uint16_t R; - struct { - uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; - uint16_t KEY_SLOT_HEADER_CRC:11; - } B; - } PCR12_t; - - typedef union uPCR13 { - uint16_t R; - struct { - uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; - uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; - } B; - } PCR13_t; - - typedef union uPCR14 { - uint16_t R; - struct { - uint16_t RATE_CORRECTION_OUT:11; - uint16_t LISTEN_TIMEOUT_H:5; - } B; - } PCR14_t; - - typedef union uPCR15 { - uint16_t R; - struct { - uint16_t LISTEN_TIMEOUT_L:16; - } B; - } PCR15_t; - - typedef union uPCR16 { - uint16_t R; - struct { - uint16_t MACRO_INITIAL_OFFSET_B:7; - uint16_t NOISE_LISTEN_TIMEOUT_H:9; - } B; - } PCR16_t; - - typedef union uPCR17 { - uint16_t R; - struct { - uint16_t NOISE_LISTEN_TIMEOUT_L:16; - } B; - } PCR17_t; - - typedef union uPCR18 { - uint16_t R; - struct { - uint16_t WAKEUP_PATTERN:6; - uint16_t KEY_SLOT_ID:10; - } B; - } PCR18_t; - - typedef union uPCR19 { - uint16_t R; - struct { - uint16_t DECODING_CORRECTION_A:9; - uint16_t PAYLOAD_LENGTH_STATIC:7; - } B; - } PCR19_t; - - typedef union uPCR20 { - uint16_t R; - struct { - uint16_t MICRO_INITIAL_OFFSET_B:8; - uint16_t MICRO_INITIAL_OFFSET_A:8; - } B; - } PCR20_t; - - typedef union uPCR21 { - uint16_t R; - struct { - uint16_t EXTERN_RATE_CORRECTION:3; - uint16_t LATEST_TX:13; - } B; - } PCR21_t; - - typedef union uPCR22 { - uint16_t R; - struct { - uint16_t:1; - uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; - uint16_t MICRO_PER_CYCLE_H:4; - } B; - } PCR22_t; - - typedef union uPCR23 { - uint16_t R; - struct { - uint16_t micro_per_cycle_l:16; - } B; - } PCR23_t; - - typedef union uPCR24 { - uint16_t R; - struct { - uint16_t CLUSTER_DRIFT_DAMPING:5; - uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; - uint16_t MICRO_PER_CYCLE_MIN_H:4; - } B; - } PCR24_t; - - typedef union uPCR25 { - uint16_t R; - struct { - uint16_t MICRO_PER_CYCLE_MIN_L:16; - } B; - } PCR25_t; - - typedef union uPCR26 { - uint16_t R; - struct { - uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; - uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; - uint16_t MICRO_PER_CYCLE_MAX_H:4; - } B; - } PCR26_t; - - typedef union uPCR27 { - uint16_t R; - struct { - uint16_t MICRO_PER_CYCLE_MAX_L:16; - } B; - } PCR27_t; - - typedef union uPCR28 { - uint16_t R; - struct { - uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; - uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; - } B; - } PCR28_t; - - typedef union uPCR29 { - uint16_t R; - struct { - uint16_t EXTERN_OFFSET_CORRECTION:3; - uint16_t MINISLOTS_MAX:13; - } B; - } PCR29_t; - - typedef union uPCR30 { - uint16_t R; - struct { - uint16_t:12; - uint16_t SYNC_NODE_MAX:4; - } B; - } PCR30_t; - - typedef struct uMSG_BUFF_CCS { - union { - uint16_t R; - struct { - uint16_t:1; - uint16_t MCM:1; /* message buffer commit mode */ - uint16_t MBT:1; /* message buffer type */ - uint16_t MTD:1; /* message buffer direction */ - uint16_t CMT:1; /* commit for transmission */ - uint16_t EDT:1; /* enable / disable trigger */ - uint16_t LCKT:1; /* lock request trigger */ - uint16_t MBIE:1; /* message buffer interrupt enable */ - uint16_t:3; - uint16_t DUP:1; /* data updated */ - uint16_t DVAL:1; /* data valid */ - uint16_t EDS:1; /* lock status */ - uint16_t LCKS:1; /* enable / disable status */ - uint16_t MBIF:1; /* message buffer interrupt flag */ - } B; - } MBCCSR; - union { - uint16_t R; - struct { - uint16_t MTM:1; /* message buffer transmission mode */ - uint16_t CHNLA:1; /* channel assignement */ - uint16_t CHNLB:1; /* channel assignement */ - uint16_t CCFE:1; /* cycle counter filter enable */ - uint16_t CCFMSK:6; /* cycle counter filter mask */ - uint16_t CCFVAL:6; /* cycle counter filter value */ - } B; - } MBCCFR; - union { - uint16_t R; - struct { - uint16_t:5; - uint16_t FID:11; /* frame ID */ - } B; - } MBFIDR; - union { - uint16_t R; - struct { - uint16_t:8; - uint16_t MBIDX:8; /* message buffer index */ - } B; - } MBIDXR; - } MSG_BUFF_CCS_t; - typedef union uSYSBADHR { - uint16_t R; - } SYSBADHR_t; - typedef union uSYSBADLR { - uint16_t R; - } SYSBADLR_t; - typedef union uPDAR { - uint16_t R; - } PDAR_t; - typedef union uCASERCR { - uint16_t R; - } CASERCR_t; - typedef union uCBSERCR { - uint16_t R; - } CBSERCR_t; - typedef union uCYCTR { - uint16_t R; - } CYCTR_t; - typedef union uMTCTR { - uint16_t R; - } MTCTR_t; - typedef union uSLTCTAR { - uint16_t R; - } SLTCTAR_t; - typedef union uSLTCTBR { - uint16_t R; - } SLTCTBR_t; - typedef union uRTCORVR { - uint16_t R; - } RTCORVR_t; - typedef union uOFCORVR { - uint16_t R; - } OFCORVR_t; - typedef union uSFTOR { - uint16_t R; - } SFTOR_t; - typedef union uSFIDAFVR { - uint16_t R; - } SFIDAFVR_t; - typedef union uSFIDAFMR { - uint16_t R; - } SFIDAFMR_t; - typedef union uNMVR { - uint16_t R; - } NMVR_t; - typedef union uNMVLR { - uint16_t R; - } NMVLR_t; - typedef union uT1MTOR { - uint16_t R; - } T1MTOR_t; - typedef union uTI2CR0 { - uint16_t R; - } TI2CR0_t; - typedef union uTI2CR1 { - uint16_t R; - } TI2CR1_t; - typedef union uSSCR { - uint16_t R; - } SSCR_t; - typedef union uRFSR { - uint16_t R; - } RFSR_t; - typedef union uRFSIR { - uint16_t R; - } RFSIR_t; - typedef union uRFARIR { - uint16_t R; - } RFARIR_t; - typedef union uRFBRIR { - uint16_t R; - } RFBRIR_t; - typedef union uRFMIDAFVR { - uint16_t R; - } RFMIDAFVR_t; - typedef union uRFMIAFMR { - uint16_t R; - } RFMIAFMR_t; - typedef union uRFFIDRFVR { - uint16_t R; - } RFFIDRFVR_t; - typedef union uRFFIDRFMR { - uint16_t R; - } RFFIDRFMR_t; - typedef union uLDTXSLAR { - uint16_t R; - } LDTXSLAR_t; - typedef union uLDTXSLBR { - uint16_t R; - } LDTXSLBR_t; - - typedef struct FR_tag { - volatile MVR_t MVR; /*module version register *//*0 */ - volatile MCR_t MCR; /*module configuration register *//*2 */ - volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ - volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ - volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ - volatile STBPCR_t STBPCR; /*strobe port control register *//*A */ - volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ - volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ - uint16_t reserved3a[1]; /*10 */ - volatile PDAR_t PDAR; /*PE data register *//*12 */ - volatile POCR_t POCR; /*Protocol operation control register *//*14 */ - volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ - volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ - volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ - volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ - volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ - volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ - volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ - volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ - volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ - volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ - volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ - volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ - volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ - volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ - volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ - volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ - volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ - volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ - volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ - volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ - uint16_t reserved3[1]; /*3E */ - volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ - volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ - volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ - volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ - volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ - volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ - volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ - volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ - volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ - volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ - volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ - volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ - volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ - volatile SSSR_t SSSR; /*slot status selection register *//*64 */ - volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ - volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ - volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ - volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ - volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ - volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ - volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ - volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ - volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ - volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ - volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ - volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ - volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ - volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ - volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ - volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ - volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ - volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ - volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ - volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ - volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ - volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ - volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ - volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ - volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ - volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ - volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ - volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ - volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ - volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ - volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ - volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ - volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ - volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ - volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ - volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ - volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ - volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ - volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ - volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ - volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ - volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ - volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ - volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ - volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ - volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ - volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ - volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ - volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ - volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ - uint16_t reserved2[17]; - volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ - } FR_tag_t; - - typedef union uF_HEADER /* frame header */ - { - struct { - uint16_t:5; - uint16_t HDCRC:11; /* Header CRC */ - uint16_t:2; - uint16_t CYCCNT:6; /* Cycle Count */ - uint16_t:1; - uint16_t PLDLEN:7; /* Payload Length */ - uint16_t:1; - uint16_t PPI:1; /* Payload Preamble Indicator */ - uint16_t NUF:1; /* Null Frame Indicator */ - uint16_t SYF:1; /* Sync Frame Indicator */ - uint16_t SUF:1; /* Startup Frame Indicator */ - uint16_t FID:11; /* Frame ID */ - } B; - uint16_t WORDS[3]; - } F_HEADER_t; - typedef union uS_STSTUS /* slot status */ - { - struct { - uint16_t VFB:1; /* Valid Frame on channel B */ - uint16_t SYB:1; /* Sync Frame Indicator channel B */ - uint16_t NFB:1; /* Null Frame Indicator channel B */ - uint16_t SUB:1; /* Startup Frame Indicator channel B */ - uint16_t SEB:1; /* Syntax Error on channel B */ - uint16_t CEB:1; /* Content Error on channel B */ - uint16_t BVB:1; /* Boundary Violation on channel B */ - uint16_t CH:1; /* Channel */ - uint16_t VFA:1; /* Valid Frame on channel A */ - uint16_t SYA:1; /* Sync Frame Indicator channel A */ - uint16_t NFA:1; /* Null Frame Indicator channel A */ - uint16_t SUA:1; /* Startup Frame Indicator channel A */ - uint16_t SEA:1; /* Syntax Error on channel A */ - uint16_t CEA:1; /* Content Error on channel A */ - uint16_t BVA:1; /* Boundary Violation on channel A */ - uint16_t:1; - } RX; - struct { - uint16_t VFB:1; /* Valid Frame on channel B */ - uint16_t SYB:1; /* Sync Frame Indicator channel B */ - uint16_t NFB:1; /* Null Frame Indicator channel B */ - uint16_t SUB:1; /* Startup Frame Indicator channel B */ - uint16_t SEB:1; /* Syntax Error on channel B */ - uint16_t CEB:1; /* Content Error on channel B */ - uint16_t BVB:1; /* Boundary Violation on channel B */ - uint16_t TCB:1; /* Tx Conflict on channel B */ - uint16_t VFA:1; /* Valid Frame on channel A */ - uint16_t SYA:1; /* Sync Frame Indicator channel A */ - uint16_t NFA:1; /* Null Frame Indicator channel A */ - uint16_t SUA:1; /* Startup Frame Indicator channel A */ - uint16_t SEA:1; /* Syntax Error on channel A */ - uint16_t CEA:1; /* Content Error on channel A */ - uint16_t BVA:1; /* Boundary Violation on channel A */ - uint16_t TCA:1; /* Tx Conflict on channel A */ - } TX; - uint16_t R; - } S_STATUS_t; - - typedef struct uMB_HEADER /* message buffer header */ - { - F_HEADER_t FRAME_HEADER; - uint16_t DATA_OFFSET; - S_STATUS_t SLOT_STATUS; - } MB_HEADER_t; - -/* Define memories */ - -#define SRAM_START 0x40000000 -#define SRAM_SIZE 0x14000 -#define SRAM_END 0x40013FFF - -#define FLASH_START 0x0 -#define FLASH_SIZE 0x200000 -#define FLASH_END 0x1FFFFF - -/* Define instances of modules */ -#define PBRIDGE_A (*(volatile struct PBRIDGE_A_tag *) 0xC3F00000) -#define FMPLL (*(volatile struct FMPLL_tag *) 0xC3F80000) -#define EBI (*(volatile struct EBI_tag *) 0xC3F84000) -#define FLASH (*(volatile struct FLASH_tag *) 0xC3F88000) -#define SIU (*(volatile struct SIU_tag *) 0xC3F90000) - -#define EMIOS (*(volatile struct EMIOS_tag *) 0xC3FA0000) -#define ETPU (*(volatile struct ETPU_tag *) 0xC3FC0000) -#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) -#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) -#define ETPU_DATA_RAM_END 0xC3FC89FC -#define CODE_RAM (*( uint32_t *) 0xC3FD0000) -#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) - -#define PBRIDGE_B (*(volatile struct PBRIDGE_B_tag *) 0xFFF00000) -#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000) -#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000) -#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000) -#define INTC (*(volatile struct INTC_tag *) 0xFFF48000) - -#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000) - -#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000) -#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000) -#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000) -#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000) - -#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFB0000) -#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFB4000) - -#define CAN_A (*(volatile struct FLEXCAN2_tag *) 0xFFFC0000) -#define CAN_B (*(volatile struct FLEXCAN2_tag *) 0xFFFC4000) -#define CAN_C (*(volatile struct FLEXCAN2_tag *) 0xFFFC8000) -#define CAN_D (*(volatile struct FLEXCAN2_tag *) 0xFFFCC000) -#define CAN_E (*(volatile struct FLEXCAN2_tag *) 0xFFFD0000) - -#define FEC (*(volatile struct FEC_tag *) 0xFFF4C000) - -#define FR (*(volatile struct FR_tag *) 0xFFFE0000) - -#ifdef __MWERKS__ -#pragma pop -#endif - -#ifdef __cplusplus -} -#endif -#endif /* ASM */ -#endif /* ifdef _MPC5567_H */ -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - * - ********************************************************************/ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc564xL.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc564xL.h deleted file mode 100644 index 61217ac656..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc564xL.h +++ /dev/null @@ -1,20666 +0,0 @@ -/* - * Modifications of the original file provided by Freescale Semiconductor and - * ST Microelectronics are: - * - * Copyright (c) 2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/****************************************************************************\ - * PROJECT : MPC5643L - * FILE : mpc5643l.h - * - * DESCRIPTION : This is the header file describing the register - * set for the named projects. - * - * COPYRIGHT : (c) 2009, Freescale Semiconductor & ST Microelectronics - * - * VERSION : 1.04 - * RELEASE DATE : Tue Dec 1 2009 - * CREATION DATE : Thu Oct 8 13:53:51 CEST 2009 - * AUTHOR : generated from IP-XACT database - * HISTORY : Preliminary release. -\****************************************************************************/ - -/* >>>> NOTE! this file is auto-generated please do not edit it! <<<< */ - -/****************************************************************************\ - * Example instantiation and use: - * - * <MODULE>.<REGISTER>.B.<BIT> = 1; - * <MODULE>.<REGISTER>.R = 0x10000000; - * -\****************************************************************************/ - -/* - * LICENSE: - * Copyright (c) 2006 Freescale Semiconductor - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice - * shall be included in all copies or substantial portions - * of the Software. - * - * THIS SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _leopard_H_ /* prevents multiple inclusions of this file */ -#define _leopard_H_ - -#ifndef ASM - -#include <stdint.h> - -#include <mpc55xx/regs-edma.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __MWERKS__ -#pragma push -#pragma ANSI_strict off -#endif - -//#define USE_FIELD_ALIASES_CFLASH -//#define USE_FIELD_ALIASES_SIUL -//#define USE_FIELD_ALIASES_SSCM -//#define USE_FIELD_ALIASES_ME -//#define USE_FIELD_ALIASES_RGM -//#define USE_FIELD_ALIASES_ADC -//#define USE_FIELD_ALIASES_CTU -//#define USE_FIELD_ALIASES_mcTIMER -//#define USE_FIELD_ALIASES_mcPWM -//#define USE_FIELD_ALIASES_LINFLEX -//#define USE_FIELD_ALIASES_SPP_MCM -#define USE_FIELD_ALIASES_INTC -#define USE_FIELD_ALIASES_DSPI -//#define USE_FIELD_ALIASES_FLEXCAN -//#define USE_FIELD_ALIASES_FR -//#define USE_FIELD_ALIASES_CMU -//#define USE_FIELD_ALIASES_PLLD -//#define USE_FIELD_ALIASES_SPP_DMA2 - -/* Define memories */ - -#define SRAM_START 0x40000000 -#define SRAM_SIZE 0x20000 -#define SRAM_END 0x4001FFFF - -#define FLASH_START 0x0 -#define FLASH_SIZE 0xC0000 -#define FLASH_END 0xBFFFF - -/****************************************************************/ -/* */ -/* Global definitions and aliases */ -/* */ -/****************************************************************/ - -/* - Platform blocks that are only accessible by the second core (core 1) when - the device is in DPM mode. The block definition is equivalent to the one - for the first core (core 0) and reuses the related block structure. - - NOTE: the <block_name>_1 defines are the preferred method for programming - */ -#define PBRIDGE_1 (*(volatile PBRIDGE_tag*) 0x8FF00000UL) -#define MAX_1 (*(volatile MAX_tag*) 0x8FF04000UL) -#define MPU_1 (*(volatile MPU_tag*) 0x8FF10000UL) -#define SEMA4_1 (*(volatile SEMA4_tag*) 0x8FF24000UL) -#define SWT_1 (*(volatile SWT_tag*) 0x8FF38000UL) -#define STM_1 (*(volatile STM_tag*) 0x8FF3C000UL) -#define SPP_MCM_1 (*(volatile SPP_MCM_tag*) 0x8FF40000UL) -#define SPP_DMA2_1 (*(volatile SPP_DMA2_tag*) 0x8FF44000UL) -#define INTC_1 (*(volatile INTC_tag*) 0x8FF48000UL) - -/* - Platform blocks that are only accessible by the second core (core 1) when - the device is in DPM mode. The block definition is equivalent to the one - for the first core (core 0) and reuses the related block structure. - - NOTE: the <block_name>_DPM defines are deprecated, use <block_name>_1 for - programming the corresponding blocks for new code instead. - */ -#define PBRIDGE_DPM PBRIDGE_1 -#define MAX_DPM MAX_1 -#define MPU_DPM MPU_1 -#define SEMA4_DPM SEMA4_1 -#define SWT_DPM SWT_1 -#define STM_DPM STM_1 -#define SPP_MCM_DPM SPP_MCM_1 -#define SPP_DMA2_DPM SPP_DMA2_1 -#define INTC_DPM INTC_1 - -/* Aliases for Pictus Module names */ -#define CAN_0 FLEXCAN_A -#define CAN_1 FLEXCAN_B -#define CTU_0 CTU -#define DFLASH CRC -#define DMAMUX DMA_CH_MUX -#define DSPI_0 DSPI_A -#define DSPI_1 DSPI_B -#define DSPI_2 DSPI_C -#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) -#define ETIMER_0 mcTIMER0 -#define ETIMER_1 mcTIMER1 -#define FLEXPWM_0 mcPWM_A -#define FLEXPWM_1 mcPWM_B -#define LINFLEX_0 LINFLEX0 -#define LINFLEX_1 LINFLEX1 -#define MCM_ SPP_MCM -#define PIT PIT_RTI -#define SIU SIUL -#define WKUP WKPU -#define ADC_0 ADC0 -#define ADC_1 ADC1 - -/* Other Aliases */ -#define AIPS_DPM PBRIDGE_1 -#define AIPS_1 PBRIDGE_1 -#define AIPS PBRIDGE - -/****************************************************************/ -/* */ -/* Module: CFLASH_SHADOW */ -/* */ -/****************************************************************/ - - - /* Register layout for all registers NVPWD... */ - - typedef union { /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ - uint32_t R; - struct { - uint32_t PWD:32; /* PassWorD */ - } B; - } CFLASH_SHADOW_NVPWD_32B_tag; - - - /* Register layout for all registers NVSCI... */ - - typedef union { /* NVSCI - Non Volatile System Censoring Information Register */ - uint32_t R; - struct { - uint32_t SC:16; /* Serial Censorship Control Word */ - uint32_t CW:16; /* Censorship Control Word */ - } B; - } CFLASH_SHADOW_NVSCI_32B_tag; - - typedef union { /* Non Volatile LML Default Value */ - uint32_t R; - } CFLASH_SHADOW_NVLML_32B_tag; - - typedef union { /* Non Volatile HBL Default Value */ - uint32_t R; - } CFLASH_SHADOW_NVHBL_32B_tag; - - typedef union { /* Non Volatile SLL Default Value */ - uint32_t R; - } CFLASH_SHADOW_NVSLL_32B_tag; - - - /* Register layout for all registers NVBIU... */ - - typedef union { /* Non Volatile Bus Interface Unit Register */ - uint32_t R; - struct { - uint32_t BI:32; /* Bus interface Unit */ - } B; - } CFLASH_SHADOW_NVBIU_32B_tag; - - typedef union { /* NVUSRO - Non Volatile USeR Options Register */ - uint32_t R; - struct { - uint32_t UO:32; /* User Options */ - } B; - } CFLASH_SHADOW_NVUSRO_32B_tag; - - - typedef struct CFLASH_SHADOW_BIU_DEFAULTS_struct_tag { - - /* Non Volatile Bus Interface Unit Register */ - CFLASH_SHADOW_NVBIU_32B_tag NVBIU; /* relative offset: 0x0000 */ - int8_t CFLASH_SHADOW_BIU_DEFAULTS_reserved_0004[4]; - - } CFLASH_SHADOW_BIU_DEFAULTS_tag; - - - typedef struct CFLASH_SHADOW_struct_tag { /* start of CFLASH_SHADOW_tag */ - int8_t CFLASH_SHADOW_reserved_0000_C[15832]; - union { - /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ - CFLASH_SHADOW_NVPWD_32B_tag NVPWD[2]; /* offset: 0x3DD8 (0x0004 x 2) */ - - struct { - /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ - CFLASH_SHADOW_NVPWD_32B_tag NVPWD0; /* offset: 0x3DD8 size: 32 bit */ - CFLASH_SHADOW_NVPWD_32B_tag NVPWD1; /* offset: 0x3DDC size: 32 bit */ - }; - - }; - union { - /* NVSCI - Non Volatile System Censoring Information Register */ - CFLASH_SHADOW_NVSCI_32B_tag NVSCI[2]; /* offset: 0x3DE0 (0x0004 x 2) */ - - struct { - /* NVSCI - Non Volatile System Censoring Information Register */ - CFLASH_SHADOW_NVSCI_32B_tag NVSCI0; /* offset: 0x3DE0 size: 32 bit */ - CFLASH_SHADOW_NVSCI_32B_tag NVSCI1; /* offset: 0x3DE4 size: 32 bit */ - }; - - }; - /* Non Volatile LML Default Value */ - CFLASH_SHADOW_NVLML_32B_tag NVLML; /* offset: 0x3DE8 size: 32 bit */ - int8_t CFLASH_SHADOW_reserved_3DEC[4]; - /* Non Volatile HBL Default Value */ - CFLASH_SHADOW_NVHBL_32B_tag NVHBL; /* offset: 0x3DF0 size: 32 bit */ - int8_t CFLASH_SHADOW_reserved_3DF4[4]; - /* Non Volatile SLL Default Value */ - CFLASH_SHADOW_NVSLL_32B_tag NVSLL; /* offset: 0x3DF8 size: 32 bit */ - int8_t CFLASH_SHADOW_reserved_3DFC_C[4]; - union { - /* Register set BIU_DEFAULTS */ - CFLASH_SHADOW_BIU_DEFAULTS_tag BIU_DEFAULTS[3]; /* offset: 0x3E00 (0x0008 x 3) */ - - struct { - /* Non Volatile Bus Interface Unit Register */ - CFLASH_SHADOW_NVBIU_32B_tag NVBIU2; /* offset: 0x3E00 size: 32 bit */ - int8_t CFLASH_SHADOW_reserved_3E04_I1[4]; - CFLASH_SHADOW_NVBIU_32B_tag NVBIU3; /* offset: 0x3E08 size: 32 bit */ - int8_t CFLASH_SHADOW_reserved_3E0C_I1[4]; - CFLASH_SHADOW_NVBIU_32B_tag NVBIU4; /* offset: 0x3E10 size: 32 bit */ - int8_t CFLASH_SHADOW_reserved_3E14_E1[4]; - }; - - }; - /* NVUSRO - Non Volatile USeR Options Register */ - CFLASH_SHADOW_NVUSRO_32B_tag NVUSRO; /* offset: 0x3E18 size: 32 bit */ - } CFLASH_SHADOW_tag; - - -#define CFLASH_SHADOW (*(volatile CFLASH_SHADOW_tag *) 0x00F00000UL) - - - -/****************************************************************/ -/* */ -/* Module: CFLASH */ -/* */ -/****************************************************************/ - - typedef union { /* MCR - Module Configuration Register */ - uint32_t R; - struct { - uint32_t:5; - uint32_t SIZE:3; /* Array Space Size */ - uint32_t:1; - uint32_t LAS:3; /* Low Address Space */ - uint32_t:3; - uint32_t MAS:1; /* Mid Address Space Configuration */ - uint32_t EER:1; /* ECC Event Error */ - uint32_t RWE:1; /* Read-while-Write Event Error */ - uint32_t SBC:1; /* Single Bit Correction */ - uint32_t:1; - uint32_t PEAS:1; /* Program/Erase Access Space */ - uint32_t DONE:1; /* modify operation DONE */ - uint32_t PEG:1; /* Program/Erase Good */ - uint32_t:4; - uint32_t PGM:1; /* Program Bit */ - uint32_t PSUS:1; /* Program Suspend */ - uint32_t ERS:1; /* Erase Bit */ - uint32_t ESUS:1; /* Erase Suspend */ - uint32_t EHV:1; /* Enable High Voltage */ - } B; - } CFLASH_MCR_32B_tag; - - typedef union { /* LML - Low/Mid Address Space Block Locking Register */ - uint32_t R; - struct { - uint32_t LME:1; /* Low/Mid Address Space Block Enable */ - uint32_t:10; -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t SLOCK:1; /* Shadow Address Space Block Lock */ -#else - uint32_t TSLK:1; /* deprecated name - please avoid */ -#endif - uint32_t:2; -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t MLOCK:2; /* Mid Address Space Block Lock */ -#else - uint32_t MLK:2; /* deprecated name - please avoid */ -#endif - uint32_t:6; - uint32_t LLOCK:10; /* Low Address Space Block Lock */ - } B; - } CFLASH_LML_32B_tag; - - typedef union { /* HBL - High Address Space Block Locking Register */ - uint32_t R; - struct { - uint32_t HBE:1; /* High Address Space Block Enable */ - uint32_t:25; - uint32_t HLOCK:6; /* High Address Space Block Lock */ - } B; - } CFLASH_HBL_32B_tag; - - typedef union { /* SLL - Secondary Low/Mid Address Space Block Locking Register */ - uint32_t R; - struct { - uint32_t SLE:1; /* Secondary Low/Mid Address Space Block Enable */ - uint32_t:10; -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t SSLOCK:1; /* Secondary Shadow Address Space Block Lock */ -#else - uint32_t STSLK:1; /* deprecated name - please avoid */ -#endif - uint32_t:2; -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t SMLOCK:2; /* Secondary Mid Address Space Block Lock */ -#else - uint32_t SMK:2; /* deprecated name - please avoid */ -#endif - uint32_t:6; - uint32_t SLLOCK:10; /* Secondary Low Address Space Block Lock */ - } B; - } CFLASH_SLL_32B_tag; - - typedef union { /* LMS - Low/Mid Address Space Block Select Register */ - uint32_t R; - struct { - uint32_t:14; - uint32_t MSL:2; /* Mid Address Space Block Select */ - uint32_t:6; - uint32_t LSL:10; /* Low Address Space Block Select */ - } B; - } CFLASH_LMS_32B_tag; - - typedef union { /* HBS - High Address Space Block Select Register */ - uint32_t R; - struct { - uint32_t:26; - uint32_t HSL:6; /* High Address Space Block Select */ - } B; - } CFLASH_HBS_32B_tag; - - typedef union { /* ADR - Address Register */ - uint32_t R; - struct { - uint32_t SAD:1; /* Shadow Address */ - uint32_t:10; - uint32_t ADDR:18; /* Address */ - uint32_t:3; - } B; - } CFLASH_ADR_32B_tag; - - typedef union { /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */ - uint32_t R; - struct { -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_APC:5; /* Bank0+2 Address Pipelining Control */ -#else - uint32_t BK0_APC:5; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_WWSC:5; /* Bank0+2 Write Wait State Control */ -#else - uint32_t BK0_WWSC:5; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_RWSC:5; /* Bank0+2 Read Wait State Control */ -#else - uint32_t BK0_RWSC:5; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_RWWC2:1; /* Bank 0+2 Read While Write Control, bit 2 */ -#else - uint32_t BK0_RWWC2:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_RWWC1:1; /* Bank 0+2 Read While Write Control, bit 1 */ -#else - uint32_t BK0_RWWC1:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_P1_BCFG:2; /* Bank0+2 Port 1 Page Buffer Configuration */ -#else - uint32_t B0_P1_BCFG:2; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_P1_DPFE:1; /* Bank0+2 Port 1 Data Prefetch Enable */ -#else - uint32_t B0_P1_DPFE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_P1_IPFE:1; /* Bank0+2 Port 1 Inst Prefetch Enable */ -#else - uint32_t B0_P1_IPFE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_P1_PFLM:2; /* Bank0+2 Port 1 Prefetch Limit */ -#else - uint32_t B0_P1_PFLM:2; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_P1_BFE:1; /* Bank0+2 Port 1 Buffer Enable */ -#else - uint32_t B0_P1_BFE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_RWWC0:1; /* Bank 0+2 Read While Write Control, bit 0 */ -#else - uint32_t BK0_RWWC0:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_P0_BCFG:2; /* Bank0+2 Port 0 Page Buffer Configuration */ -#else - uint32_t B0_P0_BCFG:2; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_P0_DPFE:1; /* Bank0+2 Port 0 Data Prefetch Enable */ -#else - uint32_t B0_P0_DPFE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_P0_IPFE:1; /* Bank0+2 Port 0 Inst Prefetch Enable */ -#else - uint32_t B0_P0_IPFE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_P0_PFLM:2; /* Bank0+2 Port 0 Prefetch Limit */ -#else - uint32_t B0_P0_PFLM:2; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B02_P0_BFE:1; /* Bank0+2 Port 0 Buffer Enable */ -#else - uint32_t B0_P0_BFE:1; /* deprecated name - please avoid */ -#endif - } B; - } CFLASH_PFCR0_32B_tag; - - - /* Register layout for all registers BIU... */ - - typedef union { /* Bus Interface Unit Register */ - uint32_t R; - } CFLASH_BIU_32B_tag; - - typedef union { /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */ - uint32_t R; - struct { -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t B1_APC:5; /* Bank 1 Address Pipelining Control */ - uint32_t B1_WWSC:5; /* Bank 1 Write Wait State Control */ - uint32_t B1_RWSC:5; /* Bank 1 Read Wait State Control */ - uint32_t B1_RWWC2:1; /* Bank1 Read While Write Control, bit 2 */ - uint32_t B1_RWWC1:1; /* Bank1 Read While Write Control, bit 1 */ - uint32_t:6; - uint32_t B1_P1_BFE:1; /* Bank 1 Port 1 Buffer Enable */ - uint32_t B1_RWWC0:1; /* Bank1 Read While Write Control, bit 0 */ - uint32_t:6; - uint32_t B1_P0_BFE:1; /* Bank 1 Port 0 Buffer Enable */ -#else - uint32_t BK1_APC:5; - uint32_t BK1_WWSC:5; - uint32_t BK1_RWSC:5; - uint32_t BK1_RWWC2:1; - uint32_t BK1_RWWC1:1; - uint32_t:6; - uint32_t B0_P1_BFE:1; - uint32_t BK1_RWWC0:1; - uint32_t:6; - uint32_t B1_P0_BFE:1; -#endif - } B; - } CFLASH_PFCR1_32B_tag; - - typedef union { /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */ - uint32_t R; - struct { - uint32_t:6; - uint32_t ARBM:2; /* Arbitration Mode */ - uint32_t M7PFD:1; /* Master x Prefetch Disable */ - uint32_t M6PFD:1; /* Master x Prefetch Disable */ - uint32_t M5PFD:1; /* Master x Prefetch Disable */ - uint32_t M4PFD:1; /* Master x Prefetch Disable */ - uint32_t M3PFD:1; /* Master x Prefetch Disable */ - uint32_t M2PFD:1; /* Master x Prefetch Disable */ - uint32_t M1PFD:1; /* Master x Prefetch Disable */ - uint32_t M0PFD:1; /* Master x Prefetch Disable */ - uint32_t M7AP:2; /* Master 7 Access Protection */ - uint32_t M6AP:2; /* Master 6 Access Protection */ - uint32_t M5AP:2; /* Master 5 Access Protection */ - uint32_t M4AP:2; /* Master 4 Access Protection */ - uint32_t M3AP:2; /* Master 3 Access Protection */ - uint32_t M2AP:2; /* Master 2 Access Protection */ - uint32_t M1AP:2; /* Master 1 Access Protection */ - uint32_t M0AP:2; /* Master 0 Access Protection */ - } B; - } CFLASH_PFAPR_32B_tag; - - typedef union { /* UT0 - User Test Register */ - uint32_t R; - struct { - uint32_t UTE:1; /* User Test Enable */ - uint32_t SBCE:1; /* Single Bit Correction Enable */ - uint32_t:6; - uint32_t DSI:8; /* Data Syndrome Input */ - uint32_t:10; - uint32_t MRE:1; /* Margin Read Enable */ - uint32_t MRV:1; /* Margin Read Value */ - uint32_t EIE:1; /* ECC Data Input Enable */ - uint32_t AIS:1; /* Array Integrity Sequence */ - uint32_t AIE:1; /* Array Integrity Enable */ - uint32_t AID:1; /* Array Integrity Done */ - } B; - } CFLASH_UT0_32B_tag; - - typedef union { /* UT1 - User Test Register */ - uint32_t R; - } CFLASH_UT1_32B_tag; - - typedef union { /* UT2 - User Test Register */ - uint32_t R; - } CFLASH_UT2_32B_tag; - - - /* Register layout for all registers UM... */ - - typedef union { /* UM - User Multiple Input Signature Register */ - uint32_t R; - struct { -#ifndef USE_FIELD_ALIASES_CFLASH - uint32_t MISR:32; /* Multiple Input Signature */ -#else - uint32_t MS:32; /* deprecated - please avoid */ -#endif - } B; - } CFLASH_UM_32B_tag; - - - /* Register layout for generated register(s) UT... */ - - typedef union { /* */ - uint32_t R; - } CFLASH_UT_32B_tag; - - - /* Register layout for generated register(s) PFCR... */ - - typedef union { /* */ - uint32_t R; - } CFLASH_PFCR_32B_tag; - - - - typedef struct CFLASH_struct_tag { /* start of CFLASH_tag */ - /* MCR - Module Configuration Register */ - CFLASH_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ - /* LML - Low/Mid Address Space Block Locking Register */ - CFLASH_LML_32B_tag LML; /* offset: 0x0004 size: 32 bit */ - /* HBL - High Address Space Block Locking Register */ - CFLASH_HBL_32B_tag HBL; /* offset: 0x0008 size: 32 bit */ - /* SLL - Secondary Low/Mid Address Space Block Locking Register */ - CFLASH_SLL_32B_tag SLL; /* offset: 0x000C size: 32 bit */ - /* LMS - Low/Mid Address Space Block Select Register */ - CFLASH_LMS_32B_tag LMS; /* offset: 0x0010 size: 32 bit */ - /* HBS - High Address Space Block Select Register */ - CFLASH_HBS_32B_tag HBS; /* offset: 0x0014 size: 32 bit */ - /* ADR - Address Register */ - CFLASH_ADR_32B_tag ADR; /* offset: 0x0018 size: 32 bit */ - union { - struct { - /* */ - CFLASH_PFCR_32B_tag PFCR[2]; /* offset: 0x001C (0x0004 x 2) */ - int8_t CFLASH_reserved_0024_E0[12]; - }; - - /* Bus Interface Unit Register */ - CFLASH_BIU_32B_tag BIU[5]; /* offset: 0x001C (0x0004 x 5) */ - - struct { - /* Bus Interface Unit Register */ - CFLASH_BIU_32B_tag BIU0; /* offset: 0x001C size: 32 bit */ - CFLASH_BIU_32B_tag BIU1; /* offset: 0x0020 size: 32 bit */ - CFLASH_BIU_32B_tag BIU2; /* offset: 0x0024 size: 32 bit */ - CFLASH_BIU_32B_tag BIU3; /* offset: 0x0028 size: 32 bit */ - CFLASH_BIU_32B_tag BIU4; /* offset: 0x002C size: 32 bit */ - }; - - struct { - int8_t CFLASH_reserved_001C_I3[8]; - CFLASH_PFAPR_32B_tag FAPR; /* deprecated - please avoid */ - int8_t CFLASH_reserved_0028_E3[8]; - }; - - struct { - /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */ - CFLASH_PFCR0_32B_tag PFCR0; /* offset: 0x001C size: 32 bit */ - /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */ - CFLASH_PFCR1_32B_tag PFCR1; /* offset: 0x0020 size: 32 bit */ - /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */ - CFLASH_PFAPR_32B_tag PFAPR; /* offset: 0x0024 size: 32 bit */ - int8_t CFLASH_reserved_0028_E4[8]; - }; - - }; - int8_t CFLASH_reserved_0030_C[12]; - union { - CFLASH_UT_32B_tag UT[3]; /* offset: 0x003C (0x0004 x 3) */ - - struct { - /* UT0 - User Test Register */ - CFLASH_UT0_32B_tag UT0; /* offset: 0x003C size: 32 bit */ - /* UT1 - User Test Register */ - CFLASH_UT1_32B_tag UT1; /* offset: 0x0040 size: 32 bit */ - /* UT2 - User Test Register */ - CFLASH_UT2_32B_tag UT2; /* offset: 0x0044 size: 32 bit */ - }; - - }; - union { - CFLASH_UM_32B_tag UMISR[5]; /* offset: 0x0048 (0x0004 x 5) */ - - /* UM - User Multiple Input Signature Register */ - CFLASH_UM_32B_tag UM[5]; /* offset: 0x0048 (0x0004 x 5) */ - - struct { - /* UM - User Multiple Input Signature Register */ - CFLASH_UM_32B_tag UM0; /* offset: 0x0048 size: 32 bit */ - CFLASH_UM_32B_tag UM1; /* offset: 0x004C size: 32 bit */ - CFLASH_UM_32B_tag UM2; /* offset: 0x0050 size: 32 bit */ - CFLASH_UM_32B_tag UM3; /* offset: 0x0054 size: 32 bit */ - CFLASH_UM_32B_tag UM4; /* offset: 0x0058 size: 32 bit */ - }; - - }; - } CFLASH_tag; - - -#define CFLASH (*(volatile CFLASH_tag *) 0xC3F88000UL) - - - -/****************************************************************/ -/* */ -/* Module: SIUL */ -/* */ -/****************************************************************/ - - typedef union { /* MIDR1 - MCU ID Register #1 */ - uint32_t R; - struct { - uint32_t PARTNUM:16; /* MCU Part Number */ - uint32_t CSP:1; /* CSP Package */ - uint32_t PKG:5; /* Package Settings */ - uint32_t:2; -#ifndef USE_FIELD_ALIASES_SIUL - uint32_t MAJOR_MASK:4; /* Major Mask Revision */ -#else - uint32_t MAJORMASK:4; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_SIUL - uint32_t MINOR_MASK:4; /* Minor Mask Revision */ -#else - uint32_t MINORMASK:4; /* deprecated name - please avoid */ -#endif - } B; - } SIUL_MIDR1_32B_tag; - - typedef union { /* MIDR2 - MCU ID Register #2 */ - uint32_t R; - struct { - uint32_t SF:1; /* Manufacturer */ - uint32_t FLASH_SIZE_1:4; /* Coarse Flash Memory Size */ - uint32_t FLASH_SIZE_2:4; /* Fine Flash Memory Size */ - uint32_t:7; -#ifndef USE_FIELD_ALIASES_SIUL - uint32_t PARTNUM2:8; /* MCU Part Number */ -#else - uint32_t PARTNUM:8; /* deprecated name - please avoid */ -#endif - uint32_t TBD:1; /* Optional Bit */ - uint32_t:2; - uint32_t EE:1; /* Data Flash Present */ - uint32_t:3; - uint32_t FR:1; /* Flexray Present */ - } B; - } SIUL_MIDR2_32B_tag; - - typedef union { /* ISR - Interrupt Status Flag Register */ - uint32_t R; - struct { - uint32_t EIF31:1; /* External Interrupt Status Flag */ - uint32_t EIF30:1; /* External Interrupt Status Flag */ - uint32_t EIF29:1; /* External Interrupt Status Flag */ - uint32_t EIF28:1; /* External Interrupt Status Flag */ - uint32_t EIF27:1; /* External Interrupt Status Flag */ - uint32_t EIF26:1; /* External Interrupt Status Flag */ - uint32_t EIF25:1; /* External Interrupt Status Flag */ - uint32_t EIF24:1; /* External Interrupt Status Flag */ - uint32_t EIF23:1; /* External Interrupt Status Flag */ - uint32_t EIF22:1; /* External Interrupt Status Flag */ - uint32_t EIF21:1; /* External Interrupt Status Flag */ - uint32_t EIF20:1; /* External Interrupt Status Flag */ - uint32_t EIF19:1; /* External Interrupt Status Flag */ - uint32_t EIF18:1; /* External Interrupt Status Flag */ - uint32_t EIF17:1; /* External Interrupt Status Flag */ - uint32_t EIF16:1; /* External Interrupt Status Flag */ - uint32_t EIF15:1; /* External Interrupt Status Flag */ - uint32_t EIF14:1; /* External Interrupt Status Flag */ - uint32_t EIF13:1; /* External Interrupt Status Flag */ - uint32_t EIF12:1; /* External Interrupt Status Flag */ - uint32_t EIF11:1; /* External Interrupt Status Flag */ - uint32_t EIF10:1; /* External Interrupt Status Flag */ - uint32_t EIF9:1; /* External Interrupt Status Flag */ - uint32_t EIF8:1; /* External Interrupt Status Flag */ - uint32_t EIF7:1; /* External Interrupt Status Flag */ - uint32_t EIF6:1; /* External Interrupt Status Flag */ - uint32_t EIF5:1; /* External Interrupt Status Flag */ - uint32_t EIF4:1; /* External Interrupt Status Flag */ - uint32_t EIF3:1; /* External Interrupt Status Flag */ - uint32_t EIF2:1; /* External Interrupt Status Flag */ - uint32_t EIF1:1; /* External Interrupt Status Flag */ - uint32_t EIF0:1; /* External Interrupt Status Flag */ - } B; - } SIUL_ISR_32B_tag; - - typedef union { /* IRER - Interrupt Request Enable Register */ - uint32_t R; - struct { - uint32_t EIRE31:1; /* Enable External Interrupt Requests */ - uint32_t EIRE30:1; /* Enable External Interrupt Requests */ - uint32_t EIRE29:1; /* Enable External Interrupt Requests */ - uint32_t EIRE28:1; /* Enable External Interrupt Requests */ - uint32_t EIRE27:1; /* Enable External Interrupt Requests */ - uint32_t EIRE26:1; /* Enable External Interrupt Requests */ - uint32_t EIRE25:1; /* Enable External Interrupt Requests */ - uint32_t EIRE24:1; /* Enable External Interrupt Requests */ - uint32_t EIRE23:1; /* Enable External Interrupt Requests */ - uint32_t EIRE22:1; /* Enable External Interrupt Requests */ - uint32_t EIRE21:1; /* Enable External Interrupt Requests */ - uint32_t EIRE20:1; /* Enable External Interrupt Requests */ - uint32_t EIRE19:1; /* Enable External Interrupt Requests */ - uint32_t EIRE18:1; /* Enable External Interrupt Requests */ - uint32_t EIRE17:1; /* Enable External Interrupt Requests */ - uint32_t EIRE16:1; /* Enable External Interrupt Requests */ - uint32_t EIRE15:1; /* Enable External Interrupt Requests */ - uint32_t EIRE14:1; /* Enable External Interrupt Requests */ - uint32_t EIRE13:1; /* Enable External Interrupt Requests */ - uint32_t EIRE12:1; /* Enable External Interrupt Requests */ - uint32_t EIRE11:1; /* Enable External Interrupt Requests */ - uint32_t EIRE10:1; /* Enable External Interrupt Requests */ - uint32_t EIRE9:1; /* Enable External Interrupt Requests */ - uint32_t EIRE8:1; /* Enable External Interrupt Requests */ - uint32_t EIRE7:1; /* Enable External Interrupt Requests */ - uint32_t EIRE6:1; /* Enable External Interrupt Requests */ - uint32_t EIRE5:1; /* Enable External Interrupt Requests */ - uint32_t EIRE4:1; /* Enable External Interrupt Requests */ - uint32_t EIRE3:1; /* Enable External Interrupt Requests */ - uint32_t EIRE2:1; /* Enable External Interrupt Requests */ - uint32_t EIRE1:1; /* Enable External Interrupt Requests */ - uint32_t EIRE0:1; /* Enable External Interrupt Requests */ - } B; - } SIUL_IRER_32B_tag; - - typedef union { /* IREER - Interrupt Rising Edge Event Enable */ - uint32_t R; - struct { - uint32_t IREE31:1; /* Enable rising-edge events */ - uint32_t IREE30:1; /* Enable rising-edge events */ - uint32_t IREE29:1; /* Enable rising-edge events */ - uint32_t IREE28:1; /* Enable rising-edge events */ - uint32_t IREE27:1; /* Enable rising-edge events */ - uint32_t IREE26:1; /* Enable rising-edge events */ - uint32_t IREE25:1; /* Enable rising-edge events */ - uint32_t IREE24:1; /* Enable rising-edge events */ - uint32_t IREE23:1; /* Enable rising-edge events */ - uint32_t IREE22:1; /* Enable rising-edge events */ - uint32_t IREE21:1; /* Enable rising-edge events */ - uint32_t IREE20:1; /* Enable rising-edge events */ - uint32_t IREE19:1; /* Enable rising-edge events */ - uint32_t IREE18:1; /* Enable rising-edge events */ - uint32_t IREE17:1; /* Enable rising-edge events */ - uint32_t IREE16:1; /* Enable rising-edge events */ - uint32_t IREE15:1; /* Enable rising-edge events */ - uint32_t IREE14:1; /* Enable rising-edge events */ - uint32_t IREE13:1; /* Enable rising-edge events */ - uint32_t IREE12:1; /* Enable rising-edge events */ - uint32_t IREE11:1; /* Enable rising-edge events */ - uint32_t IREE10:1; /* Enable rising-edge events */ - uint32_t IREE9:1; /* Enable rising-edge events */ - uint32_t IREE8:1; /* Enable rising-edge events */ - uint32_t IREE7:1; /* Enable rising-edge events */ - uint32_t IREE6:1; /* Enable rising-edge events */ - uint32_t IREE5:1; /* Enable rising-edge events */ - uint32_t IREE4:1; /* Enable rising-edge events */ - uint32_t IREE3:1; /* Enable rising-edge events */ - uint32_t IREE2:1; /* Enable rising-edge events */ - uint32_t IREE1:1; /* Enable rising-edge events */ - uint32_t IREE0:1; /* Enable rising-edge events */ - } B; - } SIUL_IREER_32B_tag; - - typedef union { /* IFEER - Interrupt Falling-Edge Event Enable */ - uint32_t R; - struct { - uint32_t IFEE31:1; /* Enable Falling Edge Events */ - uint32_t IFEE30:1; /* Enable Falling Edge Events */ - uint32_t IFEE29:1; /* Enable Falling Edge Events */ - uint32_t IFEE28:1; /* Enable Falling Edge Events */ - uint32_t IFEE27:1; /* Enable Falling Edge Events */ - uint32_t IFEE26:1; /* Enable Falling Edge Events */ - uint32_t IFEE25:1; /* Enable Falling Edge Events */ - uint32_t IFEE24:1; /* Enable Falling Edge Events */ - uint32_t IFEE23:1; /* Enable Falling Edge Events */ - uint32_t IFEE22:1; /* Enable Falling Edge Events */ - uint32_t IFEE21:1; /* Enable Falling Edge Events */ - uint32_t IFEE20:1; /* Enable Falling Edge Events */ - uint32_t IFEE19:1; /* Enable Falling Edge Events */ - uint32_t IFEE18:1; /* Enable Falling Edge Events */ - uint32_t IFEE17:1; /* Enable Falling Edge Events */ - uint32_t IFEE16:1; /* Enable Falling Edge Events */ - uint32_t IFEE15:1; /* Enable Falling Edge Events */ - uint32_t IFEE14:1; /* Enable Falling Edge Events */ - uint32_t IFEE13:1; /* Enable Falling Edge Events */ - uint32_t IFEE12:1; /* Enable Falling Edge Events */ - uint32_t IFEE11:1; /* Enable Falling Edge Events */ - uint32_t IFEE10:1; /* Enable Falling Edge Events */ - uint32_t IFEE9:1; /* Enable Falling Edge Events */ - uint32_t IFEE8:1; /* Enable Falling Edge Events */ - uint32_t IFEE7:1; /* Enable Falling Edge Events */ - uint32_t IFEE6:1; /* Enable Falling Edge Events */ - uint32_t IFEE5:1; /* Enable Falling Edge Events */ - uint32_t IFEE4:1; /* Enable Falling Edge Events */ - uint32_t IFEE3:1; /* Enable Falling Edge Events */ - uint32_t IFEE2:1; /* Enable Falling Edge Events */ - uint32_t IFEE1:1; /* Enable Falling Edge Events */ - uint32_t IFEE0:1; /* Enable Falling Edge Events */ - } B; - } SIUL_IFEER_32B_tag; - - typedef union { /* IFER Interrupt Filter Enable Register */ - uint32_t R; - struct { - uint32_t IFE31:1; /* Enable Digital Glitch Filter */ - uint32_t IFE30:1; /* Enable Digital Glitch Filter */ - uint32_t IFE29:1; /* Enable Digital Glitch Filter */ - uint32_t IFE28:1; /* Enable Digital Glitch Filter */ - uint32_t IFE27:1; /* Enable Digital Glitch Filter */ - uint32_t IFE26:1; /* Enable Digital Glitch Filter */ - uint32_t IFE25:1; /* Enable Digital Glitch Filter */ - uint32_t IFE24:1; /* Enable Digital Glitch Filter */ - uint32_t IFE23:1; /* Enable Digital Glitch Filter */ - uint32_t IFE22:1; /* Enable Digital Glitch Filter */ - uint32_t IFE21:1; /* Enable Digital Glitch Filter */ - uint32_t IFE20:1; /* Enable Digital Glitch Filter */ - uint32_t IFE19:1; /* Enable Digital Glitch Filter */ - uint32_t IFE18:1; /* Enable Digital Glitch Filter */ - uint32_t IFE17:1; /* Enable Digital Glitch Filter */ - uint32_t IFE16:1; /* Enable Digital Glitch Filter */ - uint32_t IFE15:1; /* Enable Digital Glitch Filter */ - uint32_t IFE14:1; /* Enable Digital Glitch Filter */ - uint32_t IFE13:1; /* Enable Digital Glitch Filter */ - uint32_t IFE12:1; /* Enable Digital Glitch Filter */ - uint32_t IFE11:1; /* Enable Digital Glitch Filter */ - uint32_t IFE10:1; /* Enable Digital Glitch Filter */ - uint32_t IFE9:1; /* Enable Digital Glitch Filter */ - uint32_t IFE8:1; /* Enable Digital Glitch Filter */ - uint32_t IFE7:1; /* Enable Digital Glitch Filter */ - uint32_t IFE6:1; /* Enable Digital Glitch Filter */ - uint32_t IFE5:1; /* Enable Digital Glitch Filter */ - uint32_t IFE4:1; /* Enable Digital Glitch Filter */ - uint32_t IFE3:1; /* Enable Digital Glitch Filter */ - uint32_t IFE2:1; /* Enable Digital Glitch Filter */ - uint32_t IFE1:1; /* Enable Digital Glitch Filter */ - uint32_t IFE0:1; /* Enable Digital Glitch Filter */ - } B; - } SIUL_IFER_32B_tag; - - - /* Register layout for all registers PCR... */ - - typedef union SIU_PCR_tag { /* PCR - Pad Configuration Register */ - uint16_t R; - struct { - uint16_t:1; -#ifndef USE_FIELD_ALIASES_SIUL - uint16_t SMC:1; /* Safe Mode Control */ -#else - uint16_t SME:1; /* deprecated name - please avoid */ -#endif - uint16_t APC:1; /* Analog Pad Control */ - uint16_t:1; - uint16_t PA:2; /* Pad Output Assignment */ - uint16_t OBE:1; /* Output Buffer Enable */ - uint16_t IBE:1; /* Input Buffer Enable */ -#ifndef USE_FIELD_ALIASES_SIUL - uint16_t DSC:2; /* Drive Strength Control */ -#else - uint16_t DCS:2; /* deprecated name - please avoid */ -#endif - uint16_t ODE:1; /* Open Drain Output Enable */ - uint16_t HYS:1; /* Input Hysteresis */ - uint16_t SRC:2; /* Slew Rate Control */ - uint16_t WPE:1; /* Weak Pull Up/Down Enable */ - uint16_t WPS:1; /* Weak Pull Up/Down Select */ - } B; - } SIU_PCR_tag; - - - /* Register layout for all registers PSMI... */ - - typedef union SIUL_PSMI_8B_tag { /* PSMI - Pad Selection for Multiplexed Inputs */ - uint8_t R; - struct { - uint8_t:4; - uint8_t PADSEL:4; /* Pad selection for pin */ - } B; - } SIUL_PSMI_8B_tag; - - - /* Register layout for all registers PSMI... */ - - typedef union { /* PSMI - Pad Selection for Multiplexed Inputs */ - uint32_t R; - struct { - uint32_t:4; - uint32_t PADSEL0:4; /* Pad selection for pin */ - uint32_t:4; - uint32_t PADSEL1:4; /* Pad selection for pin */ - uint32_t:4; - uint32_t PADSEL2:4; /* Pad selection for pin */ - uint32_t:4; - uint32_t PADSEL3:4; /* Pad selection for pin */ - } B; - } SIUL_PSMI_32B_tag; - - - /* Register layout for all registers GPDO... */ - - typedef union { /* GPDO - GPIO Pad Data Output Register */ - uint8_t R; - struct { - uint8_t:7; - uint8_t PDO:1; /* Pad Data Out */ - } B; - } SIUL_GPDO_8B_tag; - - - /* Register layout for all registers GPDO... */ - - typedef union { /* GPDO - GPIO Pad Data Output Register */ - uint32_t R; - struct { - uint32_t:7; - uint32_t PDO0:1; /* Pad Data Out */ - uint32_t:7; - uint32_t PDO1:1; /* Pad Data Out */ - uint32_t:7; - uint32_t PDO2:1; /* Pad Data Out */ - uint32_t:7; - uint32_t PDO3:1; /* Pad Data Out */ - } B; - } SIUL_GPDO_32B_tag; - - - /* Register layout for all registers GPDI... */ - - typedef union { /* GPDI - GPIO Pad Data Input Register */ - uint8_t R; - struct { - uint8_t:7; - uint8_t PDI:1; /* Pad Data In */ - } B; - } SIUL_GPDI_8B_tag; - - - /* Register layout for all registers GPDI... */ - - typedef union { /* GPDI - GPIO Pad Data Input Register */ - uint32_t R; - struct { - uint32_t:7; - uint32_t PDI0:1; /* Pad Data In */ - uint32_t:7; - uint32_t PDI1:1; /* Pad Data In */ - uint32_t:7; - uint32_t PDI2:1; /* Pad Data In */ - uint32_t:7; - uint32_t PDI3:1; /* Pad Data In */ - } B; - } SIUL_GPDI_32B_tag; - - - /* Register layout for all registers PGPDO... */ - - typedef union { /* PGPDO - Parallel GPIO Pad Data Out Register */ - uint16_t R; - } SIUL_PGPDO_16B_tag; - - - /* Register layout for all registers PGPDI... */ - - typedef union { /* PGPDI - Parallel GPIO Pad Data In Register */ - uint16_t R; - } SIUL_PGPDI_16B_tag; - - - /* Register layout for all registers MPGPDO... */ - - typedef union { /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ - uint32_t R; - struct { - uint32_t MASK:16; /* Mask Field */ - uint32_t MPPDO:16; /* Masked Parallel Pad Data Out */ - } B; - } SIUL_MPGPDO_32B_tag; - - - /* Register layout for all registers IFMC... */ - - typedef union { /* IFMC - Interrupt Filter Maximum Counter Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t MAXCNT:4; /* Maximum Interrupt Filter Counter Setting */ - } B; - } SIUL_IFMC_32B_tag; - - typedef union { /* IFCPR - Inerrupt Filter Clock Prescaler Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t IFCP:4; /* Interrupt Filter Clock Prescaler Setting */ - } B; - } SIUL_IFCPR_32B_tag; - - - - typedef struct SIU_tag { /* start of SIUL_tag */ - int8_t SIUL_reserved_0000_C[4]; - union { - SIUL_MIDR1_32B_tag MIDR; /* deprecated - please avoid */ - - /* MIDR1 - MCU ID Register #1 */ - SIUL_MIDR1_32B_tag MIDR1; /* offset: 0x0004 size: 32 bit */ - - }; - /* MIDR2 - MCU ID Register #2 */ - SIUL_MIDR2_32B_tag MIDR2; /* offset: 0x0008 size: 32 bit */ - int8_t SIUL_reserved_000C[8]; - /* ISR - Interrupt Status Flag Register */ - SIUL_ISR_32B_tag ISR; /* offset: 0x0014 size: 32 bit */ - /* IRER - Interrupt Request Enable Register */ - SIUL_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */ - int8_t SIUL_reserved_001C[12]; - /* IREER - Interrupt Rising Edge Event Enable */ - SIUL_IREER_32B_tag IREER; /* offset: 0x0028 size: 32 bit */ - /* IFEER - Interrupt Falling-Edge Event Enable */ - SIUL_IFEER_32B_tag IFEER; /* offset: 0x002C size: 32 bit */ - /* IFER Interrupt Filter Enable Register */ - SIUL_IFER_32B_tag IFER; /* offset: 0x0030 size: 32 bit */ - int8_t SIUL_reserved_0034_C[12]; - union { - /* PCR - Pad Configuration Register */ - SIU_PCR_tag PCR[512]; /* offset: 0x0040 (0x0002 x 512) */ - - struct { - /* PCR - Pad Configuration Register */ - SIU_PCR_tag PCR0; /* offset: 0x0040 size: 16 bit */ - SIU_PCR_tag PCR1; /* offset: 0x0042 size: 16 bit */ - SIU_PCR_tag PCR2; /* offset: 0x0044 size: 16 bit */ - SIU_PCR_tag PCR3; /* offset: 0x0046 size: 16 bit */ - SIU_PCR_tag PCR4; /* offset: 0x0048 size: 16 bit */ - SIU_PCR_tag PCR5; /* offset: 0x004A size: 16 bit */ - SIU_PCR_tag PCR6; /* offset: 0x004C size: 16 bit */ - SIU_PCR_tag PCR7; /* offset: 0x004E size: 16 bit */ - SIU_PCR_tag PCR8; /* offset: 0x0050 size: 16 bit */ - SIU_PCR_tag PCR9; /* offset: 0x0052 size: 16 bit */ - SIU_PCR_tag PCR10; /* offset: 0x0054 size: 16 bit */ - SIU_PCR_tag PCR11; /* offset: 0x0056 size: 16 bit */ - SIU_PCR_tag PCR12; /* offset: 0x0058 size: 16 bit */ - SIU_PCR_tag PCR13; /* offset: 0x005A size: 16 bit */ - SIU_PCR_tag PCR14; /* offset: 0x005C size: 16 bit */ - SIU_PCR_tag PCR15; /* offset: 0x005E size: 16 bit */ - SIU_PCR_tag PCR16; /* offset: 0x0060 size: 16 bit */ - SIU_PCR_tag PCR17; /* offset: 0x0062 size: 16 bit */ - SIU_PCR_tag PCR18; /* offset: 0x0064 size: 16 bit */ - SIU_PCR_tag PCR19; /* offset: 0x0066 size: 16 bit */ - SIU_PCR_tag PCR20; /* offset: 0x0068 size: 16 bit */ - SIU_PCR_tag PCR21; /* offset: 0x006A size: 16 bit */ - SIU_PCR_tag PCR22; /* offset: 0x006C size: 16 bit */ - SIU_PCR_tag PCR23; /* offset: 0x006E size: 16 bit */ - SIU_PCR_tag PCR24; /* offset: 0x0070 size: 16 bit */ - SIU_PCR_tag PCR25; /* offset: 0x0072 size: 16 bit */ - SIU_PCR_tag PCR26; /* offset: 0x0074 size: 16 bit */ - SIU_PCR_tag PCR27; /* offset: 0x0076 size: 16 bit */ - SIU_PCR_tag PCR28; /* offset: 0x0078 size: 16 bit */ - SIU_PCR_tag PCR29; /* offset: 0x007A size: 16 bit */ - SIU_PCR_tag PCR30; /* offset: 0x007C size: 16 bit */ - SIU_PCR_tag PCR31; /* offset: 0x007E size: 16 bit */ - SIU_PCR_tag PCR32; /* offset: 0x0080 size: 16 bit */ - SIU_PCR_tag PCR33; /* offset: 0x0082 size: 16 bit */ - SIU_PCR_tag PCR34; /* offset: 0x0084 size: 16 bit */ - SIU_PCR_tag PCR35; /* offset: 0x0086 size: 16 bit */ - SIU_PCR_tag PCR36; /* offset: 0x0088 size: 16 bit */ - SIU_PCR_tag PCR37; /* offset: 0x008A size: 16 bit */ - SIU_PCR_tag PCR38; /* offset: 0x008C size: 16 bit */ - SIU_PCR_tag PCR39; /* offset: 0x008E size: 16 bit */ - SIU_PCR_tag PCR40; /* offset: 0x0090 size: 16 bit */ - SIU_PCR_tag PCR41; /* offset: 0x0092 size: 16 bit */ - SIU_PCR_tag PCR42; /* offset: 0x0094 size: 16 bit */ - SIU_PCR_tag PCR43; /* offset: 0x0096 size: 16 bit */ - SIU_PCR_tag PCR44; /* offset: 0x0098 size: 16 bit */ - SIU_PCR_tag PCR45; /* offset: 0x009A size: 16 bit */ - SIU_PCR_tag PCR46; /* offset: 0x009C size: 16 bit */ - SIU_PCR_tag PCR47; /* offset: 0x009E size: 16 bit */ - SIU_PCR_tag PCR48; /* offset: 0x00A0 size: 16 bit */ - SIU_PCR_tag PCR49; /* offset: 0x00A2 size: 16 bit */ - SIU_PCR_tag PCR50; /* offset: 0x00A4 size: 16 bit */ - SIU_PCR_tag PCR51; /* offset: 0x00A6 size: 16 bit */ - SIU_PCR_tag PCR52; /* offset: 0x00A8 size: 16 bit */ - SIU_PCR_tag PCR53; /* offset: 0x00AA size: 16 bit */ - SIU_PCR_tag PCR54; /* offset: 0x00AC size: 16 bit */ - SIU_PCR_tag PCR55; /* offset: 0x00AE size: 16 bit */ - SIU_PCR_tag PCR56; /* offset: 0x00B0 size: 16 bit */ - SIU_PCR_tag PCR57; /* offset: 0x00B2 size: 16 bit */ - SIU_PCR_tag PCR58; /* offset: 0x00B4 size: 16 bit */ - SIU_PCR_tag PCR59; /* offset: 0x00B6 size: 16 bit */ - SIU_PCR_tag PCR60; /* offset: 0x00B8 size: 16 bit */ - SIU_PCR_tag PCR61; /* offset: 0x00BA size: 16 bit */ - SIU_PCR_tag PCR62; /* offset: 0x00BC size: 16 bit */ - SIU_PCR_tag PCR63; /* offset: 0x00BE size: 16 bit */ - SIU_PCR_tag PCR64; /* offset: 0x00C0 size: 16 bit */ - SIU_PCR_tag PCR65; /* offset: 0x00C2 size: 16 bit */ - SIU_PCR_tag PCR66; /* offset: 0x00C4 size: 16 bit */ - SIU_PCR_tag PCR67; /* offset: 0x00C6 size: 16 bit */ - SIU_PCR_tag PCR68; /* offset: 0x00C8 size: 16 bit */ - SIU_PCR_tag PCR69; /* offset: 0x00CA size: 16 bit */ - SIU_PCR_tag PCR70; /* offset: 0x00CC size: 16 bit */ - SIU_PCR_tag PCR71; /* offset: 0x00CE size: 16 bit */ - SIU_PCR_tag PCR72; /* offset: 0x00D0 size: 16 bit */ - SIU_PCR_tag PCR73; /* offset: 0x00D2 size: 16 bit */ - SIU_PCR_tag PCR74; /* offset: 0x00D4 size: 16 bit */ - SIU_PCR_tag PCR75; /* offset: 0x00D6 size: 16 bit */ - SIU_PCR_tag PCR76; /* offset: 0x00D8 size: 16 bit */ - SIU_PCR_tag PCR77; /* offset: 0x00DA size: 16 bit */ - SIU_PCR_tag PCR78; /* offset: 0x00DC size: 16 bit */ - SIU_PCR_tag PCR79; /* offset: 0x00DE size: 16 bit */ - SIU_PCR_tag PCR80; /* offset: 0x00E0 size: 16 bit */ - SIU_PCR_tag PCR81; /* offset: 0x00E2 size: 16 bit */ - SIU_PCR_tag PCR82; /* offset: 0x00E4 size: 16 bit */ - SIU_PCR_tag PCR83; /* offset: 0x00E6 size: 16 bit */ - SIU_PCR_tag PCR84; /* offset: 0x00E8 size: 16 bit */ - SIU_PCR_tag PCR85; /* offset: 0x00EA size: 16 bit */ - SIU_PCR_tag PCR86; /* offset: 0x00EC size: 16 bit */ - SIU_PCR_tag PCR87; /* offset: 0x00EE size: 16 bit */ - SIU_PCR_tag PCR88; /* offset: 0x00F0 size: 16 bit */ - SIU_PCR_tag PCR89; /* offset: 0x00F2 size: 16 bit */ - SIU_PCR_tag PCR90; /* offset: 0x00F4 size: 16 bit */ - SIU_PCR_tag PCR91; /* offset: 0x00F6 size: 16 bit */ - SIU_PCR_tag PCR92; /* offset: 0x00F8 size: 16 bit */ - SIU_PCR_tag PCR93; /* offset: 0x00FA size: 16 bit */ - SIU_PCR_tag PCR94; /* offset: 0x00FC size: 16 bit */ - SIU_PCR_tag PCR95; /* offset: 0x00FE size: 16 bit */ - SIU_PCR_tag PCR96; /* offset: 0x0100 size: 16 bit */ - SIU_PCR_tag PCR97; /* offset: 0x0102 size: 16 bit */ - SIU_PCR_tag PCR98; /* offset: 0x0104 size: 16 bit */ - SIU_PCR_tag PCR99; /* offset: 0x0106 size: 16 bit */ - SIU_PCR_tag PCR100; /* offset: 0x0108 size: 16 bit */ - SIU_PCR_tag PCR101; /* offset: 0x010A size: 16 bit */ - SIU_PCR_tag PCR102; /* offset: 0x010C size: 16 bit */ - SIU_PCR_tag PCR103; /* offset: 0x010E size: 16 bit */ - SIU_PCR_tag PCR104; /* offset: 0x0110 size: 16 bit */ - SIU_PCR_tag PCR105; /* offset: 0x0112 size: 16 bit */ - SIU_PCR_tag PCR106; /* offset: 0x0114 size: 16 bit */ - SIU_PCR_tag PCR107; /* offset: 0x0116 size: 16 bit */ - SIU_PCR_tag PCR108; /* offset: 0x0118 size: 16 bit */ - SIU_PCR_tag PCR109; /* offset: 0x011A size: 16 bit */ - SIU_PCR_tag PCR110; /* offset: 0x011C size: 16 bit */ - SIU_PCR_tag PCR111; /* offset: 0x011E size: 16 bit */ - SIU_PCR_tag PCR112; /* offset: 0x0120 size: 16 bit */ - SIU_PCR_tag PCR113; /* offset: 0x0122 size: 16 bit */ - SIU_PCR_tag PCR114; /* offset: 0x0124 size: 16 bit */ - SIU_PCR_tag PCR115; /* offset: 0x0126 size: 16 bit */ - SIU_PCR_tag PCR116; /* offset: 0x0128 size: 16 bit */ - SIU_PCR_tag PCR117; /* offset: 0x012A size: 16 bit */ - SIU_PCR_tag PCR118; /* offset: 0x012C size: 16 bit */ - SIU_PCR_tag PCR119; /* offset: 0x012E size: 16 bit */ - SIU_PCR_tag PCR120; /* offset: 0x0130 size: 16 bit */ - SIU_PCR_tag PCR121; /* offset: 0x0132 size: 16 bit */ - SIU_PCR_tag PCR122; /* offset: 0x0134 size: 16 bit */ - SIU_PCR_tag PCR123; /* offset: 0x0136 size: 16 bit */ - SIU_PCR_tag PCR124; /* offset: 0x0138 size: 16 bit */ - SIU_PCR_tag PCR125; /* offset: 0x013A size: 16 bit */ - SIU_PCR_tag PCR126; /* offset: 0x013C size: 16 bit */ - SIU_PCR_tag PCR127; /* offset: 0x013E size: 16 bit */ - SIU_PCR_tag PCR128; /* offset: 0x0140 size: 16 bit */ - SIU_PCR_tag PCR129; /* offset: 0x0142 size: 16 bit */ - SIU_PCR_tag PCR130; /* offset: 0x0144 size: 16 bit */ - SIU_PCR_tag PCR131; /* offset: 0x0146 size: 16 bit */ - SIU_PCR_tag PCR132; /* offset: 0x0148 size: 16 bit */ - SIU_PCR_tag PCR133; /* offset: 0x014A size: 16 bit */ - SIU_PCR_tag PCR134; /* offset: 0x014C size: 16 bit */ - SIU_PCR_tag PCR135; /* offset: 0x014E size: 16 bit */ - SIU_PCR_tag PCR136; /* offset: 0x0150 size: 16 bit */ - SIU_PCR_tag PCR137; /* offset: 0x0152 size: 16 bit */ - SIU_PCR_tag PCR138; /* offset: 0x0154 size: 16 bit */ - SIU_PCR_tag PCR139; /* offset: 0x0156 size: 16 bit */ - SIU_PCR_tag PCR140; /* offset: 0x0158 size: 16 bit */ - SIU_PCR_tag PCR141; /* offset: 0x015A size: 16 bit */ - SIU_PCR_tag PCR142; /* offset: 0x015C size: 16 bit */ - SIU_PCR_tag PCR143; /* offset: 0x015E size: 16 bit */ - SIU_PCR_tag PCR144; /* offset: 0x0160 size: 16 bit */ - SIU_PCR_tag PCR145; /* offset: 0x0162 size: 16 bit */ - SIU_PCR_tag PCR146; /* offset: 0x0164 size: 16 bit */ - SIU_PCR_tag PCR147; /* offset: 0x0166 size: 16 bit */ - SIU_PCR_tag PCR148; /* offset: 0x0168 size: 16 bit */ - SIU_PCR_tag PCR149; /* offset: 0x016A size: 16 bit */ - SIU_PCR_tag PCR150; /* offset: 0x016C size: 16 bit */ - SIU_PCR_tag PCR151; /* offset: 0x016E size: 16 bit */ - SIU_PCR_tag PCR152; /* offset: 0x0170 size: 16 bit */ - SIU_PCR_tag PCR153; /* offset: 0x0172 size: 16 bit */ - SIU_PCR_tag PCR154; /* offset: 0x0174 size: 16 bit */ - SIU_PCR_tag PCR155; /* offset: 0x0176 size: 16 bit */ - SIU_PCR_tag PCR156; /* offset: 0x0178 size: 16 bit */ - SIU_PCR_tag PCR157; /* offset: 0x017A size: 16 bit */ - SIU_PCR_tag PCR158; /* offset: 0x017C size: 16 bit */ - SIU_PCR_tag PCR159; /* offset: 0x017E size: 16 bit */ - SIU_PCR_tag PCR160; /* offset: 0x0180 size: 16 bit */ - SIU_PCR_tag PCR161; /* offset: 0x0182 size: 16 bit */ - SIU_PCR_tag PCR162; /* offset: 0x0184 size: 16 bit */ - SIU_PCR_tag PCR163; /* offset: 0x0186 size: 16 bit */ - SIU_PCR_tag PCR164; /* offset: 0x0188 size: 16 bit */ - SIU_PCR_tag PCR165; /* offset: 0x018A size: 16 bit */ - SIU_PCR_tag PCR166; /* offset: 0x018C size: 16 bit */ - SIU_PCR_tag PCR167; /* offset: 0x018E size: 16 bit */ - SIU_PCR_tag PCR168; /* offset: 0x0190 size: 16 bit */ - SIU_PCR_tag PCR169; /* offset: 0x0192 size: 16 bit */ - SIU_PCR_tag PCR170; /* offset: 0x0194 size: 16 bit */ - SIU_PCR_tag PCR171; /* offset: 0x0196 size: 16 bit */ - SIU_PCR_tag PCR172; /* offset: 0x0198 size: 16 bit */ - SIU_PCR_tag PCR173; /* offset: 0x019A size: 16 bit */ - SIU_PCR_tag PCR174; /* offset: 0x019C size: 16 bit */ - SIU_PCR_tag PCR175; /* offset: 0x019E size: 16 bit */ - SIU_PCR_tag PCR176; /* offset: 0x01A0 size: 16 bit */ - SIU_PCR_tag PCR177; /* offset: 0x01A2 size: 16 bit */ - SIU_PCR_tag PCR178; /* offset: 0x01A4 size: 16 bit */ - SIU_PCR_tag PCR179; /* offset: 0x01A6 size: 16 bit */ - SIU_PCR_tag PCR180; /* offset: 0x01A8 size: 16 bit */ - SIU_PCR_tag PCR181; /* offset: 0x01AA size: 16 bit */ - SIU_PCR_tag PCR182; /* offset: 0x01AC size: 16 bit */ - SIU_PCR_tag PCR183; /* offset: 0x01AE size: 16 bit */ - SIU_PCR_tag PCR184; /* offset: 0x01B0 size: 16 bit */ - SIU_PCR_tag PCR185; /* offset: 0x01B2 size: 16 bit */ - SIU_PCR_tag PCR186; /* offset: 0x01B4 size: 16 bit */ - SIU_PCR_tag PCR187; /* offset: 0x01B6 size: 16 bit */ - SIU_PCR_tag PCR188; /* offset: 0x01B8 size: 16 bit */ - SIU_PCR_tag PCR189; /* offset: 0x01BA size: 16 bit */ - SIU_PCR_tag PCR190; /* offset: 0x01BC size: 16 bit */ - SIU_PCR_tag PCR191; /* offset: 0x01BE size: 16 bit */ - SIU_PCR_tag PCR192; /* offset: 0x01C0 size: 16 bit */ - SIU_PCR_tag PCR193; /* offset: 0x01C2 size: 16 bit */ - SIU_PCR_tag PCR194; /* offset: 0x01C4 size: 16 bit */ - SIU_PCR_tag PCR195; /* offset: 0x01C6 size: 16 bit */ - SIU_PCR_tag PCR196; /* offset: 0x01C8 size: 16 bit */ - SIU_PCR_tag PCR197; /* offset: 0x01CA size: 16 bit */ - SIU_PCR_tag PCR198; /* offset: 0x01CC size: 16 bit */ - SIU_PCR_tag PCR199; /* offset: 0x01CE size: 16 bit */ - SIU_PCR_tag PCR200; /* offset: 0x01D0 size: 16 bit */ - SIU_PCR_tag PCR201; /* offset: 0x01D2 size: 16 bit */ - SIU_PCR_tag PCR202; /* offset: 0x01D4 size: 16 bit */ - SIU_PCR_tag PCR203; /* offset: 0x01D6 size: 16 bit */ - SIU_PCR_tag PCR204; /* offset: 0x01D8 size: 16 bit */ - SIU_PCR_tag PCR205; /* offset: 0x01DA size: 16 bit */ - SIU_PCR_tag PCR206; /* offset: 0x01DC size: 16 bit */ - SIU_PCR_tag PCR207; /* offset: 0x01DE size: 16 bit */ - SIU_PCR_tag PCR208; /* offset: 0x01E0 size: 16 bit */ - SIU_PCR_tag PCR209; /* offset: 0x01E2 size: 16 bit */ - SIU_PCR_tag PCR210; /* offset: 0x01E4 size: 16 bit */ - SIU_PCR_tag PCR211; /* offset: 0x01E6 size: 16 bit */ - SIU_PCR_tag PCR212; /* offset: 0x01E8 size: 16 bit */ - SIU_PCR_tag PCR213; /* offset: 0x01EA size: 16 bit */ - SIU_PCR_tag PCR214; /* offset: 0x01EC size: 16 bit */ - SIU_PCR_tag PCR215; /* offset: 0x01EE size: 16 bit */ - SIU_PCR_tag PCR216; /* offset: 0x01F0 size: 16 bit */ - SIU_PCR_tag PCR217; /* offset: 0x01F2 size: 16 bit */ - SIU_PCR_tag PCR218; /* offset: 0x01F4 size: 16 bit */ - SIU_PCR_tag PCR219; /* offset: 0x01F6 size: 16 bit */ - SIU_PCR_tag PCR220; /* offset: 0x01F8 size: 16 bit */ - SIU_PCR_tag PCR221; /* offset: 0x01FA size: 16 bit */ - SIU_PCR_tag PCR222; /* offset: 0x01FC size: 16 bit */ - SIU_PCR_tag PCR223; /* offset: 0x01FE size: 16 bit */ - SIU_PCR_tag PCR224; /* offset: 0x0200 size: 16 bit */ - SIU_PCR_tag PCR225; /* offset: 0x0202 size: 16 bit */ - SIU_PCR_tag PCR226; /* offset: 0x0204 size: 16 bit */ - SIU_PCR_tag PCR227; /* offset: 0x0206 size: 16 bit */ - SIU_PCR_tag PCR228; /* offset: 0x0208 size: 16 bit */ - SIU_PCR_tag PCR229; /* offset: 0x020A size: 16 bit */ - SIU_PCR_tag PCR230; /* offset: 0x020C size: 16 bit */ - SIU_PCR_tag PCR231; /* offset: 0x020E size: 16 bit */ - SIU_PCR_tag PCR232; /* offset: 0x0210 size: 16 bit */ - SIU_PCR_tag PCR233; /* offset: 0x0212 size: 16 bit */ - SIU_PCR_tag PCR234; /* offset: 0x0214 size: 16 bit */ - SIU_PCR_tag PCR235; /* offset: 0x0216 size: 16 bit */ - SIU_PCR_tag PCR236; /* offset: 0x0218 size: 16 bit */ - SIU_PCR_tag PCR237; /* offset: 0x021A size: 16 bit */ - SIU_PCR_tag PCR238; /* offset: 0x021C size: 16 bit */ - SIU_PCR_tag PCR239; /* offset: 0x021E size: 16 bit */ - SIU_PCR_tag PCR240; /* offset: 0x0220 size: 16 bit */ - SIU_PCR_tag PCR241; /* offset: 0x0222 size: 16 bit */ - SIU_PCR_tag PCR242; /* offset: 0x0224 size: 16 bit */ - SIU_PCR_tag PCR243; /* offset: 0x0226 size: 16 bit */ - SIU_PCR_tag PCR244; /* offset: 0x0228 size: 16 bit */ - SIU_PCR_tag PCR245; /* offset: 0x022A size: 16 bit */ - SIU_PCR_tag PCR246; /* offset: 0x022C size: 16 bit */ - SIU_PCR_tag PCR247; /* offset: 0x022E size: 16 bit */ - SIU_PCR_tag PCR248; /* offset: 0x0230 size: 16 bit */ - SIU_PCR_tag PCR249; /* offset: 0x0232 size: 16 bit */ - SIU_PCR_tag PCR250; /* offset: 0x0234 size: 16 bit */ - SIU_PCR_tag PCR251; /* offset: 0x0236 size: 16 bit */ - SIU_PCR_tag PCR252; /* offset: 0x0238 size: 16 bit */ - SIU_PCR_tag PCR253; /* offset: 0x023A size: 16 bit */ - SIU_PCR_tag PCR254; /* offset: 0x023C size: 16 bit */ - SIU_PCR_tag PCR255; /* offset: 0x023E size: 16 bit */ - SIU_PCR_tag PCR256; /* offset: 0x0240 size: 16 bit */ - SIU_PCR_tag PCR257; /* offset: 0x0242 size: 16 bit */ - SIU_PCR_tag PCR258; /* offset: 0x0244 size: 16 bit */ - SIU_PCR_tag PCR259; /* offset: 0x0246 size: 16 bit */ - SIU_PCR_tag PCR260; /* offset: 0x0248 size: 16 bit */ - SIU_PCR_tag PCR261; /* offset: 0x024A size: 16 bit */ - SIU_PCR_tag PCR262; /* offset: 0x024C size: 16 bit */ - SIU_PCR_tag PCR263; /* offset: 0x024E size: 16 bit */ - SIU_PCR_tag PCR264; /* offset: 0x0250 size: 16 bit */ - SIU_PCR_tag PCR265; /* offset: 0x0252 size: 16 bit */ - SIU_PCR_tag PCR266; /* offset: 0x0254 size: 16 bit */ - SIU_PCR_tag PCR267; /* offset: 0x0256 size: 16 bit */ - SIU_PCR_tag PCR268; /* offset: 0x0258 size: 16 bit */ - SIU_PCR_tag PCR269; /* offset: 0x025A size: 16 bit */ - SIU_PCR_tag PCR270; /* offset: 0x025C size: 16 bit */ - SIU_PCR_tag PCR271; /* offset: 0x025E size: 16 bit */ - SIU_PCR_tag PCR272; /* offset: 0x0260 size: 16 bit */ - SIU_PCR_tag PCR273; /* offset: 0x0262 size: 16 bit */ - SIU_PCR_tag PCR274; /* offset: 0x0264 size: 16 bit */ - SIU_PCR_tag PCR275; /* offset: 0x0266 size: 16 bit */ - SIU_PCR_tag PCR276; /* offset: 0x0268 size: 16 bit */ - SIU_PCR_tag PCR277; /* offset: 0x026A size: 16 bit */ - SIU_PCR_tag PCR278; /* offset: 0x026C size: 16 bit */ - SIU_PCR_tag PCR279; /* offset: 0x026E size: 16 bit */ - SIU_PCR_tag PCR280; /* offset: 0x0270 size: 16 bit */ - SIU_PCR_tag PCR281; /* offset: 0x0272 size: 16 bit */ - SIU_PCR_tag PCR282; /* offset: 0x0274 size: 16 bit */ - SIU_PCR_tag PCR283; /* offset: 0x0276 size: 16 bit */ - SIU_PCR_tag PCR284; /* offset: 0x0278 size: 16 bit */ - SIU_PCR_tag PCR285; /* offset: 0x027A size: 16 bit */ - SIU_PCR_tag PCR286; /* offset: 0x027C size: 16 bit */ - SIU_PCR_tag PCR287; /* offset: 0x027E size: 16 bit */ - SIU_PCR_tag PCR288; /* offset: 0x0280 size: 16 bit */ - SIU_PCR_tag PCR289; /* offset: 0x0282 size: 16 bit */ - SIU_PCR_tag PCR290; /* offset: 0x0284 size: 16 bit */ - SIU_PCR_tag PCR291; /* offset: 0x0286 size: 16 bit */ - SIU_PCR_tag PCR292; /* offset: 0x0288 size: 16 bit */ - SIU_PCR_tag PCR293; /* offset: 0x028A size: 16 bit */ - SIU_PCR_tag PCR294; /* offset: 0x028C size: 16 bit */ - SIU_PCR_tag PCR295; /* offset: 0x028E size: 16 bit */ - SIU_PCR_tag PCR296; /* offset: 0x0290 size: 16 bit */ - SIU_PCR_tag PCR297; /* offset: 0x0292 size: 16 bit */ - SIU_PCR_tag PCR298; /* offset: 0x0294 size: 16 bit */ - SIU_PCR_tag PCR299; /* offset: 0x0296 size: 16 bit */ - SIU_PCR_tag PCR300; /* offset: 0x0298 size: 16 bit */ - SIU_PCR_tag PCR301; /* offset: 0x029A size: 16 bit */ - SIU_PCR_tag PCR302; /* offset: 0x029C size: 16 bit */ - SIU_PCR_tag PCR303; /* offset: 0x029E size: 16 bit */ - SIU_PCR_tag PCR304; /* offset: 0x02A0 size: 16 bit */ - SIU_PCR_tag PCR305; /* offset: 0x02A2 size: 16 bit */ - SIU_PCR_tag PCR306; /* offset: 0x02A4 size: 16 bit */ - SIU_PCR_tag PCR307; /* offset: 0x02A6 size: 16 bit */ - SIU_PCR_tag PCR308; /* offset: 0x02A8 size: 16 bit */ - SIU_PCR_tag PCR309; /* offset: 0x02AA size: 16 bit */ - SIU_PCR_tag PCR310; /* offset: 0x02AC size: 16 bit */ - SIU_PCR_tag PCR311; /* offset: 0x02AE size: 16 bit */ - SIU_PCR_tag PCR312; /* offset: 0x02B0 size: 16 bit */ - SIU_PCR_tag PCR313; /* offset: 0x02B2 size: 16 bit */ - SIU_PCR_tag PCR314; /* offset: 0x02B4 size: 16 bit */ - SIU_PCR_tag PCR315; /* offset: 0x02B6 size: 16 bit */ - SIU_PCR_tag PCR316; /* offset: 0x02B8 size: 16 bit */ - SIU_PCR_tag PCR317; /* offset: 0x02BA size: 16 bit */ - SIU_PCR_tag PCR318; /* offset: 0x02BC size: 16 bit */ - SIU_PCR_tag PCR319; /* offset: 0x02BE size: 16 bit */ - SIU_PCR_tag PCR320; /* offset: 0x02C0 size: 16 bit */ - SIU_PCR_tag PCR321; /* offset: 0x02C2 size: 16 bit */ - SIU_PCR_tag PCR322; /* offset: 0x02C4 size: 16 bit */ - SIU_PCR_tag PCR323; /* offset: 0x02C6 size: 16 bit */ - SIU_PCR_tag PCR324; /* offset: 0x02C8 size: 16 bit */ - SIU_PCR_tag PCR325; /* offset: 0x02CA size: 16 bit */ - SIU_PCR_tag PCR326; /* offset: 0x02CC size: 16 bit */ - SIU_PCR_tag PCR327; /* offset: 0x02CE size: 16 bit */ - SIU_PCR_tag PCR328; /* offset: 0x02D0 size: 16 bit */ - SIU_PCR_tag PCR329; /* offset: 0x02D2 size: 16 bit */ - SIU_PCR_tag PCR330; /* offset: 0x02D4 size: 16 bit */ - SIU_PCR_tag PCR331; /* offset: 0x02D6 size: 16 bit */ - SIU_PCR_tag PCR332; /* offset: 0x02D8 size: 16 bit */ - SIU_PCR_tag PCR333; /* offset: 0x02DA size: 16 bit */ - SIU_PCR_tag PCR334; /* offset: 0x02DC size: 16 bit */ - SIU_PCR_tag PCR335; /* offset: 0x02DE size: 16 bit */ - SIU_PCR_tag PCR336; /* offset: 0x02E0 size: 16 bit */ - SIU_PCR_tag PCR337; /* offset: 0x02E2 size: 16 bit */ - SIU_PCR_tag PCR338; /* offset: 0x02E4 size: 16 bit */ - SIU_PCR_tag PCR339; /* offset: 0x02E6 size: 16 bit */ - SIU_PCR_tag PCR340; /* offset: 0x02E8 size: 16 bit */ - SIU_PCR_tag PCR341; /* offset: 0x02EA size: 16 bit */ - SIU_PCR_tag PCR342; /* offset: 0x02EC size: 16 bit */ - SIU_PCR_tag PCR343; /* offset: 0x02EE size: 16 bit */ - SIU_PCR_tag PCR344; /* offset: 0x02F0 size: 16 bit */ - SIU_PCR_tag PCR345; /* offset: 0x02F2 size: 16 bit */ - SIU_PCR_tag PCR346; /* offset: 0x02F4 size: 16 bit */ - SIU_PCR_tag PCR347; /* offset: 0x02F6 size: 16 bit */ - SIU_PCR_tag PCR348; /* offset: 0x02F8 size: 16 bit */ - SIU_PCR_tag PCR349; /* offset: 0x02FA size: 16 bit */ - SIU_PCR_tag PCR350; /* offset: 0x02FC size: 16 bit */ - SIU_PCR_tag PCR351; /* offset: 0x02FE size: 16 bit */ - SIU_PCR_tag PCR352; /* offset: 0x0300 size: 16 bit */ - SIU_PCR_tag PCR353; /* offset: 0x0302 size: 16 bit */ - SIU_PCR_tag PCR354; /* offset: 0x0304 size: 16 bit */ - SIU_PCR_tag PCR355; /* offset: 0x0306 size: 16 bit */ - SIU_PCR_tag PCR356; /* offset: 0x0308 size: 16 bit */ - SIU_PCR_tag PCR357; /* offset: 0x030A size: 16 bit */ - SIU_PCR_tag PCR358; /* offset: 0x030C size: 16 bit */ - SIU_PCR_tag PCR359; /* offset: 0x030E size: 16 bit */ - SIU_PCR_tag PCR360; /* offset: 0x0310 size: 16 bit */ - SIU_PCR_tag PCR361; /* offset: 0x0312 size: 16 bit */ - SIU_PCR_tag PCR362; /* offset: 0x0314 size: 16 bit */ - SIU_PCR_tag PCR363; /* offset: 0x0316 size: 16 bit */ - SIU_PCR_tag PCR364; /* offset: 0x0318 size: 16 bit */ - SIU_PCR_tag PCR365; /* offset: 0x031A size: 16 bit */ - SIU_PCR_tag PCR366; /* offset: 0x031C size: 16 bit */ - SIU_PCR_tag PCR367; /* offset: 0x031E size: 16 bit */ - SIU_PCR_tag PCR368; /* offset: 0x0320 size: 16 bit */ - SIU_PCR_tag PCR369; /* offset: 0x0322 size: 16 bit */ - SIU_PCR_tag PCR370; /* offset: 0x0324 size: 16 bit */ - SIU_PCR_tag PCR371; /* offset: 0x0326 size: 16 bit */ - SIU_PCR_tag PCR372; /* offset: 0x0328 size: 16 bit */ - SIU_PCR_tag PCR373; /* offset: 0x032A size: 16 bit */ - SIU_PCR_tag PCR374; /* offset: 0x032C size: 16 bit */ - SIU_PCR_tag PCR375; /* offset: 0x032E size: 16 bit */ - SIU_PCR_tag PCR376; /* offset: 0x0330 size: 16 bit */ - SIU_PCR_tag PCR377; /* offset: 0x0332 size: 16 bit */ - SIU_PCR_tag PCR378; /* offset: 0x0334 size: 16 bit */ - SIU_PCR_tag PCR379; /* offset: 0x0336 size: 16 bit */ - SIU_PCR_tag PCR380; /* offset: 0x0338 size: 16 bit */ - SIU_PCR_tag PCR381; /* offset: 0x033A size: 16 bit */ - SIU_PCR_tag PCR382; /* offset: 0x033C size: 16 bit */ - SIU_PCR_tag PCR383; /* offset: 0x033E size: 16 bit */ - SIU_PCR_tag PCR384; /* offset: 0x0340 size: 16 bit */ - SIU_PCR_tag PCR385; /* offset: 0x0342 size: 16 bit */ - SIU_PCR_tag PCR386; /* offset: 0x0344 size: 16 bit */ - SIU_PCR_tag PCR387; /* offset: 0x0346 size: 16 bit */ - SIU_PCR_tag PCR388; /* offset: 0x0348 size: 16 bit */ - SIU_PCR_tag PCR389; /* offset: 0x034A size: 16 bit */ - SIU_PCR_tag PCR390; /* offset: 0x034C size: 16 bit */ - SIU_PCR_tag PCR391; /* offset: 0x034E size: 16 bit */ - SIU_PCR_tag PCR392; /* offset: 0x0350 size: 16 bit */ - SIU_PCR_tag PCR393; /* offset: 0x0352 size: 16 bit */ - SIU_PCR_tag PCR394; /* offset: 0x0354 size: 16 bit */ - SIU_PCR_tag PCR395; /* offset: 0x0356 size: 16 bit */ - SIU_PCR_tag PCR396; /* offset: 0x0358 size: 16 bit */ - SIU_PCR_tag PCR397; /* offset: 0x035A size: 16 bit */ - SIU_PCR_tag PCR398; /* offset: 0x035C size: 16 bit */ - SIU_PCR_tag PCR399; /* offset: 0x035E size: 16 bit */ - SIU_PCR_tag PCR400; /* offset: 0x0360 size: 16 bit */ - SIU_PCR_tag PCR401; /* offset: 0x0362 size: 16 bit */ - SIU_PCR_tag PCR402; /* offset: 0x0364 size: 16 bit */ - SIU_PCR_tag PCR403; /* offset: 0x0366 size: 16 bit */ - SIU_PCR_tag PCR404; /* offset: 0x0368 size: 16 bit */ - SIU_PCR_tag PCR405; /* offset: 0x036A size: 16 bit */ - SIU_PCR_tag PCR406; /* offset: 0x036C size: 16 bit */ - SIU_PCR_tag PCR407; /* offset: 0x036E size: 16 bit */ - SIU_PCR_tag PCR408; /* offset: 0x0370 size: 16 bit */ - SIU_PCR_tag PCR409; /* offset: 0x0372 size: 16 bit */ - SIU_PCR_tag PCR410; /* offset: 0x0374 size: 16 bit */ - SIU_PCR_tag PCR411; /* offset: 0x0376 size: 16 bit */ - SIU_PCR_tag PCR412; /* offset: 0x0378 size: 16 bit */ - SIU_PCR_tag PCR413; /* offset: 0x037A size: 16 bit */ - SIU_PCR_tag PCR414; /* offset: 0x037C size: 16 bit */ - SIU_PCR_tag PCR415; /* offset: 0x037E size: 16 bit */ - SIU_PCR_tag PCR416; /* offset: 0x0380 size: 16 bit */ - SIU_PCR_tag PCR417; /* offset: 0x0382 size: 16 bit */ - SIU_PCR_tag PCR418; /* offset: 0x0384 size: 16 bit */ - SIU_PCR_tag PCR419; /* offset: 0x0386 size: 16 bit */ - SIU_PCR_tag PCR420; /* offset: 0x0388 size: 16 bit */ - SIU_PCR_tag PCR421; /* offset: 0x038A size: 16 bit */ - SIU_PCR_tag PCR422; /* offset: 0x038C size: 16 bit */ - SIU_PCR_tag PCR423; /* offset: 0x038E size: 16 bit */ - SIU_PCR_tag PCR424; /* offset: 0x0390 size: 16 bit */ - SIU_PCR_tag PCR425; /* offset: 0x0392 size: 16 bit */ - SIU_PCR_tag PCR426; /* offset: 0x0394 size: 16 bit */ - SIU_PCR_tag PCR427; /* offset: 0x0396 size: 16 bit */ - SIU_PCR_tag PCR428; /* offset: 0x0398 size: 16 bit */ - SIU_PCR_tag PCR429; /* offset: 0x039A size: 16 bit */ - SIU_PCR_tag PCR430; /* offset: 0x039C size: 16 bit */ - SIU_PCR_tag PCR431; /* offset: 0x039E size: 16 bit */ - SIU_PCR_tag PCR432; /* offset: 0x03A0 size: 16 bit */ - SIU_PCR_tag PCR433; /* offset: 0x03A2 size: 16 bit */ - SIU_PCR_tag PCR434; /* offset: 0x03A4 size: 16 bit */ - SIU_PCR_tag PCR435; /* offset: 0x03A6 size: 16 bit */ - SIU_PCR_tag PCR436; /* offset: 0x03A8 size: 16 bit */ - SIU_PCR_tag PCR437; /* offset: 0x03AA size: 16 bit */ - SIU_PCR_tag PCR438; /* offset: 0x03AC size: 16 bit */ - SIU_PCR_tag PCR439; /* offset: 0x03AE size: 16 bit */ - SIU_PCR_tag PCR440; /* offset: 0x03B0 size: 16 bit */ - SIU_PCR_tag PCR441; /* offset: 0x03B2 size: 16 bit */ - SIU_PCR_tag PCR442; /* offset: 0x03B4 size: 16 bit */ - SIU_PCR_tag PCR443; /* offset: 0x03B6 size: 16 bit */ - SIU_PCR_tag PCR444; /* offset: 0x03B8 size: 16 bit */ - SIU_PCR_tag PCR445; /* offset: 0x03BA size: 16 bit */ - SIU_PCR_tag PCR446; /* offset: 0x03BC size: 16 bit */ - SIU_PCR_tag PCR447; /* offset: 0x03BE size: 16 bit */ - SIU_PCR_tag PCR448; /* offset: 0x03C0 size: 16 bit */ - SIU_PCR_tag PCR449; /* offset: 0x03C2 size: 16 bit */ - SIU_PCR_tag PCR450; /* offset: 0x03C4 size: 16 bit */ - SIU_PCR_tag PCR451; /* offset: 0x03C6 size: 16 bit */ - SIU_PCR_tag PCR452; /* offset: 0x03C8 size: 16 bit */ - SIU_PCR_tag PCR453; /* offset: 0x03CA size: 16 bit */ - SIU_PCR_tag PCR454; /* offset: 0x03CC size: 16 bit */ - SIU_PCR_tag PCR455; /* offset: 0x03CE size: 16 bit */ - SIU_PCR_tag PCR456; /* offset: 0x03D0 size: 16 bit */ - SIU_PCR_tag PCR457; /* offset: 0x03D2 size: 16 bit */ - SIU_PCR_tag PCR458; /* offset: 0x03D4 size: 16 bit */ - SIU_PCR_tag PCR459; /* offset: 0x03D6 size: 16 bit */ - SIU_PCR_tag PCR460; /* offset: 0x03D8 size: 16 bit */ - SIU_PCR_tag PCR461; /* offset: 0x03DA size: 16 bit */ - SIU_PCR_tag PCR462; /* offset: 0x03DC size: 16 bit */ - SIU_PCR_tag PCR463; /* offset: 0x03DE size: 16 bit */ - SIU_PCR_tag PCR464; /* offset: 0x03E0 size: 16 bit */ - SIU_PCR_tag PCR465; /* offset: 0x03E2 size: 16 bit */ - SIU_PCR_tag PCR466; /* offset: 0x03E4 size: 16 bit */ - SIU_PCR_tag PCR467; /* offset: 0x03E6 size: 16 bit */ - SIU_PCR_tag PCR468; /* offset: 0x03E8 size: 16 bit */ - SIU_PCR_tag PCR469; /* offset: 0x03EA size: 16 bit */ - SIU_PCR_tag PCR470; /* offset: 0x03EC size: 16 bit */ - SIU_PCR_tag PCR471; /* offset: 0x03EE size: 16 bit */ - SIU_PCR_tag PCR472; /* offset: 0x03F0 size: 16 bit */ - SIU_PCR_tag PCR473; /* offset: 0x03F2 size: 16 bit */ - SIU_PCR_tag PCR474; /* offset: 0x03F4 size: 16 bit */ - SIU_PCR_tag PCR475; /* offset: 0x03F6 size: 16 bit */ - SIU_PCR_tag PCR476; /* offset: 0x03F8 size: 16 bit */ - SIU_PCR_tag PCR477; /* offset: 0x03FA size: 16 bit */ - SIU_PCR_tag PCR478; /* offset: 0x03FC size: 16 bit */ - SIU_PCR_tag PCR479; /* offset: 0x03FE size: 16 bit */ - SIU_PCR_tag PCR480; /* offset: 0x0400 size: 16 bit */ - SIU_PCR_tag PCR481; /* offset: 0x0402 size: 16 bit */ - SIU_PCR_tag PCR482; /* offset: 0x0404 size: 16 bit */ - SIU_PCR_tag PCR483; /* offset: 0x0406 size: 16 bit */ - SIU_PCR_tag PCR484; /* offset: 0x0408 size: 16 bit */ - SIU_PCR_tag PCR485; /* offset: 0x040A size: 16 bit */ - SIU_PCR_tag PCR486; /* offset: 0x040C size: 16 bit */ - SIU_PCR_tag PCR487; /* offset: 0x040E size: 16 bit */ - SIU_PCR_tag PCR488; /* offset: 0x0410 size: 16 bit */ - SIU_PCR_tag PCR489; /* offset: 0x0412 size: 16 bit */ - SIU_PCR_tag PCR490; /* offset: 0x0414 size: 16 bit */ - SIU_PCR_tag PCR491; /* offset: 0x0416 size: 16 bit */ - SIU_PCR_tag PCR492; /* offset: 0x0418 size: 16 bit */ - SIU_PCR_tag PCR493; /* offset: 0x041A size: 16 bit */ - SIU_PCR_tag PCR494; /* offset: 0x041C size: 16 bit */ - SIU_PCR_tag PCR495; /* offset: 0x041E size: 16 bit */ - SIU_PCR_tag PCR496; /* offset: 0x0420 size: 16 bit */ - SIU_PCR_tag PCR497; /* offset: 0x0422 size: 16 bit */ - SIU_PCR_tag PCR498; /* offset: 0x0424 size: 16 bit */ - SIU_PCR_tag PCR499; /* offset: 0x0426 size: 16 bit */ - SIU_PCR_tag PCR500; /* offset: 0x0428 size: 16 bit */ - SIU_PCR_tag PCR501; /* offset: 0x042A size: 16 bit */ - SIU_PCR_tag PCR502; /* offset: 0x042C size: 16 bit */ - SIU_PCR_tag PCR503; /* offset: 0x042E size: 16 bit */ - SIU_PCR_tag PCR504; /* offset: 0x0430 size: 16 bit */ - SIU_PCR_tag PCR505; /* offset: 0x0432 size: 16 bit */ - SIU_PCR_tag PCR506; /* offset: 0x0434 size: 16 bit */ - SIU_PCR_tag PCR507; /* offset: 0x0436 size: 16 bit */ - SIU_PCR_tag PCR508; /* offset: 0x0438 size: 16 bit */ - SIU_PCR_tag PCR509; /* offset: 0x043A size: 16 bit */ - SIU_PCR_tag PCR510; /* offset: 0x043C size: 16 bit */ - SIU_PCR_tag PCR511; /* offset: 0x043E size: 16 bit */ - }; - - }; - int8_t SIUL_reserved_0440_C[192]; - union { - /* PSMI - Pad Selection for Multiplexed Inputs */ - SIUL_PSMI_32B_tag PSMI_32B[64]; /* offset: 0x0500 (0x0004 x 64) */ - - /* PSMI - Pad Selection for Multiplexed Inputs */ - SIUL_PSMI_8B_tag PSMI[256]; /* offset: 0x0500 (0x0001 x 256) */ - - struct { - /* PSMI - Pad Selection for Multiplexed Inputs */ - SIUL_PSMI_32B_tag PSMI0_3; /* offset: 0x0500 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI4_7; /* offset: 0x0504 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI8_11; /* offset: 0x0508 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI12_15; /* offset: 0x050C size: 32 bit */ - SIUL_PSMI_32B_tag PSMI16_19; /* offset: 0x0510 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI20_23; /* offset: 0x0514 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI24_27; /* offset: 0x0518 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI28_31; /* offset: 0x051C size: 32 bit */ - SIUL_PSMI_32B_tag PSMI32_35; /* offset: 0x0520 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI36_39; /* offset: 0x0524 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI40_43; /* offset: 0x0528 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI44_47; /* offset: 0x052C size: 32 bit */ - SIUL_PSMI_32B_tag PSMI48_51; /* offset: 0x0530 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI52_55; /* offset: 0x0534 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI56_59; /* offset: 0x0538 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI60_63; /* offset: 0x053C size: 32 bit */ - SIUL_PSMI_32B_tag PSMI64_67; /* offset: 0x0540 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI68_71; /* offset: 0x0544 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI72_75; /* offset: 0x0548 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI76_79; /* offset: 0x054C size: 32 bit */ - SIUL_PSMI_32B_tag PSMI80_83; /* offset: 0x0550 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI84_87; /* offset: 0x0554 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI88_91; /* offset: 0x0558 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI92_95; /* offset: 0x055C size: 32 bit */ - SIUL_PSMI_32B_tag PSMI96_99; /* offset: 0x0560 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI100_103; /* offset: 0x0564 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI104_107; /* offset: 0x0568 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI108_111; /* offset: 0x056C size: 32 bit */ - SIUL_PSMI_32B_tag PSMI112_115; /* offset: 0x0570 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI116_119; /* offset: 0x0574 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI120_123; /* offset: 0x0578 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI124_127; /* offset: 0x057C size: 32 bit */ - SIUL_PSMI_32B_tag PSMI128_131; /* offset: 0x0580 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI132_135; /* offset: 0x0584 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI136_139; /* offset: 0x0588 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI140_143; /* offset: 0x058C size: 32 bit */ - SIUL_PSMI_32B_tag PSMI144_147; /* offset: 0x0590 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI148_151; /* offset: 0x0594 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI152_155; /* offset: 0x0598 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI156_159; /* offset: 0x059C size: 32 bit */ - SIUL_PSMI_32B_tag PSMI160_163; /* offset: 0x05A0 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI164_167; /* offset: 0x05A4 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI168_171; /* offset: 0x05A8 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI172_175; /* offset: 0x05AC size: 32 bit */ - SIUL_PSMI_32B_tag PSMI176_179; /* offset: 0x05B0 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI180_183; /* offset: 0x05B4 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI184_187; /* offset: 0x05B8 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI188_191; /* offset: 0x05BC size: 32 bit */ - SIUL_PSMI_32B_tag PSMI192_195; /* offset: 0x05C0 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI196_199; /* offset: 0x05C4 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI200_203; /* offset: 0x05C8 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI204_207; /* offset: 0x05CC size: 32 bit */ - SIUL_PSMI_32B_tag PSMI208_211; /* offset: 0x05D0 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI212_215; /* offset: 0x05D4 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI216_219; /* offset: 0x05D8 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI220_223; /* offset: 0x05DC size: 32 bit */ - SIUL_PSMI_32B_tag PSMI224_227; /* offset: 0x05E0 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI228_231; /* offset: 0x05E4 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI232_235; /* offset: 0x05E8 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI236_239; /* offset: 0x05EC size: 32 bit */ - SIUL_PSMI_32B_tag PSMI240_243; /* offset: 0x05F0 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI244_247; /* offset: 0x05F4 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI248_251; /* offset: 0x05F8 size: 32 bit */ - SIUL_PSMI_32B_tag PSMI252_255; /* offset: 0x05FC size: 32 bit */ - }; - - struct { - /* PSMI - Pad Selection for Multiplexed Inputs */ - SIUL_PSMI_8B_tag PSMI0; /* offset: 0x0500 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI1; /* offset: 0x0501 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI2; /* offset: 0x0502 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI3; /* offset: 0x0503 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI4; /* offset: 0x0504 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI5; /* offset: 0x0505 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI6; /* offset: 0x0506 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI7; /* offset: 0x0507 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI8; /* offset: 0x0508 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI9; /* offset: 0x0509 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI10; /* offset: 0x050A size: 8 bit */ - SIUL_PSMI_8B_tag PSMI11; /* offset: 0x050B size: 8 bit */ - SIUL_PSMI_8B_tag PSMI12; /* offset: 0x050C size: 8 bit */ - SIUL_PSMI_8B_tag PSMI13; /* offset: 0x050D size: 8 bit */ - SIUL_PSMI_8B_tag PSMI14; /* offset: 0x050E size: 8 bit */ - SIUL_PSMI_8B_tag PSMI15; /* offset: 0x050F size: 8 bit */ - SIUL_PSMI_8B_tag PSMI16; /* offset: 0x0510 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI17; /* offset: 0x0511 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI18; /* offset: 0x0512 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI19; /* offset: 0x0513 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI20; /* offset: 0x0514 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI21; /* offset: 0x0515 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI22; /* offset: 0x0516 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI23; /* offset: 0x0517 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI24; /* offset: 0x0518 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI25; /* offset: 0x0519 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI26; /* offset: 0x051A size: 8 bit */ - SIUL_PSMI_8B_tag PSMI27; /* offset: 0x051B size: 8 bit */ - SIUL_PSMI_8B_tag PSMI28; /* offset: 0x051C size: 8 bit */ - SIUL_PSMI_8B_tag PSMI29; /* offset: 0x051D size: 8 bit */ - SIUL_PSMI_8B_tag PSMI30; /* offset: 0x051E size: 8 bit */ - SIUL_PSMI_8B_tag PSMI31; /* offset: 0x051F size: 8 bit */ - SIUL_PSMI_8B_tag PSMI32; /* offset: 0x0520 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI33; /* offset: 0x0521 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI34; /* offset: 0x0522 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI35; /* offset: 0x0523 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI36; /* offset: 0x0524 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI37; /* offset: 0x0525 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI38; /* offset: 0x0526 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI39; /* offset: 0x0527 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI40; /* offset: 0x0528 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI41; /* offset: 0x0529 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI42; /* offset: 0x052A size: 8 bit */ - SIUL_PSMI_8B_tag PSMI43; /* offset: 0x052B size: 8 bit */ - SIUL_PSMI_8B_tag PSMI44; /* offset: 0x052C size: 8 bit */ - SIUL_PSMI_8B_tag PSMI45; /* offset: 0x052D size: 8 bit */ - SIUL_PSMI_8B_tag PSMI46; /* offset: 0x052E size: 8 bit */ - SIUL_PSMI_8B_tag PSMI47; /* offset: 0x052F size: 8 bit */ - SIUL_PSMI_8B_tag PSMI48; /* offset: 0x0530 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI49; /* offset: 0x0531 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI50; /* offset: 0x0532 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI51; /* offset: 0x0533 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI52; /* offset: 0x0534 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI53; /* offset: 0x0535 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI54; /* offset: 0x0536 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI55; /* offset: 0x0537 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI56; /* offset: 0x0538 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI57; /* offset: 0x0539 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI58; /* offset: 0x053A size: 8 bit */ - SIUL_PSMI_8B_tag PSMI59; /* offset: 0x053B size: 8 bit */ - SIUL_PSMI_8B_tag PSMI60; /* offset: 0x053C size: 8 bit */ - SIUL_PSMI_8B_tag PSMI61; /* offset: 0x053D size: 8 bit */ - SIUL_PSMI_8B_tag PSMI62; /* offset: 0x053E size: 8 bit */ - SIUL_PSMI_8B_tag PSMI63; /* offset: 0x053F size: 8 bit */ - SIUL_PSMI_8B_tag PSMI64; /* offset: 0x0540 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI65; /* offset: 0x0541 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI66; /* offset: 0x0542 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI67; /* offset: 0x0543 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI68; /* offset: 0x0544 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI69; /* offset: 0x0545 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI70; /* offset: 0x0546 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI71; /* offset: 0x0547 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI72; /* offset: 0x0548 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI73; /* offset: 0x0549 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI74; /* offset: 0x054A size: 8 bit */ - SIUL_PSMI_8B_tag PSMI75; /* offset: 0x054B size: 8 bit */ - SIUL_PSMI_8B_tag PSMI76; /* offset: 0x054C size: 8 bit */ - SIUL_PSMI_8B_tag PSMI77; /* offset: 0x054D size: 8 bit */ - SIUL_PSMI_8B_tag PSMI78; /* offset: 0x054E size: 8 bit */ - SIUL_PSMI_8B_tag PSMI79; /* offset: 0x054F size: 8 bit */ - SIUL_PSMI_8B_tag PSMI80; /* offset: 0x0550 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI81; /* offset: 0x0551 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI82; /* offset: 0x0552 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI83; /* offset: 0x0553 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI84; /* offset: 0x0554 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI85; /* offset: 0x0555 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI86; /* offset: 0x0556 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI87; /* offset: 0x0557 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI88; /* offset: 0x0558 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI89; /* offset: 0x0559 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI90; /* offset: 0x055A size: 8 bit */ - SIUL_PSMI_8B_tag PSMI91; /* offset: 0x055B size: 8 bit */ - SIUL_PSMI_8B_tag PSMI92; /* offset: 0x055C size: 8 bit */ - SIUL_PSMI_8B_tag PSMI93; /* offset: 0x055D size: 8 bit */ - SIUL_PSMI_8B_tag PSMI94; /* offset: 0x055E size: 8 bit */ - SIUL_PSMI_8B_tag PSMI95; /* offset: 0x055F size: 8 bit */ - SIUL_PSMI_8B_tag PSMI96; /* offset: 0x0560 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI97; /* offset: 0x0561 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI98; /* offset: 0x0562 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI99; /* offset: 0x0563 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI100; /* offset: 0x0564 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI101; /* offset: 0x0565 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI102; /* offset: 0x0566 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI103; /* offset: 0x0567 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI104; /* offset: 0x0568 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI105; /* offset: 0x0569 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI106; /* offset: 0x056A size: 8 bit */ - SIUL_PSMI_8B_tag PSMI107; /* offset: 0x056B size: 8 bit */ - SIUL_PSMI_8B_tag PSMI108; /* offset: 0x056C size: 8 bit */ - SIUL_PSMI_8B_tag PSMI109; /* offset: 0x056D size: 8 bit */ - SIUL_PSMI_8B_tag PSMI110; /* offset: 0x056E size: 8 bit */ - SIUL_PSMI_8B_tag PSMI111; /* offset: 0x056F size: 8 bit */ - SIUL_PSMI_8B_tag PSMI112; /* offset: 0x0570 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI113; /* offset: 0x0571 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI114; /* offset: 0x0572 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI115; /* offset: 0x0573 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI116; /* offset: 0x0574 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI117; /* offset: 0x0575 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI118; /* offset: 0x0576 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI119; /* offset: 0x0577 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI120; /* offset: 0x0578 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI121; /* offset: 0x0579 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI122; /* offset: 0x057A size: 8 bit */ - SIUL_PSMI_8B_tag PSMI123; /* offset: 0x057B size: 8 bit */ - SIUL_PSMI_8B_tag PSMI124; /* offset: 0x057C size: 8 bit */ - SIUL_PSMI_8B_tag PSMI125; /* offset: 0x057D size: 8 bit */ - SIUL_PSMI_8B_tag PSMI126; /* offset: 0x057E size: 8 bit */ - SIUL_PSMI_8B_tag PSMI127; /* offset: 0x057F size: 8 bit */ - SIUL_PSMI_8B_tag PSMI128; /* offset: 0x0580 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI129; /* offset: 0x0581 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI130; /* offset: 0x0582 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI131; /* offset: 0x0583 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI132; /* offset: 0x0584 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI133; /* offset: 0x0585 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI134; /* offset: 0x0586 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI135; /* offset: 0x0587 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI136; /* offset: 0x0588 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI137; /* offset: 0x0589 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI138; /* offset: 0x058A size: 8 bit */ - SIUL_PSMI_8B_tag PSMI139; /* offset: 0x058B size: 8 bit */ - SIUL_PSMI_8B_tag PSMI140; /* offset: 0x058C size: 8 bit */ - SIUL_PSMI_8B_tag PSMI141; /* offset: 0x058D size: 8 bit */ - SIUL_PSMI_8B_tag PSMI142; /* offset: 0x058E size: 8 bit */ - SIUL_PSMI_8B_tag PSMI143; /* offset: 0x058F size: 8 bit */ - SIUL_PSMI_8B_tag PSMI144; /* offset: 0x0590 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI145; /* offset: 0x0591 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI146; /* offset: 0x0592 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI147; /* offset: 0x0593 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI148; /* offset: 0x0594 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI149; /* offset: 0x0595 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI150; /* offset: 0x0596 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI151; /* offset: 0x0597 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI152; /* offset: 0x0598 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI153; /* offset: 0x0599 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI154; /* offset: 0x059A size: 8 bit */ - SIUL_PSMI_8B_tag PSMI155; /* offset: 0x059B size: 8 bit */ - SIUL_PSMI_8B_tag PSMI156; /* offset: 0x059C size: 8 bit */ - SIUL_PSMI_8B_tag PSMI157; /* offset: 0x059D size: 8 bit */ - SIUL_PSMI_8B_tag PSMI158; /* offset: 0x059E size: 8 bit */ - SIUL_PSMI_8B_tag PSMI159; /* offset: 0x059F size: 8 bit */ - SIUL_PSMI_8B_tag PSMI160; /* offset: 0x05A0 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI161; /* offset: 0x05A1 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI162; /* offset: 0x05A2 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI163; /* offset: 0x05A3 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI164; /* offset: 0x05A4 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI165; /* offset: 0x05A5 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI166; /* offset: 0x05A6 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI167; /* offset: 0x05A7 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI168; /* offset: 0x05A8 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI169; /* offset: 0x05A9 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI170; /* offset: 0x05AA size: 8 bit */ - SIUL_PSMI_8B_tag PSMI171; /* offset: 0x05AB size: 8 bit */ - SIUL_PSMI_8B_tag PSMI172; /* offset: 0x05AC size: 8 bit */ - SIUL_PSMI_8B_tag PSMI173; /* offset: 0x05AD size: 8 bit */ - SIUL_PSMI_8B_tag PSMI174; /* offset: 0x05AE size: 8 bit */ - SIUL_PSMI_8B_tag PSMI175; /* offset: 0x05AF size: 8 bit */ - SIUL_PSMI_8B_tag PSMI176; /* offset: 0x05B0 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI177; /* offset: 0x05B1 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI178; /* offset: 0x05B2 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI179; /* offset: 0x05B3 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI180; /* offset: 0x05B4 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI181; /* offset: 0x05B5 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI182; /* offset: 0x05B6 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI183; /* offset: 0x05B7 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI184; /* offset: 0x05B8 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI185; /* offset: 0x05B9 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI186; /* offset: 0x05BA size: 8 bit */ - SIUL_PSMI_8B_tag PSMI187; /* offset: 0x05BB size: 8 bit */ - SIUL_PSMI_8B_tag PSMI188; /* offset: 0x05BC size: 8 bit */ - SIUL_PSMI_8B_tag PSMI189; /* offset: 0x05BD size: 8 bit */ - SIUL_PSMI_8B_tag PSMI190; /* offset: 0x05BE size: 8 bit */ - SIUL_PSMI_8B_tag PSMI191; /* offset: 0x05BF size: 8 bit */ - SIUL_PSMI_8B_tag PSMI192; /* offset: 0x05C0 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI193; /* offset: 0x05C1 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI194; /* offset: 0x05C2 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI195; /* offset: 0x05C3 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI196; /* offset: 0x05C4 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI197; /* offset: 0x05C5 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI198; /* offset: 0x05C6 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI199; /* offset: 0x05C7 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI200; /* offset: 0x05C8 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI201; /* offset: 0x05C9 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI202; /* offset: 0x05CA size: 8 bit */ - SIUL_PSMI_8B_tag PSMI203; /* offset: 0x05CB size: 8 bit */ - SIUL_PSMI_8B_tag PSMI204; /* offset: 0x05CC size: 8 bit */ - SIUL_PSMI_8B_tag PSMI205; /* offset: 0x05CD size: 8 bit */ - SIUL_PSMI_8B_tag PSMI206; /* offset: 0x05CE size: 8 bit */ - SIUL_PSMI_8B_tag PSMI207; /* offset: 0x05CF size: 8 bit */ - SIUL_PSMI_8B_tag PSMI208; /* offset: 0x05D0 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI209; /* offset: 0x05D1 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI210; /* offset: 0x05D2 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI211; /* offset: 0x05D3 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI212; /* offset: 0x05D4 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI213; /* offset: 0x05D5 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI214; /* offset: 0x05D6 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI215; /* offset: 0x05D7 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI216; /* offset: 0x05D8 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI217; /* offset: 0x05D9 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI218; /* offset: 0x05DA size: 8 bit */ - SIUL_PSMI_8B_tag PSMI219; /* offset: 0x05DB size: 8 bit */ - SIUL_PSMI_8B_tag PSMI220; /* offset: 0x05DC size: 8 bit */ - SIUL_PSMI_8B_tag PSMI221; /* offset: 0x05DD size: 8 bit */ - SIUL_PSMI_8B_tag PSMI222; /* offset: 0x05DE size: 8 bit */ - SIUL_PSMI_8B_tag PSMI223; /* offset: 0x05DF size: 8 bit */ - SIUL_PSMI_8B_tag PSMI224; /* offset: 0x05E0 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI225; /* offset: 0x05E1 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI226; /* offset: 0x05E2 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI227; /* offset: 0x05E3 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI228; /* offset: 0x05E4 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI229; /* offset: 0x05E5 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI230; /* offset: 0x05E6 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI231; /* offset: 0x05E7 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI232; /* offset: 0x05E8 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI233; /* offset: 0x05E9 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI234; /* offset: 0x05EA size: 8 bit */ - SIUL_PSMI_8B_tag PSMI235; /* offset: 0x05EB size: 8 bit */ - SIUL_PSMI_8B_tag PSMI236; /* offset: 0x05EC size: 8 bit */ - SIUL_PSMI_8B_tag PSMI237; /* offset: 0x05ED size: 8 bit */ - SIUL_PSMI_8B_tag PSMI238; /* offset: 0x05EE size: 8 bit */ - SIUL_PSMI_8B_tag PSMI239; /* offset: 0x05EF size: 8 bit */ - SIUL_PSMI_8B_tag PSMI240; /* offset: 0x05F0 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI241; /* offset: 0x05F1 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI242; /* offset: 0x05F2 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI243; /* offset: 0x05F3 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI244; /* offset: 0x05F4 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI245; /* offset: 0x05F5 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI246; /* offset: 0x05F6 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI247; /* offset: 0x05F7 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI248; /* offset: 0x05F8 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI249; /* offset: 0x05F9 size: 8 bit */ - SIUL_PSMI_8B_tag PSMI250; /* offset: 0x05FA size: 8 bit */ - SIUL_PSMI_8B_tag PSMI251; /* offset: 0x05FB size: 8 bit */ - SIUL_PSMI_8B_tag PSMI252; /* offset: 0x05FC size: 8 bit */ - SIUL_PSMI_8B_tag PSMI253; /* offset: 0x05FD size: 8 bit */ - SIUL_PSMI_8B_tag PSMI254; /* offset: 0x05FE size: 8 bit */ - SIUL_PSMI_8B_tag PSMI255; /* offset: 0x05FF size: 8 bit */ - }; - - }; - union { - /* GPDO - GPIO Pad Data Output Register */ - SIUL_GPDO_32B_tag GPDO_32B[128]; /* offset: 0x0600 (0x0004 x 128) */ - - /* GPDO - GPIO Pad Data Output Register */ - SIUL_GPDO_8B_tag GPDO[512]; /* offset: 0x0600 (0x0001 x 512) */ - - struct { - /* GPDO - GPIO Pad Data Output Register */ - SIUL_GPDO_32B_tag GPDO0_3; /* offset: 0x0600 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO4_7; /* offset: 0x0604 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO8_11; /* offset: 0x0608 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO12_15; /* offset: 0x060C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO16_19; /* offset: 0x0610 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO20_23; /* offset: 0x0614 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO24_27; /* offset: 0x0618 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO28_31; /* offset: 0x061C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO32_35; /* offset: 0x0620 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO36_39; /* offset: 0x0624 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO40_43; /* offset: 0x0628 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO44_47; /* offset: 0x062C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO48_51; /* offset: 0x0630 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO52_55; /* offset: 0x0634 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO56_59; /* offset: 0x0638 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO60_63; /* offset: 0x063C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO64_67; /* offset: 0x0640 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO68_71; /* offset: 0x0644 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO72_75; /* offset: 0x0648 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO76_79; /* offset: 0x064C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO80_83; /* offset: 0x0650 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO84_87; /* offset: 0x0654 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO88_91; /* offset: 0x0658 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO92_95; /* offset: 0x065C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO96_99; /* offset: 0x0660 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO100_103; /* offset: 0x0664 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO104_107; /* offset: 0x0668 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO108_111; /* offset: 0x066C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO112_115; /* offset: 0x0670 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO116_119; /* offset: 0x0674 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO120_123; /* offset: 0x0678 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO124_127; /* offset: 0x067C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO128_131; /* offset: 0x0680 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO132_135; /* offset: 0x0684 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO136_139; /* offset: 0x0688 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO140_143; /* offset: 0x068C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO144_147; /* offset: 0x0690 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO148_151; /* offset: 0x0694 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO152_155; /* offset: 0x0698 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO156_159; /* offset: 0x069C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO160_163; /* offset: 0x06A0 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO164_167; /* offset: 0x06A4 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO168_171; /* offset: 0x06A8 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO172_175; /* offset: 0x06AC size: 32 bit */ - SIUL_GPDO_32B_tag GPDO176_179; /* offset: 0x06B0 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO180_183; /* offset: 0x06B4 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO184_187; /* offset: 0x06B8 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO188_191; /* offset: 0x06BC size: 32 bit */ - SIUL_GPDO_32B_tag GPDO192_195; /* offset: 0x06C0 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO196_199; /* offset: 0x06C4 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO200_203; /* offset: 0x06C8 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO204_207; /* offset: 0x06CC size: 32 bit */ - SIUL_GPDO_32B_tag GPDO208_211; /* offset: 0x06D0 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO212_215; /* offset: 0x06D4 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO216_219; /* offset: 0x06D8 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO220_223; /* offset: 0x06DC size: 32 bit */ - SIUL_GPDO_32B_tag GPDO224_227; /* offset: 0x06E0 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO228_231; /* offset: 0x06E4 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO232_235; /* offset: 0x06E8 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO236_239; /* offset: 0x06EC size: 32 bit */ - SIUL_GPDO_32B_tag GPDO240_243; /* offset: 0x06F0 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO244_247; /* offset: 0x06F4 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO248_251; /* offset: 0x06F8 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO252_255; /* offset: 0x06FC size: 32 bit */ - SIUL_GPDO_32B_tag GPDO256_259; /* offset: 0x0700 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO260_263; /* offset: 0x0704 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO264_267; /* offset: 0x0708 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO268_271; /* offset: 0x070C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO272_275; /* offset: 0x0710 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO276_279; /* offset: 0x0714 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO280_283; /* offset: 0x0718 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO284_287; /* offset: 0x071C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO288_291; /* offset: 0x0720 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO292_295; /* offset: 0x0724 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO296_299; /* offset: 0x0728 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO300_303; /* offset: 0x072C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO304_307; /* offset: 0x0730 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO308_311; /* offset: 0x0734 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO312_315; /* offset: 0x0738 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO316_319; /* offset: 0x073C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO320_323; /* offset: 0x0740 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO324_327; /* offset: 0x0744 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO328_331; /* offset: 0x0748 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO332_335; /* offset: 0x074C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO336_339; /* offset: 0x0750 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO340_343; /* offset: 0x0754 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO344_347; /* offset: 0x0758 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO348_351; /* offset: 0x075C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO352_355; /* offset: 0x0760 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO356_359; /* offset: 0x0764 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO360_363; /* offset: 0x0768 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO364_367; /* offset: 0x076C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO368_371; /* offset: 0x0770 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO372_375; /* offset: 0x0774 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO376_379; /* offset: 0x0778 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO380_383; /* offset: 0x077C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO384_387; /* offset: 0x0780 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO388_391; /* offset: 0x0784 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO392_395; /* offset: 0x0788 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO396_399; /* offset: 0x078C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO400_403; /* offset: 0x0790 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO404_407; /* offset: 0x0794 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO408_411; /* offset: 0x0798 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO412_415; /* offset: 0x079C size: 32 bit */ - SIUL_GPDO_32B_tag GPDO416_419; /* offset: 0x07A0 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO420_423; /* offset: 0x07A4 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO424_427; /* offset: 0x07A8 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO428_431; /* offset: 0x07AC size: 32 bit */ - SIUL_GPDO_32B_tag GPDO432_435; /* offset: 0x07B0 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO436_439; /* offset: 0x07B4 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO440_443; /* offset: 0x07B8 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO444_447; /* offset: 0x07BC size: 32 bit */ - SIUL_GPDO_32B_tag GPDO448_451; /* offset: 0x07C0 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO452_455; /* offset: 0x07C4 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO456_459; /* offset: 0x07C8 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO460_463; /* offset: 0x07CC size: 32 bit */ - SIUL_GPDO_32B_tag GPDO464_467; /* offset: 0x07D0 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO468_471; /* offset: 0x07D4 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO472_475; /* offset: 0x07D8 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO476_479; /* offset: 0x07DC size: 32 bit */ - SIUL_GPDO_32B_tag GPDO480_483; /* offset: 0x07E0 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO484_487; /* offset: 0x07E4 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO488_491; /* offset: 0x07E8 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO492_495; /* offset: 0x07EC size: 32 bit */ - SIUL_GPDO_32B_tag GPDO496_499; /* offset: 0x07F0 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO500_503; /* offset: 0x07F4 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO504_507; /* offset: 0x07F8 size: 32 bit */ - SIUL_GPDO_32B_tag GPDO508_511; /* offset: 0x07FC size: 32 bit */ - }; - - struct { - /* GPDO - GPIO Pad Data Output Register */ - SIUL_GPDO_8B_tag GPDO0; /* offset: 0x0600 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO1; /* offset: 0x0601 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO2; /* offset: 0x0602 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO3; /* offset: 0x0603 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO4; /* offset: 0x0604 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO5; /* offset: 0x0605 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO6; /* offset: 0x0606 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO7; /* offset: 0x0607 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO8; /* offset: 0x0608 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO9; /* offset: 0x0609 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO10; /* offset: 0x060A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO11; /* offset: 0x060B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO12; /* offset: 0x060C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO13; /* offset: 0x060D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO14; /* offset: 0x060E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO15; /* offset: 0x060F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO16; /* offset: 0x0610 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO17; /* offset: 0x0611 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO18; /* offset: 0x0612 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO19; /* offset: 0x0613 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO20; /* offset: 0x0614 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO21; /* offset: 0x0615 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO22; /* offset: 0x0616 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO23; /* offset: 0x0617 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO24; /* offset: 0x0618 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO25; /* offset: 0x0619 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO26; /* offset: 0x061A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO27; /* offset: 0x061B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO28; /* offset: 0x061C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO29; /* offset: 0x061D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO30; /* offset: 0x061E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO31; /* offset: 0x061F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO32; /* offset: 0x0620 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO33; /* offset: 0x0621 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO34; /* offset: 0x0622 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO35; /* offset: 0x0623 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO36; /* offset: 0x0624 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO37; /* offset: 0x0625 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO38; /* offset: 0x0626 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO39; /* offset: 0x0627 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO40; /* offset: 0x0628 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO41; /* offset: 0x0629 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO42; /* offset: 0x062A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO43; /* offset: 0x062B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO44; /* offset: 0x062C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO45; /* offset: 0x062D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO46; /* offset: 0x062E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO47; /* offset: 0x062F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO48; /* offset: 0x0630 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO49; /* offset: 0x0631 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO50; /* offset: 0x0632 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO51; /* offset: 0x0633 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO52; /* offset: 0x0634 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO53; /* offset: 0x0635 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO54; /* offset: 0x0636 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO55; /* offset: 0x0637 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO56; /* offset: 0x0638 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO57; /* offset: 0x0639 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO58; /* offset: 0x063A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO59; /* offset: 0x063B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO60; /* offset: 0x063C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO61; /* offset: 0x063D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO62; /* offset: 0x063E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO63; /* offset: 0x063F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO64; /* offset: 0x0640 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO65; /* offset: 0x0641 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO66; /* offset: 0x0642 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO67; /* offset: 0x0643 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO68; /* offset: 0x0644 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO69; /* offset: 0x0645 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO70; /* offset: 0x0646 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO71; /* offset: 0x0647 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO72; /* offset: 0x0648 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO73; /* offset: 0x0649 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO74; /* offset: 0x064A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO75; /* offset: 0x064B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO76; /* offset: 0x064C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO77; /* offset: 0x064D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO78; /* offset: 0x064E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO79; /* offset: 0x064F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO80; /* offset: 0x0650 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO81; /* offset: 0x0651 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO82; /* offset: 0x0652 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO83; /* offset: 0x0653 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO84; /* offset: 0x0654 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO85; /* offset: 0x0655 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO86; /* offset: 0x0656 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO87; /* offset: 0x0657 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO88; /* offset: 0x0658 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO89; /* offset: 0x0659 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO90; /* offset: 0x065A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO91; /* offset: 0x065B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO92; /* offset: 0x065C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO93; /* offset: 0x065D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO94; /* offset: 0x065E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO95; /* offset: 0x065F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO96; /* offset: 0x0660 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO97; /* offset: 0x0661 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO98; /* offset: 0x0662 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO99; /* offset: 0x0663 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO100; /* offset: 0x0664 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO101; /* offset: 0x0665 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO102; /* offset: 0x0666 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO103; /* offset: 0x0667 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO104; /* offset: 0x0668 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO105; /* offset: 0x0669 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO106; /* offset: 0x066A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO107; /* offset: 0x066B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO108; /* offset: 0x066C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO109; /* offset: 0x066D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO110; /* offset: 0x066E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO111; /* offset: 0x066F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO112; /* offset: 0x0670 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO113; /* offset: 0x0671 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO114; /* offset: 0x0672 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO115; /* offset: 0x0673 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO116; /* offset: 0x0674 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO117; /* offset: 0x0675 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO118; /* offset: 0x0676 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO119; /* offset: 0x0677 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO120; /* offset: 0x0678 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO121; /* offset: 0x0679 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO122; /* offset: 0x067A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO123; /* offset: 0x067B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO124; /* offset: 0x067C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO125; /* offset: 0x067D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO126; /* offset: 0x067E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO127; /* offset: 0x067F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO128; /* offset: 0x0680 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO129; /* offset: 0x0681 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO130; /* offset: 0x0682 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO131; /* offset: 0x0683 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO132; /* offset: 0x0684 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO133; /* offset: 0x0685 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO134; /* offset: 0x0686 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO135; /* offset: 0x0687 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO136; /* offset: 0x0688 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO137; /* offset: 0x0689 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO138; /* offset: 0x068A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO139; /* offset: 0x068B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO140; /* offset: 0x068C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO141; /* offset: 0x068D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO142; /* offset: 0x068E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO143; /* offset: 0x068F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO144; /* offset: 0x0690 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO145; /* offset: 0x0691 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO146; /* offset: 0x0692 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO147; /* offset: 0x0693 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO148; /* offset: 0x0694 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO149; /* offset: 0x0695 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO150; /* offset: 0x0696 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO151; /* offset: 0x0697 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO152; /* offset: 0x0698 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO153; /* offset: 0x0699 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO154; /* offset: 0x069A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO155; /* offset: 0x069B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO156; /* offset: 0x069C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO157; /* offset: 0x069D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO158; /* offset: 0x069E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO159; /* offset: 0x069F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO160; /* offset: 0x06A0 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO161; /* offset: 0x06A1 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO162; /* offset: 0x06A2 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO163; /* offset: 0x06A3 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO164; /* offset: 0x06A4 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO165; /* offset: 0x06A5 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO166; /* offset: 0x06A6 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO167; /* offset: 0x06A7 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO168; /* offset: 0x06A8 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO169; /* offset: 0x06A9 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO170; /* offset: 0x06AA size: 8 bit */ - SIUL_GPDO_8B_tag GPDO171; /* offset: 0x06AB size: 8 bit */ - SIUL_GPDO_8B_tag GPDO172; /* offset: 0x06AC size: 8 bit */ - SIUL_GPDO_8B_tag GPDO173; /* offset: 0x06AD size: 8 bit */ - SIUL_GPDO_8B_tag GPDO174; /* offset: 0x06AE size: 8 bit */ - SIUL_GPDO_8B_tag GPDO175; /* offset: 0x06AF size: 8 bit */ - SIUL_GPDO_8B_tag GPDO176; /* offset: 0x06B0 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO177; /* offset: 0x06B1 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO178; /* offset: 0x06B2 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO179; /* offset: 0x06B3 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO180; /* offset: 0x06B4 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO181; /* offset: 0x06B5 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO182; /* offset: 0x06B6 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO183; /* offset: 0x06B7 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO184; /* offset: 0x06B8 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO185; /* offset: 0x06B9 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO186; /* offset: 0x06BA size: 8 bit */ - SIUL_GPDO_8B_tag GPDO187; /* offset: 0x06BB size: 8 bit */ - SIUL_GPDO_8B_tag GPDO188; /* offset: 0x06BC size: 8 bit */ - SIUL_GPDO_8B_tag GPDO189; /* offset: 0x06BD size: 8 bit */ - SIUL_GPDO_8B_tag GPDO190; /* offset: 0x06BE size: 8 bit */ - SIUL_GPDO_8B_tag GPDO191; /* offset: 0x06BF size: 8 bit */ - SIUL_GPDO_8B_tag GPDO192; /* offset: 0x06C0 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO193; /* offset: 0x06C1 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO194; /* offset: 0x06C2 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO195; /* offset: 0x06C3 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO196; /* offset: 0x06C4 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO197; /* offset: 0x06C5 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO198; /* offset: 0x06C6 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO199; /* offset: 0x06C7 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO200; /* offset: 0x06C8 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO201; /* offset: 0x06C9 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO202; /* offset: 0x06CA size: 8 bit */ - SIUL_GPDO_8B_tag GPDO203; /* offset: 0x06CB size: 8 bit */ - SIUL_GPDO_8B_tag GPDO204; /* offset: 0x06CC size: 8 bit */ - SIUL_GPDO_8B_tag GPDO205; /* offset: 0x06CD size: 8 bit */ - SIUL_GPDO_8B_tag GPDO206; /* offset: 0x06CE size: 8 bit */ - SIUL_GPDO_8B_tag GPDO207; /* offset: 0x06CF size: 8 bit */ - SIUL_GPDO_8B_tag GPDO208; /* offset: 0x06D0 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO209; /* offset: 0x06D1 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO210; /* offset: 0x06D2 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO211; /* offset: 0x06D3 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO212; /* offset: 0x06D4 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO213; /* offset: 0x06D5 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO214; /* offset: 0x06D6 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO215; /* offset: 0x06D7 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO216; /* offset: 0x06D8 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO217; /* offset: 0x06D9 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO218; /* offset: 0x06DA size: 8 bit */ - SIUL_GPDO_8B_tag GPDO219; /* offset: 0x06DB size: 8 bit */ - SIUL_GPDO_8B_tag GPDO220; /* offset: 0x06DC size: 8 bit */ - SIUL_GPDO_8B_tag GPDO221; /* offset: 0x06DD size: 8 bit */ - SIUL_GPDO_8B_tag GPDO222; /* offset: 0x06DE size: 8 bit */ - SIUL_GPDO_8B_tag GPDO223; /* offset: 0x06DF size: 8 bit */ - SIUL_GPDO_8B_tag GPDO224; /* offset: 0x06E0 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO225; /* offset: 0x06E1 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO226; /* offset: 0x06E2 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO227; /* offset: 0x06E3 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO228; /* offset: 0x06E4 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO229; /* offset: 0x06E5 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO230; /* offset: 0x06E6 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO231; /* offset: 0x06E7 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO232; /* offset: 0x06E8 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO233; /* offset: 0x06E9 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO234; /* offset: 0x06EA size: 8 bit */ - SIUL_GPDO_8B_tag GPDO235; /* offset: 0x06EB size: 8 bit */ - SIUL_GPDO_8B_tag GPDO236; /* offset: 0x06EC size: 8 bit */ - SIUL_GPDO_8B_tag GPDO237; /* offset: 0x06ED size: 8 bit */ - SIUL_GPDO_8B_tag GPDO238; /* offset: 0x06EE size: 8 bit */ - SIUL_GPDO_8B_tag GPDO239; /* offset: 0x06EF size: 8 bit */ - SIUL_GPDO_8B_tag GPDO240; /* offset: 0x06F0 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO241; /* offset: 0x06F1 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO242; /* offset: 0x06F2 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO243; /* offset: 0x06F3 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO244; /* offset: 0x06F4 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO245; /* offset: 0x06F5 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO246; /* offset: 0x06F6 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO247; /* offset: 0x06F7 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO248; /* offset: 0x06F8 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO249; /* offset: 0x06F9 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO250; /* offset: 0x06FA size: 8 bit */ - SIUL_GPDO_8B_tag GPDO251; /* offset: 0x06FB size: 8 bit */ - SIUL_GPDO_8B_tag GPDO252; /* offset: 0x06FC size: 8 bit */ - SIUL_GPDO_8B_tag GPDO253; /* offset: 0x06FD size: 8 bit */ - SIUL_GPDO_8B_tag GPDO254; /* offset: 0x06FE size: 8 bit */ - SIUL_GPDO_8B_tag GPDO255; /* offset: 0x06FF size: 8 bit */ - SIUL_GPDO_8B_tag GPDO256; /* offset: 0x0700 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO257; /* offset: 0x0701 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO258; /* offset: 0x0702 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO259; /* offset: 0x0703 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO260; /* offset: 0x0704 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO261; /* offset: 0x0705 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO262; /* offset: 0x0706 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO263; /* offset: 0x0707 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO264; /* offset: 0x0708 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO265; /* offset: 0x0709 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO266; /* offset: 0x070A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO267; /* offset: 0x070B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO268; /* offset: 0x070C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO269; /* offset: 0x070D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO270; /* offset: 0x070E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO271; /* offset: 0x070F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO272; /* offset: 0x0710 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO273; /* offset: 0x0711 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO274; /* offset: 0x0712 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO275; /* offset: 0x0713 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO276; /* offset: 0x0714 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO277; /* offset: 0x0715 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO278; /* offset: 0x0716 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO279; /* offset: 0x0717 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO280; /* offset: 0x0718 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO281; /* offset: 0x0719 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO282; /* offset: 0x071A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO283; /* offset: 0x071B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO284; /* offset: 0x071C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO285; /* offset: 0x071D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO286; /* offset: 0x071E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO287; /* offset: 0x071F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO288; /* offset: 0x0720 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO289; /* offset: 0x0721 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO290; /* offset: 0x0722 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO291; /* offset: 0x0723 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO292; /* offset: 0x0724 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO293; /* offset: 0x0725 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO294; /* offset: 0x0726 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO295; /* offset: 0x0727 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO296; /* offset: 0x0728 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO297; /* offset: 0x0729 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO298; /* offset: 0x072A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO299; /* offset: 0x072B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO300; /* offset: 0x072C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO301; /* offset: 0x072D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO302; /* offset: 0x072E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO303; /* offset: 0x072F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO304; /* offset: 0x0730 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO305; /* offset: 0x0731 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO306; /* offset: 0x0732 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO307; /* offset: 0x0733 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO308; /* offset: 0x0734 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO309; /* offset: 0x0735 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO310; /* offset: 0x0736 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO311; /* offset: 0x0737 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO312; /* offset: 0x0738 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO313; /* offset: 0x0739 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO314; /* offset: 0x073A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO315; /* offset: 0x073B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO316; /* offset: 0x073C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO317; /* offset: 0x073D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO318; /* offset: 0x073E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO319; /* offset: 0x073F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO320; /* offset: 0x0740 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO321; /* offset: 0x0741 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO322; /* offset: 0x0742 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO323; /* offset: 0x0743 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO324; /* offset: 0x0744 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO325; /* offset: 0x0745 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO326; /* offset: 0x0746 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO327; /* offset: 0x0747 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO328; /* offset: 0x0748 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO329; /* offset: 0x0749 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO330; /* offset: 0x074A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO331; /* offset: 0x074B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO332; /* offset: 0x074C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO333; /* offset: 0x074D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO334; /* offset: 0x074E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO335; /* offset: 0x074F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO336; /* offset: 0x0750 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO337; /* offset: 0x0751 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO338; /* offset: 0x0752 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO339; /* offset: 0x0753 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO340; /* offset: 0x0754 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO341; /* offset: 0x0755 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO342; /* offset: 0x0756 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO343; /* offset: 0x0757 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO344; /* offset: 0x0758 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO345; /* offset: 0x0759 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO346; /* offset: 0x075A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO347; /* offset: 0x075B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO348; /* offset: 0x075C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO349; /* offset: 0x075D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO350; /* offset: 0x075E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO351; /* offset: 0x075F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO352; /* offset: 0x0760 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO353; /* offset: 0x0761 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO354; /* offset: 0x0762 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO355; /* offset: 0x0763 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO356; /* offset: 0x0764 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO357; /* offset: 0x0765 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO358; /* offset: 0x0766 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO359; /* offset: 0x0767 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO360; /* offset: 0x0768 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO361; /* offset: 0x0769 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO362; /* offset: 0x076A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO363; /* offset: 0x076B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO364; /* offset: 0x076C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO365; /* offset: 0x076D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO366; /* offset: 0x076E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO367; /* offset: 0x076F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO368; /* offset: 0x0770 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO369; /* offset: 0x0771 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO370; /* offset: 0x0772 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO371; /* offset: 0x0773 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO372; /* offset: 0x0774 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO373; /* offset: 0x0775 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO374; /* offset: 0x0776 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO375; /* offset: 0x0777 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO376; /* offset: 0x0778 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO377; /* offset: 0x0779 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO378; /* offset: 0x077A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO379; /* offset: 0x077B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO380; /* offset: 0x077C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO381; /* offset: 0x077D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO382; /* offset: 0x077E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO383; /* offset: 0x077F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO384; /* offset: 0x0780 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO385; /* offset: 0x0781 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO386; /* offset: 0x0782 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO387; /* offset: 0x0783 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO388; /* offset: 0x0784 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO389; /* offset: 0x0785 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO390; /* offset: 0x0786 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO391; /* offset: 0x0787 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO392; /* offset: 0x0788 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO393; /* offset: 0x0789 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO394; /* offset: 0x078A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO395; /* offset: 0x078B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO396; /* offset: 0x078C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO397; /* offset: 0x078D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO398; /* offset: 0x078E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO399; /* offset: 0x078F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO400; /* offset: 0x0790 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO401; /* offset: 0x0791 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO402; /* offset: 0x0792 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO403; /* offset: 0x0793 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO404; /* offset: 0x0794 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO405; /* offset: 0x0795 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO406; /* offset: 0x0796 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO407; /* offset: 0x0797 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO408; /* offset: 0x0798 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO409; /* offset: 0x0799 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO410; /* offset: 0x079A size: 8 bit */ - SIUL_GPDO_8B_tag GPDO411; /* offset: 0x079B size: 8 bit */ - SIUL_GPDO_8B_tag GPDO412; /* offset: 0x079C size: 8 bit */ - SIUL_GPDO_8B_tag GPDO413; /* offset: 0x079D size: 8 bit */ - SIUL_GPDO_8B_tag GPDO414; /* offset: 0x079E size: 8 bit */ - SIUL_GPDO_8B_tag GPDO415; /* offset: 0x079F size: 8 bit */ - SIUL_GPDO_8B_tag GPDO416; /* offset: 0x07A0 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO417; /* offset: 0x07A1 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO418; /* offset: 0x07A2 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO419; /* offset: 0x07A3 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO420; /* offset: 0x07A4 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO421; /* offset: 0x07A5 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO422; /* offset: 0x07A6 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO423; /* offset: 0x07A7 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO424; /* offset: 0x07A8 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO425; /* offset: 0x07A9 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO426; /* offset: 0x07AA size: 8 bit */ - SIUL_GPDO_8B_tag GPDO427; /* offset: 0x07AB size: 8 bit */ - SIUL_GPDO_8B_tag GPDO428; /* offset: 0x07AC size: 8 bit */ - SIUL_GPDO_8B_tag GPDO429; /* offset: 0x07AD size: 8 bit */ - SIUL_GPDO_8B_tag GPDO430; /* offset: 0x07AE size: 8 bit */ - SIUL_GPDO_8B_tag GPDO431; /* offset: 0x07AF size: 8 bit */ - SIUL_GPDO_8B_tag GPDO432; /* offset: 0x07B0 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO433; /* offset: 0x07B1 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO434; /* offset: 0x07B2 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO435; /* offset: 0x07B3 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO436; /* offset: 0x07B4 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO437; /* offset: 0x07B5 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO438; /* offset: 0x07B6 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO439; /* offset: 0x07B7 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO440; /* offset: 0x07B8 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO441; /* offset: 0x07B9 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO442; /* offset: 0x07BA size: 8 bit */ - SIUL_GPDO_8B_tag GPDO443; /* offset: 0x07BB size: 8 bit */ - SIUL_GPDO_8B_tag GPDO444; /* offset: 0x07BC size: 8 bit */ - SIUL_GPDO_8B_tag GPDO445; /* offset: 0x07BD size: 8 bit */ - SIUL_GPDO_8B_tag GPDO446; /* offset: 0x07BE size: 8 bit */ - SIUL_GPDO_8B_tag GPDO447; /* offset: 0x07BF size: 8 bit */ - SIUL_GPDO_8B_tag GPDO448; /* offset: 0x07C0 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO449; /* offset: 0x07C1 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO450; /* offset: 0x07C2 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO451; /* offset: 0x07C3 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO452; /* offset: 0x07C4 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO453; /* offset: 0x07C5 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO454; /* offset: 0x07C6 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO455; /* offset: 0x07C7 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO456; /* offset: 0x07C8 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO457; /* offset: 0x07C9 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO458; /* offset: 0x07CA size: 8 bit */ - SIUL_GPDO_8B_tag GPDO459; /* offset: 0x07CB size: 8 bit */ - SIUL_GPDO_8B_tag GPDO460; /* offset: 0x07CC size: 8 bit */ - SIUL_GPDO_8B_tag GPDO461; /* offset: 0x07CD size: 8 bit */ - SIUL_GPDO_8B_tag GPDO462; /* offset: 0x07CE size: 8 bit */ - SIUL_GPDO_8B_tag GPDO463; /* offset: 0x07CF size: 8 bit */ - SIUL_GPDO_8B_tag GPDO464; /* offset: 0x07D0 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO465; /* offset: 0x07D1 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO466; /* offset: 0x07D2 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO467; /* offset: 0x07D3 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO468; /* offset: 0x07D4 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO469; /* offset: 0x07D5 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO470; /* offset: 0x07D6 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO471; /* offset: 0x07D7 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO472; /* offset: 0x07D8 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO473; /* offset: 0x07D9 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO474; /* offset: 0x07DA size: 8 bit */ - SIUL_GPDO_8B_tag GPDO475; /* offset: 0x07DB size: 8 bit */ - SIUL_GPDO_8B_tag GPDO476; /* offset: 0x07DC size: 8 bit */ - SIUL_GPDO_8B_tag GPDO477; /* offset: 0x07DD size: 8 bit */ - SIUL_GPDO_8B_tag GPDO478; /* offset: 0x07DE size: 8 bit */ - SIUL_GPDO_8B_tag GPDO479; /* offset: 0x07DF size: 8 bit */ - SIUL_GPDO_8B_tag GPDO480; /* offset: 0x07E0 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO481; /* offset: 0x07E1 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO482; /* offset: 0x07E2 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO483; /* offset: 0x07E3 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO484; /* offset: 0x07E4 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO485; /* offset: 0x07E5 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO486; /* offset: 0x07E6 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO487; /* offset: 0x07E7 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO488; /* offset: 0x07E8 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO489; /* offset: 0x07E9 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO490; /* offset: 0x07EA size: 8 bit */ - SIUL_GPDO_8B_tag GPDO491; /* offset: 0x07EB size: 8 bit */ - SIUL_GPDO_8B_tag GPDO492; /* offset: 0x07EC size: 8 bit */ - SIUL_GPDO_8B_tag GPDO493; /* offset: 0x07ED size: 8 bit */ - SIUL_GPDO_8B_tag GPDO494; /* offset: 0x07EE size: 8 bit */ - SIUL_GPDO_8B_tag GPDO495; /* offset: 0x07EF size: 8 bit */ - SIUL_GPDO_8B_tag GPDO496; /* offset: 0x07F0 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO497; /* offset: 0x07F1 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO498; /* offset: 0x07F2 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO499; /* offset: 0x07F3 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO500; /* offset: 0x07F4 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO501; /* offset: 0x07F5 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO502; /* offset: 0x07F6 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO503; /* offset: 0x07F7 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO504; /* offset: 0x07F8 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO505; /* offset: 0x07F9 size: 8 bit */ - SIUL_GPDO_8B_tag GPDO506; /* offset: 0x07FA size: 8 bit */ - SIUL_GPDO_8B_tag GPDO507; /* offset: 0x07FB size: 8 bit */ - SIUL_GPDO_8B_tag GPDO508; /* offset: 0x07FC size: 8 bit */ - SIUL_GPDO_8B_tag GPDO509; /* offset: 0x07FD size: 8 bit */ - SIUL_GPDO_8B_tag GPDO510; /* offset: 0x07FE size: 8 bit */ - SIUL_GPDO_8B_tag GPDO511; /* offset: 0x07FF size: 8 bit */ - }; - - }; - union { - /* GPDI - GPIO Pad Data Input Register */ - SIUL_GPDI_32B_tag GPDI_32B[128]; /* offset: 0x0800 (0x0004 x 128) */ - - /* GPDI - GPIO Pad Data Input Register */ - SIUL_GPDI_8B_tag GPDI[512]; /* offset: 0x0800 (0x0001 x 512) */ - - struct { - /* GPDI - GPIO Pad Data Input Register */ - SIUL_GPDI_32B_tag GPDI0_3; /* offset: 0x0800 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI4_7; /* offset: 0x0804 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI8_11; /* offset: 0x0808 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI12_15; /* offset: 0x080C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI16_19; /* offset: 0x0810 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI20_23; /* offset: 0x0814 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI24_27; /* offset: 0x0818 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI28_31; /* offset: 0x081C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI32_35; /* offset: 0x0820 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI36_39; /* offset: 0x0824 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI40_43; /* offset: 0x0828 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI44_47; /* offset: 0x082C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI48_51; /* offset: 0x0830 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI52_55; /* offset: 0x0834 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI56_59; /* offset: 0x0838 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI60_63; /* offset: 0x083C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI64_67; /* offset: 0x0840 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI68_71; /* offset: 0x0844 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI72_75; /* offset: 0x0848 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI76_79; /* offset: 0x084C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI80_83; /* offset: 0x0850 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI84_87; /* offset: 0x0854 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI88_91; /* offset: 0x0858 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI92_95; /* offset: 0x085C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI96_99; /* offset: 0x0860 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI100_103; /* offset: 0x0864 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI104_107; /* offset: 0x0868 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI108_111; /* offset: 0x086C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI112_115; /* offset: 0x0870 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI116_119; /* offset: 0x0874 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI120_123; /* offset: 0x0878 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI124_127; /* offset: 0x087C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI128_131; /* offset: 0x0880 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI132_135; /* offset: 0x0884 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI136_139; /* offset: 0x0888 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI140_143; /* offset: 0x088C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI144_147; /* offset: 0x0890 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI148_151; /* offset: 0x0894 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI152_155; /* offset: 0x0898 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI156_159; /* offset: 0x089C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI160_163; /* offset: 0x08A0 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI164_167; /* offset: 0x08A4 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI168_171; /* offset: 0x08A8 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI172_175; /* offset: 0x08AC size: 32 bit */ - SIUL_GPDI_32B_tag GPDI176_179; /* offset: 0x08B0 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI180_183; /* offset: 0x08B4 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI184_187; /* offset: 0x08B8 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI188_191; /* offset: 0x08BC size: 32 bit */ - SIUL_GPDI_32B_tag GPDI192_195; /* offset: 0x08C0 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI196_199; /* offset: 0x08C4 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI200_203; /* offset: 0x08C8 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI204_207; /* offset: 0x08CC size: 32 bit */ - SIUL_GPDI_32B_tag GPDI208_211; /* offset: 0x08D0 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI212_215; /* offset: 0x08D4 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI216_219; /* offset: 0x08D8 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI220_223; /* offset: 0x08DC size: 32 bit */ - SIUL_GPDI_32B_tag GPDI224_227; /* offset: 0x08E0 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI228_231; /* offset: 0x08E4 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI232_235; /* offset: 0x08E8 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI236_239; /* offset: 0x08EC size: 32 bit */ - SIUL_GPDI_32B_tag GPDI240_243; /* offset: 0x08F0 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI244_247; /* offset: 0x08F4 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI248_251; /* offset: 0x08F8 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI252_255; /* offset: 0x08FC size: 32 bit */ - SIUL_GPDI_32B_tag GPDI256_259; /* offset: 0x0900 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI260_263; /* offset: 0x0904 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI264_267; /* offset: 0x0908 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI268_271; /* offset: 0x090C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI272_275; /* offset: 0x0910 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI276_279; /* offset: 0x0914 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI280_283; /* offset: 0x0918 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI284_287; /* offset: 0x091C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI288_291; /* offset: 0x0920 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI292_295; /* offset: 0x0924 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI296_299; /* offset: 0x0928 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI300_303; /* offset: 0x092C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI304_307; /* offset: 0x0930 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI308_311; /* offset: 0x0934 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI312_315; /* offset: 0x0938 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI316_319; /* offset: 0x093C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI320_323; /* offset: 0x0940 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI324_327; /* offset: 0x0944 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI328_331; /* offset: 0x0948 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI332_335; /* offset: 0x094C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI336_339; /* offset: 0x0950 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI340_343; /* offset: 0x0954 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI344_347; /* offset: 0x0958 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI348_351; /* offset: 0x095C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI352_355; /* offset: 0x0960 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI356_359; /* offset: 0x0964 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI360_363; /* offset: 0x0968 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI364_367; /* offset: 0x096C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI368_371; /* offset: 0x0970 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI372_375; /* offset: 0x0974 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI376_379; /* offset: 0x0978 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI380_383; /* offset: 0x097C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI384_387; /* offset: 0x0980 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI388_391; /* offset: 0x0984 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI392_395; /* offset: 0x0988 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI396_399; /* offset: 0x098C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI400_403; /* offset: 0x0990 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI404_407; /* offset: 0x0994 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI408_411; /* offset: 0x0998 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI412_415; /* offset: 0x099C size: 32 bit */ - SIUL_GPDI_32B_tag GPDI416_419; /* offset: 0x09A0 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI420_423; /* offset: 0x09A4 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI424_427; /* offset: 0x09A8 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI428_431; /* offset: 0x09AC size: 32 bit */ - SIUL_GPDI_32B_tag GPDI432_435; /* offset: 0x09B0 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI436_439; /* offset: 0x09B4 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI440_443; /* offset: 0x09B8 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI444_447; /* offset: 0x09BC size: 32 bit */ - SIUL_GPDI_32B_tag GPDI448_451; /* offset: 0x09C0 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI452_455; /* offset: 0x09C4 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI456_459; /* offset: 0x09C8 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI460_463; /* offset: 0x09CC size: 32 bit */ - SIUL_GPDI_32B_tag GPDI464_467; /* offset: 0x09D0 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI468_471; /* offset: 0x09D4 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI472_475; /* offset: 0x09D8 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI476_479; /* offset: 0x09DC size: 32 bit */ - SIUL_GPDI_32B_tag GPDI480_483; /* offset: 0x09E0 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI484_487; /* offset: 0x09E4 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI488_491; /* offset: 0x09E8 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI492_495; /* offset: 0x09EC size: 32 bit */ - SIUL_GPDI_32B_tag GPDI496_499; /* offset: 0x09F0 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI500_503; /* offset: 0x09F4 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI504_507; /* offset: 0x09F8 size: 32 bit */ - SIUL_GPDI_32B_tag GPDI508_511; /* offset: 0x09FC size: 32 bit */ - }; - - struct { - /* GPDI - GPIO Pad Data Input Register */ - SIUL_GPDI_8B_tag GPDI0; /* offset: 0x0800 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI1; /* offset: 0x0801 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI2; /* offset: 0x0802 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI3; /* offset: 0x0803 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI4; /* offset: 0x0804 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI5; /* offset: 0x0805 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI6; /* offset: 0x0806 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI7; /* offset: 0x0807 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI8; /* offset: 0x0808 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI9; /* offset: 0x0809 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI10; /* offset: 0x080A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI11; /* offset: 0x080B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI12; /* offset: 0x080C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI13; /* offset: 0x080D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI14; /* offset: 0x080E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI15; /* offset: 0x080F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI16; /* offset: 0x0810 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI17; /* offset: 0x0811 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI18; /* offset: 0x0812 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI19; /* offset: 0x0813 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI20; /* offset: 0x0814 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI21; /* offset: 0x0815 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI22; /* offset: 0x0816 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI23; /* offset: 0x0817 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI24; /* offset: 0x0818 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI25; /* offset: 0x0819 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI26; /* offset: 0x081A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI27; /* offset: 0x081B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI28; /* offset: 0x081C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI29; /* offset: 0x081D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI30; /* offset: 0x081E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI31; /* offset: 0x081F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI32; /* offset: 0x0820 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI33; /* offset: 0x0821 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI34; /* offset: 0x0822 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI35; /* offset: 0x0823 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI36; /* offset: 0x0824 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI37; /* offset: 0x0825 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI38; /* offset: 0x0826 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI39; /* offset: 0x0827 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI40; /* offset: 0x0828 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI41; /* offset: 0x0829 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI42; /* offset: 0x082A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI43; /* offset: 0x082B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI44; /* offset: 0x082C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI45; /* offset: 0x082D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI46; /* offset: 0x082E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI47; /* offset: 0x082F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI48; /* offset: 0x0830 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI49; /* offset: 0x0831 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI50; /* offset: 0x0832 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI51; /* offset: 0x0833 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI52; /* offset: 0x0834 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI53; /* offset: 0x0835 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI54; /* offset: 0x0836 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI55; /* offset: 0x0837 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI56; /* offset: 0x0838 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI57; /* offset: 0x0839 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI58; /* offset: 0x083A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI59; /* offset: 0x083B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI60; /* offset: 0x083C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI61; /* offset: 0x083D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI62; /* offset: 0x083E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI63; /* offset: 0x083F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI64; /* offset: 0x0840 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI65; /* offset: 0x0841 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI66; /* offset: 0x0842 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI67; /* offset: 0x0843 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI68; /* offset: 0x0844 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI69; /* offset: 0x0845 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI70; /* offset: 0x0846 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI71; /* offset: 0x0847 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI72; /* offset: 0x0848 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI73; /* offset: 0x0849 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI74; /* offset: 0x084A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI75; /* offset: 0x084B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI76; /* offset: 0x084C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI77; /* offset: 0x084D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI78; /* offset: 0x084E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI79; /* offset: 0x084F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI80; /* offset: 0x0850 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI81; /* offset: 0x0851 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI82; /* offset: 0x0852 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI83; /* offset: 0x0853 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI84; /* offset: 0x0854 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI85; /* offset: 0x0855 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI86; /* offset: 0x0856 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI87; /* offset: 0x0857 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI88; /* offset: 0x0858 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI89; /* offset: 0x0859 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI90; /* offset: 0x085A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI91; /* offset: 0x085B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI92; /* offset: 0x085C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI93; /* offset: 0x085D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI94; /* offset: 0x085E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI95; /* offset: 0x085F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI96; /* offset: 0x0860 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI97; /* offset: 0x0861 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI98; /* offset: 0x0862 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI99; /* offset: 0x0863 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI100; /* offset: 0x0864 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI101; /* offset: 0x0865 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI102; /* offset: 0x0866 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI103; /* offset: 0x0867 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI104; /* offset: 0x0868 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI105; /* offset: 0x0869 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI106; /* offset: 0x086A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI107; /* offset: 0x086B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI108; /* offset: 0x086C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI109; /* offset: 0x086D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI110; /* offset: 0x086E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI111; /* offset: 0x086F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI112; /* offset: 0x0870 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI113; /* offset: 0x0871 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI114; /* offset: 0x0872 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI115; /* offset: 0x0873 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI116; /* offset: 0x0874 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI117; /* offset: 0x0875 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI118; /* offset: 0x0876 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI119; /* offset: 0x0877 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI120; /* offset: 0x0878 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI121; /* offset: 0x0879 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI122; /* offset: 0x087A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI123; /* offset: 0x087B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI124; /* offset: 0x087C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI125; /* offset: 0x087D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI126; /* offset: 0x087E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI127; /* offset: 0x087F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI128; /* offset: 0x0880 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI129; /* offset: 0x0881 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI130; /* offset: 0x0882 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI131; /* offset: 0x0883 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI132; /* offset: 0x0884 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI133; /* offset: 0x0885 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI134; /* offset: 0x0886 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI135; /* offset: 0x0887 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI136; /* offset: 0x0888 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI137; /* offset: 0x0889 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI138; /* offset: 0x088A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI139; /* offset: 0x088B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI140; /* offset: 0x088C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI141; /* offset: 0x088D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI142; /* offset: 0x088E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI143; /* offset: 0x088F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI144; /* offset: 0x0890 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI145; /* offset: 0x0891 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI146; /* offset: 0x0892 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI147; /* offset: 0x0893 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI148; /* offset: 0x0894 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI149; /* offset: 0x0895 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI150; /* offset: 0x0896 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI151; /* offset: 0x0897 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI152; /* offset: 0x0898 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI153; /* offset: 0x0899 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI154; /* offset: 0x089A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI155; /* offset: 0x089B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI156; /* offset: 0x089C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI157; /* offset: 0x089D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI158; /* offset: 0x089E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI159; /* offset: 0x089F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI160; /* offset: 0x08A0 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI161; /* offset: 0x08A1 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI162; /* offset: 0x08A2 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI163; /* offset: 0x08A3 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI164; /* offset: 0x08A4 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI165; /* offset: 0x08A5 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI166; /* offset: 0x08A6 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI167; /* offset: 0x08A7 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI168; /* offset: 0x08A8 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI169; /* offset: 0x08A9 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI170; /* offset: 0x08AA size: 8 bit */ - SIUL_GPDI_8B_tag GPDI171; /* offset: 0x08AB size: 8 bit */ - SIUL_GPDI_8B_tag GPDI172; /* offset: 0x08AC size: 8 bit */ - SIUL_GPDI_8B_tag GPDI173; /* offset: 0x08AD size: 8 bit */ - SIUL_GPDI_8B_tag GPDI174; /* offset: 0x08AE size: 8 bit */ - SIUL_GPDI_8B_tag GPDI175; /* offset: 0x08AF size: 8 bit */ - SIUL_GPDI_8B_tag GPDI176; /* offset: 0x08B0 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI177; /* offset: 0x08B1 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI178; /* offset: 0x08B2 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI179; /* offset: 0x08B3 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI180; /* offset: 0x08B4 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI181; /* offset: 0x08B5 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI182; /* offset: 0x08B6 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI183; /* offset: 0x08B7 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI184; /* offset: 0x08B8 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI185; /* offset: 0x08B9 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI186; /* offset: 0x08BA size: 8 bit */ - SIUL_GPDI_8B_tag GPDI187; /* offset: 0x08BB size: 8 bit */ - SIUL_GPDI_8B_tag GPDI188; /* offset: 0x08BC size: 8 bit */ - SIUL_GPDI_8B_tag GPDI189; /* offset: 0x08BD size: 8 bit */ - SIUL_GPDI_8B_tag GPDI190; /* offset: 0x08BE size: 8 bit */ - SIUL_GPDI_8B_tag GPDI191; /* offset: 0x08BF size: 8 bit */ - SIUL_GPDI_8B_tag GPDI192; /* offset: 0x08C0 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI193; /* offset: 0x08C1 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI194; /* offset: 0x08C2 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI195; /* offset: 0x08C3 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI196; /* offset: 0x08C4 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI197; /* offset: 0x08C5 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI198; /* offset: 0x08C6 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI199; /* offset: 0x08C7 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI200; /* offset: 0x08C8 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI201; /* offset: 0x08C9 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI202; /* offset: 0x08CA size: 8 bit */ - SIUL_GPDI_8B_tag GPDI203; /* offset: 0x08CB size: 8 bit */ - SIUL_GPDI_8B_tag GPDI204; /* offset: 0x08CC size: 8 bit */ - SIUL_GPDI_8B_tag GPDI205; /* offset: 0x08CD size: 8 bit */ - SIUL_GPDI_8B_tag GPDI206; /* offset: 0x08CE size: 8 bit */ - SIUL_GPDI_8B_tag GPDI207; /* offset: 0x08CF size: 8 bit */ - SIUL_GPDI_8B_tag GPDI208; /* offset: 0x08D0 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI209; /* offset: 0x08D1 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI210; /* offset: 0x08D2 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI211; /* offset: 0x08D3 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI212; /* offset: 0x08D4 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI213; /* offset: 0x08D5 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI214; /* offset: 0x08D6 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI215; /* offset: 0x08D7 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI216; /* offset: 0x08D8 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI217; /* offset: 0x08D9 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI218; /* offset: 0x08DA size: 8 bit */ - SIUL_GPDI_8B_tag GPDI219; /* offset: 0x08DB size: 8 bit */ - SIUL_GPDI_8B_tag GPDI220; /* offset: 0x08DC size: 8 bit */ - SIUL_GPDI_8B_tag GPDI221; /* offset: 0x08DD size: 8 bit */ - SIUL_GPDI_8B_tag GPDI222; /* offset: 0x08DE size: 8 bit */ - SIUL_GPDI_8B_tag GPDI223; /* offset: 0x08DF size: 8 bit */ - SIUL_GPDI_8B_tag GPDI224; /* offset: 0x08E0 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI225; /* offset: 0x08E1 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI226; /* offset: 0x08E2 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI227; /* offset: 0x08E3 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI228; /* offset: 0x08E4 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI229; /* offset: 0x08E5 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI230; /* offset: 0x08E6 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI231; /* offset: 0x08E7 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI232; /* offset: 0x08E8 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI233; /* offset: 0x08E9 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI234; /* offset: 0x08EA size: 8 bit */ - SIUL_GPDI_8B_tag GPDI235; /* offset: 0x08EB size: 8 bit */ - SIUL_GPDI_8B_tag GPDI236; /* offset: 0x08EC size: 8 bit */ - SIUL_GPDI_8B_tag GPDI237; /* offset: 0x08ED size: 8 bit */ - SIUL_GPDI_8B_tag GPDI238; /* offset: 0x08EE size: 8 bit */ - SIUL_GPDI_8B_tag GPDI239; /* offset: 0x08EF size: 8 bit */ - SIUL_GPDI_8B_tag GPDI240; /* offset: 0x08F0 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI241; /* offset: 0x08F1 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI242; /* offset: 0x08F2 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI243; /* offset: 0x08F3 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI244; /* offset: 0x08F4 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI245; /* offset: 0x08F5 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI246; /* offset: 0x08F6 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI247; /* offset: 0x08F7 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI248; /* offset: 0x08F8 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI249; /* offset: 0x08F9 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI250; /* offset: 0x08FA size: 8 bit */ - SIUL_GPDI_8B_tag GPDI251; /* offset: 0x08FB size: 8 bit */ - SIUL_GPDI_8B_tag GPDI252; /* offset: 0x08FC size: 8 bit */ - SIUL_GPDI_8B_tag GPDI253; /* offset: 0x08FD size: 8 bit */ - SIUL_GPDI_8B_tag GPDI254; /* offset: 0x08FE size: 8 bit */ - SIUL_GPDI_8B_tag GPDI255; /* offset: 0x08FF size: 8 bit */ - SIUL_GPDI_8B_tag GPDI256; /* offset: 0x0900 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI257; /* offset: 0x0901 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI258; /* offset: 0x0902 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI259; /* offset: 0x0903 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI260; /* offset: 0x0904 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI261; /* offset: 0x0905 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI262; /* offset: 0x0906 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI263; /* offset: 0x0907 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI264; /* offset: 0x0908 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI265; /* offset: 0x0909 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI266; /* offset: 0x090A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI267; /* offset: 0x090B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI268; /* offset: 0x090C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI269; /* offset: 0x090D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI270; /* offset: 0x090E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI271; /* offset: 0x090F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI272; /* offset: 0x0910 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI273; /* offset: 0x0911 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI274; /* offset: 0x0912 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI275; /* offset: 0x0913 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI276; /* offset: 0x0914 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI277; /* offset: 0x0915 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI278; /* offset: 0x0916 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI279; /* offset: 0x0917 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI280; /* offset: 0x0918 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI281; /* offset: 0x0919 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI282; /* offset: 0x091A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI283; /* offset: 0x091B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI284; /* offset: 0x091C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI285; /* offset: 0x091D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI286; /* offset: 0x091E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI287; /* offset: 0x091F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI288; /* offset: 0x0920 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI289; /* offset: 0x0921 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI290; /* offset: 0x0922 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI291; /* offset: 0x0923 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI292; /* offset: 0x0924 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI293; /* offset: 0x0925 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI294; /* offset: 0x0926 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI295; /* offset: 0x0927 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI296; /* offset: 0x0928 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI297; /* offset: 0x0929 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI298; /* offset: 0x092A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI299; /* offset: 0x092B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI300; /* offset: 0x092C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI301; /* offset: 0x092D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI302; /* offset: 0x092E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI303; /* offset: 0x092F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI304; /* offset: 0x0930 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI305; /* offset: 0x0931 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI306; /* offset: 0x0932 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI307; /* offset: 0x0933 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI308; /* offset: 0x0934 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI309; /* offset: 0x0935 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI310; /* offset: 0x0936 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI311; /* offset: 0x0937 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI312; /* offset: 0x0938 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI313; /* offset: 0x0939 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI314; /* offset: 0x093A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI315; /* offset: 0x093B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI316; /* offset: 0x093C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI317; /* offset: 0x093D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI318; /* offset: 0x093E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI319; /* offset: 0x093F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI320; /* offset: 0x0940 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI321; /* offset: 0x0941 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI322; /* offset: 0x0942 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI323; /* offset: 0x0943 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI324; /* offset: 0x0944 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI325; /* offset: 0x0945 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI326; /* offset: 0x0946 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI327; /* offset: 0x0947 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI328; /* offset: 0x0948 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI329; /* offset: 0x0949 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI330; /* offset: 0x094A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI331; /* offset: 0x094B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI332; /* offset: 0x094C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI333; /* offset: 0x094D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI334; /* offset: 0x094E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI335; /* offset: 0x094F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI336; /* offset: 0x0950 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI337; /* offset: 0x0951 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI338; /* offset: 0x0952 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI339; /* offset: 0x0953 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI340; /* offset: 0x0954 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI341; /* offset: 0x0955 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI342; /* offset: 0x0956 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI343; /* offset: 0x0957 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI344; /* offset: 0x0958 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI345; /* offset: 0x0959 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI346; /* offset: 0x095A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI347; /* offset: 0x095B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI348; /* offset: 0x095C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI349; /* offset: 0x095D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI350; /* offset: 0x095E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI351; /* offset: 0x095F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI352; /* offset: 0x0960 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI353; /* offset: 0x0961 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI354; /* offset: 0x0962 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI355; /* offset: 0x0963 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI356; /* offset: 0x0964 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI357; /* offset: 0x0965 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI358; /* offset: 0x0966 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI359; /* offset: 0x0967 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI360; /* offset: 0x0968 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI361; /* offset: 0x0969 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI362; /* offset: 0x096A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI363; /* offset: 0x096B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI364; /* offset: 0x096C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI365; /* offset: 0x096D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI366; /* offset: 0x096E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI367; /* offset: 0x096F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI368; /* offset: 0x0970 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI369; /* offset: 0x0971 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI370; /* offset: 0x0972 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI371; /* offset: 0x0973 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI372; /* offset: 0x0974 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI373; /* offset: 0x0975 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI374; /* offset: 0x0976 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI375; /* offset: 0x0977 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI376; /* offset: 0x0978 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI377; /* offset: 0x0979 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI378; /* offset: 0x097A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI379; /* offset: 0x097B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI380; /* offset: 0x097C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI381; /* offset: 0x097D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI382; /* offset: 0x097E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI383; /* offset: 0x097F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI384; /* offset: 0x0980 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI385; /* offset: 0x0981 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI386; /* offset: 0x0982 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI387; /* offset: 0x0983 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI388; /* offset: 0x0984 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI389; /* offset: 0x0985 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI390; /* offset: 0x0986 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI391; /* offset: 0x0987 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI392; /* offset: 0x0988 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI393; /* offset: 0x0989 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI394; /* offset: 0x098A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI395; /* offset: 0x098B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI396; /* offset: 0x098C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI397; /* offset: 0x098D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI398; /* offset: 0x098E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI399; /* offset: 0x098F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI400; /* offset: 0x0990 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI401; /* offset: 0x0991 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI402; /* offset: 0x0992 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI403; /* offset: 0x0993 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI404; /* offset: 0x0994 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI405; /* offset: 0x0995 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI406; /* offset: 0x0996 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI407; /* offset: 0x0997 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI408; /* offset: 0x0998 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI409; /* offset: 0x0999 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI410; /* offset: 0x099A size: 8 bit */ - SIUL_GPDI_8B_tag GPDI411; /* offset: 0x099B size: 8 bit */ - SIUL_GPDI_8B_tag GPDI412; /* offset: 0x099C size: 8 bit */ - SIUL_GPDI_8B_tag GPDI413; /* offset: 0x099D size: 8 bit */ - SIUL_GPDI_8B_tag GPDI414; /* offset: 0x099E size: 8 bit */ - SIUL_GPDI_8B_tag GPDI415; /* offset: 0x099F size: 8 bit */ - SIUL_GPDI_8B_tag GPDI416; /* offset: 0x09A0 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI417; /* offset: 0x09A1 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI418; /* offset: 0x09A2 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI419; /* offset: 0x09A3 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI420; /* offset: 0x09A4 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI421; /* offset: 0x09A5 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI422; /* offset: 0x09A6 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI423; /* offset: 0x09A7 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI424; /* offset: 0x09A8 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI425; /* offset: 0x09A9 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI426; /* offset: 0x09AA size: 8 bit */ - SIUL_GPDI_8B_tag GPDI427; /* offset: 0x09AB size: 8 bit */ - SIUL_GPDI_8B_tag GPDI428; /* offset: 0x09AC size: 8 bit */ - SIUL_GPDI_8B_tag GPDI429; /* offset: 0x09AD size: 8 bit */ - SIUL_GPDI_8B_tag GPDI430; /* offset: 0x09AE size: 8 bit */ - SIUL_GPDI_8B_tag GPDI431; /* offset: 0x09AF size: 8 bit */ - SIUL_GPDI_8B_tag GPDI432; /* offset: 0x09B0 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI433; /* offset: 0x09B1 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI434; /* offset: 0x09B2 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI435; /* offset: 0x09B3 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI436; /* offset: 0x09B4 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI437; /* offset: 0x09B5 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI438; /* offset: 0x09B6 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI439; /* offset: 0x09B7 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI440; /* offset: 0x09B8 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI441; /* offset: 0x09B9 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI442; /* offset: 0x09BA size: 8 bit */ - SIUL_GPDI_8B_tag GPDI443; /* offset: 0x09BB size: 8 bit */ - SIUL_GPDI_8B_tag GPDI444; /* offset: 0x09BC size: 8 bit */ - SIUL_GPDI_8B_tag GPDI445; /* offset: 0x09BD size: 8 bit */ - SIUL_GPDI_8B_tag GPDI446; /* offset: 0x09BE size: 8 bit */ - SIUL_GPDI_8B_tag GPDI447; /* offset: 0x09BF size: 8 bit */ - SIUL_GPDI_8B_tag GPDI448; /* offset: 0x09C0 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI449; /* offset: 0x09C1 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI450; /* offset: 0x09C2 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI451; /* offset: 0x09C3 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI452; /* offset: 0x09C4 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI453; /* offset: 0x09C5 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI454; /* offset: 0x09C6 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI455; /* offset: 0x09C7 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI456; /* offset: 0x09C8 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI457; /* offset: 0x09C9 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI458; /* offset: 0x09CA size: 8 bit */ - SIUL_GPDI_8B_tag GPDI459; /* offset: 0x09CB size: 8 bit */ - SIUL_GPDI_8B_tag GPDI460; /* offset: 0x09CC size: 8 bit */ - SIUL_GPDI_8B_tag GPDI461; /* offset: 0x09CD size: 8 bit */ - SIUL_GPDI_8B_tag GPDI462; /* offset: 0x09CE size: 8 bit */ - SIUL_GPDI_8B_tag GPDI463; /* offset: 0x09CF size: 8 bit */ - SIUL_GPDI_8B_tag GPDI464; /* offset: 0x09D0 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI465; /* offset: 0x09D1 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI466; /* offset: 0x09D2 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI467; /* offset: 0x09D3 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI468; /* offset: 0x09D4 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI469; /* offset: 0x09D5 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI470; /* offset: 0x09D6 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI471; /* offset: 0x09D7 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI472; /* offset: 0x09D8 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI473; /* offset: 0x09D9 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI474; /* offset: 0x09DA size: 8 bit */ - SIUL_GPDI_8B_tag GPDI475; /* offset: 0x09DB size: 8 bit */ - SIUL_GPDI_8B_tag GPDI476; /* offset: 0x09DC size: 8 bit */ - SIUL_GPDI_8B_tag GPDI477; /* offset: 0x09DD size: 8 bit */ - SIUL_GPDI_8B_tag GPDI478; /* offset: 0x09DE size: 8 bit */ - SIUL_GPDI_8B_tag GPDI479; /* offset: 0x09DF size: 8 bit */ - SIUL_GPDI_8B_tag GPDI480; /* offset: 0x09E0 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI481; /* offset: 0x09E1 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI482; /* offset: 0x09E2 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI483; /* offset: 0x09E3 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI484; /* offset: 0x09E4 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI485; /* offset: 0x09E5 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI486; /* offset: 0x09E6 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI487; /* offset: 0x09E7 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI488; /* offset: 0x09E8 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI489; /* offset: 0x09E9 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI490; /* offset: 0x09EA size: 8 bit */ - SIUL_GPDI_8B_tag GPDI491; /* offset: 0x09EB size: 8 bit */ - SIUL_GPDI_8B_tag GPDI492; /* offset: 0x09EC size: 8 bit */ - SIUL_GPDI_8B_tag GPDI493; /* offset: 0x09ED size: 8 bit */ - SIUL_GPDI_8B_tag GPDI494; /* offset: 0x09EE size: 8 bit */ - SIUL_GPDI_8B_tag GPDI495; /* offset: 0x09EF size: 8 bit */ - SIUL_GPDI_8B_tag GPDI496; /* offset: 0x09F0 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI497; /* offset: 0x09F1 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI498; /* offset: 0x09F2 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI499; /* offset: 0x09F3 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI500; /* offset: 0x09F4 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI501; /* offset: 0x09F5 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI502; /* offset: 0x09F6 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI503; /* offset: 0x09F7 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI504; /* offset: 0x09F8 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI505; /* offset: 0x09F9 size: 8 bit */ - SIUL_GPDI_8B_tag GPDI506; /* offset: 0x09FA size: 8 bit */ - SIUL_GPDI_8B_tag GPDI507; /* offset: 0x09FB size: 8 bit */ - SIUL_GPDI_8B_tag GPDI508; /* offset: 0x09FC size: 8 bit */ - SIUL_GPDI_8B_tag GPDI509; /* offset: 0x09FD size: 8 bit */ - SIUL_GPDI_8B_tag GPDI510; /* offset: 0x09FE size: 8 bit */ - SIUL_GPDI_8B_tag GPDI511; /* offset: 0x09FF size: 8 bit */ - }; - - }; - int8_t SIUL_reserved_0A00_C[512]; - union { - /* PGPDO - Parallel GPIO Pad Data Out Register */ - SIUL_PGPDO_16B_tag PGPDO[32]; /* offset: 0x0C00 (0x0002 x 32) */ - - struct { - /* PGPDO - Parallel GPIO Pad Data Out Register */ - SIUL_PGPDO_16B_tag PGPDO0; /* offset: 0x0C00 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO1; /* offset: 0x0C02 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO2; /* offset: 0x0C04 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO3; /* offset: 0x0C06 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO4; /* offset: 0x0C08 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO5; /* offset: 0x0C0A size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO6; /* offset: 0x0C0C size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO7; /* offset: 0x0C0E size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO8; /* offset: 0x0C10 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO9; /* offset: 0x0C12 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO10; /* offset: 0x0C14 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO11; /* offset: 0x0C16 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO12; /* offset: 0x0C18 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO13; /* offset: 0x0C1A size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO14; /* offset: 0x0C1C size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO15; /* offset: 0x0C1E size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO16; /* offset: 0x0C20 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO17; /* offset: 0x0C22 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO18; /* offset: 0x0C24 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO19; /* offset: 0x0C26 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO20; /* offset: 0x0C28 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO21; /* offset: 0x0C2A size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO22; /* offset: 0x0C2C size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO23; /* offset: 0x0C2E size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO24; /* offset: 0x0C30 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO25; /* offset: 0x0C32 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO26; /* offset: 0x0C34 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO27; /* offset: 0x0C36 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO28; /* offset: 0x0C38 size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO29; /* offset: 0x0C3A size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO30; /* offset: 0x0C3C size: 16 bit */ - SIUL_PGPDO_16B_tag PGPDO31; /* offset: 0x0C3E size: 16 bit */ - }; - - }; - union { - /* PGPDI - Parallel GPIO Pad Data In Register */ - SIUL_PGPDI_16B_tag PGPDI[32]; /* offset: 0x0C40 (0x0002 x 32) */ - - struct { - /* PGPDI - Parallel GPIO Pad Data In Register */ - SIUL_PGPDI_16B_tag PGPDI0; /* offset: 0x0C40 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI1; /* offset: 0x0C42 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI2; /* offset: 0x0C44 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI3; /* offset: 0x0C46 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI4; /* offset: 0x0C48 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI5; /* offset: 0x0C4A size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI6; /* offset: 0x0C4C size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI7; /* offset: 0x0C4E size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI8; /* offset: 0x0C50 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI9; /* offset: 0x0C52 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI10; /* offset: 0x0C54 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI11; /* offset: 0x0C56 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI12; /* offset: 0x0C58 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI13; /* offset: 0x0C5A size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI14; /* offset: 0x0C5C size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI15; /* offset: 0x0C5E size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI16; /* offset: 0x0C60 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI17; /* offset: 0x0C62 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI18; /* offset: 0x0C64 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI19; /* offset: 0x0C66 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI20; /* offset: 0x0C68 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI21; /* offset: 0x0C6A size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI22; /* offset: 0x0C6C size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI23; /* offset: 0x0C6E size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI24; /* offset: 0x0C70 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI25; /* offset: 0x0C72 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI26; /* offset: 0x0C74 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI27; /* offset: 0x0C76 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI28; /* offset: 0x0C78 size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI29; /* offset: 0x0C7A size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI30; /* offset: 0x0C7C size: 16 bit */ - SIUL_PGPDI_16B_tag PGPDI31; /* offset: 0x0C7E size: 16 bit */ - }; - - }; - union { - /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ - SIUL_MPGPDO_32B_tag MPGPDO[32]; /* offset: 0x0C80 (0x0004 x 32) */ - - struct { - /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ - SIUL_MPGPDO_32B_tag MPGPDO0; /* offset: 0x0C80 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO1; /* offset: 0x0C84 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO2; /* offset: 0x0C88 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO3; /* offset: 0x0C8C size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO4; /* offset: 0x0C90 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO5; /* offset: 0x0C94 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO6; /* offset: 0x0C98 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO7; /* offset: 0x0C9C size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO8; /* offset: 0x0CA0 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO9; /* offset: 0x0CA4 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO10; /* offset: 0x0CA8 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO11; /* offset: 0x0CAC size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO12; /* offset: 0x0CB0 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO13; /* offset: 0x0CB4 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO14; /* offset: 0x0CB8 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO15; /* offset: 0x0CBC size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO16; /* offset: 0x0CC0 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO17; /* offset: 0x0CC4 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO18; /* offset: 0x0CC8 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO19; /* offset: 0x0CCC size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO20; /* offset: 0x0CD0 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO21; /* offset: 0x0CD4 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO22; /* offset: 0x0CD8 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO23; /* offset: 0x0CDC size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO24; /* offset: 0x0CE0 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO25; /* offset: 0x0CE4 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO26; /* offset: 0x0CE8 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO27; /* offset: 0x0CEC size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO28; /* offset: 0x0CF0 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO29; /* offset: 0x0CF4 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO30; /* offset: 0x0CF8 size: 32 bit */ - SIUL_MPGPDO_32B_tag MPGPDO31; /* offset: 0x0CFC size: 32 bit */ - }; - - }; - int8_t SIUL_reserved_0D00_C[768]; - union { - /* IFMC - Interrupt Filter Maximum Counter Register */ - SIUL_IFMC_32B_tag IFMC[32]; /* offset: 0x1000 (0x0004 x 32) */ - - struct { - /* IFMC - Interrupt Filter Maximum Counter Register */ - SIUL_IFMC_32B_tag IFMC0; /* offset: 0x1000 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC1; /* offset: 0x1004 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC2; /* offset: 0x1008 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC3; /* offset: 0x100C size: 32 bit */ - SIUL_IFMC_32B_tag IFMC4; /* offset: 0x1010 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC5; /* offset: 0x1014 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC6; /* offset: 0x1018 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC7; /* offset: 0x101C size: 32 bit */ - SIUL_IFMC_32B_tag IFMC8; /* offset: 0x1020 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC9; /* offset: 0x1024 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC10; /* offset: 0x1028 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC11; /* offset: 0x102C size: 32 bit */ - SIUL_IFMC_32B_tag IFMC12; /* offset: 0x1030 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC13; /* offset: 0x1034 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC14; /* offset: 0x1038 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC15; /* offset: 0x103C size: 32 bit */ - SIUL_IFMC_32B_tag IFMC16; /* offset: 0x1040 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC17; /* offset: 0x1044 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC18; /* offset: 0x1048 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC19; /* offset: 0x104C size: 32 bit */ - SIUL_IFMC_32B_tag IFMC20; /* offset: 0x1050 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC21; /* offset: 0x1054 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC22; /* offset: 0x1058 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC23; /* offset: 0x105C size: 32 bit */ - SIUL_IFMC_32B_tag IFMC24; /* offset: 0x1060 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC25; /* offset: 0x1064 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC26; /* offset: 0x1068 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC27; /* offset: 0x106C size: 32 bit */ - SIUL_IFMC_32B_tag IFMC28; /* offset: 0x1070 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC29; /* offset: 0x1074 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC30; /* offset: 0x1078 size: 32 bit */ - SIUL_IFMC_32B_tag IFMC31; /* offset: 0x107C size: 32 bit */ - }; - - }; - /* IFCPR - Inerrupt Filter Clock Prescaler Register */ - SIUL_IFCPR_32B_tag IFCPR; /* offset: 0x1080 size: 32 bit */ - } SIU_tag; - - -#define SIUL (*(volatile SIU_tag *) 0xC3F90000UL) - - - -/****************************************************************/ -/* */ -/* Module: WKPU */ -/* */ -/****************************************************************/ - - typedef union { /* WKPU_NSR - NMI Status Flag Register */ - uint32_t R; - struct { - uint32_t NIF0:1; /* NMI Status Flag 0 */ - uint32_t NOVF0:1; /* NMI Overrun Status Flag 0 */ - uint32_t:6; - uint32_t NIF1:1; /* NMI Status Flag 1 */ - uint32_t NOVF1:1; /* NMI Overrun Status Flag 1 */ - uint32_t:6; - uint32_t NIF2:1; /* NMI Status Flag 2 */ - uint32_t NOVF2:1; /* NMI Overrun Status Flag 2 */ - uint32_t:6; - uint32_t NIF3:1; /* NMI Status Flag 3 */ - uint32_t NOVF3:1; /* NMI Overrun Status Flag 3 */ - uint32_t:6; - } B; - } WKPU_NSR_32B_tag; - - typedef union { /* WKPU_NCR - NMI Configuration Register */ - uint32_t R; - struct { - uint32_t NLOCK0:1; /* NMI Configuration Lock Register 0 */ - uint32_t NDSS0:2; /* NMI Desination Source Select 0 */ - uint32_t NWRE0:1; /* NMI Wakeup Request Enable 0 */ - uint32_t:1; - uint32_t NREE0:1; /* NMI Rising Edge Events Enable 0 */ - uint32_t NFEE0:1; /* NMI Falling Edge Events Enable 0 */ - uint32_t NFE0:1; /* NMI Filter Enable 0 */ - uint32_t NLOCK1:1; /* NMI Configuration Lock Register 1 */ - uint32_t NDSS1:2; /* NMI Desination Source Select 1 */ - uint32_t NWRE1:1; /* NMI Wakeup Request Enable 1 */ - uint32_t:1; - uint32_t NREE1:1; /* NMI Rising Edge Events Enable 1 */ - uint32_t NFEE1:1; /* NMI Falling Edge Events Enable 1 */ - uint32_t NFE1:1; /* NMI Filter Enable 1 */ - uint32_t NLOCK2:1; /* NMI Configuration Lock Register 2 */ - uint32_t NDSS2:2; /* NMI Desination Source Select 2 */ - uint32_t NWRE2:1; /* NMI Wakeup Request Enable 2 */ - uint32_t:1; - uint32_t NREE2:1; /* NMI Rising Edge Events Enable 2 */ - uint32_t NFEE2:1; /* NMI Falling Edge Events Enable 2 */ - uint32_t NFE2:1; /* NMI Filter Enable 2 */ - uint32_t NLOCK3:1; /* NMI Configuration Lock Register 3 */ - uint32_t NDSS3:2; /* NMI Desination Source Select 3 */ - uint32_t NWRE3:1; /* NMI Wakeup Request Enable 3 */ - uint32_t:1; - uint32_t NREE3:1; /* NMI Rising Edge Events Enable 3 */ - uint32_t NFEE3:1; /* NMI Falling Edge Events Enable 3 */ - uint32_t NFE3:1; /* NMI Filter Enable 3 */ - } B; - } WKPU_NCR_32B_tag; - - typedef union { /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */ - uint32_t R; - struct { - uint32_t EIF:32; /* External Wakeup/Interrupt Status Flag */ - } B; - } WKPU_WISR_32B_tag; - - typedef union { /* WKPU_IRER - Interrupt Request Enable Register */ - uint32_t R; - struct { - uint32_t EIRE:32; /* Enable External Interrupt Requests */ - } B; - } WKPU_IRER_32B_tag; - - typedef union { /* WKPU_WRER - Wakeup Request Enable Register */ - uint32_t R; - struct { - uint32_t WRE:32; /* Enable Wakeup requests to the mode entry module */ - } B; - } WKPU_WRER_32B_tag; - - typedef union { /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */ - uint32_t R; - struct { - uint32_t IREE:32; /* Enable rising-edge events to cause EIF[x] to be set */ - } B; - } WKPU_WIREER_32B_tag; - - typedef union { /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */ - uint32_t R; - struct { - uint32_t IFEE:32; /* Enable Falling-edge events to cause EIF[x] to be set */ - } B; - } WKPU_WIFEER_32B_tag; - - typedef union { /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */ - uint32_t R; - struct { - uint32_t IFE:32; /* Enable Digital glitch filter on the interrupt pad input */ - } B; - } WKPU_WIFER_32B_tag; - - typedef union { /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */ - uint32_t R; - struct { - uint32_t IPUE:32; /* Enable a pullup on the interrupt pad input */ - } B; - } WKPU_WIPUER_32B_tag; - - - - typedef struct WKPU_struct_tag { /* start of WKPU_tag */ - /* WKPU_NSR - NMI Status Flag Register */ - WKPU_NSR_32B_tag NSR; /* offset: 0x0000 size: 32 bit */ - int8_t WKPU_reserved_0004[4]; - /* WKPU_NCR - NMI Configuration Register */ - WKPU_NCR_32B_tag NCR; /* offset: 0x0008 size: 32 bit */ - int8_t WKPU_reserved_000C[8]; - /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */ - WKPU_WISR_32B_tag WISR; /* offset: 0x0014 size: 32 bit */ - /* WKPU_IRER - Interrupt Request Enable Register */ - WKPU_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */ - /* WKPU_WRER - Wakeup Request Enable Register */ - WKPU_WRER_32B_tag WRER; /* offset: 0x001C size: 32 bit */ - int8_t WKPU_reserved_0020[8]; - /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */ - WKPU_WIREER_32B_tag WIREER; /* offset: 0x0028 size: 32 bit */ - /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */ - WKPU_WIFEER_32B_tag WIFEER; /* offset: 0x002C size: 32 bit */ - /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */ - WKPU_WIFER_32B_tag WIFER; /* offset: 0x0030 size: 32 bit */ - /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */ - WKPU_WIPUER_32B_tag WIPUER; /* offset: 0x0034 size: 32 bit */ - } WKPU_tag; - - -#define WKPU (*(volatile WKPU_tag *) 0xC3F94000UL) - - - -/****************************************************************/ -/* */ -/* Module: SSCM */ -/* */ -/****************************************************************/ - - typedef union { /* SSCM_STATUS - System Status Register */ - uint16_t R; - struct { - uint16_t LSM:1; /* Lock Step Mode */ - uint16_t:2; - uint16_t NXEN1:1; /* Processor 1 Nexus enabled */ - uint16_t NXEN:1; /* Processor 0 Nexus enabled */ - uint16_t PUB:1; /* Public Serial Access Status */ - uint16_t SEC:1; /* Security Status */ - uint16_t:1; - uint16_t BMODE:3; /* Device Boot Mode */ - uint16_t VLE:1; /* Variable Length Instruction Mode */ - uint16_t ABD:1; /* Autobaud detection */ - uint16_t:3; - } B; - } SSCM_STATUS_16B_tag; - - typedef union { /* SSCM_MEMCONFIG - System Memory Configuration Register */ - uint16_t R; - struct { - uint16_t JPIN:10; /* JTAG Part ID Number */ - uint16_t IVLD:1; /* Instruction Flash Valid */ - uint16_t MREV:4; /* Minor Mask Revision */ - uint16_t DVLD:1; /* Data Flash Valid */ - } B; - } SSCM_MEMCONFIG_16B_tag; - - typedef union { /* SSCM_ERROR - Error Configuration */ - uint16_t R; - struct { - uint16_t:14; - uint16_t PAE:1; /* Peripheral Bus Abort Enable */ - uint16_t RAE:1; /* Register Bus Abort Enable */ - } B; - } SSCM_ERROR_16B_tag; - - typedef union { /* SSCM_DEBUGPORT - Debug Status Port Register */ - uint16_t R; - struct { - uint16_t:13; - uint16_t DEBUG_MODE:3; /* Debug Status Port Mode */ - } B; - } SSCM_DEBUGPORT_16B_tag; - - typedef union { /* SSCM_PWCMPH - Password Comparison Register High */ - uint32_t R; - struct { - uint32_t PWD_HI:32; /* Password High */ - } B; - } SSCM_PWCMPH_32B_tag; - - typedef union { /* SSCM_PWCMPL - Password Comparison Register Low */ - uint32_t R; - struct { - uint32_t PWD_LO:32; /* Password Low */ - } B; - } SSCM_PWCMPL_32B_tag; - - typedef union { /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */ - uint32_t R; - struct { - uint32_t P2BOOT:30; /* boot location 2nd processor */ - uint32_t DVLE:1; /* VLE mode for 2nd processor */ - uint32_t:1; - } B; - } SSCM_DPMBOOT_32B_tag; - - typedef union { /* SSCM_DPMKEY - Boot Key Register */ - uint32_t R; - struct { - uint32_t KEY:32; /* Boot Control Key */ - } B; - } SSCM_DPMKEY_32B_tag; - - typedef union { /* SSCM_UOPS - User Option Status Register */ - uint32_t R; - struct { - uint32_t UOPT:32; /* User Option Bits */ - } B; - } SSCM_UOPS_32B_tag; - - typedef union { /* SSCM_SCTR - SSCM Control Register */ - uint32_t R; - struct { - uint32_t:29; - uint32_t TFE:1; /* Test Flash Enable */ - uint32_t DSL:1; /* Disable Software-Controlled MBIST */ - uint32_t DSM:1; /* Disable Software-Controlled LBIST */ - } B; - } SSCM_SCTR_32B_tag; - - typedef union { /* SSCM_TF_INFO0 - TestFlash Information Register 0 */ - uint32_t R; - struct { - uint32_t TINFO0:32; /* General purpose TestFlash word 0 */ - } B; - } SSCM_TF_INFO0_32B_tag; - - typedef union { /* SSCM_TF_INFO1 - TestFlash Information Register 1 */ - uint32_t R; - struct { - uint32_t TINFO1:32; /* General purpose TestFlash word 1 */ - } B; - } SSCM_TF_INFO1_32B_tag; - - typedef union { /* SSCM_TF_INFO2 - TestFlash Information Register 2 */ - uint32_t R; - struct { - uint32_t TINFO2:32; /* General purpose TestFlash word 2 */ - } B; - } SSCM_TF_INFO2_32B_tag; - - typedef union { /* SSCM_TF_INFO3 - TestFlash Information Register 3 */ - uint32_t R; - struct { - uint32_t TINFO3:32; /* General purpose TestFlash word */ - } B; - } SSCM_TF_INFO3_32B_tag; - - - - typedef struct SSCM_struct_tag { /* start of SSCM_tag */ - /* SSCM_STATUS - System Status Register */ - SSCM_STATUS_16B_tag STATUS; /* offset: 0x0000 size: 16 bit */ - /* SSCM_MEMCONFIG - System Memory Configuration Register */ - SSCM_MEMCONFIG_16B_tag MEMCONFIG; /* offset: 0x0002 size: 16 bit */ - int8_t SSCM_reserved_0004[2]; - /* SSCM_ERROR - Error Configuration */ - SSCM_ERROR_16B_tag ERROR; /* offset: 0x0006 size: 16 bit */ - /* SSCM_DEBUGPORT - Debug Status Port Register */ - SSCM_DEBUGPORT_16B_tag DEBUGPORT; /* offset: 0x0008 size: 16 bit */ - int8_t SSCM_reserved_000A[2]; - /* SSCM_PWCMPH - Password Comparison Register High */ - SSCM_PWCMPH_32B_tag PWCMPH; /* offset: 0x000C size: 32 bit */ - /* SSCM_PWCMPL - Password Comparison Register Low */ - SSCM_PWCMPL_32B_tag PWCMPL; /* offset: 0x0010 size: 32 bit */ - int8_t SSCM_reserved_0014[4]; - /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */ - SSCM_DPMBOOT_32B_tag DPMBOOT; /* offset: 0x0018 size: 32 bit */ - /* SSCM_DPMKEY - Boot Key Register */ - SSCM_DPMKEY_32B_tag DPMKEY; /* offset: 0x001C size: 32 bit */ - /* SSCM_UOPS - User Option Status Register */ - SSCM_UOPS_32B_tag UOPS; /* offset: 0x0020 size: 32 bit */ - /* SSCM_SCTR - SSCM Control Register */ - SSCM_SCTR_32B_tag SCTR; /* offset: 0x0024 size: 32 bit */ - /* SSCM_TF_INFO0 - TestFlash Information Register 0 */ - SSCM_TF_INFO0_32B_tag TF_INFO0; /* offset: 0x0028 size: 32 bit */ - /* SSCM_TF_INFO1 - TestFlash Information Register 1 */ - SSCM_TF_INFO1_32B_tag TF_INFO1; /* offset: 0x002C size: 32 bit */ - /* SSCM_TF_INFO2 - TestFlash Information Register 2 */ - SSCM_TF_INFO2_32B_tag TF_INFO2; /* offset: 0x0030 size: 32 bit */ - /* SSCM_TF_INFO3 - TestFlash Information Register 3 */ - SSCM_TF_INFO3_32B_tag TF_INFO3; /* offset: 0x0034 size: 32 bit */ - } SSCM_tag; - - -#define SSCM (*(volatile SSCM_tag *) 0xC3FD8000UL) - - - -/****************************************************************/ -/* */ -/* Module: ME */ -/* */ -/****************************************************************/ - - typedef union { /* ME_GS - Global Status Register */ - uint32_t R; - struct { -#ifndef USE_FIELD_ALIASES_ME - uint32_t S_CURRENT_MODE:4; /* Current device mode status */ -#else - uint32_t S_CURRENTMODE:4; /* deprecated name - please avoid */ -#endif - uint32_t S_MTRANS:1; /* Mode transition status */ - uint32_t:3; - uint32_t S_PDO:1; /* Output power-down status */ - uint32_t:2; - uint32_t S_MVR:1; /* Main voltage regulator status */ - uint32_t:2; -#ifndef USE_FIELD_ALIASES_ME - uint32_t S_FLA:2; /* Flash availability status */ -#else - uint32_t S_CFLA:2; /* deprecated name - please avoid */ -#endif - uint32_t:8; - uint32_t S_PLL1:1; /* Secondary PLL status */ - uint32_t S_PLL0:1; /* System PLL status */ -#ifndef USE_FIELD_ALIASES_ME - uint32_t S_XOSC:1; /* System crystal oscillator status */ -#else - uint32_t S_OSC:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t S_IRCOSC:1; /* System RC oscillator status */ -#else - uint32_t S_RC:1; /* deprecated name - please avoid */ -#endif - uint32_t S_SYSCLK:4; /* System clock switch status */ - } B; - } ME_GS_32B_tag; - - typedef union { /* ME_MCTL - Mode Control Register */ - uint32_t R; - struct { - uint32_t TARGET_MODE:4; /* Target device mode */ - uint32_t:12; - uint32_t KEY:16; /* Control key */ - } B; - } ME_MCTL_32B_tag; - - typedef union { /* ME_MEN - Mode Enable Register */ - uint32_t R; - struct { - uint32_t:21; - uint32_t STOP0:1; /* STOP0 mode enable */ - uint32_t:1; - uint32_t HALT0:1; /* HALT0 mode enable */ - uint32_t RUN3:1; /* RUN3 mode enable */ - uint32_t RUN2:1; /* RUN2 mode enable */ - uint32_t RUN1:1; /* RUN1 mode enable */ - uint32_t RUN0:1; /* RUN0 mode enable */ - uint32_t DRUN:1; /* DRUN mode enable */ - uint32_t SAFE:1; /* SAFE mode enable */ - uint32_t:1; - uint32_t RESET:1; /* RESET mode enable */ - } B; - } ME_MEN_32B_tag; - - typedef union { /* ME_IS - Interrupt Status Register */ - uint32_t R; - struct { - uint32_t:28; -#ifndef USE_FIELD_ALIASES_ME - uint32_t I_ICONF:1; /* Invalid mode config interrupt */ -#else - uint32_t I_CONF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t I_IMODE:1; /* Invalid mode interrupt */ -#else - uint32_t I_MODE:1; /* deprecated name - please avoid */ -#endif - uint32_t I_SAFE:1; /* SAFE mode interrupt */ -#ifndef USE_FIELD_ALIASES_ME - uint32_t I_MTC:1; /* Mode transition complete interrupt */ -#else - uint32_t I_TC:1; /* deprecated name - please avoid */ -#endif - } B; - } ME_IS_32B_tag; - - typedef union { /* ME_IM - Interrupt Mask Register */ - uint32_t R; - struct { - uint32_t:28; -#ifndef USE_FIELD_ALIASES_ME - uint32_t M_ICONF:1; /* Invalid mode config interrupt mask */ -#else - uint32_t M_CONF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t M_IMODE:1; /* Invalid mode interrupt mask */ -#else - uint32_t M_MODE:1; /* deprecated name - please avoid */ -#endif - uint32_t M_SAFE:1; /* SAFE mode interrupt mask */ -#ifndef USE_FIELD_ALIASES_ME - uint32_t M_MTC:1; /* Mode transition complete interrupt mask */ -#else - uint32_t M_TC:1; /* deprecated name - please avoid */ -#endif - } B; - } ME_IM_32B_tag; - - typedef union { /* ME_IMTS - Invalid Mode Transition Status Register */ - uint32_t R; - struct { - uint32_t:27; - uint32_t S_MTI:1; /* Mode Transition Illegal status */ - uint32_t S_MRI:1; /* Mode Request Illegal status */ - uint32_t S_DMA:1; /* Disabled Mode Access status */ - uint32_t S_NMA:1; /* Non-existing Mode Access status */ - uint32_t S_SEA:1; /* Safe Event Active status */ - } B; - } ME_IMTS_32B_tag; - - typedef union { /* ME_DMTS - Debug Mode Transition Status Register */ - uint32_t R; - struct { - uint32_t PREVIOUS_MODE:4; /* Previous Device Mode */ - uint32_t:4; - uint32_t MPH_BUSY:1; /* MC_ME/MC_PCU Handshake Busy Indicator */ - uint32_t:2; - uint32_t PMC_PROG:1; /* MC_PCU Mode Change in Process Indicator */ - uint32_t CORE_DBG:1; /* Processor is in Debug Mode Indicator */ - uint32_t:2; - uint32_t SMR:1; /* SAFE Mode Request */ - uint32_t:1; - uint32_t VREG_CSRC_SC:1; /* Main VREG Clock Source State Change Indicator */ - uint32_t CSRC_CSRC_SC:1; /* Other Clock Source State Change Indicator */ - uint32_t IRCOSC_SC:1; /* IRCOSC State Change Indicator */ - uint32_t SCSRC_SC:1; /* Secondary System Clock Sources State Change Indicator */ - uint32_t SYSCLK_SW:1; /* System Clock Switching pending Status Indicator */ - uint32_t:1; - uint32_t FLASH_SC:1; /* FLASH State Change Indicator */ - uint32_t CDP_PRPH_0_143:1; /* Clock Disable Process Pending Status for Periph. 0-143 */ - uint32_t:4; - uint32_t CDP_PRPH_64_95:1; /* Clock Disable Process Pending Status for Periph. 64-95 */ - uint32_t CDP_PRPH_32_63:1; /* Clock Disable Process Pending Status for Periph. 32-63 */ - uint32_t CDP_PRPH_0_31:1; /* Clock Disable Process Pending Status for Periph. 0-31 */ - } B; - } ME_DMTS_32B_tag; - - typedef union { /* ME_RESET_MC - RESET Mode Configuration Register */ - uint32_t R; - struct { - uint32_t:8; - uint32_t PDO:1; /* IOs output power-down control */ - uint32_t:2; - uint32_t MVRON:1; /* Main voltage regulator control */ - uint32_t:2; - uint32_t FLAON:2; /* Flash power-down control */ - uint32_t:8; -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ -#else - uint32_t PLL2ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL0ON:1; /* System PLL control */ -#else - uint32_t PLL1ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t XOSCON:1; /* System crystal oscillator control */ -#else - uint32_t XOSC0ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t IRCOSCON:1; /* System RC oscillator control */ -#else - uint32_t IRCON:1; /* deprecated name - please avoid */ -#endif - uint32_t SYSCLK:4; /* System clock switch control */ - } B; - } ME_RESET_MC_32B_tag; - - typedef union { /* ME_SAFE_MC - Mode Configuration Register */ - uint32_t R; - struct { - uint32_t:8; - uint32_t PDO:1; /* IOs output power-down control */ - uint32_t:2; - uint32_t MVRON:1; /* Main voltage regulator control */ - uint32_t:2; - uint32_t FLAON:2; /* Flash power-down control */ - uint32_t:8; -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ -#else - uint32_t PLL2ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL0ON:1; /* System PLL control */ -#else - uint32_t PLL1ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t XOSCON:1; /* System crystal oscillator control */ -#else - uint32_t XOSC0ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t IRCOSCON:1; /* System RC oscillator control */ -#else - uint32_t IRCON:1; /* deprecated name - please avoid */ -#endif - uint32_t SYSCLK:4; /* System clock switch control */ - } B; - } ME_SAFE_MC_32B_tag; - - typedef union { /* ME_DRUN_MC - DRUN Mode Configuration Register */ - uint32_t R; - struct { - uint32_t:8; - uint32_t PDO:1; /* IOs output power-down control */ - uint32_t:2; - uint32_t MVRON:1; /* Main voltage regulator control */ - uint32_t:2; - uint32_t FLAON:2; /* Flash power-down control */ - uint32_t:8; -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ -#else - uint32_t PLL2ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL0ON:1; /* System PLL control */ -#else - uint32_t PLL1ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t XOSCON:1; /* System crystal oscillator control */ -#else - uint32_t XOSC0ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t IRCOSCON:1; /* System RC oscillator control */ -#else - uint32_t IRCON:1; /* deprecated name - please avoid */ -#endif - uint32_t SYSCLK:4; /* System clock switch control */ - } B; - } ME_DRUN_MC_32B_tag; - - - /* Register layout for all registers RUN_MC... */ - - typedef union { /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ - uint32_t R; - struct { - uint32_t:8; - uint32_t PDO:1; /* IOs output power-down control */ - uint32_t:2; - uint32_t MVRON:1; /* Main voltage regulator control */ - uint32_t:2; - uint32_t FLAON:2; /* Flash power-down control */ - uint32_t:8; -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ -#else - uint32_t PLL2ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL0ON:1; /* System PLL control */ -#else - uint32_t PLL1ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t XOSCON:1; /* System crystal oscillator control */ -#else - uint32_t XOSC0ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t IRCOSCON:1; /* System RC oscillator control */ -#else - uint32_t IRCON:1; /* deprecated name - please avoid */ -#endif - uint32_t SYSCLK:4; /* System clock switch control */ - } B; - } ME_RUN_MC_32B_tag; - - typedef union { /* ME_HALT0_MC - HALT0 Mode Configuration Register */ - uint32_t R; - struct { - uint32_t:8; - uint32_t PDO:1; /* IOs output power-down control */ - uint32_t:2; - uint32_t MVRON:1; /* Main voltage regulator control */ - uint32_t:2; - uint32_t FLAON:2; /* Flash power-down control */ - uint32_t:8; -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ -#else - uint32_t PLL2ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL0ON:1; /* System PLL control */ -#else - uint32_t PLL1ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t XOSCON:1; /* System crystal oscillator control */ -#else - uint32_t XOSC0ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t IRCOSCON:1; /* System RC oscillator control */ -#else - uint32_t IRCON:1; /* deprecated name - please avoid */ -#endif - uint32_t SYSCLK:4; /* System clock switch control */ - } B; - } ME_HALT0_MC_32B_tag; - - typedef union { /* ME_STOP0_MC - STOP0 Mode Configration Register */ - uint32_t R; - struct { - uint32_t:8; - uint32_t PDO:1; /* IOs output power-down control */ - uint32_t:2; - uint32_t MVRON:1; /* Main voltage regulator control */ - uint32_t:2; - uint32_t FLAON:2; /* Flash power-down control */ - uint32_t:8; -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ -#else - uint32_t PLL2ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL0ON:1; /* System PLL control */ -#else - uint32_t PLL1ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t XOSCON:1; /* System crystal oscillator control */ -#else - uint32_t XOSC0ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t IRCOSCON:1; /* System RC oscillator control */ -#else - uint32_t IRCON:1; /* deprecated name - please avoid */ -#endif - uint32_t SYSCLK:4; /* System clock switch control */ - } B; - } ME_STOP0_MC_32B_tag; - - typedef union { /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */ - uint32_t R; - struct { - uint32_t:8; - uint32_t PDO:1; /* IOs output power-down control */ - uint32_t:2; - uint32_t MVRON:1; /* Main voltage regulator control */ - uint32_t:2; - uint32_t FLAON:2; /* Flash power-down control */ - uint32_t:8; -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ -#else - uint32_t PLL2ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t PLL0ON:1; /* System PLL control */ -#else - uint32_t PLL1ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t XOSCON:1; /* System crystal oscillator control */ -#else - uint32_t XOSC0ON:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ME - uint32_t IRCOSCON:1; /* System RC oscillator control */ -#else - uint32_t IRCON:1; /* deprecated name - please avoid */ -#endif - uint32_t SYSCLK:4; /* System clock switch control */ - } B; - } ME_STANDBY0_MC_32B_tag; - - typedef union { /* ME_PS0 - Peripheral Status Register 0 */ - uint32_t R; - struct { - uint32_t:7; - uint32_t S_FLEXRAY:1; /* FlexRay status */ - uint32_t:6; - uint32_t S_FLEXCAN1:1; /* FlexCAN1 status */ - uint32_t S_FLEXCAN0:1; /* FlexCAN0 status */ - uint32_t:9; - uint32_t S_DSPI2:1; /* DSPI2 status */ - uint32_t S_DSPI1:1; /* DSPI1 status */ - uint32_t S_DSPI0:1; /* DSPI0 status */ - uint32_t:4; - } B; - } ME_PS0_32B_tag; - - typedef union { /* ME_PS1 - Peripheral Status Register 1 */ - uint32_t R; - struct { - uint32_t:1; - uint32_t S_SWG:1; /* SWG status */ - uint32_t:3; - uint32_t S_CRC:1; /* CRC status */ - uint32_t:8; - uint32_t S_LIN_FLEX1:1; /* LinFlex1 status */ - uint32_t S_LIN_FLEX0:1; /* LinFlex0 status */ - uint32_t:5; - uint32_t S_FLEXPWM1:1; /* FlexPWM1 status */ - uint32_t S_FLEXPWM0:1; /* FlexPWM0 status */ - uint32_t S_ETIMER2:1; /* eTimer2 status */ - uint32_t S_ETIMER1:1; /* eTimer1 status */ - uint32_t S_ETIMER0:1; /* eTimer0 status */ - uint32_t:2; - uint32_t S_CTU:1; /* CTU status */ - uint32_t:1; - uint32_t S_ADC1:1; /* ADC1 status */ - uint32_t S_ADC0:1; /* ADC0 status */ - } B; - } ME_PS1_32B_tag; - - typedef union { /* ME_PS2 - Peripheral Status Register 2 */ - uint32_t R; - struct { - uint32_t:3; - uint32_t S_PIT:1; /* PIT status */ - uint32_t:28; - } B; - } ME_PS2_32B_tag; - - - /* Register layout for all registers RUN_PC... */ - - typedef union { /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ - uint32_t R; - struct { - uint32_t:24; - uint32_t RUN3:1; /* Peripheral control during RUN3 */ - uint32_t RUN2:1; /* Peripheral control during RUN2 */ - uint32_t RUN1:1; /* Peripheral control during RUN1 */ - uint32_t RUN0:1; /* Peripheral control during RUN0 */ - uint32_t DRUN:1; /* Peripheral control during DRUN */ - uint32_t SAFE:1; /* Peripheral control during SAFE */ - uint32_t TEST:1; /* Peripheral control during TEST */ - uint32_t RESET:1; /* Peripheral control during RESET */ - } B; - } ME_RUN_PC_32B_tag; - - - /* Register layout for all registers LP_PC... */ - - typedef union { /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ - uint32_t R; - struct { - uint32_t:21; - uint32_t STOP0:1; /* Peripheral control during STOP0 */ - uint32_t:1; - uint32_t HALT0:1; /* Peripheral control during HALT0 */ - uint32_t:8; - } B; - } ME_LP_PC_32B_tag; - - - /* Register layout for all registers PCTL... */ - - typedef union { /* ME_PCTL[0...143] - Peripheral Control Registers */ - uint8_t R; - struct { - uint8_t:1; - uint8_t DBG_F:1; /* Peripheral control in debug mode */ - uint8_t LP_CFG:3; /* Peripheral configuration select for non-RUN modes */ - uint8_t RUN_CFG:3; /* Peripheral configuration select for RUN modes */ - } B; - } ME_PCTL_8B_tag; - - - - - /* Register layout for generated register(s) PS... */ - - typedef union { /* */ - uint32_t R; - } ME_PS_32B_tag; - - - - - - - typedef struct ME_struct_tag { /* start of ME_tag */ - /* ME_GS - Global Status Register */ - ME_GS_32B_tag GS; /* offset: 0x0000 size: 32 bit */ - /* ME_MCTL - Mode Control Register */ - ME_MCTL_32B_tag MCTL; /* offset: 0x0004 size: 32 bit */ - union { - ME_MEN_32B_tag MER; /* deprecated - please avoid */ - - /* ME_MEN - Mode Enable Register */ - ME_MEN_32B_tag MEN; /* offset: 0x0008 size: 32 bit */ - - }; - /* ME_IS - Interrupt Status Register */ - ME_IS_32B_tag IS; /* offset: 0x000C size: 32 bit */ - /* ME_IM - Interrupt Mask Register */ - ME_IM_32B_tag IM; /* offset: 0x0010 size: 32 bit */ - /* ME_IMTS - Invalid Mode Transition Status Register */ - ME_IMTS_32B_tag IMTS; /* offset: 0x0014 size: 32 bit */ - /* ME_DMTS - Debug Mode Transition Status Register */ - ME_DMTS_32B_tag DMTS; /* offset: 0x0018 size: 32 bit */ - int8_t ME_reserved_001C_C[4]; - union { - /* ME_RESET_MC - RESET Mode Configuration Register */ - ME_RESET_MC_32B_tag RESET_MC; /* offset: 0x0020 size: 32 bit */ - - ME_RESET_MC_32B_tag RESET; /* deprecated - please avoid */ - - }; - int8_t ME_reserved_0024_C[4]; - union { - /* ME_SAFE_MC - Mode Configuration Register */ - ME_SAFE_MC_32B_tag SAFE_MC; /* offset: 0x0028 size: 32 bit */ - - ME_SAFE_MC_32B_tag SAFE; /* deprecated - please avoid */ - - }; - union { - /* ME_DRUN_MC - DRUN Mode Configuration Register */ - ME_DRUN_MC_32B_tag DRUN_MC; /* offset: 0x002C size: 32 bit */ - - ME_DRUN_MC_32B_tag DRUN; /* deprecated - please avoid */ - - }; - union { - /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ - ME_RUN_MC_32B_tag RUN_MC[4]; /* offset: 0x0030 (0x0004 x 4) */ - - ME_RUN_MC_32B_tag RUN[4]; /* offset: 0x0030 (0x0004 x 4) */ /* deprecated - please avoid */ - - struct { - /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ - ME_RUN_MC_32B_tag RUN0_MC; /* offset: 0x0030 size: 32 bit */ - ME_RUN_MC_32B_tag RUN1_MC; /* offset: 0x0034 size: 32 bit */ - ME_RUN_MC_32B_tag RUN2_MC; /* offset: 0x0038 size: 32 bit */ - ME_RUN_MC_32B_tag RUN3_MC; /* offset: 0x003C size: 32 bit */ - }; - - }; - union { - /* ME_HALT0_MC - HALT0 Mode Configuration Register */ - ME_HALT0_MC_32B_tag HALT0_MC; /* offset: 0x0040 size: 32 bit */ - - ME_HALT0_MC_32B_tag HALT0; /* deprecated - please avoid */ - - }; - int8_t ME_reserved_0044_C[4]; - union { - /* ME_STOP0_MC - STOP0 Mode Configration Register */ - ME_STOP0_MC_32B_tag STOP0_MC; /* offset: 0x0048 size: 32 bit */ - - ME_STOP0_MC_32B_tag STOP0; /* deprecated - please avoid */ - - }; - int8_t ME_reserved_004C_C[8]; - union { - /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */ - ME_STANDBY0_MC_32B_tag STANDBY0_MC; /* offset: 0x0054 size: 32 bit */ - - ME_STANDBY0_MC_32B_tag STANDBY0; /* deprecated - please avoid */ - - }; - int8_t ME_reserved_0058_C[8]; - union { - ME_PS_32B_tag PS[3]; /* offset: 0x0060 (0x0004 x 3) */ - - struct { - /* ME_PS0 - Peripheral Status Register 0 */ - ME_PS0_32B_tag PS0; /* offset: 0x0060 size: 32 bit */ - /* ME_PS1 - Peripheral Status Register 1 */ - ME_PS1_32B_tag PS1; /* offset: 0x0064 size: 32 bit */ - /* ME_PS2 - Peripheral Status Register 2 */ - ME_PS2_32B_tag PS2; /* offset: 0x0068 size: 32 bit */ - }; - - }; - int8_t ME_reserved_006C_C[20]; - union { - ME_RUN_PC_32B_tag RUNPC[8]; /* offset: 0x0080 (0x0004 x 8) */ - - /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ - ME_RUN_PC_32B_tag RUN_PC[8]; /* offset: 0x0080 (0x0004 x 8) */ - - struct { - /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ - ME_RUN_PC_32B_tag RUN_PC0; /* offset: 0x0080 size: 32 bit */ - ME_RUN_PC_32B_tag RUN_PC1; /* offset: 0x0084 size: 32 bit */ - ME_RUN_PC_32B_tag RUN_PC2; /* offset: 0x0088 size: 32 bit */ - ME_RUN_PC_32B_tag RUN_PC3; /* offset: 0x008C size: 32 bit */ - ME_RUN_PC_32B_tag RUN_PC4; /* offset: 0x0090 size: 32 bit */ - ME_RUN_PC_32B_tag RUN_PC5; /* offset: 0x0094 size: 32 bit */ - ME_RUN_PC_32B_tag RUN_PC6; /* offset: 0x0098 size: 32 bit */ - ME_RUN_PC_32B_tag RUN_PC7; /* offset: 0x009C size: 32 bit */ - }; - - }; - union { - ME_LP_PC_32B_tag LPPC[8]; /* offset: 0x00A0 (0x0004 x 8) */ - - /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ - ME_LP_PC_32B_tag LP_PC[8]; /* offset: 0x00A0 (0x0004 x 8) */ - - struct { - /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ - ME_LP_PC_32B_tag LP_PC0; /* offset: 0x00A0 size: 32 bit */ - ME_LP_PC_32B_tag LP_PC1; /* offset: 0x00A4 size: 32 bit */ - ME_LP_PC_32B_tag LP_PC2; /* offset: 0x00A8 size: 32 bit */ - ME_LP_PC_32B_tag LP_PC3; /* offset: 0x00AC size: 32 bit */ - ME_LP_PC_32B_tag LP_PC4; /* offset: 0x00B0 size: 32 bit */ - ME_LP_PC_32B_tag LP_PC5; /* offset: 0x00B4 size: 32 bit */ - ME_LP_PC_32B_tag LP_PC6; /* offset: 0x00B8 size: 32 bit */ - ME_LP_PC_32B_tag LP_PC7; /* offset: 0x00BC size: 32 bit */ - }; - - }; - union { - /* ME_PCTL[0...143] - Peripheral Control Registers */ - ME_PCTL_8B_tag PCTL[144]; /* offset: 0x00C0 (0x0001 x 144) */ - - struct { - /* ME_PCTL[0...143] - Peripheral Control Registers */ - ME_PCTL_8B_tag PCTL0; /* offset: 0x00C0 size: 8 bit */ - ME_PCTL_8B_tag PCTL1; /* offset: 0x00C1 size: 8 bit */ - ME_PCTL_8B_tag PCTL2; /* offset: 0x00C2 size: 8 bit */ - ME_PCTL_8B_tag PCTL3; /* offset: 0x00C3 size: 8 bit */ - ME_PCTL_8B_tag PCTL4; /* offset: 0x00C4 size: 8 bit */ - ME_PCTL_8B_tag PCTL5; /* offset: 0x00C5 size: 8 bit */ - ME_PCTL_8B_tag PCTL6; /* offset: 0x00C6 size: 8 bit */ - ME_PCTL_8B_tag PCTL7; /* offset: 0x00C7 size: 8 bit */ - ME_PCTL_8B_tag PCTL8; /* offset: 0x00C8 size: 8 bit */ - ME_PCTL_8B_tag PCTL9; /* offset: 0x00C9 size: 8 bit */ - ME_PCTL_8B_tag PCTL10; /* offset: 0x00CA size: 8 bit */ - ME_PCTL_8B_tag PCTL11; /* offset: 0x00CB size: 8 bit */ - ME_PCTL_8B_tag PCTL12; /* offset: 0x00CC size: 8 bit */ - ME_PCTL_8B_tag PCTL13; /* offset: 0x00CD size: 8 bit */ - ME_PCTL_8B_tag PCTL14; /* offset: 0x00CE size: 8 bit */ - ME_PCTL_8B_tag PCTL15; /* offset: 0x00CF size: 8 bit */ - ME_PCTL_8B_tag PCTL16; /* offset: 0x00D0 size: 8 bit */ - ME_PCTL_8B_tag PCTL17; /* offset: 0x00D1 size: 8 bit */ - ME_PCTL_8B_tag PCTL18; /* offset: 0x00D2 size: 8 bit */ - ME_PCTL_8B_tag PCTL19; /* offset: 0x00D3 size: 8 bit */ - ME_PCTL_8B_tag PCTL20; /* offset: 0x00D4 size: 8 bit */ - ME_PCTL_8B_tag PCTL21; /* offset: 0x00D5 size: 8 bit */ - ME_PCTL_8B_tag PCTL22; /* offset: 0x00D6 size: 8 bit */ - ME_PCTL_8B_tag PCTL23; /* offset: 0x00D7 size: 8 bit */ - ME_PCTL_8B_tag PCTL24; /* offset: 0x00D8 size: 8 bit */ - ME_PCTL_8B_tag PCTL25; /* offset: 0x00D9 size: 8 bit */ - ME_PCTL_8B_tag PCTL26; /* offset: 0x00DA size: 8 bit */ - ME_PCTL_8B_tag PCTL27; /* offset: 0x00DB size: 8 bit */ - ME_PCTL_8B_tag PCTL28; /* offset: 0x00DC size: 8 bit */ - ME_PCTL_8B_tag PCTL29; /* offset: 0x00DD size: 8 bit */ - ME_PCTL_8B_tag PCTL30; /* offset: 0x00DE size: 8 bit */ - ME_PCTL_8B_tag PCTL31; /* offset: 0x00DF size: 8 bit */ - ME_PCTL_8B_tag PCTL32; /* offset: 0x00E0 size: 8 bit */ - ME_PCTL_8B_tag PCTL33; /* offset: 0x00E1 size: 8 bit */ - ME_PCTL_8B_tag PCTL34; /* offset: 0x00E2 size: 8 bit */ - ME_PCTL_8B_tag PCTL35; /* offset: 0x00E3 size: 8 bit */ - ME_PCTL_8B_tag PCTL36; /* offset: 0x00E4 size: 8 bit */ - ME_PCTL_8B_tag PCTL37; /* offset: 0x00E5 size: 8 bit */ - ME_PCTL_8B_tag PCTL38; /* offset: 0x00E6 size: 8 bit */ - ME_PCTL_8B_tag PCTL39; /* offset: 0x00E7 size: 8 bit */ - ME_PCTL_8B_tag PCTL40; /* offset: 0x00E8 size: 8 bit */ - ME_PCTL_8B_tag PCTL41; /* offset: 0x00E9 size: 8 bit */ - ME_PCTL_8B_tag PCTL42; /* offset: 0x00EA size: 8 bit */ - ME_PCTL_8B_tag PCTL43; /* offset: 0x00EB size: 8 bit */ - ME_PCTL_8B_tag PCTL44; /* offset: 0x00EC size: 8 bit */ - ME_PCTL_8B_tag PCTL45; /* offset: 0x00ED size: 8 bit */ - ME_PCTL_8B_tag PCTL46; /* offset: 0x00EE size: 8 bit */ - ME_PCTL_8B_tag PCTL47; /* offset: 0x00EF size: 8 bit */ - ME_PCTL_8B_tag PCTL48; /* offset: 0x00F0 size: 8 bit */ - ME_PCTL_8B_tag PCTL49; /* offset: 0x00F1 size: 8 bit */ - ME_PCTL_8B_tag PCTL50; /* offset: 0x00F2 size: 8 bit */ - ME_PCTL_8B_tag PCTL51; /* offset: 0x00F3 size: 8 bit */ - ME_PCTL_8B_tag PCTL52; /* offset: 0x00F4 size: 8 bit */ - ME_PCTL_8B_tag PCTL53; /* offset: 0x00F5 size: 8 bit */ - ME_PCTL_8B_tag PCTL54; /* offset: 0x00F6 size: 8 bit */ - ME_PCTL_8B_tag PCTL55; /* offset: 0x00F7 size: 8 bit */ - ME_PCTL_8B_tag PCTL56; /* offset: 0x00F8 size: 8 bit */ - ME_PCTL_8B_tag PCTL57; /* offset: 0x00F9 size: 8 bit */ - ME_PCTL_8B_tag PCTL58; /* offset: 0x00FA size: 8 bit */ - ME_PCTL_8B_tag PCTL59; /* offset: 0x00FB size: 8 bit */ - ME_PCTL_8B_tag PCTL60; /* offset: 0x00FC size: 8 bit */ - ME_PCTL_8B_tag PCTL61; /* offset: 0x00FD size: 8 bit */ - ME_PCTL_8B_tag PCTL62; /* offset: 0x00FE size: 8 bit */ - ME_PCTL_8B_tag PCTL63; /* offset: 0x00FF size: 8 bit */ - ME_PCTL_8B_tag PCTL64; /* offset: 0x0100 size: 8 bit */ - ME_PCTL_8B_tag PCTL65; /* offset: 0x0101 size: 8 bit */ - ME_PCTL_8B_tag PCTL66; /* offset: 0x0102 size: 8 bit */ - ME_PCTL_8B_tag PCTL67; /* offset: 0x0103 size: 8 bit */ - ME_PCTL_8B_tag PCTL68; /* offset: 0x0104 size: 8 bit */ - ME_PCTL_8B_tag PCTL69; /* offset: 0x0105 size: 8 bit */ - ME_PCTL_8B_tag PCTL70; /* offset: 0x0106 size: 8 bit */ - ME_PCTL_8B_tag PCTL71; /* offset: 0x0107 size: 8 bit */ - ME_PCTL_8B_tag PCTL72; /* offset: 0x0108 size: 8 bit */ - ME_PCTL_8B_tag PCTL73; /* offset: 0x0109 size: 8 bit */ - ME_PCTL_8B_tag PCTL74; /* offset: 0x010A size: 8 bit */ - ME_PCTL_8B_tag PCTL75; /* offset: 0x010B size: 8 bit */ - ME_PCTL_8B_tag PCTL76; /* offset: 0x010C size: 8 bit */ - ME_PCTL_8B_tag PCTL77; /* offset: 0x010D size: 8 bit */ - ME_PCTL_8B_tag PCTL78; /* offset: 0x010E size: 8 bit */ - ME_PCTL_8B_tag PCTL79; /* offset: 0x010F size: 8 bit */ - ME_PCTL_8B_tag PCTL80; /* offset: 0x0110 size: 8 bit */ - ME_PCTL_8B_tag PCTL81; /* offset: 0x0111 size: 8 bit */ - ME_PCTL_8B_tag PCTL82; /* offset: 0x0112 size: 8 bit */ - ME_PCTL_8B_tag PCTL83; /* offset: 0x0113 size: 8 bit */ - ME_PCTL_8B_tag PCTL84; /* offset: 0x0114 size: 8 bit */ - ME_PCTL_8B_tag PCTL85; /* offset: 0x0115 size: 8 bit */ - ME_PCTL_8B_tag PCTL86; /* offset: 0x0116 size: 8 bit */ - ME_PCTL_8B_tag PCTL87; /* offset: 0x0117 size: 8 bit */ - ME_PCTL_8B_tag PCTL88; /* offset: 0x0118 size: 8 bit */ - ME_PCTL_8B_tag PCTL89; /* offset: 0x0119 size: 8 bit */ - ME_PCTL_8B_tag PCTL90; /* offset: 0x011A size: 8 bit */ - ME_PCTL_8B_tag PCTL91; /* offset: 0x011B size: 8 bit */ - ME_PCTL_8B_tag PCTL92; /* offset: 0x011C size: 8 bit */ - ME_PCTL_8B_tag PCTL93; /* offset: 0x011D size: 8 bit */ - ME_PCTL_8B_tag PCTL94; /* offset: 0x011E size: 8 bit */ - ME_PCTL_8B_tag PCTL95; /* offset: 0x011F size: 8 bit */ - ME_PCTL_8B_tag PCTL96; /* offset: 0x0120 size: 8 bit */ - ME_PCTL_8B_tag PCTL97; /* offset: 0x0121 size: 8 bit */ - ME_PCTL_8B_tag PCTL98; /* offset: 0x0122 size: 8 bit */ - ME_PCTL_8B_tag PCTL99; /* offset: 0x0123 size: 8 bit */ - ME_PCTL_8B_tag PCTL100; /* offset: 0x0124 size: 8 bit */ - ME_PCTL_8B_tag PCTL101; /* offset: 0x0125 size: 8 bit */ - ME_PCTL_8B_tag PCTL102; /* offset: 0x0126 size: 8 bit */ - ME_PCTL_8B_tag PCTL103; /* offset: 0x0127 size: 8 bit */ - ME_PCTL_8B_tag PCTL104; /* offset: 0x0128 size: 8 bit */ - ME_PCTL_8B_tag PCTL105; /* offset: 0x0129 size: 8 bit */ - ME_PCTL_8B_tag PCTL106; /* offset: 0x012A size: 8 bit */ - ME_PCTL_8B_tag PCTL107; /* offset: 0x012B size: 8 bit */ - ME_PCTL_8B_tag PCTL108; /* offset: 0x012C size: 8 bit */ - ME_PCTL_8B_tag PCTL109; /* offset: 0x012D size: 8 bit */ - ME_PCTL_8B_tag PCTL110; /* offset: 0x012E size: 8 bit */ - ME_PCTL_8B_tag PCTL111; /* offset: 0x012F size: 8 bit */ - ME_PCTL_8B_tag PCTL112; /* offset: 0x0130 size: 8 bit */ - ME_PCTL_8B_tag PCTL113; /* offset: 0x0131 size: 8 bit */ - ME_PCTL_8B_tag PCTL114; /* offset: 0x0132 size: 8 bit */ - ME_PCTL_8B_tag PCTL115; /* offset: 0x0133 size: 8 bit */ - ME_PCTL_8B_tag PCTL116; /* offset: 0x0134 size: 8 bit */ - ME_PCTL_8B_tag PCTL117; /* offset: 0x0135 size: 8 bit */ - ME_PCTL_8B_tag PCTL118; /* offset: 0x0136 size: 8 bit */ - ME_PCTL_8B_tag PCTL119; /* offset: 0x0137 size: 8 bit */ - ME_PCTL_8B_tag PCTL120; /* offset: 0x0138 size: 8 bit */ - ME_PCTL_8B_tag PCTL121; /* offset: 0x0139 size: 8 bit */ - ME_PCTL_8B_tag PCTL122; /* offset: 0x013A size: 8 bit */ - ME_PCTL_8B_tag PCTL123; /* offset: 0x013B size: 8 bit */ - ME_PCTL_8B_tag PCTL124; /* offset: 0x013C size: 8 bit */ - ME_PCTL_8B_tag PCTL125; /* offset: 0x013D size: 8 bit */ - ME_PCTL_8B_tag PCTL126; /* offset: 0x013E size: 8 bit */ - ME_PCTL_8B_tag PCTL127; /* offset: 0x013F size: 8 bit */ - ME_PCTL_8B_tag PCTL128; /* offset: 0x0140 size: 8 bit */ - ME_PCTL_8B_tag PCTL129; /* offset: 0x0141 size: 8 bit */ - ME_PCTL_8B_tag PCTL130; /* offset: 0x0142 size: 8 bit */ - ME_PCTL_8B_tag PCTL131; /* offset: 0x0143 size: 8 bit */ - ME_PCTL_8B_tag PCTL132; /* offset: 0x0144 size: 8 bit */ - ME_PCTL_8B_tag PCTL133; /* offset: 0x0145 size: 8 bit */ - ME_PCTL_8B_tag PCTL134; /* offset: 0x0146 size: 8 bit */ - ME_PCTL_8B_tag PCTL135; /* offset: 0x0147 size: 8 bit */ - ME_PCTL_8B_tag PCTL136; /* offset: 0x0148 size: 8 bit */ - ME_PCTL_8B_tag PCTL137; /* offset: 0x0149 size: 8 bit */ - ME_PCTL_8B_tag PCTL138; /* offset: 0x014A size: 8 bit */ - ME_PCTL_8B_tag PCTL139; /* offset: 0x014B size: 8 bit */ - ME_PCTL_8B_tag PCTL140; /* offset: 0x014C size: 8 bit */ - ME_PCTL_8B_tag PCTL141; /* offset: 0x014D size: 8 bit */ - ME_PCTL_8B_tag PCTL142; /* offset: 0x014E size: 8 bit */ - ME_PCTL_8B_tag PCTL143; /* offset: 0x014F size: 8 bit */ - }; - - }; - } ME_tag; - - -#define ME (*(volatile ME_tag *) 0xC3FDC000UL) - - - -/****************************************************************/ -/* */ -/* Module: OSC */ -/* */ -/****************************************************************/ - - typedef union { /* OSC_CTL - Control Register */ - uint32_t R; - struct { - uint32_t OSCBYP:1; /* High Frequency Oscillator Bypass */ - uint32_t:7; - uint32_t EOCV:8; /* End of Count Value */ - uint32_t M_OSC:1; /* High Frequency Oscillator Clock Interrupt Mask */ - uint32_t:2; - uint32_t OSCDIV:5; /* High Frequency Oscillator Division Factor */ - uint32_t I_OSC:1; /* High Frequency Oscillator Clock Interrupt */ - uint32_t:5; - uint32_t S_OSC:1; - uint32_t OSCON:1; } B; - } OSC_CTL_32B_tag; - - - - typedef struct OSC_struct_tag { /* start of OSC_tag */ - /* OSC_CTL - Control Register */ - OSC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */ - } OSC_tag; - - -#define OSC (*(volatile OSC_tag *) 0xC3FE0000UL) - - - -/****************************************************************/ -/* */ -/* Module: RC */ -/* */ -/****************************************************************/ - - typedef union { /* RC_CTL - Control Register */ - uint32_t R; - struct { - uint32_t:10; - uint32_t RCTRIM:6; /* Main RC Trimming Bits */ - uint32_t:3; - uint32_t RCDIV:5; /* Main RC Clock Division Factor */ - uint32_t:2; - uint32_t S_RC_STDBY:1; /* MRC Oscillator Powerdown Status */ - uint32_t:5; - } B; - } RC_CTL_32B_tag; - - - - typedef struct RC_struct_tag { /* start of RC_tag */ - /* RC_CTL - Control Register */ - RC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */ - } RC_tag; - - -#define RC (*(volatile RC_tag *) 0xC3FE0060UL) - - - -/****************************************************************/ -/* */ -/* Module: PLLD */ -/* */ -/****************************************************************/ - - typedef union { /* PLLD_CR - Control Register */ - uint32_t R; - struct { - uint32_t:2; - uint32_t IDF:4; /* PLL Input Division Factor */ - uint32_t ODF:2; /* PLL Output Division Factor */ - uint32_t:1; - uint32_t NDIV:7; /* PLL Loop Division Factor */ - uint32_t:7; - uint32_t EN_PLL_SW:1; /* Enable Progressive Clock Switching */ - uint32_t MODE:1; /* Activate 1:1 Mode */ - uint32_t UNLOCK_ONCE:1; /* PLL Loss of Lock */ - uint32_t M_LOCK:1; /* Mask for the i_lock Output Interrupt */ - uint32_t I_LOCK:1; /* PLL Lock Signal Toggle Indicator */ - uint32_t S_LOCK:1; /* PLL has Aquired Lock */ - uint32_t PLL_FAIL_MASK:1; /* PLL Fail Mask */ - uint32_t PLL_FAIL_FLAG:1; /* PLL Fail Flag */ - uint32_t PLL_ON:1; /* PLL ON Bit */ - } B; - } PLLD_CR_32B_tag; - - typedef union { /* PLLD_MR - PLLD Modulation Register */ - uint32_t R; - struct { - uint32_t STRB_BYPASS:1; /* Strobe Bypass */ - uint32_t:1; - uint32_t SPRD_SEL:1; /* Spread Type Selection */ - uint32_t MOD_PERIOD:13; /* Modulation Period */ -#ifndef USE_FIELD_ALIASES_PLLD - uint32_t SSCG_EN:1; /* Spread Spectrum Clock Generation Enable */ -#else - uint32_t FM_EN:1; /* deprecated name - please avoid */ -#endif - uint32_t INC_STEP:15; /* Increment Step */ - } B; - } PLLD_MR_32B_tag; - - - - typedef struct PLLD_struct_tag { /* start of PLLD_tag */ - /* PLLD_CR - Control Register */ - PLLD_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ - /* PLLD_MR - PLLD Modulation Register */ - PLLD_MR_32B_tag MR; /* offset: 0x0004 size: 32 bit */ - - uint32_t plld_reserved[6]; - } PLLD_tag; - - -#define PLLD0 (*(volatile PLLD_tag *) 0xC3FE00A0UL) -#define PLLD1 (*(volatile PLLD_tag *) 0xC3FE00C0UL) - - - -/****************************************************************/ -/* */ -/* Module: CMU */ -/* */ -/****************************************************************/ - - typedef union { /* CMU_CSR - Control Status Register */ - uint32_t R; - struct { - uint32_t:8; - uint32_t SFM:1; /* Start Frequency Measure */ - uint32_t:13; -#ifndef USE_FIELD_ALIASES_RGM - uint32_t CKSEL1:2; /* RC Oscillator(s) Selection Bit */ -#else - uint32_t CLKSEL1:2; /* deprecated name - please avoid */ -#endif - uint32_t:5; - uint32_t RCDIV:2; /* RCfast Clock Division Factor */ - uint32_t CME_A:1; /* PLL_A Clock Monitor Enable */ - } B; - } CMU_CSR_32B_tag; - - typedef union { /* CMU_FDR - Frequency Display Register */ - uint32_t R; - struct { - uint32_t:12; - uint32_t FD:20; /* Measured Frequency Bits */ - } B; - } CMU_FDR_32B_tag; - - typedef union { /* CMU_HFREFR_A - High Frequency Reference Register */ - uint32_t R; - struct { - uint32_t:20; - uint32_t HFREF_A:12; /* High Frequency Reference Value */ - } B; - } CMU_HFREFR_A_32B_tag; - - typedef union { /* CMU_LFREFR_A - Low Frequency Reference Register */ - uint32_t R; - struct { - uint32_t:20; - uint32_t LFREF_A:12; /* Low Frequency Reference Value */ - } B; - } CMU_LFREFR_A_32B_tag; - - typedef union { /* CMU_ISR - Interrupt Status Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t FLCI_A:1; /* PLL_A Clock Frequency less than Reference Clock Interrupt */ -#ifndef USE_FIELD_ALIASES_RGM - uint32_t FHH_AI:1; /* PLL_A Clock Frequency higher than high Reference Interrupt */ -#else - uint32_t FHHI_A:1; /* deprecated name - please avoid */ -#endif - uint32_t FLLI_A:1; /* PLL_A Clock Frequency less than low Reference Interrupt */ - uint32_t OLRI:1; /* Oscillator Frequency less than RC Frequency Interrupt */ - } B; - } CMU_ISR_32B_tag; - - typedef union { /* CMU_IMR - Interrupt Mask Register */ - uint32_t R; - } CMU_IMR_32B_tag; - - typedef union { /* CMU_MDR - Measurement Duration Register */ - uint32_t R; - struct { - uint32_t:12; - uint32_t MD:20; /* Measurment Duration Bits */ - } B; - } CMU_MDR_32B_tag; - - - - typedef struct CMU_struct_tag { /* start of CMU_tag */ - /* CMU_CSR - Control Status Register */ - CMU_CSR_32B_tag CSR; /* offset: 0x0000 size: 32 bit */ - /* CMU_FDR - Frequency Display Register */ - CMU_FDR_32B_tag FDR; /* offset: 0x0004 size: 32 bit */ - /* CMU_HFREFR_A - High Frequency Reference Register */ - CMU_HFREFR_A_32B_tag HFREFR_A; /* offset: 0x0008 size: 32 bit */ - /* CMU_LFREFR_A - Low Frequency Reference Register */ - CMU_LFREFR_A_32B_tag LFREFR_A; /* offset: 0x000C size: 32 bit */ - /* CMU_ISR - Interrupt Status Register */ - CMU_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */ - /* CMU_IMR - Interrupt Mask Register */ - CMU_IMR_32B_tag IMR; /* offset: 0x0014 size: 32 bit */ - /* CMU_MDR - Measurement Duration Register */ - CMU_MDR_32B_tag MDR; /* offset: 0x0018 size: 32 bit */ - } CMU_tag; - - -#define CMU0 (*(volatile CMU_tag *) 0xC3FE0100UL) -#define CMU1 (*(volatile CMU_tag *) 0xC3FE0120UL) -#define CMU2 (*(volatile CMU_tag *) 0xC3FE0140UL) - - - -/****************************************************************/ -/* */ -/* Module: CGM */ -/* */ -/****************************************************************/ - - typedef union { /* Output Clock Enable Register */ - uint32_t R; - uint8_t BYTE[4]; /* individual bytes can be accessed */ - uint16_t HALF[2]; /* individual halfwords can be accessed */ - uint32_t WORD; /* individual words can be accessed */ - struct { - uint32_t:31; - uint32_t EN:1; /* Clock Enable Bit */ - } B; - } CGM_OC_EN_32B_tag; - - typedef union { /* Output Clock Division Select Register */ - uint32_t R; - uint8_t BYTE[4]; /* individual bytes can be accessed */ - uint16_t HALF[2]; /* individual halfwords can be accessed */ - uint32_t WORD; /* individual words can be accessed */ - struct { - uint32_t:2; - uint32_t SELDIV:2; /* Output Clock Division Select */ - uint32_t SELCTL:4; /* Output Clock Source Selection Control */ - uint32_t:24; - } B; - } CGM_OCDS_SC_32B_tag; - - typedef union { /* System Clock Select Status Register */ - uint32_t R; - uint8_t BYTE[4]; /* individual bytes can be accessed */ - uint16_t HALF[2]; /* individual halfwords can be accessed */ - uint32_t WORD; /* individual words can be accessed */ - struct { - uint32_t:4; - uint32_t SELSTAT:4; /* System Clock Source Selection Status */ - uint32_t:24; - } B; - } CGM_SC_SS_32B_tag; - - typedef union { /* System Clock Divider Configuration Register */ - uint32_t R; - uint8_t BYTE[4]; /* individual bytes can be accessed */ - uint16_t HALF[2]; /* individual halfwords can be accessed */ - uint32_t WORD; /* individual words can be accessed */ - struct { - uint32_t DE0:1; /* Divider 0 Enable */ - uint32_t:3; - uint32_t DIV0:4; /* Divider 0 Value */ - uint32_t:24; - } B; - } CGM_SC_DC0_3_32B_tag; - - - /* Register layout for all registers SC_DC... */ - - typedef union { /* System Clock Divider Configuration Register */ - uint8_t R; - struct { - uint8_t DE:1; /* Divider Enable */ - uint8_t:3; - uint8_t DIV:4; /* Divider Division Value */ - } B; - } CGM_SC_DC_8B_tag; - - - /* Register layout for all registers AC_SC... */ - - typedef union { /* Auxiliary Clock Select Control Registers */ - uint32_t R; - uint8_t BYTE[4]; /* individual bytes can be accessed */ - uint16_t HALF[2]; /* individual halfwords can be accessed */ - uint32_t WORD; /* individual words can be accessed */ - struct { - uint32_t:4; - uint32_t SELCTL:4; /* Auxliary Clock Source Selection Control */ - uint32_t:24; - } B; - } CGM_AC_SC_32B_tag; - - - /* Register layout for all registers AC_DC0_3... */ - - typedef union { /* Auxiliary Clock Divider Configuration Registers */ - uint32_t R; - struct { - uint32_t DE0:1; /* Divider 0 Enable */ - uint32_t:3; - uint32_t DIV0:4; /* Divider 0 Value */ - uint32_t DE1:1; /* Divider 1 Enable */ - uint32_t:3; - uint32_t DIV1:4; /* Divider 1 Value */ - uint32_t:16; - } B; - } CGM_AC_DC0_3_32B_tag; - - - typedef struct CGM_AUXCLK_struct_tag { - - /* Auxiliary Clock Select Control Registers */ - CGM_AC_SC_32B_tag AC_SC; /* relative offset: 0x0000 */ - /* Auxiliary Clock Divider Configuration Registers */ - CGM_AC_DC0_3_32B_tag AC_DC0_3; /* relative offset: 0x0004 */ - - } CGM_AUXCLK_tag; - - - typedef struct CGM_struct_tag { /* start of CGM_tag */ - OSC_CTL_32B_tag OSC_CTL; /* offset: 0x0000 size: 32 bit */ - int8_t CGM_reserved_0004[92]; - RC_CTL_32B_tag RC_CTL; /* offset: 0x0060 size: 32 bit */ - int8_t CGM_reserved_0064[60]; - PLLD_tag FMPLL[2]; /* offset: 0x00A0 (0x0020 x 2) */ - int8_t CGM_reserved_00E0[32]; - CMU_CSR_32B_tag CMU_0_CSR; /* offset: 0x0100 size: 32 bit */ - CMU_FDR_32B_tag CMU_0_FDR; /* offset: 0x0104 size: 32 bit */ - CMU_HFREFR_A_32B_tag CMU_0_HFREFR_A; /* offset: 0x0108 size: 32 bit */ - CMU_LFREFR_A_32B_tag CMU_0_LFREFR_A; /* offset: 0x010C size: 32 bit */ - CMU_ISR_32B_tag CMU_0_ISR; /* offset: 0x0110 size: 32 bit */ - CMU_IMR_32B_tag CMU_0_IMR; /* offset: 0x0114 size: 32 bit */ - CMU_MDR_32B_tag CMU_0_MDR; /* offset: 0x0118 size: 32 bit */ - int8_t CGM_reserved_011C[4]; - CMU_CSR_32B_tag CMU_1_CSR; /* offset: 0x0120 size: 32 bit */ - int8_t CGM_reserved_0124[4]; - CMU_HFREFR_A_32B_tag CMU_1_HFREFR_A; /* offset: 0x0128 size: 32 bit */ - CMU_LFREFR_A_32B_tag CMU_1_LFREFR_A; /* offset: 0x012C size: 32 bit */ - CMU_ISR_32B_tag CMU_1_ISR; /* offset: 0x0130 size: 32 bit */ - int8_t CGM_reserved_0134[572]; - union { - /* Output Clock Enable Register */ - CGM_OC_EN_32B_tag OC_EN; /* offset: 0x0370 size: 32 bit */ - - CGM_OC_EN_32B_tag OCEN; /* deprecated - please avoid */ - - }; - union { - /* Output Clock Division Select Register */ - CGM_OCDS_SC_32B_tag OCDS_SC; /* offset: 0x0374 size: 32 bit */ - - CGM_OCDS_SC_32B_tag OCDSSC; /* deprecated - please avoid */ - - }; - union { - /* Output Clock Division Select Register */ - CGM_SC_SS_32B_tag SC_SS; /* offset: 0x0378 size: 32 bit */ - - CGM_SC_SS_32B_tag SCSS; /* deprecated - please avoid */ - - }; /* System Clock Select Status Register */ - union { - struct { - /* System Clock Divider Configuration Register */ - CGM_SC_DC_8B_tag SC_DC[2]; /* offset: 0x037C (0x0001 x 2) */ - int8_t CGM_reserved_037E_E0[2]; - }; - - struct { - /* System Clock Divider Configuration Register */ - CGM_SC_DC_8B_tag SC_DC0; /* offset: 0x037C size: 8 bit */ - CGM_SC_DC_8B_tag SC_DC1; /* offset: 0x037D size: 8 bit */ - int8_t CGM_reserved_037E_E1[2]; - }; - - /* System Clock Divider Configuration Register */ - union { - CGM_SC_DC0_3_32B_tag SC_DC0_3; /* offset: 0x037C size: 32 bit */ - CGM_SC_DC0_3_32B_tag SCDC; /* deprecated - please avoid */ - }; - }; - union { - /* Register set AUXCLK */ - CGM_AUXCLK_tag AUXCLK[6]; /* offset: 0x0380 (0x0008 x 6) */ - - struct { - union { - /* Auxiliary Clock Select Control Registers */ - CGM_AC_SC_32B_tag AC0_SC; /* offset: 0x0380 size: 32 bit */ - - CGM_AC_SC_32B_tag AC0SC; /* deprecated - please avoid */ - - }; - union { - /* Auxiliary Clock Divider Configuration Registers */ - CGM_AC_DC0_3_32B_tag AC0_DC0_3; /* offset: 0x0384 size: 32 bit */ - - CGM_AC_DC0_3_32B_tag AC0DC; /* deprecated - please avoid */ - - }; - union { - /* Auxiliary Clock Select Control Registers */ - CGM_AC_SC_32B_tag AC1_SC; /* offset: 0x0388 size: 32 bit */ - - CGM_AC_SC_32B_tag AC1SC; /* deprecated - please avoid */ - - }; - union { - /* Auxiliary Clock Divider Configuration Registers */ - CGM_AC_DC0_3_32B_tag AC1_DC0_3; /* offset: 0x038C size: 32 bit */ - - CGM_AC_DC0_3_32B_tag AC1DC; /* deprecated - please avoid */ - - }; - union { - /* Auxiliary Clock Select Control Registers */ - CGM_AC_SC_32B_tag AC2_SC; /* offset: 0x0390 size: 32 bit */ - - CGM_AC_SC_32B_tag AC2SC; /* deprecated - please avoid */ - - }; - union { - /* Auxiliary Clock Divider Configuration Registers */ - CGM_AC_DC0_3_32B_tag AC2_DC0_3; /* offset: 0x0394 size: 32 bit */ - - CGM_AC_DC0_3_32B_tag AC2DC; /* deprecated - please avoid */ - - }; - union { - /* Auxiliary Clock Select Control Registers */ - CGM_AC_SC_32B_tag AC3_SC; /* offset: 0x0398 size: 32 bit */ - - CGM_AC_SC_32B_tag AC3SC; /* deprecated - please avoid */ - - }; - union { - /* Auxiliary Clock Divider Configuration Registers */ - CGM_AC_DC0_3_32B_tag AC3_DC0_3; /* offset: 0x039C size: 32 bit */ - - CGM_AC_DC0_3_32B_tag AC3DC; /* deprecated - please avoid */ - - }; - union { - /* Auxiliary Clock Select Control Registers */ - CGM_AC_SC_32B_tag AC4_SC; /* offset: 0x03A0 size: 32 bit */ - - CGM_AC_SC_32B_tag AC4SC; /* deprecated - please avoid */ - - }; - union { - /* Auxiliary Clock Divider Configuration Registers */ - CGM_AC_DC0_3_32B_tag AC4_DC0_3; /* offset: 0x03A4 size: 32 bit */ - - CGM_AC_DC0_3_32B_tag AC4DC; /* deprecated - please avoid */ - }; - union { - /* Auxiliary Clock Select Control Registers */ - CGM_AC_SC_32B_tag AC5_SC; /* offset: 0x03A8 size: 32 bit */ - - CGM_AC_SC_32B_tag AC5SC; /* deprecated - please avoid */ - - }; - union { - /* Auxiliary Clock Divider Configuration Registers */ - CGM_AC_DC0_3_32B_tag AC5_DC0_3; /* offset: 0x03AC size: 32 bit */ - - CGM_AC_DC0_3_32B_tag AC5DC; /* deprecated - please avoid */ - - }; - }; - - }; - } CGM_tag; - - -#define CGM (*(volatile CGM_tag *) 0xC3FE0000UL) - - - -/****************************************************************/ -/* */ -/* Module: RGM */ -/* */ -/****************************************************************/ - - typedef union { /* Functional Event Status Register */ - uint16_t R; - struct { - uint16_t F_EXR:1; /* Flag for External Reset */ - uint16_t F_FCCU_HARD:1; /* Flag for FCCU hard reaction request */ - uint16_t F_FCCU_SOFT:1; /* Flag for FCCU soft reaction request */ - uint16_t F_ST_DONE:1; /* Flag for self-test completed */ -#ifndef USE_FIELD_ALIASES_RGM - uint16_t F_CMU12_FHL:1; /* Flag for CMU 1/2 clock freq. too high/low */ -#else - uint16_t F_CMU1_FHL:1; /* deprecated name - please avoid */ -#endif - uint16_t F_FL_ECC_RCC:1; /* Flag for Flash, ECC, or lock-step error */ - uint16_t F_PLL1:1; /* Flag for PLL1 fail */ - uint16_t F_SWT:1; /* Flag for Software Watchdog Timer */ - uint16_t F_FCCU_SAFE:1; /* Flag for FCCU SAFE mode request */ - uint16_t F_CMU0_FHL:1; /* Flag for CMU 0 clock freq. too high/low */ - uint16_t F_CMU0_OLR:1; /* Flag for oscillator freq. too low */ - uint16_t F_PLL0:1; /* Flag for PLL0 fail */ - uint16_t F_CWD:1; /* Flag for Core Watchdog Reset */ - uint16_t F_SOFT:1; /* Flag for software reset */ - uint16_t F_CORE:1; /* Flag for core reset */ - uint16_t F_JTAG:1; /* Flag for JTAG initiated reset */ - } B; - } RGM_FES_16B_tag; - - typedef union { /* Destructive Event Status Register */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_RGM - uint16_t F_POR:1; /* Flag for Power on Reset */ -#else - uint16_t POR:1; /* deprecated name - please avoid */ -#endif - uint16_t:7; - uint16_t F_COMP:1; /* Flag for comparator error */ - uint16_t F_LVD27_IO:1; /* Flag for 2.7V low-voltage detected (I/O) */ - uint16_t F_LVD27_FLASH:1; /* Flag for 2.7V low-voltage detected (Flash) */ - uint16_t F_LVD27_VREG:1; /* Flag for 2.7V low-voltage detected (VREG) */ - uint16_t:2; - uint16_t F_HVD12:1; /* Flag for 1.2V high-voltage detected */ -#ifndef USE_FIELD_ALIASES_RGM - uint16_t F_LVD12:1; /* Flag for 1.2V low-voltage detected */ -#else - uint16_t F_LVD12_PD0:1; /* deprecated name - please avoid */ -#endif - } B; - } RGM_DES_16B_tag; - - typedef union { /* Functional Event Reset Disable Register */ - uint16_t R; - struct { - uint16_t D_EXR:1; /* Disable External Pad Event Reset */ - uint16_t D_FCCU_HARD:1; /* Disable FCCU hard reaction request */ - uint16_t D_FCCU_SOFT:1; /* Disable FCCU soft reaction request */ - uint16_t D_ST_DONE:1; /* Disable self-test completed */ -#ifndef USE_FIELD_ALIASES_RGM - uint16_t D_CMU12_FHL:1; /* Disable CMU 1/2 clock freq. too high/low */ -#else - uint16_t D_CMU1_FHL:1; /* deprecated name - please avoid */ -#endif - uint16_t D_FL_ECC_RCC:1; /* Disable Flash, ECC, or lock-step error */ - uint16_t D_PLL1:1; /* Disable PLL1 fail */ - uint16_t D_SWT:1; /* Disable Software Watchdog Timer */ - uint16_t D_FCCU_SAFE:1; /* Disable FCCU SAFE mode request */ - uint16_t D_CMU0_FHL:1; /* Disable CMU 0 clock freq. too high/low */ - uint16_t D_CMU0_OLR:1; /* Disable oscillator freq. too low */ - uint16_t D_PLL0:1; /* Disable PLL0 fail */ - uint16_t D_CWD:1; /* Disable Core Watchdog Reset */ - uint16_t D_SOFT:1; /* Disable software reset */ - uint16_t D_CORE:1; /* Disable core reset */ - uint16_t D_JTAG:1; /* Disable JTAG initiated reset */ - } B; - } RGM_FERD_16B_tag; - - typedef union { /* Destructive Event Reset Disable Register */ - uint16_t R; - struct { - uint16_t:8; - uint16_t D_COMP:1; /* Disable comparator error */ - uint16_t D_LVD27_IO:1; /* Disable 2.7V low-voltage detected (I/O) */ - uint16_t D_LVD27_FLASH:1; /* Disable 2.7V low-voltage detected (Flash) */ - uint16_t D_LVD27_VREG:1; /* Disable 2.7V low-voltage detected (VREG) */ - uint16_t:2; - uint16_t D_HVD12:1; /* Disable 1.2V high-voltage detected */ -#ifndef USE_FIELD_ALIASES_RGM - uint16_t D_LVD12:1; /* Disable 1.2V low-voltage detected */ -#else - uint16_t D_LVD12_PD0:1; /* deprecated name - please avoid */ -#endif - } B; - } RGM_DERD_16B_tag; - - typedef union { /* Functional Event Alternate Request Register */ - uint16_t R; - struct { - uint16_t:4; -#ifndef USE_FIELD_ALIASES_RGM - uint16_t AR_CMU12_FHL:1; /* Alternate Request for CMU1/2 clock freq. too high/low */ -#else - uint16_t AR_CMU1_FHL:1; /* deprecated name - please avoid */ -#endif - uint16_t:1; - uint16_t AR_PLL1:1; /* Alternate Request for PLL1 fail */ - uint16_t:1; - uint16_t AR_FCCU_SAVE:1; /* Alternate Request for FCCU SAFE mode request */ - uint16_t AR_CMU0_FHL:1; /* Alternate Request for CMU0 clock freq. - too high/low */ - uint16_t AR_CMU0_OLR:1; /* Alternate Request for oscillator freq. too low */ - uint16_t AR_PLL0:1; /* Alternate Request for PLL0 fail */ - uint16_t AR_CWD:1; /* Alternate Request for core watchdog reset */ - uint16_t:3; - } B; - } RGM_FEAR_16B_tag; - - typedef union { /* Functional Event Short Sequence Register */ - uint16_t R; - struct { - uint16_t SS_EXR:1; /* Short Sequence for External Reset */ - uint16_t SS_FCCU_HARD:1; /* Short Sequence for FCCU hard reaction request */ - uint16_t SS_FCCU_SOFT:1; /* Short Sequence for FCCU soft reaction request */ - uint16_t SS_ST_DONE:1; /* Short Sequence for self-test completed */ -#ifndef USE_FIELD_ALIASES_RGM - uint16_t SS_CMU12_FHL:1; /* Short Sequence for CMU 1/2 clock freq. too high/low */ -#else - uint16_t SS_CMU1_FHL:1; /* deprecated name - please avoid */ -#endif - uint16_t SS_FL_ECC_RCC:1; /* Short Sequence for Flash, ECC, or lock-step error */ - uint16_t SS_PLL1:1; /* Short Sequence for PLL1 fail */ - uint16_t SS_SWT:1; /* Short Sequence for Software Watchdog Timer */ - uint16_t:1; - uint16_t SS_CMU0_FHL:1; /* Short Sequence for CMU 0 clock freq. too high/low */ - uint16_t SS_CMU0_OLR:1; /* Short Sequence for oscillator freq. too low */ - uint16_t SS_PLL0:1; /* Short Sequence for PLL0 fail */ - uint16_t SS_CWD:1; /* Short Sequence for Core Watchdog Reset */ - uint16_t SS_SOFT:1; /* Short Sequence for software reset */ - uint16_t SS_CORE:1; /* Short Sequence for core reset */ - uint16_t SS_JTAG:1; /* Short Sequence for JTAG initiated reset */ - } B; - } RGM_FESS_16B_tag; - - typedef union { /* Functional Bidirectional Reset Enable Register */ - uint16_t R; - struct { - uint16_t BE_EXR:1; /* Bidirectional Reset Enable for External Reset */ - uint16_t BE_FCCU_HARD:1; /* Bidirectional Reset Enable for FCCU hard reaction request */ - uint16_t BE_FCCU_SOFT:1; /* Bidirectional Reset Enable for FCCU soft reaction request */ - uint16_t BE_ST_DONE:1; /* Bidirectional Reset Enable for self-test completed */ -#ifndef USE_FIELD_ALIASES_RGM - uint16_t BE_CMU12_FHL:1; /* Bidirectional Reset Enable for CMU 1/2 clock freq. too high/low */ -#else - uint16_t BE_CMU1_FHL:1; /* deprecated name - please avoid */ -#endif - uint16_t BE_FL_ECC_RCC:1; /* Bidirectional Reset Enable for Flash, ECC, or lock-step error */ - uint16_t BE_PLL1:1; /* Bidirectional Reset Enable for PLL1 fail */ - uint16_t BE_SWT:1; /* Bidirectional Reset Enable for Software Watchdog Timer */ - uint16_t:1; - uint16_t BE_CMU0_FHL:1; /* Bidirectional Reset Enable for CMU 0 clock freq. too high/low */ - uint16_t BE_CMU0_OLR:1; /* Bidirectional Reset Enable for oscillator freq. too low */ - uint16_t BE_PLL0:1; /* Bidirectional Reset Enable for PLL0 fail */ - uint16_t BE_CWD:1; /* Bidirectional Reset Enable for Core Watchdog Reset */ - uint16_t BE_SOFT:1; /* Bidirectional Reset Enable for software reset */ - uint16_t BE_CORE:1; /* Bidirectional Reset Enable for core reset */ - uint16_t BE_JTAG:1; /* Bidirectional Reset Enable for JTAG initiated reset */ - } B; - } RGM_FBRE_16B_tag; - - - - typedef struct RGM_struct_tag { /* start of RGM_tag */ - /* Functional Event Status Register */ - RGM_FES_16B_tag FES; /* offset: 0x0000 size: 16 bit */ - /* Destructive Event Status Register */ - RGM_DES_16B_tag DES; /* offset: 0x0002 size: 16 bit */ - /* Functional Event Reset Disable Register */ - RGM_FERD_16B_tag FERD; /* offset: 0x0004 size: 16 bit */ - /* Destructive Event Reset Disable Register */ - RGM_DERD_16B_tag DERD; /* offset: 0x0006 size: 16 bit */ - int8_t RGM_reserved_0008[8]; - /* Functional Event Alternate Request Register */ - RGM_FEAR_16B_tag FEAR; /* offset: 0x0010 size: 16 bit */ - int8_t RGM_reserved_0012[6]; - /* Functional Event Short Sequence Register */ - RGM_FESS_16B_tag FESS; /* offset: 0x0018 size: 16 bit */ - int8_t RGM_reserved_001A[2]; - /* Functional Bidirectional Reset Enable Register */ - RGM_FBRE_16B_tag FBRE; /* offset: 0x001C size: 16 bit */ - } RGM_tag; - - -#define RGM (*(volatile RGM_tag *) 0xC3FE4000UL) - - - -/****************************************************************/ -/* */ -/* Module: PCU */ -/* */ -/****************************************************************/ - - - /* Register layout for all registers PCONF... */ - - typedef union { /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ - uint32_t R; - struct { - uint32_t:18; - uint32_t STBY0:1; /* Power domain control during STBY0 */ - uint32_t:2; - uint32_t STOP0:1; /* Power domain control during STOP0 */ - uint32_t:1; - uint32_t HALT0:1; /* Power domain control during HALT0 */ - uint32_t RUN3:1; /* Power domain control during RUN3 */ - uint32_t RUN2:1; /* Power domain control during RUN2 */ - uint32_t RUN1:1; /* Power domain control during RUN1 */ - uint32_t RUN0:1; /* Power domain control during RUN0 */ - uint32_t DRUN:1; /* Power domain control during DRUN */ - uint32_t SAFE:1; /* Power domain control during SAFE */ - uint32_t TEST:1; /* Power domain control during TEST */ - uint32_t RST:1; /* Power domain control during RST */ - } B; - } PCU_PCONF_32B_tag; - - typedef union { /* PCU_PSTAT - Power Domain Status Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t PD15:1; /* Power Status for Power Domain 15 */ - uint32_t PD14:1; /* Power Status for Power Domain 14 */ - uint32_t PD13:1; /* Power Status for Power Domain 13 */ - uint32_t PD12:1; /* Power Status for Power Domain 12 */ - uint32_t PD11:1; /* Power Status for Power Domain 11 */ - uint32_t PD10:1; /* Power Status for Power Domain 10 */ - uint32_t PD9:1; /* Power Status for Power Domain 9 */ - uint32_t PD8:1; /* Power Status for Power Domain 8 */ - uint32_t PD7:1; /* Power Status for Power Domain 7 */ - uint32_t PD6:1; /* Power Status for Power Domain 6 */ - uint32_t PD5:1; /* Power Status for Power Domain 5 */ - uint32_t PD4:1; /* Power Status for Power Domain 4 */ - uint32_t PD3:1; /* Power Status for Power Domain 3 */ - uint32_t PD2:1; /* Power Status for Power Domain 2 */ - uint32_t PD1:1; /* Power Status for Power Domain 1 */ - uint32_t PD0:1; /* Power Status for Power Domain 0 */ - } B; - } PCU_PSTAT_32B_tag; - - - - typedef struct PCU_struct_tag { /* start of PCU_tag */ - union { - /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ - PCU_PCONF_32B_tag PCONF[16]; /* offset: 0x0000 (0x0004 x 16) */ - - struct { - /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ - PCU_PCONF_32B_tag PCONF0; /* offset: 0x0000 size: 32 bit */ - PCU_PCONF_32B_tag PCONF1; /* offset: 0x0004 size: 32 bit */ - PCU_PCONF_32B_tag PCONF2; /* offset: 0x0008 size: 32 bit */ - PCU_PCONF_32B_tag PCONF3; /* offset: 0x000C size: 32 bit */ - PCU_PCONF_32B_tag PCONF4; /* offset: 0x0010 size: 32 bit */ - PCU_PCONF_32B_tag PCONF5; /* offset: 0x0014 size: 32 bit */ - PCU_PCONF_32B_tag PCONF6; /* offset: 0x0018 size: 32 bit */ - PCU_PCONF_32B_tag PCONF7; /* offset: 0x001C size: 32 bit */ - PCU_PCONF_32B_tag PCONF8; /* offset: 0x0020 size: 32 bit */ - PCU_PCONF_32B_tag PCONF9; /* offset: 0x0024 size: 32 bit */ - PCU_PCONF_32B_tag PCONF10; /* offset: 0x0028 size: 32 bit */ - PCU_PCONF_32B_tag PCONF11; /* offset: 0x002C size: 32 bit */ - PCU_PCONF_32B_tag PCONF12; /* offset: 0x0030 size: 32 bit */ - PCU_PCONF_32B_tag PCONF13; /* offset: 0x0034 size: 32 bit */ - PCU_PCONF_32B_tag PCONF14; /* offset: 0x0038 size: 32 bit */ - PCU_PCONF_32B_tag PCONF15; /* offset: 0x003C size: 32 bit */ - }; - - }; - /* PCU_PSTAT - Power Domain Status Register */ - PCU_PSTAT_32B_tag PSTAT; /* offset: 0x0040 size: 32 bit */ - } PCU_tag; - - -#define PCU (*(volatile PCU_tag *) 0xC3FE8000UL) - - - -/****************************************************************/ -/* */ -/* Module: PMUCTRL */ -/* */ -/****************************************************************/ - - typedef union { /* PMUCTRL_STATHVD - PMU Status Register HVD */ - uint32_t R; - struct { - uint32_t:11; - uint32_t HVDT_LPB:5; /* High Voltage Detector trimming bits LPB bus */ - uint32_t:6; - uint32_t HVD_M:1; /* High Voltage Detector Main */ - uint32_t HVD_B:1; /* High Voltage Detector Backup */ - uint32_t:4; - uint32_t HVD_LP:4; /* High Voltage Detector trimming bits LP bus */ - } B; - } PMUCTRL_STATHVD_32B_tag; - - typedef union { /* PMUCTRL_STATLVD - PMU Status Register LVD */ - uint32_t R; - struct { - uint32_t:11; - uint32_t LVDT_LPB:5; /* Ligh Voltage Detector trimming bits LPB bus */ - uint32_t:6; - uint32_t LVD_M:1; /* Ligh Voltage Detector Main */ - uint32_t LVD_B:1; /* Ligh Voltage Detector Backup */ - uint32_t:4; - uint32_t LVD_LP:4; /* Ligh Voltage Detector trimming bits LP bus */ - } B; - } PMUCTRL_STATLVD_32B_tag; - - typedef union { /* PMUCTRL_STATIREG - PMU Status Register IREG */ - uint32_t R; - struct { - uint32_t:28; - uint32_t IIREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */ - } B; - } PMUCTRL_STATIREG_32B_tag; - - typedef union { /* PMUCTRL_STATEREG - PMU Status Register EREG */ - uint32_t R; - struct { - uint32_t:28; - uint32_t EEREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */ - } B; - } PMUCTRL_STATEREG_32B_tag; - - typedef union { /* PMUCTRL_STATUS - PMU Status Register STATUS */ - uint32_t R; - struct { - uint32_t EBMM:1; /* External Ballast Management Mode */ - uint32_t AEBD:1; /* Automatic External Ballast Detection */ - uint32_t ENPN:1; /* External NPN status flag */ - uint32_t:13; - uint32_t CTB:2; /* Configuration Trace Bits */ - uint32_t:6; - uint32_t CBS:4; /* Current BIST Status */ - uint32_t CPCS:4; /* Current Pmu Configuration Status */ - } B; - } PMUCTRL_STATUS_32B_tag; - - typedef union { /* PMUCTRL_CTRL - PMU Control Register */ - uint32_t R; - struct { - uint32_t:30; - uint32_t SILHT:2; /* Start Idle or LVD or HVD BIST Test */ - } B; - } PMUCTRL_CTRL_32B_tag; - - typedef union { /* PMUCTRL_MASKF - PMU Mask Fault Register */ - uint32_t R; - struct { - uint32_t MF_BB:4; /* Mask Fault Bypass Balast */ - uint32_t:28; - } B; - } PMUCTRL_MASKF_32B_tag; - - typedef union { /* PMUCTRL_FAULT - PMU Fault Monitor Register */ - uint32_t R; - struct { - uint32_t BB_LV:4; /* Bypass Ballast Low Voltage */ - uint32_t:9; - uint32_t FLNCF:1; /* FLash voltage monitor Non Critical Fault */ - uint32_t IONCF:1; /* IO voltage monitor Non Critical Fault */ - uint32_t RENCF:1; /* REgulator voltage monitor Non Critical Fault */ - uint32_t:13; - uint32_t LHCF:1; /* Low High voltage detector Critical Fault */ - uint32_t LNCF:1; /* Low voltage detector Non Critical Fault */ - uint32_t HNCF:1; /* High voltage detector Non Critical Fault */ - } B; - } PMUCTRL_FAULT_32B_tag; - - typedef union { /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */ - uint32_t R; - struct { - uint32_t:10; - uint32_t MFVMP:1; /* Main Flash Voltage Monitor interrupt Pending */ - uint32_t BFVMP:1; /* Backup Flash Voltage Monitor interrupt Pending */ - uint32_t MIVMP:1; /* MAin IO Voltage Monitor interrupt Pending */ - uint32_t BIVMP:1; /* Backup IO Voltage Monitor interrupt Pending */ - uint32_t MRVMP:1; /* Main Regulator Voltage Monitor interrupt Pending */ - uint32_t BRVMP:1; /* Backup Regulator Voltage Monitor interrupt Pending */ - uint32_t:12; - uint32_t MLVDP:1; /* Main Low Voltage Detector error interrupt Pending */ - uint32_t BLVDP:1; /* Backup Low Voltage Detector error interrupt Pending */ - uint32_t MHVDP:1; /* Main High Voltage Detector error interrupt Pending */ - uint32_t BHVDP:1; /* Backup High Voltage Detector error interrupt Pending */ - } B; - } PMUCTRL_IRQS_32B_tag; - - typedef union { /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */ - uint32_t R; - struct { - uint32_t:10; - uint32_t MFVME:1; /* Main Flash Voltage Monitor interrupt Enable */ - uint32_t BFVME:1; /* Backup Flash Voltage Monitor interrupt Enable */ - uint32_t MIVME:1; /* MAin IO Voltage Monitor interrupt Enable */ - uint32_t BIVME:1; /* Backup IO Voltage Monitor interrupt Enable */ - uint32_t MRVME:1; /* Main Regulator Voltage Monitor interrupt Enable */ - uint32_t BRVME:1; /* Backup Regulator Voltage Monitor interrupt Enable */ - uint32_t:12; - uint32_t MLVDE:1; /* Main Low Voltage Detector error interrupt Enable */ - uint32_t BLVDE:1; /* Backup Low Voltage Detector error interrupt Enable */ - uint32_t MHVDE:1; /* Main High Voltage Detector error interrupt Enable */ - uint32_t BHVDE:1; /* Backup High Voltage Detector error interrupt Enable */ - } B; - } PMUCTRL_IRQE_32B_tag; - - - - typedef struct PMUCTRL_struct_tag { /* start of PMUCTRL_tag */ - int8_t PMUCTRL_reserved_0000[4]; - /* PMUCTRL_STATHVD - PMU Status Register HVD */ - PMUCTRL_STATHVD_32B_tag STATHVD; /* offset: 0x0004 size: 32 bit */ - /* PMUCTRL_STATLVD - PMU Status Register LVD */ - PMUCTRL_STATLVD_32B_tag STATLVD; /* offset: 0x0008 size: 32 bit */ - int8_t PMUCTRL_reserved_000C[20]; - /* PMUCTRL_STATIREG - PMU Status Register IREG */ - PMUCTRL_STATIREG_32B_tag STATIREG; /* offset: 0x0020 size: 32 bit */ - /* PMUCTRL_STATEREG - PMU Status Register EREG */ - PMUCTRL_STATEREG_32B_tag STATEREG; /* offset: 0x0024 size: 32 bit */ - int8_t PMUCTRL_reserved_0028[24]; - /* PMUCTRL_STATUS - PMU Status Register STATUS */ - PMUCTRL_STATUS_32B_tag STATUS; /* offset: 0x0040 size: 32 bit */ - /* PMUCTRL_CTRL - PMU Control Register */ - PMUCTRL_CTRL_32B_tag CTRL; /* offset: 0x0044 size: 32 bit */ - int8_t PMUCTRL_reserved_0048[40]; - /* PMUCTRL_MASKF - PMU Mask Fault Register */ - PMUCTRL_MASKF_32B_tag MASKF; /* offset: 0x0070 size: 32 bit */ - /* PMUCTRL_FAULT - PMU Fault Monitor Register */ - PMUCTRL_FAULT_32B_tag FAULT; /* offset: 0x0074 size: 32 bit */ - /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */ - PMUCTRL_IRQS_32B_tag IRQS; /* offset: 0x0078 size: 32 bit */ - /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */ - PMUCTRL_IRQE_32B_tag IRQE; /* offset: 0x007C size: 32 bit */ - } PMUCTRL_tag; - - -#define PMUCTRL (*(volatile PMUCTRL_tag *) 0xC3FE8080UL) - - - -/****************************************************************/ -/* */ -/* Module: PIT_RTI */ -/* */ -/****************************************************************/ - - typedef union { /* PIT_RTI_PITMCR - PIT Module Control Register */ - uint32_t R; - struct { - uint32_t:30; - uint32_t MDIS:1; /* Module Disable. Disable the module clock */ - uint32_t FRZ:1; /* Freeze. Allows the timers to be stoppedwhen the device enters debug mode */ - } B; - } PIT_RTI_PITMCR_32B_tag; - - - /* Register layout for all registers LDVAL... */ - - typedef union { /* PIT_RTI_LDVAL - Timer Load Value Register */ - uint32_t R; - struct { - uint32_t TSV:32; /* Time Start Value Bits */ - } B; - } PIT_RTI_LDVAL_32B_tag; - - - /* Register layout for all registers CVAL... */ - - typedef union { /* PIT_RTI_CVAL - Current Timer Value Register */ - uint32_t R; - struct { - uint32_t TVL:32; /* Current Timer Value Bits */ - } B; - } PIT_RTI_CVAL_32B_tag; - - - /* Register layout for all registers TCTRL... */ - - typedef union { /* PIT_RTI_TCTRL - Timer Control Register */ - uint32_t R; - struct { - uint32_t:30; - uint32_t TIE:1; /* Timer Interrupt Enable Bit */ - uint32_t TEN:1; /* Timer Enable Bit */ - } B; - } PIT_RTI_TCTRL_32B_tag; - - - /* Register layout for all registers TFLG... */ - - typedef union { /* PIT_RTI_TFLG - Timer Flag Register */ - uint32_t R; - struct { - uint32_t:31; - uint32_t TIF:1; /* Timer Interrupt Flag Bit */ - } B; - } PIT_RTI_TFLG_32B_tag; - - - typedef struct PIT_RTI_CHANNEL_struct_tag { - - /* PIT_RTI_LDVAL - Timer Load Value Register */ - PIT_RTI_LDVAL_32B_tag LDVAL; /* relative offset: 0x0000 */ - /* PIT_RTI_CVAL - Current Timer Value Register */ - PIT_RTI_CVAL_32B_tag CVAL; /* relative offset: 0x0004 */ - /* PIT_RTI_TCTRL - Timer Control Register */ - PIT_RTI_TCTRL_32B_tag TCTRL; /* relative offset: 0x0008 */ - /* PIT_RTI_TFLG - Timer Flag Register */ - PIT_RTI_TFLG_32B_tag TFLG; /* relative offset: 0x000C */ - - } PIT_RTI_CHANNEL_tag; - - - typedef struct PIT_RTI_struct_tag { /* start of PIT_RTI_tag */ - /* PIT_RTI_PITMCR - PIT Module Control Register */ - PIT_RTI_PITMCR_32B_tag PITMCR; /* offset: 0x0000 size: 32 bit */ - int8_t PIT_RTI_reserved_0004_C[252]; - union { - /* Register set CHANNEL */ - PIT_RTI_CHANNEL_tag CHANNEL[4]; /* offset: 0x0100 (0x0010 x 4) */ - - PIT_RTI_CHANNEL_tag CH[4]; /* offset: 0x0100 (0x0010 x 4) */ - - struct { - /* PIT_RTI_LDVAL - Timer Load Value Register */ - PIT_RTI_LDVAL_32B_tag LDVAL0; /* offset: 0x0100 size: 32 bit */ - /* PIT_RTI_CVAL - Current Timer Value Register */ - PIT_RTI_CVAL_32B_tag CVAL0; /* offset: 0x0104 size: 32 bit */ - /* PIT_RTI_TCTRL - Timer Control Register */ - PIT_RTI_TCTRL_32B_tag TCTRL0; /* offset: 0x0108 size: 32 bit */ - /* PIT_RTI_TFLG - Timer Flag Register */ - PIT_RTI_TFLG_32B_tag TFLG0; /* offset: 0x010C size: 32 bit */ - /* PIT_RTI_LDVAL - Timer Load Value Register */ - PIT_RTI_LDVAL_32B_tag LDVAL1; /* offset: 0x0110 size: 32 bit */ - /* PIT_RTI_CVAL - Current Timer Value Register */ - PIT_RTI_CVAL_32B_tag CVAL1; /* offset: 0x0114 size: 32 bit */ - /* PIT_RTI_TCTRL - Timer Control Register */ - PIT_RTI_TCTRL_32B_tag TCTRL1; /* offset: 0x0118 size: 32 bit */ - /* PIT_RTI_TFLG - Timer Flag Register */ - PIT_RTI_TFLG_32B_tag TFLG1; /* offset: 0x011C size: 32 bit */ - /* PIT_RTI_LDVAL - Timer Load Value Register */ - PIT_RTI_LDVAL_32B_tag LDVAL2; /* offset: 0x0120 size: 32 bit */ - /* PIT_RTI_CVAL - Current Timer Value Register */ - PIT_RTI_CVAL_32B_tag CVAL2; /* offset: 0x0124 size: 32 bit */ - /* PIT_RTI_TCTRL - Timer Control Register */ - PIT_RTI_TCTRL_32B_tag TCTRL2; /* offset: 0x0128 size: 32 bit */ - /* PIT_RTI_TFLG - Timer Flag Register */ - PIT_RTI_TFLG_32B_tag TFLG2; /* offset: 0x012C size: 32 bit */ - /* PIT_RTI_LDVAL - Timer Load Value Register */ - PIT_RTI_LDVAL_32B_tag LDVAL3; /* offset: 0x0130 size: 32 bit */ - /* PIT_RTI_CVAL - Current Timer Value Register */ - PIT_RTI_CVAL_32B_tag CVAL3; /* offset: 0x0134 size: 32 bit */ - /* PIT_RTI_TCTRL - Timer Control Register */ - PIT_RTI_TCTRL_32B_tag TCTRL3; /* offset: 0x0138 size: 32 bit */ - /* PIT_RTI_TFLG - Timer Flag Register */ - PIT_RTI_TFLG_32B_tag TFLG3; /* offset: 0x013C size: 32 bit */ - }; - - }; - } PIT_RTI_tag; - - -#define PIT_RTI (*(volatile PIT_RTI_tag *) 0xC3FF0000UL) - - - -/****************************************************************/ -/* */ -/* Module: ADC */ -/* */ -/****************************************************************/ - - typedef union { /* module configuration register */ - uint32_t R; - struct { - uint32_t OWREN:1; /* Overwrite enable */ - uint32_t WLSIDE:1; /* Write Left/right Alligned */ - uint32_t MODE:1; /* One Shot/Scan Mode Selectiom */ - uint32_t EDGLEV:1; /* edge or level selection for external start trigger */ - uint32_t TRGEN:1; /* external trigger enable */ - uint32_t EDGE:1; /* start trigger egde /level detection */ - uint32_t XSTRTEN:1; /* EXTERNAL START ENABLE */ - uint32_t NSTART:1; /* start normal conversion */ - uint32_t:1; - uint32_t JTRGEN:1; /* Injectin External Trigger Enable */ - uint32_t JEDGE:1; /* start trigger egde /level detection for injected */ - uint32_t JSTART:1; /* injected conversion start */ - uint32_t:2; - uint32_t CTUEN:1; /* CTU enabaled */ - uint32_t:8; - uint32_t ADCLKSEL:1; /* Select which clock for device */ - uint32_t ABORTCHAIN:1; /* abort chain conversion */ - uint32_t ABORT:1; /* abort current conversion */ -#ifndef USE_FIELD_ALIASES_ADC - uint32_t ACKO:1; /* Auto Clock Off Enable */ -#else - uint32_t ACK0:1; /* deprecated name - please avoid */ -#endif - uint32_t OFFREFRESH:1; /* offset phase selection */ - uint32_t OFFCANC:1; /* offset phase cancellation selection */ - uint32_t:2; - uint32_t PWDN:1; /* Power Down Enable */ - } B; - } ADC_MCR_32B_tag; - - typedef union { /* module status register */ - uint32_t R; - struct { - uint32_t:7; - uint32_t NSTART:1; /* normal conversion status */ - uint32_t JABORT:1; /* Injection chain abort status */ - uint32_t:2; - uint32_t JSTART:1; /* Injection Start status */ - uint32_t:3; - uint32_t CTUSTART:1; /* ctu start status */ - uint32_t CHADDR:7; /* which address conv is goin on */ - uint32_t:3; -#ifndef USE_FIELD_ALIASES_ADC - uint32_t ACKO:1; /* Auto Clock Off Enable status */ -#else - uint32_t ACK0:1; /* deprecated name - please avoid */ -#endif - uint32_t OFFREFRESH:1; /* offset refresh status */ - uint32_t OFFCANC:1; /* offset phase cancellation status */ - uint32_t ADCSTATUS:3; /* status of ADC FSM */ - } B; - } ADC_MSR_32B_tag; - - typedef union { /* Interrupt status register */ - uint32_t R; - struct { - uint32_t:25; - uint32_t OFFCANCOVR:1; /* Offset cancellation phase over */ - uint32_t EOFFSET:1; /* error in offset refresh */ - uint32_t EOCTU:1; /* end of CTU channel conversion */ - uint32_t JEOC:1; /* end of injected channel conversion */ - uint32_t JECH:1; /* end ofinjected chain conversion */ - uint32_t EOC:1; /* end of channel conversion */ - uint32_t ECH:1; /* end of chain conversion */ - } B; - } ADC_ISR_32B_tag; - - typedef union { /* CHANNEL PENDING REGISTER 0 */ - uint32_t R; - struct { -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH31:1; /* Channel 31 conversion over */ -#else - uint32_t EOC31:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH30:1; /* Channel 30 conversion over */ -#else - uint32_t EOC30:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH29:1; /* Channel 29 conversion over */ -#else - uint32_t EOC29:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH28:1; /* Channel 28 conversion over */ -#else - uint32_t EOC28:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH27:1; /* Channel 27 conversion over */ -#else - uint32_t EOC27:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH26:1; /* Channel 26 conversion over */ -#else - uint32_t EOC26:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH25:1; /* Channel 25 conversion over */ -#else - uint32_t EOC25:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH24:1; /* Channel 24 conversion over */ -#else - uint32_t EOC24:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH23:1; /* Channel 23 conversion over */ -#else - uint32_t EOC23:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH22:1; /* Channel 22 conversion over */ -#else - uint32_t EOC22:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH21:1; /* Channel 21 conversion over */ -#else - uint32_t EOC21:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH20:1; /* Channel 20 conversion over */ -#else - uint32_t EOC20:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH19:1; /* Channel 19 conversion over */ -#else - uint32_t EOC19:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH18:1; /* Channel 18 conversion over */ -#else - uint32_t EOC18:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH17:1; /* Channel 17 conversion over */ -#else - uint32_t EOC17:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH16:1; /* Channel 16 conversion over */ -#else - uint32_t EOC16:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH15:1; /* Channel 15 conversion over */ -#else - uint32_t EOC15:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH14:1; /* Channel 14 conversion over */ -#else - uint32_t EOC14:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH13:1; /* Channel 13 conversion over */ -#else - uint32_t EOC13:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH12:1; /* Channel 12 conversion over */ -#else - uint32_t EOC12:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH11:1; /* Channel 11 conversion over */ -#else - uint32_t EOC11:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH10:1; /* Channel 10 conversion over */ -#else - uint32_t EOC10:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH9:1; /* Channel 9 conversion over */ -#else - uint32_t EOC9:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH8:1; /* Channel 8 conversion over */ -#else - uint32_t EOC8:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH7:1; /* Channel 7 conversion over */ -#else - uint32_t EOC7:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH6:1; /* Channel 6 conversion over */ -#else - uint32_t EOC6:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH5:1; /* Channel 5 conversion over */ -#else - uint32_t EOC5:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH4:1; /* Channel 4 conversion over */ -#else - uint32_t EOC4:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH3:1; /* Channel 3 conversion over */ -#else - uint32_t EOC3:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH2:1; /* Channel 2 conversion over */ -#else - uint32_t EOC2:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH1:1; /* Channel 1 conversion over */ -#else - uint32_t EOC1:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_ADC - uint32_t EOC_CH0:1; /* Channel 0 conversion over */ -#else - uint32_t EOC0:1; /* deprecated name - please avoid */ -#endif - } B; - } ADC_CEOCFR0_32B_tag; - - typedef union { /* CHANNEL PENDING REGISTER 1 */ - uint32_t R; - struct { - uint32_t EOC_CH63:1; /* Channel 63 conversion over */ - uint32_t EOC_CH62:1; /* Channel 62 conversion over */ - uint32_t EOC_CH61:1; /* Channel 61 conversion over */ - uint32_t EOC_CH60:1; /* Channel 60 conversion over */ - uint32_t EOC_CH59:1; /* Channel 59 conversion over */ - uint32_t EOC_CH58:1; /* Channel 58 conversion over */ - uint32_t EOC_CH57:1; /* Channel 57 conversion over */ - uint32_t EOC_CH56:1; /* Channel 56 conversion over */ - uint32_t EOC_CH55:1; /* Channel 55 conversion over */ - uint32_t EOC_CH54:1; /* Channel 54 conversion over */ - uint32_t EOC_CH53:1; /* Channel 53 conversion over */ - uint32_t EOC_CH52:1; /* Channel 52 conversion over */ - uint32_t EOC_CH51:1; /* Channel 51 conversion over */ - uint32_t EOC_CH50:1; /* Channel 50 conversion over */ - uint32_t EOC_CH49:1; /* Channel 49 conversion over */ - uint32_t EOC_CH48:1; /* Channel 48 conversion over */ - uint32_t EOC_CH47:1; /* Channel 47 conversion over */ - uint32_t EOC_CH46:1; /* Channel 46 conversion over */ - uint32_t EOC_CH45:1; /* Channel 45 conversion over */ - uint32_t EOC_CH44:1; /* Channel 44 conversion over */ - uint32_t EOC_CH43:1; /* Channel 43 conversion over */ - uint32_t EOC_CH42:1; /* Channel 42 conversion over */ - uint32_t EOC_CH41:1; /* Channel 41 conversion over */ - uint32_t EOC_CH40:1; /* Channel 40 conversion over */ - uint32_t EOC_CH39:1; /* Channel 39 conversion over */ - uint32_t EOC_CH38:1; /* Channel 38 conversion over */ - uint32_t EOC_CH37:1; /* Channel 37 conversion over */ - uint32_t EOC_CH36:1; /* Channel 36 conversion over */ - uint32_t EOC_CH35:1; /* Channel 35 conversion over */ - uint32_t EOC_CH34:1; /* Channel 34 conversion over */ - uint32_t EOC_CH33:1; /* Channel 33 conversion over */ - uint32_t EOC_CH32:1; /* Channel 32 conversion over */ - } B; - } ADC_CEOCFR1_32B_tag; - - typedef union { /* CHANNEL PENDING REGISTER 2 */ - uint32_t R; - struct { - uint32_t EOC_CH95:1; /* Channel 95 conversion over */ - uint32_t EOC_CH94:1; /* Channel 94 conversion over */ - uint32_t EOC_CH93:1; /* Channel 93 conversion over */ - uint32_t EOC_CH92:1; /* Channel 92 conversion over */ - uint32_t EOC_CH91:1; /* Channel 91 conversion over */ - uint32_t EOC_CH90:1; /* Channel 90 conversion over */ - uint32_t EOC_CH89:1; /* Channel 89 conversion over */ - uint32_t EOC_CH88:1; /* Channel 88 conversion over */ - uint32_t EOC_CH87:1; /* Channel 87 conversion over */ - uint32_t EOC_CH86:1; /* Channel 86 conversion over */ - uint32_t EOC_CH85:1; /* Channel 85 conversion over */ - uint32_t EOC_CH84:1; /* Channel 84 conversion over */ - uint32_t EOC_CH83:1; /* Channel 83 conversion over */ - uint32_t EOC_CH82:1; /* Channel 82 conversion over */ - uint32_t EOC_CH81:1; /* Channel 81 conversion over */ - uint32_t EOC_CH80:1; /* Channel 80 conversion over */ - uint32_t EOC_CH79:1; /* Channel 79 conversion over */ - uint32_t EOC_CH78:1; /* Channel 78 conversion over */ - uint32_t EOC_CH77:1; /* Channel 77 conversion over */ - uint32_t EOC_CH76:1; /* Channel 76 conversion over */ - uint32_t EOC_CH75:1; /* Channel 75 conversion over */ - uint32_t EOC_CH74:1; /* Channel 74 conversion over */ - uint32_t EOC_CH73:1; /* Channel 73 conversion over */ - uint32_t EOC_CH72:1; /* Channel 72 conversion over */ - uint32_t EOC_CH71:1; /* Channel 71 conversion over */ - uint32_t EOC_CH70:1; /* Channel 70 conversion over */ - uint32_t EOC_CH69:1; /* Channel 69 conversion over */ - uint32_t EOC_CH68:1; /* Channel 68 conversion over */ - uint32_t EOC_CH67:1; /* Channel 67 conversion over */ - uint32_t EOC_CH66:1; /* Channel 66 conversion over */ - uint32_t EOC_CH65:1; /* Channel 65 conversion over */ - uint32_t EOC_CH64:1; /* Channel 64 conversion over */ - } B; - } ADC_CEOCFR2_32B_tag; - - typedef union { /* interrupt mask register */ - uint32_t R; - struct { - uint32_t:25; - uint32_t MSKOFFCANCOVR:1; /* mask bit for Calibration over */ - uint32_t MSKEOFFSET:1; /* mask bit for Error in offset refresh */ - uint32_t MSKEOCTU:1; /* mask bit for EOCTU */ - uint32_t MSKJEOC:1; /* mask bit for JEOC */ - uint32_t MSKJECH:1; /* mask bit for JECH */ - uint32_t MSKEOC:1; /* mask bit for EOC */ - uint32_t MSKECH:1; /* mask bit for ECH */ - } B; - } ADC_IMR_32B_tag; - - typedef union { /* CHANNEL INTERRUPT MASK REGISTER 0 */ - uint32_t R; - struct { - uint32_t CIM31:1; /* Channel 31 mask register */ - uint32_t CIM30:1; /* Channel 30 mask register */ - uint32_t CIM29:1; /* Channel 29 mask register */ - uint32_t CIM28:1; /* Channel 28 mask register */ - uint32_t CIM27:1; /* Channel 27 mask register */ - uint32_t CIM26:1; /* Channel 26 mask register */ - uint32_t CIM25:1; /* Channel 25 mask register */ - uint32_t CIM24:1; /* Channel 24 mask register */ - uint32_t CIM23:1; /* Channel 23 mask register */ - uint32_t CIM22:1; /* Channel 22 mask register */ - uint32_t CIM21:1; /* Channel 21 mask register */ - uint32_t CIM20:1; /* Channel 20 mask register */ - uint32_t CIM19:1; /* Channel 19 mask register */ - uint32_t CIM18:1; /* Channel 18 mask register */ - uint32_t CIM17:1; /* Channel 17 mask register */ - uint32_t CIM16:1; /* Channel 16 mask register */ - uint32_t CIM15:1; /* Channel 15 mask register */ - uint32_t CIM14:1; /* Channel 14 mask register */ - uint32_t CIM13:1; /* Channel 13 mask register */ - uint32_t CIM12:1; /* Channel 12 mask register */ - uint32_t CIM11:1; /* Channel 11 mask register */ - uint32_t CIM10:1; /* Channel 10 mask register */ - uint32_t CIM9:1; /* Channel 9 mask register */ - uint32_t CIM8:1; /* Channel 8 mask register */ - uint32_t CIM7:1; /* Channel 7 mask register */ - uint32_t CIM6:1; /* Channel 6 mask register */ - uint32_t CIM5:1; /* Channel 5 mask register */ - uint32_t CIM4:1; /* Channel 4 mask register */ - uint32_t CIM3:1; /* Channel 3 mask register */ - uint32_t CIM2:1; /* Channel 2 mask register */ - uint32_t CIM1:1; /* Channel 1 mask register */ - uint32_t CIM0:1; /* Channel 0 mask register */ - } B; - } ADC_CIMR0_32B_tag; - - typedef union { /* CHANNEL INTERRUPT MASK REGISTER 1 */ - uint32_t R; - struct { - uint32_t CIM63:1; /* Channel 63 mask register */ - uint32_t CIM62:1; /* Channel 62 mask register */ - uint32_t CIM61:1; /* Channel 61 mask register */ - uint32_t CIM60:1; /* Channel 60 mask register */ - uint32_t CIM59:1; /* Channel 59 mask register */ - uint32_t CIM58:1; /* Channel 58 mask register */ - uint32_t CIM57:1; /* Channel 57 mask register */ - uint32_t CIM56:1; /* Channel 56 mask register */ - uint32_t CIM55:1; /* Channel 55 mask register */ - uint32_t CIM54:1; /* Channel 54 mask register */ - uint32_t CIM53:1; /* Channel 53 mask register */ - uint32_t CIM52:1; /* Channel 52 mask register */ - uint32_t CIM51:1; /* Channel 51 mask register */ - uint32_t CIM50:1; /* Channel 50 mask register */ - uint32_t CIM49:1; /* Channel 49 mask register */ - uint32_t CIM48:1; /* Channel 48 mask register */ - uint32_t CIM47:1; /* Channel 47 mask register */ - uint32_t CIM46:1; /* Channel 46 mask register */ - uint32_t CIM45:1; /* Channel 45 mask register */ - uint32_t CIM44:1; /* Channel 44 mask register */ - uint32_t CIM43:1; /* Channel 43 mask register */ - uint32_t CIM42:1; /* Channel 42 mask register */ - uint32_t CIM41:1; /* Channel 41 mask register */ - uint32_t CIM40:1; /* Channel 40 mask register */ - uint32_t CIM39:1; /* Channel 39 mask register */ - uint32_t CIM38:1; /* Channel 38 mask register */ - uint32_t CIM37:1; /* Channel 37 mask register */ - uint32_t CIM36:1; /* Channel 36 mask register */ - uint32_t CIM35:1; /* Channel 35 mask register */ - uint32_t CIM34:1; /* Channel 34 mask register */ - uint32_t CIM33:1; /* Channel 33 mask register */ - uint32_t CIM32:1; /* Channel 32 mask register */ - } B; - } ADC_CIMR1_32B_tag; - - typedef union { /* CHANNEL INTERRUPT MASK REGISTER 2 */ - uint32_t R; - struct { - uint32_t CIM95:1; /* Channel 95 mask register */ - uint32_t CIM94:1; /* Channel 94 mask register */ - uint32_t CIM93:1; /* Channel 93 mask register */ - uint32_t CIM92:1; /* Channel 92 mask register */ - uint32_t CIM91:1; /* Channel 91 mask register */ - uint32_t CIM90:1; /* Channel 90 mask register */ - uint32_t CIM89:1; /* Channel 89 mask register */ - uint32_t CIM88:1; /* Channel 88 mask register */ - uint32_t CIM87:1; /* Channel 87 mask register */ - uint32_t CIM86:1; /* Channel 86 mask register */ - uint32_t CIM85:1; /* Channel 85 mask register */ - uint32_t CIM84:1; /* Channel 84 mask register */ - uint32_t CIM83:1; /* Channel 83 mask register */ - uint32_t CIM82:1; /* Channel 82 mask register */ - uint32_t CIM81:1; /* Channel 81 mask register */ - uint32_t CIM80:1; /* Channel 80 mask register */ - uint32_t CIM79:1; /* Channel 79 mask register */ - uint32_t CIM78:1; /* Channel 78 mask register */ - uint32_t CIM77:1; /* Channel 77 mask register */ - uint32_t CIM76:1; /* Channel 76 mask register */ - uint32_t CIM75:1; /* Channel 75 mask register */ - uint32_t CIM74:1; /* Channel 74 mask register */ - uint32_t CIM73:1; /* Channel 73 mask register */ - uint32_t CIM72:1; /* Channel 72 mask register */ - uint32_t CIM71:1; /* Channel 71 mask register */ - uint32_t CIM70:1; /* Channel 70 mask register */ - uint32_t CIM69:1; /* Channel 69 mask register */ - uint32_t CIM68:1; /* Channel 68 mask register */ - uint32_t CIM67:1; /* Channel 67 mask register */ - uint32_t CIM66:1; /* Channel 66 mask register */ - uint32_t CIM65:1; /* Channel 65 mask register */ - uint32_t CIM64:1; /* Channel 64 mask register */ - } B; - } ADC_CIMR2_32B_tag; - - typedef union { /* Watchdog Threshold interrupt status register */ - uint32_t R; - struct { - uint32_t:24; - uint32_t WDG3H:1; /* Interrupt generated on the value being higher than the HTHV 3 */ - uint32_t WDG2H:1; /* Interrupt generated on the value being higher than the HTHV 2 */ - uint32_t WDG1H:1; /* Interrupt generated on the value being higher than the HTHV 1 */ - uint32_t WDG0H:1; /* Interrupt generated on the value being higher than the HTHV 0 */ - uint32_t WDG3L:1; /* Interrupt generated on the value being lower than the LTHV 3 */ - uint32_t WDG2L:1; /* Interrupt generated on the value being lower than the LTHV 2 */ - uint32_t WDG1L:1; /* Interrupt generated on the value being lower than the LTHV 1 */ - uint32_t WDG0L:1; /* Interrupt generated on the value being lower than the LTHV 0 */ - } B; - } ADC_WTISR_32B_tag; - - typedef union { /* Watchdog interrupt MASK register */ - uint32_t R; - struct { - uint32_t:24; - uint32_t MSKWDG3H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 3 */ - uint32_t MSKWDG2H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 2 */ - uint32_t MSKWDG1H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 1 */ - uint32_t MSKWDG0H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 0 */ - uint32_t MSKWDG3L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 3 */ - uint32_t MSKWDG2L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 2 */ - uint32_t MSKWDG1L:1; /* MAsk enable for Interrupt generated on the value being lower than the LTHV 1 */ - uint32_t MSKWDG0L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 0 */ - } B; - } ADC_WTIMR_32B_tag; - - typedef union { /* DMAE register */ - uint32_t R; - struct { - uint32_t:30; - uint32_t DCLR:1; /* DMA clear sequence enable */ - uint32_t DMAEN:1; /* DMA global enable */ - } B; - } ADC_DMAE_32B_tag; - - typedef union { /* DMA REGISTER 0 */ - uint32_t R; - struct { - uint32_t DMA31:1; /* Channel 31 DMA Enable */ - uint32_t DMA30:1; /* Channel 30 DMA Enable */ - uint32_t DMA29:1; /* Channel 29 DMA Enable */ - uint32_t DMA28:1; /* Channel 28 DMA Enable */ - uint32_t DMA27:1; /* Channel 27 DMA Enable */ - uint32_t DMA26:1; /* Channel 26 DMA Enable */ - uint32_t DMA25:1; /* Channel 25 DMA Enable */ - uint32_t DMA24:1; /* Channel 24 DMA Enable */ - uint32_t DMA23:1; /* Channel 23 DMA Enable */ - uint32_t DMA22:1; /* Channel 22 DMA Enable */ - uint32_t DMA21:1; /* Channel 21 DMA Enable */ - uint32_t DMA20:1; /* Channel 20 DMA Enable */ - uint32_t DMA19:1; /* Channel 19 DMA Enable */ - uint32_t DMA18:1; /* Channel 18 DMA Enable */ - uint32_t DMA17:1; /* Channel 17 DMA Enable */ - uint32_t DMA16:1; /* Channel 16 DMA Enable */ - uint32_t DMA15:1; /* Channel 15 DMA Enable */ - uint32_t DMA14:1; /* Channel 14 DMA Enable */ - uint32_t DMA13:1; /* Channel 13 DMA Enable */ - uint32_t DMA12:1; /* Channel 12 DMA Enable */ - uint32_t DMA11:1; /* Channel 11 DMA Enable */ - uint32_t DMA10:1; /* Channel 10 DMA Enable */ - uint32_t DMA9:1; /* Channel 9 DMA Enable */ - uint32_t DMA8:1; /* Channel 8 DMA Enable */ - uint32_t DMA7:1; /* Channel 7 DMA Enable */ - uint32_t DMA6:1; /* Channel 6 DMA Enable */ - uint32_t DMA5:1; /* Channel 5 DMA Enable */ - uint32_t DMA4:1; /* Channel 4 DMA Enable */ - uint32_t DMA3:1; /* Channel 3 DMA Enable */ - uint32_t DMA2:1; /* Channel 2 DMA Enable */ - uint32_t DMA1:1; /* Channel 1 DMA Enable */ - uint32_t DMA0:1; /* Channel 0 DMA Enable */ - } B; - } ADC_DMAR0_32B_tag; - - typedef union { /* DMA REGISTER 1 */ - uint32_t R; - struct { - uint32_t DMA63:1; /* Channel 63 DMA Enable */ - uint32_t DMA62:1; /* Channel 62 DMA Enable */ - uint32_t DMA61:1; /* Channel 61 DMA Enable */ - uint32_t DMA60:1; /* Channel 60 DMA Enable */ - uint32_t DMA59:1; /* Channel 59 DMA Enable */ - uint32_t DMA58:1; /* Channel 58 DMA Enable */ - uint32_t DMA57:1; /* Channel 57 DMA Enable */ - uint32_t DMA56:1; /* Channel 56 DMA Enable */ - uint32_t DMA55:1; /* Channel 55 DMA Enable */ - uint32_t DMA54:1; /* Channel 54 DMA Enable */ - uint32_t DMA53:1; /* Channel 53 DMA Enable */ - uint32_t DMA52:1; /* Channel 52 DMA Enable */ - uint32_t DMA51:1; /* Channel 51 DMA Enable */ - uint32_t DMA50:1; /* Channel 50 DMA Enable */ - uint32_t DMA49:1; /* Channel 49 DMA Enable */ - uint32_t DMA48:1; /* Channel 48 DMA Enable */ - uint32_t DMA47:1; /* Channel 47 DMA Enable */ - uint32_t DMA46:1; /* Channel 46 DMA Enable */ - uint32_t DMA45:1; /* Channel 45 DMA Enable */ - uint32_t DMA44:1; /* Channel 44 DMA Enable */ - uint32_t DMA43:1; /* Channel 43 DMA Enable */ - uint32_t DMA42:1; /* Channel 42 DMA Enable */ - uint32_t DMA41:1; /* Channel 41 DMA Enable */ - uint32_t DMA40:1; /* Channel 40 DMA Enable */ - uint32_t DMA39:1; /* Channel 39 DMA Enable */ - uint32_t DMA38:1; /* Channel 38 DMA Enable */ - uint32_t DMA37:1; /* Channel 37 DMA Enable */ - uint32_t DMA36:1; /* Channel 36 DMA Enable */ - uint32_t DMA35:1; /* Channel 35 DMA Enable */ - uint32_t DMA34:1; /* Channel 34 DMA Enable */ - uint32_t DMA33:1; /* Channel 33 DMA Enable */ - uint32_t DMA32:1; /* Channel 32 DMA Enable */ - } B; - } ADC_DMAR1_32B_tag; - - typedef union { /* DMA REGISTER 2 */ - uint32_t R; - struct { - uint32_t DMA95:1; /* Channel 95 DMA Enable */ - uint32_t DMA94:1; /* Channel 94 DMA Enable */ - uint32_t DMA93:1; /* Channel 93 DMA Enable */ - uint32_t DMA92:1; /* Channel 92 DMA Enable */ - uint32_t DMA91:1; /* Channel 91 DMA Enable */ - uint32_t DMA90:1; /* Channel 90 DMA Enable */ - uint32_t DMA89:1; /* Channel 89 DMA Enable */ - uint32_t DMA88:1; /* Channel 88 DMA Enable */ - uint32_t DMA87:1; /* Channel 87 DMA Enable */ - uint32_t DMA86:1; /* Channel 86 DMA Enable */ - uint32_t DMA85:1; /* Channel 85 DMA Enable */ - uint32_t DMA84:1; /* Channel 84 DMA Enable */ - uint32_t DMA83:1; /* Channel 83 DMA Enable */ - uint32_t DMA82:1; /* Channel 82 DMA Enable */ - uint32_t DMA81:1; /* Channel 81 DMA Enable */ - uint32_t DMA80:1; /* Channel 80 DMA Enable */ - uint32_t DMA79:1; /* Channel 79 DMA Enable */ - uint32_t DMA78:1; /* Channel 78 DMA Enable */ - uint32_t DMA77:1; /* Channel 77 DMA Enable */ - uint32_t DMA76:1; /* Channel 76 DMA Enable */ - uint32_t DMA75:1; /* Channel 75 DMA Enable */ - uint32_t DMA74:1; /* Channel 74 DMA Enable */ - uint32_t DMA73:1; /* Channel 73 DMA Enable */ - uint32_t DMA72:1; /* Channel 72 DMA Enable */ - uint32_t DMA71:1; /* Channel 71 DMA Enable */ - uint32_t DMA70:1; /* Channel 70 DMA Enable */ - uint32_t DMA69:1; /* Channel 69 DMA Enable */ - uint32_t DMA68:1; /* Channel 68 DMA Enable */ - uint32_t DMA67:1; /* Channel 67 DMA Enable */ - uint32_t DMA66:1; /* Channel 66 DMA Enable */ - uint32_t DMA65:1; /* Channel 65 DMA Enable */ - uint32_t DMA64:1; /* Channel 64 DMA Enable */ - } B; - } ADC_DMAR2_32B_tag; - - - /* Register layout for all registers TRC... */ - - typedef union { /* Threshold Control register C */ - uint32_t R; - struct { - uint32_t:16; - uint32_t THREN:1; /* Threshold enable */ - uint32_t THRINV:1; /* invert the output pin */ - uint32_t THROP:1; /* output pin register */ - uint32_t:6; - uint32_t THRCH:7; /* Choose channel for threshold register */ - } B; - } ADC_TRC_32B_tag; - - - /* Register layout for all registers THRHLR... */ - - typedef union { /* Upper Threshold register */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* high threshold value s */ - uint32_t:4; - uint32_t THRL:12; /* low threshold value s */ - } B; - } ADC_THRHLR_32B_tag; - - - /* Register layout for all registers THRALT... */ - - typedef union { /* alternate Upper Threshold register */ - uint32_t R; - struct { - uint32_t:6; - uint32_t THRH:10; /* high threshold value s */ - uint32_t:6; - uint32_t THRL:10; /* low threshold value s */ - } B; - } ADC_THRALT_32B_tag; - - typedef union { /* PRESAMPLING CONTROL REGISTER */ - uint32_t R; - struct { - uint32_t:25; - uint32_t PREVAL2:2; /* INternal Voltage selection for Presampling */ - uint32_t PREVAL1:2; /* INternal Voltage selection for Presampling */ - uint32_t PREVAL0:2; /* INternal Voltage selection for Presampling */ -#ifndef USE_FIELD_ALIASES_ADC - uint32_t PRECONV:1; /* Presampled value */ -#else - uint32_t PREONCE:1; /* deprecated name - please avoid */ -#endif - } B; - } ADC_PSCR_32B_tag; - - typedef union { /* Presampling Register 0 */ - uint32_t R; - struct { - uint32_t PRES31:1; /* Channel 31 Presampling Enable */ - uint32_t PRES30:1; /* Channel 30 Presampling Enable */ - uint32_t PRES29:1; /* Channel 29 Presampling Enable */ - uint32_t PRES28:1; /* Channel 28 Presampling Enable */ - uint32_t PRES27:1; /* Channel 27 Presampling Enable */ - uint32_t PRES26:1; /* Channel 26 Presampling Enable */ - uint32_t PRES25:1; /* Channel 25 Presampling Enable */ - uint32_t PRES24:1; /* Channel 24 Presampling Enable */ - uint32_t PRES23:1; /* Channel 23 Presampling Enable */ - uint32_t PRES22:1; /* Channel 22 Presampling Enable */ - uint32_t PRES21:1; /* Channel 21 Presampling Enable */ - uint32_t PRES20:1; /* Channel 20 Presampling Enable */ - uint32_t PRES19:1; /* Channel 19 Presampling Enable */ - uint32_t PRES18:1; /* Channel 18 Presampling Enable */ - uint32_t PRES17:1; /* Channel 17 Presampling Enable */ - uint32_t PRES16:1; /* Channel 16 Presampling Enable */ - uint32_t PRES15:1; /* Channel 15 Presampling Enable */ - uint32_t PRES14:1; /* Channel 14 Presampling Enable */ - uint32_t PRES13:1; /* Channel 13 Presampling Enable */ - uint32_t PRES12:1; /* Channel 12 Presampling Enable */ - uint32_t PRES11:1; /* Channel 11 Presampling Enable */ - uint32_t PRES10:1; /* Channel 10 Presampling Enable */ - uint32_t PRES9:1; /* Channel 9 Presampling Enable */ - uint32_t PRES8:1; /* Channel 8 Presampling Enable */ - uint32_t PRES7:1; /* Channel 7 Presampling Enable */ - uint32_t PRES6:1; /* Channel 6 Presampling Enable */ - uint32_t PRES5:1; /* Channel 5 Presampling Enable */ - uint32_t PRES4:1; /* Channel 4 Presampling Enable */ - uint32_t PRES3:1; /* Channel 3 Presampling Enable */ - uint32_t PRES2:1; /* Channel 2 Presampling Enable */ - uint32_t PRES1:1; /* Channel 1presampling Enable */ - uint32_t PRES0:1; /* Channel 0 Presampling Enable */ - } B; - } ADC_PSR0_32B_tag; - - typedef union { /* Presampling REGISTER 1 */ - uint32_t R; - struct { - uint32_t PRES63:1; /* Channel 63 Presampling Enable */ - uint32_t PRES62:1; /* Channel 62 Presampling Enable */ - uint32_t PRES61:1; /* Channel 61 Presampling Enable */ - uint32_t PRES60:1; /* Channel 60 Presampling Enable */ - uint32_t PRES59:1; /* Channel 59 Presampling Enable */ - uint32_t PRES58:1; /* Channel 58 Presampling Enable */ - uint32_t PRES57:1; /* Channel 57 Presampling Enable */ - uint32_t PRES56:1; /* Channel 56 Presampling Enable */ - uint32_t PRES55:1; /* Channel 55 Presampling Enable */ - uint32_t PRES54:1; /* Channel 54 Presampling Enable */ - uint32_t PRES53:1; /* Channel 53 Presampling Enable */ - uint32_t PRES52:1; /* Channel 52 Presampling Enable */ - uint32_t PRES51:1; /* Channel 51 Presampling Enable */ - uint32_t PRES50:1; /* Channel 50 Presampling Enable */ - uint32_t PRES49:1; /* Channel 49 Presampling Enable */ - uint32_t PRES48:1; /* Channel 48 Presampling Enable */ - uint32_t PRES47:1; /* Channel 47 Presampling Enable */ - uint32_t PRES46:1; /* Channel 46 Presampling Enable */ - uint32_t PRES45:1; /* Channel 45 Presampling Enable */ - uint32_t PRES44:1; /* Channel 44 Presampling Enable */ - uint32_t PRES43:1; /* Channel 43 Presampling Enable */ - uint32_t PRES42:1; /* Channel 42 Presampling Enable */ - uint32_t PRES41:1; /* Channel 41 Presampling Enable */ - uint32_t PRES40:1; /* Channel 40 Presampling Enable */ - uint32_t PRES39:1; /* Channel 39 Presampling Enable */ - uint32_t PRES38:1; /* Channel 38 Presampling Enable */ - uint32_t PRES37:1; /* Channel 37 Presampling Enable */ - uint32_t PRES36:1; /* Channel 36 Presampling Enable */ - uint32_t PRES35:1; /* Channel 35 Presampling Enable */ - uint32_t PRES34:1; /* Channel 34 Presampling Enable */ - uint32_t PRES33:1; /* Channel 33 Presampling Enable */ - uint32_t PRES32:1; /* Channel 32 Presampling Enable */ - } B; - } ADC_PSR1_32B_tag; - - typedef union { /* Presampling REGISTER 2 */ - uint32_t R; - struct { - uint32_t PRES95:1; /* Channel 95 Presampling Enable */ - uint32_t PRES94:1; /* Channel 94 Presampling Enable */ - uint32_t PRES93:1; /* Channel 93 Presampling Enable */ - uint32_t PRES92:1; /* Channel 92 Presampling Enable */ - uint32_t PRES91:1; /* Channel 91 Presampling Enable */ - uint32_t PRES90:1; /* Channel 90 Presampling Enable */ - uint32_t PRES89:1; /* Channel 89 Presampling Enable */ - uint32_t PRES88:1; /* Channel 88 Presampling Enable */ - uint32_t PRES87:1; /* Channel 87 Presampling Enable */ - uint32_t PRES86:1; /* Channel 86 Presampling Enable */ - uint32_t PRES85:1; /* Channel 85 Presampling Enable */ - uint32_t PRES84:1; /* Channel 84 Presampling Enable */ - uint32_t PRES83:1; /* Channel 83 Presampling Enable */ - uint32_t PRES82:1; /* Channel 82 Presampling Enable */ - uint32_t PRES81:1; /* Channel 81 Presampling Enable */ - uint32_t PRES80:1; /* Channel 80 Presampling Enable */ - uint32_t PRES79:1; /* Channel 79 Presampling Enable */ - uint32_t PRES78:1; /* Channel 78 Presampling Enable */ - uint32_t PRES77:1; /* Channel 77 Presampling Enable */ - uint32_t PRES76:1; /* Channel 76 Presampling Enable */ - uint32_t PRES75:1; /* Channel 75 Presampling Enable */ - uint32_t PRES74:1; /* Channel 74 Presampling Enable */ - uint32_t PRES73:1; /* Channel 73 Presampling Enable */ - uint32_t PRES72:1; /* Channel 72 Presampling Enable */ - uint32_t PRES71:1; /* Channel 71 Presampling Enable */ - uint32_t PRES70:1; /* Channel 70 Presampling Enable */ - uint32_t PRES69:1; /* Channel 69 Presampling Enable */ - uint32_t PRES68:1; /* Channel 68 Presampling Enable */ - uint32_t PRES67:1; /* Channel 67 Presampling Enable */ - uint32_t PRES66:1; /* Channel 66 Presampling Enable */ - uint32_t PRES65:1; /* Channel 65 Presampling Enable */ - uint32_t PRES64:1; /* Channel 64 Presampling Enable */ - } B; - } ADC_PSR2_32B_tag; - - - /* Register layout for all registers CTR... */ - - typedef union { /* conversion timing register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t INPLATCH:1; /* configuration bits for the LATCHING PHASE duration */ - uint32_t:1; - uint32_t OFFSHIFT:2; /* configuration for offset shift characteristics */ - uint32_t:1; - uint32_t INPCMP:2; /* configuration bits for the COMPARISON duration */ - uint32_t:1; -#ifndef USE_FIELD_ALIASES_ADC - uint32_t INSAMP:8; /* configuration bits for the SAMPLING PHASE duration */ -#else - uint32_t INPSAMP:8; -#endif - } B; - } ADC_CTR_32B_tag; - - typedef union { /* NORMAL CONVERSION MASK REGISTER 0 */ - uint32_t R; - struct { - uint32_t CH31:1; /* Channel 31 Normal Sampling Enable */ - uint32_t CH30:1; /* Channel 30 Normal Sampling Enable */ - uint32_t CH29:1; /* Channel 29 Normal Sampling Enable */ - uint32_t CH28:1; /* Channel 28 Normal Sampling Enable */ - uint32_t CH27:1; /* Channel 27 Normal Sampling Enable */ - uint32_t CH26:1; /* Channel 26 Normal Sampling Enable */ - uint32_t CH25:1; /* Channel 25 Normal Sampling Enable */ - uint32_t CH24:1; /* Channel 24 Normal Sampling Enable */ - uint32_t CH23:1; /* Channel 23 Normal Sampling Enable */ - uint32_t CH22:1; /* Channel 22 Normal Sampling Enable */ - uint32_t CH21:1; /* Channel 21 Normal Sampling Enable */ - uint32_t CH20:1; /* Channel 20 Normal Sampling Enable */ - uint32_t CH19:1; /* Channel 19 Normal Sampling Enable */ - uint32_t CH18:1; /* Channel 18 Normal Sampling Enable */ - uint32_t CH17:1; /* Channel 17 Normal Sampling Enable */ - uint32_t CH16:1; /* Channel 16 Normal Sampling Enable */ - uint32_t CH15:1; /* Channel 15 Normal Sampling Enable */ - uint32_t CH14:1; /* Channel 14 Normal Sampling Enable */ - uint32_t CH13:1; /* Channel 13 Normal Sampling Enable */ - uint32_t CH12:1; /* Channel 12 Normal Sampling Enable */ - uint32_t CH11:1; /* Channel 11 Normal Sampling Enable */ - uint32_t CH10:1; /* Channel 10 Normal Sampling Enable */ - uint32_t CH9:1; /* Channel 9 Normal Sampling Enable */ - uint32_t CH8:1; /* Channel 8 Normal Sampling Enable */ - uint32_t CH7:1; /* Channel 7 Normal Sampling Enable */ - uint32_t CH6:1; /* Channel 6 Normal Sampling Enable */ - uint32_t CH5:1; /* Channel 5 Normal Sampling Enable */ - uint32_t CH4:1; /* Channel 4 Normal Sampling Enable */ - uint32_t CH3:1; /* Channel 3 Normal Sampling Enable */ - uint32_t CH2:1; /* Channel 2 Normal Sampling Enable */ - uint32_t CH1:1; /* Channel 1 Normal Sampling Enable */ - uint32_t CH0:1; /* Channel 0 Normal Sampling Enable */ - } B; - } ADC_NCMR0_32B_tag; - - typedef union { /* NORMAL CONVERSION MASK REGISTER 1 */ - uint32_t R; - struct { - uint32_t CH63:1; /* Channel 63 Normal Sampling Enable */ - uint32_t CH62:1; /* Channel 62 Normal Sampling Enable */ - uint32_t CH61:1; /* Channel 61 Normal Sampling Enable */ - uint32_t CH60:1; /* Channel 60 Normal Sampling Enable */ - uint32_t CH59:1; /* Channel 59 Normal Sampling Enable */ - uint32_t CH58:1; /* Channel 58 Normal Sampling Enable */ - uint32_t CH57:1; /* Channel 57 Normal Sampling Enable */ - uint32_t CH56:1; /* Channel 56 Normal Sampling Enable */ - uint32_t CH55:1; /* Channel 55 Normal Sampling Enable */ - uint32_t CH54:1; /* Channel 54 Normal Sampling Enable */ - uint32_t CH53:1; /* Channel 53 Normal Sampling Enable */ - uint32_t CH52:1; /* Channel 52 Normal Sampling Enable */ - uint32_t CH51:1; /* Channel 51 Normal Sampling Enable */ - uint32_t CH50:1; /* Channel 50 Normal Sampling Enable */ - uint32_t CH49:1; /* Channel 49 Normal Sampling Enable */ - uint32_t CH48:1; /* Channel 48 Normal Sampling Enable */ - uint32_t CH47:1; /* Channel 47 Normal Sampling Enable */ - uint32_t CH46:1; /* Channel 46 Normal Sampling Enable */ - uint32_t CH45:1; /* Channel 45 Normal Sampling Enable */ - uint32_t CH44:1; /* Channel 44 Normal Sampling Enable */ - uint32_t CH43:1; /* Channel 43 Normal Sampling Enable */ - uint32_t CH42:1; /* Channel 42 Normal Sampling Enable */ - uint32_t CH41:1; /* Channel 41 Normal Sampling Enable */ - uint32_t CH40:1; /* Channel 40 Normal Sampling Enable */ - uint32_t CH39:1; /* Channel 39 Normal Sampling Enable */ - uint32_t CH38:1; /* Channel 38 Normal Sampling Enable */ - uint32_t CH37:1; /* Channel 37 Normal Sampling Enable */ - uint32_t CH36:1; /* Channel 36 Normal Sampling Enable */ - uint32_t CH35:1; /* Channel 35 Normal Sampling Enable */ - uint32_t CH34:1; /* Channel 34 Normal Sampling Enable */ - uint32_t CH33:1; /* Channel 33 Normal Sampling Enable */ - uint32_t CH32:1; /* Channel 32 Normal Sampling Enable */ - } B; - } ADC_NCMR1_32B_tag; - - typedef union { /* NORMAL CONVERSION MASK REGISTER 2 */ - uint32_t R; - struct { - uint32_t CH95:1; /* Channel 95 Normal Sampling Enable */ - uint32_t CH94:1; /* Channel 94 Normal Sampling Enable */ - uint32_t CH93:1; /* Channel 93 Normal Sampling Enable */ - uint32_t CH92:1; /* Channel 92 Normal Sampling Enable */ - uint32_t CH91:1; /* Channel 91 Normal Sampling Enable */ - uint32_t CH90:1; /* Channel 90 Normal Sampling Enable */ - uint32_t CH89:1; /* Channel 89 Normal Sampling Enable */ - uint32_t CH88:1; /* Channel 88 Normal Sampling Enable */ - uint32_t CH87:1; /* Channel 87 Normal Sampling Enable */ - uint32_t CH86:1; /* Channel 86 Normal Sampling Enable */ - uint32_t CH85:1; /* Channel 85 Normal Sampling Enable */ - uint32_t CH84:1; /* Channel 84 Normal Sampling Enable */ - uint32_t CH83:1; /* Channel 83 Normal Sampling Enable */ - uint32_t CH82:1; /* Channel 82 Normal Sampling Enable */ - uint32_t CH81:1; /* Channel 81 Normal Sampling Enable */ - uint32_t CH80:1; /* Channel 80 Normal Sampling Enable */ - uint32_t CH79:1; /* Channel 79 Normal Sampling Enable */ - uint32_t CH78:1; /* Channel 78 Normal Sampling Enable */ - uint32_t CH77:1; /* Channel 77 Normal Sampling Enable */ - uint32_t CH76:1; /* Channel 76 Normal Sampling Enable */ - uint32_t CH75:1; /* Channel 75 Normal Sampling Enable */ - uint32_t CH74:1; /* Channel 74 Normal Sampling Enable */ - uint32_t CH73:1; /* Channel 73 Normal Sampling Enable */ - uint32_t CH72:1; /* Channel 72 Normal Sampling Enable */ - uint32_t CH71:1; /* Channel 71 Normal Sampling Enable */ - uint32_t CH70:1; /* Channel 70 Normal Sampling Enable */ - uint32_t CH69:1; /* Channel 69 Normal Sampling Enable */ - uint32_t CH68:1; /* Channel 68 Normal Sampling Enable */ - uint32_t CH67:1; /* Channel 67 Normal Sampling Enable */ - uint32_t CH66:1; /* Channel 66 Normal Sampling Enable */ - uint32_t CH65:1; /* Channel 65 Normal Sampling Enable */ - uint32_t CH64:1; /* Channel 64 Normal Sampling Enable */ - } B; - } ADC_NCMR2_32B_tag; - - typedef union { /* Injected Conversion Mask Register 0 */ - uint32_t R; - struct { - uint32_t CH31:1; /* Channel 31 Injected Sampling Enable */ - uint32_t CH30:1; /* Channel 30 Injected Sampling Enable */ - uint32_t CH29:1; /* Channel 29 Injected Sampling Enable */ - uint32_t CH28:1; /* Channel 28 Injected Sampling Enable */ - uint32_t CH27:1; /* Channel 27 Injected Sampling Enable */ - uint32_t CH26:1; /* Channel 26 Injected Sampling Enable */ - uint32_t CH25:1; /* Channel 25 Injected Sampling Enable */ - uint32_t CH24:1; /* Channel 24 Injected Sampling Enable */ - uint32_t CH23:1; /* Channel 23 Injected Sampling Enable */ - uint32_t CH22:1; /* Channel 22 Injected Sampling Enable */ - uint32_t CH21:1; /* Channel 21 Injected Sampling Enable */ - uint32_t CH20:1; /* Channel 20 Injected Sampling Enable */ - uint32_t CH19:1; /* Channel 19 Injected Sampling Enable */ - uint32_t CH18:1; /* Channel 18 Injected Sampling Enable */ - uint32_t CH17:1; /* Channel 17 Injected Sampling Enable */ - uint32_t CH16:1; /* Channel 16 Injected Sampling Enable */ - uint32_t CH15:1; /* Channel 15 Injected Sampling Enable */ - uint32_t CH14:1; /* Channel 14 Injected Sampling Enable */ - uint32_t CH13:1; /* Channel 13 Injected Sampling Enable */ - uint32_t CH12:1; /* Channel 12 Injected Sampling Enable */ - uint32_t CH11:1; /* Channel 11 Injected Sampling Enable */ - uint32_t CH10:1; /* Channel 10 Injected Sampling Enable */ - uint32_t CH9:1; /* Channel 9 Injected Sampling Enable */ - uint32_t CH8:1; /* Channel 8 Injected Sampling Enable */ - uint32_t CH7:1; /* Channel 7 Injected Sampling Enable */ - uint32_t CH6:1; /* Channel 6 Injected Sampling Enable */ - uint32_t CH5:1; /* Channel 5 Injected Sampling Enable */ - uint32_t CH4:1; /* Channel 4 Injected Sampling Enable */ - uint32_t CH3:1; /* Channel 3 Injected Sampling Enable */ - uint32_t CH2:1; /* Channel 2 Injected Sampling Enable */ - uint32_t CH1:1; /* Channel 1 injected Sampling Enable */ - uint32_t CH0:1; /* Channel 0 injected Sampling Enable */ - } B; - } ADC_JCMR0_32B_tag; - - typedef union { /* INJECTED CONVERSION MASK REGISTER 1 */ - uint32_t R; - struct { - uint32_t CH63:1; /* Channel 63 Injected Sampling Enable */ - uint32_t CH62:1; /* Channel 62 Injected Sampling Enable */ - uint32_t CH61:1; /* Channel 61 Injected Sampling Enable */ - uint32_t CH60:1; /* Channel 60 Injected Sampling Enable */ - uint32_t CH59:1; /* Channel 59 Injected Sampling Enable */ - uint32_t CH58:1; /* Channel 58 Injected Sampling Enable */ - uint32_t CH57:1; /* Channel 57 Injected Sampling Enable */ - uint32_t CH56:1; /* Channel 56 Injected Sampling Enable */ - uint32_t CH55:1; /* Channel 55 Injected Sampling Enable */ - uint32_t CH54:1; /* Channel 54 Injected Sampling Enable */ - uint32_t CH53:1; /* Channel 53 Injected Sampling Enable */ - uint32_t CH52:1; /* Channel 52 Injected Sampling Enable */ - uint32_t CH51:1; /* Channel 51 Injected Sampling Enable */ - uint32_t CH50:1; /* Channel 50 Injected Sampling Enable */ - uint32_t CH49:1; /* Channel 49 Injected Sampling Enable */ - uint32_t CH48:1; /* Channel 48 Injected Sampling Enable */ - uint32_t CH47:1; /* Channel 47 Injected Sampling Enable */ - uint32_t CH46:1; /* Channel 46 Injected Sampling Enable */ - uint32_t CH45:1; /* Channel 45 Injected Sampling Enable */ - uint32_t CH44:1; /* Channel 44 Injected Sampling Enable */ - uint32_t CH43:1; /* Channel 43 Injected Sampling Enable */ - uint32_t CH42:1; /* Channel 42 Injected Sampling Enable */ - uint32_t CH41:1; /* Channel 41 Injected Sampling Enable */ - uint32_t CH40:1; /* Channel 40 Injected Sampling Enable */ - uint32_t CH39:1; /* Channel 39 Injected Sampling Enable */ - uint32_t CH38:1; /* Channel 38 Injected Sampling Enable */ - uint32_t CH37:1; /* Channel 37 Injected Sampling Enable */ - uint32_t CH36:1; /* Channel 36 Injected Sampling Enable */ - uint32_t CH35:1; /* Channel 35 Injected Sampling Enable */ - uint32_t CH34:1; /* Channel 34 Injected Sampling Enable */ - uint32_t CH33:1; /* Channel 33 Injected Sampling Enable */ - uint32_t CH32:1; /* Channel 32 Injected Sampling Enable */ - } B; - } ADC_JCMR1_32B_tag; - - typedef union { /* INJECTED CONVERSION MASK REGISTER 2 */ - uint32_t R; - struct { - uint32_t CH95:1; /* Channel 95 Injected Sampling Enable */ - uint32_t CH94:1; /* Channel 94 Injected Sampling Enable */ - uint32_t CH93:1; /* Channel 93 Injected Sampling Enable */ - uint32_t CH92:1; /* Channel 92 Injected Sampling Enable */ - uint32_t CH91:1; /* Channel 91 Injected Sampling Enable */ - uint32_t CH90:1; /* Channel 90 Injected Sampling Enable */ - uint32_t CH89:1; /* Channel 89 Injected Sampling Enable */ - uint32_t CH88:1; /* Channel 88 Injected Sampling Enable */ - uint32_t CH87:1; /* Channel 87 Injected Sampling Enable */ - uint32_t CH86:1; /* Channel 86 Injected Sampling Enable */ - uint32_t CH85:1; /* Channel 85 Injected Sampling Enable */ - uint32_t CH84:1; /* Channel 84 Injected Sampling Enable */ - uint32_t CH83:1; /* Channel 83 Injected Sampling Enable */ - uint32_t CH82:1; /* Channel 82 Injected Sampling Enable */ - uint32_t CH81:1; /* Channel 81 Injected Sampling Enable */ - uint32_t CH80:1; /* Channel 80 Injected Sampling Enable */ - uint32_t CH79:1; /* Channel 79 Injected Sampling Enable */ - uint32_t CH78:1; /* Channel 78 Injected Sampling Enable */ - uint32_t CH77:1; /* Channel 77 Injected Sampling Enable */ - uint32_t CH76:1; /* Channel 76 Injected Sampling Enable */ - uint32_t CH75:1; /* Channel 75 Injected Sampling Enable */ - uint32_t CH74:1; /* Channel 74 Injected Sampling Enable */ - uint32_t CH73:1; /* Channel 73 Injected Sampling Enable */ - uint32_t CH72:1; /* Channel 72 Injected Sampling Enable */ - uint32_t CH71:1; /* Channel 71 Injected Sampling Enable */ - uint32_t CH70:1; /* Channel 70 Injected Sampling Enable */ - uint32_t CH69:1; /* Channel 69 Injected Sampling Enable */ - uint32_t CH68:1; /* Channel 68 Injected Sampling Enable */ - uint32_t CH67:1; /* Channel 67 Injected Sampling Enable */ - uint32_t CH66:1; /* Channel 66 Injected Sampling Enable */ - uint32_t CH65:1; /* Channel 65 Injected Sampling Enable */ - uint32_t CH64:1; /* Channel 64 Injected Sampling Enable */ - } B; - } ADC_JCMR2_32B_tag; - - typedef union { /* Offset Word Regsiter */ - uint32_t R; - struct { - uint32_t:15; - uint32_t OFFSETLOAD:1; /* load_offset */ - uint32_t:8; -#ifndef USE_FIELD_ALIASES_ADC - uint32_t OFFSET_WORD:8; /* OFFSET word coeff.generated at the end of offset cancellation is lathed int o this register */ -#else - uint32_t OFFSETWORD:8; -#endif - } B; - } ADC_OFFWR_32B_tag; - - typedef union { /* Decode Signal Delay Register */ - uint32_t R; - struct { - uint32_t:24; - uint32_t DSD:8; /* take into account the settling time of the external mux */ - } B; - } ADC_DSDR_32B_tag; - - typedef union { /* Power Down Dealy Register */ - uint32_t R; - struct { - uint32_t:24; - uint32_t PDED:8; /* The delay between the power down bit reset and the starting of conversion */ - } B; - } ADC_PDEDR_32B_tag; - - - /* Register layout for all registers CDR... */ - - typedef union { /* CHANNEL DATA REGS */ - uint32_t R; - struct { - uint32_t:12; - uint32_t VALID:1; /* validity of data */ - uint32_t OVERW:1; /* overwrite data */ - uint32_t RESULT:2; /* reflects mode conversion */ - uint32_t:6; - uint32_t CDATA:10; /* Channel 0 converted data */ - } B; - } ADC_CDR_32B_tag; - - typedef union { /* Upper Threshold register 4 is not contiguous to 3 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* high threshold value s */ - uint32_t:4; - uint32_t THRL:12; /* low threshold value s */ - } B; - } ADC_THRHLR4_32B_tag; - - typedef union { /* Upper Threshold register 5 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* high threshold value s */ - uint32_t:4; - uint32_t THRL:12; /* low threshold value s */ - } B; - } ADC_THRHLR5_32B_tag; - - typedef union { /* Upper Threshold register 6 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* high threshold value s */ - uint32_t:4; - uint32_t THRL:12; /* low threshold value s */ - } B; - } ADC_THRHLR6_32B_tag; - - typedef union { /* Upper Threshold register 7 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* high threshold value s */ - uint32_t:4; - uint32_t THRL:12; /* low threshold value s */ - } B; - } ADC_THRHLR7_32B_tag; - - typedef union { /* Upper Threshold register 8 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* high threshold value s */ - uint32_t:4; - uint32_t THRL:12; /* low threshold value s */ - } B; - } ADC_THRHLR8_32B_tag; - - typedef union { /* Upper Threshold register 9 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* high threshold value s */ - uint32_t:4; - uint32_t THRL:12; /* low threshold value s */ - } B; - } ADC_THRHLR9_32B_tag; - - typedef union { /* Upper Threshold register 10 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* high threshold value s */ - uint32_t:4; - uint32_t THRL:12; /* low threshold value s */ - } B; - } ADC_THRHLR10_32B_tag; - - typedef union { /* Upper Threshold register 11 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* high threshold value s */ - uint32_t:4; - uint32_t THRL:12; /* low threshold value s */ - } B; - } ADC_THRHLR11_32B_tag; - - typedef union { /* Upper Threshold register 12 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* high threshold value s */ - uint32_t:4; - uint32_t THRL:12; /* low threshold value s */ - } B; - } ADC_THRHLR12_32B_tag; - - typedef union { /* Upper Threshold register 13 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* high threshold value s */ - uint32_t:4; - uint32_t THRL:12; /* low threshold value s */ - } B; - } ADC_THRHLR13_32B_tag; - - typedef union { /* Upper Threshold register 14 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* high threshold value s */ - uint32_t:4; - uint32_t THRL:12; /* low threshold value s */ - } B; - } ADC_THRHLR14_32B_tag; - - typedef union { /* Upper Threshold register 15 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* high threshold value s */ - uint32_t:4; - uint32_t THRL:12; /* low threshold value s */ - } B; - } ADC_THRHLR15_32B_tag; - - - /* Register layout for all registers CWSELR... */ - - typedef union { /* Channel Watchdog Select register */ - uint32_t R; - struct { - uint32_t WSEL_CH7:4; /* Channel Watchdog select for channel 7+R*8 */ - uint32_t WSEL_CH6:4; /* Channel Watchdog select for channel 6+R*8 */ - uint32_t WSEL_CH5:4; /* Channel Watchdog select for channel 5+R*8 */ - uint32_t WSEL_CH4:4; /* Channel Watchdog select for channel 4+R*8 */ - uint32_t WSEL_CH3:4; /* Channel Watchdog select for channel 3+R*8 */ - uint32_t WSEL_CH2:4; /* Channel Watchdog select for channel 2+R*8 */ - uint32_t WSEL_CH1:4; /* Channel Watchdog select for channel 1+R*8 */ - uint32_t WSEL_CH0:4; /* Channel Watchdog select for channel 0+R*8 */ - } B; - } ADC_CWSELR_32B_tag; - - - /* Register layout for all registers CWENR... */ - - typedef union { /* Channel Watchdog Enable Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t CWEN15PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN14PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN13PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN12PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN11PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN10PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN09PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN08PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN07PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN06PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN05PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN04PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN03PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN02PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN01PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - uint32_t CWEN00PRT32:1; /* Channel Watchdog Enable 0+R*32 */ - } B; - } ADC_CWENR_32B_tag; - - - /* Register layout for all registers AWORR... */ - - typedef union { /* Analog Watchdog Out of Range Register */ - uint32_t R; - struct { - uint32_t AWOR_CH31:1; /* Channel 31+R*32 converted data out of range */ - uint32_t AWOR_CH30:1; /* Channel 30+R*32 converted data out of range */ - uint32_t AWOR_CH29:1; /* Channel 29+R*32 converted data out of range */ - uint32_t AWOR_CH28:1; /* Channel 28+R*32 converted data out of range */ - uint32_t AWOR_CH27:1; /* Channel 27+R*32 converted data out of range */ - uint32_t AWOR_CH26:1; /* Channel 26+R*32 converted data out of range */ - uint32_t AWOR_CH25:1; /* Channel 25+R*32 converted data out of range */ - uint32_t AWOR_CH24:1; /* Channel 24+R*32 converted data out of range */ - uint32_t AWOR_CH23:1; /* Channel 23+R*32 converted data out of range */ - uint32_t AWOR_CH22:1; /* Channel 22+R*32 converted data out of range */ - uint32_t AWOR_CH21:1; /* Channel 21+R*32 converted data out of range */ - uint32_t AWOR_CH20:1; /* Channel 20+R*32 converted data out of range */ - uint32_t AWOR_CH19:1; /* Channel 19+R*32 converted data out of range */ - uint32_t AWOR_CH18:1; /* Channel 18+R*32 converted data out of range */ - uint32_t AWOR_CH17:1; /* Channel 17+R*32 converted data out of range */ - uint32_t AWOR_CH16:1; /* Channel 16+R*32 converted data out of range */ - uint32_t AWOR_CH15:1; /* Channel 15+R*32 converted data out of range */ - uint32_t AWOR_CH14:1; /* Channel 14+R*32 converted data out of range */ - uint32_t AWOR_CH13:1; /* Channel 13+R*32 converted data out of range */ - uint32_t AWOR_CH12:1; /* Channel 12+R*32 converted data out of range */ - uint32_t AWOR_CH11:1; /* Channel 11+R*32 converted data out of range */ - uint32_t AWOR_CH10:1; /* Channel 10+R*32 converted data out of range */ - uint32_t AWOR_CH9:1; /* Channel 9+R*32 converted data out of range */ - uint32_t AWOR_CH8:1; /* Channel 8+R*32 converted data out of range */ - uint32_t AWOR_CH7:1; /* Channel 7+R*32 converted data out of range */ - uint32_t AWOR_CH6:1; /* Channel 6+R*32 converted data out of range */ - uint32_t AWOR_CH5:1; /* Channel 5+R*32 converted data out of range */ - uint32_t AWOR_CH4:1; /* Channel 4+R*32 converted data out of range */ - uint32_t AWOR_CH3:1; /* Channel 3+R*32 converted data out of range */ - uint32_t AWOR_CH2:1; /* Channel 2+R*32 converted data out of range */ - uint32_t AWOR_CH1:1; /* Channel 1+R*32 converted data out of range */ - uint32_t AWOR_CH0:1; /* Channel 0+R*32 converted data out of range */ - } B; - } ADC_AWORR_32B_tag; - - typedef union { /* SELF TEST CONFIGURATION REGISTER 1 */ - uint32_t R; - struct { - uint32_t INPSAMP_C:8; /* Sampling phase duration for the test conversions - algorithm C */ - uint32_t INPSAMP_RC:8; /* Sampling phase duration for the test conversions - algorithm RC */ - uint32_t INPSAMP_S:8; /* Sampling phase duration for the test conversions - algorithm S */ - uint32_t:5; - uint32_t ST_INPCMP:2; /* Configuration bit for comparison phase duration for self test channel */ - uint32_t ST_INPLATCH:1; /* Configuration bit for Latching phase duration for self test channel */ - } B; - } ADC_STCR1_32B_tag; - - typedef union { /* SELF TEST CONFIGURATION REGISTER 2 */ - uint32_t R; - struct { - uint32_t:5; - uint32_t SERR:1; /* Error fault injection bit (write only) */ - uint32_t MSKSTWDTERR:1; /* Interrupt enable (STSR2.WDTERR status bit) */ - uint32_t:1; - uint32_t MSKST_EOC:1; /* Interrupt enable bit for STSR2.ST_EOC */ - uint32_t:4; - uint32_t MSKWDG_EOA_C:1; /* Interrupt enable (WDG_EOA_C status bit) */ - uint32_t MSKWDG_EOA_RC:1; /* Interrupt enable (WDG_EOA_RC status bit) */ - uint32_t MSKWDG_EOA_S:1; /* Interrupt enable (WDG_EOA_S status bit) */ - uint32_t MSKERR_C:1; /* Interrupt enable (ERR_C status bit) */ - uint32_t MSKERR_RC:1; /* Interrupt enable (ERR_RC status bit) */ - uint32_t MSKERR_S2:1; /* Interrupt enable (ERR_S2 status bit) */ - uint32_t MSKERR_S1:1; /* Interrupt enable (ERR_S1 status bit) */ - uint32_t MSKERR_S0:1; /* Interrupt enable (ERR_S0 status bit) */ - uint32_t:3; - uint32_t EN:1; /* Self testing channel enable */ - uint32_t:4; - uint32_t FMA_C:1; /* Fault mapping for the algorithm C */ - uint32_t FMAR_C:1; /* Fault mapping for the algorithm RC */ - uint32_t FMA_S:1; /* Fault mapping for the algorithm BGAP */ - } B; - } ADC_STCR2_32B_tag; - - typedef union { /* SELF TEST CONFIGURATION REGISTER 3 */ - uint32_t R; - struct { - uint32_t:22; - uint32_t ALG:2; /* Algorithm scheduling */ - uint32_t:8; - } B; - } ADC_STCR3_32B_tag; - - typedef union { /* SELF TEST BAUD RATE REGISTER */ - uint32_t R; - struct { - uint32_t:13; - uint32_t WDT:3; /* Watchdog timer value */ - uint32_t:8; - uint32_t BR:8; /* Baud rate for the selected algorithm in SCAN mode */ - } B; - } ADC_STBRR_32B_tag; - - typedef union { /* SELF TEST STATUS REGISTER 1 */ - uint32_t R; - struct { - uint32_t:6; - uint32_t WDTERR:1; /* Watchdog timer error */ - uint32_t OVERWR:1; /* Overwrite error */ - uint32_t ST_EOC:1; /* Self test EOC bit */ - uint32_t:4; - uint32_t WDG_EOA_C:1; /* Algorithm C completed without error */ - uint32_t WDG_EOA_RC:1; /* Algorithm RC completed without error */ - uint32_t WDG_EOA_S:1; /* Algorithm S completed without error */ - uint32_t ERR_C:1; /* Error on the self testing channel (algorithm C) */ - uint32_t ERR_RC:1; /* Error on the self testing channel (algorithm RC) */ - uint32_t ERR_S2:1; /* Error on the self testing channel (algorithm SUPPLY, step 2) */ - uint32_t ERR_S1:1; /* Error on the self testing channel (algorithm SUPPLY, step 1) */ - uint32_t ERR_S0:1; /* Error on the self testing channel (algorithm SUPPLY, step 0) */ - uint32_t:1; - uint32_t STEP_C:5; /* Step of algorithm C when ERR_C has occurred */ - uint32_t STEP_RC:5; /* Step of algorithm RC when ERR_RC has occurred */ - } B; - } ADC_STSR1_32B_tag; - - typedef union { /* SELF TEST STATUS REGISTER 2 */ - uint32_t R; - struct { - uint32_t OVFL:1; /* Overflow bit */ - uint32_t:3; - uint32_t DATA1:12; /* Test channel converted data when ERR_S1 has occurred */ - uint32_t:4; - uint32_t DATA0:12; /* Test channel converted data when ERR_S1 has occurred */ - } B; - } ADC_STSR2_32B_tag; - - typedef union { /* SELF TEST STATUS REGISTER 3 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t DATA1:12; /* Test channel converted data when ERR_S0 has occurred */ - uint32_t:4; - uint32_t DATA0:12; /* Test channel converted data when ERR_S0 has occurred */ - } B; - } ADC_STSR3_32B_tag; - - typedef union { /* SELF TEST STATUS REGISTER 4 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t DATA1:12; /* Test channel converted data when ERR_C has occurred */ - uint32_t:4; - uint32_t DATA0:12; /* Test channel converted data when ERR_C has occurred */ - } B; - } ADC_STSR4_32B_tag; - - typedef union { /* SELF TEST DATA REGISTER 1 */ - uint32_t R; - struct { - uint32_t:12; - uint32_t VALID:1; /* Valid data */ - uint32_t OVERWR:1; /* Overwrite data */ - uint32_t:6; - uint32_t TCDATA:12; /* Test channel converted data */ - } B; - } ADC_STDR1_32B_tag; - - typedef union { /* SELF TEST DATA REGISTER 2 */ - uint32_t R; - struct { - uint32_t FDATA:12; /* Fractional part of the ratio TEST for algorithm S */ - uint32_t VALID:1; /* Valid data */ - uint32_t OVERWR:1; /* Overwrite data */ - uint32_t:6; - uint32_t IDATA:12; /* Integer part of the ratio TEST for algorithm S */ - } B; - } ADC_STDR2_32B_tag; - - typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 0 */ - uint32_t R; - struct { - uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ - uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm S */ - uint32_t:2; - uint32_t THRH:12; /* High threshold value for channel 0 */ - uint32_t:4; - uint32_t THRL:12; /* Low threshold value for channel 0 */ - } B; - } ADC_STAW0R_32B_tag; - - typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1A */ - uint32_t R; - struct { - uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ - uint32_t:3; - uint32_t THRH:12; /* High threshold value for test channel - algorithm S */ - uint32_t:4; - uint32_t THRL:12; /* Low threshold value for test channel - algorithm S */ - } B; - } ADC_STAW1AR_32B_tag; - - typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1B */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* High threshold value for test channel - algorithm S */ - uint32_t:4; - uint32_t THRL:12; /* Low threshold value for test channel - algorithm S */ - } B; - } ADC_STAW1BR_32B_tag; - - typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 2 */ - uint32_t R; - struct { - uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ - uint32_t:19; - uint32_t THRL:12; /* Low threshold value for channel */ - } B; - } ADC_STAW2R_32B_tag; - - typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 3 */ - uint32_t R; - struct { - uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm RC */ - uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm RC */ - uint32_t:2; - uint32_t THRH:12; /* High threshold value for channel 3 */ - uint32_t:4; - uint32_t THRL:12; /* Low threshold value for channel 3 */ - } B; - } ADC_STAW3R_32B_tag; - - typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 4 */ - uint32_t R; - struct { - uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm C */ - uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm C */ - uint32_t:2; - uint32_t THRH:12; /* High threshold value for channel 4 */ - uint32_t:4; - uint32_t THRL:12; /* Low threshold value for channel 4 */ - } B; - } ADC_STAW4R_32B_tag; - - typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 5 */ - uint32_t R; - struct { - uint32_t:4; - uint32_t THRH:12; /* High threshold value for algorithm C */ - uint32_t:4; - uint32_t THRL:12; /* Low threshold value for algorithm C */ - } B; - } ADC_STAW5R_32B_tag; - - - - typedef struct ADC_struct_tag { /* start of ADC_tag */ - /* module configuration register */ - ADC_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ - /* module status register */ - ADC_MSR_32B_tag MSR; /* offset: 0x0004 size: 32 bit */ - int8_t ADC_reserved_0008[8]; - /* Interrupt status register */ - ADC_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */ - union { - ADC_CEOCFR0_32B_tag CEOCFR[3]; /* offset: 0x0014 (0x0004 x 3) */ - - struct { - /* CHANNEL PENDING REGISTER 0 */ - ADC_CEOCFR0_32B_tag CEOCFR0; /* offset: 0x0014 size: 32 bit */ - /* CHANNEL PENDING REGISTER 1 */ - ADC_CEOCFR1_32B_tag CEOCFR1; /* offset: 0x0018 size: 32 bit */ - /* CHANNEL PENDING REGISTER 2 */ - ADC_CEOCFR2_32B_tag CEOCFR2; /* offset: 0x001C size: 32 bit */ - }; - - }; - /* interrupt mask register */ - ADC_IMR_32B_tag IMR; /* offset: 0x0020 size: 32 bit */ - union { - ADC_CIMR0_32B_tag CIMR[3]; /* offset: 0x0024 (0x0004 x 3) */ - - struct { - /* CHANNEL INTERRUPT MASK REGISTER 0 */ - ADC_CIMR0_32B_tag CIMR0; /* offset: 0x0024 size: 32 bit */ - /* CHANNEL INTERRUPT MASK REGISTER 1 */ - ADC_CIMR1_32B_tag CIMR1; /* offset: 0x0028 size: 32 bit */ - /* CHANNEL INTERRUPT MASK REGISTER 2 */ - ADC_CIMR2_32B_tag CIMR2; /* offset: 0x002C size: 32 bit */ - }; - - }; - /* Watchdog Threshold interrupt status register */ - ADC_WTISR_32B_tag WTISR; /* offset: 0x0030 size: 32 bit */ - /* Watchdog interrupt MASK register */ - ADC_WTIMR_32B_tag WTIMR; /* offset: 0x0034 size: 32 bit */ - int8_t ADC_reserved_0038[8]; - /* DMAE register */ - ADC_DMAE_32B_tag DMAE; /* offset: 0x0040 size: 32 bit */ - union { - ADC_DMAR0_32B_tag DMAR[3]; /* offset: 0x0044 (0x0004 x 3) */ - - struct { - /* DMA REGISTER 0 */ - ADC_DMAR0_32B_tag DMAR0; /* offset: 0x0044 size: 32 bit */ - /* DMA REGISTER 1 */ - ADC_DMAR1_32B_tag DMAR1; /* offset: 0x0048 size: 32 bit */ - /* DMA REGISTER 2 */ - ADC_DMAR2_32B_tag DMAR2; /* offset: 0x004C size: 32 bit */ - }; - - }; - union { - /* Threshold Control register C */ - ADC_TRC_32B_tag TRC[4]; /* offset: 0x0050 (0x0004 x 4) */ - - struct { - /* Threshold Control register C */ - ADC_TRC_32B_tag TRC0; /* offset: 0x0050 size: 32 bit */ - ADC_TRC_32B_tag TRC1; /* offset: 0x0054 size: 32 bit */ - ADC_TRC_32B_tag TRC2; /* offset: 0x0058 size: 32 bit */ - ADC_TRC_32B_tag TRC3; /* offset: 0x005C size: 32 bit */ - }; - - }; - union { - /* Upper Threshold register */ - ADC_THRHLR_32B_tag THRHLR[4]; /* offset: 0x0060 (0x0004 x 4) */ - - struct { - /* Upper Threshold register */ - ADC_THRHLR_32B_tag THRHLR0; /* offset: 0x0060 size: 32 bit */ - ADC_THRHLR_32B_tag THRHLR1; /* offset: 0x0064 size: 32 bit */ - ADC_THRHLR_32B_tag THRHLR2; /* offset: 0x0068 size: 32 bit */ - ADC_THRHLR_32B_tag THRHLR3; /* offset: 0x006C size: 32 bit */ - }; - - }; - union { - /* alternate Upper Threshold register */ - ADC_THRALT_32B_tag THRALT[4]; /* offset: 0x0070 (0x0004 x 4) */ - - struct { - /* alternate Upper Threshold register */ - ADC_THRALT_32B_tag THRALT0; /* offset: 0x0070 size: 32 bit */ - ADC_THRALT_32B_tag THRALT1; /* offset: 0x0074 size: 32 bit */ - ADC_THRALT_32B_tag THRALT2; /* offset: 0x0078 size: 32 bit */ - ADC_THRALT_32B_tag THRALT3; /* offset: 0x007C size: 32 bit */ - }; - - }; - /* PRESAMPLING CONTROL REGISTER */ - ADC_PSCR_32B_tag PSCR; /* offset: 0x0080 size: 32 bit */ - union { - ADC_PSR0_32B_tag PSR[3]; /* offset: 0x0084 (0x0004 x 3) */ - - struct { - /* Presampling Register 0 */ - ADC_PSR0_32B_tag PSR0; /* offset: 0x0084 size: 32 bit */ - /* Presampling REGISTER 1 */ - ADC_PSR1_32B_tag PSR1; /* offset: 0x0088 size: 32 bit */ - /* Presampling REGISTER 2 */ - ADC_PSR2_32B_tag PSR2; /* offset: 0x008C size: 32 bit */ - }; - - }; - int8_t ADC_reserved_0090_C[4]; - union { - /* conversion timing register */ - ADC_CTR_32B_tag CTR[3]; /* offset: 0x0094 (0x0004 x 3) */ - - struct { - /* conversion timing register */ - ADC_CTR_32B_tag CTR0; /* offset: 0x0094 size: 32 bit */ - ADC_CTR_32B_tag CTR1; /* offset: 0x0098 size: 32 bit */ - ADC_CTR_32B_tag CTR2; /* offset: 0x009C size: 32 bit */ - }; - - }; - int8_t ADC_reserved_00A0_C[4]; - union { - ADC_NCMR0_32B_tag NCMR[3]; /* offset: 0x00A4 (0x0004 x 3) */ - - struct { - /* NORMAL CONVERSION MASK REGISTER 0 */ - ADC_NCMR0_32B_tag NCMR0; /* offset: 0x00A4 size: 32 bit */ - /* NORMAL CONVERSION MASK REGISTER 1 */ - ADC_NCMR1_32B_tag NCMR1; /* offset: 0x00A8 size: 32 bit */ - /* NORMAL CONVERSION MASK REGISTER 2 */ - ADC_NCMR2_32B_tag NCMR2; /* offset: 0x00AC size: 32 bit */ - }; - - }; - int8_t ADC_reserved_00B0_C[4]; - union { - ADC_JCMR0_32B_tag JCMR[3]; /* offset: 0x00B4 (0x0004 x 3) */ - - struct { - /* Injected Conversion Mask Register 0 */ - ADC_JCMR0_32B_tag JCMR0; /* offset: 0x00B4 size: 32 bit */ - /* INJECTED CONVERSION MASK REGISTER 1 */ - ADC_JCMR1_32B_tag JCMR1; /* offset: 0x00B8 size: 32 bit */ - /* INJECTED CONVERSION MASK REGISTER 2 */ - ADC_JCMR2_32B_tag JCMR2; /* offset: 0x00BC size: 32 bit */ - }; - - }; - /* Offset Word Regsiter */ - ADC_OFFWR_32B_tag OFFWR; /* offset: 0x00C0 size: 32 bit */ - /* Decode Signal Delay Register */ - ADC_DSDR_32B_tag DSDR; /* offset: 0x00C4 size: 32 bit */ - /* Power Down Dealy Register */ - ADC_PDEDR_32B_tag PDEDR; /* offset: 0x00C8 size: 32 bit */ - int8_t ADC_reserved_00CC_C[52]; - union { - /* CHANNEL DATA REGS */ - ADC_CDR_32B_tag CDR[96]; /* offset: 0x0100 (0x0004 x 96) */ - - struct { - /* CHANNEL DATA REGS */ - ADC_CDR_32B_tag CDR0; /* offset: 0x0100 size: 32 bit */ - ADC_CDR_32B_tag CDR1; /* offset: 0x0104 size: 32 bit */ - ADC_CDR_32B_tag CDR2; /* offset: 0x0108 size: 32 bit */ - ADC_CDR_32B_tag CDR3; /* offset: 0x010C size: 32 bit */ - ADC_CDR_32B_tag CDR4; /* offset: 0x0110 size: 32 bit */ - ADC_CDR_32B_tag CDR5; /* offset: 0x0114 size: 32 bit */ - ADC_CDR_32B_tag CDR6; /* offset: 0x0118 size: 32 bit */ - ADC_CDR_32B_tag CDR7; /* offset: 0x011C size: 32 bit */ - ADC_CDR_32B_tag CDR8; /* offset: 0x0120 size: 32 bit */ - ADC_CDR_32B_tag CDR9; /* offset: 0x0124 size: 32 bit */ - ADC_CDR_32B_tag CDR10; /* offset: 0x0128 size: 32 bit */ - ADC_CDR_32B_tag CDR11; /* offset: 0x012C size: 32 bit */ - ADC_CDR_32B_tag CDR12; /* offset: 0x0130 size: 32 bit */ - ADC_CDR_32B_tag CDR13; /* offset: 0x0134 size: 32 bit */ - ADC_CDR_32B_tag CDR14; /* offset: 0x0138 size: 32 bit */ - ADC_CDR_32B_tag CDR15; /* offset: 0x013C size: 32 bit */ - ADC_CDR_32B_tag CDR16; /* offset: 0x0140 size: 32 bit */ - ADC_CDR_32B_tag CDR17; /* offset: 0x0144 size: 32 bit */ - ADC_CDR_32B_tag CDR18; /* offset: 0x0148 size: 32 bit */ - ADC_CDR_32B_tag CDR19; /* offset: 0x014C size: 32 bit */ - ADC_CDR_32B_tag CDR20; /* offset: 0x0150 size: 32 bit */ - ADC_CDR_32B_tag CDR21; /* offset: 0x0154 size: 32 bit */ - ADC_CDR_32B_tag CDR22; /* offset: 0x0158 size: 32 bit */ - ADC_CDR_32B_tag CDR23; /* offset: 0x015C size: 32 bit */ - ADC_CDR_32B_tag CDR24; /* offset: 0x0160 size: 32 bit */ - ADC_CDR_32B_tag CDR25; /* offset: 0x0164 size: 32 bit */ - ADC_CDR_32B_tag CDR26; /* offset: 0x0168 size: 32 bit */ - ADC_CDR_32B_tag CDR27; /* offset: 0x016C size: 32 bit */ - ADC_CDR_32B_tag CDR28; /* offset: 0x0170 size: 32 bit */ - ADC_CDR_32B_tag CDR29; /* offset: 0x0174 size: 32 bit */ - ADC_CDR_32B_tag CDR30; /* offset: 0x0178 size: 32 bit */ - ADC_CDR_32B_tag CDR31; /* offset: 0x017C size: 32 bit */ - ADC_CDR_32B_tag CDR32; /* offset: 0x0180 size: 32 bit */ - ADC_CDR_32B_tag CDR33; /* offset: 0x0184 size: 32 bit */ - ADC_CDR_32B_tag CDR34; /* offset: 0x0188 size: 32 bit */ - ADC_CDR_32B_tag CDR35; /* offset: 0x018C size: 32 bit */ - ADC_CDR_32B_tag CDR36; /* offset: 0x0190 size: 32 bit */ - ADC_CDR_32B_tag CDR37; /* offset: 0x0194 size: 32 bit */ - ADC_CDR_32B_tag CDR38; /* offset: 0x0198 size: 32 bit */ - ADC_CDR_32B_tag CDR39; /* offset: 0x019C size: 32 bit */ - ADC_CDR_32B_tag CDR40; /* offset: 0x01A0 size: 32 bit */ - ADC_CDR_32B_tag CDR41; /* offset: 0x01A4 size: 32 bit */ - ADC_CDR_32B_tag CDR42; /* offset: 0x01A8 size: 32 bit */ - ADC_CDR_32B_tag CDR43; /* offset: 0x01AC size: 32 bit */ - ADC_CDR_32B_tag CDR44; /* offset: 0x01B0 size: 32 bit */ - ADC_CDR_32B_tag CDR45; /* offset: 0x01B4 size: 32 bit */ - ADC_CDR_32B_tag CDR46; /* offset: 0x01B8 size: 32 bit */ - ADC_CDR_32B_tag CDR47; /* offset: 0x01BC size: 32 bit */ - ADC_CDR_32B_tag CDR48; /* offset: 0x01C0 size: 32 bit */ - ADC_CDR_32B_tag CDR49; /* offset: 0x01C4 size: 32 bit */ - ADC_CDR_32B_tag CDR50; /* offset: 0x01C8 size: 32 bit */ - ADC_CDR_32B_tag CDR51; /* offset: 0x01CC size: 32 bit */ - ADC_CDR_32B_tag CDR52; /* offset: 0x01D0 size: 32 bit */ - ADC_CDR_32B_tag CDR53; /* offset: 0x01D4 size: 32 bit */ - ADC_CDR_32B_tag CDR54; /* offset: 0x01D8 size: 32 bit */ - ADC_CDR_32B_tag CDR55; /* offset: 0x01DC size: 32 bit */ - ADC_CDR_32B_tag CDR56; /* offset: 0x01E0 size: 32 bit */ - ADC_CDR_32B_tag CDR57; /* offset: 0x01E4 size: 32 bit */ - ADC_CDR_32B_tag CDR58; /* offset: 0x01E8 size: 32 bit */ - ADC_CDR_32B_tag CDR59; /* offset: 0x01EC size: 32 bit */ - ADC_CDR_32B_tag CDR60; /* offset: 0x01F0 size: 32 bit */ - ADC_CDR_32B_tag CDR61; /* offset: 0x01F4 size: 32 bit */ - ADC_CDR_32B_tag CDR62; /* offset: 0x01F8 size: 32 bit */ - ADC_CDR_32B_tag CDR63; /* offset: 0x01FC size: 32 bit */ - ADC_CDR_32B_tag CDR64; /* offset: 0x0200 size: 32 bit */ - ADC_CDR_32B_tag CDR65; /* offset: 0x0204 size: 32 bit */ - ADC_CDR_32B_tag CDR66; /* offset: 0x0208 size: 32 bit */ - ADC_CDR_32B_tag CDR67; /* offset: 0x020C size: 32 bit */ - ADC_CDR_32B_tag CDR68; /* offset: 0x0210 size: 32 bit */ - ADC_CDR_32B_tag CDR69; /* offset: 0x0214 size: 32 bit */ - ADC_CDR_32B_tag CDR70; /* offset: 0x0218 size: 32 bit */ - ADC_CDR_32B_tag CDR71; /* offset: 0x021C size: 32 bit */ - ADC_CDR_32B_tag CDR72; /* offset: 0x0220 size: 32 bit */ - ADC_CDR_32B_tag CDR73; /* offset: 0x0224 size: 32 bit */ - ADC_CDR_32B_tag CDR74; /* offset: 0x0228 size: 32 bit */ - ADC_CDR_32B_tag CDR75; /* offset: 0x022C size: 32 bit */ - ADC_CDR_32B_tag CDR76; /* offset: 0x0230 size: 32 bit */ - ADC_CDR_32B_tag CDR77; /* offset: 0x0234 size: 32 bit */ - ADC_CDR_32B_tag CDR78; /* offset: 0x0238 size: 32 bit */ - ADC_CDR_32B_tag CDR79; /* offset: 0x023C size: 32 bit */ - ADC_CDR_32B_tag CDR80; /* offset: 0x0240 size: 32 bit */ - ADC_CDR_32B_tag CDR81; /* offset: 0x0244 size: 32 bit */ - ADC_CDR_32B_tag CDR82; /* offset: 0x0248 size: 32 bit */ - ADC_CDR_32B_tag CDR83; /* offset: 0x024C size: 32 bit */ - ADC_CDR_32B_tag CDR84; /* offset: 0x0250 size: 32 bit */ - ADC_CDR_32B_tag CDR85; /* offset: 0x0254 size: 32 bit */ - ADC_CDR_32B_tag CDR86; /* offset: 0x0258 size: 32 bit */ - ADC_CDR_32B_tag CDR87; /* offset: 0x025C size: 32 bit */ - ADC_CDR_32B_tag CDR88; /* offset: 0x0260 size: 32 bit */ - ADC_CDR_32B_tag CDR89; /* offset: 0x0264 size: 32 bit */ - ADC_CDR_32B_tag CDR90; /* offset: 0x0268 size: 32 bit */ - ADC_CDR_32B_tag CDR91; /* offset: 0x026C size: 32 bit */ - ADC_CDR_32B_tag CDR92; /* offset: 0x0270 size: 32 bit */ - ADC_CDR_32B_tag CDR93; /* offset: 0x0274 size: 32 bit */ - ADC_CDR_32B_tag CDR94; /* offset: 0x0278 size: 32 bit */ - ADC_CDR_32B_tag CDR95; /* offset: 0x027C size: 32 bit */ - }; - - }; - /* Upper Threshold register 4 is not contiguous to 3 */ - ADC_THRHLR4_32B_tag THRHLR4; /* offset: 0x0280 size: 32 bit */ - /* Upper Threshold register 5 */ - ADC_THRHLR5_32B_tag THRHLR5; /* offset: 0x0284 size: 32 bit */ - /* Upper Threshold register 6 */ - ADC_THRHLR6_32B_tag THRHLR6; /* offset: 0x0288 size: 32 bit */ - /* Upper Threshold register 7 */ - ADC_THRHLR7_32B_tag THRHLR7; /* offset: 0x028C size: 32 bit */ - /* Upper Threshold register 8 */ - ADC_THRHLR8_32B_tag THRHLR8; /* offset: 0x0290 size: 32 bit */ - /* Upper Threshold register 9 */ - ADC_THRHLR9_32B_tag THRHLR9; /* offset: 0x0294 size: 32 bit */ - /* Upper Threshold register 10 */ - ADC_THRHLR10_32B_tag THRHLR10; /* offset: 0x0298 size: 32 bit */ - /* Upper Threshold register 11 */ - ADC_THRHLR11_32B_tag THRHLR11; /* offset: 0x029C size: 32 bit */ - /* Upper Threshold register 12 */ - ADC_THRHLR12_32B_tag THRHLR12; /* offset: 0x02A0 size: 32 bit */ - /* Upper Threshold register 13 */ - ADC_THRHLR13_32B_tag THRHLR13; /* offset: 0x02A4 size: 32 bit */ - /* Upper Threshold register 14 */ - ADC_THRHLR14_32B_tag THRHLR14; /* offset: 0x02A8 size: 32 bit */ - /* Upper Threshold register 15 */ - ADC_THRHLR15_32B_tag THRHLR15; /* offset: 0x02AC size: 32 bit */ - union { - /* Channel Watchdog Select register */ - ADC_CWSELR_32B_tag CWSELR[12]; /* offset: 0x02B0 (0x0004 x 12) */ - - struct { - /* Channel Watchdog Select register */ - ADC_CWSELR_32B_tag CWSELR0; /* offset: 0x02B0 size: 32 bit */ - ADC_CWSELR_32B_tag CWSELR1; /* offset: 0x02B4 size: 32 bit */ - ADC_CWSELR_32B_tag CWSELR2; /* offset: 0x02B8 size: 32 bit */ - ADC_CWSELR_32B_tag CWSELR3; /* offset: 0x02BC size: 32 bit */ - ADC_CWSELR_32B_tag CWSELR4; /* offset: 0x02C0 size: 32 bit */ - ADC_CWSELR_32B_tag CWSELR5; /* offset: 0x02C4 size: 32 bit */ - ADC_CWSELR_32B_tag CWSELR6; /* offset: 0x02C8 size: 32 bit */ - ADC_CWSELR_32B_tag CWSELR7; /* offset: 0x02CC size: 32 bit */ - ADC_CWSELR_32B_tag CWSELR8; /* offset: 0x02D0 size: 32 bit */ - ADC_CWSELR_32B_tag CWSELR9; /* offset: 0x02D4 size: 32 bit */ - ADC_CWSELR_32B_tag CWSELR10; /* offset: 0x02D8 size: 32 bit */ - ADC_CWSELR_32B_tag CWSELR11; /* offset: 0x02DC size: 32 bit */ - }; - - }; - union { - /* Channel Watchdog Enable Register */ - ADC_CWENR_32B_tag CWENR[3]; /* offset: 0x02E0 (0x0004 x 3) */ - - struct { - /* Channel Watchdog Enable Register */ - ADC_CWENR_32B_tag CWENR0; /* offset: 0x02E0 size: 32 bit */ - ADC_CWENR_32B_tag CWENR1; /* offset: 0x02E4 size: 32 bit */ - ADC_CWENR_32B_tag CWENR2; /* offset: 0x02E8 size: 32 bit */ - }; - - }; - int8_t ADC_reserved_02EC_C[4]; - union { - /* Analog Watchdog Out of Range Register */ - ADC_AWORR_32B_tag AWORR[3]; /* offset: 0x02F0 (0x0004 x 3) */ - - struct { - /* Analog Watchdog Out of Range Register */ - ADC_AWORR_32B_tag AWORR0; /* offset: 0x02F0 size: 32 bit */ - ADC_AWORR_32B_tag AWORR1; /* offset: 0x02F4 size: 32 bit */ - ADC_AWORR_32B_tag AWORR2; /* offset: 0x02F8 size: 32 bit */ - }; - - }; - int8_t ADC_reserved_02FC[68]; - /* SELF TEST CONFIGURATION REGISTER 1 */ - ADC_STCR1_32B_tag STCR1; /* offset: 0x0340 size: 32 bit */ - /* SELF TEST CONFIGURATION REGISTER 2 */ - ADC_STCR2_32B_tag STCR2; /* offset: 0x0344 size: 32 bit */ - /* SELF TEST CONFIGURATION REGISTER 3 */ - ADC_STCR3_32B_tag STCR3; /* offset: 0x0348 size: 32 bit */ - /* SELF TEST BAUD RATE REGISTER */ - ADC_STBRR_32B_tag STBRR; /* offset: 0x034C size: 32 bit */ - /* SELF TEST STATUS REGISTER 1 */ - ADC_STSR1_32B_tag STSR1; /* offset: 0x0350 size: 32 bit */ - /* SELF TEST STATUS REGISTER 2 */ - ADC_STSR2_32B_tag STSR2; /* offset: 0x0354 size: 32 bit */ - /* SELF TEST STATUS REGISTER 3 */ - ADC_STSR3_32B_tag STSR3; /* offset: 0x0358 size: 32 bit */ - /* SELF TEST STATUS REGISTER 4 */ - ADC_STSR4_32B_tag STSR4; /* offset: 0x035C size: 32 bit */ - int8_t ADC_reserved_0360[16]; - /* SELF TEST DATA REGISTER 1 */ - ADC_STDR1_32B_tag STDR1; /* offset: 0x0370 size: 32 bit */ - /* SELF TEST DATA REGISTER 2 */ - ADC_STDR2_32B_tag STDR2; /* offset: 0x0374 size: 32 bit */ - int8_t ADC_reserved_0378[8]; - /* SELF TEST ANALOG WATCHDOG REGISTER 0 */ - ADC_STAW0R_32B_tag STAW0R; /* offset: 0x0380 size: 32 bit */ - /* SELF TEST ANALOG WATCHDOG REGISTER 1A */ - ADC_STAW1AR_32B_tag STAW1AR; /* offset: 0x0384 size: 32 bit */ - /* SELF TEST ANALOG WATCHDOG REGISTER 1B */ - ADC_STAW1BR_32B_tag STAW1BR; /* offset: 0x0388 size: 32 bit */ - /* SELF TEST ANALOG WATCHDOG REGISTER 2 */ - ADC_STAW2R_32B_tag STAW2R; /* offset: 0x038C size: 32 bit */ - /* SELF TEST ANALOG WATCHDOG REGISTER 3 */ - ADC_STAW3R_32B_tag STAW3R; /* offset: 0x0390 size: 32 bit */ - /* SELF TEST ANALOG WATCHDOG REGISTER 4 */ - ADC_STAW4R_32B_tag STAW4R; /* offset: 0x0394 size: 32 bit */ - /* SELF TEST ANALOG WATCHDOG REGISTER 5 */ - ADC_STAW5R_32B_tag STAW5R; /* offset: 0x0398 size: 32 bit */ - } ADC_tag; - - -#define ADC0 (*(volatile ADC_tag *) 0xFFE00000UL) -#define ADC1 (*(volatile ADC_tag *) 0xFFE04000UL) - - - -/****************************************************************/ -/* */ -/* Module: CTU */ -/* */ -/****************************************************************/ - - typedef union { /* Trigger Generator Subunit Input Selection register */ - uint32_t R; - struct { - uint32_t I15_FE:1; /* ext_signal Falling Edge */ - uint32_t I15_RE:1; /* ext_signal Rising Edge */ - uint32_t I14_FE:1; /* eTimer2 Falling Edge Enable */ - uint32_t I14_RE:1; /* eTimer2 Rising Edge Enable */ - uint32_t I13_FE:1; /* eTimer1 Falling Edge Enable */ - uint32_t I13_RE:1; /* eTimer1 Rising Edge Enable */ - uint32_t I12_FE:1; /* RPWM ch3 Falling Edge Enable */ - uint32_t I12_RE:1; /* RPWM ch3 Rising Edge Enable */ - uint32_t I11_FE:1; /* RPWM ch2 Falling Edge Enable */ - uint32_t I11_RE:1; /* RPWM ch2 Rising Edge Enable */ - uint32_t I10_FE:1; /* RPWM ch1 Falling Edge Enable */ - uint32_t I10_RE:1; /* RPWM ch1 Rising Edge Enable */ - uint32_t I9_FE:1; /* RPWM ch0 Falling Edge Enable */ - uint32_t I9_RE:1; /* RPWM ch0 Rising Edge Enable */ - uint32_t I8_FE:1; /* PWM ch3 even trig Falling edge Enable */ - uint32_t I8_RE:1; /* PWM ch3 even trig Rising edge Enable */ - uint32_t I7_FE:1; /* PWM ch2 even trig Falling edge Enable */ - uint32_t I7_RE:1; /* PWM ch2 even trig Rising edge Enable */ - uint32_t I6_FE:1; /* PWM ch1 even trig Falling edge Enable */ - uint32_t I6_RE:1; /* PWM ch1 even trig Rising edge Enable */ - uint32_t I5_FE:1; /* PWM ch0 even trig Falling edge Enable */ - uint32_t I5_RE:1; /* PWM ch0 even trig Rising edge Enable */ - uint32_t I4_FE:1; /* PWM ch3 odd trig Falling edge Enable */ - uint32_t I4_RE:1; /* PWM ch3 odd trig Rising edge Enable */ - uint32_t I3_FE:1; /* PWM ch2 odd trig Falling edge Enable */ - uint32_t I3_RE:1; /* PWM ch2 odd trig Rising edge Enable */ - uint32_t I2_FE:1; /* PWM ch1 odd trig Falling edge Enable */ - uint32_t I2_RE:1; /* PWM ch1 odd trig Rising edge Enable */ - uint32_t I1_FE:1; /* PWM ch0 odd trig Falling edge Enable */ - uint32_t I1_RE:1; /* PWM ch0 odd trig Rising edge Enable */ - uint32_t I0_FE:1; /* PWM Reload Falling Edge Enable */ - uint32_t I0_RE:1; /* PWM Reload Rising Edge Enable */ - } B; - } CTU_TGSISR_32B_tag; - - typedef union { /* Trigger Generator Subunit Control Register */ - uint16_t R; - struct { - uint16_t:7; -#ifndef USE_FIELD_ALIASES_CTU - uint16_t ET_TM:1; /* Toggle Mode Enable */ -#else - uint16_t ETTM:1; /* deprecated name - please avoid */ -#endif - uint16_t PRES:2; /* TGS Prescaler Selection */ -#ifndef USE_FIELD_ALIASES_CTU - uint16_t MRS_SM:5; /* MRS Selection in Sequential Mode */ -#else - uint16_t MRSSM:5; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t TGS_M:1; /* Trigger Generator Subunit Mode */ -#else - uint16_t TGSM:1; /* deprecated name - please avoid */ -#endif - } B; - } CTU_TGSCR_16B_tag; - - typedef union { /* */ - uint16_t R; - } CTU_TCR_16B_tag; - - typedef union { /* TGS Counter Compare Register */ - uint16_t R; -#ifndef USE_FIELD_ALIASES_CTU - struct { - uint16_t TGSCCV:16; /* deprecated field -- do not use */ - } B; -#endif - } CTU_TGSCCR_16B_tag; - - typedef union { /* TGS Counter Reload Register */ - uint16_t R; -#ifndef USE_FIELD_ALIASES_CTU - struct { - uint16_t TGSCRV:16; /* deprecated field -- do not use */ - } B; -#endif - } CTU_TGSCRR_16B_tag; - - typedef union { /* Commands List Control Register 1 */ - uint32_t R; - struct { - uint32_t:3; - uint32_t T3INDEX:5; /* Trigger 3 First Command address */ - uint32_t:3; - uint32_t T2INDEX:5; /* Trigger 2 First Command address */ - uint32_t:3; - uint32_t T1INDEX:5; /* Trigger 1 First Command address */ - uint32_t:3; - uint32_t T0INDEX:5; /* Trigger 0 First Command address */ - } B; - } CTU_CLCR1_32B_tag; - - typedef union { /* Commands List Control Register 2 */ - uint32_t R; - struct { - uint32_t:3; - uint32_t T7INDEX:5; /* Trigger 7 First Command address */ - uint32_t:3; - uint32_t T6INDEX:5; /* Trigger 6 First Command address */ - uint32_t:3; - uint32_t T5INDEX:5; /* Trigger 5 First Command address */ - uint32_t:3; - uint32_t T4INDEX:5; /* Trigger 4 First Command address */ - } B; - } CTU_CLCR2_32B_tag; - - typedef union { /* Trigger Handler Control Register 1 */ - uint32_t R; - struct { - uint32_t:1; - uint32_t T3_E:1; /* Trigger 3 enable */ - uint32_t T3_ETE:1; /* Trigger 3 Ext Trigger output enable */ - uint32_t T3_T4E:1; /* Trigger 3 Timer4 output enable */ - uint32_t T3_T3E:1; /* Trigger 3 Timer3 output enable */ - uint32_t T3_T2E:1; /* Trigger 3 Timer2 output enable */ - uint32_t T3_T1E:1; /* Trigger 3 Timer1 output enable */ - uint32_t T3_ADCE:1; /* Trigger 3 ADC Command output enable */ - uint32_t:1; - uint32_t T2_E:1; /* Trigger 2 enable */ - uint32_t T2_ETE:1; /* Trigger 2 Ext Trigger output enable */ - uint32_t T2_T4E:1; /* Trigger 2 Timer4 output enable */ - uint32_t T2_T3E:1; /* Trigger 2 Timer3 output enable */ - uint32_t T2_T2E:1; /* Trigger 2 Timer2 output enable */ - uint32_t T2_T1E:1; /* Trigger 2 Timer1 output enable */ - uint32_t T2_ADCE:1; /* Trigger 2 ADC Command output enable */ - uint32_t:1; - uint32_t T1_E:1; /* Trigger 1 enable */ - uint32_t T1_ETE:1; /* Trigger 1 Ext Trigger output enable */ - uint32_t T1_T4E:1; /* Trigger 1 Timer4 output enable */ - uint32_t T1_T3E:1; /* Trigger 1 Timer3 output enable */ - uint32_t T1_T2E:1; /* Trigger 1 Timer2 output enable */ - uint32_t T1_T1E:1; /* Trigger 1 Timer1 output enable */ - uint32_t T1_ADCE:1; /* Trigger 1 ADC Command output enable */ - uint32_t:1; - uint32_t T0_E:1; /* Trigger 0 enable */ - uint32_t T0_ETE:1; /* Trigger 0 Ext Trigger output enable */ - uint32_t T0_T4E:1; /* Trigger 0 Timer4 output enable */ - uint32_t T0_T3E:1; /* Trigger 0 Timer3 output enable */ - uint32_t T0_T2E:1; /* Trigger 0 Timer2 output enable */ - uint32_t T0_T1E:1; /* Trigger 0 Timer1 output enable */ - uint32_t T0_ADCE:1; /* Trigger 0 ADC Command output enable */ - } B; - } CTU_THCR1_32B_tag; - - typedef union { /* Trigger Handler Control Register 2 */ - uint32_t R; - struct { - uint32_t:1; - uint32_t T7_E:1; /* Trigger 7 enable */ - uint32_t T7_ETE:1; /* Trigger 7 Ext Trigger output enable */ - uint32_t T7_T4E:1; /* Trigger 7 Timer4 output enable */ - uint32_t T7_T3E:1; /* Trigger 7 Timer3 output enable */ - uint32_t T7_T2E:1; /* Trigger 7 Timer2 output enable */ - uint32_t T7_T1E:1; /* Trigger 7 Timer1 output enable */ - uint32_t T7_ADCE:1; /* Trigger 7 ADC Command output enable */ - uint32_t:1; - uint32_t T6_E:1; /* Trigger 6 enable */ - uint32_t T6_ETE:1; /* Trigger 6 Ext Trigger output enable */ - uint32_t T6_T4E:1; /* Trigger 6 Timer4 output enable */ - uint32_t T6_T3E:1; /* Trigger 6 Timer3 output enable */ - uint32_t T6_T2E:1; /* Trigger 6 Timer2 output enable */ - uint32_t T6_T1E:1; /* Trigger 6 Timer1 output enable */ - uint32_t T6_ADCE:1; /* Trigger 6 ADC Command output enable */ - uint32_t:1; - uint32_t T5_E:1; /* Trigger 5 enable */ - uint32_t T5_ETE:1; /* Trigger 5 Ext Trigger output enable */ - uint32_t T5_T4E:1; /* Trigger 5 Timer4 output enable */ - uint32_t T5_T3E:1; /* Trigger 5 Timer3 output enable */ - uint32_t T5_T2E:1; /* Trigger 5 Timer2 output enable */ - uint32_t T5_T1E:1; /* Trigger 5 Timer1 output enable */ - uint32_t T5_ADCE:1; /* Trigger 5 ADC Command output enable */ - uint32_t:1; - uint32_t T4_E:1; /* Trigger 4 enable */ - uint32_t T4_ETE:1; /* Trigger 4 Ext Trigger output enable */ - uint32_t T4_T4E:1; /* Trigger 4 Timer4 output enable */ - uint32_t T4_T3E:1; /* Trigger 4 Timer3 output enable */ - uint32_t T4_T2E:1; /* Trigger 4 Timer2 output enable */ - uint32_t T4_T1E:1; /* Trigger 4 Timer1 output enable */ - uint32_t T4_ADCE:1; /* Trigger 4 ADC Command output enable */ - } B; - } CTU_THCR2_32B_tag; - - - /* Register layout for all registers CLR_DCM... */ - - typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ - uint16_t R; - struct { - uint16_t CIR:1; /* Command Interrupt Request */ - uint16_t LC:1; /* Last Command */ - uint16_t CMS:1; /* Conversion Mode Selection */ - uint16_t FIFO:3; /* FIFO for ADC A/B */ - uint16_t:1; - uint16_t CHB:4; /* ADC unit B channel number */ - uint16_t:1; - uint16_t CHA:4; /* ADC unit A channel number */ - } B; - } CTU_CLR_DCM_16B_tag; - - - /* Register layout for all registers CLR_SCM... */ - - typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ - uint16_t R; - struct { - uint16_t CIR:1; /* Command Interrupt Request */ - uint16_t LC:1; /* Last Command */ - uint16_t CMS:1; /* Conversion Mode Selection */ - uint16_t FIFO:3; /* FIFO for ADC A/B */ - uint16_t:4; - uint16_t SU:1; /* Selection ADC Unit */ - uint16_t:1; - uint16_t CH:4; /* ADC unit channel number */ - } B; - } CTU_CLR_SCM_16B_tag; - - - /* Register layout for all registers CLR... */ - - - typedef union { /* Control Register */ - uint16_t R; - struct { - uint16_t EMPTY_CLR7:1; /* Empty Clear 7 */ - uint16_t EMPTY_CLR6:1; /* Empty Clear 6 */ - uint16_t EMPTY_CLR5:1; /* Empty Clear 5 */ - uint16_t EMPTY_CLR4:1; /* Empty Clear 4 */ - uint16_t EMPTY_CLR3:1; /* Empty Clear 3 */ - uint16_t EMPTY_CLR2:1; /* Empty Clear 2 */ - uint16_t EMPTY_CLR1:1; /* Empty Clear 1 */ - uint16_t EMPTY_CLR0:1; /* Empty Clear 0 */ -#ifndef USE_FIELD_ALIASES_CTU - uint16_t DMA_EN7:1; /* Enable DMA interface for FIFO 7 */ -#else - uint16_t DMAEN7:1; /* Enable DMA interface for FIFO 7 */ -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t DMA_EN6:1; /* Enable DMA interface for FIFO 6 */ -#else - uint16_t DMAEN6:1; /* Enable DMA interface for FIFO 6 */ -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t DMA_EN5:1; /* Enable DMA interface for FIFO 5 */ -#else - uint16_t DMAEN5:1; /* Enable DMA interface for FIFO 5 */ -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t DMA_EN4:1; /* Enable DMA interface for FIFO 4 */ -#else - uint16_t DMAEN4:1; /* Enable DMA interface for FIFO 4 */ -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t DMA_EN3:1; /* Enable DMA interface for FIFO 3 */ -#else - uint16_t DMAEN3:1; /* Enable DMA interface for FIFO 3 */ -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t DMA_EN2:1; /* Enable DMA interface for FIFO 2 */ -#else - uint16_t DMAEN2:1; /* Enable DMA interface for FIFO 2 */ -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t DMA_EN1:1; /* Enable DMA interface for FIFO 1 */ -#else - uint16_t DMAEN1:1; /* Enable DMA interface for FIFO 1 */ -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t DMA_EN0:1; /* Enable DMA interface for FIFO 0 */ -#else - uint16_t DMAEN0:1; /* Enable DMA interface for FIFO 0 */ -#endif - } B; - } CTU_CR_16B_tag; - - typedef union { /* Control Register FIFO */ - uint32_t R; - struct { - uint32_t FIFO_OVERRUN_EN7:1; /* FIFO 7 OVERRUN Enable Interrupt */ - uint32_t FIFO_OVERFLOW_EN7:1; /* FIFO 7 OVERFLOW Enable Interrupt */ - uint32_t FIFO_EMPTY_EN7:1; /* FIFO 7 EMPTY Enable Interrupt */ - uint32_t FIFO_FULL_EN7:1; /* FIFO 7 FULL Enable Interrupt */ - uint32_t FIFO_OVERRUN_EN6:1; /* FIFO 6 OVERRUN Enable Interrupt */ - uint32_t FIFO_OVERFLOW_EN6:1; /* FIFO 6 OVERFLOW Enable Interrupt */ - uint32_t FIFO_EMPTY_EN6:1; /* FIFO 6 EMPTY Enable Interrupt */ - uint32_t FIFO_FULL_EN6:1; /* FIFO 6 FULL Enable Interrupt */ - uint32_t FIFO_OVERRUN_EN5:1; /* FIFO 5 OVERRUN Enable Interrupt */ - uint32_t FIFO_OVERFLOW_EN5:1; /* FIFO 5 OVERFLOW Enable Interrupt */ - uint32_t FIFO_EMPTY_EN5:1; /* FIFO 5 EMPTY Enable Interrupt */ - uint32_t FIFO_FULL_EN5:1; /* FIFO 5 FULL Enable Interrupt */ - uint32_t FIFO_OVERRUN_EN4:1; /* FIFO 4 OVERRUN Enable Interrupt */ - uint32_t FIFO_OVERFLOW_EN4:1; /* FIFO 4 OVERFLOW Enable Interrupt */ - uint32_t FIFO_EMPTY_EN4:1; /* FIFO 4 EMPTY Enable Interrupt */ - uint32_t FIFO_FULL_EN4:1; /* FIFO 4 FULL Enable Interrupt */ - uint32_t FIFO_OVERRUN_EN3:1; /* FIFO 3 OVERRUN Enable Interrupt */ - uint32_t FIFO_OVERFLOW_EN3:1; /* FIFO 3 OVERFLOW Enable Interrupt */ - uint32_t FIFO_EMPTY_EN3:1; /* FIFO 3 EMPTY Enable Interrupt */ - uint32_t FIFO_FULL_EN3:1; /* FIFO 3 FULL Enable Interrupt */ - uint32_t FIFO_OVERRUN_EN2:1; /* FIFO 2 OVERRUN Enable Interrupt */ - uint32_t FIFO_OVERFLOW_EN2:1; /* FIFO 2 OVERFLOW Enable Interrupt */ - uint32_t FIFO_EMPTY_EN2:1; /* FIFO 2 EMPTY Enable Interrupt */ - uint32_t FIFO_FULL_EN2:1; /* FIFO 2 FULL Enable Interrupt */ - uint32_t FIFO_OVERRUN_EN1:1; /* FIFO 1 OVERRUN Enable Interrupt */ - uint32_t FIFO_OVERFLOW_EN1:1; /* FIFO 1 OVERFLOW Enable Interrupt */ - uint32_t FIFO_EMPTY_EN1:1; /* FIFO 1 EMPTY Enable Interrupt */ - uint32_t FIFO_FULL_EN1:1; /* FIFO 1 FULL Enable Interrupt */ - uint32_t FIFO_OVERRUN_EN0:1; /* FIFO 0 OVERRUN Enable Interrupt */ - uint32_t FIFO_OVERFLOW_EN0:1; /* FIFO 0 OVERFLOW Enable Interrupt */ - uint32_t FIFO_EMPTY_EN0:1; /* FIFO 0 EMPTY Enable Interrupt */ - uint32_t FIFO_FULL_EN0:1; /* FIFO 0 FULL Enable Interrupt */ - } B; - } CTU_FCR_32B_tag; - - typedef union { /* Threshold 1 Register */ - uint32_t R; - struct { - uint32_t THRESHOLD3:8; /* Threshlod FIFO 3 */ - uint32_t THRESHOLD2:8; /* Threshlod FIFO 2 */ - uint32_t THRESHOLD1:8; /* Threshlod FIFO 1 */ - uint32_t THRESHOLD0:8; /* Threshlod FIFO 0 */ - } B; - } CTU_TH1_32B_tag; - - typedef union { /* Threshold 2 Register */ - uint32_t R; - struct { - uint32_t THRESHOLD7:8; /* Threshlod FIFO 7 */ - uint32_t THRESHOLD6:8; /* Threshlod FIFO 6 */ - uint32_t THRESHOLD5:8; /* Threshlod FIFO 5 */ - uint32_t THRESHOLD4:8; /* Threshlod FIFO 4 */ - } B; - } CTU_TH2_32B_tag; - - typedef union { /* Status Register */ - uint32_t R; - struct { - uint32_t FIFO_OVERRUN7:1; /* FIFO 7 OVERRUN Flag */ - uint32_t FIFO_OVERFLOW7:1; /* FIFO 7 OVERFLOW Flag */ - uint32_t FIFO_EMPTY7:1; /* FIFO 7 EMPTY Flag */ - uint32_t FIFO_FULL7:1; /* FIFO 7 FULL Flag */ - uint32_t FIFO_OVERRUN6:1; /* FIFO 6 OVERRUN Flag */ - uint32_t FIFO_OVERFLOW6:1; /* FIFO 6 OVERFLOW Flag */ - uint32_t FIFO_EMPTY6:1; /* FIFO 6 EMPTY Flag */ - uint32_t FIFO_FULL6:1; /* FIFO 6 FULL Flag */ - uint32_t FIFO_OVERRUN5:1; /* FIFO 5 OVERRUN Flag */ - uint32_t FIFO_OVERFLOW5:1; /* FIFO 5 OVERFLOW Flag */ - uint32_t FIFO_EMPTY5:1; /* FIFO 5 EMPTY Flag */ - uint32_t FIFO_FULL5:1; /* FIFO 5 FULL Flag */ - uint32_t FIFO_OVERRUN4:1; /* FIFO 4 OVERRUN Flag */ - uint32_t FIFO_OVERFLOW4:1; /* FIFO 4 OVERFLOW Flag */ - uint32_t FIFO_EMPTY4:1; /* FIFO 4 EMPTY Flag */ - uint32_t FIFO_FULL4:1; /* FIFO 4 FULL Flag */ - uint32_t FIFO_OVERRUN3:1; /* FIFO 3 OVERRUN Flag */ - uint32_t FIFO_OVERFLOW3:1; /* FIFO 3 OVERFLOW Flag */ - uint32_t FIFO_EMPTY3:1; /* FIFO 3 EMPTY Flag */ - uint32_t FIFO_FULL3:1; /* FIFO 3 FULL Flag */ - uint32_t FIFO_OVERRUN2:1; /* FIFO 2 OVERRUN Flag */ - uint32_t FIFO_OVERFLOW2:1; /* FIFO 2 OVERFLOW Flag */ - uint32_t FIFO_EMPTY2:1; /* FIFO 2 EMPTY Flag */ - uint32_t FIFO_FULL2:1; /* FIFO 2 FULL Flag */ - uint32_t FIFO_OVERRUN1:1; /* FIFO 1 OVERRUN Flag */ - uint32_t FIFO_OVERFLOW1:1; /* FIFO 1 OVERFLOW Flag */ - uint32_t FIFO_EMPTY1:1; /* FIFO 1 EMPTY Flag */ - uint32_t FIFO_FULL1:1; /* FIFO 1 FULL Flag */ - uint32_t FIFO_OVERRUN0:1; /* FIFO 0 OVERRUN Flag */ - uint32_t FIFO_OVERFLOW0:1; /* FIFO 0 OVERFLOW Flag */ - uint32_t FIFO_EMPTY0:1; /* FIFO 0 EMPTY Flag */ - uint32_t FIFO_FULL0:1; /* FIFO 0 FULL Flag */ - } B; - } CTU_STS_32B_tag; - - - /* Register layout for all registers FR... */ - - typedef union { /* FIFO Right Aligned register */ - uint32_t R; - struct { - uint32_t:11; - uint32_t ADC:1; /* ADC Unit */ - uint32_t N_CH:4; /* Number Channel */ - uint32_t:4; - uint32_t DATA:12; /* Data Fifo */ - } B; - } CTU_FR_32B_tag; - - - /* Register layout for all registers FL... */ - - typedef union { /* FIFO Left Aligned register */ - uint32_t R; - struct { - uint32_t:11; - uint32_t ADC:1; /* ADC Unit */ - uint32_t N_CH:4; /* Number Channel */ - uint32_t:1; - uint32_t DATA:12; /* Data Fifo */ - uint32_t:3; - } B; - } CTU_FL_32B_tag; - - typedef union { /* CTU Error Flag Register */ - uint16_t R; - struct { - uint16_t:3; - uint16_t CS:1; /* Counter Status */ - uint16_t ET_OE:1; /* ExtTrigger Generation Overrun */ - uint16_t ERR_CMP:1; /* Set if counter reaches TGSCCR register */ - uint16_t T4_OE:1; /* Timer4 Generation Overrun */ - uint16_t T3_OE:1; /* Timer3 Generation Overrun */ - uint16_t T2_OE:1; /* Timer2 Generation Overrun */ - uint16_t T1_OE:1; /* Timer1 Generation Overrun */ -#ifndef USE_FIELD_ALIASES_CTU - uint16_t ADC_OE:1; /* ADC Command Generation Overrun */ -#else - uint16_t ADCOE:1; /* ADC Command Generation Overrun */ -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t TGS_OSM:1; /* TGS Overrun */ -#else - uint16_t TGSOSM:1; /* TGS Overrun */ -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t MRS_O:1; /* MRS Overrun */ -#else - uint16_t MRSO:1; /* TGS Overrun */ -#endif - uint16_t ICE:1; /* Invalid Command Error */ -#ifndef USE_FIELD_ALIASES_CTU - uint16_t SM_TO:1; /* Trigger Overrun */ -#else - uint16_t SMTO:1; /* Trigger Overrun */ -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t MRS_RE:1; /* MRS Reload Error */ -#else - uint16_t MRSRE:1; /* MRS Reload Error */ -#endif - } B; - } CTU_CTUEFR_16B_tag; - - typedef union { /* CTU Interrupt Flag Register */ - uint16_t R; - struct { - uint16_t:4; - uint16_t S_E_B:1; /* Slice time OK */ - uint16_t S_E_A:1; /* Slice time OK */ -#ifndef USE_FIELD_ALIASES_CTU - uint16_t ADC_I:1; /* ADC Command Interrupt Flag */ -#else - uint16_t ADC:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T7_I:1; /* Trigger 7 Interrupt Flag */ -#else - uint16_t T7:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T6_I:1; /* Trigger 6 Interrupt Flag */ -#else - uint16_t T6:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T5_I:1; /* Trigger 5 Interrupt Flag */ -#else - uint16_t T5:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T4_I:1; /* Trigger 4 Interrupt Flag */ -#else - uint16_t T4:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T3_I:1; /* Trigger 3 Interrupt Flag */ -#else - uint16_t T3:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T2_I:1; /* Trigger 2 Interrupt Flag */ -#else - uint16_t T2:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T1_I:1; /* Trigger 1 Interrupt Flag */ -#else - uint16_t T1:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T0_I:1; /* Trigger 0 Interrupt Flag */ -#else - uint16_t T0:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t MRS_I:1; /* MRS Interrupt Flag */ -#else - uint16_t MRS:1; -#endif - } B; - } CTU_CTUIFR_16B_tag; - - typedef union { /* CTU Interrupt/DMA Register */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T7_I:1; /* Trigger 7 Interrupt Enable */ -#else - uint16_t T7IE:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T6_I:1; /* Trigger 6 Interrupt Enable */ -#else - uint16_t T6IE:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T5_I:1; /* Trigger 5 Interrupt Enable */ -#else - uint16_t T5IE:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T4_I:1; /* Trigger 4 Interrupt Enable */ -#else - uint16_t T4IE:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T3_I:1; /* Trigger 3 Interrupt Enable */ -#else - uint16_t T3IE:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T2_I:1; /* Trigger 2 Interrupt Enable */ -#else - uint16_t T2IE:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T1_I:1; /* Trigger 1 Interrupt Enable */ -#else - uint16_t T1IE:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T0_I:1; /* Trigger 0 Interrupt Enable */ -#else - uint16_t T0IE:1; -#endif - uint16_t:2; - uint16_t SAF_CNT_B_EN:1; /* Conversion time counter enabled */ - uint16_t SAF_CNT_A_EN:1; /* Conversion time counter enabled */ - uint16_t DMA_DE:1; /* DMA and gre bit */ -#ifndef USE_FIELD_ALIASES_CTU - uint16_t MRS_DMAE:1; /* DMA Transfer Enable */ -#else - uint16_t MRSDMAE:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t MRS_IE:1; /* MRS Interrupt Enable */ -#else - uint16_t MRSIE:1; -#endif - uint16_t IEE:1; /* Interrupt Error Enable */ - } B; - } CTU_CTUIR_16B_tag; - - typedef union { /* Control On-Time Register */ - uint16_t R; - struct { - uint16_t:8; -#ifndef USE_FIELD_ALIASES_CTU - uint16_t COTR_COTR:8; /* Control On-Time Register and Guard Time */ -#else - uint16_t COTR:8; -#endif - } B; - } CTU_COTR_16B_tag; - - typedef union { /* CTU Control Register */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T7_SG:1; /* Trigger 7 Software Generated */ -#else - uint16_t T7SG:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T6_SG:1; /* Trigger 6 Software Generated */ -#else - uint16_t T6SG:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T5_SG:1; /* Trigger 5 Software Generated */ -#else - uint16_t T5SG:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T4_SG:1; /* Trigger 4 Software Generated */ -#else - uint16_t T4SG:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T3_SG:1; /* Trigger 3 Software Generated */ -#else - uint16_t T3SG:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T2_SG:1; /* Trigger 2 Software Generated */ -#else - uint16_t T2SG:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T1_SG:1; /* Trigger 1 Software Generated */ -#else - uint16_t T1SG:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t T0_SG:1; /* Trigger 0 Software Generated */ -#else - uint16_t T0SG:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t CTU_ADC_RESET:1; /* CTU ADC State Machine Reset */ -#else - uint16_t CTUADCRESET:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t CTU_ODIS:1; /* CTU Output Disable */ -#else - uint16_t CTUODIS:1; -#endif -#ifndef USE_FIELD_ALIASES_CTU - uint16_t FILTER_EN:1; /* Synchronize Filter Register value */ -#else - uint16_t FILTERENABLE:1; -#endif - uint16_t CGRE:1; /* Clear GRE */ - uint16_t FGRE:1; /* GRE Flag */ -#ifndef USE_FIELD_ALIASES_CTU - uint16_t MRS_SG:1; /* MRS Software Generated */ -#else - uint16_t MRSSG:1; -#endif - uint16_t GRE:1; /* General Reload Enable */ -#ifndef USE_FIELD_ALIASES_CTU - uint16_t TGSISR_RE:1; /* TGSISR Reload Enable */ -#else - uint16_t TGSISRRE:1; -#endif - } B; - } CTU_CTUCR_16B_tag; - - typedef union { /* CTU Digital Filter Register */ - uint16_t R; - struct { - uint16_t:8; -#ifndef USE_FIELD_ALIASES_CTU - uint16_t FILTER_VALUE:8; /* Filter Value */ -#else - uint16_t FILTERVALUE:8; /* deprecated name - please avoid */ -#endif - } B; - } CTU_FILTER_16B_tag; - - typedef union { /* CTU Expected A Value Register */ - uint16_t R; - struct { - uint16_t EXPECTED_A_VALUE:16; /* Expected A Value */ - } B; - } CTU_EXPECTED_A_16B_tag; - - typedef union { /* CTU Expected B Value Register */ - uint16_t R; - struct { - uint16_t EXPECTED_B_VALUE:16; /* Expected B Value */ - } B; - } CTU_EXPECTED_B_16B_tag; - - typedef union { /* CTU Counter Range Register */ - uint16_t R; - struct { - uint16_t:8; - uint16_t CNT_RANGE_VALUE:8; /* Counter Range Value */ - } B; - } CTU_CNT_RANGE_16B_tag; - - - /* Register layout for generated register(s) FRA... */ - - typedef union { /* */ - uint32_t R; - } CTU_FRA_32B_tag; - - - /* Register layout for generated register(s) FLA... */ - - typedef union { /* */ - uint32_t R; - } CTU_FLA_32B_tag; - - - - typedef struct CTU_struct_tag { /* start of CTU_tag */ - /* Trigger Generator Subunit Input Selection register */ - CTU_TGSISR_32B_tag TGSISR; /* offset: 0x0000 size: 32 bit */ - /* Trigger Generator Subunit Control Register */ - CTU_TGSCR_16B_tag TGSCR; /* offset: 0x0004 size: 16 bit */ - union { - CTU_TCR_16B_tag TCR[8]; /* offset: 0x0006 (0x0002 x 8) */ - - struct { - CTU_TCR_16B_tag T0CR; /* offset: 0x0006 size: 16 bit */ - CTU_TCR_16B_tag T1CR; /* offset: 0x0008 size: 16 bit */ - CTU_TCR_16B_tag T2CR; /* offset: 0x000A size: 16 bit */ - CTU_TCR_16B_tag T3CR; /* offset: 0x000C size: 16 bit */ - CTU_TCR_16B_tag T4CR; /* offset: 0x000E size: 16 bit */ - CTU_TCR_16B_tag T5CR; /* offset: 0x0010 size: 16 bit */ - CTU_TCR_16B_tag T6CR; /* offset: 0x0012 size: 16 bit */ - CTU_TCR_16B_tag T7CR; /* offset: 0x0014 size: 16 bit */ - }; - - }; - /* TGS Counter Compare Register */ - CTU_TGSCCR_16B_tag TGSCCR; /* offset: 0x0016 size: 16 bit */ - /* TGS Counter Reload Register */ - CTU_TGSCRR_16B_tag TGSCRR; /* offset: 0x0018 size: 16 bit */ - int8_t CTU_reserved_001A[2]; - /* Commands List Control Register 1 */ - CTU_CLCR1_32B_tag CLCR1; /* offset: 0x001C size: 32 bit */ - /* Commands List Control Register 2 */ - CTU_CLCR2_32B_tag CLCR2; /* offset: 0x0020 size: 32 bit */ - /* Trigger Handler Control Register 1 */ - CTU_THCR1_32B_tag THCR1; /* offset: 0x0024 size: 32 bit */ - /* Trigger Handler Control Register 2 */ - CTU_THCR2_32B_tag THCR2; /* offset: 0x0028 size: 32 bit */ - union { - /* Command List Register. View: BIT13, BIT9 */ - CTU_CLR_SCM_16B_tag CLR[24]; /* offset: 0x002C (0x0002 x 24) */ /* deprecated name - please avoid */ - - /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ - CTU_CLR_SCM_16B_tag CLR_SCM[24]; /* offset: 0x002C (0x0002 x 24) */ - - /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ - CTU_CLR_DCM_16B_tag CLR_DCM[24]; /* offset: 0x002C (0x0002 x 24) */ - - struct { - /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ - CTU_CLR_SCM_16B_tag CLR_SCM1; /* offset: 0x002C size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM2; /* offset: 0x002E size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM3; /* offset: 0x0030 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM4; /* offset: 0x0032 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM5; /* offset: 0x0034 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM6; /* offset: 0x0036 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM7; /* offset: 0x0038 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM8; /* offset: 0x003A size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM9; /* offset: 0x003C size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM10; /* offset: 0x003E size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM11; /* offset: 0x0040 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM12; /* offset: 0x0042 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM13; /* offset: 0x0044 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM14; /* offset: 0x0046 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM15; /* offset: 0x0048 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM16; /* offset: 0x004A size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM17; /* offset: 0x004C size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM18; /* offset: 0x004E size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM19; /* offset: 0x0050 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM20; /* offset: 0x0052 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM21; /* offset: 0x0054 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM22; /* offset: 0x0056 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM23; /* offset: 0x0058 size: 16 bit */ - CTU_CLR_SCM_16B_tag CLR_SCM24; /* offset: 0x005A size: 16 bit */ - }; - - struct { - /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ - CTU_CLR_DCM_16B_tag CLR_DCM1; /* offset: 0x002C size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM2; /* offset: 0x002E size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM3; /* offset: 0x0030 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM4; /* offset: 0x0032 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM5; /* offset: 0x0034 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM6; /* offset: 0x0036 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM7; /* offset: 0x0038 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM8; /* offset: 0x003A size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM9; /* offset: 0x003C size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM10; /* offset: 0x003E size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM11; /* offset: 0x0040 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM12; /* offset: 0x0042 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM13; /* offset: 0x0044 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM14; /* offset: 0x0046 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM15; /* offset: 0x0048 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM16; /* offset: 0x004A size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM17; /* offset: 0x004C size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM18; /* offset: 0x004E size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM19; /* offset: 0x0050 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM20; /* offset: 0x0052 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM21; /* offset: 0x0054 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM22; /* offset: 0x0056 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM23; /* offset: 0x0058 size: 16 bit */ - CTU_CLR_DCM_16B_tag CLR_DCM24; /* offset: 0x005A size: 16 bit */ - }; - - }; - int8_t CTU_reserved_005C[16]; - /* Control Register */ - CTU_CR_16B_tag CR; /* offset: 0x006C size: 16 bit */ - int8_t CTU_reserved_006E[2]; - /* Control Register FIFO */ - CTU_FCR_32B_tag FCR; /* offset: 0x0070 size: 32 bit */ - /* Threshold 1 Register */ - CTU_TH1_32B_tag TH1; /* offset: 0x0074 size: 32 bit */ - /* Threshold 2 Register */ - CTU_TH2_32B_tag TH2; /* offset: 0x0078 size: 32 bit */ - union { - /* Status Register */ - CTU_STS_32B_tag STS; /* offset: 0x007C size: 32 bit */ - - CTU_STS_32B_tag STATUS; /* deprecated - please avoid */ - - }; - union { - CTU_FRA_32B_tag FRA[8]; /* offset: 0x0080 (0x0004 x 8) */ - - /* FIFO Right Aligned register */ - CTU_FR_32B_tag FR[8]; /* offset: 0x0080 (0x0004 x 8) */ - - struct { - /* FIFO Right Aligned register */ - CTU_FR_32B_tag FR0; /* offset: 0x0080 size: 32 bit */ - CTU_FR_32B_tag FR1; /* offset: 0x0084 size: 32 bit */ - CTU_FR_32B_tag FR2; /* offset: 0x0088 size: 32 bit */ - CTU_FR_32B_tag FR3; /* offset: 0x008C size: 32 bit */ - CTU_FR_32B_tag FR4; /* offset: 0x0090 size: 32 bit */ - CTU_FR_32B_tag FR5; /* offset: 0x0094 size: 32 bit */ - CTU_FR_32B_tag FR6; /* offset: 0x0098 size: 32 bit */ - CTU_FR_32B_tag FR7; /* offset: 0x009C size: 32 bit */ - }; - - }; - union { - CTU_FLA_32B_tag FLA[8]; /* offset: 0x00A0 (0x0004 x 8) */ - - /* FIFO Left Aligned register */ - CTU_FL_32B_tag FL[8]; /* offset: 0x00A0 (0x0004 x 8) */ - - struct { - /* FIFO Left Aligned register */ - CTU_FL_32B_tag FL0; /* offset: 0x00A0 size: 32 bit */ - CTU_FL_32B_tag FL1; /* offset: 0x00A4 size: 32 bit */ - CTU_FL_32B_tag FL2; /* offset: 0x00A8 size: 32 bit */ - CTU_FL_32B_tag FL3; /* offset: 0x00AC size: 32 bit */ - CTU_FL_32B_tag FL4; /* offset: 0x00B0 size: 32 bit */ - CTU_FL_32B_tag FL5; /* offset: 0x00B4 size: 32 bit */ - CTU_FL_32B_tag FL6; /* offset: 0x00B8 size: 32 bit */ - CTU_FL_32B_tag FL7; /* offset: 0x00BC size: 32 bit */ - }; - - }; - /* CTU Error Flag Register */ - CTU_CTUEFR_16B_tag CTUEFR; /* offset: 0x00C0 size: 16 bit */ - /* CTU Interrupt Flag Register */ - CTU_CTUIFR_16B_tag CTUIFR; /* offset: 0x00C2 size: 16 bit */ - /* CTU Interrupt/DMA Register */ - CTU_CTUIR_16B_tag CTUIR; /* offset: 0x00C4 size: 16 bit */ - /* Control On-Time Register */ - CTU_COTR_16B_tag COTR; /* offset: 0x00C6 size: 16 bit */ - /* CTU Control Register */ - CTU_CTUCR_16B_tag CTUCR; /* offset: 0x00C8 size: 16 bit */ - union { - /* CTU Digital Filter Register */ - CTU_FILTER_16B_tag FILTER; /* offset: 0x00CA size: 16 bit */ - - CTU_FILTER_16B_tag CTUFILTER; /* deprecated - please avoid */ - - }; - /* CTU Expected A Value Register */ - CTU_EXPECTED_A_16B_tag EXPECTED_A; /* offset: 0x00CC size: 16 bit */ - - /* CTU Expected B Value Register */ - CTU_EXPECTED_B_16B_tag EXPECTED_B; /* offset: 0x00CE size: 16 bit */ - /* CTU Counter Range Register */ - CTU_CNT_RANGE_16B_tag CNT_RANGE; /* offset: 0x00D0 size: 16 bit */ - } CTU_tag; - - -#define CTU (*(volatile CTU_tag *) 0xFFE0C000UL) - - - -/****************************************************************/ -/* */ -/* Module: mcTIMER */ -/* */ -/****************************************************************/ - - - /* Register layout for all registers COMP1... */ - - typedef union { /* Compare Register 1 */ - uint16_t R; - struct { - uint16_t COMP1:16; /* deprecated definition -- do not use */ - } B; - } mcTIMER_COMP1_16B_tag; - - - /* Register layout for all registers COMP2... */ - - typedef union { /* Compare Register 2 */ - uint16_t R; - struct { - uint16_t COMP2:16; /* deprecated definition -- do not use */ - } B; - } mcTIMER_COMP2_16B_tag; - - - /* Register layout for all registers CAPT1... */ - - typedef union { /* Capture Register 1 */ - uint16_t R; - struct { - uint16_t CAPT1:16; /* deprecated definition -- do not use */ - } B; - } mcTIMER_CAPT1_16B_tag; - - - /* Register layout for all registers CAPT2... */ - - typedef union { /* Capture Register 2 */ - uint16_t R; - struct { - uint16_t CAPT2:16; /* deprecated definition -- do not use */ - } B; - } mcTIMER_CAPT2_16B_tag; - - - /* Register layout for all registers LOAD... */ - - typedef union { /* Load Register */ - uint16_t R; - struct { - uint16_t LOAD:16; /* deprecated definition -- do not use */ - } B; - } mcTIMER_LOAD_16B_tag; - - - /* Register layout for all registers HOLD... */ - - typedef union { /* Hold Register */ - uint16_t R; - struct { - uint16_t HOLD:16; /* deprecated definition -- do not use */ - } B; - } mcTIMER_HOLD_16B_tag; - - - /* Register layout for all registers CNTR... */ - - typedef union { /* Counter Register */ - uint16_t R; - struct { - uint16_t CNTR:16; /* deprecated definition -- do not use */ - } B; - } mcTIMER_CNTR_16B_tag; - - - /* Register layout for all registers CTRL1... */ - - typedef union { /* Control Register */ - uint16_t R; - struct { - uint16_t CNTMODE:3; /* Count Mode */ - uint16_t PRISRC:5; /* Primary Count Source */ - uint16_t ONCE:1; /* Count Once */ - uint16_t LENGTH:1; /* Count Length */ - uint16_t DIR:1; /* Count Direction */ - uint16_t SECSRC:5; /* Secondary Count Source */ - } B; - } mcTIMER_CTRL1_16B_tag; - - - /* Register layout for all registers CTRL2... */ - - typedef union { /* Control Register 2 */ - uint16_t R; - struct { - uint16_t OEN:1; /* Output Enable */ - uint16_t RDNT:1; /* Redundant Channel Enable */ - uint16_t INPUT:1; /* External Input Signal */ - uint16_t VAL:1; /* Forced OFLAG Value */ - uint16_t FORCE:1; /* Force the OFLAG output */ - uint16_t COFRC:1; /* Co-channel OFLAG Force */ - uint16_t COINIT:2; /* Co-channel Initialization */ - uint16_t SIPS:1; /* Secondary Source Input Polarity Select */ - uint16_t PIPS:1; /* Primary Source Input Polarity Select */ - uint16_t OPS:1; /* Output Polarity Select */ - uint16_t MSTR:1; /* Master Mode */ - uint16_t OUTMODE:4; /* Output Mode */ - } B; - } mcTIMER_CTRL2_16B_tag; - - - /* Register layout for all registers CTRL3... */ - - typedef union { /* Control Register 3 */ - uint16_t R; - struct { - uint16_t STPEN:1; /* Stop Action Enable */ - uint16_t ROC:2; /* Reload On Capture */ - uint16_t FMODE:1; /* Fault Safing Mode */ - uint16_t FDIS:4; /* Fault Disable Mask */ - uint16_t C2FCNT:3; /* CAPT2 FIFO Word Count */ - uint16_t C1FCNT:3; /* CAPT1 FIFO Word Count */ - uint16_t DBGEN:2; /* Debug Actions Enable */ - } B; - } mcTIMER_CTRL3_16B_tag; - - - /* Register layout for all registers STS... */ - - typedef union { /* Status Register */ - uint16_t R; - struct { - uint16_t:6; - uint16_t WDF:1; /* Watchdog Time-out Flag */ - uint16_t RCF:1; /* Redundant Channel Flag */ - uint16_t ICF2:1; /* Input Capture 2 Flag */ - uint16_t ICF1:1; /* Input Capture 1 Flag */ - uint16_t IEHF:1; /* Input Edge High Flag */ - uint16_t IELF:1; /* Input Edge Low Flag */ - uint16_t TOF:1; /* Timer Overflow Flag */ - uint16_t TCF2:1; /* Timer Compare 2 Flag */ - uint16_t TCF1:1; /* Timer Compare 1 Flag */ - uint16_t TCF:1; /* Timer Compare Flag */ - } B; - } mcTIMER_STS_16B_tag; - - - /* Register layout for all registers INTDMA... */ - - typedef union { /* Interrupt and DMA Enable Register */ - uint16_t R; - struct { - uint16_t ICF2DE:1; /* Input Capture 2 Flag DMA Enable */ - uint16_t ICF1DE:1; /* Input Capture 1 Flag DMA Enable */ - uint16_t CMPLD2DE:1; /* Comparator Load Register 2 Flag DMA Enable */ - uint16_t CMPLD1DE:1; /* Comparator Load Register 1 Flag DMA Enable */ - uint16_t:2; - uint16_t WDFIE:1; /* Watchdog Flag Interrupt Enable */ - uint16_t RCFIE:1; /* Redundant Channel Flag Interrupt Enable */ - uint16_t ICF2IE:1; /* Input Capture 2 Flag Interrupt Enable */ - uint16_t ICF1IE:1; /* Input Capture 1 Flag Interrupt Enable */ - uint16_t IEHFIE:1; /* Input Edge High Flag Interrupt Enable */ - uint16_t IELFIE:1; /* Input Edge Low Flag Interrupt Enable */ - uint16_t TOFIE:1; /* Timer Overflow Flag Interrupt Enable */ - uint16_t TCF2IE:1; /* Timer Compare 2 Flag Interrupt Enable */ - uint16_t TCF1IE:1; /* Timer Compare 1 Flag Interrupt Enable */ - uint16_t TCFIE:1; /* Timer Compare Flag Interrupt Enable */ - } B; - } mcTIMER_INTDMA_16B_tag; - - - /* Register layout for all registers CMPLD1... */ - - typedef union { /* Comparator Load Register 1 */ - uint16_t R; - struct { - uint16_t CMPLD1:16; /* deprecated definition -- do not use */ - } B; - } mcTIMER_CMPLD1_16B_tag; - - - /* Register layout for all registers CMPLD2... */ - - typedef union { /* Comparator Load Register 2 */ - uint16_t R; - struct { - uint16_t CMPLD2:16; /* deprecated definition -- do not use */ - } B; - } mcTIMER_CMPLD2_16B_tag; - - - /* Register layout for all registers CCCTRL... */ - - typedef union { /* Compare and Capture Control Register */ - uint16_t R; - struct { - uint16_t CLC2:3; /* Compare Load Control 2 */ - uint16_t CLC1:3; /* Compare Load Control 1 */ - uint16_t CMPMODE:2; /* Compare Mode */ - uint16_t CPT2MODE:2; /* Capture 2 Mode Control */ - uint16_t CPT1MODE:2; /* Capture 1 Mode Control */ - uint16_t CFWM:2; /* Capture FIFO Water Mark */ - uint16_t ONESHOT:1; /* One Shot Capture Mode */ - uint16_t ARM:1; /* Arm Capture */ - } B; - } mcTIMER_CCCTRL_16B_tag; - - - /* Register layout for all registers FILT... */ - - typedef union { /* Input Filter Register */ - uint16_t R; - struct { - uint16_t:5; -#ifndef USE_FIELD_ALIASES_mcTIMER - uint16_t FILT_CNT:3; /* Input Filter Sample Count */ -#else - uint16_t FILTCNT:3; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcTIMER - uint16_t FILT_PER:8; /* Input Filter Sample Period */ -#else - uint16_t FILTPER:8; /* deprecated name - please avoid */ -#endif - } B; - } mcTIMER_FILT_16B_tag; - - typedef union { /* Watchdog Time-out Register */ - uint16_t R; - struct { - uint16_t WDTOL:16; /* deprecated definition -- do not use */ - } B; - } mcTIMER_WDTOL_16B_tag; - - typedef union { /* Watchdog Time-out Register */ - uint16_t R; - struct { - uint16_t WDTOH:16; /* deprecated definition -- do not use */ - } B; - } mcTIMER_WDTOH_16B_tag; - - typedef union { /* Fault Control Register */ - uint16_t R; - struct { - uint16_t:3; - uint16_t FTEST:1; /* Fault Test */ - uint16_t FIE:4; /* Fault Interrupt Enable */ - uint16_t:4; - uint16_t FLVL:4; /* Fault Active Logic Level */ - } B; - } mcTIMER_FCTRL_16B_tag; - - typedef union { /* Fault Status Register */ - uint16_t R; - struct { - uint16_t:4; - uint16_t FFPIN:4; /* Filtered Fault Pin */ - uint16_t:4; - uint16_t FFLAG:4; /* Fault Flag */ - } B; - } mcTIMER_FSTS_16B_tag; - - typedef union { /* Fault Filter Registers */ - uint16_t R; - struct { - uint16_t:5; -#ifndef USE_FIELD_ALIASES_mcTIMER - uint16_t FFPIN:3; /* Fault Filter Sample Count */ -#else - uint16_t FFILTCNT:3; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcTIMER - uint16_t FFILT_PER:8; /* Fault Filter Sample Period */ -#else - uint16_t FFILTPER:8; /* deprecated name - please avoid */ -#endif - } B; - } mcTIMER_FFILT_16B_tag; - - typedef union { /* Channel Enable Registers */ - uint16_t R; - struct { - uint16_t:8; - uint16_t ENBL:8; /* Timer Channel Enable */ - } B; - } mcTIMER_ENBL_16B_tag; - - typedef union { /* DMA Request 0 Select Registers */ - uint16_t R; - struct { - uint16_t:11; - uint16_t DREQ0V:5; /* DMA Request Select */ - } B; - } mcTIMER_DREQ0_16B_tag; - - typedef union { /* DMA Request 1 Select Registers */ - uint16_t R; - struct { - uint16_t:11; - uint16_t DREQ1V:5; /* DMA Request Select */ - } B; - } mcTIMER_DREQ1_16B_tag; - - typedef union { /* DMA Request 2 Select Registers */ - uint16_t R; - struct { - uint16_t:11; - uint16_t DREQ2V:5; /* DMA Request Select */ - } B; - } mcTIMER_DREQ2_16B_tag; - - typedef union { /* DMA Request 3 Select Registers */ - uint16_t R; - struct { - uint16_t:11; - uint16_t DREQ3V:5; /* DMA Request Select */ - } B; - } mcTIMER_DREQ3_16B_tag; - - - /* Register layout for generated register(s) DREQ... */ - - typedef union { /* */ - uint16_t R; - } mcTIMER_DREQ_16B_tag; - - - typedef struct mcTIMER_CHANNEL_struct_tag { - - /* Compare Register 1 */ - mcTIMER_COMP1_16B_tag COMP1; /* relative offset: 0x0000 */ - /* Compare Register 2 */ - mcTIMER_COMP2_16B_tag COMP2; /* relative offset: 0x0002 */ - /* Capture Register 1 */ - mcTIMER_CAPT1_16B_tag CAPT1; /* relative offset: 0x0004 */ - /* Capture Register 2 */ - mcTIMER_CAPT2_16B_tag CAPT2; /* relative offset: 0x0006 */ - /* Load Register */ - mcTIMER_LOAD_16B_tag LOAD; /* relative offset: 0x0008 */ - /* Hold Register */ - mcTIMER_HOLD_16B_tag HOLD; /* relative offset: 0x000A */ - /* Counter Register */ - mcTIMER_CNTR_16B_tag CNTR; /* relative offset: 0x000C */ - union { - /* Control Register */ - mcTIMER_CTRL1_16B_tag CTRL1; /* relative offset: 0x000E */ - mcTIMER_CTRL1_16B_tag CTRL; /* deprecated - please avoid */ - }; - /* Control Register 2 */ - mcTIMER_CTRL2_16B_tag CTRL2; /* relative offset: 0x0010 */ - /* Control Register 3 */ - mcTIMER_CTRL3_16B_tag CTRL3; /* relative offset: 0x0012 */ - /* Status Register */ - mcTIMER_STS_16B_tag STS; /* relative offset: 0x0014 */ - /* Interrupt and DMA Enable Register */ - mcTIMER_INTDMA_16B_tag INTDMA; /* relative offset: 0x0016 */ - /* Comparator Load Register 1 */ - mcTIMER_CMPLD1_16B_tag CMPLD1; /* relative offset: 0x0018 */ - /* Comparator Load Register 2 */ - mcTIMER_CMPLD2_16B_tag CMPLD2; /* relative offset: 0x001A */ - /* Compare and Capture Control Register */ - mcTIMER_CCCTRL_16B_tag CCCTRL; /* relative offset: 0x001C */ - /* Input Filter Register */ - mcTIMER_FILT_16B_tag FILT; /* relative offset: 0x001E */ - - } mcTIMER_CHANNEL_tag; - - - typedef struct mcTIMER_struct_tag { /* start of mcTIMER_tag */ - union { - /* Register set CHANNEL */ - mcTIMER_CHANNEL_tag CHANNEL[6]; /* offset: 0x0000 (0x0020 x 6) */ - - struct { - /* Compare Register 1 */ - mcTIMER_COMP1_16B_tag COMP10; /* offset: 0x0000 size: 16 bit */ - /* Compare Register 2 */ - mcTIMER_COMP2_16B_tag COMP20; /* offset: 0x0002 size: 16 bit */ - /* Capture Register 1 */ - mcTIMER_CAPT1_16B_tag CAPT10; /* offset: 0x0004 size: 16 bit */ - /* Capture Register 2 */ - mcTIMER_CAPT2_16B_tag CAPT20; /* offset: 0x0006 size: 16 bit */ - /* Load Register */ - mcTIMER_LOAD_16B_tag LOAD0; /* offset: 0x0008 size: 16 bit */ - /* Hold Register */ - mcTIMER_HOLD_16B_tag HOLD0; /* offset: 0x000A size: 16 bit */ - /* Counter Register */ - mcTIMER_CNTR_16B_tag CNTR0; /* offset: 0x000C size: 16 bit */ - /* Control Register */ - mcTIMER_CTRL1_16B_tag CTRL10; /* offset: 0x000E size: 16 bit */ - /* Control Register 2 */ - mcTIMER_CTRL2_16B_tag CTRL20; /* offset: 0x0010 size: 16 bit */ - /* Control Register 3 */ - mcTIMER_CTRL3_16B_tag CTRL30; /* offset: 0x0012 size: 16 bit */ - /* Status Register */ - mcTIMER_STS_16B_tag STS0; /* offset: 0x0014 size: 16 bit */ - /* Interrupt and DMA Enable Register */ - mcTIMER_INTDMA_16B_tag INTDMA0; /* offset: 0x0016 size: 16 bit */ - /* Comparator Load Register 1 */ - mcTIMER_CMPLD1_16B_tag CMPLD10; /* offset: 0x0018 size: 16 bit */ - /* Comparator Load Register 2 */ - mcTIMER_CMPLD2_16B_tag CMPLD20; /* offset: 0x001A size: 16 bit */ - /* Compare and Capture Control Register */ - mcTIMER_CCCTRL_16B_tag CCCTRL0; /* offset: 0x001C size: 16 bit */ - /* Input Filter Register */ - mcTIMER_FILT_16B_tag FILT0; /* offset: 0x001E size: 16 bit */ - /* Compare Register 1 */ - mcTIMER_COMP1_16B_tag COMP11; /* offset: 0x0020 size: 16 bit */ - /* Compare Register 2 */ - mcTIMER_COMP2_16B_tag COMP21; /* offset: 0x0022 size: 16 bit */ - /* Capture Register 1 */ - mcTIMER_CAPT1_16B_tag CAPT11; /* offset: 0x0024 size: 16 bit */ - /* Capture Register 2 */ - mcTIMER_CAPT2_16B_tag CAPT21; /* offset: 0x0026 size: 16 bit */ - /* Load Register */ - mcTIMER_LOAD_16B_tag LOAD1; /* offset: 0x0028 size: 16 bit */ - /* Hold Register */ - mcTIMER_HOLD_16B_tag HOLD1; /* offset: 0x002A size: 16 bit */ - /* Counter Register */ - mcTIMER_CNTR_16B_tag CNTR1; /* offset: 0x002C size: 16 bit */ - /* Control Register */ - mcTIMER_CTRL1_16B_tag CTRL11; /* offset: 0x002E size: 16 bit */ - /* Control Register 2 */ - mcTIMER_CTRL2_16B_tag CTRL21; /* offset: 0x0030 size: 16 bit */ - /* Control Register 3 */ - mcTIMER_CTRL3_16B_tag CTRL31; /* offset: 0x0032 size: 16 bit */ - /* Status Register */ - mcTIMER_STS_16B_tag STS1; /* offset: 0x0034 size: 16 bit */ - /* Interrupt and DMA Enable Register */ - mcTIMER_INTDMA_16B_tag INTDMA1; /* offset: 0x0036 size: 16 bit */ - /* Comparator Load Register 1 */ - mcTIMER_CMPLD1_16B_tag CMPLD11; /* offset: 0x0038 size: 16 bit */ - /* Comparator Load Register 2 */ - mcTIMER_CMPLD2_16B_tag CMPLD21; /* offset: 0x003A size: 16 bit */ - /* Compare and Capture Control Register */ - mcTIMER_CCCTRL_16B_tag CCCTRL1; /* offset: 0x003C size: 16 bit */ - /* Input Filter Register */ - mcTIMER_FILT_16B_tag FILT1; /* offset: 0x003E size: 16 bit */ - /* Compare Register 1 */ - mcTIMER_COMP1_16B_tag COMP12; /* offset: 0x0040 size: 16 bit */ - /* Compare Register 2 */ - mcTIMER_COMP2_16B_tag COMP22; /* offset: 0x0042 size: 16 bit */ - /* Capture Register 1 */ - mcTIMER_CAPT1_16B_tag CAPT12; /* offset: 0x0044 size: 16 bit */ - /* Capture Register 2 */ - mcTIMER_CAPT2_16B_tag CAPT22; /* offset: 0x0046 size: 16 bit */ - /* Load Register */ - mcTIMER_LOAD_16B_tag LOAD2; /* offset: 0x0048 size: 16 bit */ - /* Hold Register */ - mcTIMER_HOLD_16B_tag HOLD2; /* offset: 0x004A size: 16 bit */ - /* Counter Register */ - mcTIMER_CNTR_16B_tag CNTR2; /* offset: 0x004C size: 16 bit */ - /* Control Register */ - mcTIMER_CTRL1_16B_tag CTRL12; /* offset: 0x004E size: 16 bit */ - /* Control Register 2 */ - mcTIMER_CTRL2_16B_tag CTRL22; /* offset: 0x0050 size: 16 bit */ - /* Control Register 3 */ - mcTIMER_CTRL3_16B_tag CTRL32; /* offset: 0x0052 size: 16 bit */ - /* Status Register */ - mcTIMER_STS_16B_tag STS2; /* offset: 0x0054 size: 16 bit */ - /* Interrupt and DMA Enable Register */ - mcTIMER_INTDMA_16B_tag INTDMA2; /* offset: 0x0056 size: 16 bit */ - /* Comparator Load Register 1 */ - mcTIMER_CMPLD1_16B_tag CMPLD12; /* offset: 0x0058 size: 16 bit */ - /* Comparator Load Register 2 */ - mcTIMER_CMPLD2_16B_tag CMPLD22; /* offset: 0x005A size: 16 bit */ - /* Compare and Capture Control Register */ - mcTIMER_CCCTRL_16B_tag CCCTRL2; /* offset: 0x005C size: 16 bit */ - /* Input Filter Register */ - mcTIMER_FILT_16B_tag FILT2; /* offset: 0x005E size: 16 bit */ - /* Compare Register 1 */ - mcTIMER_COMP1_16B_tag COMP13; /* offset: 0x0060 size: 16 bit */ - /* Compare Register 2 */ - mcTIMER_COMP2_16B_tag COMP23; /* offset: 0x0062 size: 16 bit */ - /* Capture Register 1 */ - mcTIMER_CAPT1_16B_tag CAPT13; /* offset: 0x0064 size: 16 bit */ - /* Capture Register 2 */ - mcTIMER_CAPT2_16B_tag CAPT23; /* offset: 0x0066 size: 16 bit */ - /* Load Register */ - mcTIMER_LOAD_16B_tag LOAD3; /* offset: 0x0068 size: 16 bit */ - /* Hold Register */ - mcTIMER_HOLD_16B_tag HOLD3; /* offset: 0x006A size: 16 bit */ - /* Counter Register */ - mcTIMER_CNTR_16B_tag CNTR3; /* offset: 0x006C size: 16 bit */ - /* Control Register */ - mcTIMER_CTRL1_16B_tag CTRL13; /* offset: 0x006E size: 16 bit */ - /* Control Register 2 */ - mcTIMER_CTRL2_16B_tag CTRL23; /* offset: 0x0070 size: 16 bit */ - /* Control Register 3 */ - mcTIMER_CTRL3_16B_tag CTRL33; /* offset: 0x0072 size: 16 bit */ - /* Status Register */ - mcTIMER_STS_16B_tag STS3; /* offset: 0x0074 size: 16 bit */ - /* Interrupt and DMA Enable Register */ - mcTIMER_INTDMA_16B_tag INTDMA3; /* offset: 0x0076 size: 16 bit */ - /* Comparator Load Register 1 */ - mcTIMER_CMPLD1_16B_tag CMPLD13; /* offset: 0x0078 size: 16 bit */ - /* Comparator Load Register 2 */ - mcTIMER_CMPLD2_16B_tag CMPLD23; /* offset: 0x007A size: 16 bit */ - /* Compare and Capture Control Register */ - mcTIMER_CCCTRL_16B_tag CCCTRL3; /* offset: 0x007C size: 16 bit */ - /* Input Filter Register */ - mcTIMER_FILT_16B_tag FILT3; /* offset: 0x007E size: 16 bit */ - /* Compare Register 1 */ - mcTIMER_COMP1_16B_tag COMP14; /* offset: 0x0080 size: 16 bit */ - /* Compare Register 2 */ - mcTIMER_COMP2_16B_tag COMP24; /* offset: 0x0082 size: 16 bit */ - /* Capture Register 1 */ - mcTIMER_CAPT1_16B_tag CAPT14; /* offset: 0x0084 size: 16 bit */ - /* Capture Register 2 */ - mcTIMER_CAPT2_16B_tag CAPT24; /* offset: 0x0086 size: 16 bit */ - /* Load Register */ - mcTIMER_LOAD_16B_tag LOAD4; /* offset: 0x0088 size: 16 bit */ - /* Hold Register */ - mcTIMER_HOLD_16B_tag HOLD4; /* offset: 0x008A size: 16 bit */ - /* Counter Register */ - mcTIMER_CNTR_16B_tag CNTR4; /* offset: 0x008C size: 16 bit */ - /* Control Register */ - mcTIMER_CTRL1_16B_tag CTRL14; /* offset: 0x008E size: 16 bit */ - /* Control Register 2 */ - mcTIMER_CTRL2_16B_tag CTRL24; /* offset: 0x0090 size: 16 bit */ - /* Control Register 3 */ - mcTIMER_CTRL3_16B_tag CTRL34; /* offset: 0x0092 size: 16 bit */ - /* Status Register */ - mcTIMER_STS_16B_tag STS4; /* offset: 0x0094 size: 16 bit */ - /* Interrupt and DMA Enable Register */ - mcTIMER_INTDMA_16B_tag INTDMA4; /* offset: 0x0096 size: 16 bit */ - /* Comparator Load Register 1 */ - mcTIMER_CMPLD1_16B_tag CMPLD14; /* offset: 0x0098 size: 16 bit */ - /* Comparator Load Register 2 */ - mcTIMER_CMPLD2_16B_tag CMPLD24; /* offset: 0x009A size: 16 bit */ - /* Compare and Capture Control Register */ - mcTIMER_CCCTRL_16B_tag CCCTRL4; /* offset: 0x009C size: 16 bit */ - /* Input Filter Register */ - mcTIMER_FILT_16B_tag FILT4; /* offset: 0x009E size: 16 bit */ - /* Compare Register 1 */ - mcTIMER_COMP1_16B_tag COMP15; /* offset: 0x00A0 size: 16 bit */ - /* Compare Register 2 */ - mcTIMER_COMP2_16B_tag COMP25; /* offset: 0x00A2 size: 16 bit */ - /* Capture Register 1 */ - mcTIMER_CAPT1_16B_tag CAPT15; /* offset: 0x00A4 size: 16 bit */ - /* Capture Register 2 */ - mcTIMER_CAPT2_16B_tag CAPT25; /* offset: 0x00A6 size: 16 bit */ - /* Load Register */ - mcTIMER_LOAD_16B_tag LOAD5; /* offset: 0x00A8 size: 16 bit */ - /* Hold Register */ - mcTIMER_HOLD_16B_tag HOLD5; /* offset: 0x00AA size: 16 bit */ - /* Counter Register */ - mcTIMER_CNTR_16B_tag CNTR5; /* offset: 0x00AC size: 16 bit */ - /* Control Register */ - mcTIMER_CTRL1_16B_tag CTRL15; /* offset: 0x00AE size: 16 bit */ - /* Control Register 2 */ - mcTIMER_CTRL2_16B_tag CTRL25; /* offset: 0x00B0 size: 16 bit */ - /* Control Register 3 */ - mcTIMER_CTRL3_16B_tag CTRL35; /* offset: 0x00B2 size: 16 bit */ - /* Status Register */ - mcTIMER_STS_16B_tag STS5; /* offset: 0x00B4 size: 16 bit */ - /* Interrupt and DMA Enable Register */ - mcTIMER_INTDMA_16B_tag INTDMA5; /* offset: 0x00B6 size: 16 bit */ - /* Comparator Load Register 1 */ - mcTIMER_CMPLD1_16B_tag CMPLD15; /* offset: 0x00B8 size: 16 bit */ - /* Comparator Load Register 2 */ - mcTIMER_CMPLD2_16B_tag CMPLD25; /* offset: 0x00BA size: 16 bit */ - /* Compare and Capture Control Register */ - mcTIMER_CCCTRL_16B_tag CCCTRL5; /* offset: 0x00BC size: 16 bit */ - /* Input Filter Register */ - mcTIMER_FILT_16B_tag FILT5; /* offset: 0x00BE size: 16 bit */ - }; - - }; - int8_t mcTIMER_reserved_00C0[64]; - /* Watchdog Time-out Register */ - mcTIMER_WDTOL_16B_tag WDTOL; /* offset: 0x0100 size: 16 bit */ - /* Watchdog Time-out Register */ - mcTIMER_WDTOH_16B_tag WDTOH; /* offset: 0x0102 size: 16 bit */ - /* Fault Control Register */ - mcTIMER_FCTRL_16B_tag FCTRL; /* offset: 0x0104 size: 16 bit */ - /* Fault Status Register */ - mcTIMER_FSTS_16B_tag FSTS; /* offset: 0x0106 size: 16 bit */ - /* Fault Filter Registers */ - mcTIMER_FFILT_16B_tag FFILT; /* offset: 0x0108 size: 16 bit */ - int8_t mcTIMER_reserved_010A[2]; - /* Channel Enable Registers */ - mcTIMER_ENBL_16B_tag ENBL; /* offset: 0x010C size: 16 bit */ - int8_t mcTIMER_reserved_010E_C[2]; - union { - mcTIMER_DREQ_16B_tag DREQ[4]; /* offset: 0x0110 (0x0002 x 4) */ - - struct { - /* DMA Request 0 Select Registers */ - mcTIMER_DREQ0_16B_tag DREQ0; /* offset: 0x0110 size: 16 bit */ - /* DMA Request 1 Select Registers */ - mcTIMER_DREQ1_16B_tag DREQ1; /* offset: 0x0112 size: 16 bit */ - /* DMA Request 2 Select Registers */ - mcTIMER_DREQ2_16B_tag DREQ2; /* offset: 0x0114 size: 16 bit */ - /* DMA Request 3 Select Registers */ - mcTIMER_DREQ3_16B_tag DREQ3; /* offset: 0x0116 size: 16 bit */ - }; - - }; - } mcTIMER_tag; - - -#define mcTIMER0 (*(volatile mcTIMER_tag *) 0xFFE18000UL) -#define mcTIMER1 (*(volatile mcTIMER_tag *) 0xFFE1C000UL) -#define mcTIMER2 (*(volatile mcTIMER_tag *) 0xFFE20000UL) - - - -/****************************************************************/ -/* */ -/* Module: mcPWM */ -/* */ -/****************************************************************/ - - - /* Register layout for all registers CNT... */ - - typedef union { /* Counter Register */ - uint16_t R; - } mcPWM_CNT_16B_tag; - - - /* Register layout for all registers INIT... */ - - typedef union { /* Initial Counter Register */ - uint16_t R; - } mcPWM_INIT_16B_tag; - - - /* Register layout for all registers CTRL2... */ - - typedef union { /* Control 2 Register */ - uint16_t R; - struct { - uint16_t DBGEN:1; /* Debug Enable */ - uint16_t WAITEN:1; /* Wait Enable */ - uint16_t INDEP:1; /* Independent or Complementary Pair Operation */ -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t PWM23_INIT:1; /* PWM23 Initial Value */ -#else - uint16_t PWMA_INIT:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t PWM45_INIT:1; /* PWM23 Initial Value */ -#else - uint16_t PWMB_INIT:1; /* deprecated name - please avoid */ -#endif - uint16_t PWMX_INIT:1; /* PWMX Initial Value */ - uint16_t INIT_SEL:2; /* Initialization Control Select */ - uint16_t FRCEN:1; /* Force Initialization enable */ - uint16_t FORCE:1; /* Force Initialization */ - uint16_t FORCE_SEL:3; /* Force Source Select */ - uint16_t RELOAD_SEL:1; /* Reload Source Select */ - uint16_t CLK_SEL:2; /* Clock Source Select */ - } B; - } mcPWM_CTRL2_16B_tag; - - - /* Register layout for all registers CTRL1... */ - - typedef union { /* Control Register */ - uint16_t R; - struct { - uint16_t LDFQ:4; /* Load Frequency */ - uint16_t HALF:1; /* Half Cycle Reload */ - uint16_t FULL:1; /* Full Cycle Reload */ - uint16_t DT:2; /* Deadtime */ - uint16_t:1; - uint16_t PRSC:3; /* Prescaler */ - uint16_t:1; - uint16_t LDMOD:1; /* Load Mode Select */ - uint16_t:1; -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t DBL_EN:1; /* Double Switching Enable */ -#else - uint16_t DBLEN:1; /* deprecated name - please avoid */ -#endif - } B; - } mcPWM_CTRL1_16B_tag; - - - /* Register layout for all registers VAL_0... */ - - typedef union { /* Value Register 0 */ - uint16_t R; - } mcPWM_VAL_0_16B_tag; - - - /* Register layout for all registers VAL_1... */ - - typedef union { /* Value Register 1 */ - uint16_t R; - } mcPWM_VAL_1_16B_tag; - - - /* Register layout for all registers VAL_2... */ - - typedef union { /* Value Register 2 */ - uint16_t R; - } mcPWM_VAL_2_16B_tag; - - - /* Register layout for all registers VAL_3... */ - - typedef union { /* Value Register 3 */ - uint16_t R; - } mcPWM_VAL_3_16B_tag; - - - /* Register layout for all registers VAL_4... */ - - typedef union { /* Value Register 4 */ - uint16_t R; - } mcPWM_VAL_4_16B_tag; - - - /* Register layout for all registers VAL_5... */ - - typedef union { /* Value Register 5 */ - uint16_t R; - } mcPWM_VAL_5_16B_tag; - - /* Register layout for all registers OCTRL... */ - - typedef union { /* Output Control Register */ - uint16_t R; - struct { - uint16_t PWMA_IN:1; /* PWMA Input */ - uint16_t PWMB_IN:1; /* PWMB Input */ - uint16_t PWMX_IN:1; /* PWMX Input */ - uint16_t:2; - uint16_t POLA:1; /* PWMA Output Polarity */ - uint16_t POLB:1; /* PWMB Output Polarity */ - uint16_t POLX:1; /* PWMX Output Polarity */ - uint16_t:2; - uint16_t PWMAFS:2; /* PWMA Fault State */ - uint16_t PWMBFS:2; /* PWMB Fault State */ - uint16_t PWMXFS:2; /* PWMX Fault State */ - } B; - } mcPWM_OCTRL_16B_tag; - - - /* Register layout for all registers STS... */ - - typedef union { /* Status Register */ - uint16_t R; - struct { - uint16_t:1; - uint16_t RUF:1; /* Registers Updated Flag */ - uint16_t REF:1; /* Reload Error Flag */ - uint16_t RF:1; /* Reload Flag */ - uint16_t CFA1:1; /* Capture Flag A1 */ - uint16_t CFA0:1; /* Capture Flag A0 */ - uint16_t CFB1:1; /* Capture Flag B1 */ - uint16_t CFB0:1; /* Capture Flag B0 */ - uint16_t CFX1:1; /* Capture Flag X1 */ - uint16_t CFX0:1; /* Capture Flag X0 */ - uint16_t CMPF:6; /* Compare Flags */ - } B; - } mcPWM_STS_16B_tag; - - - /* Register layout for all registers INTEN... */ - - typedef union { /* Interrupt Enable Registers */ - uint16_t R; - struct { - uint16_t:2; - uint16_t REIE:1; /* Reload Error Interrupt Enable */ - uint16_t RIE:1; /* Reload Interrupt Enable */ - uint16_t CA1IE:1; /* Capture A1 Interrupt Enable */ - uint16_t CA0IE:1; /* Capture A0 Interrupt Enable */ - uint16_t CB1IE:1; /* Capture B1 Interrupt Enable */ - uint16_t CB0IE:1; /* Capture B0 Interrupt Enable */ - uint16_t CX1IE:1; /* Capture X1 Interrupt Enable */ - uint16_t CX0IE:1; /* Capture X0 Interrupt Enable */ - uint16_t CMPIE:6; /* Compare Interrupt Enables */ - } B; - } mcPWM_INTEN_16B_tag; - - - /* Register layout for all registers DMAEN... */ - - typedef union { /* DMA Enable Registers */ - uint16_t R; - struct { - uint16_t:6; - uint16_t VALDE:1; /* Value Register DMA Enable */ - uint16_t FAND:1; /* FIFO Watermark AND Control */ - uint16_t CAPTDE:2; /* Capture DMA Enable Source Select */ - uint16_t CA1DE:1; /* Capture A1 FIFO DMA Enable */ - uint16_t CA0DE:1; /* Capture A0 FIFO DMA Enable */ - uint16_t CB1DE:1; /* Capture B1 FIFO DMA Enable */ - uint16_t CB0DE:1; /* Capture B0 FIFO DMA Enable */ - uint16_t CX1DE:1; /* Capture X1 FIFO DMA Enable */ - uint16_t CX0DE:1; /* Capture X0 FIFO DMA Enable */ - } B; - } mcPWM_DMAEN_16B_tag; - - - /* Register layout for all registers TCTRL... */ - - typedef union { /* Output Trigger Control Registers */ - uint16_t R; - struct { - uint16_t:10; - uint16_t OUT_TRIG_EN:6; /* Output Trigger Enables */ - } B; - } mcPWM_TCTRL_16B_tag; - - - /* Register layout for all registers DISMAP... */ - - typedef union { /* Fault Disable Mapping Registers */ - uint16_t R; - struct { - uint16_t:4; - uint16_t DISX:4; /* PWMX Fault Disable Mask */ - uint16_t DISB:4; /* PWMB Fault Disable Mask */ - uint16_t DISA:4; /* PWMA Fault Disable Mask */ - } B; - } mcPWM_DISMAP_16B_tag; - - - /* Register layout for all registers DTCNT0... */ - - typedef union { /* Deadtime Count Register 0 */ - uint16_t R; - struct { - uint16_t:5; - uint16_t DTCNT0:11; /* Deadtime Count Register 0 */ - } B; - } mcPWM_DTCNT0_16B_tag; - - - /* Register layout for all registers DTCNT1... */ - - typedef union { /* Deadtime Count Register 1 */ - uint16_t R; - struct { - uint16_t:5; - uint16_t DTCNT1:11; /* Deadtime Count Register 1 */ - } B; - } mcPWM_DTCNT1_16B_tag; - - /* Register layout for all registers CAPTCTRLX... */ - - typedef union { /* Capture Control X Register */ - uint16_t R; - struct { - uint16_t CX1CNT:3; /* Capture X1 FIFO Word Count */ - uint16_t CX0CNT:3; /* Capture X0 FIFO Word Count */ - uint16_t CFXWM:2; /* Capture X FIFOs Water Mark */ -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t EDGCNTXEN:1; /* Edge Counter X Enable */ -#else - uint16_t EDGCNTX_EN:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t INPSELX:1; /* Input Select X */ -#else - uint16_t INP_SELX:1; /* deprecated name - please avoid */ -#endif - uint16_t EDGX1:2; /* Edge X 1 */ - uint16_t EDGX0:2; /* Edge X 0 */ - uint16_t ONESHOTX:1; /* One Shot Mode X */ - uint16_t ARMX:1; /* Arm X */ - } B; - } mcPWM_CAPTCTRLX_16B_tag; - - - /* Register layout for all registers CAPTCMPX... */ - - typedef union { /* Capture Compare X Register */ - uint16_t R; - struct { - uint16_t EDGCNTX:8; /* Edge Counter X */ - uint16_t EDGCMPX:8; /* Edge Compare X */ - } B; - } mcPWM_CAPTCMPX_16B_tag; - - - /* Register layout for all registers CVAL0... */ - - typedef union { /* Capture Value 0 Register */ - uint16_t R; - struct { - uint16_t CAPTVAL0:16; /* Captured value from submodule counter */ - } B; - } mcPWM_CVAL0_16B_tag; - - - /* Register layout for all registers CVAL0CYC... */ - - typedef union { /* Capture Value 0 Cycle Register */ - uint16_t R; - struct { - uint16_t:12; - uint16_t CVAL0CYC:4; /* Capture Value 0 Cycle */ - } B; - } mcPWM_CVAL0CYC_16B_tag; - - - /* Register layout for all registers CVAL1... */ - - typedef union { /* Capture Value 1 Register */ - uint16_t R; - struct { - uint16_t CAPTVAL1:16; /* Captured value from submodule counter */ - } B; - } mcPWM_CVAL1_16B_tag; - - - /* Register layout for all registers CVAL1CYC... */ - - typedef union { /* Capture Value 1 Cycle Register */ - uint16_t R; - struct { - uint16_t:12; - uint16_t CVAL1CYC:4; /* Capture Value 1 Cycle */ - } B; - } mcPWM_CVAL1CYC_16B_tag; - - - /* Register layout for all registers CVAL3... */ - - typedef union { /* Capture Value 3 Register */ - uint16_t R; - struct { - uint16_t CAPTVAL3:16; /* Captured value from submodule counter */ - } B; - } mcPWM_CVAL3_16B_tag; - - - /* Register layout for all registers CVAL3CYC... */ - - typedef union { /* Capture Value 3 Cycle Register */ - uint16_t R; - struct { - uint16_t:12; - uint16_t CVAL3CYC:4; /* Capture Value 3 Cycle */ - } B; - } mcPWM_CVAL3CYC_16B_tag; - - - /* Register layout for all registers CVAL4... */ - - typedef union { /* Capture Value 4 Register */ - uint16_t R; - struct { - uint16_t CAPTVAL4:16; /* Captured value from submodule counter */ - } B; - } mcPWM_CVAL4_16B_tag; - - - /* Register layout for all registers CVAL4CYC... */ - - typedef union { /* Capture Value 4 Cycle Register */ - uint16_t R; - struct { - uint16_t:12; - uint16_t CVAL4CYC:4; /* Capture Value 4 Cycle */ - } B; - } mcPWM_CVAL4CYC_16B_tag; - - - /* Register layout for all registers CVAL5... */ - - typedef union { /* Capture Value 5 Register */ - uint16_t R; - struct { - uint16_t CAPTVAL5:16; /* Captured value from submodule counter */ - } B; - } mcPWM_CVAL5_16B_tag; - - - /* Register layout for all registers CVAL5CYC... */ - - typedef union { /* Capture Value 5 Cycle Register */ - uint16_t R; - struct { - uint16_t:12; - uint16_t CVAL5CYC:4; /* Capture Value 5 Cycle */ - } B; - } mcPWM_CVAL5CYC_16B_tag; - - typedef union { /* Output Enable Register */ - uint16_t R; - struct { - uint16_t:4; - uint16_t PWMA_EN:4; /* PWMA Output Enables */ - uint16_t PWMB_EN:4; /* PWMB Output Enables */ - uint16_t PWMX_EN:4; /* PWMX Output Enables */ - } B; - } mcPWM_OUTEN_16B_tag; - - typedef union { /* Mask Register */ - uint16_t R; - struct { - uint16_t:4; - uint16_t MASKA:4; /* PWMA Masks */ - uint16_t MASKB:4; /* PWMB Masks */ - uint16_t MASKX:4; /* PWMX Masks */ - } B; - } mcPWM_MASK_16B_tag; - - typedef union { /* Software Controlled Output Register */ - uint16_t R; - struct { - uint16_t:8; -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t OUT23_3:1; /* Software Controlled Output 23_3 */ -#else - uint16_t OUTA_3:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t OUT45_3:1; /* Software Controlled Output 45_3 */ -#else - uint16_t OUTB_3:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t OUT23_2:1; /* Software Controlled Output 23_2 */ -#else - uint16_t OUTA_2:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t OUT45_2:1; /* Software Controlled Output 45_2 */ -#else - uint16_t OUTB_2:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t OUT23_1:1; /* Software Controlled Output 23_1 */ -#else - uint16_t OUTA_1:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t OUT45_1:1; /* Software Controlled Output 45_1 */ -#else - uint16_t OUTB_1:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t OUT23_0:1; /* Software Controlled Output 23_0 */ -#else - uint16_t OUTA_0:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t OUT45_0:1; /* Software Controlled Output 45_0 */ -#else - uint16_t OUTB_0:1; /* deprecated name - please avoid */ -#endif - } B; - } mcPWM_SWCOUT_16B_tag; - - typedef union { /* Deadtime Source Select Register */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t SEL23_3:2; /* PWM23_3 Control Select */ -#else - uint16_t SELA_3:2; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t SEL45_3:2; /* PWM45_3 Control Select */ -#else - uint16_t SELB_3:2; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t SEL23_2:2; /* PWM23_2 Control Select */ -#else - uint16_t SELA_2:2; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t SEL45_2:2; /* PWM45_2 Control Select */ -#else - uint16_t SELB_2:2; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t SEL23_1:2; /* PWM23_1 Control Select */ -#else - uint16_t SELA_1:2; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t SEL45_1:2; /* PWM45_1 Control Select */ -#else - uint16_t SELB_1:2; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t SEL23_0:2; /* PWM23_0 Control Select */ -#else - uint16_t SELA_0:2; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t SEL45_0:2; /* PWM45_0 Control Select */ -#else - uint16_t SELB_0:2; /* deprecated name - please avoid */ -#endif - } B; - } mcPWM_DTSRCSEL_16B_tag; - - typedef union { /* Master Control Register */ - uint16_t R; - struct { - uint16_t IPOL:4; /* Current Polarity */ - uint16_t RUN:4; /* Run */ -#ifndef USE_FIELD_ALIASES_mcPWM - uint16_t CLOK:4; /* Clear Load Okay */ -#else - uint16_t CLDOK:4; /* deprecated name - please avoid */ -#endif - uint16_t LDOK:4; /* Load Okay */ - } B; - } mcPWM_MCTRL_16B_tag; - - typedef union { /* Fault Control Register */ - uint16_t R; - struct { - uint16_t FLVL:4; /* Fault Level */ - uint16_t FAUTO:4; /* Automatic Fault Clearing */ - uint16_t FSAFE:4; /* Fault Safety Mode */ - uint16_t FIE:4; /* Fault Interrupt Enables */ - } B; - } mcPWM_FCTRL_16B_tag; - - typedef union { /* Fault Status Register */ - uint16_t R; - struct { - uint16_t:3; - uint16_t FTEST:1; /* Fault Test */ - uint16_t FFPIN:4; /* Filtered Fault Pins */ - uint16_t:4; - uint16_t FFLAG:4; /* Fault Flags */ - } B; - } mcPWM_FSTS_16B_tag; - - typedef union { /* Fault Filter Register */ - uint16_t R; - struct { - uint16_t:5; - uint16_t FILT_CNT:3; /* Fault Filter Count */ - uint16_t FILT_PER:8; /* Fault Filter Period */ - } B; - } mcPWM_FFILT_16B_tag; - - - /* Register layout for generated register(s) VAL... */ - - typedef union { /* */ - uint16_t R; - } mcPWM_VAL_16B_tag; - - - typedef struct mcPWM_SUBMOD_struct_tag { - - /* Counter Register */ - mcPWM_CNT_16B_tag CNT; /* relative offset: 0x0000 */ - /* Initial Counter Register */ - mcPWM_INIT_16B_tag INIT; /* relative offset: 0x0002 */ - /* Control 2 Register */ - mcPWM_CTRL2_16B_tag CTRL2; /* relative offset: 0x0004 */ - union { - /* Control Register */ - mcPWM_CTRL1_16B_tag CTRL1; /* relative offset: 0x0006 */ - mcPWM_CTRL1_16B_tag CTRL; /* deprecated - please avoid */ - }; - /* Value Register 0 */ - - union { - - struct { - - mcPWM_VAL_0_16B_tag VAL_0; /* relative offset: 0x0008 */ - /* Value Register 1 */ - mcPWM_VAL_1_16B_tag VAL_1; /* relative offset: 0x000A */ - /* Value Register 2 */ - mcPWM_VAL_2_16B_tag VAL_2; /* relative offset: 0x000C */ - /* Value Register 3 */ - mcPWM_VAL_3_16B_tag VAL_3; /* relative offset: 0x000E */ - /* Value Register 4 */ - mcPWM_VAL_4_16B_tag VAL_4; /* relative offset: 0x0010 */ - /* Value Register 5 */ - mcPWM_VAL_5_16B_tag VAL_5; /* relative offset: 0x0012 */ - - }; - - mcPWM_VAL_0_16B_tag VAL[6]; /* offset: 0x0008 size: 16 bit */ - - }; - int8_t mcPWM_reserved_0014[4]; - /* Output Control Register */ - mcPWM_OCTRL_16B_tag OCTRL; /* relative offset: 0x0018 */ - /* Status Register */ - mcPWM_STS_16B_tag STS; /* relative offset: 0x001A */ - /* Interrupt Enable Registers */ - mcPWM_INTEN_16B_tag INTEN; /* relative offset: 0x001C */ - /* DMA Enable Registers */ - mcPWM_DMAEN_16B_tag DMAEN; /* relative offset: 0x001E */ - /* Output Trigger Control Registers */ - mcPWM_TCTRL_16B_tag TCTRL; /* relative offset: 0x0020 */ - /* Fault Disable Mapping Registers */ - mcPWM_DISMAP_16B_tag DISMAP; /* relative offset: 0x0022 */ - /* Deadtime Count Register 0 */ - mcPWM_DTCNT0_16B_tag DTCNT0; /* relative offset: 0x0024 */ - /* Deadtime Count Register 1 */ - mcPWM_DTCNT1_16B_tag DTCNT1; /* relative offset: 0x0026 */ - /* Capture Control A Register */ - int8_t mcPWM_reserved_0028[8]; - /* Capture Control X Register */ - mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX; /* relative offset: 0x0030 */ - union { - /* Capture Compare X Register */ - mcPWM_CAPTCMPX_16B_tag CAPTCMPX; /* relative offset: 0x0032 */ - mcPWM_CAPTCMPX_16B_tag CAPTCOMPX; /* deprecated - please avoid */ - }; - /* Capture Value 0 Register */ - mcPWM_CVAL0_16B_tag CVAL0; /* relative offset: 0x0034 */ - union { - /* Capture Value 0 Cycle Register */ - mcPWM_CVAL0CYC_16B_tag CVAL0CYC; /* relative offset: 0x0036 */ - mcPWM_CVAL0CYC_16B_tag CVAL0C; /* deprecated - please avoid */ - }; - /* Capture Value 1 Register */ - mcPWM_CVAL1_16B_tag CVAL1; /* relative offset: 0x0038 */ - union { - /* Capture Value 1 Cycle Register */ - mcPWM_CVAL1CYC_16B_tag CVAL1CYC; /* relative offset: 0x003A */ - mcPWM_CVAL1CYC_16B_tag CVAL1C; /* deprecated - please avoid */ - }; - /* Capture Value 2 Register */ - int8_t mcPWM_SUBMOD_reserved_003C[16]; - int8_t mcPWM_SUBMOD_reserved_004C[4]; - - } mcPWM_SUBMOD_tag; - - - typedef struct mcPWM_struct_tag { /* start of mcPWM_tag */ - union { - /* Register set SUBMOD */ - mcPWM_SUBMOD_tag SUBMOD[4]; /* offset: 0x0000 (0x0050 x 4) */ - - mcPWM_SUBMOD_tag SUB[4]; /* offset: 0x0000 (0x0050 x 4) */ - - struct { - /* Counter Register */ - mcPWM_CNT_16B_tag CNT0; /* offset: 0x0000 size: 16 bit */ - /* Initial Counter Register */ - mcPWM_INIT_16B_tag INIT0; /* offset: 0x0002 size: 16 bit */ - /* Control 2 Register */ - mcPWM_CTRL2_16B_tag CTRL20; /* offset: 0x0004 size: 16 bit */ - /* Control Register */ - mcPWM_CTRL1_16B_tag CTRL10; /* offset: 0x0006 size: 16 bit */ - /* Value Register 0 */ - mcPWM_VAL_0_16B_tag VAL_00; /* offset: 0x0008 size: 16 bit */ - /* Value Register 1 */ - mcPWM_VAL_1_16B_tag VAL_10; /* offset: 0x000A size: 16 bit */ - /* Value Register 2 */ - mcPWM_VAL_2_16B_tag VAL_20; /* offset: 0x000C size: 16 bit */ - /* Value Register 3 */ - mcPWM_VAL_3_16B_tag VAL_30; /* offset: 0x000E size: 16 bit */ - /* Value Register 4 */ - mcPWM_VAL_4_16B_tag VAL_40; /* offset: 0x0010 size: 16 bit */ - /* Value Register 5 */ - mcPWM_VAL_5_16B_tag VAL_50; /* offset: 0x0012 size: 16 bit */ - int8_t mcPWM_reserved_0014[4]; - /* Output Control Register */ - mcPWM_OCTRL_16B_tag OCTRL0; /* offset: 0x0018 size: 16 bit */ - /* Status Register */ - mcPWM_STS_16B_tag STS0; /* offset: 0x001A size: 16 bit */ - /* Interrupt Enable Registers */ - mcPWM_INTEN_16B_tag INTEN0; /* offset: 0x001C size: 16 bit */ - /* DMA Enable Registers */ - mcPWM_DMAEN_16B_tag DMAEN0; /* offset: 0x001E size: 16 bit */ - /* Output Trigger Control Registers */ - mcPWM_TCTRL_16B_tag TCTRL0; /* offset: 0x0020 size: 16 bit */ - /* Fault Disable Mapping Registers */ - mcPWM_DISMAP_16B_tag DISMAP0; /* offset: 0x0022 size: 16 bit */ - /* Deadtime Count Register 0 */ - mcPWM_DTCNT0_16B_tag DTCNT00; /* offset: 0x0024 size: 16 bit */ - /* Deadtime Count Register 1 */ - mcPWM_DTCNT1_16B_tag DTCNT10; /* offset: 0x0026 size: 16 bit */ - int8_t mcPWM_reserved_0028[8]; - /* Capture Control X Register */ - mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX0; /* offset: 0x0030 size: 16 bit */ - /* Capture Compare X Register */ - mcPWM_CAPTCMPX_16B_tag CAPTCMPX0; /* offset: 0x0032 size: 16 bit */ - /* Capture Value 0 Register */ - mcPWM_CVAL0_16B_tag CVAL00; /* offset: 0x0034 size: 16 bit */ - /* Capture Value 0 Cycle Register */ - mcPWM_CVAL0CYC_16B_tag CVAL0CYC0; /* offset: 0x0036 size: 16 bit */ - /* Capture Value 1 Register */ - mcPWM_CVAL1_16B_tag CVAL10; /* offset: 0x0038 size: 16 bit */ - /* Capture Value 1 Cycle Register */ - mcPWM_CVAL1CYC_16B_tag CVAL1CYC0; /* offset: 0x003A size: 16 bit */ - int8_t mcPWM_reserved_003c[16]; - int8_t mcPWM_reserved_004C_I2[4]; - /* Counter Register */ - mcPWM_CNT_16B_tag CNT1; /* offset: 0x0050 size: 16 bit */ - /* Initial Counter Register */ - mcPWM_INIT_16B_tag INIT1; /* offset: 0x0052 size: 16 bit */ - /* Control 2 Register */ - mcPWM_CTRL2_16B_tag CTRL21; /* offset: 0x0054 size: 16 bit */ - /* Control Register */ - mcPWM_CTRL1_16B_tag CTRL11; /* offset: 0x0056 size: 16 bit */ - /* Value Register 0 */ - mcPWM_VAL_0_16B_tag VAL_01; /* offset: 0x0058 size: 16 bit */ - /* Value Register 1 */ - mcPWM_VAL_1_16B_tag VAL_11; /* offset: 0x005A size: 16 bit */ - /* Value Register 2 */ - mcPWM_VAL_2_16B_tag VAL_21; /* offset: 0x005C size: 16 bit */ - /* Value Register 3 */ - mcPWM_VAL_3_16B_tag VAL_31; /* offset: 0x005E size: 16 bit */ - /* Value Register 4 */ - mcPWM_VAL_4_16B_tag VAL_41; /* offset: 0x0060 size: 16 bit */ - /* Value Register 5 */ - mcPWM_VAL_5_16B_tag VAL_51; /* offset: 0x0062 size: 16 bit */ - int8_t mcPWM_reserved_0064[4]; - /* Output Control Register */ - mcPWM_OCTRL_16B_tag OCTRL1; /* offset: 0x0068 size: 16 bit */ - /* Status Register */ - mcPWM_STS_16B_tag STS1; /* offset: 0x006A size: 16 bit */ - /* Interrupt Enable Registers */ - mcPWM_INTEN_16B_tag INTEN1; /* offset: 0x006C size: 16 bit */ - /* DMA Enable Registers */ - mcPWM_DMAEN_16B_tag DMAEN1; /* offset: 0x006E size: 16 bit */ - /* Output Trigger Control Registers */ - mcPWM_TCTRL_16B_tag TCTRL1; /* offset: 0x0070 size: 16 bit */ - /* Fault Disable Mapping Registers */ - mcPWM_DISMAP_16B_tag DISMAP1; /* offset: 0x0072 size: 16 bit */ - /* Deadtime Count Register 0 */ - mcPWM_DTCNT0_16B_tag DTCNT01; /* offset: 0x0074 size: 16 bit */ - /* Deadtime Count Register 1 */ - mcPWM_DTCNT1_16B_tag DTCNT11; /* offset: 0x0076 size: 16 bit */ - /* Capture Control A Register */ - int8_t mcPWM_reserved_0078[8]; - /* Capture Control X Register */ - mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX1; /* offset: 0x0080 size: 16 bit */ - /* Capture Compare X Register */ - mcPWM_CAPTCMPX_16B_tag CAPTCMPX1; /* offset: 0x0082 size: 16 bit */ - /* Capture Value 0 Register */ - mcPWM_CVAL0_16B_tag CVAL01; /* offset: 0x0084 size: 16 bit */ - /* Capture Value 0 Cycle Register */ - mcPWM_CVAL0CYC_16B_tag CVAL0CYC1; /* offset: 0x0086 size: 16 bit */ - /* Capture Value 1 Register */ - mcPWM_CVAL1_16B_tag CVAL11; /* offset: 0x0088 size: 16 bit */ - /* Capture Value 1 Cycle Register */ - mcPWM_CVAL1CYC_16B_tag CVAL1CYC1; /* offset: 0x008A size: 16 bit */ - int8_t mcPWM_reserved_008c[16]; - int8_t mcPWM_reserved_009C_I2[4]; - /* Counter Register */ - mcPWM_CNT_16B_tag CNT2; /* offset: 0x00A0 size: 16 bit */ - /* Initial Counter Register */ - mcPWM_INIT_16B_tag INIT2; /* offset: 0x00A2 size: 16 bit */ - /* Control 2 Register */ - mcPWM_CTRL2_16B_tag CTRL22; /* offset: 0x00A4 size: 16 bit */ - /* Control Register */ - mcPWM_CTRL1_16B_tag CTRL12; /* offset: 0x00A6 size: 16 bit */ - /* Value Register 0 */ - mcPWM_VAL_0_16B_tag VAL_02; /* offset: 0x00A8 size: 16 bit */ - /* Value Register 1 */ - mcPWM_VAL_1_16B_tag VAL_12; /* offset: 0x00AA size: 16 bit */ - /* Value Register 2 */ - mcPWM_VAL_2_16B_tag VAL_22; /* offset: 0x00AC size: 16 bit */ - /* Value Register 3 */ - mcPWM_VAL_3_16B_tag VAL_32; /* offset: 0x00AE size: 16 bit */ - /* Value Register 4 */ - mcPWM_VAL_4_16B_tag VAL_42; /* offset: 0x00B0 size: 16 bit */ - /* Value Register 5 */ - mcPWM_VAL_5_16B_tag VAL_52; /* offset: 0x00B2 size: 16 bit */ - int8_t mcPWM_reserved_00b4[4]; - /* Output Control Register */ - mcPWM_OCTRL_16B_tag OCTRL2; /* offset: 0x00B8 size: 16 bit */ - /* Status Register */ - mcPWM_STS_16B_tag STS2; /* offset: 0x00BA size: 16 bit */ - /* Interrupt Enable Registers */ - mcPWM_INTEN_16B_tag INTEN2; /* offset: 0x00BC size: 16 bit */ - /* DMA Enable Registers */ - mcPWM_DMAEN_16B_tag DMAEN2; /* offset: 0x00BE size: 16 bit */ - /* Output Trigger Control Registers */ - mcPWM_TCTRL_16B_tag TCTRL2; /* offset: 0x00C0 size: 16 bit */ - /* Fault Disable Mapping Registers */ - mcPWM_DISMAP_16B_tag DISMAP2; /* offset: 0x00C2 size: 16 bit */ - /* Deadtime Count Register 0 */ - mcPWM_DTCNT0_16B_tag DTCNT02; /* offset: 0x00C4 size: 16 bit */ - /* Deadtime Count Register 1 */ - mcPWM_DTCNT1_16B_tag DTCNT12; /* offset: 0x00C6 size: 16 bit */ - /* Capture Control A Register */ - int8_t mcPWM_reserved_00c8[8]; - /* Capture Control X Register */ - mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX2; /* offset: 0x00D0 size: 16 bit */ - /* Capture Compare X Register */ - mcPWM_CAPTCMPX_16B_tag CAPTCMPX2; /* offset: 0x00D2 size: 16 bit */ - /* Capture Value 0 Register */ - mcPWM_CVAL0_16B_tag CVAL02; /* offset: 0x00D4 size: 16 bit */ - /* Capture Value 0 Cycle Register */ - mcPWM_CVAL0CYC_16B_tag CVAL0CYC2; /* offset: 0x00D6 size: 16 bit */ - /* Capture Value 1 Register */ - mcPWM_CVAL1_16B_tag CVAL12; /* offset: 0x00D8 size: 16 bit */ - /* Capture Value 1 Cycle Register */ - mcPWM_CVAL1CYC_16B_tag CVAL1CYC2; /* offset: 0x00DA size: 16 bit */ - int8_t mcPWM_reserved_00dc[16]; - int8_t mcPWM_reserved_00EC_I2[4]; - /* Counter Register */ - mcPWM_CNT_16B_tag CNT3; /* offset: 0x00F0 size: 16 bit */ - /* Initial Counter Register */ - mcPWM_INIT_16B_tag INIT3; /* offset: 0x00F2 size: 16 bit */ - /* Control 2 Register */ - mcPWM_CTRL2_16B_tag CTRL23; /* offset: 0x00F4 size: 16 bit */ - /* Control Register */ - mcPWM_CTRL1_16B_tag CTRL13; /* offset: 0x00F6 size: 16 bit */ - /* Value Register 0 */ - mcPWM_VAL_0_16B_tag VAL_03; /* offset: 0x00F8 size: 16 bit */ - /* Value Register 1 */ - mcPWM_VAL_1_16B_tag VAL_13; /* offset: 0x00FA size: 16 bit */ - /* Value Register 2 */ - mcPWM_VAL_2_16B_tag VAL_23; /* offset: 0x00FC size: 16 bit */ - /* Value Register 3 */ - mcPWM_VAL_3_16B_tag VAL_33; /* offset: 0x00FE size: 16 bit */ - /* Value Register 4 */ - mcPWM_VAL_4_16B_tag VAL_43; /* offset: 0x0100 size: 16 bit */ - /* Value Register 5 */ - mcPWM_VAL_5_16B_tag VAL_53; /* offset: 0x0102 size: 16 bit */ - int8_t mcPWM_reserved_00104[4]; - /* Output Control Register */ - mcPWM_OCTRL_16B_tag OCTRL3; /* offset: 0x0108 size: 16 bit */ - /* Status Register */ - mcPWM_STS_16B_tag STS3; /* offset: 0x010A size: 16 bit */ - /* Interrupt Enable Registers */ - mcPWM_INTEN_16B_tag INTEN3; /* offset: 0x010C size: 16 bit */ - /* DMA Enable Registers */ - mcPWM_DMAEN_16B_tag DMAEN3; /* offset: 0x010E size: 16 bit */ - /* Output Trigger Control Registers */ - mcPWM_TCTRL_16B_tag TCTRL3; /* offset: 0x0110 size: 16 bit */ - /* Fault Disable Mapping Registers */ - mcPWM_DISMAP_16B_tag DISMAP3; /* offset: 0x0112 size: 16 bit */ - /* Deadtime Count Register 0 */ - mcPWM_DTCNT0_16B_tag DTCNT03; /* offset: 0x0114 size: 16 bit */ - /* Deadtime Count Register 1 */ - mcPWM_DTCNT1_16B_tag DTCNT13; /* offset: 0x0116 size: 16 bit */ - /* Capture Control A Register */ - int8_t mcPWM_reserved_00118[8]; - /* Capture Control X Register */ - mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX3; /* offset: 0x0120 size: 16 bit */ - /* Capture Compare X Register */ - mcPWM_CAPTCMPX_16B_tag CAPTCMPX3; /* offset: 0x0122 size: 16 bit */ - /* Capture Value 0 Register */ - mcPWM_CVAL0_16B_tag CVAL03; /* offset: 0x0124 size: 16 bit */ - /* Capture Value 0 Cycle Register */ - mcPWM_CVAL0CYC_16B_tag CVAL0CYC3; /* offset: 0x0126 size: 16 bit */ - /* Capture Value 1 Register */ - mcPWM_CVAL1_16B_tag CVAL13; /* offset: 0x0128 size: 16 bit */ - /* Capture Value 1 Cycle Register */ - mcPWM_CVAL1CYC_16B_tag CVAL1CYC3; /* offset: 0x012A size: 16 bit */ - int8_t mcPWM_reserved_0012c[16]; - int8_t mcPWM_reserved_013C_E2[4]; - }; - - }; - /* Output Enable Register */ - mcPWM_OUTEN_16B_tag OUTEN; /* offset: 0x0140 size: 16 bit */ - /* Mask Register */ - mcPWM_MASK_16B_tag MASK; /* offset: 0x0142 size: 16 bit */ - /* Software Controlled Output Register */ - mcPWM_SWCOUT_16B_tag SWCOUT; /* offset: 0x0144 size: 16 bit */ - /* Deadtime Source Select Register */ - mcPWM_DTSRCSEL_16B_tag DTSRCSEL; /* offset: 0x0146 size: 16 bit */ - /* Master Control Register */ - mcPWM_MCTRL_16B_tag MCTRL; /* offset: 0x0148 size: 16 bit */ - int8_t mcPWM_reserved_014A[2]; - /* Fault Control Register */ - mcPWM_FCTRL_16B_tag FCTRL; /* offset: 0x014C size: 16 bit */ - /* Fault Status Register */ - mcPWM_FSTS_16B_tag FSTS; /* offset: 0x014E size: 16 bit */ - /* Fault Filter Register */ - mcPWM_FFILT_16B_tag FFILT; /* offset: 0x0150 size: 16 bit */ - } mcPWM_tag; - - -#define mcPWM_A (*(volatile mcPWM_tag *) 0xFFE24000UL) -#define mcPWM_B (*(volatile mcPWM_tag *) 0xFFE28000UL) - - - -/****************************************************************/ -/* */ -/* Module: LINFLEX */ -/* */ -/****************************************************************/ - - typedef union { /* LIN Control Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t CCD:1; /* Checksum Calculation Disable */ - uint32_t CFD:1; /* Checksum Field Disable */ - uint32_t LASE:1; /* LIN Auto Synchronization Enable */ -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t AUTOWU:1; /* Auto Wake Up */ -#else - uint32_t AWUM:1; /* deprecated name - please avoid */ -#endif - uint32_t MBL:4; /* Master Break Length */ - uint32_t BF:1; /* By-Pass Filter */ -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t SLFM:1; /* Selftest Mode */ -#else - uint32_t SFTM:1; /* deprecated name - please avoid */ -#endif - uint32_t LBKM:1; /* Loopback Mode */ - uint32_t MME:1; /* Master Mode Enable */ -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t SSBL:1; /* Slave Mode Synch Break Length */ -#else - uint32_t SSDT:1; /* deprecated name - please avoid */ -#endif - uint32_t RBLM:1; /* Receiver Buffer Locked Mode */ - uint32_t SLEEP:1; /* Sleep Mode Request */ - uint32_t INIT:1; /* Initialization Mode Request */ - } B; - } LINFLEX_LINCR1_32B_tag; - - typedef union { /* LIN Interrupt Enable Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t SZIE:1; /* Stuck at Zero Interrupt Enable */ - uint32_t OCIE:1; /* Output Compare Interrupt Enable */ - uint32_t BEIE:1; /* Bit Error Interrupt Enable */ - uint32_t CEIE:1; /* Checksum Error Interrupt Enable */ - uint32_t HEIE:1; /* Header Error Interrupt Enable */ - uint32_t:2; - uint32_t FEIE:1; /* Frame Error Interrupt Enable */ - uint32_t BOIE:1; /* Buffer Overrun Error Interrupt Enable */ - uint32_t LSIE:1; /* LIN State Interrupt Enable */ - uint32_t WUIE:1; /* Wakeup Interrupt Enable */ - uint32_t DBFIE:1; /* Data Buffer Full Interrupt Enable */ -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t DBEIE_TOIE:1; /* Data Buffer Empty Interrupt Enable */ -#else - uint32_t DBEIE:1; /* deprecated name - please avoid */ -#endif - uint32_t DRIE:1; /* Data Reception complete Interrupt Enable */ - uint32_t DTIE:1; /* Data Transmitted Interrupt Enable */ - uint32_t HRIE:1; /* Header Received Interrupt Enable */ - } B; - } LINFLEX_LINIER_32B_tag; - - typedef union { /* LIN Status Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t LINS:4; /* LIN State */ - uint32_t:2; - uint32_t RMB:1; /* Release Message Buffer */ - uint32_t:1; -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t RXBUSY:1; /* Receiver Busy Flag */ -#else - uint32_t RBSY:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t RDI:1; /* LIN Receive Signal */ -#else - uint32_t RPS:1; /* deprecated name - please avoid */ -#endif - uint32_t WUF:1; /* Wake Up Flag */ - uint32_t DBFF:1; /* Data Buffer Full Flag */ - uint32_t DBEF:1; /* Data Buffer Empty Flag */ - uint32_t DRF:1; /* Data Reception Completed Flag */ - uint32_t DTF:1; /* Data Transmission Completed Flag */ - uint32_t HRF:1; /* Header Received Flag */ - } B; - } LINFLEX_LINSR_32B_tag; - - typedef union { /* LIN Error Status Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t SZF:1; /* Stuck at Zero Flag */ - uint32_t OCF:1; /* Output Compare Flag */ - uint32_t BEF:1; /* Bit Error Flag */ - uint32_t CEF:1; /* Checksum Error Flag */ - uint32_t SFEF:1; /* Sync Field Error Flag */ -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t SDEF:1; /* Sync Delimiter Error Flag */ -#else - uint32_t BDEF:1; /* deprecated name - please avoid */ -#endif - uint32_t IDPEF:1; /* ID Parity Error Flag */ - uint32_t FEF:1; /* Framing Error Flag */ - uint32_t BOF:1; /* Buffer Overrun Flag */ - uint32_t:6; - uint32_t NF:1; /* Noise Flag */ - } B; - } LINFLEX_LINESR_32B_tag; - - typedef union { /* UART Mode Control Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t TDFL_TFC:3; /* Transmitter Data Field Length/TX FIFO Counter */ - uint32_t RDFL_RFC0:3; /* Reception Data Field Length/RX FIFO Counter */ - uint32_t RFBM:1; /* RX FIFO/ Buffer Mode */ - uint32_t TFBM:1; /* TX FIFO/ Buffer Mode */ - uint32_t WL1:1; /* Word Length in UART mode - bit 1 */ - uint32_t PC1:1; /* Parity Check - bit 1 */ - uint32_t RXEN:1; /* Receiver Enable */ - uint32_t TXEN:1; /* Transmitter Enable */ -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t PC0:1; /* Parity Check - bit 0 */ -#else - uint32_t OP:1; /* deprecated name - please avoid */ -#endif - uint32_t PCE:1; /* Parity Control Enable */ -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t WL0:1; /* Word Length in UART Mode - bit 0 */ -#else - uint32_t WL:1; /* deprecated name - please avoid */ -#endif - uint32_t UART:1; /* UART Mode */ - } B; - } LINFLEX_UARTCR_32B_tag; - - typedef union { /* UART Mode Status Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t SZF:1; /* Stuck at Zero Flag */ - uint32_t OCF:1; /* Output Compare Flag */ - uint32_t PE:4; /* Parity Error Flag */ - uint32_t RMB:1; /* Release Message Buffer */ - uint32_t FEF:1; /* Framing Error Flag */ - uint32_t BOF:1; /* Buffer Overrun Flag */ - uint32_t RDI:1; /* Receiver Data Input Signal */ - uint32_t WUF:1; /* Wakeup Flag */ - uint32_t:1; - uint32_t TO:1; /* Time Out */ -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t DRF_RFE:1; /* Data Reception Completed Flag/RX FIFO Empty Flag */ -#else - uint32_t DRF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t DTF_TFF:1; /* Data Transmission Completed Flag/TX FIFO Full Flag */ -#else - uint32_t DTF:1; /* deprecated name - please avoid */ -#endif - uint32_t NF:1; /* Noise Flag */ - } B; - } LINFLEX_UARTSR_32B_tag; - - typedef union { /* LIN Time-Out Control Status Register */ - uint32_t R; - struct { - uint32_t:21; -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t MODE:1; /* Time-out Counter Mode */ -#else - uint32_t LTOM:1; /* deprecated name - please avoid */ -#endif - uint32_t IOT:1; /* Idle on Timeout */ - uint32_t TOCE:1; /* Time-Out Counter Enable */ - uint32_t CNT:8; /* Counter Value */ - } B; - } LINFLEX_LINTCSR_32B_tag; - - typedef union { /* LIN Output Compare Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t OC2:8; /* Output Compare Value 2 */ - uint32_t OC1:8; /* Output Compare Value 1 */ - } B; - } LINFLEX_LINOCR_32B_tag; - - typedef union { /* LIN Time-Out Control Register */ - uint32_t R; - struct { - uint32_t:20; - uint32_t RTO:4; /* Response Time-Out Value */ - uint32_t:1; - uint32_t HTO:7; /* Header Time-Out Value */ - } B; - } LINFLEX_LINTOCR_32B_tag; - - typedef union { /* LIN Fractional Baud Rate Register */ - uint32_t R; - struct { - uint32_t:28; -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t FBR:4; /* Fractional Baud Rates */ -#else - uint32_t DIV_F:4; /* deprecated name - please avoid */ -#endif - } B; - } LINFLEX_LINFBRR_32B_tag; - - typedef union { /* LIN Integer Baud Rate Register */ - uint32_t R; - struct { - uint32_t:13; -#ifndef USE_FIELD_ALIASES_LINFLEX - uint32_t IBR:19; /* Integer Baud Rates */ -#else - uint32_t DIV_M:19; /* deprecated name - please avoid */ -#endif - } B; - } LINFLEX_LINIBRR_32B_tag; - - typedef union { /* LIN Checksum Field Register */ - uint32_t R; - struct { - uint32_t:24; - uint32_t CF:8; /* Checksum Bits */ - } B; - } LINFLEX_LINCFR_32B_tag; - - typedef union { /* LIN Control Register 2 */ - uint32_t R; - struct { - uint32_t:17; - uint32_t IOBE:1; /* Idle on Bit Error */ - uint32_t IOPE:1; /* Idle on Identifier Parity Error */ - uint32_t WURQ:1; /* Wakeup Generate Request */ - uint32_t DDRQ:1; /* Data Discard Request */ - uint32_t DTRQ:1; /* Data Transmission Request */ - uint32_t ABRQ:1; /* Abort Request */ - uint32_t HTRQ:1; /* Header Transmission Request */ - uint32_t:8; - } B; - } LINFLEX_LINCR2_32B_tag; - - typedef union { /* Buffer Identifier Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t DFL:6; /* Data Field Length */ - uint32_t DIR:1; /* Direction */ - uint32_t CCS:1; /* Classic Checksum */ - uint32_t:2; - uint32_t ID:6; /* Identifier */ - } B; - } LINFLEX_BIDR_32B_tag; - - typedef union { /* Buffer Data Register Least Significant */ - uint32_t R; - struct { - uint32_t DATA3:8; /* Data3 */ - uint32_t DATA2:8; /* Data2 */ - uint32_t DATA1:8; /* Data1 */ - uint32_t DATA0:8; /* Data0 */ - } B; - } LINFLEX_BDRL_32B_tag; - - typedef union { /* Buffer Data Register Most Significant */ - uint32_t R; - struct { - uint32_t DATA7:8; /* Data7 */ - uint32_t DATA6:8; /* Data6 */ - uint32_t DATA5:8; /* Data5 */ - uint32_t DATA4:8; /* Data4 */ - } B; - } LINFLEX_BDRM_32B_tag; - - typedef union { /* Identifier Filter Enable Register */ - uint32_t R; - struct { - uint32_t:24; - uint32_t FACT:8; /* Filter Active */ - } B; - } LINFLEX_IFER_32B_tag; - - typedef union { /* Identifier Filter Match Index */ - uint32_t R; - struct { - uint32_t:28; - uint32_t IFMI_IFMI:4; /* Filter Match Index */ - } B; - } LINFLEX_IFMI_32B_tag; - - typedef union { /* Identifier Filter Mode Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t IFM:4; /* Filter Mode */ - } B; - } LINFLEX_IFMR_32B_tag; - - - /* Register layout for all registers IFCR... */ - - typedef union { /* Identifier Filter Control Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t DFL:6; /* Data Field Length */ - uint32_t DIR:1; /* Direction */ - uint32_t CCS:1; /* Classic Checksum */ - uint32_t:2; - uint32_t ID:6; /* Identifier */ - } B; - } LINFLEX_IFCR_32B_tag; - - typedef union { /* Global Control Register */ - uint32_t R; - struct { - uint32_t:26; - uint32_t TDFBM:1; /* Transmit Data First Bit MSB */ - uint32_t RDFBM:1; /* Received Data First Bit MSB */ - uint32_t TDLIS:1; /* Transmit Data Level Inversion Selection */ - uint32_t RDLIS:1; /* Received Data Level Inversion Selection */ - uint32_t STOP:1; /* 1/2 stop bit configuration */ - uint32_t SR:1; /* Soft Reset */ - } B; - } LINFLEX_GCR_32B_tag; - - typedef union { /* UART Preset Time Out Register */ - uint32_t R; - struct { - uint32_t:20; - uint32_t PTO:12; /* Preset Time Out */ - } B; - } LINFLEX_UARTPTO_32B_tag; - - typedef union { /* UART Current Time Out Register */ - uint32_t R; - struct { - uint32_t:20; - uint32_t CTO:12; /* Current Time Out */ - } B; - } LINFLEX_UARTCTO_32B_tag; - - typedef union { /* DMA TX Enable Register */ - uint32_t R; - struct { - uint32_t:17; - uint32_t DTE:15; /* DMA Tx channel Enable */ - } B; - } LINFLEX_DMATXE_32B_tag; - - typedef union { /* DMA RX Enable Register */ - uint32_t R; - struct { - uint32_t:17; - uint32_t DRE:15; /* DMA Rx channel Enable */ - } B; - } LINFLEX_DMARXE_32B_tag; - - - - typedef struct LINFLEX_struct_tag { /* start of LINFLEX_tag */ - /* LIN Control Register */ - LINFLEX_LINCR1_32B_tag LINCR1; /* offset: 0x0000 size: 32 bit */ - /* LIN Interrupt Enable Register */ - LINFLEX_LINIER_32B_tag LINIER; /* offset: 0x0004 size: 32 bit */ - /* LIN Status Register */ - LINFLEX_LINSR_32B_tag LINSR; /* offset: 0x0008 size: 32 bit */ - /* LIN Error Status Register */ - LINFLEX_LINESR_32B_tag LINESR; /* offset: 0x000C size: 32 bit */ - /* UART Mode Control Register */ - LINFLEX_UARTCR_32B_tag UARTCR; /* offset: 0x0010 size: 32 bit */ - /* UART Mode Status Register */ - LINFLEX_UARTSR_32B_tag UARTSR; /* offset: 0x0014 size: 32 bit */ - /* LIN Time-Out Control Status Register */ - LINFLEX_LINTCSR_32B_tag LINTCSR; /* offset: 0x0018 size: 32 bit */ - /* LIN Output Compare Register */ - LINFLEX_LINOCR_32B_tag LINOCR; /* offset: 0x001C size: 32 bit */ - /* LIN Time-Out Control Register */ - LINFLEX_LINTOCR_32B_tag LINTOCR; /* offset: 0x0020 size: 32 bit */ - /* LIN Fractional Baud Rate Register */ - LINFLEX_LINFBRR_32B_tag LINFBRR; /* offset: 0x0024 size: 32 bit */ - /* LIN Integer Baud Rate Register */ - LINFLEX_LINIBRR_32B_tag LINIBRR; /* offset: 0x0028 size: 32 bit */ - /* LIN Checksum Field Register */ - LINFLEX_LINCFR_32B_tag LINCFR; /* offset: 0x002C size: 32 bit */ - /* LIN Control Register 2 */ - LINFLEX_LINCR2_32B_tag LINCR2; /* offset: 0x0030 size: 32 bit */ - /* Buffer Identifier Register */ - LINFLEX_BIDR_32B_tag BIDR; /* offset: 0x0034 size: 32 bit */ - /* Buffer Data Register Least Significant */ - LINFLEX_BDRL_32B_tag BDRL; /* offset: 0x0038 size: 32 bit */ - /* Buffer Data Register Most Significant */ - LINFLEX_BDRM_32B_tag BDRM; /* offset: 0x003C size: 32 bit */ - /* Identifier Filter Enable Register */ - LINFLEX_IFER_32B_tag IFER; /* offset: 0x0040 size: 32 bit */ - /* Identifier Filter Match Index */ - LINFLEX_IFMI_32B_tag IFMI; /* offset: 0x0044 size: 32 bit */ - /* Identifier Filter Mode Register */ - LINFLEX_IFMR_32B_tag IFMR; /* offset: 0x0048 size: 32 bit */ - union { - /* Identifier Filter Control Register */ - LINFLEX_IFCR_32B_tag IFCR[8]; /* offset: 0x004C (0x0004 x 8) */ - - struct { - /* Identifier Filter Control Register */ - LINFLEX_IFCR_32B_tag IFCR0; /* offset: 0x004C size: 32 bit */ - LINFLEX_IFCR_32B_tag IFCR1; /* offset: 0x0050 size: 32 bit */ - LINFLEX_IFCR_32B_tag IFCR2; /* offset: 0x0054 size: 32 bit */ - LINFLEX_IFCR_32B_tag IFCR3; /* offset: 0x0058 size: 32 bit */ - LINFLEX_IFCR_32B_tag IFCR4; /* offset: 0x005C size: 32 bit */ - LINFLEX_IFCR_32B_tag IFCR5; /* offset: 0x0060 size: 32 bit */ - LINFLEX_IFCR_32B_tag IFCR6; /* offset: 0x0064 size: 32 bit */ - LINFLEX_IFCR_32B_tag IFCR7; /* offset: 0x0068 size: 32 bit */ - }; - - }; - int8_t LINFLEX_reserved_006C[32]; - /* Global Control Register */ - LINFLEX_GCR_32B_tag GCR; /* offset: 0x008C size: 32 bit */ - /* UART Preset Time Out Register */ - LINFLEX_UARTPTO_32B_tag UARTPTO; /* offset: 0x0090 size: 32 bit */ - /* UART Current Time Out Register */ - LINFLEX_UARTCTO_32B_tag UARTCTO; /* offset: 0x0094 size: 32 bit */ - /* DMA TX Enable Register */ - LINFLEX_DMATXE_32B_tag DMATXE; /* offset: 0x0098 size: 32 bit */ - /* DMA RX Enable Register */ - LINFLEX_DMARXE_32B_tag DMARXE; /* offset: 0x009C size: 32 bit */ - } LINFLEX_tag; - - -#define LINFLEX0 (*(volatile LINFLEX_tag *) 0xFFE40000UL) -#define LINFLEX1 (*(volatile LINFLEX_tag *) 0xFFE44000UL) - - - -/****************************************************************/ -/* */ -/* Module: CRC */ -/* */ -/****************************************************************/ - - - /* Register layout for all registers CFG... */ - - typedef union { /* CRC_CFG - CRC Configuration register */ - uint32_t R; - uint8_t BYTE[4]; /* individual bytes can be accessed */ - uint16_t HALF[2]; /* individual halfwords can be accessed */ - uint32_t WORD; /* individual words can be accessed */ - struct { - uint32_t:29; - uint32_t POLYG:1; /* Polynomal selection 0- CRC-CCITT, 1- CRC-CRC-32 INV selection */ - uint32_t SWAP:1; /* SWAP selection */ - uint32_t INV:1; /* INV selection */ - } B; - } CRC_CFG_32B_tag; - - - /* Register layout for all registers INP... */ - - typedef union { /* CRC_INP - CRC Input register */ - uint32_t R; - uint8_t BYTE[4]; /* individual bytes can be accessed */ - uint16_t HALF[2]; /* individual halfwords can be accessed */ - uint32_t WORD; /* individual words can be accessed */ - } CRC_INP_32B_tag; - - - /* Register layout for all registers CSTAT... */ - - typedef union { /* CRC_STATUS - CRC Status register */ - uint32_t R; - uint8_t BYTE[4]; /* individual bytes can be accessed */ - uint16_t HALF[2]; /* individual halfwords can be accessed */ - uint32_t WORD; /* individual words can be accessed */ - } CRC_CSTAT_32B_tag; - - - /* Register layout for all registers OUTP... */ - - typedef union { /* CRC_STATUS - CRC OUTPUT register */ - uint32_t R; - uint8_t BYTE[4]; /* individual bytes can be accessed */ - uint16_t HALF[2]; /* individual halfwords can be accessed */ - uint32_t WORD; /* individual words can be accessed */ - } CRC_OUTP_32B_tag; - - - typedef struct CRC_CNTX_struct_tag { - - /* CRC_CFG - CRC Configuration register */ - CRC_CFG_32B_tag CFG; /* relative offset: 0x0000 */ - /* CRC_INP - CRC Input register */ - CRC_INP_32B_tag INP; /* relative offset: 0x0004 */ - /* CRC_STATUS - CRC Status register */ - CRC_CSTAT_32B_tag CSTAT; /* relative offset: 0x0008 */ - /* CRC_STATUS - CRC OUTPUT register */ - CRC_OUTP_32B_tag OUTP; /* relative offset: 0x000C */ - - } CRC_CNTX_tag; - - - typedef struct CRC_struct_tag { /* start of CRC_tag */ - union { - /* Register set CNTX */ - CRC_CNTX_tag CNTX[3]; /* offset: 0x0000 (0x0010 x 3) */ - - struct { - /* CRC_CFG - CRC Configuration register */ - CRC_CFG_32B_tag CFG0; /* offset: 0x0000 size: 32 bit */ - /* CRC_INP - CRC Input register */ - CRC_INP_32B_tag INP0; /* offset: 0x0004 size: 32 bit */ - /* CRC_STATUS - CRC Status register */ - CRC_CSTAT_32B_tag CSTAT0; /* offset: 0x0008 size: 32 bit */ - /* CRC_STATUS - CRC OUTPUT register */ - CRC_OUTP_32B_tag OUTP0; /* offset: 0x000C size: 32 bit */ - /* CRC_CFG - CRC Configuration register */ - CRC_CFG_32B_tag CFG1; /* offset: 0x0010 size: 32 bit */ - /* CRC_INP - CRC Input register */ - CRC_INP_32B_tag INP1; /* offset: 0x0014 size: 32 bit */ - /* CRC_STATUS - CRC Status register */ - CRC_CSTAT_32B_tag CSTAT1; /* offset: 0x0018 size: 32 bit */ - /* CRC_STATUS - CRC OUTPUT register */ - CRC_OUTP_32B_tag OUTP1; /* offset: 0x001C size: 32 bit */ - /* CRC_CFG - CRC Configuration register */ - CRC_CFG_32B_tag CFG2; /* offset: 0x0020 size: 32 bit */ - /* CRC_INP - CRC Input register */ - CRC_INP_32B_tag INP2; /* offset: 0x0024 size: 32 bit */ - /* CRC_STATUS - CRC Status register */ - CRC_CSTAT_32B_tag CSTAT2; /* offset: 0x0028 size: 32 bit */ - /* CRC_STATUS - CRC OUTPUT register */ - CRC_OUTP_32B_tag OUTP2; /* offset: 0x002C size: 32 bit */ - }; - - }; - } CRC_tag; - - -#define CRC (*(volatile CRC_tag *) 0xFFE68000UL) - - - -/****************************************************************/ -/* */ -/* Module: FCCU */ -/* */ -/****************************************************************/ - - typedef union { /* FCCU Control Register */ - uint32_t R; - struct { - uint32_t:23; - uint32_t NVML:1; /* NVM configuration loaded */ - uint32_t OPS:2; /* Operation status */ - uint32_t:1; - uint32_t OPR:5; /* Operation run */ - } B; - } FCCU_CTRL_32B_tag; - - typedef union { /* FCCU CTRL Key Register */ - uint32_t R; - } FCCU_CTRLK_32B_tag; - - typedef union { /* FCCU Configuration Register */ - uint32_t R; - struct { - uint32_t:10; - uint32_t RCCE1:1; /* RCC1 enable */ - uint32_t RCCE0:1; /* RCC0 enable */ - uint32_t SMRT:4; /* Safe Mode Request Timer */ - uint32_t:4; - uint32_t CM:1; /* Config mode */ - uint32_t SM:1; /* Switching mode */ - uint32_t PS:1; /* Polarity Selection */ - uint32_t FOM:3; /* Fault Output Mode Selection */ - uint32_t FOP:6; /* Fault Output Prescaler */ - } B; - } FCCU_CFG_32B_tag; - - typedef union { /* FCCU CF Configuration Register 0 */ - uint32_t R; - struct { - uint32_t CFC31:1; /* CF 31 configuration */ - uint32_t CFC30:1; /* CF 30 configuration */ - uint32_t CFC29:1; /* CF 29 configuration */ - uint32_t CFC28:1; /* CF 28 configuration */ - uint32_t CFC27:1; /* CF 27 configuration */ - uint32_t CFC26:1; /* CF 26 configuration */ - uint32_t CFC25:1; /* CF 25 configuration */ - uint32_t CFC24:1; /* CF 24 configuration */ - uint32_t CFC23:1; /* CF 23 configuration */ - uint32_t CFC22:1; /* CF 22 configuration */ - uint32_t CFC21:1; /* CF 21 configuration */ - uint32_t CFC20:1; /* CF 20 configuration */ - uint32_t CFC19:1; /* CF 19 configuration */ - uint32_t CFC18:1; /* CF 18 configuration */ - uint32_t CFC17:1; /* CF 17 configuration */ - uint32_t CFC16:1; /* CF 16 configuration */ - uint32_t CFC15:1; /* CF 15 configuration */ - uint32_t CFC14:1; /* CF 14 configuration */ - uint32_t CFC13:1; /* CF 13 configuration */ - uint32_t CFC12:1; /* CF 12 configuration */ - uint32_t CFC11:1; /* CF 11 configuration */ - uint32_t CFC10:1; /* CF 10 configuration */ - uint32_t CFC9:1; /* CF 9 configuration */ - uint32_t CFC8:1; /* CF 8 configuration */ - uint32_t CFC7:1; /* CF 7 configuration */ - uint32_t CFC6:1; /* CF 6 configuration */ - uint32_t CFC5:1; /* CF 5 configuration */ - uint32_t CFC4:1; /* CF 4 configuration */ - uint32_t CFC3:1; /* CF 3 configuration */ - uint32_t CFC2:1; /* CF 2 configuration */ - uint32_t CFC1:1; /* CF 1 configuration */ - uint32_t CFC0:1; /* CF 0 configuration */ - } B; - } FCCU_CF_CFG0_32B_tag; - - typedef union { /* FCCU CF Configuration Register 1 */ - uint32_t R; - struct { - uint32_t CFC63:1; /* CF 63 configuration */ - uint32_t CFC62:1; /* CF 62 configuration */ - uint32_t CFC61:1; /* CF 61 configuration */ - uint32_t CFC60:1; /* CF 60 configuration */ - uint32_t CFC59:1; /* CF 59 configuration */ - uint32_t CFC58:1; /* CF 58 configuration */ - uint32_t CFC57:1; /* CF 57 configuration */ - uint32_t CFC56:1; /* CF 56 configuration */ - uint32_t CFC55:1; /* CF 55 configuration */ - uint32_t CFC54:1; /* CF 54 configuration */ - uint32_t CFC53:1; /* CF 53 configuration */ - uint32_t CFC52:1; /* CF 52 configuration */ - uint32_t CFC51:1; /* CF 51 configuration */ - uint32_t CFC50:1; /* CF 50 configuration */ - uint32_t CFC49:1; /* CF 49 configuration */ - uint32_t CFC48:1; /* CF 48 configuration */ - uint32_t CFC47:1; /* CF 47 configuration */ - uint32_t CFC46:1; /* CF 46 configuration */ - uint32_t CFC45:1; /* CF 45 configuration */ - uint32_t CFC44:1; /* CF 44 configuration */ - uint32_t CFC43:1; /* CF 43 configuration */ - uint32_t CFC42:1; /* CF 42 configuration */ - uint32_t CFC41:1; /* CF 41 configuration */ - uint32_t CFC40:1; /* CF 40 configuration */ - uint32_t CFC39:1; /* CF 39 configuration */ - uint32_t CFC38:1; /* CF 38 configuration */ - uint32_t CFC37:1; /* CF 37 configuration */ - uint32_t CFC36:1; /* CF 36 configuration */ - uint32_t CFC35:1; /* CF 35 configuration */ - uint32_t CFC34:1; /* CF 34 configuration */ - uint32_t CFC33:1; /* CF 33 configuration */ - uint32_t CFC32:1; /* CF 32 configuration */ - } B; - } FCCU_CF_CFG1_32B_tag; - - typedef union { /* FCCU CF Configuration Register 2 */ - uint32_t R; - struct { - uint32_t CFC95:1; /* CF 95 configuration */ - uint32_t CFC94:1; /* CF 94 configuration */ - uint32_t CFC93:1; /* CF 93 configuration */ - uint32_t CFC92:1; /* CF 92 configuration */ - uint32_t CFC91:1; /* CF 91 configuration */ - uint32_t CFC90:1; /* CF 90 configuration */ - uint32_t CFC89:1; /* CF 89 configuration */ - uint32_t CFC88:1; /* CF 88 configuration */ - uint32_t CFC87:1; /* CF 87 configuration */ - uint32_t CFC86:1; /* CF 86 configuration */ - uint32_t CFC85:1; /* CF 85 configuration */ - uint32_t CFC84:1; /* CF 84 configuration */ - uint32_t CFC83:1; /* CF 83 configuration */ - uint32_t CFC82:1; /* CF 82 configuration */ - uint32_t CFC81:1; /* CF 81 configuration */ - uint32_t CFC80:1; /* CF 80 configuration */ - uint32_t CFC79:1; /* CF 79 configuration */ - uint32_t CFC78:1; /* CF 78 configuration */ - uint32_t CFC77:1; /* CF 77 configuration */ - uint32_t CFC76:1; /* CF 76 configuration */ - uint32_t CFC75:1; /* CF 75 configuration */ - uint32_t CFC74:1; /* CF 74 configuration */ - uint32_t CFC73:1; /* CF 73 configuration */ - uint32_t CFC72:1; /* CF 72 configuration */ - uint32_t CFC71:1; /* CF 71 configuration */ - uint32_t CFC70:1; /* CF 70 configuration */ - uint32_t CFC69:1; /* CF 69 configuration */ - uint32_t CFC68:1; /* CF 68 configuration */ - uint32_t CFC67:1; /* CF 67 configuration */ - uint32_t CFC66:1; /* CF 66 configuration */ - uint32_t CFC65:1; /* CF 65 configuration */ - uint32_t CFC64:1; /* CF 64 configuration */ - } B; - } FCCU_CF_CFG2_32B_tag; - - typedef union { /* FCCU CF Configuration Register 3 */ - uint32_t R; - struct { - uint32_t CFC127:1; /* CF 127 configuration */ - uint32_t CFC126:1; /* CF 126 configuration */ - uint32_t CFC125:1; /* CF 125 configuration */ - uint32_t CFC124:1; /* CF 124 configuration */ - uint32_t CFC123:1; /* CF 123 configuration */ - uint32_t CFC122:1; /* CF 122 configuration */ - uint32_t CFC121:1; /* CF 121 configuration */ - uint32_t CFC120:1; /* CF 120 configuration */ - uint32_t CFC119:1; /* CF 119 configuration */ - uint32_t CFC118:1; /* CF 118 configuration */ - uint32_t CFC117:1; /* CF 117 configuration */ - uint32_t CFC116:1; /* CF 116 configuration */ - uint32_t CFC115:1; /* CF 115 configuration */ - uint32_t CFC114:1; /* CF 114 configuration */ - uint32_t CFC113:1; /* CF 113 configuration */ - uint32_t CFC112:1; /* CF 112 configuration */ - uint32_t CFC111:1; /* CF 111 configuration */ - uint32_t CFC110:1; /* CF 110 configuration */ - uint32_t CFC109:1; /* CF 109 configuration */ - uint32_t CFC108:1; /* CF 108 configuration */ - uint32_t CFC107:1; /* CF 107 configuration */ - uint32_t CFC106:1; /* CF 106 configuration */ - uint32_t CFC105:1; /* CF 105 configuration */ - uint32_t CFC104:1; /* CF 104 configuration */ - uint32_t CFC103:1; /* CF 103 configuration */ - uint32_t CFC102:1; /* CF 102 configuration */ - uint32_t CFC101:1; /* CF 101 configuration */ - uint32_t CFC100:1; /* CF 100 configuration */ - uint32_t CFC99:1; /* CF 99 configuration */ - uint32_t CFC98:1; /* CF 98 configuration */ - uint32_t CFC97:1; /* CF 97 configuration */ - uint32_t CFC96:1; /* CF 96 configuration */ - } B; - } FCCU_CF_CFG3_32B_tag; - - typedef union { /* FCCU NCF Configuration Register 0 */ - uint32_t R; - struct { - uint32_t NCFC31:1; /* NCF 31 configuration */ - uint32_t NCFC30:1; /* NCF 30 configuration */ - uint32_t NCFC29:1; /* NCF 29 configuration */ - uint32_t NCFC28:1; /* NCF 28 configuration */ - uint32_t NCFC27:1; /* NCF 27 configuration */ - uint32_t NCFC26:1; /* NCF 26 configuration */ - uint32_t NCFC25:1; /* NCF 25 configuration */ - uint32_t NCFC24:1; /* NCF 24 configuration */ - uint32_t NCFC23:1; /* NCF 23 configuration */ - uint32_t NCFC22:1; /* NCF 22 configuration */ - uint32_t NCFC21:1; /* NCF 21 configuration */ - uint32_t NCFC20:1; /* NCF 20 configuration */ - uint32_t NCFC19:1; /* NCF 19 configuration */ - uint32_t NCFC18:1; /* NCF 18 configuration */ - uint32_t NCFC17:1; /* NCF 17 configuration */ - uint32_t NCFC16:1; /* NCF 16 configuration */ - uint32_t NCFC15:1; /* NCF 15 configuration */ - uint32_t NCFC14:1; /* NCF 14 configuration */ - uint32_t NCFC13:1; /* NCF 13 configuration */ - uint32_t NCFC12:1; /* NCF 12 configuration */ - uint32_t NCFC11:1; /* NCF 11 configuration */ - uint32_t NCFC10:1; /* NCF 10 configuration */ - uint32_t NCFC9:1; /* NCF 9 configuration */ - uint32_t NCFC8:1; /* NCF 8 configuration */ - uint32_t NCFC7:1; /* NCF 7 configuration */ - uint32_t NCFC6:1; /* NCF 6 configuration */ - uint32_t NCFC5:1; /* NCF 5 configuration */ - uint32_t NCFC4:1; /* NCF 4 configuration */ - uint32_t NCFC3:1; /* NCF 3 configuration */ - uint32_t NCFC2:1; /* NCF 2 configuration */ - uint32_t NCFC1:1; /* NCF 1 configuration */ - uint32_t NCFC0:1; /* NCF 0 configuration */ - } B; - } FCCU_NCF_CFG0_32B_tag; - - typedef union { /* FCCU NCF Configuration Register 1 */ - uint32_t R; - struct { - uint32_t NCFC63:1; /* NCF 63 configuration */ - uint32_t NCFC62:1; /* NCF 62 configuration */ - uint32_t NCFC61:1; /* NCF 61 configuration */ - uint32_t NCFC60:1; /* NCF 60 configuration */ - uint32_t NCFC59:1; /* NCF 59 configuration */ - uint32_t NCFC58:1; /* NCF 58 configuration */ - uint32_t NCFC57:1; /* NCF 57 configuration */ - uint32_t NCFC56:1; /* NCF 56 configuration */ - uint32_t NCFC55:1; /* NCF 55 configuration */ - uint32_t NCFC54:1; /* NCF 54 configuration */ - uint32_t NCFC53:1; /* NCF 53 configuration */ - uint32_t NCFC52:1; /* NCF 52 configuration */ - uint32_t NCFC51:1; /* NCF 51 configuration */ - uint32_t NCFC50:1; /* NCF 50 configuration */ - uint32_t NCFC49:1; /* NCF 49 configuration */ - uint32_t NCFC48:1; /* NCF 48 configuration */ - uint32_t NCFC47:1; /* NCF 47 configuration */ - uint32_t NCFC46:1; /* NCF 46 configuration */ - uint32_t NCFC45:1; /* NCF 45 configuration */ - uint32_t NCFC44:1; /* NCF 44 configuration */ - uint32_t NCFC43:1; /* NCF 43 configuration */ - uint32_t NCFC42:1; /* NCF 42 configuration */ - uint32_t NCFC41:1; /* NCF 41 configuration */ - uint32_t NCFC40:1; /* NCF 40 configuration */ - uint32_t NCFC39:1; /* NCF 39 configuration */ - uint32_t NCFC38:1; /* NCF 38 configuration */ - uint32_t NCFC37:1; /* NCF 37 configuration */ - uint32_t NCFC36:1; /* NCF 36 configuration */ - uint32_t NCFC35:1; /* NCF 35 configuration */ - uint32_t NCFC34:1; /* NCF 34 configuration */ - uint32_t NCFC33:1; /* NCF 33 configuration */ - uint32_t NCFC32:1; /* NCF 32 configuration */ - } B; - } FCCU_NCF_CFG1_32B_tag; - - typedef union { /* FCCU NCF Configuration Register 2 */ - uint32_t R; - struct { - uint32_t NCFC95:1; /* NCF 95 configuration */ - uint32_t NCFC94:1; /* NCF 94 configuration */ - uint32_t NCFC93:1; /* NCF 93 configuration */ - uint32_t NCFC92:1; /* NCF 92 configuration */ - uint32_t NCFC91:1; /* NCF 91 configuration */ - uint32_t NCFC90:1; /* NCF 90 configuration */ - uint32_t NCFC89:1; /* NCF 89 configuration */ - uint32_t NCFC88:1; /* NCF 88 configuration */ - uint32_t NCFC87:1; /* NCF 87 configuration */ - uint32_t NCFC86:1; /* NCF 86 configuration */ - uint32_t NCFC85:1; /* NCF 85 configuration */ - uint32_t NCFC84:1; /* NCF 84 configuration */ - uint32_t NCFC83:1; /* NCF 83 configuration */ - uint32_t NCFC82:1; /* NCF 82 configuration */ - uint32_t NCFC81:1; /* NCF 81 configuration */ - uint32_t NCFC80:1; /* NCF 80 configuration */ - uint32_t NCFC79:1; /* NCF 79 configuration */ - uint32_t NCFC78:1; /* NCF 78 configuration */ - uint32_t NCFC77:1; /* NCF 77 configuration */ - uint32_t NCFC76:1; /* NCF 76 configuration */ - uint32_t NCFC75:1; /* NCF 75 configuration */ - uint32_t NCFC74:1; /* NCF 74 configuration */ - uint32_t NCFC73:1; /* NCF 73 configuration */ - uint32_t NCFC72:1; /* NCF 72 configuration */ - uint32_t NCFC71:1; /* NCF 71 configuration */ - uint32_t NCFC70:1; /* NCF 70 configuration */ - uint32_t NCFC69:1; /* NCF 69 configuration */ - uint32_t NCFC68:1; /* NCF 68 configuration */ - uint32_t NCFC67:1; /* NCF 67 configuration */ - uint32_t NCFC66:1; /* NCF 66 configuration */ - uint32_t NCFC65:1; /* NCF 65 configuration */ - uint32_t NCFC64:1; /* NCF 64 configuration */ - } B; - } FCCU_NCF_CFG2_32B_tag; - - typedef union { /* FCCU NCF Configuration Register 3 */ - uint32_t R; - struct { - uint32_t NCFC127:1; /* NCF 127 configuration */ - uint32_t NCFC126:1; /* NCF 126 configuration */ - uint32_t NCFC125:1; /* NCF 125 configuration */ - uint32_t NCFC124:1; /* NCF 124 configuration */ - uint32_t NCFC123:1; /* NCF 123 configuration */ - uint32_t NCFC122:1; /* NCF 122 configuration */ - uint32_t NCFC121:1; /* NCF 121 configuration */ - uint32_t NCFC120:1; /* NCF 120 configuration */ - uint32_t NCFC119:1; /* NCF 119 configuration */ - uint32_t NCFC118:1; /* NCF 118 configuration */ - uint32_t NCFC117:1; /* NCF 117 configuration */ - uint32_t NCFC116:1; /* NCF 116 configuration */ - uint32_t NCFC115:1; /* NCF 115 configuration */ - uint32_t NCFC114:1; /* NCF 114 configuration */ - uint32_t NCFC113:1; /* NCF 113 configuration */ - uint32_t NCFC112:1; /* NCF 112 configuration */ - uint32_t NCFC111:1; /* NCF 111 configuration */ - uint32_t NCFC110:1; /* NCF 110 configuration */ - uint32_t NCFC109:1; /* NCF 109 configuration */ - uint32_t NCFC108:1; /* NCF 108 configuration */ - uint32_t NCFC107:1; /* NCF 107 configuration */ - uint32_t NCFC106:1; /* NCF 106 configuration */ - uint32_t NCFC105:1; /* NCF 105 configuration */ - uint32_t NCFC104:1; /* NCF 104 configuration */ - uint32_t NCFC103:1; /* NCF 103 configuration */ - uint32_t NCFC102:1; /* NCF 102 configuration */ - uint32_t NCFC101:1; /* NCF 101 configuration */ - uint32_t NCFC100:1; /* NCF 100 configuration */ - uint32_t NCFC99:1; /* NCF 99 configuration */ - uint32_t NCFC98:1; /* NCF 98 configuration */ - uint32_t NCFC97:1; /* NCF 97 configuration */ - uint32_t NCFC96:1; /* NCF 96 configuration */ - } B; - } FCCU_NCF_CFG3_32B_tag; - - typedef union { /* FCCU CFS Configuration Register 0 */ - uint32_t R; - struct { - uint32_t CFSC15:2; /* CF 15 state configuration */ - uint32_t CFSC14:2; /* CF 14 state configuration */ - uint32_t CFSC13:2; /* CF 13 state configuration */ - uint32_t CFSC12:2; /* CF 12 state configuration */ - uint32_t CFSC11:2; /* CF 11 state configuration */ - uint32_t CFSC10:2; /* CF 10 state configuration */ - uint32_t CFSC9:2; /* CF 9 state configuration */ - uint32_t CFSC8:2; /* CF 8 state configuration */ - uint32_t CFSC7:2; /* CF 7 state configuration */ - uint32_t CFSC6:2; /* CF 6 state configuration */ - uint32_t CFSC5:2; /* CF 5 state configuration */ - uint32_t CFSC4:2; /* CF 4 state configuration */ - uint32_t CFSC3:2; /* CF 3 state configuration */ - uint32_t CFSC2:2; /* CF 2 state configuration */ - uint32_t CFSC1:2; /* CF 1 state configuration */ - uint32_t CFSC0:2; /* CF 0 state configuration */ - } B; - } FCCU_CFS_CFG0_32B_tag; - - typedef union { /* FCCU CFS Configuration Register 1 */ - uint32_t R; - struct { - uint32_t CFSC31:2; /* CF 31 state configuration */ - uint32_t CFSC30:2; /* CF 30 state configuration */ - uint32_t CFSC29:2; /* CF 29 state configuration */ - uint32_t CFSC28:2; /* CF 28 state configuration */ - uint32_t CFSC27:2; /* CF 27 state configuration */ - uint32_t CFSC26:2; /* CF 26 state configuration */ - uint32_t CFSC25:2; /* CF 25 state configuration */ - uint32_t CFSC24:2; /* CF 24 state configuration */ - uint32_t CFSC23:2; /* CF 23 state configuration */ - uint32_t CFSC22:2; /* CF 22 state configuration */ - uint32_t CFSC21:2; /* CF 21 state configuration */ - uint32_t CFSC20:2; /* CF 20 state configuration */ - uint32_t CFSC19:2; /* CF 19 state configuration */ - uint32_t CFSC18:2; /* CF 18 state configuration */ - uint32_t CFSC17:2; /* CF 17 state configuration */ - uint32_t CFSC16:2; /* CF 16 state configuration */ - } B; - } FCCU_CFS_CFG1_32B_tag; - - typedef union { /* FCCU CFS Configuration Register 2 */ - uint32_t R; - struct { - uint32_t CFSC47:2; /* CF 47 state configuration */ - uint32_t CFSC46:2; /* CF 46 state configuration */ - uint32_t CFSC45:2; /* CF 45 state configuration */ - uint32_t CFSC44:2; /* CF 44 state configuration */ - uint32_t CFSC43:2; /* CF 43 state configuration */ - uint32_t CFSC42:2; /* CF 42 state configuration */ - uint32_t CFSC41:2; /* CF 41 state configuration */ - uint32_t CFSC40:2; /* CF 40 state configuration */ - uint32_t CFSC39:2; /* CF 39 state configuration */ - uint32_t CFSC38:2; /* CF 38 state configuration */ - uint32_t CFSC37:2; /* CF 37 state configuration */ - uint32_t CFSC36:2; /* CF 36 state configuration */ - uint32_t CFSC35:2; /* CF 35 state configuration */ - uint32_t CFSC34:2; /* CF 34 state configuration */ - uint32_t CFSC33:2; /* CF 33 state configuration */ - uint32_t CFSC32:2; /* CF 32 state configuration */ - } B; - } FCCU_CFS_CFG2_32B_tag; - - typedef union { /* FCCU CFS Configuration Register 3 */ - uint32_t R; - struct { - uint32_t CFSC63:2; /* CF 63 state configuration */ - uint32_t CFSC62:2; /* CF 62 state configuration */ - uint32_t CFSC61:2; /* CF 61 state configuration */ - uint32_t CFSC60:2; /* CF 60 state configuration */ - uint32_t CFSC59:2; /* CF 59 state configuration */ - uint32_t CFSC58:2; /* CF 58 state configuration */ - uint32_t CFSC57:2; /* CF 57 state configuration */ - uint32_t CFSC56:2; /* CF 56 state configuration */ - uint32_t CFSC55:2; /* CF 55 state configuration */ - uint32_t CFSC54:2; /* CF 54 state configuration */ - uint32_t CFSC53:2; /* CF 53 state configuration */ - uint32_t CFSC52:2; /* CF 52 state configuration */ - uint32_t CFSC51:2; /* CF 51 state configuration */ - uint32_t CFSC50:2; /* CF 50 state configuration */ - uint32_t CFSC49:2; /* CF 49 state configuration */ - uint32_t CFSC48:2; /* CF 48 state configuration */ - } B; - } FCCU_CFS_CFG3_32B_tag; - - typedef union { /* FCCU CFS Configuration Register 4 */ - uint32_t R; - struct { - uint32_t CFSC79:2; /* CF 79 state configuration */ - uint32_t CFSC78:2; /* CF 78 state configuration */ - uint32_t CFSC77:2; /* CF 77 state configuration */ - uint32_t CFSC76:2; /* CF 76 state configuration */ - uint32_t CFSC75:2; /* CF 75 state configuration */ - uint32_t CFSC74:2; /* CF 74 state configuration */ - uint32_t CFSC73:2; /* CF 73 state configuration */ - uint32_t CFSC72:2; /* CF 72 state configuration */ - uint32_t CFSC71:2; /* CF 71 state configuration */ - uint32_t CFSC70:2; /* CF 70 state configuration */ - uint32_t CFSC69:2; /* CF 69 state configuration */ - uint32_t CFSC68:2; /* CF 68 state configuration */ - uint32_t CFSC67:2; /* CF 67 state configuration */ - uint32_t CFSC66:2; /* CF 66 state configuration */ - uint32_t CFSC65:2; /* CF 65 state configuration */ - uint32_t CFSC64:2; /* CF 64 state configuration */ - } B; - } FCCU_CFS_CFG4_32B_tag; - - typedef union { /* FCCU CFS Configuration Register 5 */ - uint32_t R; - struct { - uint32_t CFSC95:2; /* CF 95 state configuration */ - uint32_t CFSC94:2; /* CF 94 state configuration */ - uint32_t CFSC93:2; /* CF 93 state configuration */ - uint32_t CFSC92:2; /* CF 92 state configuration */ - uint32_t CFSC91:2; /* CF 91 state configuration */ - uint32_t CFSC90:2; /* CF 90 state configuration */ - uint32_t CFSC89:2; /* CF 89 state configuration */ - uint32_t CFSC88:2; /* CF 88 state configuration */ - uint32_t CFSC87:2; /* CF 87 state configuration */ - uint32_t CFSC86:2; /* CF 86 state configuration */ - uint32_t CFSC85:2; /* CF 85 state configuration */ - uint32_t CFSC84:2; /* CF 84 state configuration */ - uint32_t CFSC83:2; /* CF 83 state configuration */ - uint32_t CFSC82:2; /* CF 82 state configuration */ - uint32_t CFSC81:2; /* CF 81 state configuration */ - uint32_t CFSC80:2; /* CF 80 state configuration */ - } B; - } FCCU_CFS_CFG5_32B_tag; - - typedef union { /* FCCU CFS Configuration Register 6 */ - uint32_t R; - struct { - uint32_t CFSC111:2; /* CF 111 state configuration */ - uint32_t CFSC110:2; /* CF 110 state configuration */ - uint32_t CFSC109:2; /* CF 109 state configuration */ - uint32_t CFSC108:2; /* CF 108 state configuration */ - uint32_t CFSC107:2; /* CF 107 state configuration */ - uint32_t CFSC106:2; /* CF 106 state configuration */ - uint32_t CFSC105:2; /* CF 105 state configuration */ - uint32_t CFSC104:2; /* CF 104 state configuration */ - uint32_t CFSC103:2; /* CF 103 state configuration */ - uint32_t CFSC102:2; /* CF 102 state configuration */ - uint32_t CFSC101:2; /* CF 101 state configuration */ - uint32_t CFSC100:2; /* CF 100 state configuration */ - uint32_t CFSC99:2; /* CF 99 state configuration */ - uint32_t CFSC98:2; /* CF 98 state configuration */ - uint32_t CFSC97:2; /* CF 97 state configuration */ - uint32_t CFSC96:2; /* CF 96 state configuration */ - } B; - } FCCU_CFS_CFG6_32B_tag; - - typedef union { /* FCCU CFS Configuration Register 7 */ - uint32_t R; - struct { - uint32_t CFSC127:2; /* CF 127 state configuration */ - uint32_t CFSC126:2; /* CF 126 state configuration */ - uint32_t CFSC125:2; /* CF 125 state configuration */ - uint32_t CFSC124:2; /* CF 124 state configuration */ - uint32_t CFSC123:2; /* CF 123 state configuration */ - uint32_t CFSC122:2; /* CF 122 state configuration */ - uint32_t CFSC121:2; /* CF 121 state configuration */ - uint32_t CFSC120:2; /* CF 120 state configuration */ - uint32_t CFSC119:2; /* CF 119 state configuration */ - uint32_t CFSC118:2; /* CF 118 state configuration */ - uint32_t CFSC117:2; /* CF 117 state configuration */ - uint32_t CFSC116:2; /* CF 116 state configuration */ - uint32_t CFSC115:2; /* CF 115 state configuration */ - uint32_t CFSC114:2; /* CF 114 state configuration */ - uint32_t CFSC113:2; /* CF 113 state configuration */ - uint32_t CFSC112:2; /* CF 112 state configuration */ - } B; - } FCCU_CFS_CFG7_32B_tag; - - typedef union { /* FCCU NCFS Configuration Register 0 */ - uint32_t R; - struct { - uint32_t NCFSC15:2; /* NCF 15 state configuration */ - uint32_t NCFSC14:2; /* NCF 14 state configuration */ - uint32_t NCFSC13:2; /* NCF 13 state configuration */ - uint32_t NCFSC12:2; /* NCF 12 state configuration */ - uint32_t NCFSC11:2; /* NCF 11 state configuration */ - uint32_t NCFSC10:2; /* NCF 10 state configuration */ - uint32_t NCFSC9:2; /* NCF 9 state configuration */ - uint32_t NCFSC8:2; /* NCF 8 state configuration */ - uint32_t NCFSC7:2; /* NCF 7 state configuration */ - uint32_t NCFSC6:2; /* NCF 6 state configuration */ - uint32_t NCFSC5:2; /* NCF 5 state configuration */ - uint32_t NCFSC4:2; /* NCF 4 state configuration */ - uint32_t NCFSC3:2; /* NCF 3 state configuration */ - uint32_t NCFSC2:2; /* NCF 2 state configuration */ - uint32_t NCFSC1:2; /* NCF 1 state configuration */ - uint32_t NCFSC0:2; /* NCF 0 state configuration */ - } B; - } FCCU_NCFS_CFG0_32B_tag; - - typedef union { /* FCCU NCFS Configuration Register 1 */ - uint32_t R; - struct { - uint32_t NCFSC31:2; /* NCF 31 state configuration */ - uint32_t NCFSC30:2; /* NCF 30 state configuration */ - uint32_t NCFSC29:2; /* NCF 29 state configuration */ - uint32_t NCFSC28:2; /* NCF 28 state configuration */ - uint32_t NCFSC27:2; /* NCF 27 state configuration */ - uint32_t NCFSC26:2; /* NCF 26 state configuration */ - uint32_t NCFSC25:2; /* NCF 25 state configuration */ - uint32_t NCFSC24:2; /* NCF 24 state configuration */ - uint32_t NCFSC23:2; /* NCF 23 state configuration */ - uint32_t NCFSC22:2; /* NCF 22 state configuration */ - uint32_t NCFSC21:2; /* NCF 21 state configuration */ - uint32_t NCFSC20:2; /* NCF 20 state configuration */ - uint32_t NCFSC19:2; /* NCF 19 state configuration */ - uint32_t NCFSC18:2; /* NCF 18 state configuration */ - uint32_t NCFSC17:2; /* NCF 17 state configuration */ - uint32_t NCFSC16:2; /* NCF 16 state configuration */ - } B; - } FCCU_NCFS_CFG1_32B_tag; - - typedef union { /* FCCU NCFS Configuration Register 2 */ - uint32_t R; - struct { - uint32_t NCFSC47:2; /* NCF 47 state configuration */ - uint32_t NCFSC46:2; /* NCF 46 state configuration */ - uint32_t NCFSC45:2; /* NCF 45 state configuration */ - uint32_t NCFSC44:2; /* NCF 44 state configuration */ - uint32_t NCFSC43:2; /* NCF 43 state configuration */ - uint32_t NCFSC42:2; /* NCF 42 state configuration */ - uint32_t NCFSC41:2; /* NCF 41 state configuration */ - uint32_t NCFSC40:2; /* NCF 40 state configuration */ - uint32_t NCFSC39:2; /* NCF 39 state configuration */ - uint32_t NCFSC38:2; /* NCF 38 state configuration */ - uint32_t NCFSC37:2; /* NCF 37 state configuration */ - uint32_t NCFSC36:2; /* NCF 36 state configuration */ - uint32_t NCFSC35:2; /* NCF 35 state configuration */ - uint32_t NCFSC34:2; /* NCF 34 state configuration */ - uint32_t NCFSC33:2; /* NCF 33 state configuration */ - uint32_t NCFSC32:2; /* NCF 32 state configuration */ - } B; - } FCCU_NCFS_CFG2_32B_tag; - - typedef union { /* FCCU NCFS Configuration Register 3 */ - uint32_t R; - struct { - uint32_t NCFSC63:2; /* NCF 63 state configuration */ - uint32_t NCFSC62:2; /* NCF 62 state configuration */ - uint32_t NCFSC61:2; /* NCF 61 state configuration */ - uint32_t NCFSC60:2; /* NCF 60 state configuration */ - uint32_t NCFSC59:2; /* NCF 59 state configuration */ - uint32_t NCFSC58:2; /* NCF 58 state configuration */ - uint32_t NCFSC57:2; /* NCF 57 state configuration */ - uint32_t NCFSC56:2; /* NCF 56 state configuration */ - uint32_t NCFSC55:2; /* NCF 55 state configuration */ - uint32_t NCFSC54:2; /* NCF 54 state configuration */ - uint32_t NCFSC53:2; /* NCF 53 state configuration */ - uint32_t NCFSC52:2; /* NCF 52 state configuration */ - uint32_t NCFSC51:2; /* NCF 51 state configuration */ - uint32_t NCFSC50:2; /* NCF 50 state configuration */ - uint32_t NCFSC49:2; /* NCF 49 state configuration */ - uint32_t NCFSC48:2; /* NCF 48 state configuration */ - } B; - } FCCU_NCFS_CFG3_32B_tag; - - typedef union { /* FCCU NCFS Configuration Register 4 */ - uint32_t R; - struct { - uint32_t NCFSC79:2; /* NCF 79 state configuration */ - uint32_t NCFSC78:2; /* NCF 78 state configuration */ - uint32_t NCFSC77:2; /* NCF 77 state configuration */ - uint32_t NCFSC76:2; /* NCF 76 state configuration */ - uint32_t NCFSC75:2; /* NCF 75 state configuration */ - uint32_t NCFSC74:2; /* NCF 74 state configuration */ - uint32_t NCFSC73:2; /* NCF 73 state configuration */ - uint32_t NCFSC72:2; /* NCF 72 state configuration */ - uint32_t NCFSC71:2; /* NCF 71 state configuration */ - uint32_t NCFSC70:2; /* NCF 70 state configuration */ - uint32_t NCFSC69:2; /* NCF 69 state configuration */ - uint32_t NCFSC68:2; /* NCF 68 state configuration */ - uint32_t NCFSC67:2; /* NCF 67 state configuration */ - uint32_t NCFSC66:2; /* NCF 66 state configuration */ - uint32_t NCFSC65:2; /* NCF 65 state configuration */ - uint32_t NCFSC64:2; /* NCF 64 state configuration */ - } B; - } FCCU_NCFS_CFG4_32B_tag; - - typedef union { /* FCCU NCFS Configuration Register 5 */ - uint32_t R; - struct { - uint32_t NCFSC95:2; /* NCF 95 state configuration */ - uint32_t NCFSC94:2; /* NCF 94 state configuration */ - uint32_t NCFSC93:2; /* NCF 93 state configuration */ - uint32_t NCFSC92:2; /* NCF 92 state configuration */ - uint32_t NCFSC91:2; /* NCF 91 state configuration */ - uint32_t NCFSC90:2; /* NCF 90 state configuration */ - uint32_t NCFSC89:2; /* NCF 89 state configuration */ - uint32_t NCFSC88:2; /* NCF 88 state configuration */ - uint32_t NCFSC87:2; /* NCF 87 state configuration */ - uint32_t NCFSC86:2; /* NCF 86 state configuration */ - uint32_t NCFSC85:2; /* NCF 85 state configuration */ - uint32_t NCFSC84:2; /* NCF 84 state configuration */ - uint32_t NCFSC83:2; /* NCF 83 state configuration */ - uint32_t NCFSC82:2; /* NCF 82 state configuration */ - uint32_t NCFSC81:2; /* NCF 81 state configuration */ - uint32_t NCFSC80:2; /* NCF 80 state configuration */ - } B; - } FCCU_NCFS_CFG5_32B_tag; - - typedef union { /* FCCU NCFS Configuration Register 6 */ - uint32_t R; - struct { - uint32_t NCFSC111:2; /* NCF 111 state configuration */ - uint32_t NCFSC110:2; /* NCF 110 state configuration */ - uint32_t NCFSC109:2; /* NCF 109 state configuration */ - uint32_t NCFSC108:2; /* NCF 108 state configuration */ - uint32_t NCFSC107:2; /* NCF 107 state configuration */ - uint32_t NCFSC106:2; /* NCF 106 state configuration */ - uint32_t NCFSC105:2; /* NCF 105 state configuration */ - uint32_t NCFSC104:2; /* NCF 104 state configuration */ - uint32_t NCFSC103:2; /* NCF 103 state configuration */ - uint32_t NCFSC102:2; /* NCF 102 state configuration */ - uint32_t NCFSC101:2; /* NCF 101 state configuration */ - uint32_t NCFSC100:2; /* NCF 100 state configuration */ - uint32_t NCFSC99:2; /* NCF 99 state configuration */ - uint32_t NCFSC98:2; /* NCF 98 state configuration */ - uint32_t NCFSC97:2; /* NCF 97 state configuration */ - uint32_t NCFSC96:2; /* NCF 96 state configuration */ - } B; - } FCCU_NCFS_CFG6_32B_tag; - - typedef union { /* FCCU NCFS Configuration Register 7 */ - uint32_t R; - struct { - uint32_t NCFSC127:2; /* NCF 127 state configuration */ - uint32_t NCFSC126:2; /* NCF 126 state configuration */ - uint32_t NCFSC125:2; /* NCF 125 state configuration */ - uint32_t NCFSC124:2; /* NCF 124 state configuration */ - uint32_t NCFSC123:2; /* NCF 123 state configuration */ - uint32_t NCFSC122:2; /* NCF 122 state configuration */ - uint32_t NCFSC121:2; /* NCF 121 state configuration */ - uint32_t NCFSC120:2; /* NCF 120 state configuration */ - uint32_t NCFSC119:2; /* NCF 119 state configuration */ - uint32_t NCFSC118:2; /* NCF 118 state configuration */ - uint32_t NCFSC117:2; /* NCF 117 state configuration */ - uint32_t NCFSC116:2; /* NCF 116 state configuration */ - uint32_t NCFSC115:2; /* NCF 115 state configuration */ - uint32_t NCFSC114:2; /* NCF 114 state configuration */ - uint32_t NCFSC113:2; /* NCF 113 state configuration */ - uint32_t NCFSC112:2; /* NCF 112 state configuration */ - } B; - } FCCU_NCFS_CFG7_32B_tag; - - typedef union { /* FCCU CF Status Register 0 */ - uint32_t R; - struct { - uint32_t CFS31:1; /* CF 31 status */ - uint32_t CFS30:1; /* CF 30 status */ - uint32_t CFS29:1; /* CF 29 status */ - uint32_t CFS28:1; /* CF 28 status */ - uint32_t CFS27:1; /* CF 27 status */ - uint32_t CFS26:1; /* CF 26 status */ - uint32_t CFS25:1; /* CF 25 status */ - uint32_t CFS24:1; /* CF 24 status */ - uint32_t CFS23:1; /* CF 23 status */ - uint32_t CFS22:1; /* CF 22 status */ - uint32_t CFS21:1; /* CF 21 status */ - uint32_t CFS20:1; /* CF 20 status */ - uint32_t CFS19:1; /* CF 19 status */ - uint32_t CFS18:1; /* CF 18 status */ - uint32_t CFS17:1; /* CF 17 status */ - uint32_t CFS16:1; /* CF 16 status */ - uint32_t CFS15:1; /* CF 15 status */ - uint32_t CFS14:1; /* CF 14 status */ - uint32_t CFS13:1; /* CF 13 status */ - uint32_t CFS12:1; /* CF 12 status */ - uint32_t CFS11:1; /* CF 11 status */ - uint32_t CFS10:1; /* CF 10 status */ - uint32_t CFS9:1; /* CF 9 status */ - uint32_t CFS8:1; /* CF 8 status */ - uint32_t CFS7:1; /* CF 7 status */ - uint32_t CFS6:1; /* CF 6 status */ - uint32_t CFS5:1; /* CF 5 status */ - uint32_t CFS4:1; /* CF 4 status */ - uint32_t CFS3:1; /* CF 3 status */ - uint32_t CFS2:1; /* CF 2 status */ - uint32_t CFS1:1; /* CF 1 status */ - uint32_t CFS0:1; /* CF 0 status */ - } B; - } FCCU_CFS0_32B_tag; - - typedef union { /* FCCU CF Status Register 1 */ - uint32_t R; - struct { - uint32_t CFS63:1; /* CF 63 status */ - uint32_t CFS62:1; /* CF 62 status */ - uint32_t CFS61:1; /* CF 61 status */ - uint32_t CFS60:1; /* CF 60 status */ - uint32_t CFS59:1; /* CF 59 status */ - uint32_t CFS58:1; /* CF 58 status */ - uint32_t CFS57:1; /* CF 57 status */ - uint32_t CFS56:1; /* CF 56 status */ - uint32_t CFS55:1; /* CF 55 status */ - uint32_t CFS54:1; /* CF 54 status */ - uint32_t CFS53:1; /* CF 53 status */ - uint32_t CFS52:1; /* CF 52 status */ - uint32_t CFS51:1; /* CF 51 status */ - uint32_t CFS50:1; /* CF 50 status */ - uint32_t CFS49:1; /* CF 49 status */ - uint32_t CFS48:1; /* CF 48 status */ - uint32_t CFS47:1; /* CF 47 status */ - uint32_t CFS46:1; /* CF 46 status */ - uint32_t CFS45:1; /* CF 45 status */ - uint32_t CFS44:1; /* CF 44 status */ - uint32_t CFS43:1; /* CF 43 status */ - uint32_t CFS42:1; /* CF 42 status */ - uint32_t CFS41:1; /* CF 41 status */ - uint32_t CFS40:1; /* CF 40 status */ - uint32_t CFS39:1; /* CF 39 status */ - uint32_t CFS38:1; /* CF 38 status */ - uint32_t CFS37:1; /* CF 37 status */ - uint32_t CFS36:1; /* CF 36 status */ - uint32_t CFS35:1; /* CF 35 status */ - uint32_t CFS34:1; /* CF 34 status */ - uint32_t CFS33:1; /* CF 33 status */ - uint32_t CFS32:1; /* CF 32 status */ - } B; - } FCCU_CFS1_32B_tag; - - typedef union { /* FCCU CF Status Register 2 */ - uint32_t R; - struct { - uint32_t CFS95:1; /* CF 95 status */ - uint32_t CFS94:1; /* CF 94 status */ - uint32_t CFS93:1; /* CF 93 status */ - uint32_t CFS92:1; /* CF 92 status */ - uint32_t CFS91:1; /* CF 91 status */ - uint32_t CFS90:1; /* CF 90 status */ - uint32_t CFS89:1; /* CF 89 status */ - uint32_t CFS88:1; /* CF 88 status */ - uint32_t CFS87:1; /* CF 87 status */ - uint32_t CFS86:1; /* CF 86 status */ - uint32_t CFS85:1; /* CF 85 status */ - uint32_t CFS84:1; /* CF 84 status */ - uint32_t CFS83:1; /* CF 83 status */ - uint32_t CFS82:1; /* CF 82 status */ - uint32_t CFS81:1; /* CF 81 status */ - uint32_t CFS80:1; /* CF 80 status */ - uint32_t CFS79:1; /* CF 79 status */ - uint32_t CFS78:1; /* CF 78 status */ - uint32_t CFS77:1; /* CF 77 status */ - uint32_t CFS76:1; /* CF 76 status */ - uint32_t CFS75:1; /* CF 75 status */ - uint32_t CFS74:1; /* CF 74 status */ - uint32_t CFS73:1; /* CF 73 status */ - uint32_t CFS72:1; /* CF 72 status */ - uint32_t CFS71:1; /* CF 71 status */ - uint32_t CFS70:1; /* CF 70 status */ - uint32_t CFS69:1; /* CF 69 status */ - uint32_t CFS68:1; /* CF 68 status */ - uint32_t CFS67:1; /* CF 67 status */ - uint32_t CFS66:1; /* CF 66 status */ - uint32_t CFS65:1; /* CF 65 status */ - uint32_t CFS64:1; /* CF 64 status */ - } B; - } FCCU_CFS2_32B_tag; - - typedef union { /* FCCU CF Status Register 3 */ - uint32_t R; - struct { - uint32_t CFS127:1; /* CF 127 status */ - uint32_t CFS126:1; /* CF 126 status */ - uint32_t CFS125:1; /* CF 125 status */ - uint32_t CFS124:1; /* CF 124 status */ - uint32_t CFS123:1; /* CF 123 status */ - uint32_t CFS122:1; /* CF 122 status */ - uint32_t CFS121:1; /* CF 121 status */ - uint32_t CFS120:1; /* CF 120 status */ - uint32_t CFS119:1; /* CF 119 status */ - uint32_t CFS118:1; /* CF 118 status */ - uint32_t CFS117:1; /* CF 117 status */ - uint32_t CFS116:1; /* CF 116 status */ - uint32_t CFS115:1; /* CF 115 status */ - uint32_t CFS114:1; /* CF 114 status */ - uint32_t CFS113:1; /* CF 113 status */ - uint32_t CFS112:1; /* CF 112 status */ - uint32_t CFS111:1; /* CF 111 status */ - uint32_t CFS110:1; /* CF 110 status */ - uint32_t CFS109:1; /* CF 109 status */ - uint32_t CFS108:1; /* CF 108 status */ - uint32_t CFS107:1; /* CF 107 status */ - uint32_t CFS106:1; /* CF 106 status */ - uint32_t CFS105:1; /* CF 105 status */ - uint32_t CFS104:1; /* CF 104 status */ - uint32_t CFS103:1; /* CF 103 status */ - uint32_t CFS102:1; /* CF 102 status */ - uint32_t CFS101:1; /* CF 101 status */ - uint32_t CFS100:1; /* CF 100 status */ - uint32_t CFS99:1; /* CF 99 status */ - uint32_t CFS98:1; /* CF 98 status */ - uint32_t CFS97:1; /* CF 97 status */ - uint32_t CFS96:1; /* CF 96 status */ - } B; - } FCCU_CFS3_32B_tag; - - typedef union { /* FCCU_CFK - FCCU CF Key Register */ - uint32_t R; - } FCCU_CFK_32B_tag; - - typedef union { /* FCCU NCF Status Register 0 */ - uint32_t R; - struct { - uint32_t NCFS31:1; /* NCF 31 status */ - uint32_t NCFS30:1; /* NCF 30 status */ - uint32_t NCFS29:1; /* NCF 29 status */ - uint32_t NCFS28:1; /* NCF 28 status */ - uint32_t NCFS27:1; /* NCF 27 status */ - uint32_t NCFS26:1; /* NCF 26 status */ - uint32_t NCFS25:1; /* NCF 25 status */ - uint32_t NCFS24:1; /* NCF 24 status */ - uint32_t NCFS23:1; /* NCF 23 status */ - uint32_t NCFS22:1; /* NCF 22 status */ - uint32_t NCFS21:1; /* NCF 21 status */ - uint32_t NCFS20:1; /* NCF 20 status */ - uint32_t NCFS19:1; /* NCF 19 status */ - uint32_t NCFS18:1; /* NCF 18 status */ - uint32_t NCFS17:1; /* NCF 17 status */ - uint32_t NCFS16:1; /* NCF 16 status */ - uint32_t NCFS15:1; /* NCF 15 status */ - uint32_t NCFS14:1; /* NCF 14 status */ - uint32_t NCFS13:1; /* NCF 13 status */ - uint32_t NCFS12:1; /* NCF 12 status */ - uint32_t NCFS11:1; /* NCF 11 status */ - uint32_t NCFS10:1; /* NCF 10 status */ - uint32_t NCFS9:1; /* NCF 9 status */ - uint32_t NCFS8:1; /* NCF 8 status */ - uint32_t NCFS7:1; /* NCF 7 status */ - uint32_t NCFS6:1; /* NCF 6 status */ - uint32_t NCFS5:1; /* NCF 5 status */ - uint32_t NCFS4:1; /* NCF 4 status */ - uint32_t NCFS3:1; /* NCF 3 status */ - uint32_t NCFS2:1; /* NCF 2 status */ - uint32_t NCFS1:1; /* NCF 1 status */ - uint32_t NCFS0:1; /* NCF 0 status */ - } B; - } FCCU_NCFS0_32B_tag; - - typedef union { /* FCCU NCF Status Register 1 */ - uint32_t R; - struct { - uint32_t NCFS63:1; /* NCF 63 status */ - uint32_t NCFS62:1; /* NCF 62 status */ - uint32_t NCFS61:1; /* NCF 61 status */ - uint32_t NCFS60:1; /* NCF 60 status */ - uint32_t NCFS59:1; /* NCF 59 status */ - uint32_t NCFS58:1; /* NCF 58 status */ - uint32_t NCFS57:1; /* NCF 57 status */ - uint32_t NCFS56:1; /* NCF 56 status */ - uint32_t NCFS55:1; /* NCF 55 status */ - uint32_t NCFS54:1; /* NCF 54 status */ - uint32_t NCFS53:1; /* NCF 53 status */ - uint32_t NCFS52:1; /* NCF 52 status */ - uint32_t NCFS51:1; /* NCF 51 status */ - uint32_t NCFS50:1; /* NCF 50 status */ - uint32_t NCFS49:1; /* NCF 49 status */ - uint32_t NCFS48:1; /* NCF 48 status */ - uint32_t NCFS47:1; /* NCF 47 status */ - uint32_t NCFS46:1; /* NCF 46 status */ - uint32_t NCFS45:1; /* NCF 45 status */ - uint32_t NCFS44:1; /* NCF 44 status */ - uint32_t NCFS43:1; /* NCF 43 status */ - uint32_t NCFS42:1; /* NCF 42 status */ - uint32_t NCFS41:1; /* NCF 41 status */ - uint32_t NCFS40:1; /* NCF 40 status */ - uint32_t NCFS39:1; /* NCF 39 status */ - uint32_t NCFS38:1; /* NCF 38 status */ - uint32_t NCFS37:1; /* NCF 37 status */ - uint32_t NCFS36:1; /* NCF 36 status */ - uint32_t NCFS35:1; /* NCF 35 status */ - uint32_t NCFS34:1; /* NCF 34 status */ - uint32_t NCFS33:1; /* NCF 33 status */ - uint32_t NCFS32:1; /* NCF 32 status */ - } B; - } FCCU_NCFS1_32B_tag; - - typedef union { /* FCCU NCF Status Register 2 */ - uint32_t R; - struct { - uint32_t NCFS95:1; /* NCF 95 status */ - uint32_t NCFS94:1; /* NCF 94 status */ - uint32_t NCFS93:1; /* NCF 93 status */ - uint32_t NCFS92:1; /* NCF 92 status */ - uint32_t NCFS91:1; /* NCF 91 status */ - uint32_t NCFS90:1; /* NCF 90 status */ - uint32_t NCFS89:1; /* NCF 89 status */ - uint32_t NCFS88:1; /* NCF 88 status */ - uint32_t NCFS87:1; /* NCF 87 status */ - uint32_t NCFS86:1; /* NCF 86 status */ - uint32_t NCFS85:1; /* NCF 85 status */ - uint32_t NCFS84:1; /* NCF 84 status */ - uint32_t NCFS83:1; /* NCF 83 status */ - uint32_t NCFS82:1; /* NCF 82 status */ - uint32_t NCFS81:1; /* NCF 81 status */ - uint32_t NCFS80:1; /* NCF 80 status */ - uint32_t NCFS79:1; /* NCF 79 status */ - uint32_t NCFS78:1; /* NCF 78 status */ - uint32_t NCFS77:1; /* NCF 77 status */ - uint32_t NCFS76:1; /* NCF 76 status */ - uint32_t NCFS75:1; /* NCF 75 status */ - uint32_t NCFS74:1; /* NCF 74 status */ - uint32_t NCFS73:1; /* NCF 73 status */ - uint32_t NCFS72:1; /* NCF 72 status */ - uint32_t NCFS71:1; /* NCF 71 status */ - uint32_t NCFS70:1; /* NCF 70 status */ - uint32_t NCFS69:1; /* NCF 69 status */ - uint32_t NCFS68:1; /* NCF 68 status */ - uint32_t NCFS67:1; /* NCF 67 status */ - uint32_t NCFS66:1; /* NCF 66 status */ - uint32_t NCFS65:1; /* NCF 65 status */ - uint32_t NCFS64:1; /* NCF 64 status */ - } B; - } FCCU_NCFS2_32B_tag; - - typedef union { /* FCCU NCF Status Register 3 */ - uint32_t R; - struct { - uint32_t NCFS127:1; /* NCF 127 status */ - uint32_t NCFS126:1; /* NCF 126 status */ - uint32_t NCFS125:1; /* NCF 125 status */ - uint32_t NCFS124:1; /* NCF 124 status */ - uint32_t NCFS123:1; /* NCF 123 status */ - uint32_t NCFS122:1; /* NCF 122 status */ - uint32_t NCFS121:1; /* NCF 121 status */ - uint32_t NCFS120:1; /* NCF 120 status */ - uint32_t NCFS119:1; /* NCF 119 status */ - uint32_t NCFS118:1; /* NCF 118 status */ - uint32_t NCFS117:1; /* NCF 117 status */ - uint32_t NCFS116:1; /* NCF 116 status */ - uint32_t NCFS115:1; /* NCF 115 status */ - uint32_t NCFS114:1; /* NCF 114 status */ - uint32_t NCFS113:1; /* NCF 113 status */ - uint32_t NCFS112:1; /* NCF 112 status */ - uint32_t NCFS111:1; /* NCF 111 status */ - uint32_t NCFS110:1; /* NCF 110 status */ - uint32_t NCFS109:1; /* NCF 109 status */ - uint32_t NCFS108:1; /* NCF 108 status */ - uint32_t NCFS107:1; /* NCF 107 status */ - uint32_t NCFS106:1; /* NCF 106 status */ - uint32_t NCFS105:1; /* NCF 105 status */ - uint32_t NCFS104:1; /* NCF 104 status */ - uint32_t NCFS103:1; /* NCF 103 status */ - uint32_t NCFS102:1; /* NCF 102 status */ - uint32_t NCFS101:1; /* NCF 101 status */ - uint32_t NCFS100:1; /* NCF 100 status */ - uint32_t NCFS99:1; /* NCF 99 status */ - uint32_t NCFS98:1; /* NCF 98 status */ - uint32_t NCFS97:1; /* NCF 97 status */ - uint32_t NCFS96:1; /* NCF 96 status */ - } B; - } FCCU_NCFS3_32B_tag; - - typedef union { /* FCCU_NCFK - FCCU NCF Key Register */ - uint32_t R; - } FCCU_NCFK_32B_tag; - - typedef union { /* FCCU NCF Enable Register 0 */ - uint32_t R; - struct { - uint32_t NCFE31:1; /* NCF 31 enable */ - uint32_t NCFE30:1; /* NCF 30 enable */ - uint32_t NCFE29:1; /* NCF 29 enable */ - uint32_t NCFE28:1; /* NCF 28 enable */ - uint32_t NCFE27:1; /* NCF 27 enable */ - uint32_t NCFE26:1; /* NCF 26 enable */ - uint32_t NCFE25:1; /* NCF 25 enable */ - uint32_t NCFE24:1; /* NCF 24 enable */ - uint32_t NCFE23:1; /* NCF 23 enable */ - uint32_t NCFE22:1; /* NCF 22 enable */ - uint32_t NCFE21:1; /* NCF 21 enable */ - uint32_t NCFE20:1; /* NCF 20 enable */ - uint32_t NCFE19:1; /* NCF 19 enable */ - uint32_t NCFE18:1; /* NCF 18 enable */ - uint32_t NCFE17:1; /* NCF 17 enable */ - uint32_t NCFE16:1; /* NCF 16 enable */ - uint32_t NCFE15:1; /* NCF 15 enable */ - uint32_t NCFE14:1; /* NCF 14 enable */ - uint32_t NCFE13:1; /* NCF 13 enable */ - uint32_t NCFE12:1; /* NCF 12 enable */ - uint32_t NCFE11:1; /* NCF 11 enable */ - uint32_t NCFE10:1; /* NCF 10 enable */ - uint32_t NCFE9:1; /* NCF 9 enable */ - uint32_t NCFE8:1; /* NCF 8 enable */ - uint32_t NCFE7:1; /* NCF 7 enable */ - uint32_t NCFE6:1; /* NCF 6 enable */ - uint32_t NCFE5:1; /* NCF 5 enable */ - uint32_t NCFE4:1; /* NCF 4 enable */ - uint32_t NCFE3:1; /* NCF 3 enable */ - uint32_t NCFE2:1; /* NCF 2 enable */ - uint32_t NCFE1:1; /* NCF 1 enable */ - uint32_t NCFE0:1; /* NCF 0 enable */ - } B; - } FCCU_NCFE0_32B_tag; - - typedef union { /* FCCU NCF Enable Register 1 */ - uint32_t R; - struct { - uint32_t NCFE63:1; /* NCF 63 enable */ - uint32_t NCFE62:1; /* NCF 62 enable */ - uint32_t NCFE61:1; /* NCF 61 enable */ - uint32_t NCFE60:1; /* NCF 60 enable */ - uint32_t NCFE59:1; /* NCF 59 enable */ - uint32_t NCFE58:1; /* NCF 58 enable */ - uint32_t NCFE57:1; /* NCF 57 enable */ - uint32_t NCFE56:1; /* NCF 56 enable */ - uint32_t NCFE55:1; /* NCF 55 enable */ - uint32_t NCFE54:1; /* NCF 54 enable */ - uint32_t NCFE53:1; /* NCF 53 enable */ - uint32_t NCFE52:1; /* NCF 52 enable */ - uint32_t NCFE51:1; /* NCF 51 enable */ - uint32_t NCFE50:1; /* NCF 50 enable */ - uint32_t NCFE49:1; /* NCF 49 enable */ - uint32_t NCFE48:1; /* NCF 48 enable */ - uint32_t NCFE47:1; /* NCF 47 enable */ - uint32_t NCFE46:1; /* NCF 46 enable */ - uint32_t NCFE45:1; /* NCF 45 enable */ - uint32_t NCFE44:1; /* NCF 44 enable */ - uint32_t NCFE43:1; /* NCF 43 enable */ - uint32_t NCFE42:1; /* NCF 42 enable */ - uint32_t NCFE41:1; /* NCF 41 enable */ - uint32_t NCFE40:1; /* NCF 40 enable */ - uint32_t NCFE39:1; /* NCF 39 enable */ - uint32_t NCFE38:1; /* NCF 38 enable */ - uint32_t NCFE37:1; /* NCF 37 enable */ - uint32_t NCFE36:1; /* NCF 36 enable */ - uint32_t NCFE35:1; /* NCF 35 enable */ - uint32_t NCFE34:1; /* NCF 34 enable */ - uint32_t NCFE33:1; /* NCF 33 enable */ - uint32_t NCFE32:1; /* NCF 32 enable */ - } B; - } FCCU_NCFE1_32B_tag; - - typedef union { /* FCCU NCF Enable Register 2 */ - uint32_t R; - struct { - uint32_t NCFE95:1; /* NCF 95 enable */ - uint32_t NCFE94:1; /* NCF 94 enable */ - uint32_t NCFE93:1; /* NCF 93 enable */ - uint32_t NCFE92:1; /* NCF 92 enable */ - uint32_t NCFE91:1; /* NCF 91 enable */ - uint32_t NCFE90:1; /* NCF 90 enable */ - uint32_t NCFE89:1; /* NCF 89 enable */ - uint32_t NCFE88:1; /* NCF 88 enable */ - uint32_t NCFE87:1; /* NCF 87 enable */ - uint32_t NCFE86:1; /* NCF 86 enable */ - uint32_t NCFE85:1; /* NCF 85 enable */ - uint32_t NCFE84:1; /* NCF 84 enable */ - uint32_t NCFE83:1; /* NCF 83 enable */ - uint32_t NCFE82:1; /* NCF 82 enable */ - uint32_t NCFE81:1; /* NCF 81 enable */ - uint32_t NCFE80:1; /* NCF 80 enable */ - uint32_t NCFE79:1; /* NCF 79 enable */ - uint32_t NCFE78:1; /* NCF 78 enable */ - uint32_t NCFE77:1; /* NCF 77 enable */ - uint32_t NCFE76:1; /* NCF 76 enable */ - uint32_t NCFE75:1; /* NCF 75 enable */ - uint32_t NCFE74:1; /* NCF 74 enable */ - uint32_t NCFE73:1; /* NCF 73 enable */ - uint32_t NCFE72:1; /* NCF 72 enable */ - uint32_t NCFE71:1; /* NCF 71 enable */ - uint32_t NCFE70:1; /* NCF 70 enable */ - uint32_t NCFE69:1; /* NCF 69 enable */ - uint32_t NCFE68:1; /* NCF 68 enable */ - uint32_t NCFE67:1; /* NCF 67 enable */ - uint32_t NCFE66:1; /* NCF 66 enable */ - uint32_t NCFE65:1; /* NCF 65 enable */ - uint32_t NCFE64:1; /* NCF 64 enable */ - } B; - } FCCU_NCFE2_32B_tag; - - typedef union { /* FCCU NCF Enable Register 3 */ - uint32_t R; - struct { - uint32_t NCFE127:1; /* NCF 127 enable */ - uint32_t NCFE126:1; /* NCF 126 enable */ - uint32_t NCFE125:1; /* NCF 125 enable */ - uint32_t NCFE124:1; /* NCF 124 enable */ - uint32_t NCFE123:1; /* NCF 123 enable */ - uint32_t NCFE122:1; /* NCF 122 enable */ - uint32_t NCFE121:1; /* NCF 121 enable */ - uint32_t NCFE120:1; /* NCF 120 enable */ - uint32_t NCFE119:1; /* NCF 119 enable */ - uint32_t NCFE118:1; /* NCF 118 enable */ - uint32_t NCFE117:1; /* NCF 117 enable */ - uint32_t NCFE116:1; /* NCF 116 enable */ - uint32_t NCFE115:1; /* NCF 115 enable */ - uint32_t NCFE114:1; /* NCF 114 enable */ - uint32_t NCFE113:1; /* NCF 113 enable */ - uint32_t NCFE112:1; /* NCF 112 enable */ - uint32_t NCFE111:1; /* NCF 111 enable */ - uint32_t NCFE110:1; /* NCF 110 enable */ - uint32_t NCFE109:1; /* NCF 109 enable */ - uint32_t NCFE108:1; /* NCF 108 enable */ - uint32_t NCFE107:1; /* NCF 107 enable */ - uint32_t NCFE106:1; /* NCF 106 enable */ - uint32_t NCFE105:1; /* NCF 105 enable */ - uint32_t NCFE104:1; /* NCF 104 enable */ - uint32_t NCFE103:1; /* NCF 103 enable */ - uint32_t NCFE102:1; /* NCF 102 enable */ - uint32_t NCFE101:1; /* NCF 101 enable */ - uint32_t NCFE100:1; /* NCF 100 enable */ - uint32_t NCFE99:1; /* NCF 99 enable */ - uint32_t NCFE98:1; /* NCF 98 enable */ - uint32_t NCFE97:1; /* NCF 97 enable */ - uint32_t NCFE96:1; /* NCF 96 enable */ - } B; - } FCCU_NCFE3_32B_tag; - - typedef union { /* FCCU NCF Time-out Enable Register 0 */ - uint32_t R; - struct { - uint32_t NCFTOE31:1; /* NCF 31 time-out enable */ - uint32_t NCFTOE30:1; /* NCF 30 time-out enable */ - uint32_t NCFTOE29:1; /* NCF 29 time-out enable */ - uint32_t NCFTOE28:1; /* NCF 28 time-out enable */ - uint32_t NCFTOE27:1; /* NCF 27 time-out enable */ - uint32_t NCFTOE26:1; /* NCF 26 time-out enable */ - uint32_t NCFTOE25:1; /* NCF 25 time-out enable */ - uint32_t NCFTOE24:1; /* NCF 24 time-out enable */ - uint32_t NCFTOE23:1; /* NCF 23 time-out enable */ - uint32_t NCFTOE22:1; /* NCF 22 time-out enable */ - uint32_t NCFTOE21:1; /* NCF 21 time-out enable */ - uint32_t NCFTOE20:1; /* NCF 20 time-out enable */ - uint32_t NCFTOE19:1; /* NCF 19 time-out enable */ - uint32_t NCFTOE18:1; /* NCF 18 time-out enable */ - uint32_t NCFTOE17:1; /* NCF 17 time-out enable */ - uint32_t NCFTOE16:1; /* NCF 16 time-out enable */ - uint32_t NCFTOE15:1; /* NCF 15 time-out enable */ - uint32_t NCFTOE14:1; /* NCF 14 time-out enable */ - uint32_t NCFTOE13:1; /* NCF 13 time-out enable */ - uint32_t NCFTOE12:1; /* NCF 12 time-out enable */ - uint32_t NCFTOE11:1; /* NCF 11 time-out enable */ - uint32_t NCFTOE10:1; /* NCF 10 time-out enable */ - uint32_t NCFTOE9:1; /* NCF 9 time-out enable */ - uint32_t NCFTOE8:1; /* NCF 8 time-out enable */ - uint32_t NCFTOE7:1; /* NCF 7 time-out enable */ - uint32_t NCFTOE6:1; /* NCF 6 time-out enable */ - uint32_t NCFTOE5:1; /* NCF 5 time-out enable */ - uint32_t NCFTOE4:1; /* NCF 4 time-out enable */ - uint32_t NCFTOE3:1; /* NCF 3 time-out enable */ - uint32_t NCFTOE2:1; /* NCF 2 time-out enable */ - uint32_t NCFTOE1:1; /* NCF 1 time-out enable */ - uint32_t NCFTOE0:1; /* NCF 0 time-out enable */ - } B; - } FCCU_NCF_TOE0_32B_tag; - - typedef union { /* FCCU NCF Time-out Enable Register 1 */ - uint32_t R; - struct { - uint32_t NCFTOE63:1; /* NCF 63 time-out enable */ - uint32_t NCFTOE62:1; /* NCF 62 time-out enable */ - uint32_t NCFTOE61:1; /* NCF 61 time-out enable */ - uint32_t NCFTOE60:1; /* NCF 60 time-out enable */ - uint32_t NCFTOE59:1; /* NCF 59 time-out enable */ - uint32_t NCFTOE58:1; /* NCF 58 time-out enable */ - uint32_t NCFTOE57:1; /* NCF 57 time-out enable */ - uint32_t NCFTOE56:1; /* NCF 56 time-out enable */ - uint32_t NCFTOE55:1; /* NCF 55 time-out enable */ - uint32_t NCFTOE54:1; /* NCF 54 time-out enable */ - uint32_t NCFTOE53:1; /* NCF 53 time-out enable */ - uint32_t NCFTOE52:1; /* NCF 52 time-out enable */ - uint32_t NCFTOE51:1; /* NCF 51 time-out enable */ - uint32_t NCFTOE50:1; /* NCF 50 time-out enable */ - uint32_t NCFTOE49:1; /* NCF 49 time-out enable */ - uint32_t NCFTOE48:1; /* NCF 48 time-out enable */ - uint32_t NCFTOE47:1; /* NCF 47 time-out enable */ - uint32_t NCFTOE46:1; /* NCF 46 time-out enable */ - uint32_t NCFTOE45:1; /* NCF 45 time-out enable */ - uint32_t NCFTOE44:1; /* NCF 44 time-out enable */ - uint32_t NCFTOE43:1; /* NCF 43 time-out enable */ - uint32_t NCFTOE42:1; /* NCF 42 time-out enable */ - uint32_t NCFTOE41:1; /* NCF 41 time-out enable */ - uint32_t NCFTOE40:1; /* NCF 40 time-out enable */ - uint32_t NCFTOE39:1; /* NCF 39 time-out enable */ - uint32_t NCFTOE38:1; /* NCF 38 time-out enable */ - uint32_t NCFTOE37:1; /* NCF 37 time-out enable */ - uint32_t NCFTOE36:1; /* NCF 36 time-out enable */ - uint32_t NCFTOE35:1; /* NCF 35 time-out enable */ - uint32_t NCFTOE34:1; /* NCF 34 time-out enable */ - uint32_t NCFTOE33:1; /* NCF 33 time-out enable */ - uint32_t NCFTOE32:1; /* NCF 32 time-out enable */ - } B; - } FCCU_NCF_TOE1_32B_tag; - - typedef union { /* FCCU NCF Time-out Enable Register 2 */ - uint32_t R; - struct { - uint32_t NCFTOE95:1; /* NCF 95 time-out enable */ - uint32_t NCFTOE94:1; /* NCF 94 time-out enable */ - uint32_t NCFTOE93:1; /* NCF 93 time-out enable */ - uint32_t NCFTOE92:1; /* NCF 92 time-out enable */ - uint32_t NCFTOE91:1; /* NCF 91 time-out enable */ - uint32_t NCFTOE90:1; /* NCF 90 time-out enable */ - uint32_t NCFTOE89:1; /* NCF 89 time-out enable */ - uint32_t NCFTOE88:1; /* NCF 88 time-out enable */ - uint32_t NCFTOE87:1; /* NCF 87 time-out enable */ - uint32_t NCFTOE86:1; /* NCF 86 time-out enable */ - uint32_t NCFTOE85:1; /* NCF 85 time-out enable */ - uint32_t NCFTOE84:1; /* NCF 84 time-out enable */ - uint32_t NCFTOE83:1; /* NCF 83 time-out enable */ - uint32_t NCFTOE82:1; /* NCF 82 time-out enable */ - uint32_t NCFTOE81:1; /* NCF 81 time-out enable */ - uint32_t NCFTOE80:1; /* NCF 80 time-out enable */ - uint32_t NCFTOE79:1; /* NCF 79 time-out enable */ - uint32_t NCFTOE78:1; /* NCF 78 time-out enable */ - uint32_t NCFTOE77:1; /* NCF 77 time-out enable */ - uint32_t NCFTOE76:1; /* NCF 76 time-out enable */ - uint32_t NCFTOE75:1; /* NCF 75 time-out enable */ - uint32_t NCFTOE74:1; /* NCF 74 time-out enable */ - uint32_t NCFTOE73:1; /* NCF 73 time-out enable */ - uint32_t NCFTOE72:1; /* NCF 72 time-out enable */ - uint32_t NCFTOE71:1; /* NCF 71 time-out enable */ - uint32_t NCFTOE70:1; /* NCF 70 time-out enable */ - uint32_t NCFTOE69:1; /* NCF 69 time-out enable */ - uint32_t NCFTOE68:1; /* NCF 68 time-out enable */ - uint32_t NCFTOE67:1; /* NCF 67 time-out enable */ - uint32_t NCFTOE66:1; /* NCF 66 time-out enable */ - uint32_t NCFTOE65:1; /* NCF 65 time-out enable */ - uint32_t NCFTOE64:1; /* NCF 64 time-out enable */ - } B; - } FCCU_NCF_TOE2_32B_tag; - - typedef union { /* FCCU NCF Time-out Enable Register 3 */ - uint32_t R; - struct { - uint32_t NCFTOE127:1; /* NCF 127 time-out enable */ - uint32_t NCFTOE126:1; /* NCF 126 time-out enable */ - uint32_t NCFTOE125:1; /* NCF 125 time-out enable */ - uint32_t NCFTOE124:1; /* NCF 124 time-out enable */ - uint32_t NCFTOE123:1; /* NCF 123 time-out enable */ - uint32_t NCFTOE122:1; /* NCF 122 time-out enable */ - uint32_t NCFTOE121:1; /* NCF 121 time-out enable */ - uint32_t NCFTOE120:1; /* NCF 120 time-out enable */ - uint32_t NCFTOE119:1; /* NCF 119 time-out enable */ - uint32_t NCFTOE118:1; /* NCF 118 time-out enable */ - uint32_t NCFTOE117:1; /* NCF 117 time-out enable */ - uint32_t NCFTOE116:1; /* NCF 116 time-out enable */ - uint32_t NCFTOE115:1; /* NCF 115 time-out enable */ - uint32_t NCFTOE114:1; /* NCF 114 time-out enable */ - uint32_t NCFTOE113:1; /* NCF 113 time-out enable */ - uint32_t NCFTOE112:1; /* NCF 112 time-out enable */ - uint32_t NCFTOE111:1; /* NCF 111 time-out enable */ - uint32_t NCFTOE110:1; /* NCF 110 time-out enable */ - uint32_t NCFTOE109:1; /* NCF 109 time-out enable */ - uint32_t NCFTOE108:1; /* NCF 108 time-out enable */ - uint32_t NCFTOE107:1; /* NCF 107 time-out enable */ - uint32_t NCFTOE106:1; /* NCF 106 time-out enable */ - uint32_t NCFTOE105:1; /* NCF 105 time-out enable */ - uint32_t NCFTOE104:1; /* NCF 104 time-out enable */ - uint32_t NCFTOE103:1; /* NCF 103 time-out enable */ - uint32_t NCFTOE102:1; /* NCF 102 time-out enable */ - uint32_t NCFTOE101:1; /* NCF 101 time-out enable */ - uint32_t NCFTOE100:1; /* NCF 100 time-out enable */ - uint32_t NCFTOE99:1; /* NCF 99 time-out enable */ - uint32_t NCFTOE98:1; /* NCF 98 time-out enable */ - uint32_t NCFTOE97:1; /* NCF 97 time-out enable */ - uint32_t NCFTOE96:1; /* NCF 96 time-out enable */ - } B; - } FCCU_NCF_TOE3_32B_tag; - - typedef union { /* FCCU_NCF_TO - FCCU NCF Time-out Register */ - uint32_t R; - } FCCU_NCF_TO_32B_tag; - - typedef union { /* FCCU_CFG_TO - FCCU CFG Timeout Register */ - uint32_t R; - struct { - uint32_t:29; - uint32_t TO:3; /* Configuration time-out */ - } B; - } FCCU_CFG_TO_32B_tag; - - typedef union { /* FCCU_EINOUT - FCCU IO Control Register */ - uint32_t R; - struct { - uint32_t:26; - uint32_t EIN1:1; /* Error input 1 */ - uint32_t EIN0:1; /* Error input 0 */ - uint32_t:2; - uint32_t EOUT1:1; /* Error out 1 */ - uint32_t EOUT0:1; /* Error out 0 */ - } B; - } FCCU_EINOUT_32B_tag; - - typedef union { /* FCCU_STAT - FCCU Status Register */ - uint32_t R; - struct { - uint32_t:29; - uint32_t STATUS:3; /* FCCU status */ - } B; - } FCCU_STAT_32B_tag; - - typedef union { /* FCCU_NAFS - FCCU NA Freeze Status Register */ - uint32_t R; - struct { - uint32_t:24; - uint32_t N2AFSTATUS:8; /* Normal to Alarm Frozen Status */ - } B; - } FCCU_NAFS_32B_tag; - - typedef union { /* FCCU_AFFS - FCCU AF Freeze Status Register */ - uint32_t R; - struct { - uint32_t:22; - uint32_t AFFS_SRC:2; /* Fault source */ - uint32_t A2AFSTATUS:8; /* Alarm to Fault Frozen Status */ - } B; - } FCCU_AFFS_32B_tag; - - typedef union { /* FCCU_NFFS - FCCU NF Freeze Status Register */ - uint32_t R; - struct { - uint32_t:22; - uint32_t NFFS_SRC:2; /* Fault source */ - uint32_t NFFS_NFFS:8; /* Normal to Fault Frozen Status */ - } B; - } FCCU_NFFS_32B_tag; - - typedef union { /* FCCU_FAFS - FCCU FA Freeze Status Register */ - uint32_t R; - struct { - uint32_t:24; - uint32_t FAFS_FAFS:8; /* Fault to Normal Frozen Status */ - } B; - } FCCU_FAFS_32B_tag; - - typedef union { /* FCCU_SCFS - FCCU SC Freeze Status Register */ - uint32_t R; - struct { - uint32_t:30; - uint32_t RCCS1:1; /* RCC1 Status */ - uint32_t RCCS0:1; /* RCC0 Status */ - } B; - } FCCU_SCFS_32B_tag; - - typedef union { /* FCCU_CFF - FCCU CF Fake Register */ - uint32_t R; - struct { - uint32_t:25; - uint32_t FCFC:7; /* Fake critical fault code */ - } B; - } FCCU_CFF_32B_tag; - - typedef union { /* FCCU_NCFF - FCCU NCF Fake Register */ - uint32_t R; - struct { - uint32_t:25; - uint32_t FNCFC:7; /* Fake non-critical fault code */ - } B; - } FCCU_NCFF_32B_tag; - - typedef union { /* FCCU_IRQ_STAT - FCCU IRQ Status Register */ - uint32_t R; - struct { - uint32_t:29; - uint32_t NMI_STAT:1; /* NMI Interrupt Status */ - uint32_t ALRM_STAT:1; /* Alarm Interrupt Status */ - uint32_t CFG_TO_STAT:1; /* Configuration Time-out Status */ - } B; - } FCCU_IRQ_STAT_32B_tag; - - typedef union { /* FCCU_IRQ_EN - FCCU IRQ Enable Register */ - uint32_t R; - struct { - uint32_t:31; - uint32_t CFG_TO_IEN:1; /* Configuration Time-out Interrupt Enable */ - } B; - } FCCU_IRQ_EN_32B_tag; - - typedef union { /* FCCU_XTMR - FCCU XTMR Register */ - uint32_t R; - struct { - uint32_t XTMR_XTMR:32; /* Alarm/Watchdog/safe request timer */ - } B; - } FCCU_XTMR_32B_tag; - - typedef union { /* FCCU_MCS - FCCU MCS Register */ - uint32_t R; - struct { - uint32_t VL3:1; /* Valid */ - uint32_t FS3:1; /* Fault Status */ - uint32_t:2; - uint32_t MCS3:4; /* Magic Carpet oldest state */ - uint32_t VL2:1; /* Valid */ - uint32_t FS2:1; /* Fault Status */ - uint32_t:2; - uint32_t MCS2:4; /* Magic Carpet previous-previous state */ - uint32_t VL1:1; /* Valid */ - uint32_t FS1:1; /* Fault Status */ - uint32_t:2; - uint32_t MCS1:4; /* Magic Carpet previous state */ - uint32_t VL0:1; /* Valid */ - uint32_t FS0:1; /* Fault Status */ - uint32_t:2; - uint32_t MCS0:4; /* Magic Carpet latest state */ - } B; - } FCCU_MCS_32B_tag; - - - /* Register layout for generated register(s) CF_CFG... */ - - typedef union { /* */ - uint32_t R; - } FCCU_CF_CFG_32B_tag; - - - /* Register layout for generated register(s) NCF_CFG... */ - - typedef union { /* */ - uint32_t R; - } FCCU_NCF_CFG_32B_tag; - - - /* Register layout for generated register(s) CFS_CFG... */ - - typedef union { /* */ - uint32_t R; - } FCCU_CFS_CFG_32B_tag; - - - /* Register layout for generated register(s) NCFS_CFG... */ - - typedef union { /* */ - uint32_t R; - } FCCU_NCFS_CFG_32B_tag; - - - /* Register layout for generated register(s) CFS... */ - - typedef union { /* */ - uint32_t R; - } FCCU_CFS_32B_tag; - - - /* Register layout for generated register(s) NCFS... */ - - typedef union { /* */ - uint32_t R; - } FCCU_NCFS_32B_tag; - - - /* Register layout for generated register(s) NCFE... */ - - typedef union { /* */ - uint32_t R; - } FCCU_NCFE_32B_tag; - - - /* Register layout for generated register(s) NCF_TOE... */ - - typedef union { /* */ - uint32_t R; - } FCCU_NCF_TOE_32B_tag; - - - - typedef struct FCCU_struct_tag { /* start of FCCU_tag */ - /* FCCU Control Register */ - FCCU_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */ - /* FCCU CTRL Key Register */ - FCCU_CTRLK_32B_tag CTRLK; /* offset: 0x0004 size: 32 bit */ - /* FCCU Configuration Register */ - FCCU_CFG_32B_tag CFG; /* offset: 0x0008 size: 32 bit */ - union { - FCCU_CF_CFG_32B_tag CF_CFG[4]; /* offset: 0x000C (0x0004 x 4) */ - - struct { - /* FCCU CF Configuration Register 0 */ - FCCU_CF_CFG0_32B_tag CF_CFG0; /* offset: 0x000C size: 32 bit */ - /* FCCU CF Configuration Register 1 */ - FCCU_CF_CFG1_32B_tag CF_CFG1; /* offset: 0x0010 size: 32 bit */ - /* FCCU CF Configuration Register 2 */ - FCCU_CF_CFG2_32B_tag CF_CFG2; /* offset: 0x0014 size: 32 bit */ - /* FCCU CF Configuration Register 3 */ - FCCU_CF_CFG3_32B_tag CF_CFG3; /* offset: 0x0018 size: 32 bit */ - }; - - }; - union { - FCCU_NCF_CFG_32B_tag NCF_CFG[4]; /* offset: 0x001C (0x0004 x 4) */ - - struct { - /* FCCU NCF Configuration Register 0 */ - FCCU_NCF_CFG0_32B_tag NCF_CFG0; /* offset: 0x001C size: 32 bit */ - /* FCCU NCF Configuration Register 1 */ - FCCU_NCF_CFG1_32B_tag NCF_CFG1; /* offset: 0x0020 size: 32 bit */ - /* FCCU NCF Configuration Register 2 */ - FCCU_NCF_CFG2_32B_tag NCF_CFG2; /* offset: 0x0024 size: 32 bit */ - /* FCCU NCF Configuration Register 3 */ - FCCU_NCF_CFG3_32B_tag NCF_CFG3; /* offset: 0x0028 size: 32 bit */ - }; - - }; - union { - FCCU_CFS_CFG_32B_tag CFS_CFG[8]; /* offset: 0x002C (0x0004 x 8) */ - - struct { - /* FCCU CFS Configuration Register 0 */ - FCCU_CFS_CFG0_32B_tag CFS_CFG0; /* offset: 0x002C size: 32 bit */ - /* FCCU CFS Configuration Register 1 */ - FCCU_CFS_CFG1_32B_tag CFS_CFG1; /* offset: 0x0030 size: 32 bit */ - /* FCCU CFS Configuration Register 2 */ - FCCU_CFS_CFG2_32B_tag CFS_CFG2; /* offset: 0x0034 size: 32 bit */ - /* FCCU CFS Configuration Register 3 */ - FCCU_CFS_CFG3_32B_tag CFS_CFG3; /* offset: 0x0038 size: 32 bit */ - /* FCCU CFS Configuration Register 4 */ - FCCU_CFS_CFG4_32B_tag CFS_CFG4; /* offset: 0x003C size: 32 bit */ - /* FCCU CFS Configuration Register 5 */ - FCCU_CFS_CFG5_32B_tag CFS_CFG5; /* offset: 0x0040 size: 32 bit */ - /* FCCU CFS Configuration Register 6 */ - FCCU_CFS_CFG6_32B_tag CFS_CFG6; /* offset: 0x0044 size: 32 bit */ - /* FCCU CFS Configuration Register 7 */ - FCCU_CFS_CFG7_32B_tag CFS_CFG7; /* offset: 0x0048 size: 32 bit */ - }; - - }; - union { - FCCU_NCFS_CFG_32B_tag NCFS_CFG[8]; /* offset: 0x004C (0x0004 x 8) */ - - struct { - /* FCCU NCFS Configuration Register 0 */ - FCCU_NCFS_CFG0_32B_tag NCFS_CFG0; /* offset: 0x004C size: 32 bit */ - /* FCCU NCFS Configuration Register 1 */ - FCCU_NCFS_CFG1_32B_tag NCFS_CFG1; /* offset: 0x0050 size: 32 bit */ - /* FCCU NCFS Configuration Register 2 */ - FCCU_NCFS_CFG2_32B_tag NCFS_CFG2; /* offset: 0x0054 size: 32 bit */ - /* FCCU NCFS Configuration Register 3 */ - FCCU_NCFS_CFG3_32B_tag NCFS_CFG3; /* offset: 0x0058 size: 32 bit */ - /* FCCU NCFS Configuration Register 4 */ - FCCU_NCFS_CFG4_32B_tag NCFS_CFG4; /* offset: 0x005C size: 32 bit */ - /* FCCU NCFS Configuration Register 5 */ - FCCU_NCFS_CFG5_32B_tag NCFS_CFG5; /* offset: 0x0060 size: 32 bit */ - /* FCCU NCFS Configuration Register 6 */ - FCCU_NCFS_CFG6_32B_tag NCFS_CFG6; /* offset: 0x0064 size: 32 bit */ - /* FCCU NCFS Configuration Register 7 */ - FCCU_NCFS_CFG7_32B_tag NCFS_CFG7; /* offset: 0x0068 size: 32 bit */ - }; - - }; - union { - FCCU_CFS_32B_tag CFS[4]; /* offset: 0x006C (0x0004 x 4) */ - - struct { - /* FCCU CF Status Register 0 */ - FCCU_CFS0_32B_tag CFS0; /* offset: 0x006C size: 32 bit */ - /* FCCU CF Status Register 1 */ - FCCU_CFS1_32B_tag CFS1; /* offset: 0x0070 size: 32 bit */ - /* FCCU CF Status Register 2 */ - FCCU_CFS2_32B_tag CFS2; /* offset: 0x0074 size: 32 bit */ - /* FCCU CF Status Register 3 */ - FCCU_CFS3_32B_tag CFS3; /* offset: 0x0078 size: 32 bit */ - }; - - }; - /* FCCU_CFK - FCCU CF Key Register */ - FCCU_CFK_32B_tag CFK; /* offset: 0x007C size: 32 bit */ - union { - FCCU_NCFS_32B_tag NCFS[4]; /* offset: 0x0080 (0x0004 x 4) */ - - struct { - /* FCCU NCF Status Register 0 */ - FCCU_NCFS0_32B_tag NCFS0; /* offset: 0x0080 size: 32 bit */ - /* FCCU NCF Status Register 1 */ - FCCU_NCFS1_32B_tag NCFS1; /* offset: 0x0084 size: 32 bit */ - /* FCCU NCF Status Register 2 */ - FCCU_NCFS2_32B_tag NCFS2; /* offset: 0x0088 size: 32 bit */ - /* FCCU NCF Status Register 3 */ - FCCU_NCFS3_32B_tag NCFS3; /* offset: 0x008C size: 32 bit */ - }; - - }; - /* FCCU_NCFK - FCCU NCF Key Register */ - FCCU_NCFK_32B_tag NCFK; /* offset: 0x0090 size: 32 bit */ - union { - FCCU_NCFE_32B_tag NCFE[4]; /* offset: 0x0094 (0x0004 x 4) */ - - struct { - /* FCCU NCF Enable Register 0 */ - FCCU_NCFE0_32B_tag NCFE0; /* offset: 0x0094 size: 32 bit */ - /* FCCU NCF Enable Register 1 */ - FCCU_NCFE1_32B_tag NCFE1; /* offset: 0x0098 size: 32 bit */ - /* FCCU NCF Enable Register 2 */ - FCCU_NCFE2_32B_tag NCFE2; /* offset: 0x009C size: 32 bit */ - /* FCCU NCF Enable Register 3 */ - FCCU_NCFE3_32B_tag NCFE3; /* offset: 0x00A0 size: 32 bit */ - }; - - }; - union { - FCCU_NCF_TOE_32B_tag NCF_TOE[4]; /* offset: 0x00A4 (0x0004 x 4) */ - - struct { - /* FCCU NCF Time-out Enable Register 0 */ - FCCU_NCF_TOE0_32B_tag NCF_TOE0; /* offset: 0x00A4 size: 32 bit */ - /* FCCU NCF Time-out Enable Register 1 */ - FCCU_NCF_TOE1_32B_tag NCF_TOE1; /* offset: 0x00A8 size: 32 bit */ - /* FCCU NCF Time-out Enable Register 2 */ - FCCU_NCF_TOE2_32B_tag NCF_TOE2; /* offset: 0x00AC size: 32 bit */ - /* FCCU NCF Time-out Enable Register 3 */ - FCCU_NCF_TOE3_32B_tag NCF_TOE3; /* offset: 0x00B0 size: 32 bit */ - }; - - }; - /* FCCU_NCF_TO - FCCU NCF Time-out Register */ - FCCU_NCF_TO_32B_tag NCF_TO; /* offset: 0x00B4 size: 32 bit */ - /* FCCU_CFG_TO - FCCU CFG Timeout Register */ - FCCU_CFG_TO_32B_tag CFG_TO; /* offset: 0x00B8 size: 32 bit */ - /* FCCU_EINOUT - FCCU IO Control Register */ - FCCU_EINOUT_32B_tag EINOUT; /* offset: 0x00BC size: 32 bit */ - /* FCCU_STAT - FCCU Status Register */ - FCCU_STAT_32B_tag STAT; /* offset: 0x00C0 size: 32 bit */ - /* FCCU_NAFS - FCCU NA Freeze Status Register */ - FCCU_NAFS_32B_tag NAFS; /* offset: 0x00C4 size: 32 bit */ - /* FCCU_AFFS - FCCU AF Freeze Status Register */ - FCCU_AFFS_32B_tag AFFS; /* offset: 0x00C8 size: 32 bit */ - /* FCCU_NFFS - FCCU NF Freeze Status Register */ - FCCU_NFFS_32B_tag NFFS; /* offset: 0x00CC size: 32 bit */ - /* FCCU_FAFS - FCCU FA Freeze Status Register */ - FCCU_FAFS_32B_tag FAFS; /* offset: 0x00D0 size: 32 bit */ - /* FCCU_SCFS - FCCU SC Freeze Status Register */ - FCCU_SCFS_32B_tag SCFS; /* offset: 0x00D4 size: 32 bit */ - /* FCCU_CFF - FCCU CF Fake Register */ - FCCU_CFF_32B_tag CFF; /* offset: 0x00D8 size: 32 bit */ - /* FCCU_NCFF - FCCU NCF Fake Register */ - FCCU_NCFF_32B_tag NCFF; /* offset: 0x00DC size: 32 bit */ - /* FCCU_IRQ_STAT - FCCU IRQ Status Register */ - FCCU_IRQ_STAT_32B_tag IRQ_STAT; /* offset: 0x00E0 size: 32 bit */ - /* FCCU_IRQ_EN - FCCU IRQ Enable Register */ - FCCU_IRQ_EN_32B_tag IRQ_EN; /* offset: 0x00E4 size: 32 bit */ - /* FCCU_XTMR - FCCU XTMR Register */ - FCCU_XTMR_32B_tag XTMR; /* offset: 0x00E8 size: 32 bit */ - /* FCCU_MCS - FCCU MCS Register */ - FCCU_MCS_32B_tag MCS; /* offset: 0x00EC size: 32 bit */ - } FCCU_tag; - - -#define FCCU (*(volatile FCCU_tag *) 0xFFE6C000UL) - - - -/****************************************************************/ -/* */ -/* Module: SGENDIG */ -/* */ -/****************************************************************/ - - typedef union { /* SGENDIG_CTRL - SGENDIG Control Register */ - uint32_t R; - struct { - uint32_t LDOS:1; /* Operation Status */ - uint32_t IOAMPL:5; /* Define the AMPLitude value on I/O pad */ - uint32_t:2; - uint32_t SEMASK:1; /* Sine wave generator Error MASK interrupt register */ - uint32_t:5; - uint32_t S0H1:1; /* Operation Status */ - uint32_t PDS:1; /* Operation Status */ - uint32_t IOFREQ:16; /* Define the FREQuency value on I/O pad */ - } B; - } SGENDIG_CTRL_32B_tag; - - typedef union { /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */ - uint32_t R; - struct { - uint32_t:8; - uint32_t SERR:1; /* Sine wave generator Error bit */ - uint32_t:3; - uint32_t FERR:1; /* Sine wave generator Force Error bit */ - uint32_t:19; - } B; - } SGENDIG_IRQE_32B_tag; - - - - typedef struct SGENDIG_struct_tag { /* start of SGENDIG_tag */ - /* SGENDIG_CTRL - SGENDIG Control Register */ - SGENDIG_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */ - /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */ - SGENDIG_IRQE_32B_tag IRQE; /* offset: 0x0004 size: 32 bit */ - } SGENDIG_tag; - - -#define SGENDIG (*(volatile SGENDIG_tag *) 0xFFE78000UL) - - - -/****************************************************************/ -/* */ -/* Module: PBRIDGE */ -/* */ -/****************************************************************/ - - typedef union { /* MPROT - Master Privilege Registers */ - uint32_t R; - struct { - uint32_t MPROT0_MBW:1; /* Master 0 Buffer Writes */ - uint32_t MPROT0_MTR:1; /* Master 0 Trusted for Reads */ - uint32_t MPROT0_MTW:1; /* Master 0 Trusted for Writes */ - uint32_t MPROT0_MPL:1; /* Master 0 Priviledge Level */ - uint32_t MPROT1_MBW:1; /* Master 1 Buffer Writes */ - uint32_t MPROT1_MTR:1; /* Master 1 Trusted for Reads */ - uint32_t MPROT1_MTW:1; /* Master 1 Trusted for Writes */ - uint32_t MPROT1_MPL:1; /* Master 1 Priviledge Level */ - uint32_t MPROT2_MBW:1; /* Master 2 Buffer Writes */ - uint32_t MPROT2_MTR:1; /* Master 2 Trusted for Reads */ - uint32_t MPROT2_MTW:1; /* Master 2 Trusted for Writes */ - uint32_t MPROT2_MPL:1; /* Master 2 Priviledge Level */ - uint32_t MPROT3_MBW:1; /* Master 3 Buffer Writes */ - uint32_t MPROT3_MTR:1; /* Master 3 Trusted for Reads */ - uint32_t MPROT3_MTW:1; /* Master 3 Trusted for Writes */ - uint32_t MPROT3_MPL:1; /* Master 3 Priviledge Level */ - uint32_t MPROT4_MBW:1; /* Master 4 Buffer Writes */ - uint32_t MPROT4_MTR:1; /* Master 4 Trusted for Reads */ - uint32_t MPROT4_MTW:1; /* Master 4 Trusted for Writes */ - uint32_t MPROT4_MPL:1; /* Master 4 Priviledge Level */ - uint32_t MPROT5_MBW:1; /* Master 5 Buffer Writes */ - uint32_t MPROT5_MTR:1; /* Master 5 Trusted for Reads */ - uint32_t MPROT5_MTW:1; /* Master 5 Trusted for Writes */ - uint32_t MPROT5_MPL:1; /* Master 5 Priviledge Level */ - uint32_t MPROT6_MBW:1; /* Master 6 Buffer Writes */ - uint32_t MPROT6_MTR:1; /* Master 6 Trusted for Reads */ - uint32_t MPROT6_MTW:1; /* Master 6 Trusted for Writes */ - uint32_t MPROT6_MPL:1; /* Master 6 Priviledge Level */ - uint32_t MPROT7_MBW:1; /* Master 7 Buffer Writes */ - uint32_t MPROT7_MTR:1; /* Master 7 Trusted for Reads */ - uint32_t MPROT7_MTW:1; /* Master 7 Trusted for Writes */ - uint32_t MPROT7_MPL:1; /* Master 7 Priviledge Level */ - } B; - } PBRIDGE_MPROT_32B_tag; - - typedef union { /* PACR0_7 - Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t PACR0_BW:1; /* Buffer Writes */ - uint32_t PACR0_SP:1; /* Supervisor Protect */ - uint32_t PACR0_WP:1; /* Write Protect */ - uint32_t PACR0_TP:1; /* Trusted Protect */ - uint32_t PACR1_BW:1; /* Buffer Writes */ - uint32_t PACR1_SP:1; /* Supervisor Protect */ - uint32_t PACR1_WP:1; /* Write Protect */ - uint32_t PACR1_TP:1; /* Trusted Protect */ - uint32_t PACR2_BW:1; /* Buffer Writes */ - uint32_t PACR2_SP:1; /* Supervisor Protect */ - uint32_t PACR2_WP:1; /* Write Protect */ - uint32_t PACR2_TP:1; /* Trusted Protect */ - uint32_t PACR3_BW:1; /* Buffer Writes */ - uint32_t PACR3_SP:1; /* Supervisor Protect */ - uint32_t PACR3_WP:1; /* Write Protect */ - uint32_t PACR3_TP:1; /* Trusted Protect */ - uint32_t PACR4_BW:1; /* Buffer Writes */ - uint32_t PACR4_SP:1; /* Supervisor Protect */ - uint32_t PACR4_WP:1; /* Write Protect */ - uint32_t PACR4_TP:1; /* Trusted Protect */ - uint32_t PACR5_BW:1; /* Buffer Writes */ - uint32_t PACR5_SP:1; /* Supervisor Protect */ - uint32_t PACR5_WP:1; /* Write Protect */ - uint32_t PACR5_TP:1; /* Trusted Protect */ - uint32_t PACR6_BW:1; /* Buffer Writes */ - uint32_t PACR6_SP:1; /* Supervisor Protect */ - uint32_t PACR6_WP:1; /* Write Protect */ - uint32_t PACR6_TP:1; /* Trusted Protect */ - uint32_t PACR7_BW:1; /* Buffer Writes */ - uint32_t PACR7_SP:1; /* Supervisor Protect */ - uint32_t PACR7_WP:1; /* Write Protect */ - uint32_t PACR7_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_PACR0_7_32B_tag; - - typedef union { /* PACR8_15 - Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t PACR8_BW:1; /* Buffer Writes */ - uint32_t PACR8_SP:1; /* Supervisor Protect */ - uint32_t PACR8_WP:1; /* Write Protect */ - uint32_t PACR8_TP:1; /* Trusted Protect */ - uint32_t PACR9_BW:1; /* Buffer Writes */ - uint32_t PACR9_SP:1; /* Supervisor Protect */ - uint32_t PACR9_WP:1; /* Write Protect */ - uint32_t PACR9_TP:1; /* Trusted Protect */ - uint32_t PACR10_BW:1; /* Buffer Writes */ - uint32_t PACR10_SP:1; /* Supervisor Protect */ - uint32_t PACR10_WP:1; /* Write Protect */ - uint32_t PACR10_TP:1; /* Trusted Protect */ - uint32_t PACR11_BW:1; /* Buffer Writes */ - uint32_t PACR11_SP:1; /* Supervisor Protect */ - uint32_t PACR11_WP:1; /* Write Protect */ - uint32_t PACR11_TP:1; /* Trusted Protect */ - uint32_t PACR12_BW:1; /* Buffer Writes */ - uint32_t PACR12_SP:1; /* Supervisor Protect */ - uint32_t PACR12_WP:1; /* Write Protect */ - uint32_t PACR12_TP:1; /* Trusted Protect */ - uint32_t PACR13_BW:1; /* Buffer Writes */ - uint32_t PACR13_SP:1; /* Supervisor Protect */ - uint32_t PACR13_WP:1; /* Write Protect */ - uint32_t PACR13_TP:1; /* Trusted Protect */ - uint32_t PACR14_BW:1; /* Buffer Writes */ - uint32_t PACR14_SP:1; /* Supervisor Protect */ - uint32_t PACR14_WP:1; /* Write Protect */ - uint32_t PACR14_TP:1; /* Trusted Protect */ - uint32_t PACR15_BW:1; /* Buffer Writes */ - uint32_t PACR15_SP:1; /* Supervisor Protect */ - uint32_t PACR15_WP:1; /* Write Protect */ - uint32_t PACR15_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_PACR8_15_32B_tag; - - typedef union { /* PACR16_23 - Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t PACR16_BW:1; /* Buffer Writes */ - uint32_t PACR16_SP:1; /* Supervisor Protect */ - uint32_t PACR16_WP:1; /* Write Protect */ - uint32_t PACR16_TP:1; /* Trusted Protect */ - uint32_t PACR17_BW:1; /* Buffer Writes */ - uint32_t PACR17_SP:1; /* Supervisor Protect */ - uint32_t PACR17_WP:1; /* Write Protect */ - uint32_t PACR17_TP:1; /* Trusted Protect */ - uint32_t PACR18_BW:1; /* Buffer Writes */ - uint32_t PACR18_SP:1; /* Supervisor Protect */ - uint32_t PACR18_WP:1; /* Write Protect */ - uint32_t PACR18_TP:1; /* Trusted Protect */ - uint32_t PACR19_BW:1; /* Buffer Writes */ - uint32_t PACR19_SP:1; /* Supervisor Protect */ - uint32_t PACR19_WP:1; /* Write Protect */ - uint32_t PACR19_TP:1; /* Trusted Protect */ - uint32_t PACR20_BW:1; /* Buffer Writes */ - uint32_t PACR20_SP:1; /* Supervisor Protect */ - uint32_t PACR20_WP:1; /* Write Protect */ - uint32_t PACR20_TP:1; /* Trusted Protect */ - uint32_t PACR21_BW:1; /* Buffer Writes */ - uint32_t PACR21_SP:1; /* Supervisor Protect */ - uint32_t PACR21_WP:1; /* Write Protect */ - uint32_t PACR21_TP:1; /* Trusted Protect */ - uint32_t PACR22_BW:1; /* Buffer Writes */ - uint32_t PACR22_SP:1; /* Supervisor Protect */ - uint32_t PACR22_WP:1; /* Write Protect */ - uint32_t PACR22_TP:1; /* Trusted Protect */ - uint32_t PACR23_BW:1; /* Buffer Writes */ - uint32_t PACR23_SP:1; /* Supervisor Protect */ - uint32_t PACR23_WP:1; /* Write Protect */ - uint32_t PACR23_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_PACR16_23_32B_tag; - - typedef union { /* PACR24_31 - Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t PACR24_BW:1; /* Buffer Writes */ - uint32_t PACR24_SP:1; /* Supervisor Protect */ - uint32_t PACR24_WP:1; /* Write Protect */ - uint32_t PACR24_TP:1; /* Trusted Protect */ - uint32_t PACR25_BW:1; /* Buffer Writes */ - uint32_t PACR25_SP:1; /* Supervisor Protect */ - uint32_t PACR25_WP:1; /* Write Protect */ - uint32_t PACR25_TP:1; /* Trusted Protect */ - uint32_t PACR26_BW:1; /* Buffer Writes */ - uint32_t PACR26_SP:1; /* Supervisor Protect */ - uint32_t PACR26_WP:1; /* Write Protect */ - uint32_t PACR26_TP:1; /* Trusted Protect */ - uint32_t PACR27_BW:1; /* Buffer Writes */ - uint32_t PACR27_SP:1; /* Supervisor Protect */ - uint32_t PACR27_WP:1; /* Write Protect */ - uint32_t PACR27_TP:1; /* Trusted Protect */ - uint32_t PACR28_BW:1; /* Buffer Writes */ - uint32_t PACR28_SP:1; /* Supervisor Protect */ - uint32_t PACR28_WP:1; /* Write Protect */ - uint32_t PACR28_TP:1; /* Trusted Protect */ - uint32_t PACR29_BW:1; /* Buffer Writes */ - uint32_t PACR29_SP:1; /* Supervisor Protect */ - uint32_t PACR29_WP:1; /* Write Protect */ - uint32_t PACR29_TP:1; /* Trusted Protect */ - uint32_t PACR30_BW:1; /* Buffer Writes */ - uint32_t PACR30_SP:1; /* Supervisor Protect */ - uint32_t PACR30_WP:1; /* Write Protect */ - uint32_t PACR30_TP:1; /* Trusted Protect */ - uint32_t PACR31_BW:1; /* Buffer Writes */ - uint32_t PACR31_SP:1; /* Supervisor Protect */ - uint32_t PACR31_WP:1; /* Write Protect */ - uint32_t PACR31_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_PACR24_31_32B_tag; - - typedef union { /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t OPACR0_BW:1; /* Buffer Writes */ - uint32_t OPACR0_SP:1; /* Supervisor Protect */ - uint32_t OPACR0_WP:1; /* Write Protect */ - uint32_t OPACR0_TP:1; /* Trusted Protect */ - uint32_t OPACR1_BW:1; /* Buffer Writes */ - uint32_t OPACR1_SP:1; /* Supervisor Protect */ - uint32_t OPACR1_WP:1; /* Write Protect */ - uint32_t OPACR1_TP:1; /* Trusted Protect */ - uint32_t OPACR2_BW:1; /* Buffer Writes */ - uint32_t OPACR2_SP:1; /* Supervisor Protect */ - uint32_t OPACR2_WP:1; /* Write Protect */ - uint32_t OPACR2_TP:1; /* Trusted Protect */ - uint32_t OPACR3_BW:1; /* Buffer Writes */ - uint32_t OPACR3_SP:1; /* Supervisor Protect */ - uint32_t OPACR3_WP:1; /* Write Protect */ - uint32_t OPACR3_TP:1; /* Trusted Protect */ - uint32_t OPACR4_BW:1; /* Buffer Writes */ - uint32_t OPACR4_SP:1; /* Supervisor Protect */ - uint32_t OPACR4_WP:1; /* Write Protect */ - uint32_t OPACR4_TP:1; /* Trusted Protect */ - uint32_t OPACR5_BW:1; /* Buffer Writes */ - uint32_t OPACR5_SP:1; /* Supervisor Protect */ - uint32_t OPACR5_WP:1; /* Write Protect */ - uint32_t OPACR5_TP:1; /* Trusted Protect */ - uint32_t OPACR6_BW:1; /* Buffer Writes */ - uint32_t OPACR6_SP:1; /* Supervisor Protect */ - uint32_t OPACR6_WP:1; /* Write Protect */ - uint32_t OPACR6_TP:1; /* Trusted Protect */ - uint32_t OPACR7_BW:1; /* Buffer Writes */ - uint32_t OPACR7_SP:1; /* Supervisor Protect */ - uint32_t OPACR7_WP:1; /* Write Protect */ - uint32_t OPACR7_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_OPACR0_7_32B_tag; - - typedef union { /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t OPACR8_BW:1; /* Buffer Writes */ - uint32_t OPACR8_SP:1; /* Supervisor Protect */ - uint32_t OPACR8_WP:1; /* Write Protect */ - uint32_t OPACR8_TP:1; /* Trusted Protect */ - uint32_t OPACR9_BW:1; /* Buffer Writes */ - uint32_t OPACR9_SP:1; /* Supervisor Protect */ - uint32_t OPACR9_WP:1; /* Write Protect */ - uint32_t OPACR9_TP:1; /* Trusted Protect */ - uint32_t OPACR10_BW:1; /* Buffer Writes */ - uint32_t OPACR10_SP:1; /* Supervisor Protect */ - uint32_t OPACR10_WP:1; /* Write Protect */ - uint32_t OPACR10_TP:1; /* Trusted Protect */ - uint32_t OPACR11_BW:1; /* Buffer Writes */ - uint32_t OPACR11_SP:1; /* Supervisor Protect */ - uint32_t OPACR11_WP:1; /* Write Protect */ - uint32_t OPACR11_TP:1; /* Trusted Protect */ - uint32_t OPACR12_BW:1; /* Buffer Writes */ - uint32_t OPACR12_SP:1; /* Supervisor Protect */ - uint32_t OPACR12_WP:1; /* Write Protect */ - uint32_t OPACR12_TP:1; /* Trusted Protect */ - uint32_t OPACR13_BW:1; /* Buffer Writes */ - uint32_t OPACR13_SP:1; /* Supervisor Protect */ - uint32_t OPACR13_WP:1; /* Write Protect */ - uint32_t OPACR13_TP:1; /* Trusted Protect */ - uint32_t OPACR14_BW:1; /* Buffer Writes */ - uint32_t OPACR14_SP:1; /* Supervisor Protect */ - uint32_t OPACR14_WP:1; /* Write Protect */ - uint32_t OPACR14_TP:1; /* Trusted Protect */ - uint32_t OPACR15_BW:1; /* Buffer Writes */ - uint32_t OPACR15_SP:1; /* Supervisor Protect */ - uint32_t OPACR15_WP:1; /* Write Protect */ - uint32_t OPACR15_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_OPACR8_15_32B_tag; - - typedef union { /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t OPACR16_BW:1; /* Buffer Writes */ - uint32_t OPACR16_SP:1; /* Supervisor Protect */ - uint32_t OPACR16_WP:1; /* Write Protect */ - uint32_t OPACR16_TP:1; /* Trusted Protect */ - uint32_t OPACR17_BW:1; /* Buffer Writes */ - uint32_t OPACR17_SP:1; /* Supervisor Protect */ - uint32_t OPACR17_WP:1; /* Write Protect */ - uint32_t OPACR17_TP:1; /* Trusted Protect */ - uint32_t OPACR18_BW:1; /* Buffer Writes */ - uint32_t OPACR18_SP:1; /* Supervisor Protect */ - uint32_t OPACR18_WP:1; /* Write Protect */ - uint32_t OPACR18_TP:1; /* Trusted Protect */ - uint32_t OPACR19_BW:1; /* Buffer Writes */ - uint32_t OPACR19_SP:1; /* Supervisor Protect */ - uint32_t OPACR19_WP:1; /* Write Protect */ - uint32_t OPACR19_TP:1; /* Trusted Protect */ - uint32_t OPACR20_BW:1; /* Buffer Writes */ - uint32_t OPACR20_SP:1; /* Supervisor Protect */ - uint32_t OPACR20_WP:1; /* Write Protect */ - uint32_t OPACR20_TP:1; /* Trusted Protect */ - uint32_t OPACR21_BW:1; /* Buffer Writes */ - uint32_t OPACR21_SP:1; /* Supervisor Protect */ - uint32_t OPACR21_WP:1; /* Write Protect */ - uint32_t OPACR21_TP:1; /* Trusted Protect */ - uint32_t OPACR22_BW:1; /* Buffer Writes */ - uint32_t OPACR22_SP:1; /* Supervisor Protect */ - uint32_t OPACR22_WP:1; /* Write Protect */ - uint32_t OPACR22_TP:1; /* Trusted Protect */ - uint32_t OPACR23_BW:1; /* Buffer Writes */ - uint32_t OPACR23_SP:1; /* Supervisor Protect */ - uint32_t OPACR23_WP:1; /* Write Protect */ - uint32_t OPACR23_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_OPACR16_23_32B_tag; - - typedef union { /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t OPACR24_BW:1; /* Buffer Writes */ - uint32_t OPACR24_SP:1; /* Supervisor Protect */ - uint32_t OPACR24_WP:1; /* Write Protect */ - uint32_t OPACR24_TP:1; /* Trusted Protect */ - uint32_t OPACR25_BW:1; /* Buffer Writes */ - uint32_t OPACR25_SP:1; /* Supervisor Protect */ - uint32_t OPACR25_WP:1; /* Write Protect */ - uint32_t OPACR25_TP:1; /* Trusted Protect */ - uint32_t OPACR26_BW:1; /* Buffer Writes */ - uint32_t OPACR26_SP:1; /* Supervisor Protect */ - uint32_t OPACR26_WP:1; /* Write Protect */ - uint32_t OPACR26_TP:1; /* Trusted Protect */ - uint32_t OPACR27_BW:1; /* Buffer Writes */ - uint32_t OPACR27_SP:1; /* Supervisor Protect */ - uint32_t OPACR27_WP:1; /* Write Protect */ - uint32_t OPACR27_TP:1; /* Trusted Protect */ - uint32_t OPACR28_BW:1; /* Buffer Writes */ - uint32_t OPACR28_SP:1; /* Supervisor Protect */ - uint32_t OPACR28_WP:1; /* Write Protect */ - uint32_t OPACR28_TP:1; /* Trusted Protect */ - uint32_t OPACR29_BW:1; /* Buffer Writes */ - uint32_t OPACR29_SP:1; /* Supervisor Protect */ - uint32_t OPACR29_WP:1; /* Write Protect */ - uint32_t OPACR29_TP:1; /* Trusted Protect */ - uint32_t OPACR30_BW:1; /* Buffer Writes */ - uint32_t OPACR30_SP:1; /* Supervisor Protect */ - uint32_t OPACR30_WP:1; /* Write Protect */ - uint32_t OPACR30_TP:1; /* Trusted Protect */ - uint32_t OPACR31_BW:1; /* Buffer Writes */ - uint32_t OPACR31_SP:1; /* Supervisor Protect */ - uint32_t OPACR31_WP:1; /* Write Protect */ - uint32_t OPACR31_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_OPACR24_31_32B_tag; - - typedef union { /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t OPACR32_BW:1; /* Buffer Writes */ - uint32_t OPACR32_SP:1; /* Supervisor Protect */ - uint32_t OPACR32_WP:1; /* Write Protect */ - uint32_t OPACR32_TP:1; /* Trusted Protect */ - uint32_t OPACR33_BW:1; /* Buffer Writes */ - uint32_t OPACR33_SP:1; /* Supervisor Protect */ - uint32_t OPACR33_WP:1; /* Write Protect */ - uint32_t OPACR33_TP:1; /* Trusted Protect */ - uint32_t OPACR34_BW:1; /* Buffer Writes */ - uint32_t OPACR34_SP:1; /* Supervisor Protect */ - uint32_t OPACR34_WP:1; /* Write Protect */ - uint32_t OPACR34_TP:1; /* Trusted Protect */ - uint32_t OPACR35_BW:1; /* Buffer Writes */ - uint32_t OPACR35_SP:1; /* Supervisor Protect */ - uint32_t OPACR35_WP:1; /* Write Protect */ - uint32_t OPACR35_TP:1; /* Trusted Protect */ - uint32_t OPACR36_BW:1; /* Buffer Writes */ - uint32_t OPACR36_SP:1; /* Supervisor Protect */ - uint32_t OPACR36_WP:1; /* Write Protect */ - uint32_t OPACR36_TP:1; /* Trusted Protect */ - uint32_t OPACR37_BW:1; /* Buffer Writes */ - uint32_t OPACR37_SP:1; /* Supervisor Protect */ - uint32_t OPACR37_WP:1; /* Write Protect */ - uint32_t OPACR37_TP:1; /* Trusted Protect */ - uint32_t OPACR38_BW:1; /* Buffer Writes */ - uint32_t OPACR38_SP:1; /* Supervisor Protect */ - uint32_t OPACR38_WP:1; /* Write Protect */ - uint32_t OPACR38_TP:1; /* Trusted Protect */ - uint32_t OPACR39_BW:1; /* Buffer Writes */ - uint32_t OPACR39_SP:1; /* Supervisor Protect */ - uint32_t OPACR39_WP:1; /* Write Protect */ - uint32_t OPACR39_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_OPACR32_39_32B_tag; - - typedef union { /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t OPACR40_BW:1; /* Buffer Writes */ - uint32_t OPACR40_SP:1; /* Supervisor Protect */ - uint32_t OPACR40_WP:1; /* Write Protect */ - uint32_t OPACR40_TP:1; /* Trusted Protect */ - uint32_t OPACR41_BW:1; /* Buffer Writes */ - uint32_t OPACR41_SP:1; /* Supervisor Protect */ - uint32_t OPACR41_WP:1; /* Write Protect */ - uint32_t OPACR41_TP:1; /* Trusted Protect */ - uint32_t OPACR42_BW:1; /* Buffer Writes */ - uint32_t OPACR42_SP:1; /* Supervisor Protect */ - uint32_t OPACR42_WP:1; /* Write Protect */ - uint32_t OPACR42_TP:1; /* Trusted Protect */ - uint32_t OPACR43_BW:1; /* Buffer Writes */ - uint32_t OPACR43_SP:1; /* Supervisor Protect */ - uint32_t OPACR43_WP:1; /* Write Protect */ - uint32_t OPACR43_TP:1; /* Trusted Protect */ - uint32_t OPACR44_BW:1; /* Buffer Writes */ - uint32_t OPACR44_SP:1; /* Supervisor Protect */ - uint32_t OPACR44_WP:1; /* Write Protect */ - uint32_t OPACR44_TP:1; /* Trusted Protect */ - uint32_t OPACR45_BW:1; /* Buffer Writes */ - uint32_t OPACR45_SP:1; /* Supervisor Protect */ - uint32_t OPACR45_WP:1; /* Write Protect */ - uint32_t OPACR45_TP:1; /* Trusted Protect */ - uint32_t OPACR46_BW:1; /* Buffer Writes */ - uint32_t OPACR46_SP:1; /* Supervisor Protect */ - uint32_t OPACR46_WP:1; /* Write Protect */ - uint32_t OPACR46_TP:1; /* Trusted Protect */ - uint32_t OPACR47_BW:1; /* Buffer Writes */ - uint32_t OPACR47_SP:1; /* Supervisor Protect */ - uint32_t OPACR47_WP:1; /* Write Protect */ - uint32_t OPACR47_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_OPACR40_47_32B_tag; - - typedef union { /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t OPACR48_BW:1; /* Buffer Writes */ - uint32_t OPACR48_SP:1; /* Supervisor Protect */ - uint32_t OPACR48_WP:1; /* Write Protect */ - uint32_t OPACR48_TP:1; /* Trusted Protect */ - uint32_t OPACR49_BW:1; /* Buffer Writes */ - uint32_t OPACR49_SP:1; /* Supervisor Protect */ - uint32_t OPACR49_WP:1; /* Write Protect */ - uint32_t OPACR49_TP:1; /* Trusted Protect */ - uint32_t OPACR50_BW:1; /* Buffer Writes */ - uint32_t OPACR50_SP:1; /* Supervisor Protect */ - uint32_t OPACR50_WP:1; /* Write Protect */ - uint32_t OPACR50_TP:1; /* Trusted Protect */ - uint32_t OPACR51_BW:1; /* Buffer Writes */ - uint32_t OPACR51_SP:1; /* Supervisor Protect */ - uint32_t OPACR51_WP:1; /* Write Protect */ - uint32_t OPACR51_TP:1; /* Trusted Protect */ - uint32_t OPACR52_BW:1; /* Buffer Writes */ - uint32_t OPACR52_SP:1; /* Supervisor Protect */ - uint32_t OPACR52_WP:1; /* Write Protect */ - uint32_t OPACR52_TP:1; /* Trusted Protect */ - uint32_t OPACR53_BW:1; /* Buffer Writes */ - uint32_t OPACR53_SP:1; /* Supervisor Protect */ - uint32_t OPACR53_WP:1; /* Write Protect */ - uint32_t OPACR53_TP:1; /* Trusted Protect */ - uint32_t OPACR54_BW:1; /* Buffer Writes */ - uint32_t OPACR54_SP:1; /* Supervisor Protect */ - uint32_t OPACR54_WP:1; /* Write Protect */ - uint32_t OPACR54_TP:1; /* Trusted Protect */ - uint32_t OPACR55_BW:1; /* Buffer Writes */ - uint32_t OPACR55_SP:1; /* Supervisor Protect */ - uint32_t OPACR55_WP:1; /* Write Protect */ - uint32_t OPACR55_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_OPACR48_55_32B_tag; - - typedef union { /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t OPACR56_BW:1; /* Buffer Writes */ - uint32_t OPACR56_SP:1; /* Supervisor Protect */ - uint32_t OPACR56_WP:1; /* Write Protect */ - uint32_t OPACR56_TP:1; /* Trusted Protect */ - uint32_t OPACR57_BW:1; /* Buffer Writes */ - uint32_t OPACR57_SP:1; /* Supervisor Protect */ - uint32_t OPACR57_WP:1; /* Write Protect */ - uint32_t OPACR57_TP:1; /* Trusted Protect */ - uint32_t OPACR58_BW:1; /* Buffer Writes */ - uint32_t OPACR58_SP:1; /* Supervisor Protect */ - uint32_t OPACR58_WP:1; /* Write Protect */ - uint32_t OPACR58_TP:1; /* Trusted Protect */ - uint32_t OPACR59_BW:1; /* Buffer Writes */ - uint32_t OPACR59_SP:1; /* Supervisor Protect */ - uint32_t OPACR59_WP:1; /* Write Protect */ - uint32_t OPACR59_TP:1; /* Trusted Protect */ - uint32_t OPACR60_BW:1; /* Buffer Writes */ - uint32_t OPACR60_SP:1; /* Supervisor Protect */ - uint32_t OPACR60_WP:1; /* Write Protect */ - uint32_t OPACR60_TP:1; /* Trusted Protect */ - uint32_t OPACR61_BW:1; /* Buffer Writes */ - uint32_t OPACR61_SP:1; /* Supervisor Protect */ - uint32_t OPACR61_WP:1; /* Write Protect */ - uint32_t OPACR61_TP:1; /* Trusted Protect */ - uint32_t OPACR62_BW:1; /* Buffer Writes */ - uint32_t OPACR62_SP:1; /* Supervisor Protect */ - uint32_t OPACR62_WP:1; /* Write Protect */ - uint32_t OPACR62_TP:1; /* Trusted Protect */ - uint32_t OPACR63_BW:1; /* Buffer Writes */ - uint32_t OPACR63_SP:1; /* Supervisor Protect */ - uint32_t OPACR63_WP:1; /* Write Protect */ - uint32_t OPACR63_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_OPACR56_63_32B_tag; - - typedef union { /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t OPACR64_BW:1; /* Buffer Writes */ - uint32_t OPACR64_SP:1; /* Supervisor Protect */ - uint32_t OPACR64_WP:1; /* Write Protect */ - uint32_t OPACR64_TP:1; /* Trusted Protect */ - uint32_t OPACR65_BW:1; /* Buffer Writes */ - uint32_t OPACR65_SP:1; /* Supervisor Protect */ - uint32_t OPACR65_WP:1; /* Write Protect */ - uint32_t OPACR65_TP:1; /* Trusted Protect */ - uint32_t OPACR66_BW:1; /* Buffer Writes */ - uint32_t OPACR66_SP:1; /* Supervisor Protect */ - uint32_t OPACR66_WP:1; /* Write Protect */ - uint32_t OPACR66_TP:1; /* Trusted Protect */ - uint32_t OPACR67_BW:1; /* Buffer Writes */ - uint32_t OPACR67_SP:1; /* Supervisor Protect */ - uint32_t OPACR67_WP:1; /* Write Protect */ - uint32_t OPACR67_TP:1; /* Trusted Protect */ - uint32_t OPACR68_BW:1; /* Buffer Writes */ - uint32_t OPACR68_SP:1; /* Supervisor Protect */ - uint32_t OPACR68_WP:1; /* Write Protect */ - uint32_t OPACR68_TP:1; /* Trusted Protect */ - uint32_t OPACR69_BW:1; /* Buffer Writes */ - uint32_t OPACR69_SP:1; /* Supervisor Protect */ - uint32_t OPACR69_WP:1; /* Write Protect */ - uint32_t OPACR69_TP:1; /* Trusted Protect */ - uint32_t OPACR70_BW:1; /* Buffer Writes */ - uint32_t OPACR70_SP:1; /* Supervisor Protect */ - uint32_t OPACR70_WP:1; /* Write Protect */ - uint32_t OPACR70_TP:1; /* Trusted Protect */ - uint32_t OPACR71_BW:1; /* Buffer Writes */ - uint32_t OPACR71_SP:1; /* Supervisor Protect */ - uint32_t OPACR71_WP:1; /* Write Protect */ - uint32_t OPACR71_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_OPACR64_71_32B_tag; - - typedef union { /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t OPACR72_BW:1; /* Buffer Writes */ - uint32_t OPACR72_SP:1; /* Supervisor Protect */ - uint32_t OPACR72_WP:1; /* Write Protect */ - uint32_t OPACR72_TP:1; /* Trusted Protect */ - uint32_t OPACR73_BW:1; /* Buffer Writes */ - uint32_t OPACR73_SP:1; /* Supervisor Protect */ - uint32_t OPACR73_WP:1; /* Write Protect */ - uint32_t OPACR73_TP:1; /* Trusted Protect */ - uint32_t OPACR74_BW:1; /* Buffer Writes */ - uint32_t OPACR74_SP:1; /* Supervisor Protect */ - uint32_t OPACR74_WP:1; /* Write Protect */ - uint32_t OPACR74_TP:1; /* Trusted Protect */ - uint32_t OPACR75_BW:1; /* Buffer Writes */ - uint32_t OPACR75_SP:1; /* Supervisor Protect */ - uint32_t OPACR75_WP:1; /* Write Protect */ - uint32_t OPACR75_TP:1; /* Trusted Protect */ - uint32_t OPACR76_BW:1; /* Buffer Writes */ - uint32_t OPACR76_SP:1; /* Supervisor Protect */ - uint32_t OPACR76_WP:1; /* Write Protect */ - uint32_t OPACR76_TP:1; /* Trusted Protect */ - uint32_t OPACR77_BW:1; /* Buffer Writes */ - uint32_t OPACR77_SP:1; /* Supervisor Protect */ - uint32_t OPACR77_WP:1; /* Write Protect */ - uint32_t OPACR77_TP:1; /* Trusted Protect */ - uint32_t OPACR78_BW:1; /* Buffer Writes */ - uint32_t OPACR78_SP:1; /* Supervisor Protect */ - uint32_t OPACR78_WP:1; /* Write Protect */ - uint32_t OPACR78_TP:1; /* Trusted Protect */ - uint32_t OPACR79_BW:1; /* Buffer Writes */ - uint32_t OPACR79_SP:1; /* Supervisor Protect */ - uint32_t OPACR79_WP:1; /* Write Protect */ - uint32_t OPACR79_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_OPACR72_79_32B_tag; - - typedef union { /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t OPACR80_BW:1; /* Buffer Writes */ - uint32_t OPACR80_SP:1; /* Supervisor Protect */ - uint32_t OPACR80_WP:1; /* Write Protect */ - uint32_t OPACR80_TP:1; /* Trusted Protect */ - uint32_t OPACR81_BW:1; /* Buffer Writes */ - uint32_t OPACR81_SP:1; /* Supervisor Protect */ - uint32_t OPACR81_WP:1; /* Write Protect */ - uint32_t OPACR81_TP:1; /* Trusted Protect */ - uint32_t OPACR82_BW:1; /* Buffer Writes */ - uint32_t OPACR82_SP:1; /* Supervisor Protect */ - uint32_t OPACR82_WP:1; /* Write Protect */ - uint32_t OPACR82_TP:1; /* Trusted Protect */ - uint32_t OPACR83_BW:1; /* Buffer Writes */ - uint32_t OPACR83_SP:1; /* Supervisor Protect */ - uint32_t OPACR83_WP:1; /* Write Protect */ - uint32_t OPACR83_TP:1; /* Trusted Protect */ - uint32_t OPACR84_BW:1; /* Buffer Writes */ - uint32_t OPACR84_SP:1; /* Supervisor Protect */ - uint32_t OPACR84_WP:1; /* Write Protect */ - uint32_t OPACR84_TP:1; /* Trusted Protect */ - uint32_t OPACR85_BW:1; /* Buffer Writes */ - uint32_t OPACR85_SP:1; /* Supervisor Protect */ - uint32_t OPACR85_WP:1; /* Write Protect */ - uint32_t OPACR85_TP:1; /* Trusted Protect */ - uint32_t OPACR86_BW:1; /* Buffer Writes */ - uint32_t OPACR86_SP:1; /* Supervisor Protect */ - uint32_t OPACR86_WP:1; /* Write Protect */ - uint32_t OPACR86_TP:1; /* Trusted Protect */ - uint32_t OPACR87_BW:1; /* Buffer Writes */ - uint32_t OPACR87_SP:1; /* Supervisor Protect */ - uint32_t OPACR87_WP:1; /* Write Protect */ - uint32_t OPACR87_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_OPACR80_87_32B_tag; - - typedef union { /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */ - uint32_t R; - struct { - uint32_t OPACR88_BW:1; /* Buffer Writes */ - uint32_t OPACR88_SP:1; /* Supervisor Protect */ - uint32_t OPACR88_WP:1; /* Write Protect */ - uint32_t OPACR88_TP:1; /* Trusted Protect */ - uint32_t OPACR89_BW:1; /* Buffer Writes */ - uint32_t OPACR89_SP:1; /* Supervisor Protect */ - uint32_t OPACR89_WP:1; /* Write Protect */ - uint32_t OPACR89_TP:1; /* Trusted Protect */ - uint32_t OPACR90_BW:1; /* Buffer Writes */ - uint32_t OPACR90_SP:1; /* Supervisor Protect */ - uint32_t OPACR90_WP:1; /* Write Protect */ - uint32_t OPACR90_TP:1; /* Trusted Protect */ - uint32_t OPACR91_BW:1; /* Buffer Writes */ - uint32_t OPACR91_SP:1; /* Supervisor Protect */ - uint32_t OPACR91_WP:1; /* Write Protect */ - uint32_t OPACR91_TP:1; /* Trusted Protect */ - uint32_t OPACR92_BW:1; /* Buffer Writes */ - uint32_t OPACR92_SP:1; /* Supervisor Protect */ - uint32_t OPACR92_WP:1; /* Write Protect */ - uint32_t OPACR92_TP:1; /* Trusted Protect */ - uint32_t OPACR93_BW:1; /* Buffer Writes */ - uint32_t OPACR93_SP:1; /* Supervisor Protect */ - uint32_t OPACR93_WP:1; /* Write Protect */ - uint32_t OPACR93_TP:1; /* Trusted Protect */ - uint32_t OPACR94_BW:1; /* Buffer Writes */ - uint32_t OPACR94_SP:1; /* Supervisor Protect */ - uint32_t OPACR94_WP:1; /* Write Protect */ - uint32_t OPACR94_TP:1; /* Trusted Protect */ - uint32_t OPACR95_BW:1; /* Buffer Writes */ - uint32_t OPACR95_SP:1; /* Supervisor Protect */ - uint32_t OPACR95_WP:1; /* Write Protect */ - uint32_t OPACR95_TP:1; /* Trusted Protect */ - } B; - } PBRIDGE_OPACR88_95_32B_tag; - - - - typedef struct PBRIDGE_struct_tag { /* start of PBRIDGE_tag */ - /* MPROT - Master Privilege Registers */ - PBRIDGE_MPROT_32B_tag MPROT; /* offset: 0x0000 size: 32 bit */ - int8_t PBRIDGE_reserved_0004[28]; - /* PACR0_7 - Peripheral Access Control Registers */ - PBRIDGE_PACR0_7_32B_tag PACR0_7; /* offset: 0x0020 size: 32 bit */ - /* PACR8_15 - Peripheral Access Control Registers */ - PBRIDGE_PACR8_15_32B_tag PACR8_15; /* offset: 0x0024 size: 32 bit */ - /* PACR16_23 - Peripheral Access Control Registers */ - PBRIDGE_PACR16_23_32B_tag PACR16_23; /* offset: 0x0028 size: 32 bit */ - /* PACR24_31 - Peripheral Access Control Registers */ - PBRIDGE_PACR24_31_32B_tag PACR24_31; /* offset: 0x002C size: 32 bit */ - int8_t PBRIDGE_reserved_0030[16]; - /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */ - PBRIDGE_OPACR0_7_32B_tag OPACR0_7; /* offset: 0x0040 size: 32 bit */ - /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */ - PBRIDGE_OPACR8_15_32B_tag OPACR8_15; /* offset: 0x0044 size: 32 bit */ - /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */ - PBRIDGE_OPACR16_23_32B_tag OPACR16_23; /* offset: 0x0048 size: 32 bit */ - /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */ - PBRIDGE_OPACR24_31_32B_tag OPACR24_31; /* offset: 0x004C size: 32 bit */ - /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */ - PBRIDGE_OPACR32_39_32B_tag OPACR32_39; /* offset: 0x0050 size: 32 bit */ - /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */ - PBRIDGE_OPACR40_47_32B_tag OPACR40_47; /* offset: 0x0054 size: 32 bit */ - /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */ - PBRIDGE_OPACR48_55_32B_tag OPACR48_55; /* offset: 0x0058 size: 32 bit */ - /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */ - PBRIDGE_OPACR56_63_32B_tag OPACR56_63; /* offset: 0x005C size: 32 bit */ - /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */ - PBRIDGE_OPACR64_71_32B_tag OPACR64_71; /* offset: 0x0060 size: 32 bit */ - /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */ - PBRIDGE_OPACR72_79_32B_tag OPACR72_79; /* offset: 0x0064 size: 32 bit */ - /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */ - PBRIDGE_OPACR80_87_32B_tag OPACR80_87; /* offset: 0x0068 size: 32 bit */ - /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */ - PBRIDGE_OPACR88_95_32B_tag OPACR88_95; /* offset: 0x006C size: 32 bit */ - } PBRIDGE_tag; - - -#define PBRIDGE (*(volatile PBRIDGE_tag *) 0xFFF00000UL) - - - -/****************************************************************/ -/* */ -/* Module: MAX */ -/* */ -/****************************************************************/ - - - /* Register layout for all registers MPR... */ - - typedef union { /* Master Priority Register for slave port n */ - uint32_t R; - struct { - uint32_t:1; - uint32_t MSTR_7:3; /* Master 7 Priority */ - uint32_t:1; - uint32_t MSTR_6:3; /* Master 6 Priority */ - uint32_t:1; - uint32_t MSTR_5:3; /* Master 5 Priority */ - uint32_t:1; - uint32_t MSTR_4:3; /* Master 4 Priority */ - uint32_t:1; - uint32_t MSTR_3:3; /* Master 3 Priority */ - uint32_t:1; - uint32_t MSTR_2:3; /* Master 2 Priority */ - uint32_t:1; - uint32_t MSTR_1:3; /* Master 1 Priority */ - uint32_t:1; - uint32_t MSTR_0:3; /* Master 0 Priority */ - } B; - } MAX_MPR_32B_tag; - - - /* Register layout for all registers AMPR matches xxx */ - - - /* Register layout for all registers SGPCR... */ - - typedef union { /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ - uint32_t R; - struct { - uint32_t RO:1; /* Read Only */ - uint32_t HLP:1; /* Halt Low Priority */ - uint32_t:6; - uint32_t HPE7:1; /* High Priority Enable */ - uint32_t HPE6:1; /* High Priority Enable */ - uint32_t HPE5:1; /* High Priority Enable */ - uint32_t HPE4:1; /* High Priority Enable */ - uint32_t HPE3:1; /* High Priority Enable */ - uint32_t HPE2:1; /* High Priority Enable */ - uint32_t HPE1:1; /* High Priority Enable */ - uint32_t HPE0:1; /* High Priority Enable */ - uint32_t:6; - uint32_t ARB:2; /* Arbitration Mode */ - uint32_t:2; - uint32_t PCTL:2; /* Parking Control */ - uint32_t:1; - uint32_t PARK:3; /* Park */ - } B; - } MAX_SGPCR_32B_tag; - - - /* Register layout for all registers ASGPCR... */ - - typedef union { /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ - uint32_t R; - struct { - uint32_t:1; - uint32_t HLP:1; /* Halt Low Priority */ - uint32_t:6; - uint32_t HPE7:1; /* High Priority Enable */ - uint32_t HPE6:1; /* High Priority Enable */ - uint32_t HPE5:1; /* High Priority Enable */ - uint32_t HPE4:1; /* High Priority Enable */ - uint32_t HPE3:1; /* High Priority Enable */ - uint32_t HPE2:1; /* High Priority Enable */ - uint32_t HPE1:1; /* High Priority Enable */ - uint32_t HPE0:1; /* High Priority Enable */ - uint32_t:6; - uint32_t ARB:2; /* Arbitration Mode */ - uint32_t:2; - uint32_t PCTL:2; /* Parking Control */ - uint32_t:1; - uint32_t PARK:3; /* Park */ - } B; - } MAX_ASGPCR_32B_tag; - - - /* Register layout for all registers MGPCR... */ - - typedef union { /* MAX_MGPCRn - Master General Purpose Control Register n */ - uint32_t R; - struct { - uint32_t:29; - uint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ - } B; - } MAX_MGPCR_32B_tag; - - - typedef struct MAX_SLAVE_PORT_struct_tag { - - /* Master Priority Register for slave port n */ - MAX_MPR_32B_tag MPR; /* relative offset: 0x0000 */ - /* Alternate Master Priority Register for slave port n */ - MAX_MPR_32B_tag AMPR; /* relative offset: 0x0004 */ - int8_t MAX_SLAVE_PORT_reserved_0008[8]; - /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ - MAX_SGPCR_32B_tag SGPCR; /* relative offset: 0x0010 */ - /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ - MAX_ASGPCR_32B_tag ASGPCR; /* relative offset: 0x0014 */ - int8_t MAX_SLAVE_PORT_reserved_0018[232]; - - } MAX_SLAVE_PORT_tag; - - typedef struct MAX_MASTER_PORT_struct_tag { - - /* MAX_MGPCRn - Master General Purpose Control Register n */ - MAX_MGPCR_32B_tag MGPCR; /* relative offset: 0x0000 */ - int8_t MAX_MASTER_PORT_reserved_0004[252]; - - } MAX_MASTER_PORT_tag; - - - typedef struct MAX_struct_tag { /* start of MAX_tag */ - union { - /* Register set SLAVE_PORT */ - MAX_SLAVE_PORT_tag SLAVE_PORT[8]; /* offset: 0x0000 (0x0100 x 8) */ - - struct { - /* Master Priority Register for slave port n */ - MAX_MPR_32B_tag MPR0; /* offset: 0x0000 size: 32 bit */ - /* Alternate Master Priority Register for slave port n */ - MAX_MPR_32B_tag AMPR0; /* offset: 0x0004 size: 32 bit */ - int8_t MAX_reserved_0008_I1[8]; - /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ - MAX_SGPCR_32B_tag SGPCR0; /* offset: 0x0010 size: 32 bit */ - /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ - MAX_ASGPCR_32B_tag ASGPCR0; /* offset: 0x0014 size: 32 bit */ - int8_t MAX_reserved_0018_I1[232]; - /* Master Priority Register for slave port n */ - MAX_MPR_32B_tag MPR1; /* offset: 0x0100 size: 32 bit */ - /* Alternate Master Priority Register for slave port n */ - MAX_MPR_32B_tag AMPR1; /* offset: 0x0104 size: 32 bit */ - int8_t MAX_reserved_0108_I1[8]; - /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ - MAX_SGPCR_32B_tag SGPCR1; /* offset: 0x0110 size: 32 bit */ - /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ - MAX_ASGPCR_32B_tag ASGPCR1; /* offset: 0x0114 size: 32 bit */ - int8_t MAX_reserved_0118_I1[232]; - /* Master Priority Register for slave port n */ - MAX_MPR_32B_tag MPR2; /* offset: 0x0200 size: 32 bit */ - /* Alternate Master Priority Register for slave port n */ - MAX_MPR_32B_tag AMPR2; /* offset: 0x0204 size: 32 bit */ - int8_t MAX_reserved_0208_I1[8]; - /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ - MAX_SGPCR_32B_tag SGPCR2; /* offset: 0x0210 size: 32 bit */ - /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ - MAX_ASGPCR_32B_tag ASGPCR2; /* offset: 0x0214 size: 32 bit */ - int8_t MAX_reserved_0218_I1[232]; - /* Master Priority Register for slave port n */ - MAX_MPR_32B_tag MPR3; /* offset: 0x0300 size: 32 bit */ - /* Alternate Master Priority Register for slave port n */ - MAX_MPR_32B_tag AMPR3; /* offset: 0x0304 size: 32 bit */ - int8_t MAX_reserved_0308_I1[8]; - /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ - MAX_SGPCR_32B_tag SGPCR3; /* offset: 0x0310 size: 32 bit */ - /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ - MAX_ASGPCR_32B_tag ASGPCR3; /* offset: 0x0314 size: 32 bit */ - int8_t MAX_reserved_0318_I1[232]; - /* Master Priority Register for slave port n */ - MAX_MPR_32B_tag MPR4; /* offset: 0x0400 size: 32 bit */ - /* Alternate Master Priority Register for slave port n */ - MAX_MPR_32B_tag AMPR4; /* offset: 0x0404 size: 32 bit */ - int8_t MAX_reserved_0408_I1[8]; - /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ - MAX_SGPCR_32B_tag SGPCR4; /* offset: 0x0410 size: 32 bit */ - /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ - MAX_ASGPCR_32B_tag ASGPCR4; /* offset: 0x0414 size: 32 bit */ - int8_t MAX_reserved_0418_I1[232]; - /* Master Priority Register for slave port n */ - MAX_MPR_32B_tag MPR5; /* offset: 0x0500 size: 32 bit */ - /* Alternate Master Priority Register for slave port n */ - MAX_MPR_32B_tag AMPR5; /* offset: 0x0504 size: 32 bit */ - int8_t MAX_reserved_0508_I1[8]; - /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ - MAX_SGPCR_32B_tag SGPCR5; /* offset: 0x0510 size: 32 bit */ - /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ - MAX_ASGPCR_32B_tag ASGPCR5; /* offset: 0x0514 size: 32 bit */ - int8_t MAX_reserved_0518_I1[232]; - /* Master Priority Register for slave port n */ - MAX_MPR_32B_tag MPR6; /* offset: 0x0600 size: 32 bit */ - /* Alternate Master Priority Register for slave port n */ - MAX_MPR_32B_tag AMPR6; /* offset: 0x0604 size: 32 bit */ - int8_t MAX_reserved_0608_I1[8]; - /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ - MAX_SGPCR_32B_tag SGPCR6; /* offset: 0x0610 size: 32 bit */ - /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ - MAX_ASGPCR_32B_tag ASGPCR6; /* offset: 0x0614 size: 32 bit */ - int8_t MAX_reserved_0618_I1[232]; - /* Master Priority Register for slave port n */ - MAX_MPR_32B_tag MPR7; /* offset: 0x0700 size: 32 bit */ - /* Alternate Master Priority Register for slave port n */ - MAX_MPR_32B_tag AMPR7; /* offset: 0x0704 size: 32 bit */ - int8_t MAX_reserved_0708_I1[8]; - /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ - MAX_SGPCR_32B_tag SGPCR7; /* offset: 0x0710 size: 32 bit */ - /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ - MAX_ASGPCR_32B_tag ASGPCR7; /* offset: 0x0714 size: 32 bit */ - int8_t MAX_reserved_0718_E1[232]; - }; - - }; - union { - /* Register set MASTER_PORT */ - MAX_MASTER_PORT_tag MASTER_PORT[8]; /* offset: 0x0800 (0x0100 x 8) */ - - struct { - /* MAX_MGPCRn - Master General Purpose Control Register n */ - MAX_MGPCR_32B_tag MGPCR0; /* offset: 0x0800 size: 32 bit */ - int8_t MAX_reserved_0804_I1[252]; - MAX_MGPCR_32B_tag MGPCR1; /* offset: 0x0900 size: 32 bit */ - int8_t MAX_reserved_0904_I1[252]; - MAX_MGPCR_32B_tag MGPCR2; /* offset: 0x0A00 size: 32 bit */ - int8_t MAX_reserved_0A04_I1[252]; - MAX_MGPCR_32B_tag MGPCR3; /* offset: 0x0B00 size: 32 bit */ - int8_t MAX_reserved_0B04_I1[252]; - MAX_MGPCR_32B_tag MGPCR4; /* offset: 0x0C00 size: 32 bit */ - int8_t MAX_reserved_0C04_I1[252]; - MAX_MGPCR_32B_tag MGPCR5; /* offset: 0x0D00 size: 32 bit */ - int8_t MAX_reserved_0D04_I1[252]; - MAX_MGPCR_32B_tag MGPCR6; /* offset: 0x0E00 size: 32 bit */ - int8_t MAX_reserved_0E04_I1[252]; - MAX_MGPCR_32B_tag MGPCR7; /* offset: 0x0F00 size: 32 bit */ - int8_t MAX_reserved_0F04_E1[252]; - }; - - }; - } MAX_tag; - - -#define MAX (*(volatile MAX_tag *) 0xFFF04000UL) - - - -/****************************************************************/ -/* */ -/* Module: MPU */ -/* */ -/****************************************************************/ - - typedef union { /* MPU_CESR - MPU Control/Error Status Register */ - uint32_t R; - struct { - uint32_t SPERR:8; /* Slave Port n Error */ - uint32_t:4; - uint32_t HRL:4; /* Hardware Revision Level */ - uint32_t NSP:4; /* Number of Slave Ports */ - uint32_t NRGD:4; /* Number of Region Descriptors */ - uint32_t:7; - uint32_t VLD:1; /* Valid bit */ - } B; - } MPU_CESR_32B_tag; - - - /* Register layout for all registers EAR... */ - - typedef union { /* MPU_EARn - MPU Error Address Register, Slave Port n */ - uint32_t R; - struct { - uint32_t EADDR:32; /* Error Address */ - } B; - } MPU_EAR_32B_tag; - - - /* Register layout for all registers EDR... */ - - typedef union { /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ - uint32_t R; - struct { - uint32_t EACD:16; /* Error Access Control Detail */ - uint32_t EPID:8; /* Error Process Identification */ - uint32_t EMN:4; /* Error Master Number */ - uint32_t EATTR:3; /* Error Attributes */ - uint32_t ERW:1; /* Error Read/Write */ - } B; - } MPU_EDR_32B_tag; - - - /* Register layout for all registers RGD_WORD0... */ - - typedef union { /* MPU_RGDn_Word0 - MPU Region Descriptor */ - uint32_t R; - struct { - uint32_t SRTADDR:27; /* Start Address */ - uint32_t:5; - } B; - } MPU_RGD_WORD0_32B_tag; - - - /* Register layout for all registers RGD_WORD1... */ - - typedef union { /* MPU_RGDn_Word1 - MPU Region Descriptor */ - uint32_t R; - struct { - uint32_t ENDADDR:27; /* End Address */ - uint32_t:5; - } B; - } MPU_RGD_WORD1_32B_tag; - - - /* Register layout for all registers RGD_WORD2... */ - - typedef union { /* MPU_RGDn_Word2 - MPU Region Descriptor */ - uint32_t R; - struct { - uint32_t M7RE:1; /* Bus Master 7 Read Enable */ - uint32_t M7WE:1; /* Bus Master 7 Write Enable */ - uint32_t M6RE:1; /* Bus Master 6 Read Enable */ - uint32_t M6WE:1; /* Bus Master 7 Write Enable */ - uint32_t M5RE:1; /* Bus Master 5 Read Enable */ - uint32_t M5WE:1; /* Bus Master 5 Write Enable */ - uint32_t M4RE:1; /* Bus Master 4 Read Enable */ - uint32_t M4WE:1; /* Bus Master 4 Write Enable */ - uint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */ - uint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */ - uint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */ - uint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */ - uint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */ - uint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */ - uint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */ - uint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */ - uint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */ - uint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */ - uint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */ - uint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */ - } B; - } MPU_RGD_WORD2_32B_tag; - - - /* Register layout for all registers RGD_WORD3... */ - - typedef union { /* MPU_RGDn_Word3 - MPU Region Descriptor */ - uint32_t R; - struct { - uint32_t PID:8; /* Process Identifier */ - uint32_t PIDMASK:8; /* Process Identifier Mask */ - uint32_t:15; - uint32_t VLD:1; /* Valid */ - } B; - } MPU_RGD_WORD3_32B_tag; - - - /* Register layout for all registers RGDAAC... */ - - typedef union { /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ - uint32_t R; - struct { - uint32_t M7RE:1; /* Bus Master 7 Read Enable */ - uint32_t M7WE:1; /* Bus Master 7 Write Enable */ - uint32_t M6RE:1; /* Bus Master 6 Read Enable */ - uint32_t M6WE:1; /* Bus Master 7 Write Enable */ - uint32_t M5RE:1; /* Bus Master 5 Read Enable */ - uint32_t M5WE:1; /* Bus Master 5 Write Enable */ - uint32_t M4RE:1; /* Bus Master 4 Read Enable */ - uint32_t M4WE:1; /* Bus Master 4 Write Enable */ - uint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */ - uint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */ - uint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */ - uint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */ - uint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */ - uint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */ - uint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */ - uint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */ - uint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */ - uint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */ - uint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */ - uint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */ - } B; - } MPU_RGDAAC_32B_tag; - - - typedef struct MPU_SLAVE_PORT_struct_tag { - - /* MPU_EARn - MPU Error Address Register, Slave Port n */ - MPU_EAR_32B_tag EAR; /* relative offset: 0x0000 */ - /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ - MPU_EDR_32B_tag EDR; /* relative offset: 0x0004 */ - - } MPU_SLAVE_PORT_tag; - - typedef struct MPU_REGION_struct_tag { - - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD_WORD0; /* relative offset: 0x0000 */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD_WORD1; /* relative offset: 0x0004 */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD_WORD2; /* relative offset: 0x0008 */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD_WORD3; /* relative offset: 0x000C */ - - } MPU_REGION_tag; - - - typedef struct MPU_struct_tag { /* start of MPU_tag */ - /* MPU_CESR - MPU Control/Error Status Register */ - MPU_CESR_32B_tag CESR; /* offset: 0x0000 size: 32 bit */ - int8_t MPU_reserved_0004_C[12]; - union { - /* Register set SLAVE_PORT */ - MPU_SLAVE_PORT_tag SLAVE_PORT[4]; /* offset: 0x0010 (0x0008 x 4) */ - - struct { - /* MPU_EARn - MPU Error Address Register, Slave Port n */ - MPU_EAR_32B_tag EAR0; /* offset: 0x0010 size: 32 bit */ - /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ - MPU_EDR_32B_tag EDR0; /* offset: 0x0014 size: 32 bit */ - /* MPU_EARn - MPU Error Address Register, Slave Port n */ - MPU_EAR_32B_tag EAR1; /* offset: 0x0018 size: 32 bit */ - /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ - MPU_EDR_32B_tag EDR1; /* offset: 0x001C size: 32 bit */ - /* MPU_EARn - MPU Error Address Register, Slave Port n */ - MPU_EAR_32B_tag EAR2; /* offset: 0x0020 size: 32 bit */ - /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ - MPU_EDR_32B_tag EDR2; /* offset: 0x0024 size: 32 bit */ - /* MPU_EARn - MPU Error Address Register, Slave Port n */ - MPU_EAR_32B_tag EAR3; /* offset: 0x0028 size: 32 bit */ - /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ - MPU_EDR_32B_tag EDR3; /* offset: 0x002C size: 32 bit */ - }; - - }; - int8_t MPU_reserved_0030_C[976]; - union { - /* Register set REGION */ - MPU_REGION_tag REGION[16]; /* offset: 0x0400 (0x0010 x 16) */ - - struct { - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD0_WORD0; /* offset: 0x0400 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD0_WORD1; /* offset: 0x0404 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD0_WORD2; /* offset: 0x0408 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD0_WORD3; /* offset: 0x040C size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD1_WORD0; /* offset: 0x0410 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD1_WORD1; /* offset: 0x0414 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD1_WORD2; /* offset: 0x0418 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD1_WORD3; /* offset: 0x041C size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD2_WORD0; /* offset: 0x0420 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD2_WORD1; /* offset: 0x0424 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD2_WORD2; /* offset: 0x0428 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD2_WORD3; /* offset: 0x042C size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD3_WORD0; /* offset: 0x0430 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD3_WORD1; /* offset: 0x0434 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD3_WORD2; /* offset: 0x0438 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD3_WORD3; /* offset: 0x043C size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD4_WORD0; /* offset: 0x0440 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD4_WORD1; /* offset: 0x0444 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD4_WORD2; /* offset: 0x0448 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD4_WORD3; /* offset: 0x044C size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD5_WORD0; /* offset: 0x0450 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD5_WORD1; /* offset: 0x0454 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD5_WORD2; /* offset: 0x0458 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD5_WORD3; /* offset: 0x045C size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD6_WORD0; /* offset: 0x0460 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD6_WORD1; /* offset: 0x0464 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD6_WORD2; /* offset: 0x0468 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD6_WORD3; /* offset: 0x046C size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD7_WORD0; /* offset: 0x0470 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD7_WORD1; /* offset: 0x0474 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD7_WORD2; /* offset: 0x0478 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD7_WORD3; /* offset: 0x047C size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD8_WORD0; /* offset: 0x0480 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD8_WORD1; /* offset: 0x0484 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD8_WORD2; /* offset: 0x0488 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD8_WORD3; /* offset: 0x048C size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD9_WORD0; /* offset: 0x0490 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD9_WORD1; /* offset: 0x0494 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD9_WORD2; /* offset: 0x0498 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD9_WORD3; /* offset: 0x049C size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD10_WORD0; /* offset: 0x04A0 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD10_WORD1; /* offset: 0x04A4 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD10_WORD2; /* offset: 0x04A8 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD10_WORD3; /* offset: 0x04AC size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD11_WORD0; /* offset: 0x04B0 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD11_WORD1; /* offset: 0x04B4 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD11_WORD2; /* offset: 0x04B8 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD11_WORD3; /* offset: 0x04BC size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD12_WORD0; /* offset: 0x04C0 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD12_WORD1; /* offset: 0x04C4 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD12_WORD2; /* offset: 0x04C8 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD12_WORD3; /* offset: 0x04CC size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD13_WORD0; /* offset: 0x04D0 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD13_WORD1; /* offset: 0x04D4 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD13_WORD2; /* offset: 0x04D8 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD13_WORD3; /* offset: 0x04DC size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD14_WORD0; /* offset: 0x04E0 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD14_WORD1; /* offset: 0x04E4 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD14_WORD2; /* offset: 0x04E8 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD14_WORD3; /* offset: 0x04EC size: 32 bit */ - /* MPU_RGDn_Word0 - MPU Region Descriptor */ - MPU_RGD_WORD0_32B_tag RGD15_WORD0; /* offset: 0x04F0 size: 32 bit */ - /* MPU_RGDn_Word1 - MPU Region Descriptor */ - MPU_RGD_WORD1_32B_tag RGD15_WORD1; /* offset: 0x04F4 size: 32 bit */ - /* MPU_RGDn_Word2 - MPU Region Descriptor */ - MPU_RGD_WORD2_32B_tag RGD15_WORD2; /* offset: 0x04F8 size: 32 bit */ - /* MPU_RGDn_Word3 - MPU Region Descriptor */ - MPU_RGD_WORD3_32B_tag RGD15_WORD3; /* offset: 0x04FC size: 32 bit */ - }; - - }; - int8_t MPU_reserved_0500_C[768]; - union { - /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ - MPU_RGDAAC_32B_tag RGDAAC[16]; /* offset: 0x0800 (0x0004 x 16) */ - - struct { - /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ - MPU_RGDAAC_32B_tag RGDAAC0; /* offset: 0x0800 size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC1; /* offset: 0x0804 size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC2; /* offset: 0x0808 size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC3; /* offset: 0x080C size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC4; /* offset: 0x0810 size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC5; /* offset: 0x0814 size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC6; /* offset: 0x0818 size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC7; /* offset: 0x081C size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC8; /* offset: 0x0820 size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC9; /* offset: 0x0824 size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC10; /* offset: 0x0828 size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC11; /* offset: 0x082C size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC12; /* offset: 0x0830 size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC13; /* offset: 0x0834 size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC14; /* offset: 0x0838 size: 32 bit */ - MPU_RGDAAC_32B_tag RGDAAC15; /* offset: 0x083C size: 32 bit */ - }; - - }; - } MPU_tag; - - -#define MPU (*(volatile MPU_tag *) 0xFFF10000UL) - - - -/****************************************************************/ -/* */ -/* Module: SEMA4 */ -/* */ -/****************************************************************/ - - - /* Register layout for all registers GATE... */ - - typedef union { /* SEMA4_GATEn - Semephores Gate Register */ - uint8_t R; - struct { - uint8_t:6; - uint8_t GTFSM:2; /* Gate Finite State machine */ - } B; - } SEMA4_GATE_8B_tag; - - typedef union { /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */ - uint16_t R; - struct { - uint16_t INE:16; /* Interrupt Request Notification Enable */ - } B; - } SEMA4_CP0INE_16B_tag; - - typedef union { /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */ - uint16_t R; - struct { - uint16_t INE:16; /* Interrupt Request Notification Enable */ - } B; - } SEMA4_CP1INE_16B_tag; - - typedef union { /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */ - uint16_t R; - struct { - uint16_t GN:16; /* Gate 0 Notification */ - } B; - } SEMA4_CP0NTF_16B_tag; - - typedef union { /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */ - uint16_t R; - struct { - uint16_t GN:16; /* Gate 1 Notification */ - } B; - } SEMA4_CP1NTF_16B_tag; - - typedef union { /* SEMA4_RSTGT - Semaphores Reset Gate */ - uint16_t R; - struct { - uint16_t:2; - uint16_t RSTGSM:2; /* Reset Gate Finite State Machine */ - uint16_t RSTGDP:7; /* Reset Gate Data Pattern */ - uint16_t RSTGMS:3; /* Reset Gate Bus Master */ - uint16_t RSTGTN:8; /* Reset Gate Number */ - } B; - } SEMA4_RSTGT_16B_tag; - - typedef union { /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */ - uint16_t R; - struct { - uint16_t:2; - uint16_t RSTNSM:2; /* Reset Gate Finite State Machine */ - uint16_t RSTNDP:7; /* Reset Gate Data Pattern */ - uint16_t RSTNMS:3; /* Reset Gate Bus Master */ - uint16_t RSTNTN:8; /* Reset Gate Number */ - } B; - } SEMA4_RSTNTF_16B_tag; - - - - typedef struct SEMA4_struct_tag { /* start of SEMA4_tag */ - union { - /* SEMA4_GATEn - Semephores Gate Register */ - SEMA4_GATE_8B_tag GATE[16]; /* offset: 0x0000 (0x0001 x 16) */ - - struct { - /* SEMA4_GATEn - Semephores Gate Register */ - SEMA4_GATE_8B_tag GATE0; /* offset: 0x0000 size: 8 bit */ - SEMA4_GATE_8B_tag GATE1; /* offset: 0x0001 size: 8 bit */ - SEMA4_GATE_8B_tag GATE2; /* offset: 0x0002 size: 8 bit */ - SEMA4_GATE_8B_tag GATE3; /* offset: 0x0003 size: 8 bit */ - SEMA4_GATE_8B_tag GATE4; /* offset: 0x0004 size: 8 bit */ - SEMA4_GATE_8B_tag GATE5; /* offset: 0x0005 size: 8 bit */ - SEMA4_GATE_8B_tag GATE6; /* offset: 0x0006 size: 8 bit */ - SEMA4_GATE_8B_tag GATE7; /* offset: 0x0007 size: 8 bit */ - SEMA4_GATE_8B_tag GATE8; /* offset: 0x0008 size: 8 bit */ - SEMA4_GATE_8B_tag GATE9; /* offset: 0x0009 size: 8 bit */ - SEMA4_GATE_8B_tag GATE10; /* offset: 0x000A size: 8 bit */ - SEMA4_GATE_8B_tag GATE11; /* offset: 0x000B size: 8 bit */ - SEMA4_GATE_8B_tag GATE12; /* offset: 0x000C size: 8 bit */ - SEMA4_GATE_8B_tag GATE13; /* offset: 0x000D size: 8 bit */ - SEMA4_GATE_8B_tag GATE14; /* offset: 0x000E size: 8 bit */ - SEMA4_GATE_8B_tag GATE15; /* offset: 0x000F size: 8 bit */ - }; - - }; - int8_t SEMA4_reserved_0010[48]; - /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */ - SEMA4_CP0INE_16B_tag CP0INE; /* offset: 0x0040 size: 16 bit */ - int8_t SEMA4_reserved_0042[6]; - /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */ - SEMA4_CP1INE_16B_tag CP1INE; /* offset: 0x0048 size: 16 bit */ - int8_t SEMA4_reserved_004A[54]; - /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */ - SEMA4_CP0NTF_16B_tag CP0NTF; /* offset: 0x0080 size: 16 bit */ - int8_t SEMA4_reserved_0082[6]; - /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */ - SEMA4_CP1NTF_16B_tag CP1NTF; /* offset: 0x0088 size: 16 bit */ - int8_t SEMA4_reserved_008A[118]; - /* SEMA4_RSTGT - Semaphores Reset Gate */ - SEMA4_RSTGT_16B_tag RSTGT; /* offset: 0x0100 size: 16 bit */ - int8_t SEMA4_reserved_0102[2]; - /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */ - SEMA4_RSTNTF_16B_tag RSTNTF; /* offset: 0x0104 size: 16 bit */ - } SEMA4_tag; - - -#define SEMA4 (*(volatile SEMA4_tag *) 0xFFF24000UL) - - - -/****************************************************************/ -/* */ -/* Module: SWT */ -/* */ -/****************************************************************/ - - typedef union { /* SWT_CR - Control Register */ - uint32_t R; - struct { - uint32_t MAP0:1; /* Master Acces Protection for Master 0 */ - uint32_t MAP1:1; /* Master Acces Protection for Master 1 */ - uint32_t MAP2:1; /* Master Acces Protection for Master 2 */ - uint32_t MAP3:1; /* Master Acces Protection for Master 3 */ - uint32_t MAP4:1; /* Master Acces Protection for Master 4 */ - uint32_t MAP5:1; /* Master Acces Protection for Master 5 */ - uint32_t MAP6:1; /* Master Acces Protection for Master 6 */ - uint32_t MAP7:1; /* Master Acces Protection for Master 7 */ - uint32_t:14; - uint32_t KEY:1; /* Keyed Service Mode */ - uint32_t RIA:1; /* Reset on Invalid Access */ - uint32_t WND:1; /* Window Mode */ - uint32_t ITR:1; /* Interrupt Then Reset */ - uint32_t HLK:1; /* Hard Lock */ - uint32_t SLK:1; /* Soft Lock */ - uint32_t:1; - uint32_t STP:1; /* Stop Mode Control */ - uint32_t FRZ:1; /* Debug Mode Control */ - uint32_t WEN:1; /* Watchdog Enabled */ - } B; - } SWT_CR_32B_tag; - - typedef union { /* SWT_IR - SWT Interrupt Register */ - uint32_t R; - struct { - uint32_t:31; - uint32_t TIF:1; /* Time Out Interrupt Flag */ - } B; - } SWT_IR_32B_tag; - - typedef union { /* SWT_TO - SWT Time-Out Register */ - uint32_t R; - struct { - uint32_t WTO:32; /* Watchdog Time Out Period */ - } B; - } SWT_TO_32B_tag; - - typedef union { /* SWT_WN - SWT Window Register */ - uint32_t R; - struct { - uint32_t WST:32; /* Watchdog Time Out Period */ - } B; - } SWT_WN_32B_tag; - - typedef union { /* SWT_SR - SWT Service Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t WSC:16; /* Watchdog Service Code */ - } B; - } SWT_SR_32B_tag; - - typedef union { /* SWT_CO - SWT Counter Output Register */ - uint32_t R; - struct { - uint32_t CNT:32; /* Watchdog Count */ - } B; - } SWT_CO_32B_tag; - - typedef union { /* SWT_SK - SWT Service Key Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t SERVICEKEY:16; /* Service Key */ - } B; - } SWT_SK_32B_tag; - - - - typedef struct SWT_struct_tag { /* start of SWT_tag */ - /* SWT_CR - Control Register */ - SWT_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ - /* SWT_IR - SWT Interrupt Register */ - SWT_IR_32B_tag IR; /* offset: 0x0004 size: 32 bit */ - /* SWT_TO - SWT Time-Out Register */ - SWT_TO_32B_tag TO; /* offset: 0x0008 size: 32 bit */ - /* SWT_WN - SWT Window Register */ - SWT_WN_32B_tag WN; /* offset: 0x000C size: 32 bit */ - /* SWT_SR - SWT Service Register */ - SWT_SR_32B_tag SR; /* offset: 0x0010 size: 32 bit */ - /* SWT_CO - SWT Counter Output Register */ - SWT_CO_32B_tag CO; /* offset: 0x0014 size: 32 bit */ - /* SWT_SK - SWT Service Key Register */ - SWT_SK_32B_tag SK; /* offset: 0x0018 size: 32 bit */ - } SWT_tag; - - -#define SWT (*(volatile SWT_tag *) 0xFFF38000UL) - - - -/****************************************************************/ -/* */ -/* Module: STM */ -/* */ -/****************************************************************/ - - typedef union { /* STM_CR - Control Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t CPS:8; /* Counter Prescaler */ - uint32_t:6; - uint32_t FRZ:1; /* Freeze Control */ - uint32_t TEN:1; /* Timer Counter Enabled */ - } B; - } STM_CR_32B_tag; - - typedef union { /* STM_CNT - STM Count Register */ - uint32_t R; - } STM_CNT_32B_tag; - - - /* Register layout for all registers CCR... */ - - typedef union { /* STM_CCRn - STM Channel Control Register */ - uint32_t R; - struct { - uint32_t:31; - uint32_t CEN:1; /* Channel Enable */ - } B; - } STM_CCR_32B_tag; - - - /* Register layout for all registers CIR... */ - - typedef union { /* STM_CIRn - STM Channel Interrupt Register */ - uint32_t R; - struct { - uint32_t:31; - uint32_t CIF:1; /* Channel Interrupt Flag */ - } B; - } STM_CIR_32B_tag; - - - /* Register layout for all registers CMP... */ - - typedef union { /* STM_CMPn - STM Channel Compare Register */ - uint32_t R; - } STM_CMP_32B_tag; - - - typedef struct STM_CHANNEL_struct_tag { - - /* STM_CCRn - STM Channel Control Register */ - STM_CCR_32B_tag CCR; /* relative offset: 0x0000 */ - /* STM_CIRn - STM Channel Interrupt Register */ - STM_CIR_32B_tag CIR; /* relative offset: 0x0004 */ - /* STM_CMPn - STM Channel Compare Register */ - STM_CMP_32B_tag CMP; /* relative offset: 0x0008 */ - int8_t STM_CHANNEL_reserved_000C[4]; - - } STM_CHANNEL_tag; - - - typedef struct STM_struct_tag { /* start of STM_tag */ - union { - STM_CR_32B_tag CR0; /* deprecated - please avoid */ - - /* STM_CR - Control Register */ - STM_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ - - }; - union { - STM_CNT_32B_tag CNT0; /* deprecated - please avoid */ - - /* STM_CNT - STM Count Register */ - STM_CNT_32B_tag CNT; /* offset: 0x0004 size: 32 bit */ - - }; - int8_t STM_reserved_0008_C[8]; - union { - /* Register set CHANNEL */ - STM_CHANNEL_tag CHANNEL[4]; /* offset: 0x0010 (0x0010 x 4) */ - - struct { - /* STM_CCRn - STM Channel Control Register */ - STM_CCR_32B_tag CCR0; /* offset: 0x0010 size: 32 bit */ - /* STM_CIRn - STM Channel Interrupt Register */ - STM_CIR_32B_tag CIR0; /* offset: 0x0014 size: 32 bit */ - /* STM_CMPn - STM Channel Compare Register */ - STM_CMP_32B_tag CMP0; /* offset: 0x0018 size: 32 bit */ - int8_t STM_reserved_001C_I1[4]; - /* STM_CCRn - STM Channel Control Register */ - STM_CCR_32B_tag CCR1; /* offset: 0x0020 size: 32 bit */ - /* STM_CIRn - STM Channel Interrupt Register */ - STM_CIR_32B_tag CIR1; /* offset: 0x0024 size: 32 bit */ - /* STM_CMPn - STM Channel Compare Register */ - STM_CMP_32B_tag CMP1; /* offset: 0x0028 size: 32 bit */ - int8_t STM_reserved_002C_I1[4]; - /* STM_CCRn - STM Channel Control Register */ - STM_CCR_32B_tag CCR2; /* offset: 0x0030 size: 32 bit */ - /* STM_CIRn - STM Channel Interrupt Register */ - STM_CIR_32B_tag CIR2; /* offset: 0x0034 size: 32 bit */ - /* STM_CMPn - STM Channel Compare Register */ - STM_CMP_32B_tag CMP2; /* offset: 0x0038 size: 32 bit */ - int8_t STM_reserved_003C_I1[4]; - /* STM_CCRn - STM Channel Control Register */ - STM_CCR_32B_tag CCR3; /* offset: 0x0040 size: 32 bit */ - /* STM_CIRn - STM Channel Interrupt Register */ - STM_CIR_32B_tag CIR3; /* offset: 0x0044 size: 32 bit */ - /* STM_CMPn - STM Channel Compare Register */ - STM_CMP_32B_tag CMP3; /* offset: 0x0048 size: 32 bit */ - int8_t STM_reserved_004C_E1[4]; - }; - - }; - } STM_tag; - - -#define STM (*(volatile STM_tag *) 0xFFF3C000UL) - - - -/****************************************************************/ -/* */ -/* Module: SPP_MCM */ -/* */ -/****************************************************************/ - - typedef union { /* SPP_MCM_PCT - Processor Core Type */ - uint16_t R; - struct { - uint16_t PCTYPE:16; /* Processor Core Type */ - } B; - } SPP_MCM_PCT_16B_tag; - - typedef union { /* SPP_MCM_PLREV - SOC-Defined Platform Revision */ - uint16_t R; - struct { - uint16_t PLREVISION:16; /* Platform Revision */ - } B; - } SPP_MCM_PLREV_16B_tag; - - typedef union { /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */ - uint32_t R; - struct { - uint32_t PMC:32; /* IPS Module Configuration */ - } B; - } SPP_MCM_IOPMC_32B_tag; - - typedef union { /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */ - uint8_t R; - struct { - uint8_t POR:1; /* Power on Reset */ -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t OFPLR:1; /* Off-Platform Reset */ -#else - uint8_t DIR:1; /* deprecated name - please avoid */ -#endif - uint8_t:6; - } B; - } SPP_MCM_MRSR_8B_tag; - - typedef union { /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */ - uint8_t R; - struct { - uint8_t ENBWCR:1; /* Enable WCR */ - uint8_t:3; - uint8_t PRILVL:4; /* Interrupt Priority Level */ - } B; - } SPP_MCM_MWCR_8B_tag; - - typedef union { /* SPP_MCM_MIR - Miscellaneous Interrupt Register */ - uint8_t R; - struct { - uint8_t FB0AI:1; /* Flash Bank 0 Abort Interrupt */ - uint8_t FB0SI:1; /* Flash Bank 0 Stall Interrupt */ - uint8_t FB1AI:1; /* Flash Bank 1 Abort Interrupt */ - uint8_t FB1SI:1; /* Flash Bank 1 Stall Interrupt */ - uint8_t FB2AI:1; /* Flash Bank 2 Abort Interrupt */ - uint8_t FB2SI:1; /* Flash Bank 2 Stall Interrupt */ - uint8_t:2; - } B; - } SPP_MCM_MIR_8B_tag; - - typedef union { /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */ - uint32_t R; - struct { - uint32_t MUSERDCR:32; /* User Defined Control Register */ - } B; - } SPP_MCM_MUDCR_32B_tag; - - typedef union { /* SPP_MCM_ECR - ECC Configuration Register */ - uint8_t R; - struct { - uint8_t:2; -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t EPR1BR:1; /* Enable Platform RAM 1-bit Reporting */ -#else - uint8_t ER1BR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t EPF1BR:1; /* Enable Platform FLASH 1-bit Reporting */ -#else - uint8_t EF1BR:1; /* deprecated name - please avoid */ -#endif - uint8_t:2; -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t EPRNCR:1; /* Enable Platform RAM Non-Correctable Reporting */ -#else - uint8_t ERNCR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t EPFNCR:1; /* Enable Platform FLASH Non-Correctable Reporting */ -#else - uint8_t EFNCR:1; /* deprecated name - please avoid */ -#endif - } B; - } SPP_MCM_ECR_8B_tag; - - typedef union { /* SPP_MCM_ESR - ECC Status Register */ - uint8_t R; - struct { - uint8_t:2; -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t PR1BC:1; /* Platform RAM 1-bit Correction */ -#else - uint8_t R1BC:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t PF1BC:1; /* Platform FLASH 1-bit Correction */ -#else - uint8_t F1BC:1; /* deprecated name - please avoid */ -#endif - uint8_t:2; -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t PRNCE:1; /* Platform RAM Non-Correctable Error */ -#else - uint8_t RNCE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t PFNCE:1; /* Platform FLASH Non-Correctable Error */ -#else - uint8_t FNCE:1; /* deprecated name - please avoid */ -#endif - } B; - } SPP_MCM_ESR_8B_tag; - - typedef union { /* SPP_MCM_EEGR - ECC Error Generation Register */ - uint16_t R; - struct { - uint16_t FRCAP:1; /* Force Platform RAM Error Injection Access Protection */ - uint16_t:1; - uint16_t FRC1BI:1; /* Force Platform RAM Continuous 1-Bit Data Inversions */ - uint16_t FR11BI:1; /* Force Platform RAM One 1-Bit Data Inversion */ - uint16_t:2; - uint16_t FRCNCI:1; /* Force Platform RAM Continuous Noncorrectable Data Inversions */ - uint16_t FR1NCI:1; /* Force Platform RAM One Noncorrectable Data Inversions */ - uint16_t:1; - uint16_t ERRBIT:7; /* Error Bit Position */ - } B; - } SPP_MCM_EEGR_16B_tag; - - typedef union { /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */ - uint32_t R; - } SPP_MCM_PFEAR_32B_tag; - - typedef union { /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */ - uint8_t R; - } SPP_MCM_PFEMR_8B_tag; - - typedef union { /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */ - uint8_t R; - struct { -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t F_WRITE:1; /* AMBA-AHBH Write */ -#else - uint8_t WRITE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t F_SIZE:3; /* AMBA-AHBH Size */ -#else - uint8_t SIZE:3; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t F_PROTECT:4; /* AMBA-AHBH PROT */ -#else - uint8_t PROTECTION:4; /* deprecated name - please avoid */ -#endif - } B; - } SPP_MCM_PFEAT_8B_tag; - - typedef union { /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */ - uint32_t R; - } SPP_MCM_PFEDRH_32B_tag; - - typedef union { /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */ - uint32_t R; - } SPP_MCM_PFEDR_32B_tag; - - typedef union { /* SPP_MCM_PREAR - Platform RAM ECC Address Register */ - uint32_t R; - } SPP_MCM_PREAR_32B_tag; - - typedef union { /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */ - uint8_t R; - } SPP_MCM_PRESR_8B_tag; - - typedef union { /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */ - uint8_t R; - struct { - uint8_t:4; -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t PR_EMR:4; /* Platform RAM ECC Master Number */ -#else - uint8_t REMR:4; /* deprecated name - please avoid */ -#endif - } B; - } SPP_MCM_PREMR_8B_tag; - - typedef union { /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */ - uint8_t R; - struct { -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t R_WRITE:1; /* AMBA-AHBH Write */ -#else - uint8_t WRITE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t R_SIZE:3; /* AMBA-AHBH Size */ -#else - uint8_t SIZE:3; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_SPP_MCM - uint8_t R_PROTECT:4; /* AMBA-AHBH PROT */ -#else - uint8_t PROTECTION:4; /* deprecated name - please avoid */ -#endif - } B; - } SPP_MCM_PREAT_8B_tag; - - typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */ - uint32_t R; - } SPP_MCM_PREDRH_32B_tag; - - typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register */ - uint32_t R; - } SPP_MCM_PREDR_32B_tag; - - - - typedef struct SPP_MCM_struct_tag { /* start of SPP_MCM_tag */ - /* SPP_MCM_PCT - Processor Core Type */ - SPP_MCM_PCT_16B_tag PCT; /* offset: 0x0000 size: 16 bit */ - union { - SPP_MCM_PLREV_16B_tag REV; /* deprecated - please avoid */ - - /* SPP_MCM_PLREV - SOC-Defined Platform Revision */ - SPP_MCM_PLREV_16B_tag PLREV; /* offset: 0x0002 size: 16 bit */ - - }; - int8_t SPP_MCM_reserved_0004_C[4]; - union { - SPP_MCM_IOPMC_32B_tag MC; /* deprecated - please avoid */ - - /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */ - SPP_MCM_IOPMC_32B_tag IOPMC; /* offset: 0x0008 size: 32 bit */ - - }; - int8_t SPP_MCM_reserved_000C[3]; - /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */ - SPP_MCM_MRSR_8B_tag MRSR; /* offset: 0x000F size: 8 bit */ - int8_t SPP_MCM_reserved_0010[3]; - /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */ - SPP_MCM_MWCR_8B_tag MWCR; /* offset: 0x0013 size: 8 bit */ - int8_t SPP_MCM_reserved_0014[11]; - /* SPP_MCM_MIR - Miscellaneous Interrupt Register */ - SPP_MCM_MIR_8B_tag MIR; /* offset: 0x001F size: 8 bit */ - int8_t SPP_MCM_reserved_0020[4]; - /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */ - SPP_MCM_MUDCR_32B_tag MUDCR; /* offset: 0x0024 size: 32 bit */ - int8_t SPP_MCM_reserved_0028[27]; - /* SPP_MCM_ECR - ECC Configuration Register */ - SPP_MCM_ECR_8B_tag ECR; /* offset: 0x0043 size: 8 bit */ - int8_t SPP_MCM_reserved_0044[3]; - /* SPP_MCM_ESR - ECC Status Register */ - SPP_MCM_ESR_8B_tag ESR; /* offset: 0x0047 size: 8 bit */ - int8_t SPP_MCM_reserved_0048[2]; - /* SPP_MCM_EEGR - ECC Error Generation Register */ - SPP_MCM_EEGR_16B_tag EEGR; /* offset: 0x004A size: 16 bit */ - int8_t SPP_MCM_reserved_004C_C[4]; - union { - /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */ - SPP_MCM_PFEAR_32B_tag PFEAR; /* offset: 0x0050 size: 32 bit */ - - SPP_MCM_PFEAR_32B_tag FEAR; /* deprecated - please avoid */ - - }; - int8_t SPP_MCM_reserved_0054_C[2]; - union { - /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */ - SPP_MCM_PFEMR_8B_tag PFEMR; /* offset: 0x0056 size: 8 bit */ - - SPP_MCM_PFEMR_8B_tag FEMR; /* deprecated - please avoid */ - - }; - union { - /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */ - SPP_MCM_PFEAT_8B_tag PFEAT; /* offset: 0x0057 size: 8 bit */ - - SPP_MCM_PFEAT_8B_tag FEAT; /* deprecated - please avoid */ - - }; - /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */ - SPP_MCM_PFEDRH_32B_tag PFEDRH; /* offset: 0x0058 size: 32 bit */ - union { - /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */ - SPP_MCM_PFEDR_32B_tag PFEDR; /* offset: 0x005C size: 32 bit */ - - SPP_MCM_PFEDR_32B_tag FEDR; /* deprecated - please avoid */ - - }; - union { - SPP_MCM_PREAR_32B_tag REAR; /* deprecated - please avoid */ - - /* SPP_MCM_PREAR - Platform RAM ECC Address Register */ - SPP_MCM_PREAR_32B_tag PREAR; /* offset: 0x0060 size: 32 bit */ - - }; - int8_t SPP_MCM_reserved_0064_C; - union { - SPP_MCM_PRESR_8B_tag RESR; /* deprecated - please avoid */ - - /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */ - SPP_MCM_PRESR_8B_tag PRESR; /* offset: 0x0065 size: 8 bit */ - - }; - union { - SPP_MCM_PREMR_8B_tag REMR; /* deprecated - please avoid */ - - /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */ - SPP_MCM_PREMR_8B_tag PREMR; /* offset: 0x0066 size: 8 bit */ - - }; - union { - SPP_MCM_PREAT_8B_tag REAT; /* deprecated - please avoid */ - - /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */ - SPP_MCM_PREAT_8B_tag PREAT; /* offset: 0x0067 size: 8 bit */ - - }; - /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */ - SPP_MCM_PREDRH_32B_tag PREDRH; /* offset: 0x0068 size: 32 bit */ - union { - SPP_MCM_PREDR_32B_tag REDR; /* deprecated - please avoid */ - - /* SPP_MCM_PREDR - Platform RAM ECC Data Register */ - SPP_MCM_PREDR_32B_tag PREDR; /* offset: 0x006C size: 32 bit */ - - }; - } SPP_MCM_tag; - - -#define SPP_MCM (*(volatile SPP_MCM_tag *) 0xFFF40000UL) - - - -/****************************************************************/ -/* */ -/* Module: SPP_DMA2 */ -/* */ -/****************************************************************/ - - typedef union { /* SPP_DMA2_DMACR - DMA Control Register */ - uint32_t R; - struct { - uint32_t:14; - uint32_t CX:1; /* Cancel Transfer */ - uint32_t ECX:1; /* Error Cancel Transfer */ - uint32_t GRP3PRI:2; /* Channel Group 3 Priority */ - uint32_t GRP2PRI:2; /* Channel Group 2 Priority */ - uint32_t GRP1PRI:2; /* Channel Group 1 Priority */ - uint32_t GRP0PRI:2; /* Channel Group 0 Priority */ - uint32_t EMLM:1; /* Enable Minor Loop Mapping */ - uint32_t CLM:1; /* Continuous Link Mode */ - uint32_t HALT:1; /* Halt DMA Operations */ - uint32_t HOE:1; /* Halt on Error */ - uint32_t ERGA:1; /* Enable Round Robin Group Arbitration */ - uint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */ - uint32_t EDBG:1; /* Enable Debug */ - uint32_t EBW:1; /* Enable Buffered Writes */ - } B; - } SPP_DMA2_DMACR_32B_tag; - - typedef union { /* SPP_DMA2_DMAES - DMA Error Status Register */ - uint32_t R; - struct { - uint32_t VLD:1; /* Logical OR of DMAERRH and DMAERRL status bits */ - uint32_t:14; - uint32_t ECX:1; /* Transfer Cancelled */ - uint32_t GPE:1; /* Group Priority Error */ - uint32_t CPE:1; /* Channel Priority Error */ - uint32_t ERRCHN:6; /* Error Channel Number or Cancelled Channel Number */ - uint32_t SAE:1; /* Source Address Error */ - uint32_t SOE:1; /* Source Offset Error */ - uint32_t DAE:1; /* Destination Address Error */ - uint32_t DOE:1; /* Destination Offset Error */ - uint32_t NCE:1; /* Nbytes/Citer Configuration Error */ - uint32_t SGE:1; /* Scatter/Gather Configuration Error */ - uint32_t SBE:1; /* Source Bus Error */ - uint32_t DBE:1; /* Destination Bus Error */ - } B; - } SPP_DMA2_DMAES_32B_tag; - - typedef union { /* SPP_DMA2_DMAERQH - DMA Enable Request Register */ - uint32_t R; - struct { - uint32_t ERQ:32; /* DMA Enable Request */ - } B; - } SPP_DMA2_DMAERQH_32B_tag; - - typedef union { /* SPP_DMA2_DMAERQL - DMA Enable Request Register */ - uint32_t R; - struct { - uint32_t ERQ:32; /* DMA Enable Request */ - } B; - } SPP_DMA2_DMAERQL_32B_tag; - - typedef union { /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */ - uint32_t R; - struct { - uint32_t EEI:32; /* DMA Enable Error Interrupt */ - } B; - } SPP_DMA2_DMAEEIH_32B_tag; - - typedef union { /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */ - uint32_t R; - struct { - uint32_t EEI:32; /* DMA Enable Error Interrupt */ - } B; - } SPP_DMA2_DMAEEIL_32B_tag; - - typedef union { /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */ - uint8_t R; - struct { - uint8_t:1; - uint8_t SERQ:7; /* Set Enable Request */ - } B; - } SPP_DMA2_DMASERQ_8B_tag; - - typedef union { /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */ - uint8_t R; - struct { - uint8_t:1; - uint8_t CERQ:7; /* Clear Enable Request */ - } B; - } SPP_DMA2_DMACERQ_8B_tag; - - typedef union { /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */ - uint8_t R; - struct { - uint8_t:1; - uint8_t SEEI:7; /* Set Enable Error Interrupt */ - } B; - } SPP_DMA2_DMASEEI_8B_tag; - - typedef union { /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */ - uint8_t R; - struct { - uint8_t:1; - uint8_t CEEI:7; /* Clear Enable Error Interrupt */ - } B; - } SPP_DMA2_DMACEEI_8B_tag; - - typedef union { /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */ - uint8_t R; - struct { - uint8_t:1; - uint8_t CINT:7; /* Clear Interrupt Request */ - } B; - } SPP_DMA2_DMACINT_8B_tag; - - typedef union { /* SPP_DMA2_DMACERR - DMA Clear Error */ - uint8_t R; - struct { - uint8_t:1; - uint8_t CERR:7; /* Clear Error Indicator */ - } B; - } SPP_DMA2_DMACERR_8B_tag; - - typedef union { /* SPP_DMA2_DMASSRT - DMA Set START Bit */ - uint8_t R; - struct { - uint8_t:1; - uint8_t SSRT:7; /* Set START Bit */ - } B; - } SPP_DMA2_DMASSRT_8B_tag; - - typedef union { /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */ - uint8_t R; - struct { - uint8_t:1; - uint8_t CDNE:7; /* Clear DONE Status Bit */ - } B; - } SPP_DMA2_DMACDNE_8B_tag; - - typedef union { /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */ - uint32_t R; - struct { - uint32_t INT:32; /* DMA Interrupt Request */ - } B; - } SPP_DMA2_DMAINTH_32B_tag; - - typedef union { /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */ - uint32_t R; - struct { - uint32_t INT:32; /* DMA Interrupt Request */ - } B; - } SPP_DMA2_DMAINTL_32B_tag; - - typedef union { /* SPP_DMA2_DMAERRH - DMA Error Register */ - uint32_t R; - struct { - uint32_t ERR:32; /* DMA Error n */ - } B; - } SPP_DMA2_DMAERRH_32B_tag; - - typedef union { /* SPP_DMA2_DMAERRL - DMA Error Register */ - uint32_t R; - struct { - uint32_t ERR:32; /* DMA Error n */ - } B; - } SPP_DMA2_DMAERRL_32B_tag; - - typedef union { /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */ - uint32_t R; - struct { - uint32_t HRS:32; /* DMA Hardware Request Status */ - } B; - } SPP_DMA2_DMAHRSH_32B_tag; - - typedef union { /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */ - uint32_t R; - struct { - uint32_t HRS:32; /* DMA Hardware Request Status */ - } B; - } SPP_DMA2_DMAHRSL_32B_tag; - - typedef union { /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */ - uint32_t R; - struct { - uint32_t GPOR:32; /* DMA General Purpose Output */ - } B; - } SPP_DMA2_DMAGPOR_32B_tag; - - - /* Register layout for all registers DCHPRI... */ - - typedef union { /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ - uint8_t R; - struct { - uint8_t ECP:1; /* Enable Channel Preemption */ - uint8_t DPA:1; /* Disable Preempt Ability */ - uint8_t GRPPRI:2; /* Channel n Current Group Priority */ - uint8_t CHPRI:4; /* Channel n Arbitration Priority */ - } B; - } SPP_DMA2_DCHPRI_8B_tag; - - - /* Register layout for all registers TCDWORD0_... */ - - typedef union { /* SPP_DMA2_TCDn Word0 - Source Address */ - uint32_t R; - struct { - uint32_t SADDR:32; /* Source Address */ - } B; - } SPP_DMA2_TCDWORD0__32B_tag; - - - /* Register layout for all registers TCDWORD4_... */ - - typedef union { /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - uint32_t R; - struct { - uint32_t SMOD:5; /* Source Address Modulo */ - uint32_t SSIZE:3; /* Source Data Transfer Size */ - uint32_t DMOD:5; /* Destination Address Module */ - uint32_t DSIZE:3; /* Destination Data Transfer Size */ - uint32_t SOFF:16; /* Source Address Signed Offset */ - } B; - } SPP_DMA2_TCDWORD4__32B_tag; - - - /* Register layout for all registers TCDWORD8_... */ - - typedef union { /* SPP_DMA2_TCDn Word2 - nbytes */ - uint32_t R; - struct { - uint32_t SMLOE:1; /* Source Minor Loop Offset Enable */ - uint32_t DMLOE:1; /* Destination Minor Loop Offset Enable */ - uint32_t MLOFF:20; /* Minor Loop Offset */ - uint32_t NBYTES:10; /* Inner Minor byte transfer Count */ - } B; - } SPP_DMA2_TCDWORD8__32B_tag; - - - /* Register layout for all registers TCDWORD12_... */ - - typedef union { /* SPP_DMA2_TCDn Word3 - slast */ - uint32_t R; - struct { - uint32_t SLAST:32; /* Last Source Address Adjustment */ - } B; - } SPP_DMA2_TCDWORD12__32B_tag; - - - /* Register layout for all registers TCDWORD16_... */ - - typedef union { /* SPP_DMA2_TCDn Word4 - daddr */ - uint32_t R; - struct { - uint32_t DADDR:32; /* Destination Address */ - } B; - } SPP_DMA2_TCDWORD16__32B_tag; - - - /* Register layout for all registers TCDWORD20_... */ - - typedef union { /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - uint32_t R; - struct { - uint32_t CITER_E_LINK:1; /* Enable Channel to channel linking on minor loop complete */ - uint32_t CITER_LINKCH:6; /* Link Channel Number */ - uint32_t CITER:9; /* Current Major Iteration Count */ - uint32_t DOFF:16; /* Destination Address Signed Offset */ - } B; - } SPP_DMA2_TCDWORD20__32B_tag; - - - /* Register layout for all registers TCDWORD24_... */ - - typedef union { /* SPP_DMA2_TCDn Word6 - dlast_sga */ - uint32_t R; - struct { - uint32_t DLAST_SGA:32; /* Last destination address adjustment */ - } B; - } SPP_DMA2_TCDWORD24__32B_tag; - - - /* Register layout for all registers TCDWORD28_... */ - - typedef union { /* SPP_DMA2_TCDn Word7 - biter, etc. */ - uint32_t R; - struct { - -#ifndef USE_FIELD_ALIASES_SPP_DMA2 - uint32_t BITER_E_LINK:1; /* beginning ("major") iteration count */ -#else - uint32_t BITERE_LINK:1; /* deprecated name - please avoid */ -#endif - uint32_t BITER:15; /* Enable Channel to Channel linking on minor loop complete */ - uint32_t BWC:2; /* Bandwidth Control */ - uint32_t MAJOR_LINKCH:6; /* Link Channel Number */ - uint32_t DONE:1; /* channel done */ - uint32_t ACTIVE:1; /* Channel Active */ - uint32_t MAJOR_E_LINK:1; /* Enable Channel to Channel Linking on major loop complete */ - uint32_t E_SG:1; /* Enable Scatter/Gather Processing */ - uint32_t D_REQ:1; /* Disable Request */ - uint32_t INT_HALF:1; /* Enable an Interrupt when Major Counter is half complete */ - uint32_t INT_MAJ:1; /* Enable an Interrupt when Major Iteration count completes */ - uint32_t START:1; /* Channel Start */ - } B; - } SPP_DMA2_TCDWORD28__32B_tag; - - - typedef struct SPP_DMA2_CHANNEL_struct_tag { - - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_; /* relative offset: 0x0000 */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_; /* relative offset: 0x0004 */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_; /* relative offset: 0x0008 */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_; /* relative offset: 0x000C */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_; /* relative offset: 0x0010 */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_; /* relative offset: 0x0014 */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_; /* relative offset: 0x0018 */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_; /* relative offset: 0x001C */ - - } SPP_DMA2_CHANNEL_tag; - - - typedef struct SPP_DMA2_struct_tag { /* start of SPP_DMA2_tag */ - /* SPP_DMA2_DMACR - DMA Control Register */ - SPP_DMA2_DMACR_32B_tag DMACR; /* offset: 0x0000 size: 32 bit */ - /* SPP_DMA2_DMAES - DMA Error Status Register */ - SPP_DMA2_DMAES_32B_tag DMAES; /* offset: 0x0004 size: 32 bit */ - /* SPP_DMA2_DMAERQH - DMA Enable Request Register */ - SPP_DMA2_DMAERQH_32B_tag DMAERQH; /* offset: 0x0008 size: 32 bit */ - /* SPP_DMA2_DMAERQL - DMA Enable Request Register */ - SPP_DMA2_DMAERQL_32B_tag DMAERQL; /* offset: 0x000C size: 32 bit */ - /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */ - SPP_DMA2_DMAEEIH_32B_tag DMAEEIH; /* offset: 0x0010 size: 32 bit */ - /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */ - SPP_DMA2_DMAEEIL_32B_tag DMAEEIL; /* offset: 0x0014 size: 32 bit */ - /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */ - SPP_DMA2_DMASERQ_8B_tag DMASERQ; /* offset: 0x0018 size: 8 bit */ - /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */ - SPP_DMA2_DMACERQ_8B_tag DMACERQ; /* offset: 0x0019 size: 8 bit */ - /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */ - SPP_DMA2_DMASEEI_8B_tag DMASEEI; /* offset: 0x001A size: 8 bit */ - /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */ - SPP_DMA2_DMACEEI_8B_tag DMACEEI; /* offset: 0x001B size: 8 bit */ - /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */ - SPP_DMA2_DMACINT_8B_tag DMACINT; /* offset: 0x001C size: 8 bit */ - /* SPP_DMA2_DMACERR - DMA Clear Error */ - SPP_DMA2_DMACERR_8B_tag DMACERR; /* offset: 0x001D size: 8 bit */ - /* SPP_DMA2_DMASSRT - DMA Set START Bit */ - SPP_DMA2_DMASSRT_8B_tag DMASSRT; /* offset: 0x001E size: 8 bit */ - /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */ - SPP_DMA2_DMACDNE_8B_tag DMACDNE; /* offset: 0x001F size: 8 bit */ - /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */ - SPP_DMA2_DMAINTH_32B_tag DMAINTH; /* offset: 0x0020 size: 32 bit */ - /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */ - SPP_DMA2_DMAINTL_32B_tag DMAINTL; /* offset: 0x0024 size: 32 bit */ - /* SPP_DMA2_DMAERRH - DMA Error Register */ - SPP_DMA2_DMAERRH_32B_tag DMAERRH; /* offset: 0x0028 size: 32 bit */ - /* SPP_DMA2_DMAERRL - DMA Error Register */ - SPP_DMA2_DMAERRL_32B_tag DMAERRL; /* offset: 0x002C size: 32 bit */ - /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */ - SPP_DMA2_DMAHRSH_32B_tag DMAHRSH; /* offset: 0x0030 size: 32 bit */ - /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */ - SPP_DMA2_DMAHRSL_32B_tag DMAHRSL; /* offset: 0x0034 size: 32 bit */ - /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */ - SPP_DMA2_DMAGPOR_32B_tag DMAGPOR; /* offset: 0x0038 size: 32 bit */ - int8_t SPP_DMA2_reserved_003C_C[196]; - union { - /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI[64]; /* offset: 0x0100 (0x0001 x 64) */ - - struct { - /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI0; /* offset: 0x0100 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI1; /* offset: 0x0101 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI2; /* offset: 0x0102 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI3; /* offset: 0x0103 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI4; /* offset: 0x0104 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI5; /* offset: 0x0105 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI6; /* offset: 0x0106 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI7; /* offset: 0x0107 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI8; /* offset: 0x0108 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI9; /* offset: 0x0109 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI10; /* offset: 0x010A size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI11; /* offset: 0x010B size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI12; /* offset: 0x010C size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI13; /* offset: 0x010D size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI14; /* offset: 0x010E size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI15; /* offset: 0x010F size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI16; /* offset: 0x0110 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI17; /* offset: 0x0111 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI18; /* offset: 0x0112 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI19; /* offset: 0x0113 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI20; /* offset: 0x0114 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI21; /* offset: 0x0115 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI22; /* offset: 0x0116 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI23; /* offset: 0x0117 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI24; /* offset: 0x0118 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI25; /* offset: 0x0119 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI26; /* offset: 0x011A size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI27; /* offset: 0x011B size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI28; /* offset: 0x011C size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI29; /* offset: 0x011D size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI30; /* offset: 0x011E size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI31; /* offset: 0x011F size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI32; /* offset: 0x0120 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI33; /* offset: 0x0121 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI34; /* offset: 0x0122 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI35; /* offset: 0x0123 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI36; /* offset: 0x0124 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI37; /* offset: 0x0125 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI38; /* offset: 0x0126 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI39; /* offset: 0x0127 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI40; /* offset: 0x0128 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI41; /* offset: 0x0129 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI42; /* offset: 0x012A size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI43; /* offset: 0x012B size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI44; /* offset: 0x012C size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI45; /* offset: 0x012D size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI46; /* offset: 0x012E size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI47; /* offset: 0x012F size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI48; /* offset: 0x0130 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI49; /* offset: 0x0131 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI50; /* offset: 0x0132 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI51; /* offset: 0x0133 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI52; /* offset: 0x0134 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI53; /* offset: 0x0135 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI54; /* offset: 0x0136 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI55; /* offset: 0x0137 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI56; /* offset: 0x0138 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI57; /* offset: 0x0139 size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI58; /* offset: 0x013A size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI59; /* offset: 0x013B size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI60; /* offset: 0x013C size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI61; /* offset: 0x013D size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI62; /* offset: 0x013E size: 8 bit */ - SPP_DMA2_DCHPRI_8B_tag DCHPRI63; /* offset: 0x013F size: 8 bit */ - }; - - }; - int8_t SPP_DMA2_reserved_0140_C[3776]; - union { - /* Register set CHANNEL */ - SPP_DMA2_CHANNEL_tag CHANNEL[64]; /* offset: 0x1000 (0x0020 x 64) */ - - struct { - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_0; /* offset: 0x1000 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_0; /* offset: 0x1004 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_0; /* offset: 0x1008 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_0; /* offset: 0x100C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_0; /* offset: 0x1010 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_0; /* offset: 0x1014 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_0; /* offset: 0x1018 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_0; /* offset: 0x101C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_1; /* offset: 0x1020 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_1; /* offset: 0x1024 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_1; /* offset: 0x1028 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_1; /* offset: 0x102C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_1; /* offset: 0x1030 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_1; /* offset: 0x1034 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_1; /* offset: 0x1038 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_1; /* offset: 0x103C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_2; /* offset: 0x1040 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_2; /* offset: 0x1044 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_2; /* offset: 0x1048 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_2; /* offset: 0x104C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_2; /* offset: 0x1050 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_2; /* offset: 0x1054 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_2; /* offset: 0x1058 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_2; /* offset: 0x105C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_3; /* offset: 0x1060 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_3; /* offset: 0x1064 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_3; /* offset: 0x1068 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_3; /* offset: 0x106C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_3; /* offset: 0x1070 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_3; /* offset: 0x1074 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_3; /* offset: 0x1078 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_3; /* offset: 0x107C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_4; /* offset: 0x1080 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_4; /* offset: 0x1084 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_4; /* offset: 0x1088 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_4; /* offset: 0x108C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_4; /* offset: 0x1090 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_4; /* offset: 0x1094 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_4; /* offset: 0x1098 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_4; /* offset: 0x109C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_5; /* offset: 0x10A0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_5; /* offset: 0x10A4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_5; /* offset: 0x10A8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_5; /* offset: 0x10AC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_5; /* offset: 0x10B0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_5; /* offset: 0x10B4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_5; /* offset: 0x10B8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_5; /* offset: 0x10BC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_6; /* offset: 0x10C0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_6; /* offset: 0x10C4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_6; /* offset: 0x10C8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_6; /* offset: 0x10CC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_6; /* offset: 0x10D0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_6; /* offset: 0x10D4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_6; /* offset: 0x10D8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_6; /* offset: 0x10DC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_7; /* offset: 0x10E0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_7; /* offset: 0x10E4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_7; /* offset: 0x10E8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_7; /* offset: 0x10EC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_7; /* offset: 0x10F0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_7; /* offset: 0x10F4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_7; /* offset: 0x10F8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_7; /* offset: 0x10FC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_8; /* offset: 0x1100 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_8; /* offset: 0x1104 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_8; /* offset: 0x1108 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_8; /* offset: 0x110C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_8; /* offset: 0x1110 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_8; /* offset: 0x1114 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_8; /* offset: 0x1118 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_8; /* offset: 0x111C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_9; /* offset: 0x1120 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_9; /* offset: 0x1124 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_9; /* offset: 0x1128 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_9; /* offset: 0x112C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_9; /* offset: 0x1130 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_9; /* offset: 0x1134 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_9; /* offset: 0x1138 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_9; /* offset: 0x113C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_10; /* offset: 0x1140 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_10; /* offset: 0x1144 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_10; /* offset: 0x1148 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_10; /* offset: 0x114C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_10; /* offset: 0x1150 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_10; /* offset: 0x1154 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_10; /* offset: 0x1158 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_10; /* offset: 0x115C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_11; /* offset: 0x1160 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_11; /* offset: 0x1164 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_11; /* offset: 0x1168 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_11; /* offset: 0x116C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_11; /* offset: 0x1170 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_11; /* offset: 0x1174 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_11; /* offset: 0x1178 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_11; /* offset: 0x117C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_12; /* offset: 0x1180 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_12; /* offset: 0x1184 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_12; /* offset: 0x1188 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_12; /* offset: 0x118C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_12; /* offset: 0x1190 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_12; /* offset: 0x1194 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_12; /* offset: 0x1198 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_12; /* offset: 0x119C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_13; /* offset: 0x11A0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_13; /* offset: 0x11A4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_13; /* offset: 0x11A8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_13; /* offset: 0x11AC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_13; /* offset: 0x11B0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_13; /* offset: 0x11B4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_13; /* offset: 0x11B8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_13; /* offset: 0x11BC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_14; /* offset: 0x11C0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_14; /* offset: 0x11C4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_14; /* offset: 0x11C8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_14; /* offset: 0x11CC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_14; /* offset: 0x11D0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_14; /* offset: 0x11D4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_14; /* offset: 0x11D8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_14; /* offset: 0x11DC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_15; /* offset: 0x11E0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_15; /* offset: 0x11E4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_15; /* offset: 0x11E8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_15; /* offset: 0x11EC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_15; /* offset: 0x11F0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_15; /* offset: 0x11F4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_15; /* offset: 0x11F8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_15; /* offset: 0x11FC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_16; /* offset: 0x1200 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_16; /* offset: 0x1204 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_16; /* offset: 0x1208 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_16; /* offset: 0x120C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_16; /* offset: 0x1210 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_16; /* offset: 0x1214 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_16; /* offset: 0x1218 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_16; /* offset: 0x121C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_17; /* offset: 0x1220 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_17; /* offset: 0x1224 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_17; /* offset: 0x1228 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_17; /* offset: 0x122C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_17; /* offset: 0x1230 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_17; /* offset: 0x1234 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_17; /* offset: 0x1238 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_17; /* offset: 0x123C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_18; /* offset: 0x1240 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_18; /* offset: 0x1244 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_18; /* offset: 0x1248 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_18; /* offset: 0x124C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_18; /* offset: 0x1250 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_18; /* offset: 0x1254 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_18; /* offset: 0x1258 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_18; /* offset: 0x125C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_19; /* offset: 0x1260 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_19; /* offset: 0x1264 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_19; /* offset: 0x1268 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_19; /* offset: 0x126C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_19; /* offset: 0x1270 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_19; /* offset: 0x1274 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_19; /* offset: 0x1278 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_19; /* offset: 0x127C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_20; /* offset: 0x1280 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_20; /* offset: 0x1284 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_20; /* offset: 0x1288 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_20; /* offset: 0x128C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_20; /* offset: 0x1290 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_20; /* offset: 0x1294 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_20; /* offset: 0x1298 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_20; /* offset: 0x129C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_21; /* offset: 0x12A0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_21; /* offset: 0x12A4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_21; /* offset: 0x12A8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_21; /* offset: 0x12AC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_21; /* offset: 0x12B0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_21; /* offset: 0x12B4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_21; /* offset: 0x12B8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_21; /* offset: 0x12BC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_22; /* offset: 0x12C0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_22; /* offset: 0x12C4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_22; /* offset: 0x12C8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_22; /* offset: 0x12CC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_22; /* offset: 0x12D0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_22; /* offset: 0x12D4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_22; /* offset: 0x12D8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_22; /* offset: 0x12DC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_23; /* offset: 0x12E0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_23; /* offset: 0x12E4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_23; /* offset: 0x12E8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_23; /* offset: 0x12EC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_23; /* offset: 0x12F0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_23; /* offset: 0x12F4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_23; /* offset: 0x12F8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_23; /* offset: 0x12FC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_24; /* offset: 0x1300 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_24; /* offset: 0x1304 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_24; /* offset: 0x1308 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_24; /* offset: 0x130C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_24; /* offset: 0x1310 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_24; /* offset: 0x1314 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_24; /* offset: 0x1318 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_24; /* offset: 0x131C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_25; /* offset: 0x1320 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_25; /* offset: 0x1324 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_25; /* offset: 0x1328 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_25; /* offset: 0x132C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_25; /* offset: 0x1330 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_25; /* offset: 0x1334 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_25; /* offset: 0x1338 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_25; /* offset: 0x133C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_26; /* offset: 0x1340 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_26; /* offset: 0x1344 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_26; /* offset: 0x1348 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_26; /* offset: 0x134C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_26; /* offset: 0x1350 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_26; /* offset: 0x1354 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_26; /* offset: 0x1358 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_26; /* offset: 0x135C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_27; /* offset: 0x1360 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_27; /* offset: 0x1364 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_27; /* offset: 0x1368 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_27; /* offset: 0x136C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_27; /* offset: 0x1370 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_27; /* offset: 0x1374 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_27; /* offset: 0x1378 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_27; /* offset: 0x137C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_28; /* offset: 0x1380 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_28; /* offset: 0x1384 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_28; /* offset: 0x1388 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_28; /* offset: 0x138C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_28; /* offset: 0x1390 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_28; /* offset: 0x1394 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_28; /* offset: 0x1398 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_28; /* offset: 0x139C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_29; /* offset: 0x13A0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_29; /* offset: 0x13A4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_29; /* offset: 0x13A8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_29; /* offset: 0x13AC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_29; /* offset: 0x13B0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_29; /* offset: 0x13B4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_29; /* offset: 0x13B8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_29; /* offset: 0x13BC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_30; /* offset: 0x13C0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_30; /* offset: 0x13C4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_30; /* offset: 0x13C8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_30; /* offset: 0x13CC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_30; /* offset: 0x13D0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_30; /* offset: 0x13D4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_30; /* offset: 0x13D8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_30; /* offset: 0x13DC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_31; /* offset: 0x13E0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_31; /* offset: 0x13E4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_31; /* offset: 0x13E8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_31; /* offset: 0x13EC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_31; /* offset: 0x13F0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_31; /* offset: 0x13F4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_31; /* offset: 0x13F8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_31; /* offset: 0x13FC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_32; /* offset: 0x1400 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_32; /* offset: 0x1404 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_32; /* offset: 0x1408 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_32; /* offset: 0x140C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_32; /* offset: 0x1410 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_32; /* offset: 0x1414 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_32; /* offset: 0x1418 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_32; /* offset: 0x141C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_33; /* offset: 0x1420 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_33; /* offset: 0x1424 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_33; /* offset: 0x1428 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_33; /* offset: 0x142C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_33; /* offset: 0x1430 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_33; /* offset: 0x1434 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_33; /* offset: 0x1438 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_33; /* offset: 0x143C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_34; /* offset: 0x1440 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_34; /* offset: 0x1444 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_34; /* offset: 0x1448 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_34; /* offset: 0x144C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_34; /* offset: 0x1450 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_34; /* offset: 0x1454 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_34; /* offset: 0x1458 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_34; /* offset: 0x145C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_35; /* offset: 0x1460 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_35; /* offset: 0x1464 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_35; /* offset: 0x1468 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_35; /* offset: 0x146C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_35; /* offset: 0x1470 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_35; /* offset: 0x1474 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_35; /* offset: 0x1478 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_35; /* offset: 0x147C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_36; /* offset: 0x1480 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_36; /* offset: 0x1484 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_36; /* offset: 0x1488 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_36; /* offset: 0x148C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_36; /* offset: 0x1490 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_36; /* offset: 0x1494 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_36; /* offset: 0x1498 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_36; /* offset: 0x149C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_37; /* offset: 0x14A0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_37; /* offset: 0x14A4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_37; /* offset: 0x14A8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_37; /* offset: 0x14AC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_37; /* offset: 0x14B0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_37; /* offset: 0x14B4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_37; /* offset: 0x14B8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_37; /* offset: 0x14BC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_38; /* offset: 0x14C0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_38; /* offset: 0x14C4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_38; /* offset: 0x14C8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_38; /* offset: 0x14CC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_38; /* offset: 0x14D0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_38; /* offset: 0x14D4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_38; /* offset: 0x14D8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_38; /* offset: 0x14DC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_39; /* offset: 0x14E0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_39; /* offset: 0x14E4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_39; /* offset: 0x14E8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_39; /* offset: 0x14EC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_39; /* offset: 0x14F0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_39; /* offset: 0x14F4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_39; /* offset: 0x14F8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_39; /* offset: 0x14FC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_40; /* offset: 0x1500 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_40; /* offset: 0x1504 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_40; /* offset: 0x1508 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_40; /* offset: 0x150C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_40; /* offset: 0x1510 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_40; /* offset: 0x1514 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_40; /* offset: 0x1518 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_40; /* offset: 0x151C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_41; /* offset: 0x1520 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_41; /* offset: 0x1524 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_41; /* offset: 0x1528 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_41; /* offset: 0x152C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_41; /* offset: 0x1530 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_41; /* offset: 0x1534 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_41; /* offset: 0x1538 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_41; /* offset: 0x153C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_42; /* offset: 0x1540 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_42; /* offset: 0x1544 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_42; /* offset: 0x1548 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_42; /* offset: 0x154C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_42; /* offset: 0x1550 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_42; /* offset: 0x1554 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_42; /* offset: 0x1558 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_42; /* offset: 0x155C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_43; /* offset: 0x1560 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_43; /* offset: 0x1564 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_43; /* offset: 0x1568 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_43; /* offset: 0x156C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_43; /* offset: 0x1570 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_43; /* offset: 0x1574 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_43; /* offset: 0x1578 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_43; /* offset: 0x157C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_44; /* offset: 0x1580 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_44; /* offset: 0x1584 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_44; /* offset: 0x1588 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_44; /* offset: 0x158C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_44; /* offset: 0x1590 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_44; /* offset: 0x1594 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_44; /* offset: 0x1598 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_44; /* offset: 0x159C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_45; /* offset: 0x15A0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_45; /* offset: 0x15A4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_45; /* offset: 0x15A8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_45; /* offset: 0x15AC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_45; /* offset: 0x15B0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_45; /* offset: 0x15B4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_45; /* offset: 0x15B8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_45; /* offset: 0x15BC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_46; /* offset: 0x15C0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_46; /* offset: 0x15C4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_46; /* offset: 0x15C8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_46; /* offset: 0x15CC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_46; /* offset: 0x15D0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_46; /* offset: 0x15D4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_46; /* offset: 0x15D8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_46; /* offset: 0x15DC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_47; /* offset: 0x15E0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_47; /* offset: 0x15E4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_47; /* offset: 0x15E8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_47; /* offset: 0x15EC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_47; /* offset: 0x15F0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_47; /* offset: 0x15F4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_47; /* offset: 0x15F8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_47; /* offset: 0x15FC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_48; /* offset: 0x1600 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_48; /* offset: 0x1604 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_48; /* offset: 0x1608 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_48; /* offset: 0x160C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_48; /* offset: 0x1610 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_48; /* offset: 0x1614 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_48; /* offset: 0x1618 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_48; /* offset: 0x161C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_49; /* offset: 0x1620 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_49; /* offset: 0x1624 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_49; /* offset: 0x1628 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_49; /* offset: 0x162C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_49; /* offset: 0x1630 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_49; /* offset: 0x1634 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_49; /* offset: 0x1638 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_49; /* offset: 0x163C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_50; /* offset: 0x1640 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_50; /* offset: 0x1644 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_50; /* offset: 0x1648 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_50; /* offset: 0x164C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_50; /* offset: 0x1650 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_50; /* offset: 0x1654 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_50; /* offset: 0x1658 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_50; /* offset: 0x165C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_51; /* offset: 0x1660 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_51; /* offset: 0x1664 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_51; /* offset: 0x1668 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_51; /* offset: 0x166C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_51; /* offset: 0x1670 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_51; /* offset: 0x1674 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_51; /* offset: 0x1678 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_51; /* offset: 0x167C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_52; /* offset: 0x1680 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_52; /* offset: 0x1684 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_52; /* offset: 0x1688 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_52; /* offset: 0x168C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_52; /* offset: 0x1690 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_52; /* offset: 0x1694 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_52; /* offset: 0x1698 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_52; /* offset: 0x169C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_53; /* offset: 0x16A0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_53; /* offset: 0x16A4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_53; /* offset: 0x16A8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_53; /* offset: 0x16AC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_53; /* offset: 0x16B0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_53; /* offset: 0x16B4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_53; /* offset: 0x16B8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_53; /* offset: 0x16BC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_54; /* offset: 0x16C0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_54; /* offset: 0x16C4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_54; /* offset: 0x16C8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_54; /* offset: 0x16CC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_54; /* offset: 0x16D0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_54; /* offset: 0x16D4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_54; /* offset: 0x16D8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_54; /* offset: 0x16DC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_55; /* offset: 0x16E0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_55; /* offset: 0x16E4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_55; /* offset: 0x16E8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_55; /* offset: 0x16EC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_55; /* offset: 0x16F0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_55; /* offset: 0x16F4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_55; /* offset: 0x16F8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_55; /* offset: 0x16FC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_56; /* offset: 0x1700 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_56; /* offset: 0x1704 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_56; /* offset: 0x1708 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_56; /* offset: 0x170C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_56; /* offset: 0x1710 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_56; /* offset: 0x1714 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_56; /* offset: 0x1718 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_56; /* offset: 0x171C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_57; /* offset: 0x1720 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_57; /* offset: 0x1724 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_57; /* offset: 0x1728 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_57; /* offset: 0x172C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_57; /* offset: 0x1730 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_57; /* offset: 0x1734 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_57; /* offset: 0x1738 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_57; /* offset: 0x173C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_58; /* offset: 0x1740 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_58; /* offset: 0x1744 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_58; /* offset: 0x1748 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_58; /* offset: 0x174C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_58; /* offset: 0x1750 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_58; /* offset: 0x1754 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_58; /* offset: 0x1758 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_58; /* offset: 0x175C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_59; /* offset: 0x1760 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_59; /* offset: 0x1764 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_59; /* offset: 0x1768 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_59; /* offset: 0x176C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_59; /* offset: 0x1770 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_59; /* offset: 0x1774 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_59; /* offset: 0x1778 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_59; /* offset: 0x177C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_60; /* offset: 0x1780 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_60; /* offset: 0x1784 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_60; /* offset: 0x1788 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_60; /* offset: 0x178C size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_60; /* offset: 0x1790 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_60; /* offset: 0x1794 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_60; /* offset: 0x1798 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_60; /* offset: 0x179C size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_61; /* offset: 0x17A0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_61; /* offset: 0x17A4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_61; /* offset: 0x17A8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_61; /* offset: 0x17AC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_61; /* offset: 0x17B0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_61; /* offset: 0x17B4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_61; /* offset: 0x17B8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_61; /* offset: 0x17BC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_62; /* offset: 0x17C0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_62; /* offset: 0x17C4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_62; /* offset: 0x17C8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_62; /* offset: 0x17CC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_62; /* offset: 0x17D0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_62; /* offset: 0x17D4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_62; /* offset: 0x17D8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_62; /* offset: 0x17DC size: 32 bit */ - /* SPP_DMA2_TCDn Word0 - Source Address */ - SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_63; /* offset: 0x17E0 size: 32 bit */ - /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ - SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_63; /* offset: 0x17E4 size: 32 bit */ - /* SPP_DMA2_TCDn Word2 - nbytes */ - SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_63; /* offset: 0x17E8 size: 32 bit */ - /* SPP_DMA2_TCDn Word3 - slast */ - SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_63; /* offset: 0x17EC size: 32 bit */ - /* SPP_DMA2_TCDn Word4 - daddr */ - SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_63; /* offset: 0x17F0 size: 32 bit */ - /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ - SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_63; /* offset: 0x17F4 size: 32 bit */ - /* SPP_DMA2_TCDn Word6 - dlast_sga */ - SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_63; /* offset: 0x17F8 size: 32 bit */ - /* SPP_DMA2_TCDn Word7 - biter, etc. */ - SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_63; /* offset: 0x17FC size: 32 bit */ - }; - - }; - } SPP_DMA2_tag; - - -#define SPP_DMA2 (*(volatile SPP_DMA2_tag *) 0xFFF44000UL) - - - -/****************************************************************/ -/* */ -/* Module: INTC */ -/* */ -/****************************************************************/ - - typedef union { /* BCR - Block Configuration Register */ - uint32_t R; - struct { - uint32_t:18; - uint32_t VTES_PRC1:1; /* Vector Table Entry Size - Processor 1 */ - uint32_t:4; - uint32_t HVEN_PRC1:1; /* Hardware Vector Enable - Processor 1 */ - uint32_t:2; -#ifndef USE_FIELD_ALIASES_INTC - uint32_t VTES_PRC0:1; /* Vector Table Entry Size - Processor 0 */ -#else - uint32_t VTES:1; /* deprecated name - please avoid */ -#endif - uint32_t:4; -#ifndef USE_FIELD_ALIASES_INTC - uint32_t HVEN_PRC0:1; /* Hardware Vector Enable - Processor 0 */ -#else - uint32_t HVEN:1; /* deprecated name - please avoid */ -#endif - } B; - } INTC_BCR_32B_tag; - - typedef union { /* CPR - Current Priority Register - Processor 0 */ - uint32_t R; - struct { - uint32_t:28; - uint32_t PRI:4; /* Priority Bits */ - } B; - } INTC_CPR_PRC0_32B_tag; - - typedef union { /* CPR - Current Priority Register - Processor 1 */ - uint32_t R; - struct { - uint32_t:28; - uint32_t PRI:4; /* Priority Bits */ - } B; - } INTC_CPR_PRC1_32B_tag; - - typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 0 */ - uint32_t R; - struct { -#ifndef USE_FIELD_ALIASES_INTC - uint32_t VTBA_PRC0:21; /* Vector Table Base Address - Processor 0 */ -#else - uint32_t VTBA:21; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_INTC - uint32_t INTEC_PRC0:9; /* Interrupt Vector - Processor 0 */ -#else - uint32_t INTVEC:9; /* deprecated name - please avoid */ -#endif - uint32_t:2; - } B; - } INTC_IACKR_PRC0_32B_tag; - - typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 1 */ - uint32_t R; - struct { - uint32_t VTBA_PRC1:21; /* Vector Table Base Address - Processor 1 */ - uint32_t INTEC_PRC1:9; /* Interrupt Vector - Processor 1 */ - uint32_t:2; - } B; - } INTC_IACKR_PRC1_32B_tag; - - typedef union { /* EOIR- End of Interrupt Register - Processor 0 */ - uint32_t R; - } INTC_EOIR_PRC0_32B_tag; - - typedef union { /* EOIR- End of Interrupt Register - Processor 1 */ - uint32_t R; - } INTC_EOIR_PRC1_32B_tag; - - - /* Register layout for all registers SSCIR... */ - - typedef union { /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ - uint8_t R; - struct { - uint8_t:6; - uint8_t SET:1; /* Set Flag bit */ - uint8_t CLR:1; /* Clear Flag bit */ - } B; - } INTC_SSCIR_8B_tag; - - typedef union { /* SSCIR0_3 - Software Set/Clear Interrupt Registers */ - uint32_t R; - struct { - uint32_t:6; - uint32_t SET0:1; /* Set Flag 0 bit */ - uint32_t CLR0:1; /* Clear Flag 0 bit */ - uint32_t:6; - uint32_t SET1:1; /* Set Flag 1 bit */ - uint32_t CLR1:1; /* Clear Flag 1 bit */ - uint32_t:6; - uint32_t SET2:1; /* Set Flag 2 bit */ - uint32_t CLR2:1; /* Clear Flag 2 bit */ - uint32_t:6; - uint32_t SET3:1; /* Set Flag 3 bit */ - uint32_t CLR3:1; /* Clear Flag 3 bit */ - } B; - } INTC_SSCIR0_3_32B_tag; - - typedef union { /* SSCIR4_7 - Software Set/Clear Interrupt Registers */ - uint32_t R; - struct { - uint32_t:6; - uint32_t SET4:1; /* Set Flag 4 bit */ - uint32_t CLR4:1; /* Clear Flag 4 bit */ - uint32_t:6; - uint32_t SET5:1; /* Set Flag 5 bit */ - uint32_t CLR5:1; /* Clear Flag 5 bit */ - uint32_t:6; - uint32_t SET6:1; /* Set Flag 6 bit */ - uint32_t CLR6:1; /* Clear Flag 6 bit */ - uint32_t:6; - uint32_t SET7:1; /* Set Flag 7 bit */ - uint32_t CLR7:1; /* Clear Flag 7 bit */ - } B; - } INTC_SSCIR4_7_32B_tag; - - - /* Register layout for all registers PSR... */ - - typedef union { /* PSR0-511 - Priority Select Registers */ - uint8_t R; - struct { - uint8_t PRC_SEL:2; /* Processor Select */ - uint8_t:2; - uint8_t PRI:4; /* Priority Select */ - } B; - } INTC_PSR_8B_tag; - - - /* Register layout for all registers PSR... */ - - typedef union { /* PSR0_3 - 508_511 - Priority Select Registers */ - uint32_t R; - struct { - uint32_t PRC_SEL0:2; /* Processor Select - Entry 0 */ - uint32_t:2; - uint32_t PRI0:4; /* Priority Select - Entry 0 */ - uint32_t PRC_SEL1:2; /* Processor Select - Entry 1 */ - uint32_t:2; - uint32_t PRI1:4; /* Priority Select - Entry 1 */ - uint32_t PRC_SEL2:2; /* Processor Select - Entry 2 */ - uint32_t:2; - uint32_t PRI2:4; /* Priority Select - Entry 2 */ - uint32_t PRC_SEL3:2; /* Processor Select - Entry 3 */ - uint32_t:2; - uint32_t PRI3:4; /* Priority Select - Entry 3 */ - } B; - } INTC_PSR_32B_tag; - - - - typedef struct INTC_struct_tag { /* start of INTC_tag */ - union { - INTC_BCR_32B_tag MCR; /* deprecated - please avoid */ - - /* BCR - Block Configuration Register */ - INTC_BCR_32B_tag BCR; /* offset: 0x0000 size: 32 bit */ - - }; - int8_t INTC_reserved_0004_C[4]; - union { - /* CPR - Current Priority Register - Processor 0 */ - INTC_CPR_PRC0_32B_tag CPR_PRC0; /* offset: 0x0008 size: 32 bit */ - - INTC_CPR_PRC0_32B_tag CPR; /* deprecated - please avoid */ - - }; - /* CPR - Current Priority Register - Processor 1 */ - INTC_CPR_PRC1_32B_tag CPR_PRC1; /* offset: 0x000C size: 32 bit */ - union { - /* IACKR- Interrupt Acknowledge Register - Processor 0 */ - INTC_IACKR_PRC0_32B_tag IACKR_PRC0; /* offset: 0x0010 size: 32 bit */ - - INTC_IACKR_PRC0_32B_tag IACKR; /* deprecated - please avoid */ - - }; - /* IACKR- Interrupt Acknowledge Register - Processor 1 */ - INTC_IACKR_PRC1_32B_tag IACKR_PRC1; /* offset: 0x0014 size: 32 bit */ - union { - /* EOIR- End of Interrupt Register - Processor 0 */ - INTC_EOIR_PRC0_32B_tag EOIR_PRC0; /* offset: 0x0018 size: 32 bit */ - - INTC_EOIR_PRC0_32B_tag EOIR; /* deprecated - please avoid */ - - }; - /* EOIR- End of Interrupt Register - Processor 1 */ - INTC_EOIR_PRC1_32B_tag EOIR_PRC1; /* offset: 0x001C size: 32 bit */ - union { - /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ - INTC_SSCIR_8B_tag SSCIR[8]; /* offset: 0x0020 (0x0001 x 8) */ - - struct { - /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ - INTC_SSCIR_8B_tag SSCIR0; /* offset: 0x0020 size: 8 bit */ - INTC_SSCIR_8B_tag SSCIR1; /* offset: 0x0021 size: 8 bit */ - INTC_SSCIR_8B_tag SSCIR2; /* offset: 0x0022 size: 8 bit */ - INTC_SSCIR_8B_tag SSCIR3; /* offset: 0x0023 size: 8 bit */ - INTC_SSCIR_8B_tag SSCIR4; /* offset: 0x0024 size: 8 bit */ - INTC_SSCIR_8B_tag SSCIR5; /* offset: 0x0025 size: 8 bit */ - INTC_SSCIR_8B_tag SSCIR6; /* offset: 0x0026 size: 8 bit */ - INTC_SSCIR_8B_tag SSCIR7; /* offset: 0x0027 size: 8 bit */ - }; - - struct { - /* SSCIR0_3 - Software Set/Clear Interrupt Registers */ - INTC_SSCIR0_3_32B_tag SSCIR0_3; /* offset: 0x0020 size: 32 bit */ - /* SSCIR4_7 - Software Set/Clear Interrupt Registers */ - INTC_SSCIR4_7_32B_tag SSCIR4_7; /* offset: 0x0024 size: 32 bit */ - }; - - }; - int8_t INTC_reserved_0028_C[24]; - union { - /* PSR0_3 - 508_511 - Priority Select Registers */ - INTC_PSR_32B_tag PSR_32B[128]; /* offset: 0x0040 (0x0004 x 128) */ - - /* PSR0-511 - Priority Select Registers */ - INTC_PSR_8B_tag PSR[512]; /* offset: 0x0040 (0x0001 x 512) */ - - struct { - /* PSR0_3 - 508_511 - Priority Select Registers */ - INTC_PSR_32B_tag PSR0_3; /* offset: 0x0040 size: 32 bit */ - INTC_PSR_32B_tag PSR4_7; /* offset: 0x0044 size: 32 bit */ - INTC_PSR_32B_tag PSR8_11; /* offset: 0x0048 size: 32 bit */ - INTC_PSR_32B_tag PSR12_15; /* offset: 0x004C size: 32 bit */ - INTC_PSR_32B_tag PSR16_19; /* offset: 0x0050 size: 32 bit */ - INTC_PSR_32B_tag PSR20_23; /* offset: 0x0054 size: 32 bit */ - INTC_PSR_32B_tag PSR24_27; /* offset: 0x0058 size: 32 bit */ - INTC_PSR_32B_tag PSR28_31; /* offset: 0x005C size: 32 bit */ - INTC_PSR_32B_tag PSR32_35; /* offset: 0x0060 size: 32 bit */ - INTC_PSR_32B_tag PSR36_39; /* offset: 0x0064 size: 32 bit */ - INTC_PSR_32B_tag PSR40_43; /* offset: 0x0068 size: 32 bit */ - INTC_PSR_32B_tag PSR44_47; /* offset: 0x006C size: 32 bit */ - INTC_PSR_32B_tag PSR48_51; /* offset: 0x0070 size: 32 bit */ - INTC_PSR_32B_tag PSR52_55; /* offset: 0x0074 size: 32 bit */ - INTC_PSR_32B_tag PSR56_59; /* offset: 0x0078 size: 32 bit */ - INTC_PSR_32B_tag PSR60_63; /* offset: 0x007C size: 32 bit */ - INTC_PSR_32B_tag PSR64_67; /* offset: 0x0080 size: 32 bit */ - INTC_PSR_32B_tag PSR68_71; /* offset: 0x0084 size: 32 bit */ - INTC_PSR_32B_tag PSR72_75; /* offset: 0x0088 size: 32 bit */ - INTC_PSR_32B_tag PSR76_79; /* offset: 0x008C size: 32 bit */ - INTC_PSR_32B_tag PSR80_83; /* offset: 0x0090 size: 32 bit */ - INTC_PSR_32B_tag PSR84_87; /* offset: 0x0094 size: 32 bit */ - INTC_PSR_32B_tag PSR88_91; /* offset: 0x0098 size: 32 bit */ - INTC_PSR_32B_tag PSR92_95; /* offset: 0x009C size: 32 bit */ - INTC_PSR_32B_tag PSR96_99; /* offset: 0x00A0 size: 32 bit */ - INTC_PSR_32B_tag PSR100_103; /* offset: 0x00A4 size: 32 bit */ - INTC_PSR_32B_tag PSR104_107; /* offset: 0x00A8 size: 32 bit */ - INTC_PSR_32B_tag PSR108_111; /* offset: 0x00AC size: 32 bit */ - INTC_PSR_32B_tag PSR112_115; /* offset: 0x00B0 size: 32 bit */ - INTC_PSR_32B_tag PSR116_119; /* offset: 0x00B4 size: 32 bit */ - INTC_PSR_32B_tag PSR120_123; /* offset: 0x00B8 size: 32 bit */ - INTC_PSR_32B_tag PSR124_127; /* offset: 0x00BC size: 32 bit */ - INTC_PSR_32B_tag PSR128_131; /* offset: 0x00C0 size: 32 bit */ - INTC_PSR_32B_tag PSR132_135; /* offset: 0x00C4 size: 32 bit */ - INTC_PSR_32B_tag PSR136_139; /* offset: 0x00C8 size: 32 bit */ - INTC_PSR_32B_tag PSR140_143; /* offset: 0x00CC size: 32 bit */ - INTC_PSR_32B_tag PSR144_147; /* offset: 0x00D0 size: 32 bit */ - INTC_PSR_32B_tag PSR148_151; /* offset: 0x00D4 size: 32 bit */ - INTC_PSR_32B_tag PSR152_155; /* offset: 0x00D8 size: 32 bit */ - INTC_PSR_32B_tag PSR156_159; /* offset: 0x00DC size: 32 bit */ - INTC_PSR_32B_tag PSR160_163; /* offset: 0x00E0 size: 32 bit */ - INTC_PSR_32B_tag PSR164_167; /* offset: 0x00E4 size: 32 bit */ - INTC_PSR_32B_tag PSR168_171; /* offset: 0x00E8 size: 32 bit */ - INTC_PSR_32B_tag PSR172_175; /* offset: 0x00EC size: 32 bit */ - INTC_PSR_32B_tag PSR176_179; /* offset: 0x00F0 size: 32 bit */ - INTC_PSR_32B_tag PSR180_183; /* offset: 0x00F4 size: 32 bit */ - INTC_PSR_32B_tag PSR184_187; /* offset: 0x00F8 size: 32 bit */ - INTC_PSR_32B_tag PSR188_191; /* offset: 0x00FC size: 32 bit */ - INTC_PSR_32B_tag PSR192_195; /* offset: 0x0100 size: 32 bit */ - INTC_PSR_32B_tag PSR196_199; /* offset: 0x0104 size: 32 bit */ - INTC_PSR_32B_tag PSR200_203; /* offset: 0x0108 size: 32 bit */ - INTC_PSR_32B_tag PSR204_207; /* offset: 0x010C size: 32 bit */ - INTC_PSR_32B_tag PSR208_211; /* offset: 0x0110 size: 32 bit */ - INTC_PSR_32B_tag PSR212_215; /* offset: 0x0114 size: 32 bit */ - INTC_PSR_32B_tag PSR216_219; /* offset: 0x0118 size: 32 bit */ - INTC_PSR_32B_tag PSR220_223; /* offset: 0x011C size: 32 bit */ - INTC_PSR_32B_tag PSR224_227; /* offset: 0x0120 size: 32 bit */ - INTC_PSR_32B_tag PSR228_231; /* offset: 0x0124 size: 32 bit */ - INTC_PSR_32B_tag PSR232_235; /* offset: 0x0128 size: 32 bit */ - INTC_PSR_32B_tag PSR236_239; /* offset: 0x012C size: 32 bit */ - INTC_PSR_32B_tag PSR240_243; /* offset: 0x0130 size: 32 bit */ - INTC_PSR_32B_tag PSR244_247; /* offset: 0x0134 size: 32 bit */ - INTC_PSR_32B_tag PSR248_251; /* offset: 0x0138 size: 32 bit */ - INTC_PSR_32B_tag PSR252_255; /* offset: 0x013C size: 32 bit */ - INTC_PSR_32B_tag PSR256_259; /* offset: 0x0140 size: 32 bit */ - INTC_PSR_32B_tag PSR260_263; /* offset: 0x0144 size: 32 bit */ - INTC_PSR_32B_tag PSR264_267; /* offset: 0x0148 size: 32 bit */ - INTC_PSR_32B_tag PSR268_271; /* offset: 0x014C size: 32 bit */ - INTC_PSR_32B_tag PSR272_275; /* offset: 0x0150 size: 32 bit */ - INTC_PSR_32B_tag PSR276_279; /* offset: 0x0154 size: 32 bit */ - INTC_PSR_32B_tag PSR280_283; /* offset: 0x0158 size: 32 bit */ - INTC_PSR_32B_tag PSR284_287; /* offset: 0x015C size: 32 bit */ - INTC_PSR_32B_tag PSR288_291; /* offset: 0x0160 size: 32 bit */ - INTC_PSR_32B_tag PSR292_295; /* offset: 0x0164 size: 32 bit */ - INTC_PSR_32B_tag PSR296_299; /* offset: 0x0168 size: 32 bit */ - INTC_PSR_32B_tag PSR300_303; /* offset: 0x016C size: 32 bit */ - INTC_PSR_32B_tag PSR304_307; /* offset: 0x0170 size: 32 bit */ - INTC_PSR_32B_tag PSR308_311; /* offset: 0x0174 size: 32 bit */ - INTC_PSR_32B_tag PSR312_315; /* offset: 0x0178 size: 32 bit */ - INTC_PSR_32B_tag PSR316_319; /* offset: 0x017C size: 32 bit */ - INTC_PSR_32B_tag PSR320_323; /* offset: 0x0180 size: 32 bit */ - INTC_PSR_32B_tag PSR324_327; /* offset: 0x0184 size: 32 bit */ - INTC_PSR_32B_tag PSR328_331; /* offset: 0x0188 size: 32 bit */ - INTC_PSR_32B_tag PSR332_335; /* offset: 0x018C size: 32 bit */ - INTC_PSR_32B_tag PSR336_339; /* offset: 0x0190 size: 32 bit */ - INTC_PSR_32B_tag PSR340_343; /* offset: 0x0194 size: 32 bit */ - INTC_PSR_32B_tag PSR344_347; /* offset: 0x0198 size: 32 bit */ - INTC_PSR_32B_tag PSR348_351; /* offset: 0x019C size: 32 bit */ - INTC_PSR_32B_tag PSR352_355; /* offset: 0x01A0 size: 32 bit */ - INTC_PSR_32B_tag PSR356_359; /* offset: 0x01A4 size: 32 bit */ - INTC_PSR_32B_tag PSR360_363; /* offset: 0x01A8 size: 32 bit */ - INTC_PSR_32B_tag PSR364_367; /* offset: 0x01AC size: 32 bit */ - INTC_PSR_32B_tag PSR368_371; /* offset: 0x01B0 size: 32 bit */ - INTC_PSR_32B_tag PSR372_375; /* offset: 0x01B4 size: 32 bit */ - INTC_PSR_32B_tag PSR376_379; /* offset: 0x01B8 size: 32 bit */ - INTC_PSR_32B_tag PSR380_383; /* offset: 0x01BC size: 32 bit */ - INTC_PSR_32B_tag PSR384_387; /* offset: 0x01C0 size: 32 bit */ - INTC_PSR_32B_tag PSR388_391; /* offset: 0x01C4 size: 32 bit */ - INTC_PSR_32B_tag PSR392_395; /* offset: 0x01C8 size: 32 bit */ - INTC_PSR_32B_tag PSR396_399; /* offset: 0x01CC size: 32 bit */ - INTC_PSR_32B_tag PSR400_403; /* offset: 0x01D0 size: 32 bit */ - INTC_PSR_32B_tag PSR404_407; /* offset: 0x01D4 size: 32 bit */ - INTC_PSR_32B_tag PSR408_411; /* offset: 0x01D8 size: 32 bit */ - INTC_PSR_32B_tag PSR412_415; /* offset: 0x01DC size: 32 bit */ - INTC_PSR_32B_tag PSR416_419; /* offset: 0x01E0 size: 32 bit */ - INTC_PSR_32B_tag PSR420_423; /* offset: 0x01E4 size: 32 bit */ - INTC_PSR_32B_tag PSR424_427; /* offset: 0x01E8 size: 32 bit */ - INTC_PSR_32B_tag PSR428_431; /* offset: 0x01EC size: 32 bit */ - INTC_PSR_32B_tag PSR432_435; /* offset: 0x01F0 size: 32 bit */ - INTC_PSR_32B_tag PSR436_439; /* offset: 0x01F4 size: 32 bit */ - INTC_PSR_32B_tag PSR440_443; /* offset: 0x01F8 size: 32 bit */ - INTC_PSR_32B_tag PSR444_447; /* offset: 0x01FC size: 32 bit */ - INTC_PSR_32B_tag PSR448_451; /* offset: 0x0200 size: 32 bit */ - INTC_PSR_32B_tag PSR452_455; /* offset: 0x0204 size: 32 bit */ - INTC_PSR_32B_tag PSR456_459; /* offset: 0x0208 size: 32 bit */ - INTC_PSR_32B_tag PSR460_463; /* offset: 0x020C size: 32 bit */ - INTC_PSR_32B_tag PSR464_467; /* offset: 0x0210 size: 32 bit */ - INTC_PSR_32B_tag PSR468_471; /* offset: 0x0214 size: 32 bit */ - INTC_PSR_32B_tag PSR472_475; /* offset: 0x0218 size: 32 bit */ - INTC_PSR_32B_tag PSR476_479; /* offset: 0x021C size: 32 bit */ - INTC_PSR_32B_tag PSR480_483; /* offset: 0x0220 size: 32 bit */ - INTC_PSR_32B_tag PSR484_487; /* offset: 0x0224 size: 32 bit */ - INTC_PSR_32B_tag PSR488_491; /* offset: 0x0228 size: 32 bit */ - INTC_PSR_32B_tag PSR492_495; /* offset: 0x022C size: 32 bit */ - INTC_PSR_32B_tag PSR496_499; /* offset: 0x0230 size: 32 bit */ - INTC_PSR_32B_tag PSR500_503; /* offset: 0x0234 size: 32 bit */ - INTC_PSR_32B_tag PSR504_507; /* offset: 0x0238 size: 32 bit */ - INTC_PSR_32B_tag PSR508_511; /* offset: 0x023C size: 32 bit */ - }; - - struct { - /* PSR0-511 - Priority Select Registers */ - INTC_PSR_8B_tag PSR0; /* offset: 0x0040 size: 8 bit */ - INTC_PSR_8B_tag PSR1; /* offset: 0x0041 size: 8 bit */ - INTC_PSR_8B_tag PSR2; /* offset: 0x0042 size: 8 bit */ - INTC_PSR_8B_tag PSR3; /* offset: 0x0043 size: 8 bit */ - INTC_PSR_8B_tag PSR4; /* offset: 0x0044 size: 8 bit */ - INTC_PSR_8B_tag PSR5; /* offset: 0x0045 size: 8 bit */ - INTC_PSR_8B_tag PSR6; /* offset: 0x0046 size: 8 bit */ - INTC_PSR_8B_tag PSR7; /* offset: 0x0047 size: 8 bit */ - INTC_PSR_8B_tag PSR8; /* offset: 0x0048 size: 8 bit */ - INTC_PSR_8B_tag PSR9; /* offset: 0x0049 size: 8 bit */ - INTC_PSR_8B_tag PSR10; /* offset: 0x004A size: 8 bit */ - INTC_PSR_8B_tag PSR11; /* offset: 0x004B size: 8 bit */ - INTC_PSR_8B_tag PSR12; /* offset: 0x004C size: 8 bit */ - INTC_PSR_8B_tag PSR13; /* offset: 0x004D size: 8 bit */ - INTC_PSR_8B_tag PSR14; /* offset: 0x004E size: 8 bit */ - INTC_PSR_8B_tag PSR15; /* offset: 0x004F size: 8 bit */ - INTC_PSR_8B_tag PSR16; /* offset: 0x0050 size: 8 bit */ - INTC_PSR_8B_tag PSR17; /* offset: 0x0051 size: 8 bit */ - INTC_PSR_8B_tag PSR18; /* offset: 0x0052 size: 8 bit */ - INTC_PSR_8B_tag PSR19; /* offset: 0x0053 size: 8 bit */ - INTC_PSR_8B_tag PSR20; /* offset: 0x0054 size: 8 bit */ - INTC_PSR_8B_tag PSR21; /* offset: 0x0055 size: 8 bit */ - INTC_PSR_8B_tag PSR22; /* offset: 0x0056 size: 8 bit */ - INTC_PSR_8B_tag PSR23; /* offset: 0x0057 size: 8 bit */ - INTC_PSR_8B_tag PSR24; /* offset: 0x0058 size: 8 bit */ - INTC_PSR_8B_tag PSR25; /* offset: 0x0059 size: 8 bit */ - INTC_PSR_8B_tag PSR26; /* offset: 0x005A size: 8 bit */ - INTC_PSR_8B_tag PSR27; /* offset: 0x005B size: 8 bit */ - INTC_PSR_8B_tag PSR28; /* offset: 0x005C size: 8 bit */ - INTC_PSR_8B_tag PSR29; /* offset: 0x005D size: 8 bit */ - INTC_PSR_8B_tag PSR30; /* offset: 0x005E size: 8 bit */ - INTC_PSR_8B_tag PSR31; /* offset: 0x005F size: 8 bit */ - INTC_PSR_8B_tag PSR32; /* offset: 0x0060 size: 8 bit */ - INTC_PSR_8B_tag PSR33; /* offset: 0x0061 size: 8 bit */ - INTC_PSR_8B_tag PSR34; /* offset: 0x0062 size: 8 bit */ - INTC_PSR_8B_tag PSR35; /* offset: 0x0063 size: 8 bit */ - INTC_PSR_8B_tag PSR36; /* offset: 0x0064 size: 8 bit */ - INTC_PSR_8B_tag PSR37; /* offset: 0x0065 size: 8 bit */ - INTC_PSR_8B_tag PSR38; /* offset: 0x0066 size: 8 bit */ - INTC_PSR_8B_tag PSR39; /* offset: 0x0067 size: 8 bit */ - INTC_PSR_8B_tag PSR40; /* offset: 0x0068 size: 8 bit */ - INTC_PSR_8B_tag PSR41; /* offset: 0x0069 size: 8 bit */ - INTC_PSR_8B_tag PSR42; /* offset: 0x006A size: 8 bit */ - INTC_PSR_8B_tag PSR43; /* offset: 0x006B size: 8 bit */ - INTC_PSR_8B_tag PSR44; /* offset: 0x006C size: 8 bit */ - INTC_PSR_8B_tag PSR45; /* offset: 0x006D size: 8 bit */ - INTC_PSR_8B_tag PSR46; /* offset: 0x006E size: 8 bit */ - INTC_PSR_8B_tag PSR47; /* offset: 0x006F size: 8 bit */ - INTC_PSR_8B_tag PSR48; /* offset: 0x0070 size: 8 bit */ - INTC_PSR_8B_tag PSR49; /* offset: 0x0071 size: 8 bit */ - INTC_PSR_8B_tag PSR50; /* offset: 0x0072 size: 8 bit */ - INTC_PSR_8B_tag PSR51; /* offset: 0x0073 size: 8 bit */ - INTC_PSR_8B_tag PSR52; /* offset: 0x0074 size: 8 bit */ - INTC_PSR_8B_tag PSR53; /* offset: 0x0075 size: 8 bit */ - INTC_PSR_8B_tag PSR54; /* offset: 0x0076 size: 8 bit */ - INTC_PSR_8B_tag PSR55; /* offset: 0x0077 size: 8 bit */ - INTC_PSR_8B_tag PSR56; /* offset: 0x0078 size: 8 bit */ - INTC_PSR_8B_tag PSR57; /* offset: 0x0079 size: 8 bit */ - INTC_PSR_8B_tag PSR58; /* offset: 0x007A size: 8 bit */ - INTC_PSR_8B_tag PSR59; /* offset: 0x007B size: 8 bit */ - INTC_PSR_8B_tag PSR60; /* offset: 0x007C size: 8 bit */ - INTC_PSR_8B_tag PSR61; /* offset: 0x007D size: 8 bit */ - INTC_PSR_8B_tag PSR62; /* offset: 0x007E size: 8 bit */ - INTC_PSR_8B_tag PSR63; /* offset: 0x007F size: 8 bit */ - INTC_PSR_8B_tag PSR64; /* offset: 0x0080 size: 8 bit */ - INTC_PSR_8B_tag PSR65; /* offset: 0x0081 size: 8 bit */ - INTC_PSR_8B_tag PSR66; /* offset: 0x0082 size: 8 bit */ - INTC_PSR_8B_tag PSR67; /* offset: 0x0083 size: 8 bit */ - INTC_PSR_8B_tag PSR68; /* offset: 0x0084 size: 8 bit */ - INTC_PSR_8B_tag PSR69; /* offset: 0x0085 size: 8 bit */ - INTC_PSR_8B_tag PSR70; /* offset: 0x0086 size: 8 bit */ - INTC_PSR_8B_tag PSR71; /* offset: 0x0087 size: 8 bit */ - INTC_PSR_8B_tag PSR72; /* offset: 0x0088 size: 8 bit */ - INTC_PSR_8B_tag PSR73; /* offset: 0x0089 size: 8 bit */ - INTC_PSR_8B_tag PSR74; /* offset: 0x008A size: 8 bit */ - INTC_PSR_8B_tag PSR75; /* offset: 0x008B size: 8 bit */ - INTC_PSR_8B_tag PSR76; /* offset: 0x008C size: 8 bit */ - INTC_PSR_8B_tag PSR77; /* offset: 0x008D size: 8 bit */ - INTC_PSR_8B_tag PSR78; /* offset: 0x008E size: 8 bit */ - INTC_PSR_8B_tag PSR79; /* offset: 0x008F size: 8 bit */ - INTC_PSR_8B_tag PSR80; /* offset: 0x0090 size: 8 bit */ - INTC_PSR_8B_tag PSR81; /* offset: 0x0091 size: 8 bit */ - INTC_PSR_8B_tag PSR82; /* offset: 0x0092 size: 8 bit */ - INTC_PSR_8B_tag PSR83; /* offset: 0x0093 size: 8 bit */ - INTC_PSR_8B_tag PSR84; /* offset: 0x0094 size: 8 bit */ - INTC_PSR_8B_tag PSR85; /* offset: 0x0095 size: 8 bit */ - INTC_PSR_8B_tag PSR86; /* offset: 0x0096 size: 8 bit */ - INTC_PSR_8B_tag PSR87; /* offset: 0x0097 size: 8 bit */ - INTC_PSR_8B_tag PSR88; /* offset: 0x0098 size: 8 bit */ - INTC_PSR_8B_tag PSR89; /* offset: 0x0099 size: 8 bit */ - INTC_PSR_8B_tag PSR90; /* offset: 0x009A size: 8 bit */ - INTC_PSR_8B_tag PSR91; /* offset: 0x009B size: 8 bit */ - INTC_PSR_8B_tag PSR92; /* offset: 0x009C size: 8 bit */ - INTC_PSR_8B_tag PSR93; /* offset: 0x009D size: 8 bit */ - INTC_PSR_8B_tag PSR94; /* offset: 0x009E size: 8 bit */ - INTC_PSR_8B_tag PSR95; /* offset: 0x009F size: 8 bit */ - INTC_PSR_8B_tag PSR96; /* offset: 0x00A0 size: 8 bit */ - INTC_PSR_8B_tag PSR97; /* offset: 0x00A1 size: 8 bit */ - INTC_PSR_8B_tag PSR98; /* offset: 0x00A2 size: 8 bit */ - INTC_PSR_8B_tag PSR99; /* offset: 0x00A3 size: 8 bit */ - INTC_PSR_8B_tag PSR100; /* offset: 0x00A4 size: 8 bit */ - INTC_PSR_8B_tag PSR101; /* offset: 0x00A5 size: 8 bit */ - INTC_PSR_8B_tag PSR102; /* offset: 0x00A6 size: 8 bit */ - INTC_PSR_8B_tag PSR103; /* offset: 0x00A7 size: 8 bit */ - INTC_PSR_8B_tag PSR104; /* offset: 0x00A8 size: 8 bit */ - INTC_PSR_8B_tag PSR105; /* offset: 0x00A9 size: 8 bit */ - INTC_PSR_8B_tag PSR106; /* offset: 0x00AA size: 8 bit */ - INTC_PSR_8B_tag PSR107; /* offset: 0x00AB size: 8 bit */ - INTC_PSR_8B_tag PSR108; /* offset: 0x00AC size: 8 bit */ - INTC_PSR_8B_tag PSR109; /* offset: 0x00AD size: 8 bit */ - INTC_PSR_8B_tag PSR110; /* offset: 0x00AE size: 8 bit */ - INTC_PSR_8B_tag PSR111; /* offset: 0x00AF size: 8 bit */ - INTC_PSR_8B_tag PSR112; /* offset: 0x00B0 size: 8 bit */ - INTC_PSR_8B_tag PSR113; /* offset: 0x00B1 size: 8 bit */ - INTC_PSR_8B_tag PSR114; /* offset: 0x00B2 size: 8 bit */ - INTC_PSR_8B_tag PSR115; /* offset: 0x00B3 size: 8 bit */ - INTC_PSR_8B_tag PSR116; /* offset: 0x00B4 size: 8 bit */ - INTC_PSR_8B_tag PSR117; /* offset: 0x00B5 size: 8 bit */ - INTC_PSR_8B_tag PSR118; /* offset: 0x00B6 size: 8 bit */ - INTC_PSR_8B_tag PSR119; /* offset: 0x00B7 size: 8 bit */ - INTC_PSR_8B_tag PSR120; /* offset: 0x00B8 size: 8 bit */ - INTC_PSR_8B_tag PSR121; /* offset: 0x00B9 size: 8 bit */ - INTC_PSR_8B_tag PSR122; /* offset: 0x00BA size: 8 bit */ - INTC_PSR_8B_tag PSR123; /* offset: 0x00BB size: 8 bit */ - INTC_PSR_8B_tag PSR124; /* offset: 0x00BC size: 8 bit */ - INTC_PSR_8B_tag PSR125; /* offset: 0x00BD size: 8 bit */ - INTC_PSR_8B_tag PSR126; /* offset: 0x00BE size: 8 bit */ - INTC_PSR_8B_tag PSR127; /* offset: 0x00BF size: 8 bit */ - INTC_PSR_8B_tag PSR128; /* offset: 0x00C0 size: 8 bit */ - INTC_PSR_8B_tag PSR129; /* offset: 0x00C1 size: 8 bit */ - INTC_PSR_8B_tag PSR130; /* offset: 0x00C2 size: 8 bit */ - INTC_PSR_8B_tag PSR131; /* offset: 0x00C3 size: 8 bit */ - INTC_PSR_8B_tag PSR132; /* offset: 0x00C4 size: 8 bit */ - INTC_PSR_8B_tag PSR133; /* offset: 0x00C5 size: 8 bit */ - INTC_PSR_8B_tag PSR134; /* offset: 0x00C6 size: 8 bit */ - INTC_PSR_8B_tag PSR135; /* offset: 0x00C7 size: 8 bit */ - INTC_PSR_8B_tag PSR136; /* offset: 0x00C8 size: 8 bit */ - INTC_PSR_8B_tag PSR137; /* offset: 0x00C9 size: 8 bit */ - INTC_PSR_8B_tag PSR138; /* offset: 0x00CA size: 8 bit */ - INTC_PSR_8B_tag PSR139; /* offset: 0x00CB size: 8 bit */ - INTC_PSR_8B_tag PSR140; /* offset: 0x00CC size: 8 bit */ - INTC_PSR_8B_tag PSR141; /* offset: 0x00CD size: 8 bit */ - INTC_PSR_8B_tag PSR142; /* offset: 0x00CE size: 8 bit */ - INTC_PSR_8B_tag PSR143; /* offset: 0x00CF size: 8 bit */ - INTC_PSR_8B_tag PSR144; /* offset: 0x00D0 size: 8 bit */ - INTC_PSR_8B_tag PSR145; /* offset: 0x00D1 size: 8 bit */ - INTC_PSR_8B_tag PSR146; /* offset: 0x00D2 size: 8 bit */ - INTC_PSR_8B_tag PSR147; /* offset: 0x00D3 size: 8 bit */ - INTC_PSR_8B_tag PSR148; /* offset: 0x00D4 size: 8 bit */ - INTC_PSR_8B_tag PSR149; /* offset: 0x00D5 size: 8 bit */ - INTC_PSR_8B_tag PSR150; /* offset: 0x00D6 size: 8 bit */ - INTC_PSR_8B_tag PSR151; /* offset: 0x00D7 size: 8 bit */ - INTC_PSR_8B_tag PSR152; /* offset: 0x00D8 size: 8 bit */ - INTC_PSR_8B_tag PSR153; /* offset: 0x00D9 size: 8 bit */ - INTC_PSR_8B_tag PSR154; /* offset: 0x00DA size: 8 bit */ - INTC_PSR_8B_tag PSR155; /* offset: 0x00DB size: 8 bit */ - INTC_PSR_8B_tag PSR156; /* offset: 0x00DC size: 8 bit */ - INTC_PSR_8B_tag PSR157; /* offset: 0x00DD size: 8 bit */ - INTC_PSR_8B_tag PSR158; /* offset: 0x00DE size: 8 bit */ - INTC_PSR_8B_tag PSR159; /* offset: 0x00DF size: 8 bit */ - INTC_PSR_8B_tag PSR160; /* offset: 0x00E0 size: 8 bit */ - INTC_PSR_8B_tag PSR161; /* offset: 0x00E1 size: 8 bit */ - INTC_PSR_8B_tag PSR162; /* offset: 0x00E2 size: 8 bit */ - INTC_PSR_8B_tag PSR163; /* offset: 0x00E3 size: 8 bit */ - INTC_PSR_8B_tag PSR164; /* offset: 0x00E4 size: 8 bit */ - INTC_PSR_8B_tag PSR165; /* offset: 0x00E5 size: 8 bit */ - INTC_PSR_8B_tag PSR166; /* offset: 0x00E6 size: 8 bit */ - INTC_PSR_8B_tag PSR167; /* offset: 0x00E7 size: 8 bit */ - INTC_PSR_8B_tag PSR168; /* offset: 0x00E8 size: 8 bit */ - INTC_PSR_8B_tag PSR169; /* offset: 0x00E9 size: 8 bit */ - INTC_PSR_8B_tag PSR170; /* offset: 0x00EA size: 8 bit */ - INTC_PSR_8B_tag PSR171; /* offset: 0x00EB size: 8 bit */ - INTC_PSR_8B_tag PSR172; /* offset: 0x00EC size: 8 bit */ - INTC_PSR_8B_tag PSR173; /* offset: 0x00ED size: 8 bit */ - INTC_PSR_8B_tag PSR174; /* offset: 0x00EE size: 8 bit */ - INTC_PSR_8B_tag PSR175; /* offset: 0x00EF size: 8 bit */ - INTC_PSR_8B_tag PSR176; /* offset: 0x00F0 size: 8 bit */ - INTC_PSR_8B_tag PSR177; /* offset: 0x00F1 size: 8 bit */ - INTC_PSR_8B_tag PSR178; /* offset: 0x00F2 size: 8 bit */ - INTC_PSR_8B_tag PSR179; /* offset: 0x00F3 size: 8 bit */ - INTC_PSR_8B_tag PSR180; /* offset: 0x00F4 size: 8 bit */ - INTC_PSR_8B_tag PSR181; /* offset: 0x00F5 size: 8 bit */ - INTC_PSR_8B_tag PSR182; /* offset: 0x00F6 size: 8 bit */ - INTC_PSR_8B_tag PSR183; /* offset: 0x00F7 size: 8 bit */ - INTC_PSR_8B_tag PSR184; /* offset: 0x00F8 size: 8 bit */ - INTC_PSR_8B_tag PSR185; /* offset: 0x00F9 size: 8 bit */ - INTC_PSR_8B_tag PSR186; /* offset: 0x00FA size: 8 bit */ - INTC_PSR_8B_tag PSR187; /* offset: 0x00FB size: 8 bit */ - INTC_PSR_8B_tag PSR188; /* offset: 0x00FC size: 8 bit */ - INTC_PSR_8B_tag PSR189; /* offset: 0x00FD size: 8 bit */ - INTC_PSR_8B_tag PSR190; /* offset: 0x00FE size: 8 bit */ - INTC_PSR_8B_tag PSR191; /* offset: 0x00FF size: 8 bit */ - INTC_PSR_8B_tag PSR192; /* offset: 0x0100 size: 8 bit */ - INTC_PSR_8B_tag PSR193; /* offset: 0x0101 size: 8 bit */ - INTC_PSR_8B_tag PSR194; /* offset: 0x0102 size: 8 bit */ - INTC_PSR_8B_tag PSR195; /* offset: 0x0103 size: 8 bit */ - INTC_PSR_8B_tag PSR196; /* offset: 0x0104 size: 8 bit */ - INTC_PSR_8B_tag PSR197; /* offset: 0x0105 size: 8 bit */ - INTC_PSR_8B_tag PSR198; /* offset: 0x0106 size: 8 bit */ - INTC_PSR_8B_tag PSR199; /* offset: 0x0107 size: 8 bit */ - INTC_PSR_8B_tag PSR200; /* offset: 0x0108 size: 8 bit */ - INTC_PSR_8B_tag PSR201; /* offset: 0x0109 size: 8 bit */ - INTC_PSR_8B_tag PSR202; /* offset: 0x010A size: 8 bit */ - INTC_PSR_8B_tag PSR203; /* offset: 0x010B size: 8 bit */ - INTC_PSR_8B_tag PSR204; /* offset: 0x010C size: 8 bit */ - INTC_PSR_8B_tag PSR205; /* offset: 0x010D size: 8 bit */ - INTC_PSR_8B_tag PSR206; /* offset: 0x010E size: 8 bit */ - INTC_PSR_8B_tag PSR207; /* offset: 0x010F size: 8 bit */ - INTC_PSR_8B_tag PSR208; /* offset: 0x0110 size: 8 bit */ - INTC_PSR_8B_tag PSR209; /* offset: 0x0111 size: 8 bit */ - INTC_PSR_8B_tag PSR210; /* offset: 0x0112 size: 8 bit */ - INTC_PSR_8B_tag PSR211; /* offset: 0x0113 size: 8 bit */ - INTC_PSR_8B_tag PSR212; /* offset: 0x0114 size: 8 bit */ - INTC_PSR_8B_tag PSR213; /* offset: 0x0115 size: 8 bit */ - INTC_PSR_8B_tag PSR214; /* offset: 0x0116 size: 8 bit */ - INTC_PSR_8B_tag PSR215; /* offset: 0x0117 size: 8 bit */ - INTC_PSR_8B_tag PSR216; /* offset: 0x0118 size: 8 bit */ - INTC_PSR_8B_tag PSR217; /* offset: 0x0119 size: 8 bit */ - INTC_PSR_8B_tag PSR218; /* offset: 0x011A size: 8 bit */ - INTC_PSR_8B_tag PSR219; /* offset: 0x011B size: 8 bit */ - INTC_PSR_8B_tag PSR220; /* offset: 0x011C size: 8 bit */ - INTC_PSR_8B_tag PSR221; /* offset: 0x011D size: 8 bit */ - INTC_PSR_8B_tag PSR222; /* offset: 0x011E size: 8 bit */ - INTC_PSR_8B_tag PSR223; /* offset: 0x011F size: 8 bit */ - INTC_PSR_8B_tag PSR224; /* offset: 0x0120 size: 8 bit */ - INTC_PSR_8B_tag PSR225; /* offset: 0x0121 size: 8 bit */ - INTC_PSR_8B_tag PSR226; /* offset: 0x0122 size: 8 bit */ - INTC_PSR_8B_tag PSR227; /* offset: 0x0123 size: 8 bit */ - INTC_PSR_8B_tag PSR228; /* offset: 0x0124 size: 8 bit */ - INTC_PSR_8B_tag PSR229; /* offset: 0x0125 size: 8 bit */ - INTC_PSR_8B_tag PSR230; /* offset: 0x0126 size: 8 bit */ - INTC_PSR_8B_tag PSR231; /* offset: 0x0127 size: 8 bit */ - INTC_PSR_8B_tag PSR232; /* offset: 0x0128 size: 8 bit */ - INTC_PSR_8B_tag PSR233; /* offset: 0x0129 size: 8 bit */ - INTC_PSR_8B_tag PSR234; /* offset: 0x012A size: 8 bit */ - INTC_PSR_8B_tag PSR235; /* offset: 0x012B size: 8 bit */ - INTC_PSR_8B_tag PSR236; /* offset: 0x012C size: 8 bit */ - INTC_PSR_8B_tag PSR237; /* offset: 0x012D size: 8 bit */ - INTC_PSR_8B_tag PSR238; /* offset: 0x012E size: 8 bit */ - INTC_PSR_8B_tag PSR239; /* offset: 0x012F size: 8 bit */ - INTC_PSR_8B_tag PSR240; /* offset: 0x0130 size: 8 bit */ - INTC_PSR_8B_tag PSR241; /* offset: 0x0131 size: 8 bit */ - INTC_PSR_8B_tag PSR242; /* offset: 0x0132 size: 8 bit */ - INTC_PSR_8B_tag PSR243; /* offset: 0x0133 size: 8 bit */ - INTC_PSR_8B_tag PSR244; /* offset: 0x0134 size: 8 bit */ - INTC_PSR_8B_tag PSR245; /* offset: 0x0135 size: 8 bit */ - INTC_PSR_8B_tag PSR246; /* offset: 0x0136 size: 8 bit */ - INTC_PSR_8B_tag PSR247; /* offset: 0x0137 size: 8 bit */ - INTC_PSR_8B_tag PSR248; /* offset: 0x0138 size: 8 bit */ - INTC_PSR_8B_tag PSR249; /* offset: 0x0139 size: 8 bit */ - INTC_PSR_8B_tag PSR250; /* offset: 0x013A size: 8 bit */ - INTC_PSR_8B_tag PSR251; /* offset: 0x013B size: 8 bit */ - INTC_PSR_8B_tag PSR252; /* offset: 0x013C size: 8 bit */ - INTC_PSR_8B_tag PSR253; /* offset: 0x013D size: 8 bit */ - INTC_PSR_8B_tag PSR254; /* offset: 0x013E size: 8 bit */ - INTC_PSR_8B_tag PSR255; /* offset: 0x013F size: 8 bit */ - INTC_PSR_8B_tag PSR256; /* offset: 0x0140 size: 8 bit */ - INTC_PSR_8B_tag PSR257; /* offset: 0x0141 size: 8 bit */ - INTC_PSR_8B_tag PSR258; /* offset: 0x0142 size: 8 bit */ - INTC_PSR_8B_tag PSR259; /* offset: 0x0143 size: 8 bit */ - INTC_PSR_8B_tag PSR260; /* offset: 0x0144 size: 8 bit */ - INTC_PSR_8B_tag PSR261; /* offset: 0x0145 size: 8 bit */ - INTC_PSR_8B_tag PSR262; /* offset: 0x0146 size: 8 bit */ - INTC_PSR_8B_tag PSR263; /* offset: 0x0147 size: 8 bit */ - INTC_PSR_8B_tag PSR264; /* offset: 0x0148 size: 8 bit */ - INTC_PSR_8B_tag PSR265; /* offset: 0x0149 size: 8 bit */ - INTC_PSR_8B_tag PSR266; /* offset: 0x014A size: 8 bit */ - INTC_PSR_8B_tag PSR267; /* offset: 0x014B size: 8 bit */ - INTC_PSR_8B_tag PSR268; /* offset: 0x014C size: 8 bit */ - INTC_PSR_8B_tag PSR269; /* offset: 0x014D size: 8 bit */ - INTC_PSR_8B_tag PSR270; /* offset: 0x014E size: 8 bit */ - INTC_PSR_8B_tag PSR271; /* offset: 0x014F size: 8 bit */ - INTC_PSR_8B_tag PSR272; /* offset: 0x0150 size: 8 bit */ - INTC_PSR_8B_tag PSR273; /* offset: 0x0151 size: 8 bit */ - INTC_PSR_8B_tag PSR274; /* offset: 0x0152 size: 8 bit */ - INTC_PSR_8B_tag PSR275; /* offset: 0x0153 size: 8 bit */ - INTC_PSR_8B_tag PSR276; /* offset: 0x0154 size: 8 bit */ - INTC_PSR_8B_tag PSR277; /* offset: 0x0155 size: 8 bit */ - INTC_PSR_8B_tag PSR278; /* offset: 0x0156 size: 8 bit */ - INTC_PSR_8B_tag PSR279; /* offset: 0x0157 size: 8 bit */ - INTC_PSR_8B_tag PSR280; /* offset: 0x0158 size: 8 bit */ - INTC_PSR_8B_tag PSR281; /* offset: 0x0159 size: 8 bit */ - INTC_PSR_8B_tag PSR282; /* offset: 0x015A size: 8 bit */ - INTC_PSR_8B_tag PSR283; /* offset: 0x015B size: 8 bit */ - INTC_PSR_8B_tag PSR284; /* offset: 0x015C size: 8 bit */ - INTC_PSR_8B_tag PSR285; /* offset: 0x015D size: 8 bit */ - INTC_PSR_8B_tag PSR286; /* offset: 0x015E size: 8 bit */ - INTC_PSR_8B_tag PSR287; /* offset: 0x015F size: 8 bit */ - INTC_PSR_8B_tag PSR288; /* offset: 0x0160 size: 8 bit */ - INTC_PSR_8B_tag PSR289; /* offset: 0x0161 size: 8 bit */ - INTC_PSR_8B_tag PSR290; /* offset: 0x0162 size: 8 bit */ - INTC_PSR_8B_tag PSR291; /* offset: 0x0163 size: 8 bit */ - INTC_PSR_8B_tag PSR292; /* offset: 0x0164 size: 8 bit */ - INTC_PSR_8B_tag PSR293; /* offset: 0x0165 size: 8 bit */ - INTC_PSR_8B_tag PSR294; /* offset: 0x0166 size: 8 bit */ - INTC_PSR_8B_tag PSR295; /* offset: 0x0167 size: 8 bit */ - INTC_PSR_8B_tag PSR296; /* offset: 0x0168 size: 8 bit */ - INTC_PSR_8B_tag PSR297; /* offset: 0x0169 size: 8 bit */ - INTC_PSR_8B_tag PSR298; /* offset: 0x016A size: 8 bit */ - INTC_PSR_8B_tag PSR299; /* offset: 0x016B size: 8 bit */ - INTC_PSR_8B_tag PSR300; /* offset: 0x016C size: 8 bit */ - INTC_PSR_8B_tag PSR301; /* offset: 0x016D size: 8 bit */ - INTC_PSR_8B_tag PSR302; /* offset: 0x016E size: 8 bit */ - INTC_PSR_8B_tag PSR303; /* offset: 0x016F size: 8 bit */ - INTC_PSR_8B_tag PSR304; /* offset: 0x0170 size: 8 bit */ - INTC_PSR_8B_tag PSR305; /* offset: 0x0171 size: 8 bit */ - INTC_PSR_8B_tag PSR306; /* offset: 0x0172 size: 8 bit */ - INTC_PSR_8B_tag PSR307; /* offset: 0x0173 size: 8 bit */ - INTC_PSR_8B_tag PSR308; /* offset: 0x0174 size: 8 bit */ - INTC_PSR_8B_tag PSR309; /* offset: 0x0175 size: 8 bit */ - INTC_PSR_8B_tag PSR310; /* offset: 0x0176 size: 8 bit */ - INTC_PSR_8B_tag PSR311; /* offset: 0x0177 size: 8 bit */ - INTC_PSR_8B_tag PSR312; /* offset: 0x0178 size: 8 bit */ - INTC_PSR_8B_tag PSR313; /* offset: 0x0179 size: 8 bit */ - INTC_PSR_8B_tag PSR314; /* offset: 0x017A size: 8 bit */ - INTC_PSR_8B_tag PSR315; /* offset: 0x017B size: 8 bit */ - INTC_PSR_8B_tag PSR316; /* offset: 0x017C size: 8 bit */ - INTC_PSR_8B_tag PSR317; /* offset: 0x017D size: 8 bit */ - INTC_PSR_8B_tag PSR318; /* offset: 0x017E size: 8 bit */ - INTC_PSR_8B_tag PSR319; /* offset: 0x017F size: 8 bit */ - INTC_PSR_8B_tag PSR320; /* offset: 0x0180 size: 8 bit */ - INTC_PSR_8B_tag PSR321; /* offset: 0x0181 size: 8 bit */ - INTC_PSR_8B_tag PSR322; /* offset: 0x0182 size: 8 bit */ - INTC_PSR_8B_tag PSR323; /* offset: 0x0183 size: 8 bit */ - INTC_PSR_8B_tag PSR324; /* offset: 0x0184 size: 8 bit */ - INTC_PSR_8B_tag PSR325; /* offset: 0x0185 size: 8 bit */ - INTC_PSR_8B_tag PSR326; /* offset: 0x0186 size: 8 bit */ - INTC_PSR_8B_tag PSR327; /* offset: 0x0187 size: 8 bit */ - INTC_PSR_8B_tag PSR328; /* offset: 0x0188 size: 8 bit */ - INTC_PSR_8B_tag PSR329; /* offset: 0x0189 size: 8 bit */ - INTC_PSR_8B_tag PSR330; /* offset: 0x018A size: 8 bit */ - INTC_PSR_8B_tag PSR331; /* offset: 0x018B size: 8 bit */ - INTC_PSR_8B_tag PSR332; /* offset: 0x018C size: 8 bit */ - INTC_PSR_8B_tag PSR333; /* offset: 0x018D size: 8 bit */ - INTC_PSR_8B_tag PSR334; /* offset: 0x018E size: 8 bit */ - INTC_PSR_8B_tag PSR335; /* offset: 0x018F size: 8 bit */ - INTC_PSR_8B_tag PSR336; /* offset: 0x0190 size: 8 bit */ - INTC_PSR_8B_tag PSR337; /* offset: 0x0191 size: 8 bit */ - INTC_PSR_8B_tag PSR338; /* offset: 0x0192 size: 8 bit */ - INTC_PSR_8B_tag PSR339; /* offset: 0x0193 size: 8 bit */ - INTC_PSR_8B_tag PSR340; /* offset: 0x0194 size: 8 bit */ - INTC_PSR_8B_tag PSR341; /* offset: 0x0195 size: 8 bit */ - INTC_PSR_8B_tag PSR342; /* offset: 0x0196 size: 8 bit */ - INTC_PSR_8B_tag PSR343; /* offset: 0x0197 size: 8 bit */ - INTC_PSR_8B_tag PSR344; /* offset: 0x0198 size: 8 bit */ - INTC_PSR_8B_tag PSR345; /* offset: 0x0199 size: 8 bit */ - INTC_PSR_8B_tag PSR346; /* offset: 0x019A size: 8 bit */ - INTC_PSR_8B_tag PSR347; /* offset: 0x019B size: 8 bit */ - INTC_PSR_8B_tag PSR348; /* offset: 0x019C size: 8 bit */ - INTC_PSR_8B_tag PSR349; /* offset: 0x019D size: 8 bit */ - INTC_PSR_8B_tag PSR350; /* offset: 0x019E size: 8 bit */ - INTC_PSR_8B_tag PSR351; /* offset: 0x019F size: 8 bit */ - INTC_PSR_8B_tag PSR352; /* offset: 0x01A0 size: 8 bit */ - INTC_PSR_8B_tag PSR353; /* offset: 0x01A1 size: 8 bit */ - INTC_PSR_8B_tag PSR354; /* offset: 0x01A2 size: 8 bit */ - INTC_PSR_8B_tag PSR355; /* offset: 0x01A3 size: 8 bit */ - INTC_PSR_8B_tag PSR356; /* offset: 0x01A4 size: 8 bit */ - INTC_PSR_8B_tag PSR357; /* offset: 0x01A5 size: 8 bit */ - INTC_PSR_8B_tag PSR358; /* offset: 0x01A6 size: 8 bit */ - INTC_PSR_8B_tag PSR359; /* offset: 0x01A7 size: 8 bit */ - INTC_PSR_8B_tag PSR360; /* offset: 0x01A8 size: 8 bit */ - INTC_PSR_8B_tag PSR361; /* offset: 0x01A9 size: 8 bit */ - INTC_PSR_8B_tag PSR362; /* offset: 0x01AA size: 8 bit */ - INTC_PSR_8B_tag PSR363; /* offset: 0x01AB size: 8 bit */ - INTC_PSR_8B_tag PSR364; /* offset: 0x01AC size: 8 bit */ - INTC_PSR_8B_tag PSR365; /* offset: 0x01AD size: 8 bit */ - INTC_PSR_8B_tag PSR366; /* offset: 0x01AE size: 8 bit */ - INTC_PSR_8B_tag PSR367; /* offset: 0x01AF size: 8 bit */ - INTC_PSR_8B_tag PSR368; /* offset: 0x01B0 size: 8 bit */ - INTC_PSR_8B_tag PSR369; /* offset: 0x01B1 size: 8 bit */ - INTC_PSR_8B_tag PSR370; /* offset: 0x01B2 size: 8 bit */ - INTC_PSR_8B_tag PSR371; /* offset: 0x01B3 size: 8 bit */ - INTC_PSR_8B_tag PSR372; /* offset: 0x01B4 size: 8 bit */ - INTC_PSR_8B_tag PSR373; /* offset: 0x01B5 size: 8 bit */ - INTC_PSR_8B_tag PSR374; /* offset: 0x01B6 size: 8 bit */ - INTC_PSR_8B_tag PSR375; /* offset: 0x01B7 size: 8 bit */ - INTC_PSR_8B_tag PSR376; /* offset: 0x01B8 size: 8 bit */ - INTC_PSR_8B_tag PSR377; /* offset: 0x01B9 size: 8 bit */ - INTC_PSR_8B_tag PSR378; /* offset: 0x01BA size: 8 bit */ - INTC_PSR_8B_tag PSR379; /* offset: 0x01BB size: 8 bit */ - INTC_PSR_8B_tag PSR380; /* offset: 0x01BC size: 8 bit */ - INTC_PSR_8B_tag PSR381; /* offset: 0x01BD size: 8 bit */ - INTC_PSR_8B_tag PSR382; /* offset: 0x01BE size: 8 bit */ - INTC_PSR_8B_tag PSR383; /* offset: 0x01BF size: 8 bit */ - INTC_PSR_8B_tag PSR384; /* offset: 0x01C0 size: 8 bit */ - INTC_PSR_8B_tag PSR385; /* offset: 0x01C1 size: 8 bit */ - INTC_PSR_8B_tag PSR386; /* offset: 0x01C2 size: 8 bit */ - INTC_PSR_8B_tag PSR387; /* offset: 0x01C3 size: 8 bit */ - INTC_PSR_8B_tag PSR388; /* offset: 0x01C4 size: 8 bit */ - INTC_PSR_8B_tag PSR389; /* offset: 0x01C5 size: 8 bit */ - INTC_PSR_8B_tag PSR390; /* offset: 0x01C6 size: 8 bit */ - INTC_PSR_8B_tag PSR391; /* offset: 0x01C7 size: 8 bit */ - INTC_PSR_8B_tag PSR392; /* offset: 0x01C8 size: 8 bit */ - INTC_PSR_8B_tag PSR393; /* offset: 0x01C9 size: 8 bit */ - INTC_PSR_8B_tag PSR394; /* offset: 0x01CA size: 8 bit */ - INTC_PSR_8B_tag PSR395; /* offset: 0x01CB size: 8 bit */ - INTC_PSR_8B_tag PSR396; /* offset: 0x01CC size: 8 bit */ - INTC_PSR_8B_tag PSR397; /* offset: 0x01CD size: 8 bit */ - INTC_PSR_8B_tag PSR398; /* offset: 0x01CE size: 8 bit */ - INTC_PSR_8B_tag PSR399; /* offset: 0x01CF size: 8 bit */ - INTC_PSR_8B_tag PSR400; /* offset: 0x01D0 size: 8 bit */ - INTC_PSR_8B_tag PSR401; /* offset: 0x01D1 size: 8 bit */ - INTC_PSR_8B_tag PSR402; /* offset: 0x01D2 size: 8 bit */ - INTC_PSR_8B_tag PSR403; /* offset: 0x01D3 size: 8 bit */ - INTC_PSR_8B_tag PSR404; /* offset: 0x01D4 size: 8 bit */ - INTC_PSR_8B_tag PSR405; /* offset: 0x01D5 size: 8 bit */ - INTC_PSR_8B_tag PSR406; /* offset: 0x01D6 size: 8 bit */ - INTC_PSR_8B_tag PSR407; /* offset: 0x01D7 size: 8 bit */ - INTC_PSR_8B_tag PSR408; /* offset: 0x01D8 size: 8 bit */ - INTC_PSR_8B_tag PSR409; /* offset: 0x01D9 size: 8 bit */ - INTC_PSR_8B_tag PSR410; /* offset: 0x01DA size: 8 bit */ - INTC_PSR_8B_tag PSR411; /* offset: 0x01DB size: 8 bit */ - INTC_PSR_8B_tag PSR412; /* offset: 0x01DC size: 8 bit */ - INTC_PSR_8B_tag PSR413; /* offset: 0x01DD size: 8 bit */ - INTC_PSR_8B_tag PSR414; /* offset: 0x01DE size: 8 bit */ - INTC_PSR_8B_tag PSR415; /* offset: 0x01DF size: 8 bit */ - INTC_PSR_8B_tag PSR416; /* offset: 0x01E0 size: 8 bit */ - INTC_PSR_8B_tag PSR417; /* offset: 0x01E1 size: 8 bit */ - INTC_PSR_8B_tag PSR418; /* offset: 0x01E2 size: 8 bit */ - INTC_PSR_8B_tag PSR419; /* offset: 0x01E3 size: 8 bit */ - INTC_PSR_8B_tag PSR420; /* offset: 0x01E4 size: 8 bit */ - INTC_PSR_8B_tag PSR421; /* offset: 0x01E5 size: 8 bit */ - INTC_PSR_8B_tag PSR422; /* offset: 0x01E6 size: 8 bit */ - INTC_PSR_8B_tag PSR423; /* offset: 0x01E7 size: 8 bit */ - INTC_PSR_8B_tag PSR424; /* offset: 0x01E8 size: 8 bit */ - INTC_PSR_8B_tag PSR425; /* offset: 0x01E9 size: 8 bit */ - INTC_PSR_8B_tag PSR426; /* offset: 0x01EA size: 8 bit */ - INTC_PSR_8B_tag PSR427; /* offset: 0x01EB size: 8 bit */ - INTC_PSR_8B_tag PSR428; /* offset: 0x01EC size: 8 bit */ - INTC_PSR_8B_tag PSR429; /* offset: 0x01ED size: 8 bit */ - INTC_PSR_8B_tag PSR430; /* offset: 0x01EE size: 8 bit */ - INTC_PSR_8B_tag PSR431; /* offset: 0x01EF size: 8 bit */ - INTC_PSR_8B_tag PSR432; /* offset: 0x01F0 size: 8 bit */ - INTC_PSR_8B_tag PSR433; /* offset: 0x01F1 size: 8 bit */ - INTC_PSR_8B_tag PSR434; /* offset: 0x01F2 size: 8 bit */ - INTC_PSR_8B_tag PSR435; /* offset: 0x01F3 size: 8 bit */ - INTC_PSR_8B_tag PSR436; /* offset: 0x01F4 size: 8 bit */ - INTC_PSR_8B_tag PSR437; /* offset: 0x01F5 size: 8 bit */ - INTC_PSR_8B_tag PSR438; /* offset: 0x01F6 size: 8 bit */ - INTC_PSR_8B_tag PSR439; /* offset: 0x01F7 size: 8 bit */ - INTC_PSR_8B_tag PSR440; /* offset: 0x01F8 size: 8 bit */ - INTC_PSR_8B_tag PSR441; /* offset: 0x01F9 size: 8 bit */ - INTC_PSR_8B_tag PSR442; /* offset: 0x01FA size: 8 bit */ - INTC_PSR_8B_tag PSR443; /* offset: 0x01FB size: 8 bit */ - INTC_PSR_8B_tag PSR444; /* offset: 0x01FC size: 8 bit */ - INTC_PSR_8B_tag PSR445; /* offset: 0x01FD size: 8 bit */ - INTC_PSR_8B_tag PSR446; /* offset: 0x01FE size: 8 bit */ - INTC_PSR_8B_tag PSR447; /* offset: 0x01FF size: 8 bit */ - INTC_PSR_8B_tag PSR448; /* offset: 0x0200 size: 8 bit */ - INTC_PSR_8B_tag PSR449; /* offset: 0x0201 size: 8 bit */ - INTC_PSR_8B_tag PSR450; /* offset: 0x0202 size: 8 bit */ - INTC_PSR_8B_tag PSR451; /* offset: 0x0203 size: 8 bit */ - INTC_PSR_8B_tag PSR452; /* offset: 0x0204 size: 8 bit */ - INTC_PSR_8B_tag PSR453; /* offset: 0x0205 size: 8 bit */ - INTC_PSR_8B_tag PSR454; /* offset: 0x0206 size: 8 bit */ - INTC_PSR_8B_tag PSR455; /* offset: 0x0207 size: 8 bit */ - INTC_PSR_8B_tag PSR456; /* offset: 0x0208 size: 8 bit */ - INTC_PSR_8B_tag PSR457; /* offset: 0x0209 size: 8 bit */ - INTC_PSR_8B_tag PSR458; /* offset: 0x020A size: 8 bit */ - INTC_PSR_8B_tag PSR459; /* offset: 0x020B size: 8 bit */ - INTC_PSR_8B_tag PSR460; /* offset: 0x020C size: 8 bit */ - INTC_PSR_8B_tag PSR461; /* offset: 0x020D size: 8 bit */ - INTC_PSR_8B_tag PSR462; /* offset: 0x020E size: 8 bit */ - INTC_PSR_8B_tag PSR463; /* offset: 0x020F size: 8 bit */ - INTC_PSR_8B_tag PSR464; /* offset: 0x0210 size: 8 bit */ - INTC_PSR_8B_tag PSR465; /* offset: 0x0211 size: 8 bit */ - INTC_PSR_8B_tag PSR466; /* offset: 0x0212 size: 8 bit */ - INTC_PSR_8B_tag PSR467; /* offset: 0x0213 size: 8 bit */ - INTC_PSR_8B_tag PSR468; /* offset: 0x0214 size: 8 bit */ - INTC_PSR_8B_tag PSR469; /* offset: 0x0215 size: 8 bit */ - INTC_PSR_8B_tag PSR470; /* offset: 0x0216 size: 8 bit */ - INTC_PSR_8B_tag PSR471; /* offset: 0x0217 size: 8 bit */ - INTC_PSR_8B_tag PSR472; /* offset: 0x0218 size: 8 bit */ - INTC_PSR_8B_tag PSR473; /* offset: 0x0219 size: 8 bit */ - INTC_PSR_8B_tag PSR474; /* offset: 0x021A size: 8 bit */ - INTC_PSR_8B_tag PSR475; /* offset: 0x021B size: 8 bit */ - INTC_PSR_8B_tag PSR476; /* offset: 0x021C size: 8 bit */ - INTC_PSR_8B_tag PSR477; /* offset: 0x021D size: 8 bit */ - INTC_PSR_8B_tag PSR478; /* offset: 0x021E size: 8 bit */ - INTC_PSR_8B_tag PSR479; /* offset: 0x021F size: 8 bit */ - INTC_PSR_8B_tag PSR480; /* offset: 0x0220 size: 8 bit */ - INTC_PSR_8B_tag PSR481; /* offset: 0x0221 size: 8 bit */ - INTC_PSR_8B_tag PSR482; /* offset: 0x0222 size: 8 bit */ - INTC_PSR_8B_tag PSR483; /* offset: 0x0223 size: 8 bit */ - INTC_PSR_8B_tag PSR484; /* offset: 0x0224 size: 8 bit */ - INTC_PSR_8B_tag PSR485; /* offset: 0x0225 size: 8 bit */ - INTC_PSR_8B_tag PSR486; /* offset: 0x0226 size: 8 bit */ - INTC_PSR_8B_tag PSR487; /* offset: 0x0227 size: 8 bit */ - INTC_PSR_8B_tag PSR488; /* offset: 0x0228 size: 8 bit */ - INTC_PSR_8B_tag PSR489; /* offset: 0x0229 size: 8 bit */ - INTC_PSR_8B_tag PSR490; /* offset: 0x022A size: 8 bit */ - INTC_PSR_8B_tag PSR491; /* offset: 0x022B size: 8 bit */ - INTC_PSR_8B_tag PSR492; /* offset: 0x022C size: 8 bit */ - INTC_PSR_8B_tag PSR493; /* offset: 0x022D size: 8 bit */ - INTC_PSR_8B_tag PSR494; /* offset: 0x022E size: 8 bit */ - INTC_PSR_8B_tag PSR495; /* offset: 0x022F size: 8 bit */ - INTC_PSR_8B_tag PSR496; /* offset: 0x0230 size: 8 bit */ - INTC_PSR_8B_tag PSR497; /* offset: 0x0231 size: 8 bit */ - INTC_PSR_8B_tag PSR498; /* offset: 0x0232 size: 8 bit */ - INTC_PSR_8B_tag PSR499; /* offset: 0x0233 size: 8 bit */ - INTC_PSR_8B_tag PSR500; /* offset: 0x0234 size: 8 bit */ - INTC_PSR_8B_tag PSR501; /* offset: 0x0235 size: 8 bit */ - INTC_PSR_8B_tag PSR502; /* offset: 0x0236 size: 8 bit */ - INTC_PSR_8B_tag PSR503; /* offset: 0x0237 size: 8 bit */ - INTC_PSR_8B_tag PSR504; /* offset: 0x0238 size: 8 bit */ - INTC_PSR_8B_tag PSR505; /* offset: 0x0239 size: 8 bit */ - INTC_PSR_8B_tag PSR506; /* offset: 0x023A size: 8 bit */ - INTC_PSR_8B_tag PSR507; /* offset: 0x023B size: 8 bit */ - INTC_PSR_8B_tag PSR508; /* offset: 0x023C size: 8 bit */ - INTC_PSR_8B_tag PSR509; /* offset: 0x023D size: 8 bit */ - INTC_PSR_8B_tag PSR510; /* offset: 0x023E size: 8 bit */ - INTC_PSR_8B_tag PSR511; /* offset: 0x023F size: 8 bit */ - }; - - }; - } INTC_tag; - - -#define INTC (*(volatile INTC_tag *) 0xFFF48000UL) - - - -/****************************************************************/ -/* */ -/* Module: DSPI */ -/* */ -/****************************************************************/ - - typedef union DSPI_MCR_tag { /* MCR - Module Configuration Register */ - uint32_t R; - struct { - uint32_t MSTR:1; /* Master/Slave mode select */ - uint32_t CONT_SCKE:1; /* Continuous SCK Enable */ - uint32_t DCONF:2; /* DSPI Configuration */ - uint32_t FRZ:1; /* Freeze */ - uint32_t MTFE:1; /* Modified Timing Format Enable */ - uint32_t PCSSE:1; /* Peripheral Chip Select Strobe Enable */ - uint32_t ROOE:1; /* Receive FIFO Overflow Overwrite Enable */ - uint32_t PCSIS7:1; /* Peripheral Chip Select 7 Inactive State */ - uint32_t PCSIS6:1; /* Peripheral Chip Select 6 Inactive State */ - uint32_t PCSIS5:1; /* Peripheral Chip Select 5 Inactive State */ - uint32_t PCSIS4:1; /* Peripheral Chip Select 4 Inactive State */ - uint32_t PCSIS3:1; /* Peripheral Chip Select 3 Inactive State */ - uint32_t PCSIS2:1; /* Peripheral Chip Select 2 Inactive State */ - uint32_t PCSIS1:1; /* Peripheral Chip Select 1 Inactive State */ - uint32_t PCSIS0:1; /* Peripheral Chip Select 0 Inactive State */ - uint32_t DOZE:1; /* Doze Enable */ - uint32_t MDIS:1; /* Module Disable */ - uint32_t DIS_TXF:1; /* Disable Transmit FIFO */ - uint32_t DIS_RXF:1; /* Disable Receive FIFO */ - uint32_t CLR_TXF:1; /* Clear TX FIFO */ - uint32_t CLR_RXF:1; /* Clear RX FIFO */ - uint32_t SMPL_PT:2; /* Sample Point */ - uint32_t:7; - uint32_t HALT:1; /* Halt */ - } B; - } DSPI_MCR_32B_tag; - - typedef union { /* TCR - Transfer Count Register */ - uint32_t R; - struct { -#ifndef USE_FIELD_ALIASES_DSPI - uint32_t SPI_TCNT:16; /* SPI Transfer Counter */ -#else - uint32_t TCNT:16; /* deprecated name - please avoid */ -#endif - uint32_t:16; - } B; - } DSPI_TCR_32B_tag; - - - /* Register layout for all registers CTAR... */ - - typedef union DSPI_CTAR_tag { /* CTAR0-7 - Clock and Transfer Attribute Registers */ - uint32_t R; - struct { - uint32_t DBR:1; /* Double Baud Rate */ - uint32_t FMSZ:4; /* Frame Size */ - uint32_t CPOL:1; /* Clock Polarity */ - uint32_t CPHA:1; /* Clock Phase */ - uint32_t LSBFE:1; /* LSB First Enable */ - uint32_t PCSSCK:2; /* PCS to SCK Delay Prescaler */ - uint32_t PASC:2; /* After SCK Delay Prescaler */ - uint32_t PDT:2; /* Delay after Transfer Prescaler */ - uint32_t PBR:2; /* Baud Rate Prescaler */ - uint32_t CSSCK:4; /* PCS to SCK Delay Scaler */ - uint32_t ASC:4; /* After SCK Delay Scaler */ - uint32_t DT:4; /* Delay after Transfer Scaler */ - uint32_t BR:4; /* Baud Rate Scaler */ - } B; - } DSPI_CTAR_32B_tag; - - typedef union DSPI_SR_tag { /* SR - Status Register */ - uint32_t R; - struct { - uint32_t TCF:1; /* Transfer Complete Flag */ - uint32_t TXRXS:1; /* TX & RX Status */ - uint32_t:1; - uint32_t EOQF:1; /* End of queue Flag */ - uint32_t TFUF:1; /* Transmit FIFO Underflow Flag */ - uint32_t:1; - uint32_t TFFF:1; /* Transmit FIFO FIll Flag */ - uint32_t:5; - uint32_t RFOF:1; /* Receive FIFO Overflow Flag */ - uint32_t:1; - uint32_t RFDF:1; /* Receive FIFO Drain Flag */ - uint32_t:1; - uint32_t TXCTR:4; /* TX FIFO Counter */ - uint32_t TXNXTPTR:4; /* Transmit Next Pointer */ - uint32_t RXCTR:4; /* RX FIFO Counter */ - uint32_t POPNXTPTR:4; /* Pop Next Pointer */ - } B; - } DSPI_SR_32B_tag; - - typedef union DSPI_RSER_tag { /* RSER - DMA/Interrupt Request Register */ - uint32_t R; - struct { -#ifndef USE_FIELD_ALIASES_DSPI - uint32_t TCF_RE:1; /* Transmission Complete Request Enable */ -#else - uint32_t TCFRE:1; /* deprecated name - please avoid */ -#endif - uint32_t:2; -#ifndef USE_FIELD_ALIASES_DSPI - uint32_t EOQF_RE:1; /* DSPI Finished Request Enable */ -#else - uint32_t EOQFRE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_DSPI - uint32_t TFUF_RE:1; /* Transmit FIFO Underflow Request Enable */ -#else - uint32_t TFUFRE:1; /* deprecated name - please avoid */ -#endif - uint32_t:1; -#ifndef USE_FIELD_ALIASES_DSPI - uint32_t TFFF_RE:1; /* Transmit FIFO Fill Request Enable */ -#else - uint32_t TFFFRE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_DSPI - uint32_t TFFF_DIRS:1; /* Transmit FIFO Fill DMA or Interrupt Request Select */ -#else - uint32_t TFFFDIRS:1; /* deprecated name - please avoid */ -#endif - uint32_t:4; -#ifndef USE_FIELD_ALIASES_DSPI - uint32_t RFOF_RE:1; /* Receive FIFO overflow Request Enable */ -#else - uint32_t RFOFRE:1; /* deprecated name - please avoid */ -#endif - uint32_t:1; -#ifndef USE_FIELD_ALIASES_DSPI - uint32_t RFDF_RE:1; /* Receive FIFO Drain Request Enable */ -#else - uint32_t RFDFRE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_DSPI - uint32_t RFDF_DIRS:1; /* Receive FIFO Drain DMA or Interrupt Request Select */ -#else - uint32_t RFDFDIRS:1; /* deprecated name - please avoid */ -#endif - uint32_t:16; - } B; - } DSPI_RSER_32B_tag; - - typedef union DSPI_PUSHR_tag { /* PUSHR - PUSH TX FIFO Register */ - uint32_t R; - struct { - uint32_t CONT:1; /* Continuous Peripheral Chip Select Enable */ - uint32_t CTAS:3; /* Clock and Transfer Attributes Select */ - uint32_t EOQ:1; /* End of Queue */ - uint32_t CTCNT:1; /* Clear SPI_TCNT */ - uint32_t:2; - uint32_t PCS7:1; /* Peripheral Chip Select 7 */ - uint32_t PCS6:1; /* Peripheral Chip Select 6 */ - uint32_t PCS5:1; /* Peripheral Chip Select 5 */ - uint32_t PCS4:1; /* Peripheral Chip Select 4 */ - uint32_t PCS3:1; /* Peripheral Chip Select 3 */ - uint32_t PCS2:1; /* Peripheral Chip Select 2 */ - uint32_t PCS1:1; /* Peripheral Chip Select 1 */ - uint32_t PCS0:1; /* Peripheral Chip Select 0 */ - uint32_t TXDATA:16; /* Transmit Data */ - } B; - } DSPI_PUSHR_32B_tag; - - typedef union DSPI_POPR_tag { /* POPR - POP RX FIFO Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t RXDATA:16; /* Receive Data */ - } B; - } DSPI_POPR_32B_tag; - - - /* Register layout for all registers TXFR... */ - - typedef union { /* Transmit FIFO Registers */ - uint32_t R; - struct { -#ifndef USE_FIELD_ALIASES_DSPI - uint32_t FIFO_TXCMD:16; /* Transmit Command */ -#else - uint32_t TXCMD:16; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_DSPI - uint32_t FIFO_TXDATA:16; /* Transmit Data */ -#else - uint32_t TXDATA:16; /* deprecated name - please avoid */ -#endif - } B; - } DSPI_TXFR_32B_tag; - - - /* Register layout for all registers RXFR... */ - - typedef union { /* Receive FIFO Registers */ - uint32_t R; - struct { - uint32_t:16; -#ifndef USE_FIELD_ALIASES_DSPI - uint32_t FIFO_RXDATA:16; /* Transmit Data */ -#else - uint32_t RXDATA:16; /* deprecated name - please avoid */ -#endif - } B; - } DSPI_RXFR_32B_tag; - - typedef union { /* DSICR - DSI Configuration Register */ - uint32_t R; - struct { - uint32_t MTOE:1; /* Multiple Transfer Operation Enable */ - uint32_t:1; - uint32_t MTOCNT:6; /* Multiple Transfer Operation Count */ - uint32_t:4; - uint32_t TXSS:1; /* Transmit Data Source Select */ - uint32_t TPOL:1; /* Trigger Polarity */ - uint32_t TRRE:1; /* Trigger Reception Enable */ - uint32_t CID:1; /* Change in Data Transfer Enable */ - uint32_t DCONT:1; /* DSI Continuous Peripheral Chip Select Enable */ - uint32_t DSICTAS:3; /* DSI CLock and Transfer Attributes Select */ - uint32_t:4; - uint32_t DPCS7:1; /* DSI Peripheral Chip Select 7 */ - uint32_t DPCS6:1; /* DSI Peripheral Chip Select 6 */ - uint32_t DPCS5:1; /* DSI Peripheral Chip Select 5 */ - uint32_t DPCS4:1; /* DSI Peripheral Chip Select 4 */ - uint32_t DPCS3:1; /* DSI Peripheral Chip Select 3 */ - uint32_t DPCS2:1; /* DSI Peripheral Chip Select 2 */ - uint32_t DPCS1:1; /* DSI Peripheral Chip Select 1 */ - uint32_t DPCS0:1; /* DSI Peripheral Chip Select 0 */ - } B; - } DSPI_DSICR_32B_tag; - - typedef union { /* SDR - DSI Serialization Data Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t SER_DATA:16; /* Serialized Data */ - } B; - } DSPI_SDR_32B_tag; - - typedef union { /* ASDR - DSI Alternate Serialization Data Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t ASER_DATA:16; /* Alternate Serialized Data */ - } B; - } DSPI_ASDR_32B_tag; - - typedef union { /* COMPR - DSI Transmit Comparison Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t COMP_DATA:16; /* Compare Data */ - } B; - } DSPI_COMPR_32B_tag; - - typedef union { /* DDR - DSI Deserialization Data Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t DESER_DATA:16; /* Deserialized Data */ - } B; - } DSPI_DDR_32B_tag; - - typedef union { /* DSICR1 - DSI Configuration Register 1 */ - uint32_t R; - } DSPI_DSICR1_32B_tag; - - - - typedef struct DSPI_tag { /* start of DSPI_tag */ - /* MCR - Module Configuration Register */ - DSPI_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ - int8_t DSPI_reserved_0004[4]; - /* TCR - Transfer Count Register */ - DSPI_TCR_32B_tag TCR; /* offset: 0x0008 size: 32 bit */ - union { - /* CTAR0-7 - Clock and Transfer Attribute Registers */ - DSPI_CTAR_32B_tag CTAR[8]; /* offset: 0x000C (0x0004 x 8) */ - - struct { - /* CTAR0-7 - Clock and Transfer Attribute Registers */ - DSPI_CTAR_32B_tag CTAR0; /* offset: 0x000C size: 32 bit */ - DSPI_CTAR_32B_tag CTAR1; /* offset: 0x0010 size: 32 bit */ - DSPI_CTAR_32B_tag CTAR2; /* offset: 0x0014 size: 32 bit */ - DSPI_CTAR_32B_tag CTAR3; /* offset: 0x0018 size: 32 bit */ - DSPI_CTAR_32B_tag CTAR4; /* offset: 0x001C size: 32 bit */ - DSPI_CTAR_32B_tag CTAR5; /* offset: 0x0020 size: 32 bit */ - DSPI_CTAR_32B_tag CTAR6; /* offset: 0x0024 size: 32 bit */ - DSPI_CTAR_32B_tag CTAR7; /* offset: 0x0028 size: 32 bit */ - }; - - }; - /* SR - Status Register */ - DSPI_SR_32B_tag SR; /* offset: 0x002C size: 32 bit */ - /* RSER - DMA/Interrupt Request Register */ - DSPI_RSER_32B_tag RSER; /* offset: 0x0030 size: 32 bit */ - /* PUSHR - PUSH TX FIFO Register */ - DSPI_PUSHR_32B_tag PUSHR; /* offset: 0x0034 size: 32 bit */ - /* POPR - POP RX FIFO Register */ - DSPI_POPR_32B_tag POPR; /* offset: 0x0038 size: 32 bit */ - union { - /* Transmit FIFO Registers */ - DSPI_TXFR_32B_tag TXFR[5]; /* offset: 0x003C (0x0004 x 5) */ - - struct { - /* Transmit FIFO Registers */ - DSPI_TXFR_32B_tag TXFR0; /* offset: 0x003C size: 32 bit */ - DSPI_TXFR_32B_tag TXFR1; /* offset: 0x0040 size: 32 bit */ - DSPI_TXFR_32B_tag TXFR2; /* offset: 0x0044 size: 32 bit */ - DSPI_TXFR_32B_tag TXFR3; /* offset: 0x0048 size: 32 bit */ - DSPI_TXFR_32B_tag TXFR4; /* offset: 0x004C size: 32 bit */ - }; - - }; - int8_t DSPI_reserved_0050_C[44]; - union { - /* Receive FIFO Registers */ - DSPI_RXFR_32B_tag RXFR[5]; /* offset: 0x007C (0x0004 x 5) */ - - struct { - /* Receive FIFO Registers */ - DSPI_RXFR_32B_tag RXFR0; /* offset: 0x007C size: 32 bit */ - DSPI_RXFR_32B_tag RXFR1; /* offset: 0x0080 size: 32 bit */ - DSPI_RXFR_32B_tag RXFR2; /* offset: 0x0084 size: 32 bit */ - DSPI_RXFR_32B_tag RXFR3; /* offset: 0x0088 size: 32 bit */ - DSPI_RXFR_32B_tag RXFR4; /* offset: 0x008C size: 32 bit */ - }; - - }; - int8_t DSPI_reserved_0090[44]; - /* DSICR - DSI Configuration Register */ - DSPI_DSICR_32B_tag DSICR; /* offset: 0x00BC size: 32 bit */ - /* SDR - DSI Serialization Data Register */ - DSPI_SDR_32B_tag SDR; /* offset: 0x00C0 size: 32 bit */ - /* ASDR - DSI Alternate Serialization Data Register */ - DSPI_ASDR_32B_tag ASDR; /* offset: 0x00C4 size: 32 bit */ - /* COMPR - DSI Transmit Comparison Register */ - DSPI_COMPR_32B_tag COMPR; /* offset: 0x00C8 size: 32 bit */ - /* DDR - DSI Deserialization Data Register */ - DSPI_DDR_32B_tag DDR; /* offset: 0x00CC size: 32 bit */ - /* DSICR1 - DSI Configuration Register 1 */ - DSPI_DSICR1_32B_tag DSICR1; /* offset: 0x00D0 size: 32 bit */ - } DSPI_tag; - - -#define DSPI_A (*(volatile DSPI_tag *) 0xFFF90000UL) -#define DSPI_B (*(volatile DSPI_tag *) 0xFFF94000UL) -#define DSPI_C (*(volatile DSPI_tag *) 0xFFF98000UL) - - - -/****************************************************************/ -/* */ -/* Module: FLEXCAN */ -/* */ -/****************************************************************/ - - typedef union { /* MCR - Module Configuration Register */ - uint32_t R; - struct { - uint32_t MDIS:1; /* Module Disable */ - uint32_t FRZ:1; /* Freeze Enable */ - uint32_t FEN:1; /* FIFO Enable */ - uint32_t HALT:1; /* Halt Flexcan */ -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t NOT_RDY:1; /* Flexcan Not Ready */ -#else - uint32_t NOTRDY:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t WAK_MSK:1; /* Wake Up Interrupt Mask */ -#else - uint32_t WAKMSK:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t SOFT_RST:1; /* Soft Reset */ -#else - uint32_t SOFTRST:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t FRZ_ACK:1; /* Freeze Mode Acknowledge */ -#else - uint32_t FRZACK:1; /* deprecated name - please avoid */ -#endif - uint32_t SUPV:1; /* Supervisor Mode */ -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t SLF_WAK:1; /* Self Wake Up */ -#else - uint32_t SLFWAK:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t WRN_EN:1; /* Warning Interrupt Enable */ -#else - uint32_t WRNEN:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t LPM_ACK:1; /* Low Power Mode Acknowledge */ -#else - uint32_t LPMACK:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t WAK_SRC:1; /* Wake Up Source */ -#else - uint32_t WAKSRC:1; /* deprecated name - please avoid */ -#endif - uint32_t DOZE:1; /* Doze Mode Enable */ -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t SRX_DIS:1; /* Self Reception Disable */ -#else - uint32_t SRXDIS:1; /* deprecated name - please avoid */ -#endif - uint32_t BCC:1; /* Backwards Compatibility Configuration */ - uint32_t:2; - uint32_t LPRIO_EN:1; /* Local Priority Enable */ - uint32_t AEN:1; /* Abort Enable */ - uint32_t:2; - uint32_t IDAM:2; /* ID Acceptance Mode */ - uint32_t:2; - uint32_t MAXMB:6; /* Maximum Number of Message Buffers */ - } B; - } FLEXCAN_MCR_32B_tag; - - typedef union { /* CTRL - Control Register */ - uint32_t R; - struct { - uint32_t PRESDIV:8; /* Prescaler Divsion Factor */ - uint32_t RJW:2; /* Resync Jump Width */ - uint32_t PSEG1:3; /* Phase Segment 1 */ - uint32_t PSEG2:3; /* Phase Segment 2 */ -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BOFF_MSK:1; /* Bus Off Mask */ -#else - uint32_t BOFFMSK:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t ERR_MSK:1; /* Error Mask */ -#else - uint32_t ERRMSK:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t CLK_SRC:1; /* CAN Engine Clock Source */ -#else - uint32_t CLKSRC:1; /* deprecated name - please avoid */ -#endif - uint32_t LPB:1; /* Loop Back */ -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t TWRN_MSK:1; /* Tx Warning Interrupt Mask */ -#else - uint32_t TWRNMSK:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t RWRN_MSK:1; /* Rx Warning Interrupt Mask */ -#else - uint32_t RWRNMSK:1; /* deprecated name - please avoid */ -#endif - uint32_t:2; - uint32_t SMP:1; /* Sampling Mode */ -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BOFF_REC:1; /* Bus Off Recovery Mode */ -#else - uint32_t BOFFREC:1; /* deprecated name - please avoid */ -#endif - uint32_t TSYN:1; /* Timer Sync Mode */ - uint32_t LBUF:1; /* Lowest Buffer Transmitted First */ - uint32_t LOM:1; /* Listen-Only Mode */ - uint32_t PROPSEG:3; /* Propagation Segment */ - } B; - } FLEXCAN_CTRL_32B_tag; - - typedef union { /* TIMER - Free Running Timer */ - uint32_t R; - } FLEXCAN_TIMER_32B_tag; - - typedef union { /* RXGMASK - Rx Global Mask Register */ - uint32_t R; -#ifndef USE_FIELD_ALIASES_FLEXCAN - struct { - uint32_t MI:32; /* deprecated field -- do not use */ - } B; -#endif - } FLEXCAN_RXGMASK_32B_tag; - - typedef union { /* RX14MASK - Rx 14 Mask Register */ - uint32_t R; -#ifndef USE_FIELD_ALIASES_FLEXCAN - struct { - uint32_t MI:32; /* deprecated field -- do not use */ - } B; -#endif - } FLEXCAN_RX14MASK_32B_tag; - - typedef union { /* RX15MASK - Rx 15 Mask Register */ - uint32_t R; -#ifndef USE_FIELD_ALIASES_FLEXCAN - struct { - uint32_t MI:32; /* deprecated field -- do not use */ - } B; -#endif - } FLEXCAN_RX15MASK_32B_tag; - - typedef union { /* ECR - Error Counter Register */ - uint32_t R; - struct { - uint32_t:16; -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t RX_ERR_COUNTER:8; /* Rx Error Counter */ -#else - uint32_t RXECNT:8; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t TX_ERR_COUNTER:8; /* Tx Error Counter */ -#else - uint32_t TXECNT:8; /* deprecated name - please avoid */ -#endif - } B; - } FLEXCAN_ECR_32B_tag; - - typedef union { /* ESR - Error and Status Register */ - uint32_t R; - struct { - uint32_t:14; -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t TWRN_INT:1; /* Tx Warning Interrupt Flag */ -#else - uint32_t TWRNINT:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t RWRN_INT:1; /* Rx Warning Interrupt Flag */ -#else - uint32_t RWRNINT:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BIT1_ERR:1; /* Bit 1 Error */ -#else - uint32_t BIT1ERR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BIT0_ERR:1; /* Bit 0 Error */ -#else - uint32_t BIT0ERR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t ACK_ERR:1; /* Acknowledge Error */ -#else - uint32_t ACKERR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t CRC_ERR:1; /* Cyclic Redundancy Check Error */ -#else - uint32_t CRCERR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t FRM_ERR:1; /* Form Error */ -#else - uint32_t FRMERR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t STF_ERR:1; /* Stuffing Error */ -#else - uint32_t STFERR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t TX_WRN:1; /* Tx Error Counter */ -#else - uint32_t TXWRN:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t RX_WRN:1; /* Rx Error Counter */ -#else - uint32_t RXWRN:1; /* deprecated name - please avoid */ -#endif - uint32_t IDLE:1; /* CAN bus Idle State */ - uint32_t TXRX:1; /* Current Flexcan Status */ -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t FLT_CONF:2; /* Fault Confinement State */ -#else - uint32_t FLTCONF:2; /* deprecated name - please avoid */ -#endif - uint32_t:1; -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BOFF_INT:1; /* Bus Off Interrupt */ -#else - uint32_t BOFFINT:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t ERR_INT:1; /* Error Interrupt */ -#else - uint32_t ERRINT:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t WAK_INT:1; /* Wake-Up Interrupt */ -#else - uint32_t WAKINT:1; /* deprecated name - please avoid */ -#endif - } B; - } FLEXCAN_ESR_32B_tag; - - typedef union { /* IMASK2 - Interrupt Masks 2 Register */ - uint32_t R; - struct { - uint32_t BUF63M:1; /* Buffer MB Mask 63 Bit */ - uint32_t BUF62M:1; /* Buffer MB Mask 62 Bit */ - uint32_t BUF61M:1; /* Buffer MB Mask 61 Bit */ - uint32_t BUF60M:1; /* Buffer MB Mask 60 Bit */ - uint32_t BUF59M:1; /* Buffer MB Mask 59 Bit */ - uint32_t BUF58M:1; /* Buffer MB Mask 58 Bit */ - uint32_t BUF57M:1; /* Buffer MB Mask 57 Bit */ - uint32_t BUF56M:1; /* Buffer MB Mask 56 Bit */ - uint32_t BUF55M:1; /* Buffer MB Mask 55 Bit */ - uint32_t BUF54M:1; /* Buffer MB Mask 54 Bit */ - uint32_t BUF53M:1; /* Buffer MB Mask 53 Bit */ - uint32_t BUF52M:1; /* Buffer MB Mask 52 Bit */ - uint32_t BUF51M:1; /* Buffer MB Mask 51 Bit */ - uint32_t BUF50M:1; /* Buffer MB Mask 50 Bit */ - uint32_t BUF49M:1; /* Buffer MB Mask 49 Bit */ - uint32_t BUF48M:1; /* Buffer MB Mask 48 Bit */ - uint32_t BUF47M:1; /* Buffer MB Mask 47 Bit */ - uint32_t BUF46M:1; /* Buffer MB Mask 46 Bit */ - uint32_t BUF45M:1; /* Buffer MB Mask 45 Bit */ - uint32_t BUF44M:1; /* Buffer MB Mask 44 Bit */ - uint32_t BUF43M:1; /* Buffer MB Mask 43 Bit */ - uint32_t BUF42M:1; /* Buffer MB Mask 42 Bit */ - uint32_t BUF41M:1; /* Buffer MB Mask 41 Bit */ - uint32_t BUF40M:1; /* Buffer MB Mask 40 Bit */ - uint32_t BUF39M:1; /* Buffer MB Mask 39 Bit */ - uint32_t BUF38M:1; /* Buffer MB Mask 38 Bit */ - uint32_t BUF37M:1; /* Buffer MB Mask 37 Bit */ - uint32_t BUF36M:1; /* Buffer MB Mask 36 Bit */ - uint32_t BUF35M:1; /* Buffer MB Mask 35 Bit */ - uint32_t BUF34M:1; /* Buffer MB Mask 34 Bit */ - uint32_t BUF33M:1; /* Buffer MB Mask 33 Bit */ - uint32_t BUF32M:1; /* Buffer MB Mask 32 Bit */ - } B; - } FLEXCAN_IMASK2_32B_tag; - - typedef union { /* IMASK1 - Interrupt Masks 1 Register */ - uint32_t R; - struct { - uint32_t BUF31M:1; /* Buffer MB Mask 31 Bit */ - uint32_t BUF30M:1; /* Buffer MB Mask 30 Bit */ - uint32_t BUF29M:1; /* Buffer MB Mask 29 Bit */ - uint32_t BUF28M:1; /* Buffer MB Mask 28 Bit */ - uint32_t BUF27M:1; /* Buffer MB Mask 27 Bit */ - uint32_t BUF26M:1; /* Buffer MB Mask 26 Bit */ - uint32_t BUF25M:1; /* Buffer MB Mask 25 Bit */ - uint32_t BUF24M:1; /* Buffer MB Mask 24 Bit */ - uint32_t BUF23M:1; /* Buffer MB Mask 23 Bit */ - uint32_t BUF22M:1; /* Buffer MB Mask 22 Bit */ - uint32_t BUF21M:1; /* Buffer MB Mask 21 Bit */ - uint32_t BUF20M:1; /* Buffer MB Mask 20 Bit */ - uint32_t BUF19M:1; /* Buffer MB Mask 19 Bit */ - uint32_t BUF18M:1; /* Buffer MB Mask 18 Bit */ - uint32_t BUF17M:1; /* Buffer MB Mask 17 Bit */ - uint32_t BUF16M:1; /* Buffer MB Mask 16 Bit */ - uint32_t BUF15M:1; /* Buffer MB Mask 15 Bit */ - uint32_t BUF14M:1; /* Buffer MB Mask 14 Bit */ - uint32_t BUF13M:1; /* Buffer MB Mask 13 Bit */ - uint32_t BUF12M:1; /* Buffer MB Mask 12 Bit */ - uint32_t BUF11M:1; /* Buffer MB Mask 11 Bit */ - uint32_t BUF10M:1; /* Buffer MB Mask 10 Bit */ -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF9M:1; /* Buffer MB Mask 9 Bit */ -#else - uint32_t BUF09M:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF8M:1; /* Buffer MB Mask 8 Bit */ -#else - uint32_t BUF08M:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF7M:1; /* Buffer MB Mask 7 Bit */ -#else - uint32_t BUF07M:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF6M:1; /* Buffer MB Mask 6 Bit */ -#else - uint32_t BUF06M:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF5M:1; /* Buffer MB Mask 5 Bit */ -#else - uint32_t BUF05M:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF4M:1; /* Buffer MB Mask 4 Bit */ -#else - uint32_t BUF04M:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF3M:1; /* Buffer MB Mask 3 Bit */ -#else - uint32_t BUF03M:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF2M:1; /* Buffer MB Mask 2 Bit */ -#else - uint32_t BUF02M:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF1M:1; /* Buffer MB Mask 1 Bit */ -#else - uint32_t BUF01M:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF0M:1; /* Buffer MB Mask 0 Bit */ -#else - uint32_t BUF00M:1; /* deprecated name - please avoid */ -#endif - } B; - } FLEXCAN_IMASK1_32B_tag; - - typedef union { /* IFLAG2 - Interrupt Flags 2 Register */ - uint32_t R; - struct { - uint32_t BUF63I:1; /* Buffer MB Interrupt 63 Bit */ - uint32_t BUF62I:1; /* Buffer MB Interrupt 62 Bit */ - uint32_t BUF61I:1; /* Buffer MB Interrupt 61 Bit */ - uint32_t BUF60I:1; /* Buffer MB Interrupt 60 Bit */ - uint32_t BUF59I:1; /* Buffer MB Interrupt 59 Bit */ - uint32_t BUF58I:1; /* Buffer MB Interrupt 58 Bit */ - uint32_t BUF57I:1; /* Buffer MB Interrupt 57 Bit */ - uint32_t BUF56I:1; /* Buffer MB Interrupt 56 Bit */ - uint32_t BUF55I:1; /* Buffer MB Interrupt 55 Bit */ - uint32_t BUF54I:1; /* Buffer MB Interrupt 54 Bit */ - uint32_t BUF53I:1; /* Buffer MB Interrupt 53 Bit */ - uint32_t BUF52I:1; /* Buffer MB Interrupt 52 Bit */ - uint32_t BUF51I:1; /* Buffer MB Interrupt 51 Bit */ - uint32_t BUF50I:1; /* Buffer MB Interrupt 50 Bit */ - uint32_t BUF49I:1; /* Buffer MB Interrupt 49 Bit */ - uint32_t BUF48I:1; /* Buffer MB Interrupt 48 Bit */ - uint32_t BUF47I:1; /* Buffer MB Interrupt 47 Bit */ - uint32_t BUF46I:1; /* Buffer MB Interrupt 46 Bit */ - uint32_t BUF45I:1; /* Buffer MB Interrupt 45 Bit */ - uint32_t BUF44I:1; /* Buffer MB Interrupt 44 Bit */ - uint32_t BUF43I:1; /* Buffer MB Interrupt 43 Bit */ - uint32_t BUF42I:1; /* Buffer MB Interrupt 42 Bit */ - uint32_t BUF41I:1; /* Buffer MB Interrupt 41 Bit */ - uint32_t BUF40I:1; /* Buffer MB Interrupt 40 Bit */ - uint32_t BUF39I:1; /* Buffer MB Interrupt 39 Bit */ - uint32_t BUF38I:1; /* Buffer MB Interrupt 38 Bit */ - uint32_t BUF37I:1; /* Buffer MB Interrupt 37 Bit */ - uint32_t BUF36I:1; /* Buffer MB Interrupt 36 Bit */ - uint32_t BUF35I:1; /* Buffer MB Interrupt 35 Bit */ - uint32_t BUF34I:1; /* Buffer MB Interrupt 34 Bit */ - uint32_t BUF33I:1; /* Buffer MB Interrupt 33 Bit */ - uint32_t BUF32I:1; /* Buffer MB Interrupt 32 Bit */ - } B; - } FLEXCAN_IFLAG2_32B_tag; - - typedef union { /* IFLAG1 - Interrupt Flags 1 Register */ - uint32_t R; - struct { - uint32_t BUF31I:1; /* Buffer MB Interrupt 31 Bit */ - uint32_t BUF30I:1; /* Buffer MB Interrupt 30 Bit */ - uint32_t BUF29I:1; /* Buffer MB Interrupt 29 Bit */ - uint32_t BUF28I:1; /* Buffer MB Interrupt 28 Bit */ - uint32_t BUF27I:1; /* Buffer MB Interrupt 27 Bit */ - uint32_t BUF26I:1; /* Buffer MB Interrupt 26 Bit */ - uint32_t BUF25I:1; /* Buffer MB Interrupt 25 Bit */ - uint32_t BUF24I:1; /* Buffer MB Interrupt 24 Bit */ - uint32_t BUF23I:1; /* Buffer MB Interrupt 23 Bit */ - uint32_t BUF22I:1; /* Buffer MB Interrupt 22 Bit */ - uint32_t BUF21I:1; /* Buffer MB Interrupt 21 Bit */ - uint32_t BUF20I:1; /* Buffer MB Interrupt 20 Bit */ - uint32_t BUF19I:1; /* Buffer MB Interrupt 19 Bit */ - uint32_t BUF18I:1; /* Buffer MB Interrupt 18 Bit */ - uint32_t BUF17I:1; /* Buffer MB Interrupt 17 Bit */ - uint32_t BUF16I:1; /* Buffer MB Interrupt 16 Bit */ - uint32_t BUF15I:1; /* Buffer MB Interrupt 15 Bit */ - uint32_t BUF14I:1; /* Buffer MB Interrupt 14 Bit */ - uint32_t BUF13I:1; /* Buffer MB Interrupt 13 Bit */ - uint32_t BUF12I:1; /* Buffer MB Interrupt 12 Bit */ - uint32_t BUF11I:1; /* Buffer MB Interrupt 11 Bit */ - uint32_t BUF10I:1; /* Buffer MB Interrupt 10 Bit */ -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF9I:1; /* Buffer MB Interrupt 9 Bit */ -#else - uint32_t BUF09I:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF8I:1; /* Buffer MB Interrupt 8 Bit */ -#else - uint32_t BUF08I:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF7I:1; /* Buffer MB Interrupt 7 Bit */ -#else - uint32_t BUF07I:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF6I:1; /* Buffer MB Interrupt 6 Bit */ -#else - uint32_t BUF06I:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF5I:1; /* Buffer MB Interrupt 5 Bit */ -#else - uint32_t BUF05I:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF4I:1; /* Buffer MB Interrupt 4 Bit */ -#else - uint32_t BUF04I:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF3I:1; /* Buffer MB Interrupt 3 Bit */ -#else - uint32_t BUF03I:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF2I:1; /* Buffer MB Interrupt 2 Bit */ -#else - uint32_t BUF02I:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF1I:1; /* Buffer MB Interrupt 1 Bit */ -#else - uint32_t BUF01I:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FLEXCAN - uint32_t BUF0I:1; /* Buffer MB Interrupt 0 Bit */ -#else - uint32_t BUF00I:1; /* deprecated name - please avoid */ -#endif - } B; - } FLEXCAN_IFLAG1_32B_tag; - - - /* Register layout for all registers MSG_CS... */ - - typedef union { /* Message Buffer Control and Status */ - uint32_t R; - struct { - uint32_t:4; - uint32_t CODE:4; /* Message Buffer Code */ - uint32_t:1; - uint32_t SRR:1; /* Substitute Remote Request */ - uint32_t IDE:1; /* ID Extended Bit */ - uint32_t RTR:1; /* Remote Transmission Request */ - uint32_t LENGTH:4; /* Length of Data in Bytes */ - uint32_t TIMESTAMP:16; /* Free-Running Counter Time Stamp */ - } B; - } FLEXCAN_MSG_CS_32B_tag; - - - /* Register layout for all registers MSG_ID... */ - - typedef union { /* Message Buffer Identifier Field */ - uint32_t R; - struct { - uint32_t PRIO:3; /* Local Priority */ - uint32_t STD_ID:11; - uint32_t EXT_ID:18; - } B; - } FLEXCAN_MSG_ID_32B_tag; - - - /* Register layout for all registers MSG_BYTE0_3... */ - - typedef union { /* Message Buffer Data Register */ - uint32_t R; - uint8_t BYTE[4]; /* individual bytes can be accessed */ - uint32_t WORD; /* individual words can be accessed */ - } FLEXCAN_MSG_DATA_32B_tag; - - typedef union { - uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ - uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ - uint32_t W[2]; /* Data buffer in words (32 bits) */ - uint32_t R[2]; /* Data buffer in words (32 bits) */ - } FLEXCAN_MSG_DATA2_32B_tag; - - /* Register layout for all registers MSG_BYTE4_7 matches xxx */ - - - /* Register layout for all registers RXIMR... */ - - typedef union { /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ - uint32_t R; - } FLEXCAN_RXIMR_32B_tag; - - - typedef struct FLEXCAN_MB_struct_tag { - - union { - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG_CS; /* relative offset: 0x0000 */ - FLEXCAN_MSG_CS_32B_tag CS; /* deprecated - please avoid */ - }; - union { - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG_ID; /* relative offset: 0x0004 */ - FLEXCAN_MSG_ID_32B_tag ID; /* deprecated - please avoid */ - }; - union { /* Message Buffer Data Register */ - - struct { - FLEXCAN_MSG_DATA_32B_tag MSG_BYTE0_3; /* relative offset: 0x0008 */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG_BYTE4_7; /* relative offset: 0x000C */ - }; - - FLEXCAN_MSG_DATA2_32B_tag DATA; /* relative offset: 0x000C */ - - }; - - } FLEXCAN_MB_tag; - - - typedef struct FLEXCAN_struct_tag { /* start of FLEXCAN_tag */ - /* MCR - Module Configuration Register */ - FLEXCAN_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ - union { - /* CTRL - Control Register */ - FLEXCAN_CTRL_32B_tag CTRL; /* offset: 0x0004 size: 32 bit */ - - FLEXCAN_CTRL_32B_tag CR; /* deprecated - please avoid */ - - }; - /* TIMER - Free Running Timer */ - FLEXCAN_TIMER_32B_tag TIMER; /* offset: 0x0008 size: 32 bit */ - int8_t FLEXCAN_reserved_000C[4]; - /* RXGMASK - Rx Global Mask Register */ - FLEXCAN_RXGMASK_32B_tag RXGMASK; /* offset: 0x0010 size: 32 bit */ - /* RX14MASK - Rx 14 Mask Register */ - FLEXCAN_RX14MASK_32B_tag RX14MASK; /* offset: 0x0014 size: 32 bit */ - /* RX15MASK - Rx 15 Mask Register */ - FLEXCAN_RX15MASK_32B_tag RX15MASK; /* offset: 0x0018 size: 32 bit */ - /* ECR - Error Counter Register */ - FLEXCAN_ECR_32B_tag ECR; /* offset: 0x001C size: 32 bit */ - /* ESR - Error and Status Register */ - FLEXCAN_ESR_32B_tag ESR; /* offset: 0x0020 size: 32 bit */ - union { - FLEXCAN_IMASK2_32B_tag IMRH; /* deprecated - please avoid */ - - /* IMASK2 - Interrupt Masks 2 Register */ - FLEXCAN_IMASK2_32B_tag IMASK2; /* offset: 0x0024 size: 32 bit */ - - }; - union { - FLEXCAN_IMASK1_32B_tag IMRL; /* deprecated - please avoid */ - - /* IMASK1 - Interrupt Masks 1 Register */ - FLEXCAN_IMASK1_32B_tag IMASK1; /* offset: 0x0028 size: 32 bit */ - - }; - union { - FLEXCAN_IFLAG2_32B_tag IFRH; /* deprecated - please avoid */ - - /* IFLAG2 - Interrupt Flags 2 Register */ - FLEXCAN_IFLAG2_32B_tag IFLAG2; /* offset: 0x002C size: 32 bit */ - - }; - union { - FLEXCAN_IFLAG1_32B_tag IFRL; /* deprecated - please avoid */ - - /* IFLAG1 - Interrupt Flags 1 Register */ - FLEXCAN_IFLAG1_32B_tag IFLAG1; /* offset: 0x0030 size: 32 bit */ - - }; - int8_t FLEXCAN_reserved_0034_C[76]; - union { - /* Register set MB */ - FLEXCAN_MB_tag MB[64]; /* offset: 0x0080 (0x0010 x 64) */ - - /* Alias name for MB */ - FLEXCAN_MB_tag BUF[64]; /* deprecated - please avoid */ - - struct { - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG0_CS; /* offset: 0x0080 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG0_ID; /* offset: 0x0084 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE0_3; /* offset: 0x0088 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE4_7; /* offset: 0x008C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG1_CS; /* offset: 0x0090 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG1_ID; /* offset: 0x0094 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE0_3; /* offset: 0x0098 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE4_7; /* offset: 0x009C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG2_CS; /* offset: 0x00A0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG2_ID; /* offset: 0x00A4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE0_3; /* offset: 0x00A8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE4_7; /* offset: 0x00AC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG3_CS; /* offset: 0x00B0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG3_ID; /* offset: 0x00B4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE0_3; /* offset: 0x00B8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE4_7; /* offset: 0x00BC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG4_CS; /* offset: 0x00C0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG4_ID; /* offset: 0x00C4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE0_3; /* offset: 0x00C8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE4_7; /* offset: 0x00CC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG5_CS; /* offset: 0x00D0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG5_ID; /* offset: 0x00D4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE0_3; /* offset: 0x00D8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE4_7; /* offset: 0x00DC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG6_CS; /* offset: 0x00E0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG6_ID; /* offset: 0x00E4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE0_3; /* offset: 0x00E8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE4_7; /* offset: 0x00EC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG7_CS; /* offset: 0x00F0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG7_ID; /* offset: 0x00F4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE0_3; /* offset: 0x00F8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE4_7; /* offset: 0x00FC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG8_CS; /* offset: 0x0100 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG8_ID; /* offset: 0x0104 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE0_3; /* offset: 0x0108 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE4_7; /* offset: 0x010C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG9_CS; /* offset: 0x0110 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG9_ID; /* offset: 0x0114 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE0_3; /* offset: 0x0118 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE4_7; /* offset: 0x011C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG10_CS; /* offset: 0x0120 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG10_ID; /* offset: 0x0124 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE0_3; /* offset: 0x0128 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE4_7; /* offset: 0x012C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG11_CS; /* offset: 0x0130 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG11_ID; /* offset: 0x0134 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE0_3; /* offset: 0x0138 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE4_7; /* offset: 0x013C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG12_CS; /* offset: 0x0140 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG12_ID; /* offset: 0x0144 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE0_3; /* offset: 0x0148 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE4_7; /* offset: 0x014C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG13_CS; /* offset: 0x0150 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG13_ID; /* offset: 0x0154 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE0_3; /* offset: 0x0158 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE4_7; /* offset: 0x015C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG14_CS; /* offset: 0x0160 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG14_ID; /* offset: 0x0164 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE0_3; /* offset: 0x0168 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE4_7; /* offset: 0x016C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG15_CS; /* offset: 0x0170 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG15_ID; /* offset: 0x0174 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE0_3; /* offset: 0x0178 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE4_7; /* offset: 0x017C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG16_CS; /* offset: 0x0180 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG16_ID; /* offset: 0x0184 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE0_3; /* offset: 0x0188 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE4_7; /* offset: 0x018C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG17_CS; /* offset: 0x0190 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG17_ID; /* offset: 0x0194 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE0_3; /* offset: 0x0198 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE4_7; /* offset: 0x019C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG18_CS; /* offset: 0x01A0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG18_ID; /* offset: 0x01A4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE0_3; /* offset: 0x01A8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE4_7; /* offset: 0x01AC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG19_CS; /* offset: 0x01B0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG19_ID; /* offset: 0x01B4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE0_3; /* offset: 0x01B8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE4_7; /* offset: 0x01BC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG20_CS; /* offset: 0x01C0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG20_ID; /* offset: 0x01C4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE0_3; /* offset: 0x01C8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE4_7; /* offset: 0x01CC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG21_CS; /* offset: 0x01D0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG21_ID; /* offset: 0x01D4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE0_3; /* offset: 0x01D8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE4_7; /* offset: 0x01DC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG22_CS; /* offset: 0x01E0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG22_ID; /* offset: 0x01E4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE0_3; /* offset: 0x01E8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE4_7; /* offset: 0x01EC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG23_CS; /* offset: 0x01F0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG23_ID; /* offset: 0x01F4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE0_3; /* offset: 0x01F8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE4_7; /* offset: 0x01FC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG24_CS; /* offset: 0x0200 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG24_ID; /* offset: 0x0204 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE0_3; /* offset: 0x0208 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE4_7; /* offset: 0x020C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG25_CS; /* offset: 0x0210 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG25_ID; /* offset: 0x0214 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE0_3; /* offset: 0x0218 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE4_7; /* offset: 0x021C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG26_CS; /* offset: 0x0220 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG26_ID; /* offset: 0x0224 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE0_3; /* offset: 0x0228 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE4_7; /* offset: 0x022C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG27_CS; /* offset: 0x0230 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG27_ID; /* offset: 0x0234 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE0_3; /* offset: 0x0238 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE4_7; /* offset: 0x023C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG28_CS; /* offset: 0x0240 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG28_ID; /* offset: 0x0244 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE0_3; /* offset: 0x0248 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE4_7; /* offset: 0x024C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG29_CS; /* offset: 0x0250 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG29_ID; /* offset: 0x0254 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE0_3; /* offset: 0x0258 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE4_7; /* offset: 0x025C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG30_CS; /* offset: 0x0260 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG30_ID; /* offset: 0x0264 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE0_3; /* offset: 0x0268 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE4_7; /* offset: 0x026C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG31_CS; /* offset: 0x0270 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG31_ID; /* offset: 0x0274 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE0_3; /* offset: 0x0278 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE4_7; /* offset: 0x027C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG32_CS; /* offset: 0x0280 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG32_ID; /* offset: 0x0284 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE0_3; /* offset: 0x0288 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE4_7; /* offset: 0x028C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG33_CS; /* offset: 0x0290 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG33_ID; /* offset: 0x0294 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE0_3; /* offset: 0x0298 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE4_7; /* offset: 0x029C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG34_CS; /* offset: 0x02A0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG34_ID; /* offset: 0x02A4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE0_3; /* offset: 0x02A8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE4_7; /* offset: 0x02AC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG35_CS; /* offset: 0x02B0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG35_ID; /* offset: 0x02B4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE0_3; /* offset: 0x02B8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE4_7; /* offset: 0x02BC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG36_CS; /* offset: 0x02C0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG36_ID; /* offset: 0x02C4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE0_3; /* offset: 0x02C8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE4_7; /* offset: 0x02CC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG37_CS; /* offset: 0x02D0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG37_ID; /* offset: 0x02D4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE0_3; /* offset: 0x02D8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE4_7; /* offset: 0x02DC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG38_CS; /* offset: 0x02E0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG38_ID; /* offset: 0x02E4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE0_3; /* offset: 0x02E8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE4_7; /* offset: 0x02EC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG39_CS; /* offset: 0x02F0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG39_ID; /* offset: 0x02F4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE0_3; /* offset: 0x02F8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE4_7; /* offset: 0x02FC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG40_CS; /* offset: 0x0300 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG40_ID; /* offset: 0x0304 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE0_3; /* offset: 0x0308 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE4_7; /* offset: 0x030C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG41_CS; /* offset: 0x0310 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG41_ID; /* offset: 0x0314 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE0_3; /* offset: 0x0318 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE4_7; /* offset: 0x031C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG42_CS; /* offset: 0x0320 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG42_ID; /* offset: 0x0324 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE0_3; /* offset: 0x0328 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE4_7; /* offset: 0x032C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG43_CS; /* offset: 0x0330 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG43_ID; /* offset: 0x0334 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE0_3; /* offset: 0x0338 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE4_7; /* offset: 0x033C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG44_CS; /* offset: 0x0340 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG44_ID; /* offset: 0x0344 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE0_3; /* offset: 0x0348 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE4_7; /* offset: 0x034C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG45_CS; /* offset: 0x0350 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG45_ID; /* offset: 0x0354 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE0_3; /* offset: 0x0358 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE4_7; /* offset: 0x035C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG46_CS; /* offset: 0x0360 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG46_ID; /* offset: 0x0364 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE0_3; /* offset: 0x0368 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE4_7; /* offset: 0x036C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG47_CS; /* offset: 0x0370 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG47_ID; /* offset: 0x0374 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE0_3; /* offset: 0x0378 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE4_7; /* offset: 0x037C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG48_CS; /* offset: 0x0380 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG48_ID; /* offset: 0x0384 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE0_3; /* offset: 0x0388 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE4_7; /* offset: 0x038C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG49_CS; /* offset: 0x0390 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG49_ID; /* offset: 0x0394 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE0_3; /* offset: 0x0398 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE4_7; /* offset: 0x039C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG50_CS; /* offset: 0x03A0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG50_ID; /* offset: 0x03A4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE0_3; /* offset: 0x03A8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE4_7; /* offset: 0x03AC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG51_CS; /* offset: 0x03B0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG51_ID; /* offset: 0x03B4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE0_3; /* offset: 0x03B8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE4_7; /* offset: 0x03BC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG52_CS; /* offset: 0x03C0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG52_ID; /* offset: 0x03C4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE0_3; /* offset: 0x03C8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE4_7; /* offset: 0x03CC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG53_CS; /* offset: 0x03D0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG53_ID; /* offset: 0x03D4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE0_3; /* offset: 0x03D8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE4_7; /* offset: 0x03DC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG54_CS; /* offset: 0x03E0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG54_ID; /* offset: 0x03E4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE0_3; /* offset: 0x03E8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE4_7; /* offset: 0x03EC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG55_CS; /* offset: 0x03F0 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG55_ID; /* offset: 0x03F4 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE0_3; /* offset: 0x03F8 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE4_7; /* offset: 0x03FC size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG56_CS; /* offset: 0x0400 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG56_ID; /* offset: 0x0404 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE0_3; /* offset: 0x0408 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE4_7; /* offset: 0x040C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG57_CS; /* offset: 0x0410 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG57_ID; /* offset: 0x0414 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE0_3; /* offset: 0x0418 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE4_7; /* offset: 0x041C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG58_CS; /* offset: 0x0420 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG58_ID; /* offset: 0x0424 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE0_3; /* offset: 0x0428 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE4_7; /* offset: 0x042C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG59_CS; /* offset: 0x0430 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG59_ID; /* offset: 0x0434 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE0_3; /* offset: 0x0438 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE4_7; /* offset: 0x043C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG60_CS; /* offset: 0x0440 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG60_ID; /* offset: 0x0444 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE0_3; /* offset: 0x0448 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE4_7; /* offset: 0x044C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG61_CS; /* offset: 0x0450 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG61_ID; /* offset: 0x0454 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE0_3; /* offset: 0x0458 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE4_7; /* offset: 0x045C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG62_CS; /* offset: 0x0460 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG62_ID; /* offset: 0x0464 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE0_3; /* offset: 0x0468 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE4_7; /* offset: 0x046C size: 32 bit */ - /* Message Buffer Control and Status */ - FLEXCAN_MSG_CS_32B_tag MSG63_CS; /* offset: 0x0470 size: 32 bit */ - /* Message Buffer Identifier Field */ - FLEXCAN_MSG_ID_32B_tag MSG63_ID; /* offset: 0x0474 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE0_3; /* offset: 0x0478 size: 32 bit */ - /* Message Buffer Data Register */ - FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE4_7; /* offset: 0x047C size: 32 bit */ - }; - - }; - int8_t FLEXCAN_reserved_0480_C[1024]; - union { - /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ - FLEXCAN_RXIMR_32B_tag RXIMR[64]; /* offset: 0x0880 (0x0004 x 64) */ - - struct { - /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ - FLEXCAN_RXIMR_32B_tag RXIMR0; /* offset: 0x0880 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR1; /* offset: 0x0884 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR2; /* offset: 0x0888 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR3; /* offset: 0x088C size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR4; /* offset: 0x0890 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR5; /* offset: 0x0894 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR6; /* offset: 0x0898 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR7; /* offset: 0x089C size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR8; /* offset: 0x08A0 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR9; /* offset: 0x08A4 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR10; /* offset: 0x08A8 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR11; /* offset: 0x08AC size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR12; /* offset: 0x08B0 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR13; /* offset: 0x08B4 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR14; /* offset: 0x08B8 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR15; /* offset: 0x08BC size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR16; /* offset: 0x08C0 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR17; /* offset: 0x08C4 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR18; /* offset: 0x08C8 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR19; /* offset: 0x08CC size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR20; /* offset: 0x08D0 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR21; /* offset: 0x08D4 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR22; /* offset: 0x08D8 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR23; /* offset: 0x08DC size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR24; /* offset: 0x08E0 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR25; /* offset: 0x08E4 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR26; /* offset: 0x08E8 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR27; /* offset: 0x08EC size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR28; /* offset: 0x08F0 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR29; /* offset: 0x08F4 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR30; /* offset: 0x08F8 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR31; /* offset: 0x08FC size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR32; /* offset: 0x0900 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR33; /* offset: 0x0904 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR34; /* offset: 0x0908 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR35; /* offset: 0x090C size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR36; /* offset: 0x0910 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR37; /* offset: 0x0914 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR38; /* offset: 0x0918 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR39; /* offset: 0x091C size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR40; /* offset: 0x0920 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR41; /* offset: 0x0924 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR42; /* offset: 0x0928 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR43; /* offset: 0x092C size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR44; /* offset: 0x0930 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR45; /* offset: 0x0934 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR46; /* offset: 0x0938 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR47; /* offset: 0x093C size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR48; /* offset: 0x0940 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR49; /* offset: 0x0944 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR50; /* offset: 0x0948 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR51; /* offset: 0x094C size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR52; /* offset: 0x0950 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR53; /* offset: 0x0954 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR54; /* offset: 0x0958 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR55; /* offset: 0x095C size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR56; /* offset: 0x0960 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR57; /* offset: 0x0964 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR58; /* offset: 0x0968 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR59; /* offset: 0x096C size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR60; /* offset: 0x0970 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR61; /* offset: 0x0974 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR62; /* offset: 0x0978 size: 32 bit */ - FLEXCAN_RXIMR_32B_tag RXIMR63; /* offset: 0x097C size: 32 bit */ - }; - - }; - } FLEXCAN_tag; - - -#define FLEXCAN_A (*(volatile FLEXCAN_tag *) 0xFFFC0000UL) -#define FLEXCAN_B (*(volatile FLEXCAN_tag *) 0xFFFC4000UL) - - - -/****************************************************************/ -/* */ -/* Module: DMA_CH_MUX */ -/* */ -/****************************************************************/ - - - /* Register layout for all registers CHCONFIG... */ - - typedef union { /* CHCONFIG[0-15] - Channel Configuration Registers */ - uint8_t R; - struct { - uint8_t ENBL:1; /* DMA Channel Enable */ - uint8_t TRIG:1; /* DMA Channel Trigger Enable */ - uint8_t SOURCE:6; /* DMA Channel Source */ - } B; - } DMA_CH_MUX_CHCONFIG_8B_tag; - - - - typedef struct DMA_CH_MUX_struct_tag { /* start of DMA_CH_MUX_tag */ - union { - /* CHCONFIG[0-15] - Channel Configuration Registers */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG[16]; /* offset: 0x0000 (0x0001 x 16) */ - - struct { - /* CHCONFIG[0-15] - Channel Configuration Registers */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG0; /* offset: 0x0000 size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG1; /* offset: 0x0001 size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG2; /* offset: 0x0002 size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG3; /* offset: 0x0003 size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG4; /* offset: 0x0004 size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG5; /* offset: 0x0005 size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG6; /* offset: 0x0006 size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG7; /* offset: 0x0007 size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG8; /* offset: 0x0008 size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG9; /* offset: 0x0009 size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG10; /* offset: 0x000A size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG11; /* offset: 0x000B size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG12; /* offset: 0x000C size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG13; /* offset: 0x000D size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG14; /* offset: 0x000E size: 8 bit */ - DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG15; /* offset: 0x000F size: 8 bit */ - }; - - }; - } DMA_CH_MUX_tag; - - -#define DMA_CH_MUX (*(volatile DMA_CH_MUX_tag *) 0xFFFDC000UL) - - - -/****************************************************************/ -/* */ -/* Module: FR */ -/* */ -/****************************************************************/ - - typedef union { /* Module Version Number */ - uint16_t R; - struct { - uint16_t CHIVER:8; /* VERSION NUMBER OF CHI */ - uint16_t PEVER:8; /* VERSION NUMBER OF PE */ - } B; - } FR_MVR_16B_tag; - - typedef union { /* Module Configuration Register */ - uint16_t R; - struct { - uint16_t MEN:1; /* Module Enable */ - uint16_t SBFF:1; /* System Bus Failure Freeze */ -#ifndef USE_FIELD_ALIASES_FR - uint16_t SCM:1; /* single channel device mode */ -#else - uint16_t SCMD:1; /* deprecated name - please avoid */ -#endif - uint16_t CHB:1; /* Channel B enable */ - uint16_t CHA:1; /* channel A enable */ - uint16_t SFFE:1; /* Sync. frame filter Enable */ - uint16_t ECCE:1; /* ECC Functionlity Enable */ - uint16_t TMODER:1; /* Functional Test mode */ - uint16_t FUM:1; /* FIFO Update Mode */ - uint16_t FAM:1; /* FIFO Address Mode */ - uint16_t:1; - uint16_t CLKSEL:1; /* Protocol Engine clock source select */ - uint16_t BITRATE:3; /* Bus bit rate */ - uint16_t:1; - } B; - } FR_MCR_16B_tag; - - typedef union { /* SYSTEM MEMORY BASE ADD HIGH REG */ - uint16_t R; - struct { - uint16_t SMBA_31_16:16; /* SYS_MEM_BASE_ADDR[31:16] */ - } B; - } FR_SYMBADHR_16B_tag; - - typedef union { /* SYSTEM MEMORY BASE ADD LOW REG */ - uint16_t R; - struct { - uint16_t SMBA_15_4:12; /* SYS_MEM_BASE_ADDR[15:4] */ - uint16_t:4; - } B; - } FR_SYMBADLR_16B_tag; - - typedef union { /* STROBE SIGNAL CONTROL REGISTER */ - uint16_t R; - struct { - uint16_t WMD:1; /* DEFINES WRITE MODE OF REG */ - uint16_t:3; - uint16_t SEL:4; /* STROBE SIGNSL SELECT */ - uint16_t:3; - uint16_t ENB:1; /* STROBE SIGNAL ENABLE */ - uint16_t:2; - uint16_t STBPSEL:2; /* STROBE PORT SELECT */ - } B; - } FR_STBSCR_16B_tag; - - typedef union { /* MESSAGE BUFFER DATA SIZE REGISTER */ - uint16_t R; - struct { - uint16_t:1; - uint16_t MBSEG2DS:7; /* MESSAGE BUFFER SEGMENT 2 DATA SIZE */ - uint16_t:1; - uint16_t MBSEG1DS:7; /* MESSAGE BUFFER SEGMENT 1 DATA SIZE */ - } B; - } FR_MBDSR_16B_tag; - - typedef union { /* MESS. BUFFER SEG. SIZE & UTILISATION REG */ - uint16_t R; - struct { - uint16_t:2; - uint16_t LAST_MB_SEG1:6; /* LAST MESS BUFFER IN SEG 1 */ - uint16_t:2; - uint16_t LAST_MB_UTIL:6; /* LAST MESSAGE BUFFER UTILISED */ - } B; - } FR_MBSSUTR_16B_tag; - - typedef union { /* PE DRAM ACCESS REGISTER */ - uint16_t R; - struct { - uint16_t INST:4; /* PE DRAM ACCESS INSTRUCTION */ - uint16_t ADDR:11; /* PE DRAM ACCESS ADDRESS */ - uint16_t DAD:1; /* PE DRAM ACCESS DONE */ - } B; - } FR_PEDRAR_16B_tag; - - typedef union { /* PE DRAM DATA REGISTER */ - uint16_t R; - struct { - uint16_t DATA:16; /* DATA TO BE READ OR WRITTEN */ - } B; - } FR_PEDRDR_16B_tag; - - typedef union { /* PROTOCOL OPERATION CONTROL REG */ - uint16_t R; - struct { - uint16_t WME:1; /* WRITE MODE EXTERNAL CORRECTION */ - uint16_t:3; - uint16_t EOC_AP:2; /* EXTERNAL OFFSET CORRECTION APPLICATION */ - uint16_t ERC_AP:2; /* EXTERNAL RATE CORRECTION APPLICATION */ - uint16_t BSY:1; /* PROTOCOL CONTROL COMMAND WRITE BUSY */ - uint16_t:3; - uint16_t POCCMD:4; /* PROTOCOL CONTROL COMMAND */ - } B; - } FR_POCR_16B_tag; - - typedef union { /* GLOBAL INTERRUPT FLAG & ENABLE REG */ - uint16_t R; - struct { - uint16_t MIF:1; /* MODULE INTERRUPT FLAG */ - uint16_t PRIF:1; /* PROTOCOL INTERRUPT FLAG */ - uint16_t CHIF:1; /* CHI INTERRUPT FLAG */ -#ifndef USE_FIELD_ALIASES_FR - uint16_t WUPIF:1; /* WAKEUP INTERRUPT FLAG */ -#else - uint16_t WKUPIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t FAFBIF:1; /* RECEIVE FIFO CHANNEL B ALMOST FULL INTERRUPT FLAG */ -#else - uint16_t FNEBIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t FAFAIF:1; /* RECEIVE FIFO CHANNEL A ALMOST FULL INTERRUPT FLAG */ -#else - uint16_t FNEAIF:1; /* deprecated name - please avoid */ -#endif - uint16_t RBIF:1; /* RECEIVE MESSAGE BUFFER INTERRUPT FLAG */ - uint16_t TBIF:1; /* TRANSMIT BUFFER INTERRUPT FLAG */ - uint16_t MIE:1; /* MODULE INTERRUPT ENABLE */ - uint16_t PRIE:1; /* PROTOCOL INTERRUPT ENABLE */ - uint16_t CHIE:1; /* CHI INTERRUPT ENABLE */ -#ifndef USE_FIELD_ALIASES_FR - uint16_t WUPIE:1; /* WAKEUP INTERRUPT ENABLE */ -#else - uint16_t WKUPIE:1; /* deprecated name - please avoid */ -#endif - uint16_t FNEBIE:1; /* RECEIVE FIFO CHANNEL B NOT EMPTY INTERRUPT ENABLE */ - uint16_t FNEAIE:1; /* RECEIVE FIFO CHANNEL A NOT EMPTY INTERRUPT ENABLE */ - uint16_t RBIE:1; /* RECEIVE BUFFER INTERRUPT ENABLE */ - uint16_t TBIE:1; /* TRANSMIT BUFFER INTERRUPT ENABLE */ - } B; - } FR_GIFER_16B_tag; - - typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 0 */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_FR - uint16_t FATL_IF:1; /* FATAL PROTOCOL ERROR INTERRUPT FLAG */ -#else - uint16_t FATLIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t INTL_IF:1; /* INTERNAL PROTOCOL ERROR INTERRUPT FLAG */ -#else - uint16_t INTLIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t ILCF_IF:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT FLAG */ -#else - uint16_t ILCFIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t CSA_IF:1; /* COLDSTART ABORT INTERRUPT FLAG */ -#else - uint16_t CSAIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t MRC_IF:1; /* MISSING RATE CORRECTION INTERRUPT FLAG */ -#else - uint16_t MRCIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t MOC_IF:1; /* MISSING OFFSET CORRECTION INTERRUPT FLAG */ -#else - uint16_t MOCIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t CCL_IF:1; /* CLOCK CORRECTION LIMIT REACHED INTERRUPT FLAG */ -#else - uint16_t CCLIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t MXS_IF:1; /* MAX SYNC FRAMES DETECTED INTERRUPT FLAG */ -#else - uint16_t MXSIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t MTX_IF:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT FLAG */ -#else - uint16_t MTXIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t LTXB_IF:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT FLAG */ -#else - uint16_t LTXBIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t LTXA_IF:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT FLAG */ -#else - uint16_t LTXAIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t TBVB_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT FLAG */ -#else - uint16_t TBVBIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t TBVA_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT FLAG */ -#else - uint16_t TBVAIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t TI2_IF:1; /* TIMER 2 EXPIRED INTERRUPT FLAG */ -#else - uint16_t TI2IF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t TI1_IF:1; /* TIMER 1 EXPIRED INTERRUPT FLAG */ -#else - uint16_t TI1IF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t CYS_IF:1; /* CYCLE START INTERRUPT FLAG */ -#else - uint16_t CYSIF:1; /* deprecated name - please avoid */ -#endif - } B; - } FR_PIFR0_16B_tag; - - typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 1 */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_FR - uint16_t EMC_IF:1; /* ERROR MODE CHANGED INTERRUPT FLAG */ -#else - uint16_t EMCIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t IPC_IF:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT FLAG */ -#else - uint16_t IPCIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t PECF_IF:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT FLAG */ -#else - uint16_t PECFIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t PSC_IF:1; /* PROTOCOL STATE CHANGED INTERRUPT FLAG */ -#else - uint16_t PSCIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t SSI3_IF:1; /* SLOT STATUS COUNTER 3 INCREMENTED INTERRUPT FLAG */ -#else - uint16_t SSI3IF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t SSI2_IF:1; /* SLOT STATUS COUNTER 2 INCREMENTED INTERRUPT FLAG */ -#else - uint16_t SSI2IF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t SSI1_IF:1; /* SLOT STATUS COUNTER 1 INCREMENTED INTERRUPT FLAG */ -#else - uint16_t SSI1IF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t SSI0_IF:1; /* SLOT STATUS COUNTER 0 INCREMENTED INTERRUPT FLAG */ -#else - uint16_t SSI0IF:1; /* deprecated name - please avoid */ -#endif - uint16_t:2; -#ifndef USE_FIELD_ALIASES_FR - uint16_t EVT_IF:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT FLAG */ -#else - uint16_t EVTIF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t ODT_IF:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT FLAG */ -#else - uint16_t ODTIF:1; /* deprecated name - please avoid */ -#endif - uint16_t:4; - } B; - } FR_PIFR1_16B_tag; - - typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_FR - uint16_t FATL_IE:1; /* FATAL PROTOCOL ERROR INTERRUPT ENABLE */ -#else - uint16_t FATLIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t INTL_IE:1; /* INTERNAL PROTOCOL ERROR INTERRUPT ENABLE */ -#else - uint16_t INTLIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t ILCF_IE:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT ENABLE */ -#else - uint16_t ILCFIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t CSA_IE:1; /* COLDSTART ABORT INTERRUPT ENABLE */ -#else - uint16_t CSAIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t MRC_IE:1; /* MISSING RATE CORRECTION INTERRUPT ENABLE */ -#else - uint16_t MRCIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t MOC_IE:1; /* MISSING OFFSET CORRECTION INTERRUPT ENABLE */ -#else - uint16_t MOCIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t CCL_IE:1; /* CLOCK CORRECTION LIMIT REACHED */ -#else - uint16_t CCLIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t MXS_IE:1; /* MAX SYNC FRAMES DETECTED INTERRUPT ENABLE */ -#else - uint16_t MXSIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t MTX_IE:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT ENABLE */ -#else - uint16_t MTXIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t LTXB_IE:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT ENABLE */ -#else - uint16_t LTXBIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t LTXA_IE:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT ENABLE */ -#else - uint16_t LTXAIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t TBVB_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT ENABLE */ -#else - uint16_t TBVBIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t TBVA_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT ENABLE */ -#else - uint16_t TBVAIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t TI2_IE:1; /* TIMER 2 EXPIRED INTERRUPT ENABLE */ -#else - uint16_t TI2IE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t TI1_IE:1; /* TIMER 1 EXPIRED INTERRUPT ENABLE */ -#else - uint16_t TI1IE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t CYS_IE:1; /* CYCLE START INTERRUPT ENABLE */ -#else - uint16_t CYSIE:1; /* deprecated name - please avoid */ -#endif - } B; - } FR_PIER0_16B_tag; - - typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_FR - uint16_t EMC_IE:1; /* ERROR MODE CHANGED INTERRUPT Enable */ -#else - uint16_t EMCIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t IPC_IE:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT Enable */ -#else - uint16_t IPCIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t PECF_IE:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT Enable */ -#else - uint16_t PECFIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t PSC_IE:1; /* PROTOCOL STATE CHANGED INTERRUPT Enable */ -#else - uint16_t PSCIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t SSI_3_0_IE:4; /* SLOT STATUS COUNTER INCREMENTED INTERRUPT Enable */ -#else - uint16_t SSI3IE:1; - uint16_t SSI2IE:1; - uint16_t SSI1IE:1; - uint16_t SSI0IE:1; -#endif - - uint16_t:2; -#ifndef USE_FIELD_ALIASES_FR - uint16_t EVT_IE:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT Enable */ -#else - uint16_t EVTIE:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t ODT_IE:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT Enable */ -#else - uint16_t ODTIE:1; /* deprecated name - please avoid */ -#endif - uint16_t:4; - } B; - } FR_PIER1_16B_tag; - - typedef union { /* CHI ERROR FLAG REGISTER */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_FR - uint16_t FRLB_EF:1; /* FRAME LOST CHANNEL B ERROR FLAG */ -#else - uint16_t FRLBEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t FRLA_EF:1; /* FRAME LOST CHANNEL A ERROR FLAG */ -#else - uint16_t FRLAEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t PCMI_EF:1; /* PROTOCOL COMMAND IGNORED ERROR FLAG */ -#else - uint16_t PCMIEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t FOVB_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL B ERROR FLAG */ -#else - uint16_t FOVBEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t FOVA_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL A ERROR FLAG */ -#else - uint16_t FOVAEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t MBS_EF:1; /* MESSAGE BUFFER SEARCH ERROR FLAG */ -#else - uint16_t MSBEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t MBU_EF:1; /* MESSAGE BUFFER UTILIZATION ERROR FLAG */ -#else - uint16_t MBUEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t LCK_EF:1; /* LOCK ERROR FLAG */ -#else - uint16_t LCKEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t DBL_EF:1; /* DOUBLE TRANSMIT MESSAGE BUFFER LOCK ERROR FLAG */ -#else - uint16_t DBLEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t SBCF_EF:1; /* SYSTEM BUS COMMUNICATION FAILURE ERROR FLAG */ -#else - uint16_t SBCFEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t FID_EF:1; /* FRAME ID ERROR FLAG */ -#else - uint16_t FIDEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t DPL_EF:1; /* DYNAMIC PAYLOAD LENGTH ERROR FLAG */ -#else - uint16_t DPLEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t SPL_EF:1; /* STATIC PAYLOAD LENGTH ERROR FLAG */ -#else - uint16_t SPLEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t NML_EF:1; /* NETWORK MANAGEMENT LENGTH ERROR FLAG */ -#else - uint16_t NMLEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t NMF_EF:1; /* NETWORK MANAGEMENT FRAME ERROR FLAG */ -#else - uint16_t NMFEF:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t ILSA_EF:1; /* ILLEGAL SYSTEM MEMORY ACCESS ERROR FLAG */ -#else - uint16_t ILSAEF:1; /* deprecated name - please avoid */ -#endif - } B; - } FR_CHIERFR_16B_tag; - - typedef union { /* Message Buffer Interrupt Vector Register */ - uint16_t R; - struct { - uint16_t:2; - uint16_t TBIVEC:6; /* Transmit Buffer Interrupt Vector */ - uint16_t:2; - uint16_t RBIVEC:6; /* Receive Buffer Interrupt Vector */ - } B; - } FR_MBIVEC_16B_tag; - - typedef union { /* Channel A Status Error Counter Register */ - uint16_t R; - struct { - uint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */ - } B; - } FR_CASERCR_16B_tag; - - typedef union { /* Channel B Status Error Counter Register */ - uint16_t R; - struct { - uint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */ - } B; - } FR_CBSERCR_16B_tag; - - typedef union { /* Protocol Status Register 0 */ - uint16_t R; - struct { - uint16_t ERRMODE:2; /* Error Mode */ - uint16_t SLOTMODE:2; /* Slot Mode */ - uint16_t:1; - uint16_t PROTSTATE:3; /* Protocol State */ -#ifndef USE_FIELD_ALIASES_FR - uint16_t STARTUPSTATE:4; /* Startup State */ -#else - uint16_t SUBSTATE:4; /* deprecated name - please avoid */ -#endif - uint16_t WAKEUPSTATE:4; /* Wakeup Status */ - } B; - } FR_PSR0_16B_tag; - - typedef union { /* Protocol Status Register 1 */ - uint16_t R; - struct { - uint16_t CSAA:1; /* Coldstart Attempt Aborted Flag */ - uint16_t CSP:1; /* Leading Coldstart Path */ - uint16_t:1; - uint16_t REMCSAT:5; /* Remaining Coldstart Attempts */ - uint16_t CPN:1; /* Leading Coldstart Path Noise */ - uint16_t HHR:1; /* Host Halt Request Pending */ - uint16_t FRZ:1; /* Freeze Occurred */ - uint16_t APTAC:5; /* Allow Passive to Active Counter */ - } B; - } FR_PSR1_16B_tag; - - typedef union { /* Protocol Status Register 2 */ - uint16_t R; - struct { - uint16_t NBVB:1; /* NIT Boundary Violation on Channel B */ - uint16_t NSEB:1; /* NIT Syntax Error on Channel B */ - uint16_t STCB:1; /* Symbol Window Transmit Conflict on Channel B */ -#ifndef USE_FIELD_ALIASES_FR - uint16_t SSVB:1; /* Symbol Window Boundary Violation on Channel B */ -#else - uint16_t SBVB:1; /* deprecated name - please avoid */ -#endif - uint16_t SSEB:1; /* Symbol Window Syntax Error on Channel B */ - uint16_t MTB:1; /* Media Access Test Symbol MTS Received on Channel B */ - uint16_t NBVA:1; /* NIT Boundary Violation on Channel A */ - uint16_t NSEA:1; /* NIT Syntax Error on Channel A */ - uint16_t STCA:1; /* Symbol Window Transmit Conflict on Channel A */ - uint16_t SBVA:1; /* Symbol Window Boundary Violation on Channel A */ - uint16_t SSEA:1; /* Symbol Window Syntax Error on Channel A */ - uint16_t MTA:1; /* Media Access Test Symbol MTS Received on Channel A */ - uint16_t CLKCORRFAILCNT:4; /* Clock Correction Failed Counter */ - } B; - } FR_PSR2_16B_tag; - - typedef union { /* Protocol Status Register 3 */ - uint16_t R; - struct { - uint16_t:2; - uint16_t WUB:1; /* Wakeup Symbol Received on Channel B */ - uint16_t ABVB:1; /* Aggregated Boundary Violation on Channel B */ - uint16_t AACB:1; /* Aggregated Additional Communication on Channel B */ - uint16_t ACEB:1; /* Aggregated Content Error on Channel B */ - uint16_t ASEB:1; /* Aggregated Syntax Error on Channel B */ - uint16_t AVFB:1; /* Aggregated Valid Frame on Channel B */ - uint16_t:2; - uint16_t WUA:1; /* Wakeup Symbol Received on Channel A */ - uint16_t ABVA:1; /* Aggregated Boundary Violation on Channel A */ - uint16_t AACA:1; /* Aggregated Additional Communication on Channel A */ - uint16_t ACEA:1; /* Aggregated Content Error on Channel A */ - uint16_t ASEA:1; /* Aggregated Syntax Error on Channel A */ - uint16_t AVFA:1; /* Aggregated Valid Frame on Channel A */ - } B; - } FR_PSR3_16B_tag; - - typedef union { /* Macrotick Counter Register */ - uint16_t R; - struct { - uint16_t:2; - uint16_t MTCT:14; /* Macrotick Counter */ - } B; - } FR_MTCTR_16B_tag; - - typedef union { /* Cycle Counter Register */ - uint16_t R; - struct { - uint16_t:10; - uint16_t CYCCNT:6; /* Cycle Counter */ - } B; - } FR_CYCTR_16B_tag; - - typedef union { /* Slot Counter Channel A Register */ - uint16_t R; - struct { - uint16_t:5; - uint16_t SLOTCNTA:11; /* Slot Counter Value for Channel A */ - } B; - } FR_SLTCTAR_16B_tag; - - typedef union { /* Slot Counter Channel B Register */ - uint16_t R; - struct { - uint16_t:5; - uint16_t SLOTCNTB:11; /* Slot Counter Value for Channel B */ - } B; - } FR_SLTCTBR_16B_tag; - - typedef union { /* Rate Correction Value Register */ - uint16_t R; - struct { - uint16_t RATECORR:16; /* Rate Correction Value */ - } B; - } FR_RTCORVR_16B_tag; - - typedef union { /* Offset Correction Value Register */ - uint16_t R; - struct { - uint16_t:6; - uint16_t OFFSETCORR:10; /* Offset Correction Value */ - } B; - } FR_OFCORVR_16B_tag; - - typedef union { /* Combined Interrupt Flag Register */ - uint16_t R; - struct { - uint16_t:8; -#ifndef USE_FIELD_ALIASES_FR - uint16_t MIF:1; /* Module Interrupt Flag */ -#else - uint16_t MIFR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t PRIF:1; /* Protocol Interrupt Flag */ -#else - uint16_t PRIFR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t CHIF:1; /* CHI Interrupt Flag */ -#else - uint16_t CHIFR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t WUPIF:1; /* Wakeup Interrupt Flag */ -#else - uint16_t WUPIFR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t FAFBIF:1; /* Receive FIFO channel B Almost Full Interrupt Flag */ -#else - uint16_t FNEBIFR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t FAFAIF:1; /* Receive FIFO channel A Almost Full Interrupt Flag */ -#else - uint16_t FNEAIFR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t RBIF:1; /* Receive Message Buffer Interrupt Flag */ -#else - uint16_t RBIFR:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t TBIF:1; /* Transmit Message Buffer Interrupt Flag */ -#else - uint16_t TBIFR:1; /* deprecated name - please avoid */ -#endif - } B; - } FR_CIFR_16B_tag; - - typedef union { /* System Memory Access Time-Out Register */ - uint16_t R; - struct { - uint16_t:8; - uint16_t TIMEOUT:8; /* Time-Out */ - } B; - } FR_SYMATOR_16B_tag; - - typedef union { /* Sync Frame Counter Register */ - uint16_t R; - struct { - uint16_t SFEVB:4; /* Sync Frames Channel B, even cycle */ - uint16_t SFEVA:4; /* Sync Frames Channel A, even cycle */ - uint16_t SFODB:4; /* Sync Frames Channel B, odd cycle */ - uint16_t SFODA:4; /* Sync Frames Channel A, odd cycle */ - } B; - } FR_SFCNTR_16B_tag; - - typedef union { /* Sync Frame Table Offset Register */ - uint16_t R; - struct { - uint16_t SFT_OFFSET_15_1:15; /* Sync Frame Table Offset */ - uint16_t:1; - } B; - } FR_SFTOR_16B_tag; - - typedef union { /* Sync Frame Table Configuration, Control, Status Register */ - uint16_t R; - struct { - uint16_t ELKT:1; /* Even Cycle Tables Lock/Unlock Trigger */ - uint16_t OLKT:1; /* Odd Cycle Tables Lock/Unlock Trigger */ - uint16_t CYCNUM:6; /* Cycle Number */ - uint16_t ELKS:1; /* Even Cycle Tables Lock Status */ - uint16_t OLKS:1; /* Odd Cycle Tables Lock Status */ - uint16_t EVAL:1; /* Even Cycle Tables Valid */ - uint16_t OVAL:1; /* Odd Cycle Tables Valid */ - uint16_t:1; - uint16_t OPT:1; /* One Pair Trigger */ - uint16_t SDVEN:1; /* Sync Frame Deviation Table Enable */ -#ifndef USE_FIELD_ALIASES_FR - uint16_t SIVEN:1; /* Sync Frame ID Table Enable */ -#else - uint16_t SIDEN:1; /* deprecated name - please avoid */ -#endif - } B; - } FR_SFTCCSR_16B_tag; - - typedef union { /* Sync Frame ID Rejection Filter */ - uint16_t R; - struct { - uint16_t:6; - uint16_t SYNFRID:10; /* Sync Frame Rejection ID */ - } B; - } FR_SFIDRFR_16B_tag; - - typedef union { /* Sync Frame ID Acceptance Filter Value Register */ - uint16_t R; - struct { - uint16_t:6; - uint16_t FVAL:10; /* Filter Value */ - } B; - } FR_SFIDAFVR_16B_tag; - - typedef union { /* Sync Frame ID Acceptance Filter Mask Register */ - uint16_t R; - struct { - uint16_t:6; - uint16_t FMSK:10; /* Filter Mask */ - } B; - } FR_SFIDAFMR_16B_tag; - - typedef union { /* Network Management Vector Register0 */ - uint16_t R; - struct { - uint16_t NMVP_15_8:8; /* Network Management Vector Part */ - uint16_t NMVP_7_0:8; /* Network Management Vector Part */ - } B; - } FR_NMVR0_16B_tag; - - typedef union { /* Network Management Vector Register1 */ - uint16_t R; - struct { - uint16_t NMVP_15_8:8; /* Network Management Vector Part */ - uint16_t NMVP_7_0:8; /* Network Management Vector Part */ - } B; - } FR_NMVR1_16B_tag; - - typedef union { /* Network Management Vector Register2 */ - uint16_t R; - struct { - uint16_t NMVP_15_8:8; /* Network Management Vector Part */ - uint16_t NMVP_7_0:8; /* Network Management Vector Part */ - } B; - } FR_NMVR2_16B_tag; - - typedef union { /* Network Management Vector Register3 */ - uint16_t R; - struct { - uint16_t NMVP_15_8:8; /* Network Management Vector Part */ - uint16_t NMVP_7_0:8; /* Network Management Vector Part */ - } B; - } FR_NMVR3_16B_tag; - - typedef union { /* Network Management Vector Register4 */ - uint16_t R; - struct { - uint16_t NMVP_15_8:8; /* Network Management Vector Part */ - uint16_t NMVP_7_0:8; /* Network Management Vector Part */ - } B; - } FR_NMVR4_16B_tag; - - typedef union { /* Network Management Vector Register5 */ - uint16_t R; - struct { - uint16_t NMVP_15_8:8; /* Network Management Vector Part */ - uint16_t NMVP_7_0:8; /* Network Management Vector Part */ - } B; - } FR_NMVR5_16B_tag; - - typedef union { /* Network Management Vector Length Register */ - uint16_t R; - struct { - uint16_t:12; - uint16_t NMVL:4; /* Network Management Vector Length */ - } B; - } FR_NMVLR_16B_tag; - - typedef union { /* Timer Configuration and Control Register */ - uint16_t R; - struct { - uint16_t:2; -#ifndef USE_FIELD_ALIASES_FR - uint16_t T2_CFG:1; /* Timer T2 Configuration */ -#else - uint16_t T2CFG:1; /* Timer T2 Configuration */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t T2_REP:1; /* Timer T2 Repetitive Mode */ -#else - uint16_t T2REP:1; /* Timer T2 Configuration */ -#endif - uint16_t:1; - uint16_t T2SP:1; /* Timer T2 Stop */ - uint16_t T2TR:1; /* Timer T2 Trigger */ - uint16_t T2ST:1; /* Timer T2 State */ - uint16_t:3; -#ifndef USE_FIELD_ALIASES_FR - uint16_t T1_REP:1; /* Timer T1 Repetitive Mode */ -#else - uint16_t T1REP:1; -#endif - uint16_t:1; - uint16_t T1SP:1; /* Timer T1 Stop */ - uint16_t T1TR:1; /* Timer T1 Trigger */ - uint16_t T1ST:1; /* Timer T1 State */ - } B; - } FR_TICCR_16B_tag; - - typedef union { /* Timer 1 Cycle Set Register */ - uint16_t R; - struct { - uint16_t:2; -#ifndef USE_FIELD_ALIASES_FR - uint16_t T1_CYC_VAL:6; /* Timer T1 Cycle Filter Value */ -#else - uint16_t TI1CYCVAL:1; /* Timer T1 Cycle Filter Value */ -#endif - uint16_t:2; -#ifndef USE_FIELD_ALIASES_FR - uint16_t T1_CYC_MSK:6; /* Timer T1 Cycle Filter Mask */ -#else - uint16_t TI1CYCMSK:1; /* Timer T1 Cycle Filter Mask */ -#endif - } B; - } FR_TI1CYSR_16B_tag; - - typedef union { /* Timer 1 Macrotick Offset Register */ - uint16_t R; - struct { - uint16_t:2; - uint16_t T1_MTOFFSET:14; /* Timer 1 Macrotick Offset */ - } B; - } FR_TI1MTOR_16B_tag; - - typedef union { /* Timer 2 Configuration Register 0 */ - uint16_t R; - struct { - uint16_t:2; - uint16_t T2_CYC_VAL:6; /* Timer T2 Cycle Filter Value */ - uint16_t:2; - uint16_t T2_CYC_MSK:6; /* Timer T2 Cycle Filter Mask */ - } B; - } FR_TI2CR0_16B_tag; - - typedef union { /* Timer 2 Configuration Register 1 */ - uint16_t R; - struct { - uint16_t T2_MTCNT:16; /* Timer T2 Macrotick Offset */ - } B; - } FR_TI2CR1_16B_tag; - - typedef union { /* Slot Status Selection Register */ - uint16_t R; - struct { - uint16_t WMD:1; /* Write Mode */ - uint16_t:1; - uint16_t SEL:2; /* Selector */ - uint16_t:1; - uint16_t SLOTNUMBER:11; /* Slot Number */ - } B; - } FR_SSSR_16B_tag; - - typedef union { /* Slot Status Counter Condition Register */ - uint16_t R; - struct { - uint16_t WMD:1; /* Write Mode */ - uint16_t:1; - uint16_t SEL:2; /* Selector */ - uint16_t:1; - uint16_t CNTCFG:2; /* Counter Configuration */ - uint16_t MCY:1; /* Multi Cycle Selection */ - uint16_t VFR:1; /* Valid Frame Restriction */ - uint16_t SYF:1; /* Sync Frame Restriction */ - uint16_t NUF:1; /* Null Frame Restriction */ - uint16_t SUF:1; /* Startup Frame Restriction */ - uint16_t STATUSMASK:4; /* Slot Status Mask */ - } B; - } FR_SSCCR_16B_tag; - - typedef union { /* Slot Status Register0 */ - uint16_t R; - struct { - uint16_t VFB:1; /* Valid Frame on Channel B */ - uint16_t SYB:1; /* Sync Frame Indicator Channel B */ - uint16_t NFB:1; /* Null Frame Indicator Channel B */ - uint16_t SUB:1; /* Startup Frame Indicator Channel B */ - uint16_t SEB:1; /* Syntax Error on Channel B */ - uint16_t CEB:1; /* Content Error on Channel B */ - uint16_t BVB:1; /* Boundary Violation on Channel B */ - uint16_t TCB:1; /* Transmission Conflict on Channel B */ - uint16_t VFA:1; /* Valid Frame on Channel A */ - uint16_t SYA:1; /* Sync Frame Indicator Channel A */ - uint16_t NFA:1; /* Null Frame Indicator Channel A */ - uint16_t SUA:1; /* Startup Frame Indicator Channel A */ - uint16_t SEA:1; /* Syntax Error on Channel A */ - uint16_t CEA:1; /* Content Error on Channel A */ - uint16_t BVA:1; /* Boundary Violation on Channel A */ - uint16_t TCA:1; /* Transmission Conflict on Channel A */ - } B; - } FR_SSR_16B_tag; - - - - typedef union { /* Slot Status Counter Register0 */ - uint16_t R; - struct { - uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ - } B; - } FR_SSCR0_16B_tag; - - typedef union { /* Slot Status Counter Register1 */ - uint16_t R; - struct { - uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ - } B; - } FR_SSCR1_16B_tag; - - typedef union { /* Slot Status Counter Register2 */ - uint16_t R; - struct { - uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ - } B; - } FR_SSCR2_16B_tag; - - typedef union { /* Slot Status Counter Register3 */ - uint16_t R; - struct { - uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ - } B; - } FR_SSCR3_16B_tag; - - typedef union { /* MTS A Configuration Register */ - uint16_t R; - struct { - uint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */ - uint16_t:1; - uint16_t CYCCNTMSK:6; /* Cycle Counter Mask */ - uint16_t:2; - uint16_t CYCCNTVAL:6; /* Cycle Counter Value */ - } B; - } FR_MTSACFR_16B_tag; - - typedef union { /* MTS B Configuration Register */ - uint16_t R; - struct { - uint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */ - uint16_t:1; - uint16_t CYCCNTMSK:6; /* Cycle Counter Mask */ - uint16_t:2; - uint16_t CYCCNTVAL:6; /* Cycle Counter Value */ - } B; - } FR_MTSBCFR_16B_tag; - - typedef union { /* Receive Shadow Buffer Index Register */ - uint16_t R; - struct { - uint16_t WMD:1; /* Write Mode */ - uint16_t:1; - uint16_t SEL:2; /* Selector */ - uint16_t:5; - uint16_t RSBIDX:7; /* Receive Shadow Buffer Index */ - } B; - } FR_RSBIR_16B_tag; - - typedef union { /* Receive FIFO Watermark and Selection Register */ - uint16_t R; - struct { - uint16_t WM:8; /* Watermark Value */ - uint16_t:7; - uint16_t SEL:1; /* Select */ - } B; - } FR_RFWMSR_16B_tag; - - typedef union { /* Receive FIFO Start Index Register */ - uint16_t R; - struct { - uint16_t:6; - uint16_t SIDX:10; /* Start Index */ - } B; - } FR_RF_RFSIR_16B_tag; - - typedef union { /* Receive FIFO Depth and Size Register */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_FR - uint16_t FIFO_DEPTH:8; /* FIFO Depth */ -#else - uint16_t FIFODEPTH:8; /* deprecated name - please avoid */ -#endif - uint16_t:1; -#ifndef USE_FIELD_ALIASES_FR - uint16_t ENTRY_SIZE:7; /* Entry Size */ -#else - uint16_t ENTRYSIZE:7; /* deprecated name - please avoid */ -#endif - } B; - } FR_RFDSR_16B_tag; - - typedef union { /* Receive FIFO A Read Index Register */ - uint16_t R; - struct { - uint16_t:6; - uint16_t RDIDX:10; /* Read Index */ - } B; - } FR_RFARIR_16B_tag; - - typedef union { /* Receive FIFO B Read Index Register */ - uint16_t R; - struct { - uint16_t:6; - uint16_t RDIDX:10; /* Read Index */ - } B; - } FR_RFBRIR_16B_tag; - - typedef union { /* Receive FIFO Message ID Acceptance Filter Value Register */ - uint16_t R; - struct { - uint16_t MIDAFVAL:16; /* Message ID Acceptance Filter Value */ - } B; - } FR_RFMIDAFVR_16B_tag; - - typedef union { /* Receive FIFO Message ID Acceptance Filter Mask Register */ - uint16_t R; - struct { - uint16_t MIDAFMSK:16; /* Message ID Acceptance Filter Mask */ - } B; - } FR_RFMIDAFMR_16B_tag; - - typedef union { /* Receive FIFO Frame ID Rejection Filter Value Register */ - uint16_t R; - struct { - uint16_t:5; - uint16_t FIDRFVAL:11; /* Frame ID Rejection Filter Value */ - } B; - } FR_RFFIDRFVR_16B_tag; - - typedef union { /* Receive FIFO Frame ID Rejection Filter Mask Register */ - uint16_t R; - struct { - uint16_t:5; - uint16_t FIDRFMSK:11; /* Frame ID Rejection Filter Mask */ - } B; - } FR_RFFIDRFMR_16B_tag; - - typedef union { /* Receive FIFO Range Filter Configuration Register */ - uint16_t R; - struct { - uint16_t WMD:1; /* Write Mode */ - uint16_t IBD:1; /* Interval Boundary */ - uint16_t SEL:2; /* Filter Selector */ - uint16_t:1; - uint16_t SID:11; /* Slot ID */ - } B; - } FR_RFRFCFR_16B_tag; - - typedef union { /* Receive FIFO Range Filter Control Register */ - uint16_t R; - struct { - uint16_t:4; - uint16_t F3MD:1; /* Range Filter 3 Mode */ - uint16_t F2MD:1; /* Range Filter 2 Mode */ - uint16_t F1MD:1; /* Range Filter 1 Mode */ - uint16_t F0MD:1; /* Range Filter 0 Mode */ - uint16_t:4; - uint16_t F3EN:1; /* Range Filter 3 Enable */ - uint16_t F2EN:1; /* Range Filter 2 Enable */ - uint16_t F1EN:1; /* Range Filter 1 Enable */ - uint16_t F0EN:1; /* Range Filter 0 Enable */ - } B; - } FR_RFRFCTR_16B_tag; - - typedef union { /* Last Dynamic Transmit Slot Channel A Register */ - uint16_t R; - struct { - uint16_t:5; - uint16_t LASTDYNTXSLOTA:11; /* Last Dynamic Transmission Slot Channel A */ - } B; - } FR_LDTXSLAR_16B_tag; - - typedef union { /* Last Dynamic Transmit Slot Channel B Register */ - uint16_t R; - struct { - uint16_t:5; - uint16_t LASTDYNTXSLOTB:11; /* Last Dynamic Transmission Slot Channel B */ - } B; - } FR_LDTXSLBR_16B_tag; - - typedef union { /* Protocol Configuration Register 0 */ - uint16_t R; - struct { - uint16_t ACTION_POINT_OFFSET:6; /* gdActionPointOffset - 1 */ - uint16_t STATIC_SLOT_LENGTH:10; /* gdStaticSlot */ - } B; - } FR_PCR0_16B_tag; - - typedef union { /* Protocol Configuration Register 1 */ - uint16_t R; - struct { - uint16_t:2; - uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; /* gMacroPerCycle - gdStaticSlot */ - } B; - } FR_PCR1_16B_tag; - - typedef union { /* Protocol Configuration Register 2 */ - uint16_t R; - struct { - uint16_t MINISLOT_AFTER_ACTION_POINT:6; /* gdMinislot - gdMinislotActionPointOffset - 1 */ - uint16_t NUMBER_OF_STATIC_SLOTS:10; /* gNumberOfStaticSlots */ - } B; - } FR_PCR2_16B_tag; - - typedef union { /* Protocol Configuration Register 3 */ - uint16_t R; - struct { - uint16_t WAKEUP_SYMBOL_RX_LOW:6; /* gdWakeupSymbolRxLow */ -#ifndef USE_FIELD_ALIASES_FR - uint16_t MINISLOT_ACTION_POINT_OFFSET_4_0:5; /* gdMinislotActionPointOffset - 1 */ -#else - uint16_t MINISLOT_ACTION_POINT_OFFSET:5; /* deprecated name - please avoid */ -#endif - uint16_t COLDSTART_ATTEMPTS:5; /* gColdstartAttempts */ - } B; - } FR_PCR3_16B_tag; - - typedef union { /* Protocol Configuration Register 4 */ - uint16_t R; - struct { - uint16_t CAS_RX_LOW_MAX:7; /* gdCASRxLowMax - 1 */ - uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; /* gdWakeupSymbolRxWindow */ - } B; - } FR_PCR4_16B_tag; - - typedef union { /* Protocol Configuration Register 5 */ - uint16_t R; - struct { - uint16_t TSS_TRANSMITTER:4; /* gdTSSTransmitter */ - uint16_t WAKEUP_SYMBOL_TX_LOW:6; /* gdWakeupSymbolTxLow */ - uint16_t WAKEUP_SYMBOL_RX_IDLE:6; /* gdWakeupSymbolRxIdle */ - } B; - } FR_PCR5_16B_tag; - - typedef union { /* Protocol Configuration Register 6 */ - uint16_t R; - struct { - uint16_t:1; - uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; /* gdSymbolWindow - gdActionPointOffset - 1 */ - uint16_t MACRO_INITIAL_OFFSET_A:7; /* pMacroInitialOffset[A] */ - } B; - } FR_PCR6_16B_tag; - - typedef union { /* Protocol Configuration Register 7 */ - uint16_t R; - struct { - uint16_t DECODING_CORRECTION_B:9; /* pDecodingCorrection + pDelayCompensation[B] + 2 */ - uint16_t MICRO_PER_MACRO_NOM_HALF:7; /* round(pMicroPerMacroNom / 2) */ - } B; - } FR_PCR7_16B_tag; - - typedef union { /* Protocol Configuration Register 8 */ - uint16_t R; - struct { - uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; /* gMaxWithoutClockCorrectionFatal */ - uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; /* gMaxWithoutClockCorrectionPassive */ - uint16_t WAKEUP_SYMBOL_TX_IDLE:8; /* gdWakeupSymbolTxIdle */ - } B; - } FR_PCR8_16B_tag; - - typedef union { /* Protocol Configuration Register 9 */ - uint16_t R; - struct { - uint16_t MINISLOT_EXISTS:1; /* gNumberOfMinislots!=0 */ - uint16_t SYMBOL_WINDOW_EXISTS:1; /* gdSymbolWindow!=0 */ - uint16_t OFFSET_CORRECTION_OUT:14; /* pOffsetCorrectionOut */ - } B; - } FR_PCR9_16B_tag; - - typedef union { /* Protocol Configuration Register 10 */ - uint16_t R; - struct { - uint16_t SINGLE_SLOT_ENABLED:1; /* pSingleSlotEnabled */ - uint16_t WAKEUP_CHANNEL:1; /* pWakeupChannel */ - uint16_t MACRO_PER_CYCLE:14; /* pMicroPerCycle */ - } B; - } FR_PCR10_16B_tag; - - typedef union { /* Protocol Configuration Register 11 */ - uint16_t R; - struct { - uint16_t KEY_SLOT_USED_FOR_STARTUP:1; /* pKeySlotUsedForStartup */ - uint16_t KEY_SLOT_USED_FOR_SYNC:1; /* pKeySlotUsedForSync */ - uint16_t OFFSET_CORRECTION_START:14; /* gOffsetCorrectionStart */ - } B; - } FR_PCR11_16B_tag; - - typedef union { /* Protocol Configuration Register 12 */ - uint16_t R; - struct { - uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; /* pAllowPassiveToActive */ - uint16_t KEY_SLOT_HEADER_CRC:11; /* header CRC for key slot */ - } B; - } FR_PCR12_16B_tag; - - typedef union { /* Protocol Configuration Register 13 */ - uint16_t R; - struct { - uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; /* max(gdActionPointOffset,gdMinislotActionPointOffset) - 1 */ - uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; /* gdStaticSlot - gdActionPointOffset - 1 */ - } B; - } FR_PCR13_16B_tag; - - typedef union { /* Protocol Configuration Register 14 */ - uint16_t R; - struct { - uint16_t RATE_CORRECTION_OUT:11; /* pRateCorrectionOut */ -#ifndef USE_FIELD_ALIASES_FR - uint16_t LISTEN_TIMEOUT_20_16:5; /* pdListenTimeout - 1 */ -#else - uint16_t LISTEN_TIMEOUT_H:5; /* deprecated name - please avoid */ -#endif - } B; - } FR_PCR14_16B_tag; - - typedef union { /* Protocol Configuration Register 15 */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_FR - uint16_t LISTEN_TIMEOUT_15_0:16; /* pdListenTimeout - 1 */ -#else - uint16_t LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */ -#endif - } B; - } FR_PCR15_16B_tag; - - typedef union { /* Protocol Configuration Register 16 */ - uint16_t R; - struct { - uint16_t MACRO_INITIAL_OFFSET_B:7; /* pMacroInitialOffset[B] */ -#ifndef USE_FIELD_ALIASES_FR - uint16_t NOISE_LISTEN_TIMEOUT_24_16:9; /* (gListenNoise * pdListenTimeout) - 1 */ -#else - uint16_t NOISE_LISTEN_TIMEOUT_H:9; /* deprecated name - please avoid */ -#endif - } B; - } FR_PCR16_16B_tag; - - typedef union { /* Protocol Configuration Register 17 */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_FR - uint16_t NOISE_LISTEN_TIMEOUT_15_0:16; /* (gListenNoise * pdListenTimeout) - 1 */ -#else - uint16_t NOISE_LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */ -#endif - } B; - } FR_PCR17_16B_tag; - - typedef union { /* Protocol Configuration Register 18 */ - uint16_t R; - struct { - uint16_t WAKEUP_PATTERN:6; /* pWakeupPattern */ - uint16_t KEY_SLOT_ID:10; /* pKeySlotId */ - } B; - } FR_PCR18_16B_tag; - - typedef union { /* Protocol Configuration Register 19 */ - uint16_t R; - struct { - uint16_t DECODING_CORRECTION_A:9; /* pDecodingCorrection + pDelayCompensation[A] + 2 */ - uint16_t PAYLOAD_LENGTH_STATIC:7; /* gPayloadLengthStatic */ - } B; - } FR_PCR19_16B_tag; - - typedef union { /* Protocol Configuration Register 20 */ - uint16_t R; - struct { - uint16_t MICRO_INITIAL_OFFSET_B:8; /* pMicroInitialOffset[B] */ - uint16_t MICRO_INITIAL_OFFSET_A:8; /* pMicroInitialOffset[A] */ - } B; - } FR_PCR20_16B_tag; - - typedef union { /* Protocol Configuration Register 21 */ - uint16_t R; - struct { - uint16_t EXTERN_RATE_CORRECTION:3; /* pExternRateCorrection */ - uint16_t LATEST_TX:13; /* gNumberOfMinislots - pLatestTx */ - } B; - } FR_PCR21_16B_tag; - - typedef union { /* Protocol Configuration Register 22 */ - uint16_t R; - struct { - uint16_t R:1; /* Reserved bit */ -#ifndef USE_FIELD_ALIASES_FR - uint16_t COMP_ACCEPTED_STARRUP_RANGE_A:11; /* pdAcceptedStartupRange - pDelayCompensationChA */ -#else - uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t MICRO_PER_CYCLE_19_16:4; /* gMicroPerCycle */ -#else - uint16_t MICRO_PER_CYCLE_H:4; /* deprecated name - please avoid */ -#endif - } B; - } FR_PCR22_16B_tag; - - typedef union { /* Protocol Configuration Register 23 */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_FR - uint16_t MICRO_PER_CYCLE_15_0:16; /* pMicroPerCycle */ -#else - uint16_t micro_per_cycle_l:16; /* deprecated name - please avoid */ -#endif - } B; - } FR_PCR23_16B_tag; - - typedef union { /* Protocol Configuration Register 24 */ - uint16_t R; - struct { - uint16_t CLUSTER_DRIFT_DAMPING:5; /* pClusterDriftDamping */ - uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; /* pPayloadLengthDynMax */ -#ifndef USE_FIELD_ALIASES_FR - uint16_t MICRO_PER_CYCLE_MIN_19_16:4; /* pMicroPerCycle - pdMaxDrift */ -#else - uint16_t MICRO_PER_CYCLE_MIN_H:4; /* deprecated name - please avoid */ -#endif - } B; - } FR_PCR24_16B_tag; - - typedef union { /* Protocol Configuration Register 25 */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_FR - uint16_t MICRO_PER_CYCLE_MIN_15_0:16; /* pMicroPerCycle - pdMaxDrift */ -#else - uint16_t MICRO_PER_CYCLE_MIN_L:16; /* deprecated name - please avoid */ -#endif - } B; - } FR_PCR25_16B_tag; - - typedef union { /* Protocol Configuration Register 26 */ - uint16_t R; - struct { - uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; /* pAllowHaltDueToClock */ - uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; /* pdAcceptedStartupRange - pDelayCompensationChB */ -#ifndef USE_FIELD_ALIASES_FR - uint16_t MICRO_PER_CYCLE_MAX_19_16:4; /* pMicroPerCycle + pdMaxDrift */ -#else - uint16_t MICRO_PER_CYCLE_MAX_H:4; /* deprecated name - please avoid */ -#endif - } B; - } FR_PCR26_16B_tag; - - typedef union { /* Protocol Configuration Register 27 */ - uint16_t R; - struct { -#ifndef USE_FIELD_ALIASES_FR - uint16_t MICRO_PER_CYCLE_MAX_15_0:16; /* pMicroPerCycle + pdMaxDrift */ -#else - uint16_t MICRO_PER_CYCLE_MAX_L:16; /* deprecated name - please avoid */ -#endif - } B; - } FR_PCR27_16B_tag; - - typedef union { /* Protocol Configuration Register 28 */ - uint16_t R; - struct { - uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; /* gdDynamicSlotIdlePhase */ - uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; /* gMacroPerCycle - gOffsetCorrectionStart */ - } B; - } FR_PCR28_16B_tag; - - typedef union { /* Protocol Configuration Register 29 */ - uint16_t R; - struct { - uint16_t EXTERN_OFFSET_CORRECTION:3; /* pExternOffsetCorrection */ - uint16_t MINISLOTS_MAX:13; /* gNumberOfMinislots - 1 */ - } B; - } FR_PCR29_16B_tag; - - typedef union { /* Protocol Configuration Register 30 */ - uint16_t R; - struct { - uint16_t:12; - uint16_t SYNC_NODE_MAX:4; /* gSyncNodeMax */ - } B; - } FR_PCR30_16B_tag; - - typedef union { /* Receive FIFO System Memory Base Address High Register */ - uint16_t R; - struct { - uint16_t SMBA_31_16:16; /* System Memory Base Address */ - } B; - } FR_RFSYMBHADR_16B_tag; - - typedef union { /* Receive FIFO System Memory Base Address Low Register */ - uint16_t R; - struct { - uint16_t:4; - uint16_t SMBA_15_4:12; /* System Memory Base Address */ - } B; - } FR_RFSYMBLADR_16B_tag; - - typedef union { /* Receive FIFO Periodic Timer Register */ - uint16_t R; - struct { - uint16_t:2; - uint16_t PTD:14; /* Periodic Timer Duration */ - } B; - } FR_RFPTR_16B_tag; - - typedef union { /* Receive FIFO Fill Level and Pop Count Register */ - uint16_t R; - struct { - uint16_t FLPCB:8; /* Fill Level and Pop Count Channel B */ - uint16_t FLPCA:8; /* Fill Level and Pop Count Channel A */ - } B; - } FR_RFFLPCR_16B_tag; - - typedef union { /* ECC Error Interrupt Flag and Enable Register */ - uint16_t R; - struct { - uint16_t LRNE_OF:1; /* LRAM Non-Corrected Error Overflow Flag */ - uint16_t LRCE_OF:1; /* LRAM Corrected Error Overflow Flag */ - uint16_t DRNE_OF:1; /* DRAM Non-Corrected Error Overflow Flag */ - uint16_t DRCE_OF:1; /* DRAM Corrected Error Overflow Flag */ - uint16_t LRNE_IF:1; /* LRAM Non-Corrected Error Interrupt Flag */ - uint16_t LRCE_IF:1; /* LRAM Corrected Error Interrupt Flag */ - uint16_t DRNE_IF:1; /* DRAM Non-Corrected Error Interrupt Flag */ - uint16_t DRCE_IF:1; /* DRAM Corrected Error Interrupt Flag */ - uint16_t:4; - uint16_t LRNE_IE:1; /* LRAM Non-Corrected Error Interrupt Enable */ - uint16_t LRCE_IE:1; /* LRAM Corrected Error Interrupt Enable */ - uint16_t DRNE_IE:1; /* DRAM Non-Corrected Error Interrupt Enable */ - uint16_t DRCE_IE:1; /* DRAM Corrected Error Interrupt Enable */ - } B; - } FR_EEIFER_16B_tag; - - typedef union { /* ECC Error Report and Injection Control Register */ - uint16_t R; - struct { - uint16_t BSY:1; /* Register Update Busy */ - uint16_t:5; - uint16_t ERS:2; /* Error Report Select */ - uint16_t:3; - uint16_t ERM:1; /* Error Report Mode */ - uint16_t:2; - uint16_t EIM:1; /* Error Injection Mode */ - uint16_t EIE:1; /* Error Injection Enable */ - } B; - } FR_EERICR_16B_tag; - - typedef union { /* ECC Error Report Adress Register */ - uint16_t R; - struct { - uint16_t MID:1; /* Memory Identifier */ - uint16_t BANK:3; /* Memory Bank */ - uint16_t ADDR:12; /* Memory Address */ - } B; - } FR_EERAR_16B_tag; - - typedef union { /* ECC Error Report Data Register */ - uint16_t R; - struct { - uint16_t DATA:16; /* Data */ - } B; - } FR_EERDR_16B_tag; - - typedef union { /* ECC Error Report Code Register */ - uint16_t R; - struct { - uint16_t:11; - uint16_t CODE:5; /* Code */ - } B; - } FR_EERCR_16B_tag; - - typedef union { /* ECC Error Injection Address Register */ - uint16_t R; - struct { - uint16_t MID:1; /* Memory Identifier */ - uint16_t BANK:3; /* Memory Bank */ - uint16_t ADDR:12; /* Memory Address */ - } B; - } FR_EEIAR_16B_tag; - - typedef union { /* ECC Error Injection Data Register */ - uint16_t R; - struct { - uint16_t DATA:16; /* Data */ - } B; - } FR_EEIDR_16B_tag; - - typedef union { /* ECC Error Injection Code Register */ - uint16_t R; - struct { - uint16_t:11; - uint16_t CODE:5; /* Code */ - } B; - } FR_EEICR_16B_tag; - - - /* Register layout for all registers MBCCSR... */ - - typedef union { /* Message Buffer Configuration Control Status Register */ - uint16_t R; - struct { - uint16_t:1; - uint16_t MCM:1; /* Message Buffer Commit Mode */ - uint16_t MBT:1; /* Message Buffer Type */ - uint16_t MTD:1; /* Message Buffer Transfer Direction */ - uint16_t CMT:1; /* Commit for Transmission */ - uint16_t EDT:1; /* Enable/Disable Trigger */ - uint16_t LCKT:1; /* Lock/Unlock Trigger */ - uint16_t MBIE:1; /* Message Buffer Interrupt Enable */ - uint16_t:3; - uint16_t DUP:1; /* Data Updated */ - uint16_t DVAL:1; /* DataValid */ - uint16_t EDS:1; /* Enable/Disable Status */ - uint16_t LCKS:1; /* LockStatus */ - uint16_t MBIF:1; /* Message Buffer Interrupt Flag */ - } B; - } FR_MBCCSR_16B_tag; - - - /* Register layout for all registers MBCCFR... */ - - typedef union { /* Message Buffer Cycle Counter Filter Register */ - uint16_t R; - struct { - uint16_t MTM:1; /* Message Buffer Transmission Mode */ -#ifndef USE_FIELD_ALIASES_FR - uint16_t CHA:1; /* Channel Assignment */ -#else - uint16_t CHNLA:1; /* deprecated name - please avoid */ -#endif -#ifndef USE_FIELD_ALIASES_FR - uint16_t CHB:1; /* Channel Assignment */ -#else - uint16_t CHNLB:1; /* deprecated name - please avoid */ -#endif - uint16_t CCFE:1; /* Cycle Counter Filtering Enable */ - uint16_t CCFMSK:6; /* Cycle Counter Filtering Mask */ - uint16_t CCFVAL:6; /* Cycle Counter Filtering Value */ - } B; - } FR_MBCCFR_16B_tag; - - - /* Register layout for all registers MBFIDR... */ - - typedef union { /* Message Buffer Frame ID Register */ - uint16_t R; - struct { - uint16_t:5; - uint16_t FID:11; /* Frame ID */ - } B; - } FR_MBFIDR_16B_tag; - - - /* Register layout for all registers MBIDXR... */ - - typedef union { /* Message Buffer Index Register */ - uint16_t R; - struct { - uint16_t:9; - uint16_t MBIDX:7; /* Message Buffer Index */ - } B; - } FR_MBIDXR_16B_tag; - - - /* Register layout for generated register(s) NMVR... */ - - typedef union { /* */ - uint16_t R; - } FR_NMVR_16B_tag; - - - - - /* Register layout for generated register(s) SSCR... */ - - typedef union { /* */ - uint16_t R; - } FR_SSCR_16B_tag; - - - typedef struct FR_MB_struct_tag { - - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR; /* relative offset: 0x0000 */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR; /* relative offset: 0x0002 */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR; /* relative offset: 0x0004 */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR; /* relative offset: 0x0006 */ - - } FR_MB_tag; - - - typedef struct FR_struct_tag { /* start of FR_tag */ - /* Module Version Number */ - FR_MVR_16B_tag MVR; /* offset: 0x0000 size: 16 bit */ - /* Module Configuration Register */ - FR_MCR_16B_tag MCR; /* offset: 0x0002 size: 16 bit */ - union { - FR_SYMBADHR_16B_tag SYSBADHR; /* deprecated - please avoid */ - - /* SYSTEM MEMORY BASE ADD HIGH REG */ - FR_SYMBADHR_16B_tag SYMBADHR; /* offset: 0x0004 size: 16 bit */ - - }; - union { - FR_SYMBADLR_16B_tag SYSBADLR; /* deprecated - please avoid */ - - /* SYSTEM MEMORY BASE ADD LOW REG */ - FR_SYMBADLR_16B_tag SYMBADLR; /* offset: 0x0006 size: 16 bit */ - - }; - /* STROBE SIGNAL CONTROL REGISTER */ - FR_STBSCR_16B_tag STBSCR; /* offset: 0x0008 size: 16 bit */ - int8_t FR_reserved_000A[2]; - /* MESSAGE BUFFER DATA SIZE REGISTER */ - FR_MBDSR_16B_tag MBDSR; /* offset: 0x000C size: 16 bit */ - /* MESS. BUFFER SEG. SIZE & UTILISATION REG */ - FR_MBSSUTR_16B_tag MBSSUTR; /* offset: 0x000E size: 16 bit */ - union { - /* PE DRAM ACCESS REGISTER */ - FR_PEDRAR_16B_tag PEDRAR; /* offset: 0x0010 size: 16 bit */ - - FR_PEDRAR_16B_tag PADR; /* deprecated - please avoid */ - - }; - union { - /* PE DRAM DATA REGISTER */ - FR_PEDRDR_16B_tag PEDRDR; /* offset: 0x0012 size: 16 bit */ - - FR_PEDRDR_16B_tag PDAR; /* deprecated - please avoid */ - - }; - /* PROTOCOL OPERATION CONTROL REG */ - FR_POCR_16B_tag POCR; /* offset: 0x0014 size: 16 bit */ - /* GLOBAL INTERRUPT FLAG & ENABLE REG */ - FR_GIFER_16B_tag GIFER; /* offset: 0x0016 size: 16 bit */ - /* PROTOCOL INTERRUPT FLAG REGISTER 0 */ - FR_PIFR0_16B_tag PIFR0; /* offset: 0x0018 size: 16 bit */ - /* PROTOCOL INTERRUPT FLAG REGISTER 1 */ - FR_PIFR1_16B_tag PIFR1; /* offset: 0x001A size: 16 bit */ - /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */ - FR_PIER0_16B_tag PIER0; /* offset: 0x001C size: 16 bit */ - /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */ - FR_PIER1_16B_tag PIER1; /* offset: 0x001E size: 16 bit */ - /* CHI ERROR FLAG REGISTER */ - FR_CHIERFR_16B_tag CHIERFR; /* offset: 0x0020 size: 16 bit */ - /* Message Buffer Interrupt Vector Register */ - FR_MBIVEC_16B_tag MBIVEC; /* offset: 0x0022 size: 16 bit */ - /* Channel A Status Error Counter Register */ - FR_CASERCR_16B_tag CASERCR; /* offset: 0x0024 size: 16 bit */ - /* Channel B Status Error Counter Register */ - FR_CBSERCR_16B_tag CBSERCR; /* offset: 0x0026 size: 16 bit */ - /* Protocol Status Register 0 */ - FR_PSR0_16B_tag PSR0; /* offset: 0x0028 size: 16 bit */ - /* Protocol Status Register 1 */ - FR_PSR1_16B_tag PSR1; /* offset: 0x002A size: 16 bit */ - /* Protocol Status Register 2 */ - FR_PSR2_16B_tag PSR2; /* offset: 0x002C size: 16 bit */ - /* Protocol Status Register 3 */ - FR_PSR3_16B_tag PSR3; /* offset: 0x002E size: 16 bit */ - /* Macrotick Counter Register */ - FR_MTCTR_16B_tag MTCTR; /* offset: 0x0030 size: 16 bit */ - /* Cycle Counter Register */ - FR_CYCTR_16B_tag CYCTR; /* offset: 0x0032 size: 16 bit */ - /* Slot Counter Channel A Register */ - FR_SLTCTAR_16B_tag SLTCTAR; /* offset: 0x0034 size: 16 bit */ - /* Slot Counter Channel B Register */ - FR_SLTCTBR_16B_tag SLTCTBR; /* offset: 0x0036 size: 16 bit */ - /* Rate Correction Value Register */ - FR_RTCORVR_16B_tag RTCORVR; /* offset: 0x0038 size: 16 bit */ - /* Offset Correction Value Register */ - FR_OFCORVR_16B_tag OFCORVR; /* offset: 0x003A size: 16 bit */ - union { - FR_CIFR_16B_tag CIFRR; /* deprecated - please avoid */ - - /* Combined Interrupt Flag Register */ - FR_CIFR_16B_tag CIFR; /* offset: 0x003C size: 16 bit */ - - }; - /* System Memory Access Time-Out Register */ - FR_SYMATOR_16B_tag SYMATOR; /* offset: 0x003E size: 16 bit */ - /* Sync Frame Counter Register */ - FR_SFCNTR_16B_tag SFCNTR; /* offset: 0x0040 size: 16 bit */ - /* Sync Frame Table Offset Register */ - FR_SFTOR_16B_tag SFTOR; /* offset: 0x0042 size: 16 bit */ - /* Sync Frame Table Configuration, Control, Status Register */ - FR_SFTCCSR_16B_tag SFTCCSR; /* offset: 0x0044 size: 16 bit */ - /* Sync Frame ID Rejection Filter */ - FR_SFIDRFR_16B_tag SFIDRFR; /* offset: 0x0046 size: 16 bit */ - /* Sync Frame ID Acceptance Filter Value Register */ - FR_SFIDAFVR_16B_tag SFIDAFVR; /* offset: 0x0048 size: 16 bit */ - /* Sync Frame ID Acceptance Filter Mask Register */ - FR_SFIDAFMR_16B_tag SFIDAFMR; /* offset: 0x004A size: 16 bit */ - union { - FR_NMVR_16B_tag NMVR[6]; /* offset: 0x004C (0x0002 x 6) */ - - struct { - /* Network Management Vector Register0 */ - FR_NMVR0_16B_tag NMVR0; /* offset: 0x004C size: 16 bit */ - /* Network Management Vector Register1 */ - FR_NMVR1_16B_tag NMVR1; /* offset: 0x004E size: 16 bit */ - /* Network Management Vector Register2 */ - FR_NMVR2_16B_tag NMVR2; /* offset: 0x0050 size: 16 bit */ - /* Network Management Vector Register3 */ - FR_NMVR3_16B_tag NMVR3; /* offset: 0x0052 size: 16 bit */ - /* Network Management Vector Register4 */ - FR_NMVR4_16B_tag NMVR4; /* offset: 0x0054 size: 16 bit */ - /* Network Management Vector Register5 */ - FR_NMVR5_16B_tag NMVR5; /* offset: 0x0056 size: 16 bit */ - }; - - }; - /* Network Management Vector Length Register */ - FR_NMVLR_16B_tag NMVLR; /* offset: 0x0058 size: 16 bit */ - /* Timer Configuration and Control Register */ - FR_TICCR_16B_tag TICCR; /* offset: 0x005A size: 16 bit */ - /* Timer 1 Cycle Set Register */ - FR_TI1CYSR_16B_tag TI1CYSR; /* offset: 0x005C size: 16 bit */ - union { - /* Timer 1 Macrotick Offset Register */ - FR_TI1MTOR_16B_tag TI1MTOR; /* offset: 0x005E size: 16 bit */ - - FR_TI1MTOR_16B_tag T1MTOR; /* deprecated - please avoid */ - - }; - /* Timer 2 Configuration Register 0 */ - FR_TI2CR0_16B_tag TI2CR0; /* offset: 0x0060 size: 16 bit */ - /* Timer 2 Configuration Register 1 */ - FR_TI2CR1_16B_tag TI2CR1; /* offset: 0x0062 size: 16 bit */ - /* Slot Status Selection Register */ - FR_SSSR_16B_tag SSSR; /* offset: 0x0064 size: 16 bit */ - /* Slot Status Counter Condition Register */ - FR_SSCCR_16B_tag SSCCR; /* offset: 0x0066 size: 16 bit */ - union { - FR_SSR_16B_tag SSR[8]; /* offset: 0x0068 (0x0002 x 8) */ - - struct { - /* Slot Status Register0 */ - FR_SSR_16B_tag SSR0; /* offset: 0x0068 size: 16 bit */ - /* Slot Status Register1 */ - FR_SSR_16B_tag SSR1; /* offset: 0x006A size: 16 bit */ - /* Slot Status Register2 */ - FR_SSR_16B_tag SSR2; /* offset: 0x006C size: 16 bit */ - /* Slot Status Register3 */ - FR_SSR_16B_tag SSR3; /* offset: 0x006E size: 16 bit */ - /* Slot Status Register4 */ - FR_SSR_16B_tag SSR4; /* offset: 0x0070 size: 16 bit */ - /* Slot Status Register5 */ - FR_SSR_16B_tag SSR5; /* offset: 0x0072 size: 16 bit */ - /* Slot Status Register6 */ - FR_SSR_16B_tag SSR6; /* offset: 0x0074 size: 16 bit */ - /* Slot Status Register7 */ - FR_SSR_16B_tag SSR7; /* offset: 0x0076 size: 16 bit */ - }; - - }; - union { - FR_SSCR_16B_tag SSCR[4]; /* offset: 0x0078 (0x0002 x 4) */ - - struct { - /* Slot Status Counter Register0 */ - FR_SSCR0_16B_tag SSCR0; /* offset: 0x0078 size: 16 bit */ - /* Slot Status Counter Register1 */ - FR_SSCR1_16B_tag SSCR1; /* offset: 0x007A size: 16 bit */ - /* Slot Status Counter Register2 */ - FR_SSCR2_16B_tag SSCR2; /* offset: 0x007C size: 16 bit */ - /* Slot Status Counter Register3 */ - FR_SSCR3_16B_tag SSCR3; /* offset: 0x007E size: 16 bit */ - }; - - }; - /* MTS A Configuration Register */ - FR_MTSACFR_16B_tag MTSACFR; /* offset: 0x0080 size: 16 bit */ - /* MTS B Configuration Register */ - FR_MTSBCFR_16B_tag MTSBCFR; /* offset: 0x0082 size: 16 bit */ - /* Receive Shadow Buffer Index Register */ - FR_RSBIR_16B_tag RSBIR; /* offset: 0x0084 size: 16 bit */ - union { - /* Receive FIFO Watermark and Selection Register */ - FR_RFWMSR_16B_tag RFWMSR; /* offset: 0x0086 size: 16 bit */ - - FR_RFWMSR_16B_tag RFSR; /* deprecated - please avoid */ - - }; - union { - FR_RF_RFSIR_16B_tag RFSIR; /* deprecated - please avoid */ - - /* Receive FIFO Start Index Register */ - FR_RF_RFSIR_16B_tag RF_RFSIR; /* offset: 0x0088 size: 16 bit */ - - }; - /* Receive FIFO Depth and Size Register */ - FR_RFDSR_16B_tag RFDSR; /* offset: 0x008A size: 16 bit */ - /* Receive FIFO A Read Index Register */ - FR_RFARIR_16B_tag RFARIR; /* offset: 0x008C size: 16 bit */ - /* Receive FIFO B Read Index Register */ - FR_RFBRIR_16B_tag RFBRIR; /* offset: 0x008E size: 16 bit */ - /* Receive FIFO Message ID Acceptance Filter Value Register */ - FR_RFMIDAFVR_16B_tag RFMIDAFVR; /* offset: 0x0090 size: 16 bit */ - union { - /* Receive FIFO Message ID Acceptance Filter Mask Register */ - FR_RFMIDAFMR_16B_tag RFMIDAFMR; /* offset: 0x0092 size: 16 bit */ - - FR_RFMIDAFMR_16B_tag RFMIAFMR; /* deprecated - please avoid */ - - }; - /* Receive FIFO Frame ID Rejection Filter Value Register */ - FR_RFFIDRFVR_16B_tag RFFIDRFVR; /* offset: 0x0094 size: 16 bit */ - /* Receive FIFO Frame ID Rejection Filter Mask Register */ - FR_RFFIDRFMR_16B_tag RFFIDRFMR; /* offset: 0x0096 size: 16 bit */ - /* Receive FIFO Range Filter Configuration Register */ - FR_RFRFCFR_16B_tag RFRFCFR; /* offset: 0x0098 size: 16 bit */ - /* Receive FIFO Range Filter Control Register */ - FR_RFRFCTR_16B_tag RFRFCTR; /* offset: 0x009A size: 16 bit */ - /* Last Dynamic Transmit Slot Channel A Register */ - FR_LDTXSLAR_16B_tag LDTXSLAR; /* offset: 0x009C size: 16 bit */ - /* Last Dynamic Transmit Slot Channel B Register */ - FR_LDTXSLBR_16B_tag LDTXSLBR; /* offset: 0x009E size: 16 bit */ - /* Protocol Configuration Register 0 */ - FR_PCR0_16B_tag PCR0; /* offset: 0x00A0 size: 16 bit */ - /* Protocol Configuration Register 1 */ - FR_PCR1_16B_tag PCR1; /* offset: 0x00A2 size: 16 bit */ - /* Protocol Configuration Register 2 */ - FR_PCR2_16B_tag PCR2; /* offset: 0x00A4 size: 16 bit */ - /* Protocol Configuration Register 3 */ - FR_PCR3_16B_tag PCR3; /* offset: 0x00A6 size: 16 bit */ - /* Protocol Configuration Register 4 */ - FR_PCR4_16B_tag PCR4; /* offset: 0x00A8 size: 16 bit */ - /* Protocol Configuration Register 5 */ - FR_PCR5_16B_tag PCR5; /* offset: 0x00AA size: 16 bit */ - /* Protocol Configuration Register 6 */ - FR_PCR6_16B_tag PCR6; /* offset: 0x00AC size: 16 bit */ - /* Protocol Configuration Register 7 */ - FR_PCR7_16B_tag PCR7; /* offset: 0x00AE size: 16 bit */ - /* Protocol Configuration Register 8 */ - FR_PCR8_16B_tag PCR8; /* offset: 0x00B0 size: 16 bit */ - /* Protocol Configuration Register 9 */ - FR_PCR9_16B_tag PCR9; /* offset: 0x00B2 size: 16 bit */ - /* Protocol Configuration Register 10 */ - FR_PCR10_16B_tag PCR10; /* offset: 0x00B4 size: 16 bit */ - /* Protocol Configuration Register 11 */ - FR_PCR11_16B_tag PCR11; /* offset: 0x00B6 size: 16 bit */ - /* Protocol Configuration Register 12 */ - FR_PCR12_16B_tag PCR12; /* offset: 0x00B8 size: 16 bit */ - /* Protocol Configuration Register 13 */ - FR_PCR13_16B_tag PCR13; /* offset: 0x00BA size: 16 bit */ - /* Protocol Configuration Register 14 */ - FR_PCR14_16B_tag PCR14; /* offset: 0x00BC size: 16 bit */ - /* Protocol Configuration Register 15 */ - FR_PCR15_16B_tag PCR15; /* offset: 0x00BE size: 16 bit */ - /* Protocol Configuration Register 16 */ - FR_PCR16_16B_tag PCR16; /* offset: 0x00C0 size: 16 bit */ - /* Protocol Configuration Register 17 */ - FR_PCR17_16B_tag PCR17; /* offset: 0x00C2 size: 16 bit */ - /* Protocol Configuration Register 18 */ - FR_PCR18_16B_tag PCR18; /* offset: 0x00C4 size: 16 bit */ - /* Protocol Configuration Register 19 */ - FR_PCR19_16B_tag PCR19; /* offset: 0x00C6 size: 16 bit */ - /* Protocol Configuration Register 20 */ - FR_PCR20_16B_tag PCR20; /* offset: 0x00C8 size: 16 bit */ - /* Protocol Configuration Register 21 */ - FR_PCR21_16B_tag PCR21; /* offset: 0x00CA size: 16 bit */ - /* Protocol Configuration Register 22 */ - FR_PCR22_16B_tag PCR22; /* offset: 0x00CC size: 16 bit */ - /* Protocol Configuration Register 23 */ - FR_PCR23_16B_tag PCR23; /* offset: 0x00CE size: 16 bit */ - /* Protocol Configuration Register 24 */ - FR_PCR24_16B_tag PCR24; /* offset: 0x00D0 size: 16 bit */ - /* Protocol Configuration Register 25 */ - FR_PCR25_16B_tag PCR25; /* offset: 0x00D2 size: 16 bit */ - /* Protocol Configuration Register 26 */ - FR_PCR26_16B_tag PCR26; /* offset: 0x00D4 size: 16 bit */ - /* Protocol Configuration Register 27 */ - FR_PCR27_16B_tag PCR27; /* offset: 0x00D6 size: 16 bit */ - /* Protocol Configuration Register 28 */ - FR_PCR28_16B_tag PCR28; /* offset: 0x00D8 size: 16 bit */ - /* Protocol Configuration Register 29 */ - FR_PCR29_16B_tag PCR29; /* offset: 0x00DA size: 16 bit */ - /* Protocol Configuration Register 30 */ - FR_PCR30_16B_tag PCR30; /* offset: 0x00DC size: 16 bit */ - int8_t FR_reserved_00DE[10]; - /* Receive FIFO System Memory Base Address High Register */ - FR_RFSYMBHADR_16B_tag RFSYMBHADR; /* offset: 0x00E8 size: 16 bit */ - /* Receive FIFO System Memory Base Address Low Register */ - FR_RFSYMBLADR_16B_tag RFSYMBLADR; /* offset: 0x00EA size: 16 bit */ - /* Receive FIFO Periodic Timer Register */ - FR_RFPTR_16B_tag RFPTR; /* offset: 0x00EC size: 16 bit */ - /* Receive FIFO Fill Level and Pop Count Register */ - FR_RFFLPCR_16B_tag RFFLPCR; /* offset: 0x00EE size: 16 bit */ - /* ECC Error Interrupt Flag and Enable Register */ - FR_EEIFER_16B_tag EEIFER; /* offset: 0x00F0 size: 16 bit */ - /* ECC Error Report and Injection Control Register */ - FR_EERICR_16B_tag EERICR; /* offset: 0x00F2 size: 16 bit */ - /* ECC Error Report Adress Register */ - FR_EERAR_16B_tag EERAR; /* offset: 0x00F4 size: 16 bit */ - /* ECC Error Report Data Register */ - FR_EERDR_16B_tag EERDR; /* offset: 0x00F6 size: 16 bit */ - /* ECC Error Report Code Register */ - FR_EERCR_16B_tag EERCR; /* offset: 0x00F8 size: 16 bit */ - /* ECC Error Injection Address Register */ - FR_EEIAR_16B_tag EEIAR; /* offset: 0x00FA size: 16 bit */ - /* ECC Error Injection Data Register */ - FR_EEIDR_16B_tag EEIDR; /* offset: 0x00FC size: 16 bit */ - /* ECC Error Injection Code Register */ - FR_EEICR_16B_tag EEICR; /* offset: 0x00FE size: 16 bit */ - union { - /* Register set MB */ - FR_MB_tag MB[64]; /* offset: 0x0100 (0x0008 x 64) */ - - FR_MB_tag MBCCS[64]; /* offset: 0x0100 (0x0008 x 64) */ - - struct { - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR0; /* offset: 0x0100 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR0; /* offset: 0x0102 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR0; /* offset: 0x0104 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR0; /* offset: 0x0106 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR1; /* offset: 0x0108 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR1; /* offset: 0x010A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR1; /* offset: 0x010C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR1; /* offset: 0x010E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR2; /* offset: 0x0110 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR2; /* offset: 0x0112 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR2; /* offset: 0x0114 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR2; /* offset: 0x0116 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR3; /* offset: 0x0118 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR3; /* offset: 0x011A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR3; /* offset: 0x011C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR3; /* offset: 0x011E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR4; /* offset: 0x0120 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR4; /* offset: 0x0122 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR4; /* offset: 0x0124 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR4; /* offset: 0x0126 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR5; /* offset: 0x0128 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR5; /* offset: 0x012A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR5; /* offset: 0x012C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR5; /* offset: 0x012E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR6; /* offset: 0x0130 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR6; /* offset: 0x0132 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR6; /* offset: 0x0134 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR6; /* offset: 0x0136 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR7; /* offset: 0x0138 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR7; /* offset: 0x013A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR7; /* offset: 0x013C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR7; /* offset: 0x013E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR8; /* offset: 0x0140 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR8; /* offset: 0x0142 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR8; /* offset: 0x0144 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR8; /* offset: 0x0146 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR9; /* offset: 0x0148 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR9; /* offset: 0x014A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR9; /* offset: 0x014C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR9; /* offset: 0x014E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR10; /* offset: 0x0150 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR10; /* offset: 0x0152 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR10; /* offset: 0x0154 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR10; /* offset: 0x0156 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR11; /* offset: 0x0158 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR11; /* offset: 0x015A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR11; /* offset: 0x015C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR11; /* offset: 0x015E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR12; /* offset: 0x0160 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR12; /* offset: 0x0162 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR12; /* offset: 0x0164 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR12; /* offset: 0x0166 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR13; /* offset: 0x0168 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR13; /* offset: 0x016A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR13; /* offset: 0x016C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR13; /* offset: 0x016E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR14; /* offset: 0x0170 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR14; /* offset: 0x0172 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR14; /* offset: 0x0174 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR14; /* offset: 0x0176 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR15; /* offset: 0x0178 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR15; /* offset: 0x017A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR15; /* offset: 0x017C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR15; /* offset: 0x017E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR16; /* offset: 0x0180 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR16; /* offset: 0x0182 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR16; /* offset: 0x0184 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR16; /* offset: 0x0186 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR17; /* offset: 0x0188 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR17; /* offset: 0x018A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR17; /* offset: 0x018C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR17; /* offset: 0x018E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR18; /* offset: 0x0190 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR18; /* offset: 0x0192 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR18; /* offset: 0x0194 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR18; /* offset: 0x0196 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR19; /* offset: 0x0198 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR19; /* offset: 0x019A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR19; /* offset: 0x019C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR19; /* offset: 0x019E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR20; /* offset: 0x01A0 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR20; /* offset: 0x01A2 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR20; /* offset: 0x01A4 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR20; /* offset: 0x01A6 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR21; /* offset: 0x01A8 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR21; /* offset: 0x01AA size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR21; /* offset: 0x01AC size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR21; /* offset: 0x01AE size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR22; /* offset: 0x01B0 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR22; /* offset: 0x01B2 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR22; /* offset: 0x01B4 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR22; /* offset: 0x01B6 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR23; /* offset: 0x01B8 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR23; /* offset: 0x01BA size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR23; /* offset: 0x01BC size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR23; /* offset: 0x01BE size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR24; /* offset: 0x01C0 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR24; /* offset: 0x01C2 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR24; /* offset: 0x01C4 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR24; /* offset: 0x01C6 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR25; /* offset: 0x01C8 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR25; /* offset: 0x01CA size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR25; /* offset: 0x01CC size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR25; /* offset: 0x01CE size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR26; /* offset: 0x01D0 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR26; /* offset: 0x01D2 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR26; /* offset: 0x01D4 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR26; /* offset: 0x01D6 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR27; /* offset: 0x01D8 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR27; /* offset: 0x01DA size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR27; /* offset: 0x01DC size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR27; /* offset: 0x01DE size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR28; /* offset: 0x01E0 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR28; /* offset: 0x01E2 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR28; /* offset: 0x01E4 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR28; /* offset: 0x01E6 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR29; /* offset: 0x01E8 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR29; /* offset: 0x01EA size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR29; /* offset: 0x01EC size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR29; /* offset: 0x01EE size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR30; /* offset: 0x01F0 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR30; /* offset: 0x01F2 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR30; /* offset: 0x01F4 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR30; /* offset: 0x01F6 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR31; /* offset: 0x01F8 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR31; /* offset: 0x01FA size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR31; /* offset: 0x01FC size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR31; /* offset: 0x01FE size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR32; /* offset: 0x0200 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR32; /* offset: 0x0202 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR32; /* offset: 0x0204 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR32; /* offset: 0x0206 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR33; /* offset: 0x0208 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR33; /* offset: 0x020A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR33; /* offset: 0x020C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR33; /* offset: 0x020E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR34; /* offset: 0x0210 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR34; /* offset: 0x0212 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR34; /* offset: 0x0214 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR34; /* offset: 0x0216 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR35; /* offset: 0x0218 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR35; /* offset: 0x021A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR35; /* offset: 0x021C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR35; /* offset: 0x021E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR36; /* offset: 0x0220 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR36; /* offset: 0x0222 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR36; /* offset: 0x0224 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR36; /* offset: 0x0226 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR37; /* offset: 0x0228 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR37; /* offset: 0x022A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR37; /* offset: 0x022C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR37; /* offset: 0x022E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR38; /* offset: 0x0230 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR38; /* offset: 0x0232 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR38; /* offset: 0x0234 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR38; /* offset: 0x0236 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR39; /* offset: 0x0238 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR39; /* offset: 0x023A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR39; /* offset: 0x023C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR39; /* offset: 0x023E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR40; /* offset: 0x0240 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR40; /* offset: 0x0242 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR40; /* offset: 0x0244 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR40; /* offset: 0x0246 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR41; /* offset: 0x0248 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR41; /* offset: 0x024A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR41; /* offset: 0x024C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR41; /* offset: 0x024E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR42; /* offset: 0x0250 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR42; /* offset: 0x0252 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR42; /* offset: 0x0254 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR42; /* offset: 0x0256 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR43; /* offset: 0x0258 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR43; /* offset: 0x025A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR43; /* offset: 0x025C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR43; /* offset: 0x025E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR44; /* offset: 0x0260 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR44; /* offset: 0x0262 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR44; /* offset: 0x0264 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR44; /* offset: 0x0266 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR45; /* offset: 0x0268 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR45; /* offset: 0x026A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR45; /* offset: 0x026C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR45; /* offset: 0x026E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR46; /* offset: 0x0270 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR46; /* offset: 0x0272 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR46; /* offset: 0x0274 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR46; /* offset: 0x0276 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR47; /* offset: 0x0278 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR47; /* offset: 0x027A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR47; /* offset: 0x027C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR47; /* offset: 0x027E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR48; /* offset: 0x0280 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR48; /* offset: 0x0282 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR48; /* offset: 0x0284 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR48; /* offset: 0x0286 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR49; /* offset: 0x0288 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR49; /* offset: 0x028A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR49; /* offset: 0x028C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR49; /* offset: 0x028E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR50; /* offset: 0x0290 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR50; /* offset: 0x0292 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR50; /* offset: 0x0294 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR50; /* offset: 0x0296 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR51; /* offset: 0x0298 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR51; /* offset: 0x029A size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR51; /* offset: 0x029C size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR51; /* offset: 0x029E size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR52; /* offset: 0x02A0 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR52; /* offset: 0x02A2 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR52; /* offset: 0x02A4 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR52; /* offset: 0x02A6 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR53; /* offset: 0x02A8 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR53; /* offset: 0x02AA size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR53; /* offset: 0x02AC size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR53; /* offset: 0x02AE size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR54; /* offset: 0x02B0 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR54; /* offset: 0x02B2 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR54; /* offset: 0x02B4 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR54; /* offset: 0x02B6 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR55; /* offset: 0x02B8 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR55; /* offset: 0x02BA size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR55; /* offset: 0x02BC size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR55; /* offset: 0x02BE size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR56; /* offset: 0x02C0 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR56; /* offset: 0x02C2 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR56; /* offset: 0x02C4 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR56; /* offset: 0x02C6 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR57; /* offset: 0x02C8 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR57; /* offset: 0x02CA size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR57; /* offset: 0x02CC size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR57; /* offset: 0x02CE size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR58; /* offset: 0x02D0 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR58; /* offset: 0x02D2 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR58; /* offset: 0x02D4 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR58; /* offset: 0x02D6 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR59; /* offset: 0x02D8 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR59; /* offset: 0x02DA size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR59; /* offset: 0x02DC size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR59; /* offset: 0x02DE size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR60; /* offset: 0x02E0 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR60; /* offset: 0x02E2 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR60; /* offset: 0x02E4 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR60; /* offset: 0x02E6 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR61; /* offset: 0x02E8 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR61; /* offset: 0x02EA size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR61; /* offset: 0x02EC size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR61; /* offset: 0x02EE size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR62; /* offset: 0x02F0 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR62; /* offset: 0x02F2 size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR62; /* offset: 0x02F4 size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR62; /* offset: 0x02F6 size: 16 bit */ - /* Message Buffer Configuration Control Status Register */ - FR_MBCCSR_16B_tag MBCCSR63; /* offset: 0x02F8 size: 16 bit */ - /* Message Buffer Cycle Counter Filter Register */ - FR_MBCCFR_16B_tag MBCCFR63; /* offset: 0x02FA size: 16 bit */ - /* Message Buffer Frame ID Register */ - FR_MBFIDR_16B_tag MBFIDR63; /* offset: 0x02FC size: 16 bit */ - /* Message Buffer Index Register */ - FR_MBIDXR_16B_tag MBIDXR63; /* offset: 0x02FE size: 16 bit */ - }; - - }; - } FR_tag; - - -#define FR (*(volatile FR_tag *) 0xFFFE0000UL) - - - - - -#ifdef __MWERKS__ -#pragma pop -#endif - -#ifdef __cplusplus -} -#endif -#endif /* ASM */ -#endif /* _leopard_H_*/ - -/* End of file */ - diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc5668.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc5668.h deleted file mode 100644 index b7a1793dca..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc5668.h +++ /dev/null @@ -1,6721 +0,0 @@ -/* - * Modifications of the original file provided by Freescale are: - * - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/************************************************************************** - * FILE NAME: mpc5668.h COPYRIGHT (c) Freescale 2009 * - * REVISION: 1.1 All Rights Reserved * - * * - * DESCRIPTION: * - * This file contain all of the register and bit field definitions for * - * MPC5668. * - **************************************************************************/ -/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ - -/************************************************************************** - * Example register & bit field write: * - * * - * <MODULE>.<REGISTER>.B.<BIT> = 1; * - * <MODULE>.<REGISTER>.R = 0x10000000; * - * * - **************************************************************************/ - -#ifndef _MPC5668_H_ -#define _MPC5668_H_ - -#ifndef ASM - -#include <stdint.h> - -#include <mpc55xx/regs-edma.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __MWERKS__ -#pragma push -#pragma ANSI_strict off -#endif - -/*************************************************************************/ -/* MODULE : ADC */ -/*************************************************************************/ - struct ADC_tag { - - union { - uint32_t R; - struct { - uint32_t OWREN:1; - uint32_t WLSIDE:1; - uint32_t MODE:1; - uint32_t EDGLEV:1; - uint32_t TRGEN:1; - uint32_t EDGE:1; - uint32_t XSTRTEN:1; - uint32_t NSTART:1; - uint32_t:1; - uint32_t JTRGEN:1; - uint32_t JEDGE:1; - uint32_t JSTART:1; - uint32_t:2; - uint32_t CTUEN:1; - uint32_t:8; - uint32_t ADCLKSEL:1; - uint32_t ABORTCHAIN:1; - uint32_t ABORT:1; - uint32_t ACKO:1; - uint32_t OFFREFRESH:1; - uint32_t OFFCANC:1; - uint32_t:2; - uint32_t PWDN:1; - } B; - } MCR; /* MAIN CONFIGURATION REGISTER */ - - union { - uint32_t R; - struct { - uint32_t:7; - uint32_t NSTART:1; - uint32_t JABORT:1; - uint32_t:2; - uint32_t JSTART:1; - uint32_t:3; - uint32_t CTUSTART:1; - uint32_t CHADDR:7; - uint32_t:3; - uint32_t ACKO:1; - uint32_t OFFREFRESH:1; - uint32_t OFFCANC:1; - uint32_t ADCSTATUS:3; - } B; - } MSR; /* MAIN STATUS REGISTER */ - - uint32_t adc_reserved1[2]; - - union { - uint32_t R; - struct { - uint32_t:25; - uint32_t OFFCANCOVR:1; - uint32_t EOFFSET:1; - uint32_t EOCTU:1; - uint32_t JEOC:1; - uint32_t JECH:1; - uint32_t EOC:1; - uint32_t ECH:1; - } B; - } ISR; /* INTERRUPT STATUS REGISTER */ - - union { - uint32_t R; - struct { - uint32_t EOCCH31:1; - uint32_t EOCCH30:1; - uint32_t EOCCH29:1; - uint32_t EOCCH28:1; - uint32_t EOCCH27:1; - uint32_t EOCCH26:1; - uint32_t EOCCH25:1; - uint32_t EOCCH24:1; - uint32_t EOCCH23:1; - uint32_t EOCCH22:1; - uint32_t EOCCH21:1; - uint32_t EOCCH20:1; - uint32_t EOCCH19:1; - uint32_t EOCCH18:1; - uint32_t EOCCH17:1; - uint32_t EOCCH16:1; - uint32_t EOCCH15:1; - uint32_t EOCCH14:1; - uint32_t EOCCH13:1; - uint32_t EOCCH12:1; - uint32_t EOCCH11:1; - uint32_t EOCCH10:1; - uint32_t EOCCH9:1; - uint32_t EOCCH8:1; - uint32_t EOCCH7:1; - uint32_t EOCCH6:1; - uint32_t EOCCH5:1; - uint32_t EOCCH4:1; - uint32_t EOCCH3:1; - uint32_t EOCCH2:1; - uint32_t EOCCH1:1; - uint32_t EOCCH0:1; - } B; - } CEOCFR0; /* CHANNEL PENDING REGISTER 0 */ - - union { - uint32_t R; - struct { - uint32_t EOCCH63:1; - uint32_t EOCCH62:1; - uint32_t EOCCH61:1; - uint32_t EOCCH60:1; - uint32_t EOCCH59:1; - uint32_t EOCCH58:1; - uint32_t EOCCH57:1; - uint32_t EOCCH56:1; - uint32_t EOCCH55:1; - uint32_t EOCCH54:1; - uint32_t EOCCH53:1; - uint32_t EOCCH52:1; - uint32_t EOCCH51:1; - uint32_t EOCCH50:1; - uint32_t EOCCH49:1; - uint32_t EOCCH48:1; - uint32_t EOCCH47:1; - uint32_t EOCCH46:1; - uint32_t EOCCH45:1; - uint32_t EOCCH44:1; - uint32_t EOCCH43:1; - uint32_t EOCCH42:1; - uint32_t EOCCH41:1; - uint32_t EOCCH40:1; - uint32_t EOCCH39:1; - uint32_t EOCCH38:1; - uint32_t EOCCH37:1; - uint32_t EOCCH36:1; - uint32_t EOCCH35:1; - uint32_t EOCCH34:1; - uint32_t EOCCH33:1; - uint32_t EOCCH32:1; - } B; - } CEOCFR1; /* CHANNEL PENDING REGISTER 1 */ - - union { - uint32_t R; - struct { - uint32_t EOCCH95:1; - uint32_t EOCCH94:1; - uint32_t EOCCH93:1; - uint32_t EOCCH92:1; - uint32_t EOCCH91:1; - uint32_t EOCCH90:1; - uint32_t EOCCH89:1; - uint32_t EOCCH88:1; - uint32_t EOCCH87:1; - uint32_t EOCCH86:1; - uint32_t EOCCH85:1; - uint32_t EOCCH84:1; - uint32_t EOCCH83:1; - uint32_t EOCCH82:1; - uint32_t EOCCH81:1; - uint32_t EOCCH80:1; - uint32_t EOCCH79:1; - uint32_t EOCCH78:1; - uint32_t EOCCH77:1; - uint32_t EOCCH76:1; - uint32_t EOCCH75:1; - uint32_t EOCCH74:1; - uint32_t EOCCH73:1; - uint32_t EOCCH72:1; - uint32_t EOCCH71:1; - uint32_t EOCCH70:1; - uint32_t EOCCH69:1; - uint32_t EOCCH68:1; - uint32_t EOCCH67:1; - uint32_t EOCCH66:1; - uint32_t EOCCH65:1; - uint32_t EOCCH64:1; - } B; - } CEOCFR2; /* CHANNEL PENDING REGISTER 2 */ - - union { - uint32_t R; - struct { - uint32_t:25; - uint32_t MSKOFFCANCOVR:1; - uint32_t MSKEOFFSET:1; - uint32_t MSKEOCTU:1; - uint32_t MSKJEOC:1; - uint32_t MSKJECH:1; - uint32_t MSKEOC:1; - uint32_t MSKECH:1; - } B; - } IMR; /* INTERRUPT MASK REGISTER */ - - union { - uint32_t R; - struct { - uint32_t CIM31:1; - uint32_t CIM30:1; - uint32_t CIM29:1; - uint32_t CIM28:1; - uint32_t CIM27:1; - uint32_t CIM26:1; - uint32_t CIM25:1; - uint32_t CIM24:1; - uint32_t CIM23:1; - uint32_t CIM22:1; - uint32_t CIM21:1; - uint32_t CIM20:1; - uint32_t CIM19:1; - uint32_t CIM18:1; - uint32_t CIM17:1; - uint32_t CIM16:1; - uint32_t CIM15:1; - uint32_t CIM14:1; - uint32_t CIM13:1; - uint32_t CIM12:1; - uint32_t CIM11:1; - uint32_t CIM10:1; - uint32_t CIM9:1; - uint32_t CIM8:1; - uint32_t CIM7:1; - uint32_t CIM6:1; - uint32_t CIM5:1; - uint32_t CIM4:1; - uint32_t CIM3:1; - uint32_t CIM2:1; - uint32_t CIM1:1; - uint32_t CIM0:1; - } B; - } CIMR0; /* CHANNEL INTERRUPT MASK REGISTER 0 */ - - union { - uint32_t R; - struct { - uint32_t CIM63:1; - uint32_t CIM62:1; - uint32_t CIM61:1; - uint32_t CIM60:1; - uint32_t CIM59:1; - uint32_t CIM58:1; - uint32_t CIM57:1; - uint32_t CIM56:1; - uint32_t CIM55:1; - uint32_t CIM54:1; - uint32_t CIM53:1; - uint32_t CIM52:1; - uint32_t CIM51:1; - uint32_t CIM50:1; - uint32_t CIM49:1; - uint32_t CIM48:1; - uint32_t CIM47:1; - uint32_t CIM46:1; - uint32_t CIM45:1; - uint32_t CIM44:1; - uint32_t CIM43:1; - uint32_t CIM42:1; - uint32_t CIM41:1; - uint32_t CIM40:1; - uint32_t CIM39:1; - uint32_t CIM38:1; - uint32_t CIM37:1; - uint32_t CIM36:1; - uint32_t CIM35:1; - uint32_t CIM34:1; - uint32_t CIM33:1; - uint32_t CIM32:1; - } B; - } CIMR1; /* CHANNEL INTERRUPT MASK REGISTER 1 */ - - union { - uint32_t R; - struct { - uint32_t CIM63:1; - uint32_t CIM62:1; - uint32_t CIM61:1; - uint32_t CIM60:1; - uint32_t CIM59:1; - uint32_t CIM58:1; - uint32_t CIM57:1; - uint32_t CIM56:1; - uint32_t CIM55:1; - uint32_t CIM54:1; - uint32_t CIM53:1; - uint32_t CIM52:1; - uint32_t CIM51:1; - uint32_t CIM50:1; - uint32_t CIM49:1; - uint32_t CIM48:1; - uint32_t CIM47:1; - uint32_t CIM46:1; - uint32_t CIM45:1; - uint32_t CIM44:1; - uint32_t CIM43:1; - uint32_t CIM42:1; - uint32_t CIM41:1; - uint32_t CIM40:1; - uint32_t CIM39:1; - uint32_t CIM38:1; - uint32_t CIM37:1; - uint32_t CIM36:1; - uint32_t CIM35:1; - uint32_t CIM34:1; - uint32_t CIM33:1; - uint32_t CIM32:1; - } B; - } CIMR2; /* CHANNEL INTERRUPT MASK REGISTER 2 */ - - union { - uint32_t R; - struct { - uint32_t:24; - uint32_t WDG3H:1; - uint32_t WDG2H:1; - uint32_t WDG1H:1; - uint32_t WDG0H:1; - uint32_t WDG3L:1; - uint32_t WDG2L:1; - uint32_t WDG1L:1; - uint32_t WDG0L:1; - } B; - } WTISR; /* WATCHDOG INTERRUPT THRESHOLD REGISTER */ - - union { - uint32_t R; - struct { - uint32_t:24; - uint32_t MSKWDG3H:1; - uint32_t MSKWDG2H:1; - uint32_t MSKWDG1H:1; - uint32_t MSKWDG0H:1; - uint32_t MSKWDG3L:1; - uint32_t MSKWDG2L:1; - uint32_t MSKWDG1L:1; - uint32_t MSKWDG0L:1; - } B; - } WTIMR; /* WATCHDOG INTERRUPT THRESHOLD MASK REGISTER */ - - uint32_t adc_reserved2[2]; - - union { - uint32_t R; - struct { - uint32_t:30; - uint32_t DCLR:1; - uint32_t DMAEN:1; - } B; - } DMAE; /* DMA ENABLE REGISTER */ - - union { - uint32_t R; - struct { - uint32_t DMA31:1; - uint32_t DMA30:1; - uint32_t DMA29:1; - uint32_t DMA28:1; - uint32_t DMA27:1; - uint32_t DMA26:1; - uint32_t DMA25:1; - uint32_t DMA24:1; - uint32_t DMA23:1; - uint32_t DMA22:1; - uint32_t DMA21:1; - uint32_t DMA20:1; - uint32_t DMA19:1; - uint32_t DMA18:1; - uint32_t DMA17:1; - uint32_t DMA16:1; - uint32_t DMA15:1; - uint32_t DMA14:1; - uint32_t DMA13:1; - uint32_t DMA12:1; - uint32_t DMA11:1; - uint32_t DMA10:1; - uint32_t DMA9:1; - uint32_t DMA8:1; - uint32_t DMA7:1; - uint32_t DMA6:1; - uint32_t DMA5:1; - uint32_t DMA4:1; - uint32_t DMA3:1; - uint32_t DMA2:1; - uint32_t DMA1:1; - uint32_t DMA0:1; - } B; - } DMAR0; /* DMA CHANNEL SELECT REGISTER 0 */ - - union { - uint32_t R; - struct { - uint32_t DMA63:1; - uint32_t DMA62:1; - uint32_t DMA61:1; - uint32_t DMA60:1; - uint32_t DMA59:1; - uint32_t DMA58:1; - uint32_t DMA57:1; - uint32_t DMA56:1; - uint32_t DMA55:1; - uint32_t DMA54:1; - uint32_t DMA53:1; - uint32_t DMA52:1; - uint32_t DMA51:1; - uint32_t DMA50:1; - uint32_t DMA49:1; - uint32_t DMA48:1; - uint32_t DMA47:1; - uint32_t DMA46:1; - uint32_t DMA45:1; - uint32_t DMA44:1; - uint32_t DMA43:1; - uint32_t DMA42:1; - uint32_t DMA41:1; - uint32_t DMA40:1; - uint32_t DMA39:1; - uint32_t DMA38:1; - uint32_t DMA37:1; - uint32_t DMA36:1; - uint32_t DMA35:1; - uint32_t DMA34:1; - uint32_t DMA33:1; - uint32_t DMA32:1; - } B; - } DMAR1; /* DMA CHANNEL SELECT REGISTER 1 */ - - union { - uint32_t R; - struct { - uint32_t DMA95:1; - uint32_t DMA94:1; - uint32_t DMA93:1; - uint32_t DMA92:1; - uint32_t DMA91:1; - uint32_t DMA90:1; - uint32_t DMA89:1; - uint32_t DMA88:1; - uint32_t DMA87:1; - uint32_t DMA86:1; - uint32_t DMA85:1; - uint32_t DMA84:1; - uint32_t DMA83:1; - uint32_t DMA82:1; - uint32_t DMA81:1; - uint32_t DMA80:1; - uint32_t DMA79:1; - uint32_t DMA78:1; - uint32_t DMA77:1; - uint32_t DMA76:1; - uint32_t DMA75:1; - uint32_t DMA74:1; - uint32_t DMA73:1; - uint32_t DMA72:1; - uint32_t DMA71:1; - uint32_t DMA70:1; - uint32_t DMA69:1; - uint32_t DMA68:1; - uint32_t DMA67:1; - uint32_t DMA66:1; - uint32_t DMA65:1; - uint32_t DMA64:1; - } B; - } DMAR2; /* DMA CHANNEL SELECT REGISTER 2 */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t THREN:1; - uint32_t THRINV:1; - uint32_t THROP:1; - uint32_t:6; - uint32_t THRCH:7; - } B; - } TRC[4]; /* THRESHOLD CONTROL REGISTER */ - - union { - uint32_t R; - struct { - uint32_t:6; - uint32_t THRH:10; - uint32_t:6; - uint32_t THRL:10; - } B; - } THRHLR[4]; /* THRESHOLD REGISTER */ - - union { - uint32_t R; - struct { - uint32_t:6; - uint32_t THRH:10; - uint32_t:6; - uint32_t THRL:10; - } B; - } THRALT[4]; /* ALTERNATE THRESHOLD REGISTER */ - - union { - uint32_t R; - struct { - uint32_t:25; - uint32_t PREVAL2:2; - uint32_t PREVAL1:2; - uint32_t PREVAL0:2; - uint32_t PRECONV:1; - } B; - } PSCR; /* PRESAMPLING CONTROL REGISTER */ - - union { - uint32_t R; - struct { - uint32_t PSR31:1; - uint32_t PSR30:1; - uint32_t PSR29:1; - uint32_t PSR28:1; - uint32_t PSR27:1; - uint32_t PSR26:1; - uint32_t PSR25:1; - uint32_t PSR24:1; - uint32_t PSR23:1; - uint32_t PSR22:1; - uint32_t PSR21:1; - uint32_t PSR20:1; - uint32_t PSR19:1; - uint32_t PSR18:1; - uint32_t PSR17:1; - uint32_t PSR16:1; - uint32_t PSR15:1; - uint32_t PSR14:1; - uint32_t PSR13:1; - uint32_t PSR12:1; - uint32_t PSR11:1; - uint32_t PSR10:1; - uint32_t PSR9:1; - uint32_t PSR8:1; - uint32_t PSR7:1; - uint32_t PSR6:1; - uint32_t PSR5:1; - uint32_t PSR4:1; - uint32_t PSR3:1; - uint32_t PSR2:1; - uint32_t PSR1:1; - uint32_t PSR0:1; - } B; - } PSR0; /* PRESAMPLING REGISTER 0 */ - - union { - uint32_t R; - struct { - uint32_t PSR63:1; - uint32_t PSR62:1; - uint32_t PSR61:1; - uint32_t PSR60:1; - uint32_t PSR59:1; - uint32_t PSR58:1; - uint32_t PSR57:1; - uint32_t PSR56:1; - uint32_t PSR55:1; - uint32_t PSR54:1; - uint32_t PSR53:1; - uint32_t PSR52:1; - uint32_t PSR51:1; - uint32_t PSR50:1; - uint32_t PSR49:1; - uint32_t PSR48:1; - uint32_t PSR47:1; - uint32_t PSR46:1; - uint32_t PSR45:1; - uint32_t PSR44:1; - uint32_t PSR43:1; - uint32_t PSR42:1; - uint32_t PSR41:1; - uint32_t PSR40:1; - uint32_t PSR39:1; - uint32_t PSR38:1; - uint32_t PSR37:1; - uint32_t PSR36:1; - uint32_t PSR35:1; - uint32_t PSR34:1; - uint32_t PSR33:1; - uint32_t PSR32:1; - } B; - } PSR1; /* PRESAMPLING REGISTER 1 */ - - union { - uint32_t R; - struct { - uint32_t PSR95:1; - uint32_t PSR94:1; - uint32_t PSR93:1; - uint32_t PSR92:1; - uint32_t PSR91:1; - uint32_t PSR90:1; - uint32_t PSR89:1; - uint32_t PSR88:1; - uint32_t PSR87:1; - uint32_t PSR86:1; - uint32_t PSR85:1; - uint32_t PSR84:1; - uint32_t PSR83:1; - uint32_t PSR82:1; - uint32_t PSR81:1; - uint32_t PSR80:1; - uint32_t PSR79:1; - uint32_t PSR78:1; - uint32_t PSR77:1; - uint32_t PSR76:1; - uint32_t PSR75:1; - uint32_t PSR74:1; - uint32_t PSR73:1; - uint32_t PSR72:1; - uint32_t PSR71:1; - uint32_t PSR70:1; - uint32_t PSR69:1; - uint32_t PSR68:1; - uint32_t PSR67:1; - uint32_t PSR66:1; - uint32_t PSR65:1; - uint32_t PSR64:1; - } B; - } PSR2; /* PRESAMPLING REGISTER 2 */ - - uint32_t adc_reserved3; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t INPLATCH:1; - uint32_t:1; - uint32_t OFFSHIFT:2; - uint32_t:1; - uint32_t INPCMP:2; - uint32_t:1; - uint32_t INPSAMP:8; - } B; - } CTR0; /* CONVERSION TIMING REGISTER 0 */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t INPLATCH:1; - uint32_t:4; - uint32_t INPCMP:2; - uint32_t:1; - uint32_t INPSAMP:8; - } B; - } CTR1; /* CONVERSION TIMING REGISTER 1 */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t INPLATCH:1; - uint32_t:4; - uint32_t INPCMP:2; - uint32_t:1; - uint32_t INPSAMP:8; - } B; - } CTR2; /* CONVERSION TIMING REGISTER 2 */ - - uint32_t adc_reserved4; - - union { - uint32_t R; - struct { - uint32_t CH31:1; - uint32_t CH30:1; - uint32_t CH29:1; - uint32_t CH28:1; - uint32_t CH27:1; - uint32_t CH26:1; - uint32_t CH25:1; - uint32_t CH24:1; - uint32_t CH23:1; - uint32_t CH22:1; - uint32_t CH21:1; - uint32_t CH20:1; - uint32_t CH19:1; - uint32_t CH18:1; - uint32_t CH17:1; - uint32_t CH16:1; - uint32_t CH15:1; - uint32_t CH14:1; - uint32_t CH13:1; - uint32_t CH12:1; - uint32_t CH11:1; - uint32_t CH10:1; - uint32_t CH9:1; - uint32_t CH8:1; - uint32_t CH7:1; - uint32_t CH6:1; - uint32_t CH5:1; - uint32_t CH4:1; - uint32_t CH3:1; - uint32_t CH2:1; - uint32_t CH1:1; - uint32_t CH0:1; - } B; - } NCMR0; /* NORMAL CONVERSION MASK REGISTER 0 */ - - union { - uint32_t R; - struct { - uint32_t CH63:1; - uint32_t CH62:1; - uint32_t CH61:1; - uint32_t CH60:1; - uint32_t CH59:1; - uint32_t CH58:1; - uint32_t CH57:1; - uint32_t CH56:1; - uint32_t CH55:1; - uint32_t CH54:1; - uint32_t CH53:1; - uint32_t CH52:1; - uint32_t CH51:1; - uint32_t CH50:1; - uint32_t CH49:1; - uint32_t CH48:1; - uint32_t CH47:1; - uint32_t CH46:1; - uint32_t CH45:1; - uint32_t CH44:1; - uint32_t CH43:1; - uint32_t CH42:1; - uint32_t CH41:1; - uint32_t CH40:1; - uint32_t CH39:1; - uint32_t CH38:1; - uint32_t CH37:1; - uint32_t CH36:1; - uint32_t CH35:1; - uint32_t CH34:1; - uint32_t CH33:1; - uint32_t CH32:1; - } B; - } NCMR1; /* NORMAL CONVERSION MASK REGISTER 1 */ - - union { - uint32_t R; - struct { - uint32_t PSR95:1; - uint32_t PSR94:1; - uint32_t PSR93:1; - uint32_t PSR92:1; - uint32_t PSR91:1; - uint32_t PSR90:1; - uint32_t PSR89:1; - uint32_t PSR88:1; - uint32_t PSR87:1; - uint32_t PSR86:1; - uint32_t PSR85:1; - uint32_t PSR84:1; - uint32_t PSR83:1; - uint32_t PSR82:1; - uint32_t PSR81:1; - uint32_t PSR80:1; - uint32_t PSR79:1; - uint32_t PSR78:1; - uint32_t PSR77:1; - uint32_t PSR76:1; - uint32_t PSR75:1; - uint32_t PSR74:1; - uint32_t PSR73:1; - uint32_t PSR72:1; - uint32_t PSR71:1; - uint32_t PSR70:1; - uint32_t PSR69:1; - uint32_t PSR68:1; - uint32_t PSR67:1; - uint32_t PSR66:1; - uint32_t PSR65:1; - uint32_t PSR64:1; - } B; - } NCMR2; /* NORMAL CONVERSION MASK REGISTER 2 */ - - uint32_t adc_reserved5; - - union { - uint32_t R; - struct { - uint32_t CH31:1; - uint32_t CH30:1; - uint32_t CH29:1; - uint32_t CH28:1; - uint32_t CH27:1; - uint32_t CH26:1; - uint32_t CH25:1; - uint32_t CH24:1; - uint32_t CH23:1; - uint32_t CH22:1; - uint32_t CH21:1; - uint32_t CH20:1; - uint32_t CH19:1; - uint32_t CH18:1; - uint32_t CH17:1; - uint32_t CH16:1; - uint32_t CH15:1; - uint32_t CH14:1; - uint32_t CH13:1; - uint32_t CH12:1; - uint32_t CH11:1; - uint32_t CH10:1; - uint32_t CH9:1; - uint32_t CH8:1; - uint32_t CH7:1; - uint32_t CH6:1; - uint32_t CH5:1; - uint32_t CH4:1; - uint32_t CH3:1; - uint32_t CH2:1; - uint32_t CH1:1; - uint32_t CH0:1; - } B; - } JCMR0; /* INJECTED CONVERSION MASK REGISTER 0 */ - - union { - uint32_t R; - struct { - uint32_t CH63:1; - uint32_t CH62:1; - uint32_t CH61:1; - uint32_t CH60:1; - uint32_t CH59:1; - uint32_t CH58:1; - uint32_t CH57:1; - uint32_t CH56:1; - uint32_t CH55:1; - uint32_t CH54:1; - uint32_t CH53:1; - uint32_t CH52:1; - uint32_t CH51:1; - uint32_t CH50:1; - uint32_t CH49:1; - uint32_t CH48:1; - uint32_t CH47:1; - uint32_t CH46:1; - uint32_t CH45:1; - uint32_t CH44:1; - uint32_t CH43:1; - uint32_t CH42:1; - uint32_t CH41:1; - uint32_t CH40:1; - uint32_t CH39:1; - uint32_t CH38:1; - uint32_t CH37:1; - uint32_t CH36:1; - uint32_t CH35:1; - uint32_t CH34:1; - uint32_t CH33:1; - uint32_t CH32:1; - } B; - } JCMR1; /* INJECTED CONVERSION MASK REGISTER 1 */ - - union { - uint32_t R; - struct { - uint32_t PSR95:1; - uint32_t PSR94:1; - uint32_t PSR93:1; - uint32_t PSR92:1; - uint32_t PSR91:1; - uint32_t PSR90:1; - uint32_t PSR89:1; - uint32_t PSR88:1; - uint32_t PSR87:1; - uint32_t PSR86:1; - uint32_t PSR85:1; - uint32_t PSR84:1; - uint32_t PSR83:1; - uint32_t PSR82:1; - uint32_t PSR81:1; - uint32_t PSR80:1; - uint32_t PSR79:1; - uint32_t PSR78:1; - uint32_t PSR77:1; - uint32_t PSR76:1; - uint32_t PSR75:1; - uint32_t PSR74:1; - uint32_t PSR73:1; - uint32_t PSR72:1; - uint32_t PSR71:1; - uint32_t PSR70:1; - uint32_t PSR69:1; - uint32_t PSR68:1; - uint32_t PSR67:1; - uint32_t PSR66:1; - uint32_t PSR65:1; - uint32_t PSR64:1; - } B; - } JCMR2; /* INJECTED CONVERSION MASK REGISTER 2 */ - - union { - uint32_t R; - struct { - uint32_t:15; - uint32_t OFFSETLOAD:1; - uint32_t:8; - uint32_t OFFSET_WORD:8; - } B; - } OFFWR; /* OFFSET WORD REGISTER */ - - union { - uint32_t R; - struct { - uint32_t:24; - uint32_t DSD:8; - } B; - } DSDR; /* DECODE SIGNALS DELAY REGISTER */ - - union { - uint32_t R; - struct { - uint32_t:24; - uint32_t PDED:8; - } B; - } PDEDR; /* DECODE SIGNALS DELAY REGISTER */ - - uint32_t adc_reserved6[9]; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t TEST_CTL:16; - } B; - } TCTLR; /* TEST CONTROL REGISTER */ - - uint32_t adc_reserved7[3]; - - union { - uint32_t R; - struct { - uint32_t:12; - uint32_t VALID:1; - uint32_t OVERW:1; - uint32_t RESULT:2; - uint32_t:6; - uint32_t CDATA:10; - } B; - } PRECDATAREG[32]; /* PRESISION DATA REGISTER */ - - union { - uint32_t R; - struct { - uint32_t:12; - uint32_t VALID:1; - uint32_t OVERW:1; - uint32_t RESULT:2; - uint32_t:6; - uint32_t CDATA:10; - } B; - } INTDATAREG[32]; /* PRESISION DATA REGISTER */ - - union { - uint32_t R; - struct { - uint32_t:12; - uint32_t VALID:1; - uint32_t OVERW:1; - uint32_t RESULT:2; - uint32_t:6; - uint32_t CDATA:10; - } B; - } EXTDATAREG[32]; /* PRESISION DATA REGISTER */ - - }; /* end of ADC_tag */ -/**************************************************************************/ -/* MODULE : AXBS Crossbar Switch (XBAR) */ -/**************************************************************************/ - struct XBAR_tag { - - union { - uint32_t R; - struct { - uint32_t:1; - uint32_t MSTR7:3; - uint32_t:1; - uint32_t MSTR6:3; - uint32_t:9; - uint32_t MSTR5:3; - uint32_t:1; - uint32_t MSTR3:3; - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:1; - } B; - } MPR0; /* Master Priority Register 0 */ - - uint32_t xbar_reserved1[3]; - - union { - uint32_t R; - struct { - uint32_t R0:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR0; /* Master Priority Register 0 */ - - uint32_t xbar_reserved2[58]; - - union { - uint32_t R; - struct { - uint32_t:1; - uint32_t MSTR7:3; - uint32_t:1; - uint32_t MSTR6:3; - uint32_t:9; - uint32_t MSTR5:3; - uint32_t:1; - uint32_t MSTR3:3; - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:1; - } B; - } MPR1; /* Master Priority Register 1 */ - - uint32_t xbar_reserved3[3]; - - union { - uint32_t R; - struct { - uint32_t R0:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR1; /* Master Priority Register 1 */ - - uint32_t xbar_reserved4[58]; - - union { - uint32_t R; - struct { - uint32_t:1; - uint32_t MSTR7:3; - uint32_t:1; - uint32_t MSTR6:3; - uint32_t:9; - uint32_t MSTR5:3; - uint32_t:1; - uint32_t MSTR3:3; - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:1; - } B; - } MPR2; /* Master Priority Register 2 */ - - uint32_t xbar_reserved5[3]; - - union { - uint32_t R; - struct { - uint32_t R0:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR2; /* Master Priority Register 2 */ - - uint32_t xbar_reserved6[58]; - - union { - uint32_t R; - struct { - uint32_t:1; - uint32_t MSTR7:3; - uint32_t:1; - uint32_t MSTR6:3; - uint32_t:9; - uint32_t MSTR5:3; - uint32_t:1; - uint32_t MSTR3:3; - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:1; - } B; - } MPR3; /* Master Priority Register 3 */ - - uint32_t xbar_reserved7[3]; - - union { - uint32_t R; - struct { - uint32_t R0:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR3; /* Master Priority Register 3 */ - - uint32_t xbar_reserved8[186]; - - union { - uint32_t R; - struct { - uint32_t:1; - uint32_t MSTR7:3; - uint32_t:1; - uint32_t MSTR6:3; - uint32_t:9; - uint32_t MSTR5:3; - uint32_t:1; - uint32_t MSTR3:3; - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:1; - } B; - } MPR6; /* Master Priority Register 6 */ - - uint32_t xbar_reserved9[3]; - - union { - uint32_t R; - struct { - uint32_t R0:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR6; /* Master Priority Register 6 */ - - uint32_t xbar_reserved10[58]; - - union { - uint32_t R; - struct { - uint32_t:1; - uint32_t MSTR7:3; - uint32_t:1; - uint32_t MSTR6:3; - uint32_t:9; - uint32_t MSTR5:3; - uint32_t:1; - uint32_t MSTR3:3; - uint32_t:1; - uint32_t MSTR2:3; - uint32_t:1; - uint32_t MSTR1:3; - uint32_t:1; - uint32_t MSTR0:1; - } B; - } MPR7; /* Master Priority Register 7 */ - - uint32_t xbar_reserved11[3]; - - union { - uint32_t R; - struct { - uint32_t R0:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR7; /* Master Priority Register 7 */ - - uint32_t xbar_reserved12[506]; - - union { - uint32_t R; - struct { - uint32_t R0:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } MGPCR7; /* Master General Purpose Register 7 */ - - }; -/*************************************************************************/ -/* MODULE : CRP */ -/*************************************************************************/ - struct CRP_tag { - - union { - uint32_t R; - struct { - uint32_t IRCTRIMEN:1; - uint32_t:4; - uint32_t PREDIV:3; - uint32_t:4; - uint32_t EN128KIRC:1; - uint32_t EN32KOSC:1; - uint32_t ENLPOSC:1; - uint32_t EN40MOSC:1; - uint32_t:3; - uint32_t TRIM128IRC:5; - uint32_t:2; - uint32_t TRIM16IRC:6; - } B; - } CLKSRC; /* CLOCK SOURCE REGISTER */ - - uint32_t crp_reserved1[3]; - - union { - uint32_t R; - struct { - uint32_t CNTEN:1; - uint32_t RTCIE:1; - uint32_t FRZEN:1; - uint32_t ROVREN:1; - uint32_t RTCVAL:12; - uint32_t APIEN:1; - uint32_t APIIE:1; - uint32_t CLKSEL:2; - uint32_t DIV512EN:1; - uint32_t DIV32EN:1; - uint32_t APIVAL:10; - } B; - } RTCC; /* RTC CONTROL REGISTER */ - - union { - uint32_t R; - struct { - uint32_t:2; - uint32_t RTCF:1; - uint32_t:15; - uint32_t APIF:1; - uint32_t:2; - uint32_t ROVRF:1; - uint32_t:10; - } B; - } RTSC; /* RTC STATUS REGISTER */ - - union { - uint32_t R; - struct { - uint32_t RTCCNT:32; - } B; - } RTCCNT; /* RTC Counter Register */ - - uint32_t crp_reserved2[9]; - - union { - uint32_t R; - struct { - uint32_t PWK31:2; - uint32_t PWK30:2; - uint32_t PWK29:2; - uint32_t PWK28:2; - uint32_t PWK27:2; - uint32_t PWK26:2; - uint32_t PWK25:2; - uint32_t PWK24:2; - uint32_t PWK23:2; - uint32_t PWK22:2; - uint32_t PWK21:2; - uint32_t PWK20:2; - uint32_t PWK19:2; - uint32_t PWK18:2; - uint32_t PWK17:2; - uint32_t PWK16:2; - } B; - } PWKENH; /* PIN WAKEUP ENABLE HIGH REGISTER */ - - union { - uint32_t R; - struct { - uint32_t PWK15:2; - uint32_t PWK14:2; - uint32_t PWK13:2; - uint32_t PWK12:2; - uint32_t PWK11:2; - uint32_t PWK10:2; - uint32_t PWK9:2; - uint32_t PWK8:2; - uint32_t PWK7:2; - uint32_t PWK6:2; - uint32_t PWK5:2; - uint32_t PWK4:2; - uint32_t PWK3:2; - uint32_t PWK2:2; - uint32_t PWK1:2; - uint32_t PWK0:2; - } B; - } PWKENL; /* PIN WAKEUP ENABLE LOW REGISTER */ - - union { - uint32_t R; - struct { - uint32_t PWKSRCIE31:1; - uint32_t PWKSRCIE30:1; - uint32_t PWKSRCIE29:1; - uint32_t PWKSRCIE28:1; - uint32_t PWKSRCIE27:1; - uint32_t PWKSRCIE26:1; - uint32_t PWKSRCIE25:1; - uint32_t PWKSRCIE24:1; - uint32_t PWKSRCIE23:1; - uint32_t PWKSRCIE22:1; - uint32_t PWKSRCIE21:1; - uint32_t PWKSRCIE20:1; - uint32_t PWKSRCIE19:1; - uint32_t PWKSRCIE18:1; - uint32_t PWKSRCIE17:1; - uint32_t PWKSRCIE16:1; - uint32_t PWKSRCIE15:1; - uint32_t PWKSRCIE14:1; - uint32_t PWKSRCIE13:1; - uint32_t PWKSRCIE12:1; - uint32_t PWKSRCIE11:1; - uint32_t PWKSRCIE10:1; - uint32_t PWKSRCIE9:1; - uint32_t PWKSRCIE8:1; - uint32_t PWKSRCIE7:1; - uint32_t PWKSRCIE6:1; - uint32_t PWKSRCIE5:1; - uint32_t PWKSRCIE4:1; - uint32_t PWKSRCIE3:1; - uint32_t PWKSRCIE2:1; - uint32_t PWKSRCIE1:1; - uint32_t PWKSRCIE0:1; - } B; - } PWKSRCIE; /* PIN WAKEUP SOURCE INTERRUPT ENABLE REGISTER */ - - union { - uint32_t R; - struct { - uint32_t PWKSRCIE31:1; - uint32_t PWKSRCIE30:1; - uint32_t PWKSRCIE29:1; - uint32_t PWKSRCIE28:1; - uint32_t PWKSRCIE27:1; - uint32_t PWKSRCIE26:1; - uint32_t PWKSRCIE25:1; - uint32_t PWKSRCIE24:1; - uint32_t PWKSRCIE23:1; - uint32_t PWKSRCIE22:1; - uint32_t PWKSRCIE21:1; - uint32_t PWKSRCIE20:1; - uint32_t PWKSRCIE19:1; - uint32_t PWKSRCIE18:1; - uint32_t PWKSRCIE17:1; - uint32_t PWKSRCIE16:1; - uint32_t PWKSRCIE15:1; - uint32_t PWKSRCIE14:1; - uint32_t PWKSRCIE13:1; - uint32_t PWKSRCIE12:1; - uint32_t PWKSRCIE11:1; - uint32_t PWKSRCIE10:1; - uint32_t PWKSRCIE9:1; - uint32_t PWKSRCIE8:1; - uint32_t PWKSRCIE7:1; - uint32_t PWKSRCIE6:1; - uint32_t PWKSRCIE5:1; - uint32_t PWKSRCIE4:1; - uint32_t PWKSRCIE3:1; - uint32_t PWKSRCIE2:1; - uint32_t PWKSRCIE1:1; - uint32_t PWKSRCIE0:1; - } B; - } PWKSRCF; /* PIN WAKEUP SOURCE FLAG REGISTER */ - - union { - uint32_t R; - struct { - uint32_t Z6VECB:20; - uint32_t:10; - uint32_t Z6RST:1; - uint32_t VLE:1; - } B; - } Z6VEC; /* Z6 RESET VECTOR REGISTER */ - - union { - uint32_t R; - struct { - uint32_t Z0VECB:30; - uint32_t Z0RST:1; - uint32_t:1; - } B; - } Z0VEC; /* Z0 RESET VECTOR REGISTER */ - - union { - uint32_t R; - struct { - uint32_t RECPTR:30; - uint32_t FASTREC:1; - uint32_t:1; - } B; - } RECPTR; /* RESET RECOVERY POINTER REGISTER */ - - uint32_t crp_reserved3; - - union { - uint32_t R; - struct { - uint32_t SLEEPF:1; - uint32_t:12; - uint32_t RTCOVRWKF:1; - uint32_t RTCWKF:1; - uint32_t APIWKF:1; - uint32_t SLEEP:1; - uint32_t:4; - uint32_t RAMSEL:3; - uint32_t:4; - uint32_t WKCLKSEL:1; - uint32_t RTCOVRWKEN:1; - uint32_t RTCWKEN:1; - uint32_t APIWKEN:1; - } B; - } PSCR; /* POWER STATUS AND CONTROL REGISTER */ - - uint32_t crp_reserved4[3]; - - union { - uint32_t R; - struct { - uint32_t LVI5LOCK:1; - uint32_t LVI5RE:1; - uint32_t:7; - uint32_t LVI5HIE:1; - uint32_t LVI5NIE:1; - uint32_t LVI5IE:1; - uint32_t:2; - uint32_t FRIE:1; - uint32_t FDIS:1; - uint32_t:9; - uint32_t LVI5HIF:1; - uint32_t LVI5NF:1; - uint32_t LVI5F:1; - uint32_t:2; - uint32_t FRF:1; - uint32_t FRDY:1; - } B; - } SOCSC; /* LVI Status and Control Register */ - - }; /* end of CRP_tag */ -/*************************************************************************/ -/* MODULE : CTU */ -/*************************************************************************/ - struct CTU_tag { - - union { - uint32_t R; - struct { - uint32_t:24; - uint32_t TRGIEN:1; - uint32_t TRGI:1; - uint32_t:2; - uint32_t PRESC_CONF:4; - } B; - } CSR; /* Control Status Register */ - - union { - uint32_t R; - struct { - uint32_t:23; - uint32_t SV:9; - } B; - } SVR[7]; /* Start Value Register */ - - union { - uint32_t R; - struct { - uint32_t:23; - uint32_t CV:9; - } B; - } CVR[4]; /* Current Value Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t TM:1; - uint32_t:1; - uint32_t COUNT_GROUP:2; - uint32_t:1; - uint32_t DELAY_INDEX:3; - uint32_t CLR_FG:1; - uint32_t:1; - uint32_t CHANNEL_VALUE:6; - } B; - } EVTCFGR[33]; /* Event Configuration Register */ - - }; /* end of CTU_tag */ -/*************************************************************************/ -/* MODULE : DMAMUX */ -/*************************************************************************/ - struct DMAMUX_tag { - union { - uint8_t R; - struct { - uint8_t ENBL:1; - uint8_t TRIG:1; - uint8_t SOURCE:6; - } B; - } CHCONFIG[32]; /* DMA Channel Configuration Register */ - - }; /* end of DMAMUX_tag */ -/*************************************************************************/ -/* MODULE : DSPI */ -/*************************************************************************/ - struct DSPI_tag { - union DSPI_MCR_tag { - uint32_t R; - struct { - uint32_t MSTR:1; - uint32_t CONT_SCKE:1; - uint32_t DCONF:2; - uint32_t FRZ:1; - uint32_t MTFE:1; - uint32_t PCSSE:1; - uint32_t ROOE:1; - uint32_t:2; - uint32_t PCSIS5:1; - uint32_t PCSIS4:1; - uint32_t PCSIS3:1; - uint32_t PCSIS2:1; - uint32_t PCSIS1:1; - uint32_t PCSIS0:1; - uint32_t:1; - uint32_t MDIS:1; - uint32_t DIS_TXF:1; - uint32_t DIS_RXF:1; - uint32_t CLR_TXF:1; - uint32_t CLR_RXF:1; - uint32_t SMPL_PT:2; - uint32_t:7; - uint32_t HALT:1; - } B; - } MCR; /* Module Configuration Register */ - - uint32_t dspi_reserved1; - - union { - uint32_t R; - struct { - uint32_t SPI_TCNT:16; - uint32_t:16; - } B; - } TCR; - - union DSPI_CTAR_tag { - uint32_t R; - struct { - uint32_t DBR:1; - uint32_t FMSZ:4; - uint32_t CPOL:1; - uint32_t CPHA:1; - uint32_t LSBFE:1; - uint32_t PCSSCK:2; - uint32_t PASC:2; - uint32_t PDT:2; - uint32_t PBR:2; - uint32_t CSSCK:4; - uint32_t ASC:4; - uint32_t DT:4; - uint32_t BR:4; - } B; - } CTAR[8]; /* Clock and Transfer Attributes Registers */ - - union DSPI_SR_tag { - uint32_t R; - struct { - uint32_t TCF:1; - uint32_t TXRXS:1; - uint32_t:1; - uint32_t EOQF:1; - uint32_t TFUF:1; - uint32_t:1; - uint32_t TFFF:1; - uint32_t:5; - uint32_t RFOF:1; - uint32_t:1; - uint32_t RFDF:1; - uint32_t:1; - uint32_t TXCTR:4; - uint32_t TXNXTPTR:4; - uint32_t RXCTR:4; - uint32_t POPNXTPTR:4; - } B; - } SR; /* Status Register */ - - union DSPI_RSER_tag { - uint32_t R; - struct { - uint32_t TCFRE:1; - uint32_t:2; - uint32_t EOQFRE:1; - uint32_t TFUFRE:1; - uint32_t:1; - uint32_t TFFFRE:1; - uint32_t TFFFDIRS:1; - uint32_t:4; - uint32_t RFOFRE:1; - uint32_t:1; - uint32_t RFDFRE:1; - uint32_t RFDFDIRS:1; - uint32_t:16; - } B; - } RSER; /* DMA/Interrupt Request Select and Enable Register */ - - union DSPI_PUSHR_tag { - uint32_t R; - struct { - uint32_t CONT:1; - uint32_t CTAS:3; - uint32_t EOQ:1; - uint32_t CTCNT:1; - uint32_t:4; - uint32_t PCS5:1; - uint32_t PCS4:1; - uint32_t PCS3:1; - uint32_t PCS2:1; - uint32_t PCS1:1; - uint32_t PCS0:1; - uint32_t TXDATA:16; - } B; - } PUSHR; /* PUSH TX FIFO Register */ - - union DSPI_POPR_tag { - uint32_t R; - struct { - uint32_t:16; - uint32_t RXDATA:16; - } B; - } POPR; /* POP RX FIFO Register */ - - union { - uint32_t R; - struct { - uint32_t TXCMD:16; - uint32_t TXDATA:16; - } B; - } TXFR[4]; /* Transmit FIFO Registers */ - - uint32_t DSPI_reserved_txf[12]; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t RXDATA:16; - } B; - } RXFR[4]; /* Transmit FIFO Registers */ - - uint32_t DSPI_reserved_rxf[12]; - - union { - uint32_t R; - struct { - uint32_t:11; - uint32_t TSBC:1; - uint32_t TXSS:1; - uint32_t:2; - uint32_t CID:1; - uint32_t DCONT:1; - uint32_t DSICTAS:3; - uint32_t:6; - uint32_t DPCS5:1; - uint32_t DPCS4:1; - uint32_t DPCS3:1; - uint32_t DPCS2:1; - uint32_t DPCS1:1; - uint32_t DPCS0:1; - } B; - } DSICR; /* DSI Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t SER_DATA:32; - } B; - } SDR; /* DSI Serialization Data Register */ - - union { - uint32_t R; - struct { - uint32_t ASER_DATA:32; - } B; - } ASDR; /* DSI Alternate Serialization Data Register */ - - union { - uint32_t R; - struct { - uint32_t COMP_DATA:32; - } B; - } COMPR; /* DSI Transmit Comparison Register */ - - union { - uint32_t R; - struct { - uint32_t DESER_DATA:32; - } B; - } DDR; /* DSI deserialization Data Register */ - - union { - uint32_t R; - struct { - uint32_t:3; - uint32_t TSBCNT:5; - uint32_t:16; - uint32_t DPCS1_7:1; - uint32_t DPCS1_6:1; - uint32_t DPCS1_5:1; - uint32_t DPCS1_4:1; - uint32_t DPCS1_3:1; - uint32_t DPCS1_2:1; - uint32_t DPCS1_1:1; - uint32_t DPCS1_0:1; - } B; - } DSICR1; /* DSI Configuration Register 1 */ - - }; /* end of DSPI_tag */ -/*************************************************************************/ -/* MODULE : ECSM */ -/*************************************************************************/ - struct ECSM_tag { - - uint32_t ecsm_reserved1[9]; - - union { - uint32_t R; - struct { - uint32_t FXSBE0:1; - uint32_t FXSBE1:1; - uint32_t FXSBE2:1; - uint32_t FXSBE3:1; - uint32_t:2; - uint32_t FXSBE6:1; - uint32_t FXSBE7:1; - uint32_t RBEN:1; - uint32_t WBEN:1; - uint32_t ACCERR:1; - uint32_t:21; - } B; - } FBOMCR; /* FEC Burst Optimisation Master Control Register */ - - uint8_t ecsm_reserved2[27]; - - union { - uint8_t R; - struct { - uint8_t:2; - uint8_t EPR1BR:1; - uint8_t EPF1BR:1; - uint8_t:2; - uint8_t EPRNCR:1; - uint8_t EPFNCR:1; - } B; - } ECR; /* ECC Configuration Register */ - - uint8_t ecsm_reserved3[3]; - - union { - uint8_t R; - struct { - uint8_t:2; - uint8_t PR1BC:1; - uint8_t PF1BC:1; - uint8_t:2; - uint8_t PRNCE:1; - uint8_t PFNCE:1; - } B; - } ESR; /* ECC Status Register */ - - uint16_t ecsm_reserved4; - - union { - uint16_t R; - struct { - uint16_t:2; - uint16_t FRC1BI:1; - uint16_t FR11BI:1; - uint16_t:2; - uint16_t FRCNCI:1; - uint16_t FR1NCI:1; - uint16_t PREI_SEL:1; - uint16_t ERRBIT:7; - } B; - } EEGR; /* ECC Error Generation Register */ - - uint32_t ecsm_reserved5; - - union { - uint32_t R; - struct { - uint32_t PFEAR:32; - } B; - } PFEAR; /* Platform Flash ECC Address Register */ - - uint16_t ecsm_reserved6; - - union { - uint8_t R; - struct { - uint8_t:4; - uint8_t PFEMR:4; - } B; - } PFEMR; /* Platform Flash ECC Address Register */ - - union { - uint8_t R; - struct { - uint8_t WRITE:1; - uint8_t SIZE:3; - uint8_t PROTECTION:4; - } B; - } PFEAT; /* Flash ECC Attributes Register */ - - union { - uint32_t R; - struct { - uint32_t PFEDRH:32; - } B; - } PFEDRH; /* Flash ECC Data High Register */ - - union { - uint32_t R; - struct { - uint32_t PFEDRL:32; - } B; - } PFEDRL; /* Flash ECC Data Low Register */ - - union { - uint32_t R; - struct { - uint32_t PREAR:32; - } B; - } PREAR; /* Platform RAM ECC Address Register */ - - uint16_t ecsm_reserved8; - - union { - uint8_t R; - struct { - uint8_t:4; - uint8_t PREMR:4; - } B; - } PREMR; /* RAM ECC Attributes Register */ - - union { - uint8_t R; - struct { - uint8_t WRITE:1; - uint8_t SIZE:3; - uint8_t PROTECTION:4; - } B; - } PREAT; /* Platform RAM ECC Attributes Register */ - - union { - uint32_t R; - struct { - uint32_t PREDR:32; - } B; - } PREDRH; /* Platform RAM ECC Data Low Register High */ - - union { - uint32_t R; - struct { - uint32_t PREDR:32; - } B; - } PREDRL; /* Platform RAM ECC Data Low Register Low */ - - }; /* end of ECSM_tag */ -/*************************************************************************/ -/* MODULE : EMIOS */ -/*************************************************************************/ - struct EMIOS_tag { - union EMIOS_MCR_tag { - uint32_t R; - struct { - uint32_t:1; - uint32_t MDIS:1; - uint32_t FRZ:1; - uint32_t GTBE:1; - uint32_t:1; - uint32_t GPREN:1; - uint32_t:10; - uint32_t GPRE:8; - uint32_t:8; - } B; - } MCR; /* Module Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t F31:1; - uint32_t F30:1; - uint32_t F29:1; - uint32_t F28:1; - uint32_t F27:1; - uint32_t F26:1; - uint32_t F25:1; - uint32_t F24:1; - uint32_t F23:1; - uint32_t F22:1; - uint32_t F21:1; - uint32_t F20:1; - uint32_t F19:1; - uint32_t F18:1; - uint32_t F17:1; - uint32_t F16:1; - uint32_t F15:1; - uint32_t F14:1; - uint32_t F13:1; - uint32_t F12:1; - uint32_t F11:1; - uint32_t F10:1; - uint32_t F9:1; - uint32_t F8:1; - uint32_t F7:1; - uint32_t F6:1; - uint32_t F5:1; - uint32_t F4:1; - uint32_t F3:1; - uint32_t F2:1; - uint32_t F1:1; - uint32_t F0:1; - } B; - } GFR; /* Global FLAG Register */ - - union { - uint32_t R; - struct { - uint32_t OU31:1; - uint32_t OU30:1; - uint32_t OU29:1; - uint32_t OU28:1; - uint32_t OU27:1; - uint32_t OU26:1; - uint32_t OU25:1; - uint32_t OU24:1; - uint32_t OU23:1; - uint32_t OU22:1; - uint32_t OU21:1; - uint32_t OU20:1; - uint32_t OU19:1; - uint32_t OU18:1; - uint32_t OU17:1; - uint32_t OU16:1; - uint32_t OU15:1; - uint32_t OU14:1; - uint32_t OU13:1; - uint32_t OU12:1; - uint32_t OU11:1; - uint32_t OU10:1; - uint32_t OU9:1; - uint32_t OU8:1; - uint32_t OU7:1; - uint32_t OU6:1; - uint32_t OU5:1; - uint32_t OU4:1; - uint32_t OU3:1; - uint32_t OU2:1; - uint32_t OU1:1; - uint32_t OU0:1; - } B; - } OUDR; /* Output Update Disable Register */ - - union { - uint32_t R; - struct { - uint32_t UC31:1; - uint32_t UC30:1; - uint32_t UC29:1; - uint32_t UC28:1; - uint32_t UC27:1; - uint32_t UC26:1; - uint32_t UC25:1; - uint32_t UC24:1; - uint32_t UC23:1; - uint32_t UC22:1; - uint32_t UC21:1; - uint32_t UC20:1; - uint32_t UC19:1; - uint32_t UC18:1; - uint32_t UC17:1; - uint32_t UC16:1; - uint32_t UC15:1; - uint32_t UC14:1; - uint32_t UC13:1; - uint32_t UC12:1; - uint32_t UC11:1; - uint32_t UC10:1; - uint32_t UC9:1; - uint32_t UC8:1; - uint32_t UC7:1; - uint32_t UC6:1; - uint32_t UC5:1; - uint32_t UC4:1; - uint32_t UC3:1; - uint32_t UC2:1; - uint32_t UC1:1; - uint32_t UC0:1; - } B; - } UCDIS; /* Disable Channel Register */ - - uint32_t emios_reserved1[4]; - - struct EMIOS_CH_tag { - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t A:16; /* Channel A Data Register */ - } B; - } CADR; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t B:16; /* Channel B Data Register */ - } B; - } CBDR; - - union { - uint32_t R; /* Channel Counter Register */ - struct { - uint32_t:16; - uint32_t C:16; /* Channel C Data Register */ - } B; - } CCNTR; - - union EMIOS_CCR_tag { - uint32_t R; - struct { - uint32_t FREN:1; - uint32_t ODIS:1; - uint32_t ODISSL:2; - uint32_t UCPRE:2; - uint32_t UCPREN:1; - uint32_t DMA:1; - uint32_t:1; - uint32_t IF:4; - uint32_t FCK:1; - uint32_t FEN:1; - uint32_t:3; - uint32_t FORCMA:1; - uint32_t FORCMB:1; - uint32_t:1; - uint32_t BSL:2; - uint32_t EDSEL:1; - uint32_t EDPOL:1; - uint32_t MODE:7; - } B; - } CCR; /* Channel Control Register */ - - union EMIOS_CSR_tag { - uint32_t R; - struct { - uint32_t OVR:1; - uint32_t:15; - uint32_t OVFL:1; - uint32_t:12; - uint32_t UCIN:1; - uint32_t UCOUT:1; - uint32_t FLAG:1; - } B; - } CSR; /* Channel Status Register */ - - union { - uint32_t R; /* Alternate Channel A Data Register */ - } ALTA; - - uint32_t emios_channel_reserved[2]; - - } CH[32]; - - }; /* end of EMIOS_tag */ -/*************************************************************************/ -/* MODULE : eSCI */ -/*************************************************************************/ - struct ESCI_tag { - union ESCI_CR1_tag { - uint32_t R; - struct { - uint32_t:3; - uint32_t SBR:13; - uint32_t LOOPS:1; - uint32_t:1; - uint32_t RSRC:1; - uint32_t M:1; - uint32_t WAKE:1; - uint32_t ILT:1; - uint32_t PE:1; - uint32_t PT:1; - uint32_t TIE:1; - uint32_t TCIE:1; - uint32_t RIE:1; - uint32_t ILIE:1; - uint32_t TE:1; - uint32_t RE:1; - uint32_t RWU:1; - uint32_t SBK:1; - } B; - } CR1; /* Control Register 1 */ - - union ESCI_CR2_tag { - uint16_t R; - struct { - uint16_t MDIS:1; - uint16_t FBR:1; - uint16_t BSTP:1; - uint16_t IEBERR:1; - uint16_t RXDMA:1; - uint16_t TXDMA:1; - uint16_t BRK13:1; - uint16_t TXDIR:1; - uint16_t BESM13:1; - uint16_t SBSTP:1; - uint16_t RXPOL:1; - uint16_t PMSK:1; - uint16_t ORIE:1; - uint16_t NFIE:1; - uint16_t FEIE:1; - uint16_t PFIE:1; - } B; - } CR2; /* Control Register 2 */ - - union ESCI_DR_tag { - uint16_t R; - struct { - uint16_t RN:1; - uint16_t TN:1; - uint16_t ERR:1; - uint16_t:1; - uint16_t RD_11:4; - uint16_t D:8; - } B; - } DR; /* Data Register */ - - union ESCI_SR_tag { - uint32_t R; - struct { - uint32_t TDRE:1; - uint32_t TC:1; - uint32_t RDRF:1; - uint32_t IDLE:1; - uint32_t OR:1; - uint32_t NF:1; - uint32_t FE:1; - uint32_t PF:1; - uint32_t:3; - uint32_t BERR:1; - uint32_t:2; - uint32_t TACT:1; - uint32_t RACT:1; - uint32_t RXRDY:1; - uint32_t TXRDY:1; - uint32_t LWAKE:1; - uint32_t STO:1; - uint32_t PBERR:1; - uint32_t CERR:1; - uint32_t CKERR:1; - uint32_t FRC:1; - uint32_t:6; - uint32_t UREQ:1; - uint32_t OVFL:1; - } B; - } SR; /* Status Register */ - - union { - uint32_t R; - struct { - uint32_t LRES:1; - uint32_t WU:1; - uint32_t WUD0:1; - uint32_t WUD1:1; - uint32_t:2; - uint32_t PRTY:1; - uint32_t LIN:1; - uint32_t RXIE:1; - uint32_t TXIE:1; - uint32_t WUIE:1; - uint32_t STIE:1; - uint32_t PBIE:1; - uint32_t CIE:1; - uint32_t CKIE:1; - uint32_t FCIE:1; - uint32_t:6; - uint32_t UQIE:1; - uint32_t OFIE:1; - uint32_t:8; - } B; - } LCR; /* LIN Control Register */ - - union { - uint8_t R; - } LTR; /* LIN Transmit Register */ - - uint8_t eSCI_reserved1[3]; - - union { - uint8_t R; - } LRR; /* LIN Recieve Register */ - - uint8_t eSCI_reserved2[3]; - - union { - uint16_t R; - } LPR; /* LIN CRC Polynom Register */ - - union { - uint8_t R; - struct { - uint8_t:3; - uint8_t SYNM:1; - uint8_t EROE:1; - uint8_t ERFE:1; - uint8_t ERPE:1; - uint8_t M2:1; - } B; - } CR3; /* Control Register 3 */ - - uint8_t eSCI_reserved3[5]; - }; /* end of ESCI_tag */ -/*************************************************************************/ -/* MODULE : FEC */ -/*************************************************************************/ - struct FEC_tag { - - uint32_t fec_reserved_start; - - union { - uint32_t R; - struct { - uint32_t HBERR:1; - uint32_t BABR:1; - uint32_t BABT:1; - uint32_t GRA:1; - uint32_t TXF:1; - uint32_t TXB:1; - uint32_t RXF:1; - uint32_t RXB:1; - uint32_t MII:1; - uint32_t EBERR:1; - uint32_t LC:1; - uint32_t RL:1; - uint32_t UN:1; - uint32_t:19; - } B; - } EIR; /* Interrupt Event Register */ - - union { - uint32_t R; - struct { - uint32_t HBERR:1; - uint32_t BABR:1; - uint32_t BABT:1; - uint32_t GRA:1; - uint32_t TXF:1; - uint32_t TXB:1; - uint32_t RXF:1; - uint32_t RXB:1; - uint32_t MII:1; - uint32_t EBERR:1; - uint32_t LC:1; - uint32_t RL:1; - uint32_t UN:1; - uint32_t:19; - } B; - } EIMR; /* Interrupt Mask Register */ - - uint32_t fec_reserved_eimr; - - union { - uint32_t R; - struct { - uint32_t:7; - uint32_t R_DES_ACTIVE:1; - uint32_t:24; - } B; - } RDAR; /* Receive Descriptor Active Register */ - - union { - uint32_t R; - struct { - uint32_t:7; - uint32_t X_DES_ACTIVE:1; - uint32_t:24; - } B; - } TDAR; /* Transmit Descriptor Active Register */ - - uint32_t fec_reserved_tdar[3]; - - union { - uint32_t R; - struct { - uint32_t:30; - uint32_t ETHER_EN:1; - uint32_t RESET:1; - } B; - } ECR; /* Ethernet Control Register */ - - uint32_t fec_reserved_ecr[6]; - - union { - uint32_t R; - struct { - uint32_t ST:2; - uint32_t OP:2; - uint32_t PA:5; - uint32_t RA:5; - uint32_t TA:2; - uint32_t DATA:16; - } B; - } MMFR; /* MII Data Register */ - - union { - uint32_t R; - struct { - uint32_t:24; - uint32_t DIS_PREAMBLE:1; - uint32_t MII_SPEED:6; - uint32_t:1; - } B; - } MSCR; /* MII Speed Control Register */ - - uint32_t fec_reserved_mscr[7]; - - union { - uint32_t R; - struct { - uint32_t MIB_DISABLE:1; - uint32_t MIB_IDLE:1; - uint32_t:30; - } B; - } MIBC; /* MIB Control Register */ - - uint32_t fec_reserved_mibc[7]; - - union { - uint32_t R; - struct { - uint32_t:5; - uint32_t MAX_FL:11; - uint32_t:10; - uint32_t FCE:1; - uint32_t BC_REJ:1; - uint32_t PROM:1; - uint32_t MII_MODE:1; - uint32_t DRT:1; - uint32_t LOOP:1; - } B; - } RCR; /* Receive Control Register */ - - uint32_t fec_reserved_rcr[15]; - - union { - uint32_t R; - struct { - uint32_t:27; - uint32_t RFC_PAUSE:1; - uint32_t TFC_PAUSE:1; - uint32_t FDEN:1; - uint32_t HBC:1; - uint32_t GTS:1; - } B; - } TCR; /* Transmit Control Register */ - - uint32_t fec_reserved_tcr[7]; - - union { - uint32_t R; - struct { - uint32_t PADDR1:32; - } B; - } PALR; /* Physical Address Low Register */ - - union { - uint32_t R; - struct { - uint32_t PADDR2:16; - uint32_t TYPE:16; - } B; - } PAUR; /* Physical Address High + Type Register */ - - union { - uint32_t R; - struct { - uint32_t OPCODE:16; - uint32_t PAUSE_DUR:16; - } B; - } OPD; /* Opcode/Pause Duration Register */ - - uint32_t fec_reserved_opd[10]; - - union { - uint32_t R; - struct { - uint32_t IADDR1:32; - } B; - } IAUR; /* Descriptor Individual Upper Address Register */ - - union { - uint32_t R; - struct { - uint32_t IADDR2:32; - } B; - } IALR; /* Descriptor Individual Lower Address Register */ - - union { - uint32_t R; - struct { - uint32_t GADDR1:32; - } B; - } GAUR; /* Descriptor Group Upper Address Register */ - - union { - uint32_t R; - struct { - uint32_t GADDR2:32; - } B; - } GALR; /* Descriptor Group Lower Address Register */ - - uint32_t fec_reserved_galr[7]; - - union { - uint32_t R; - struct { - uint32_t:30; - uint32_t X_WMRK:2; - } B; - } TFWR; /* FIFO Transmit FIFO Watermark Register */ - - uint32_t fec_reserved_tfwr; - - union { - uint32_t R; - struct { - uint32_t:22; - uint32_t R_BOUND:8; - uint32_t:2; - } B; - } FRBR; /* FIFO Receive Bound Register */ - - union { - uint32_t R; - struct { - uint32_t:22; - uint32_t R_FSTART:8; - uint32_t:2; - } B; - } FRSR; /* FIFO Receive Start Register */ - - uint32_t fec_reserved_frsr[11]; - - union { - uint32_t R; - struct { - uint32_t R_DES_START:30; - uint32_t:2; - } B; - } ERDSR; /* Receive Descriptor Ring Start Register */ - - union { - uint32_t R; - struct { - uint32_t X_DES_START:30; - uint32_t:2; - } B; - } ETDSR; /* Transmit Descriptor Ring Start Register */ - - union { - uint32_t R; - struct { - uint32_t:21; - uint32_t R_BUF_SIZE:7; - uint32_t:4; - } B; - } EMRBR; /* Receive Buffer Size Register */ - - uint32_t fec_reserved_emrbr[29]; - - union { - uint32_t R; - } RMON_T_DROP; /* Count of frames not counted correctly */ - - union { - uint32_t R; - } RMON_T_PACKETS; /* RMON Tx packet count */ - - union { - uint32_t R; - } RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */ - - union { - uint32_t R; - } RMON_T_MC_PKT; /* RMON Tx Multicast Packets */ - - union { - uint32_t R; - } RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */ - - union { - uint32_t R; - } RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */ - - union { - uint32_t R; - } RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */ - - union { - uint32_t R; - } RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */ - - union { - uint32_t R; - } RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */ - - union { - uint32_t R; - } RMON_T_COL; /* RMON Tx collision count */ - - union { - uint32_t R; - } RMON_T_P64; /* RMON Tx 64 byte packets */ - - union { - uint32_t R; - } RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */ - - union { - uint32_t R; - } RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */ - - union { - uint32_t R; - } RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */ - - union { - uint32_t R; - } RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */ - - union { - uint32_t R; - } RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */ - - union { - uint32_t R; - } RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */ - - union { - uint32_t R; - } RMON_T_OCTETS; /* RMON Tx Octets */ - - union { - uint32_t R; - } IEEE_T_DROP; /* Count of frames not counted correctly */ - - union { - uint32_t R; - } IEEE_T_FRAME_OK; /* Frames Transmitted OK */ - - union { - uint32_t R; - } IEEE_T_1COL; /* Frames Transmitted with Single Collision */ - - union { - uint32_t R; - } IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */ - - union { - uint32_t R; - } IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */ - - union { - uint32_t R; - } IEEE_T_LCOL; /* Frames Transmitted with Late Collision */ - - union { - uint32_t R; - } IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */ - - union { - uint32_t R; - } IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */ - - union { - uint32_t R; - } IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */ - - union { - uint32_t R; - } IEEE_T_SQE; /* Frames Transmitted with SQE Error */ - - union { - uint32_t R; - } IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */ - - union { - uint32_t R; - } IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */ - - uint32_t fec_reserved_rmon_t_octets_ok[2]; - - union { - uint32_t R; - } RMON_R_DROP; /* Count of frames not counted correctly */ - - union { - uint32_t R; - } RMON_R_PACKETS; /* RMON Rx packet count */ - - union { - uint32_t R; - } RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */ - - union { - uint32_t R; - } RMON_R_MC_PKT; /* RMON Rx Multicast Packets */ - - union { - uint32_t R; - } RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */ - - union { - uint32_t R; - } RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */ - - union { - uint32_t R; - } RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */ - - union { - uint32_t R; - } RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */ - - union { - uint32_t R; - } RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */ - - uint32_t fec_reserved_rmon_r_jab; - - union { - uint32_t R; - } RMON_R_P64; /* RMON Rx 64 byte packets */ - - union { - uint32_t R; - } RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */ - - union { - uint32_t R; - } RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */ - - union { - uint32_t R; - } RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */ - - union { - uint32_t R; - } RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */ - - union { - uint32_t R; - } RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */ - - union { - uint32_t R; - } RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */ - - union { - uint32_t R; - } RMON_R_OCTETS; /* RMON Rx Octets */ - - union { - uint32_t R; - } IEEE_R_DROP; /* Count of frames not counted correctly */ - - union { - uint32_t R; - } IEEE_R_FRAME_OK; /* Frames Received OK */ - - union { - uint32_t R; - } IEEE_R_CRC; /* Frames Received with CRC Error */ - - union { - uint32_t R; - } IEEE_R_ALIGN; /* Frames Received with Alignment Error */ - - union { - uint32_t R; - } IEEE_R_MACERR; /* Receive Fifo Overflow count */ - - union { - uint32_t R; - } IEEE_R_FDXFC; /* Flow Control Pause frames received */ - - union { - uint32_t R; - } IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */ - - }; /* end of FEC_tag */ -/*************************************************************************/ -/* MODULE : FLASH */ -/*************************************************************************/ - struct FLASH_tag { - union { - uint32_t R; - struct { - uint32_t:5; - uint32_t SIZE:3; - uint32_t:1; - uint32_t LAS:3; - uint32_t:3; - uint32_t MAS:1; - uint32_t EER:1; - uint32_t RWE:1; - uint32_t SBC:1; - uint32_t:1; - uint32_t PEAS:1; - uint32_t DONE:1; - uint32_t PEG:1; - uint32_t:4; - uint32_t PGM:1; - uint32_t PSUS:1; - uint32_t ERS:1; - uint32_t ESUS:1; - uint32_t EHV:1; - } B; - } MCR; /* Module Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t LME:1; - uint32_t:10; - uint32_t SLOCK:1; - uint32_t:2; - uint32_t MLOCK:2; - uint32_t:6; - uint32_t LLOCK:10; - } B; - } LML; /* Low/Mid-address space block locking Register */ - - union { - uint32_t R; - struct { - uint32_t HBE:1; - uint32_t:25; - uint32_t HBLOCK:6; - } B; - } HBL; /* High-address space block locking Register */ - - union { - uint32_t R; - struct { - uint32_t SLE:1; - uint32_t:10; - uint32_t SSLOCK:1; - uint32_t:2; - uint32_t SMLOCK:2; - uint32_t:6; - uint32_t SLLOCK:10; - } B; - } SLL; /* Secondary low/mid-address space block locking Register */ - - union { - uint32_t R; - struct { - uint32_t:14; - uint32_t MSEL:2; - uint32_t:6; - uint32_t LSEL:10; - } B; - } LMS; /* Low/Mid-address space block locking Register */ - - union { - uint32_t R; - struct { - uint32_t:26; - uint32_t HBSEL:6; - } B; - } HBS; /* High-address space block locking Register */ - - union { - uint32_t R; - struct { - uint32_t SAD:1; - uint32_t:10; - uint32_t ADDR:18; - uint32_t:3; - } B; - } ADR; /* Address Register */ - - union { - uint32_t R; - struct { - uint32_t LBCFG:4; - uint32_t ARB:1; - uint32_t PRI:1; - uint32_t:1; - uint32_t M8PFE:1; - uint32_t:1; - uint32_t M6PFE:1; - uint32_t M5PFE:1; - uint32_t M4PFE:1; - uint32_t:1; - uint32_t M2PFE:1; - uint32_t M1PFE:1; - uint32_t M0PFE:1; - uint32_t APC:3; - uint32_t WWSC:2; - uint32_t RWSC:3; - uint32_t:1; - uint32_t DPFEN:1; - uint32_t:1; - uint32_t IPFEN:1; - uint32_t:1; - uint32_t PFLIM:2; - uint32_t BFEN:1; - } B; - } PFCRP0; /* Platform Flash Configuration Register for Port 0 */ - - union { - uint32_t R; - struct { - uint32_t LBCFG:4; - uint32_t:3; - uint32_t M8PFE:1; - uint32_t:1; - uint32_t M6PFE:1; - uint32_t M5PFE:1; - uint32_t M4PFE:1; - uint32_t:1; - uint32_t M2PFE:1; - uint32_t M1PFE:1; - uint32_t M0PFE:1; - uint32_t APC:3; - uint32_t WWSC:2; - uint32_t RWSC:3; - uint32_t:1; - uint32_t DPFEN:1; - uint32_t:1; - uint32_t IPFEN:1; - uint32_t:1; - uint32_t PFLIM:2; - uint32_t BFEN:1; - } B; - } PFCRP1; /* Platform Flash Configuration Register for Port 1 */ - - union { - uint32_t R; - struct { - uint32_t M7AP:2; - uint32_t M6AP:2; - uint32_t M5AP:2; - uint32_t M4AP:2; - uint32_t M3AP:2; - uint32_t M2AP:2; - uint32_t M1AP:2; - uint32_t M0AP:2; - uint32_t SHSACC:4; - uint32_t:4; - uint32_t SHDACC:4; - uint32_t:4; - } B; - } PFAPR; /* Platform Flash access protection Register */ - - union { - uint32_t R; - struct { - uint32_t:1; - uint32_t SACC:31; - } B; - } PFSACC; /* PFlash Supervisor Access Control Register */ - - union { - uint32_t R; - struct { - uint32_t:1; - uint32_t DACC:31; - } B; - } PFDACC; /* PFlash Data Access Control Register */ - - uint32_t FLASH_reserved1[3]; - - union { - uint32_t R; - struct { - uint32_t UTE:1; - uint32_t SCBE:1; - uint32_t:6; - uint32_t DSI:8; - uint32_t:10; - uint32_t MRE:1; - uint32_t MRV:1; - uint32_t EIE:1; - uint32_t AIS:1; - uint32_t AIE:1; - uint32_t AID:1; - } B; - } UT0; /* User Test Register 0 */ - - union { - uint32_t R; - struct { - uint32_t DAI:32; - } B; - } UT1; /* User Test Register 1 */ - - union { - uint32_t R; - struct { - uint32_t DAI:32; - } B; - } UT2; /* User Test Register 2 */ - - union { - uint32_t R; - struct { - uint32_t MISR:32; - } B; - } MISR[5]; /* Multiple Input Signature Register */ - - }; /* end of FLASH_tag */ -/*************************************************************************/ -/* MODULE : FlexCAN */ -/*************************************************************************/ - struct FLEXCAN_tag { - union { - uint32_t R; - struct { - uint32_t MDIS:1; - uint32_t FRZ:1; - uint32_t FEN:1; - uint32_t HALT:1; - uint32_t NOTRDY:1; - uint32_t WAKMSK:1; - uint32_t SOFTRST:1; - uint32_t FRZACK:1; - uint32_t SUPV:1; - uint32_t SLFWAK:1; - uint32_t WRNEN:1; - uint32_t LPMACK:1; - uint32_t WAKSRC:1; - uint32_t DOZE:1; - uint32_t SRXDIS:1; - uint32_t BCC:1; - uint32_t:2; - uint32_t LPRIO_EN:1; - uint32_t AEN:1; - uint32_t:2; - uint32_t IDAM:2; - uint32_t:2; - uint32_t MAXMB:6; - } B; - } MCR; /* Module Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t PRESDIV:8; - uint32_t RJW:2; - uint32_t PSEG1:3; - uint32_t PSEG2:3; - uint32_t BOFFMSK:1; - uint32_t ERRMSK:1; - uint32_t CLKSRC:1; - uint32_t LPB:1; - uint32_t TWRNMSK:1; - uint32_t RWRNMSK:1; - uint32_t:2; - uint32_t SMP:1; - uint32_t BOFFREC:1; - uint32_t TSYN:1; - uint32_t LBUF:1; - uint32_t LOM:1; - uint32_t PROPSEG:3; - } B; - } CTRL; /* Control Register */ - - union { - uint32_t R; - } TIMER; /* Free Running Timer */ - - uint32_t FLEXCAN_reserved1; - - union { - uint32_t R; - struct { - uint32_t MI:32; - } B; - } RXGMASK; /* RX Global Mask */ - - union { - uint32_t R; - struct { - uint32_t MI:32; - } B; - } RX14MASK; /* RX 14 Mask */ - - union { - uint32_t R; - struct { - uint32_t MI:32; - } B; - } RX15MASK; /* RX 15 Mask */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t RXECNT:8; - uint32_t TXECNT:8; - } B; - } ECR; /* Error Counter Register */ - - union { - uint32_t R; - struct { - uint32_t:14; - uint32_t TWRNINT:1; - uint32_t RWRNINT:1; - uint32_t BIT1ERR:1; - uint32_t BIT0ERR:1; - uint32_t ACKERR:1; - uint32_t CRCERR:1; - uint32_t FRMERR:1; - uint32_t STFERR:1; - uint32_t TXWRN:1; - uint32_t RXWRN:1; - uint32_t IDLE:1; - uint32_t TXRX:1; - uint32_t FLTCONF:2; - uint32_t:1; - uint32_t BOFFINT:1; - uint32_t ERRINT:1; - uint32_t WAKINT:1; - } B; - } ESR; /* Error and Status Register */ - - union { - uint32_t R; - struct { - uint32_t BUF63M:1; - uint32_t BUF62M:1; - uint32_t BUF61M:1; - uint32_t BUF60M:1; - uint32_t BUF59M:1; - uint32_t BUF58M:1; - uint32_t BUF57M:1; - uint32_t BUF56M:1; - uint32_t BUF55M:1; - uint32_t BUF54M:1; - uint32_t BUF53M:1; - uint32_t BUF52M:1; - uint32_t BUF51M:1; - uint32_t BUF50M:1; - uint32_t BUF49M:1; - uint32_t BUF48M:1; - uint32_t BUF47M:1; - uint32_t BUF46M:1; - uint32_t BUF45M:1; - uint32_t BUF44M:1; - uint32_t BUF43M:1; - uint32_t BUF42M:1; - uint32_t BUF41M:1; - uint32_t BUF40M:1; - uint32_t BUF39M:1; - uint32_t BUF38M:1; - uint32_t BUF37M:1; - uint32_t BUF36M:1; - uint32_t BUF35M:1; - uint32_t BUF34M:1; - uint32_t BUF33M:1; - uint32_t BUF32M:1; - } B; - } IMASK2; /* Interruput Masks Register */ - - union { - uint32_t R; - struct { - uint32_t BUF31M:1; - uint32_t BUF30M:1; - uint32_t BUF29M:1; - uint32_t BUF28M:1; - uint32_t BUF27M:1; - uint32_t BUF26M:1; - uint32_t BUF25M:1; - uint32_t BUF24M:1; - uint32_t BUF23M:1; - uint32_t BUF22M:1; - uint32_t BUF21M:1; - uint32_t BUF20M:1; - uint32_t BUF19M:1; - uint32_t BUF18M:1; - uint32_t BUF17M:1; - uint32_t BUF16M:1; - uint32_t BUF15M:1; - uint32_t BUF14M:1; - uint32_t BUF13M:1; - uint32_t BUF12M:1; - uint32_t BUF11M:1; - uint32_t BUF10M:1; - uint32_t BUF09M:1; - uint32_t BUF08M:1; - uint32_t BUF07M:1; - uint32_t BUF06M:1; - uint32_t BUF05M:1; - uint32_t BUF04M:1; - uint32_t BUF03M:1; - uint32_t BUF02M:1; - uint32_t BUF01M:1; - uint32_t BUF00M:1; - } B; - } IMASK1; /* Interruput Masks Register */ - - union { - uint32_t R; - struct { - uint32_t BUF63I:1; - uint32_t BUF62I:1; - uint32_t BUF61I:1; - uint32_t BUF60I:1; - uint32_t BUF59I:1; - uint32_t BUF58I:1; - uint32_t BUF57I:1; - uint32_t BUF56I:1; - uint32_t BUF55I:1; - uint32_t BUF54I:1; - uint32_t BUF53I:1; - uint32_t BUF52I:1; - uint32_t BUF51I:1; - uint32_t BUF50I:1; - uint32_t BUF49I:1; - uint32_t BUF48I:1; - uint32_t BUF47I:1; - uint32_t BUF46I:1; - uint32_t BUF45I:1; - uint32_t BUF44I:1; - uint32_t BUF43I:1; - uint32_t BUF42I:1; - uint32_t BUF41I:1; - uint32_t BUF40I:1; - uint32_t BUF39I:1; - uint32_t BUF38I:1; - uint32_t BUF37I:1; - uint32_t BUF36I:1; - uint32_t BUF35I:1; - uint32_t BUF34I:1; - uint32_t BUF33I:1; - uint32_t BUF32I:1; - } B; - } IFLAG2; /* Interruput Flag Register */ - - union { - uint32_t R; - struct { - uint32_t BUF31I:1; - uint32_t BUF30I:1; - uint32_t BUF29I:1; - uint32_t BUF28I:1; - uint32_t BUF27I:1; - uint32_t BUF26I:1; - uint32_t BUF25I:1; - uint32_t BUF24I:1; - uint32_t BUF23I:1; - uint32_t BUF22I:1; - uint32_t BUF21I:1; - uint32_t BUF20I:1; - uint32_t BUF19I:1; - uint32_t BUF18I:1; - uint32_t BUF17I:1; - uint32_t BUF16I:1; - uint32_t BUF15I:1; - uint32_t BUF14I:1; - uint32_t BUF13I:1; - uint32_t BUF12I:1; - uint32_t BUF11I:1; - uint32_t BUF10I:1; - uint32_t BUF09I:1; - uint32_t BUF08I:1; - uint32_t BUF07I:1; - uint32_t BUF06I:1; - uint32_t BUF05I:1; - uint32_t BUF04I:1; - uint32_t BUF03I:1; - uint32_t BUF02I:1; - uint32_t BUF01I:1; - uint32_t BUF00I:1; - } B; - } IFLAG1; /* Interruput Flag Register */ - - uint32_t FLEXCAN_reserved2[19]; - - struct canbuf_t { - union { - uint32_t R; - struct { - uint32_t:4; - uint32_t CODE:4; - uint32_t:1; - uint32_t SRR:1; - uint32_t IDE:1; - uint32_t RTR:1; - uint32_t LENGTH:4; - uint32_t TIMESTAMP:16; - } B; - } CS; - - union { - uint32_t R; - struct { - uint32_t PRIO:3; - uint32_t STD_ID:11; - uint32_t EXT_ID:18; - } B; - } ID; - - union { - /* uint8_t B[8]; Data buffer in Bytes (8 bits) */ - /* uint16_t H[4]; Data buffer in Half-words (16 bits) */ - uint32_t W[2]; /* Data buffer in words (32 bits) */ - /* uint32_t R[2]; Data buffer in words (32 bits) */ - } DATA; - - } BUF[64]; - - uint32_t FLEXCAN_reserved3[256]; - - union { - uint32_t R; - struct { - uint32_t MI:32; - } B; - } RXIMR[64]; /* RX Individual Mask Registers */ - - }; /* end of CTU_tag */ -/**************************************************************************/ -/* MODULE : FlexRay */ -/**************************************************************************/ - - typedef union uMVR { - uint16_t R; - struct { - uint16_t CHIVER:8; /* CHI Version Number */ - uint16_t PEVER:8; /* PE Version Number */ - } B; - } MVR_t; - - typedef union uMCR { - uint16_t R; - struct { - uint16_t MEN:1; /* module enable */ - uint16_t:1; - uint16_t SCMD:1; /* single channel mode */ - uint16_t CHB:1; /* channel B enable */ - uint16_t CHA:1; /* channel A enable */ - uint16_t SFFE:1; /* synchronization frame filter enable */ - uint16_t:5; - uint16_t CLKSEL:1; /* protocol engine clock source select */ - uint16_t PRESCALE:3; /* protocol engine clock prescaler */ - uint16_t:1; - } B; - } MCR_t; - typedef union uSTBSCR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t STBSSEL:7; /* strobe signal select */ - uint16_t:3; - uint16_t ENB:1; /* strobe signal enable */ - uint16_t:2; - uint16_t STBPSEL:2; /* strobe port select */ - } B; - } STBSCR_t; - typedef union uMBDSR { - uint16_t R; - struct { - uint16_t:1; - uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ - uint16_t:1; - uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ - } B; - } MBDSR_t; - - typedef union uMBSSUTR { - uint16_t R; - struct { - - uint16_t:2; - uint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */ - uint16_t:2; - uint16_t LAST_MB_UTIL:6; /* last message buffer utilized */ - } B; - } MBSSUTR_t; - - typedef union uPOCR { - uint16_t R; - uint8_t byte[2]; - struct { - uint16_t WME:1; /* write mode external correction command */ - uint16_t:3; - uint16_t EOC_AP:2; /* external offset correction application */ - uint16_t ERC_AP:2; /* external rate correction application */ - uint16_t BSY:1; /* command write busy / write mode command */ - uint16_t:3; - uint16_t POCCMD:4; /* protocol command */ - } B; - } POCR_t; -/* protocol commands */ - typedef union uGIFER { - uint16_t R; - struct { - uint16_t MIF:1; /* module interrupt flag */ - uint16_t PRIF:1; /* protocol interrupt flag */ - uint16_t CHIF:1; /* CHI interrupt flag */ - uint16_t WKUPIF:1; /* wakeup interrupt flag */ - uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ - uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ - uint16_t RBIF:1; /* receive message buffer interrupt flag */ - uint16_t TBIF:1; /* transmit buffer interrupt flag */ - uint16_t MIE:1; /* module interrupt enable */ - uint16_t PRIE:1; /* protocol interrupt enable */ - uint16_t CHIE:1; /* CHI interrupt enable */ - uint16_t WKUPIE:1; /* wakeup interrupt enable */ - uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ - uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ - uint16_t RBIE:1; /* receive message buffer interrupt enable */ - uint16_t TBIE:1; /* transmit buffer interrupt enable */ - } B; - } GIFER_t; - typedef union uPIFR0 { - uint16_t R; - struct { - uint16_t FATLIF:1; /* fatal protocol error interrupt flag */ - uint16_t INTLIF:1; /* internal protocol error interrupt flag */ - uint16_t ILCFIF:1; /* illegal protocol configuration flag */ - uint16_t CSAIF:1; /* cold start abort interrupt flag */ - uint16_t MRCIF:1; /* missing rate correctio interrupt flag */ - uint16_t MOCIF:1; /* missing offset correctio interrupt flag */ - uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ - uint16_t MXSIF:1; /* max sync frames detected interrupt flag */ - uint16_t MTXIF:1; /* media access test symbol received flag */ - uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ - uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ - uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ - uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ - uint16_t TI2IF:1; /* timer 2 expired interrupt flag */ - uint16_t TI1IF:1; /* timer 1 expired interrupt flag */ - uint16_t CYSIF:1; /* cycle start interrupt flag */ - } B; - } PIFR0_t; - typedef union uPIFR1 { - uint16_t R; - struct { - uint16_t EMCIF:1; /* error mode changed interrupt flag */ - uint16_t IPCIF:1; /* illegal protocol command interrupt flag */ - uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ - uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ - uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ - uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ - uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ - uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ - uint16_t:2; - uint16_t EVTIF:1; /* even cycle table written interrupt flag */ - uint16_t ODTIF:1; /* odd cycle table written interrupt flag */ - uint16_t:4; - } B; - } PIFR1_t; - typedef union uPIER0 { - uint16_t R; - struct { - uint16_t FATLIE:1; /* fatal protocol error interrupt enable */ - uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ - uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ - uint16_t CSAIE:1; /* cold start abort interrupt enable */ - uint16_t MRCIE:1; /* missing rate correctio interrupt enable */ - uint16_t MOCIE:1; /* missing offset correctio interrupt enable */ - uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ - uint16_t MXSIE:1; /* max sync frames detected interrupt enable */ - uint16_t MTXIE:1; /* media access test symbol received interrupt enable */ - uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ - uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ - uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ - uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ - uint16_t TI2IE:1; /* timer 2 expired interrupt enable */ - uint16_t TI1IE:1; /* timer 1 expired interrupt enable */ - uint16_t CYSIE:1; /* cycle start interrupt enable */ - } B; - } PIER0_t; - typedef union uPIER1 { - uint16_t R; - struct { - uint16_t EMCIE:1; /* error mode changed interrupt enable */ - uint16_t IPCIE:1; /* illegal protocol command interrupt enable */ - uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ - uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ - uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ - uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ - uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ - uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ - uint16_t:2; - uint16_t EVTIE:1; /* even cycle table written interrupt enable */ - uint16_t ODTIE:1; /* odd cycle table written interrupt enable */ - uint16_t:4; - } B; - } PIER1_t; - typedef union uCHIERFR { - uint16_t R; - struct { - uint16_t FRLBEF:1; /* flame lost channel B error flag */ - uint16_t FRLAEF:1; /* frame lost channel A error flag */ - uint16_t PCMIEF:1; /* command ignored error flag */ - uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ - uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ - uint16_t MSBEF:1; /* message buffer search error flag */ - uint16_t MBUEF:1; /* message buffer utilization error flag */ - uint16_t LCKEF:1; /* lock error flag */ - uint16_t DBLEF:1; /* double transmit message buffer lock error flag */ - uint16_t SBCFEF:1; /* system bus communication failure error flag */ - uint16_t FIDEF:1; /* frame ID error flag */ - uint16_t DPLEF:1; /* dynamic payload length error flag */ - uint16_t SPLEF:1; /* static payload length error flag */ - uint16_t NMLEF:1; /* network management length error flag */ - uint16_t NMFEF:1; /* network management frame error flag */ - uint16_t ILSAEF:1; /* illegal access error flag */ - } B; - } CHIERFR_t; - typedef union uMBIVEC { - uint16_t R; - struct { - - uint16_t:2; - uint16_t TBIVEC:6; /* transmit buffer interrupt vector */ - uint16_t:2; - uint16_t RBIVEC:6; /* receive buffer interrupt vector */ - } B; - } MBIVEC_t; - - typedef union uPSR0 { - uint16_t R; - struct { - uint16_t ERRMODE:2; /* error mode */ - uint16_t SLOTMODE:2; /* slot mode */ - uint16_t:1; - uint16_t PROTSTATE:3; /* protocol state */ - uint16_t SUBSTATE:4; /* protocol sub state */ - uint16_t:1; - uint16_t WAKEUPSTATUS:3; /* wakeup status */ - } B; - } PSR0_t; - -/* protocol states */ -/* protocol sub-states */ -/* wakeup status */ - typedef union uPSR1 { - uint16_t R; - struct { - uint16_t CSAA:1; /* cold start attempt abort flag */ - uint16_t SCP:1; /* cold start path */ - uint16_t:1; - uint16_t REMCSAT:5; /* remanining coldstart attempts */ - uint16_t CPN:1; /* cold start noise path */ - uint16_t HHR:1; /* host halt request pending */ - uint16_t FRZ:1; /* freeze occured */ - uint16_t APTAC:5; /* allow passive to active counter */ - } B; - } PSR1_t; - typedef union uPSR2 { - uint16_t R; - struct { - uint16_t NBVB:1; /* NIT boundary violation on channel B */ - uint16_t NSEB:1; /* NIT syntax error on channel B */ - uint16_t STCB:1; /* symbol window transmit conflict on channel B */ - uint16_t SBVB:1; /* symbol window boundary violation on channel B */ - uint16_t SSEB:1; /* symbol window syntax error on channel B */ - uint16_t MTB:1; /* media access test symbol MTS received on channel B */ - uint16_t NBVA:1; /* NIT boundary violation on channel A */ - uint16_t NSEA:1; /* NIT syntax error on channel A */ - uint16_t STCA:1; /* symbol window transmit conflict on channel A */ - uint16_t SBVA:1; /* symbol window boundary violation on channel A */ - uint16_t SSEA:1; /* symbol window syntax error on channel A */ - uint16_t MTA:1; /* media access test symbol MTS received on channel A */ - uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ - } B; - } PSR2_t; - typedef union uPSR3 { - uint16_t R; - struct { - uint16_t:2; - uint16_t WUB:1; /* wakeup symbol received on channel B */ - uint16_t ABVB:1; /* aggregated boundary violation on channel B */ - uint16_t AACB:1; /* aggregated additional communication on channel B */ - uint16_t ACEB:1; /* aggregated content error on channel B */ - uint16_t ASEB:1; /* aggregated syntax error on channel B */ - uint16_t AVFB:1; /* aggregated valid frame on channel B */ - uint16_t:2; - uint16_t WUA:1; /* wakeup symbol received on channel A */ - uint16_t ABVA:1; /* aggregated boundary violation on channel A */ - uint16_t AACA:1; /* aggregated additional communication on channel A */ - uint16_t ACEA:1; /* aggregated content error on channel A */ - uint16_t ASEA:1; /* aggregated syntax error on channel A */ - uint16_t AVFA:1; /* aggregated valid frame on channel A */ - } B; - } PSR3_t; - typedef union uCIFRR { - uint16_t R; - struct { - uint16_t:8; - uint16_t MIFR:1; /* module interrupt flag */ - uint16_t PRIFR:1; /* protocol interrupt flag */ - uint16_t CHIFR:1; /* CHI interrupt flag */ - uint16_t WUPIFR:1; /* wakeup interrupt flag */ - uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ - uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ - uint16_t RBIFR:1; /* receive message buffer interrupt flag */ - uint16_t TBIFR:1; /* transmit buffer interrupt flag */ - } B; - } CIFRR_t; - typedef union uSYMATOR { - uint16_t R; - struct { - uint16_t:11; - uint16_t TIMEOUT:5; /* system memory time out value */ - } B; - } SYMATOR_t; - - typedef union uSFCNTR { - uint16_t R; - struct { - uint16_t SFEVB:4; /* sync frames channel B, even cycle */ - uint16_t SFEVA:4; /* sync frames channel A, even cycle */ - uint16_t SFODB:4; /* sync frames channel B, odd cycle */ - uint16_t SFODA:4; /* sync frames channel A, odd cycle */ - } B; - } SFCNTR_t; - - typedef union uSFTCCSR { - uint16_t R; - struct { - uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ - uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ - uint16_t CYCNUM:6; /* cycle number */ - uint16_t ELKS:1; /* even cycle tables lock status */ - uint16_t OLKS:1; /* odd cycle tables lock status */ - uint16_t EVAL:1; /* even cycle tables valid */ - uint16_t OVAL:1; /* odd cycle tables valid */ - uint16_t:1; - uint16_t OPT:1; /*one pair trigger */ - uint16_t SDVEN:1; /* sync frame deviation table enable */ - uint16_t SIDEN:1; /* sync frame ID table enable */ - } B; - } SFTCCSR_t; - typedef union uSFIDRFR { - uint16_t R; - struct { - uint16_t:6; - uint16_t SYNFRID:10; /* sync frame rejection ID */ - } B; - } SFIDRFR_t; - - typedef union uTICCR { - uint16_t R; - struct { - uint16_t:2; - uint16_t T2CFG:1; /* timer 2 configuration */ - uint16_t T2REP:1; /* timer 2 repetitive mode */ - uint16_t:1; - uint16_t T2SP:1; /* timer 2 stop */ - uint16_t T2TR:1; /* timer 2 trigger */ - uint16_t T2ST:1; /* timer 2 state */ - uint16_t:3; - uint16_t T1REP:1; /* timer 1 repetitive mode */ - uint16_t:1; - uint16_t T1SP:1; /* timer 1 stop */ - uint16_t T1TR:1; /* timer 1 trigger */ - uint16_t T1ST:1; /* timer 1 state */ - - } B; - } TICCR_t; - typedef union uTI1CYSR { - uint16_t R; - struct { - uint16_t:2; - uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ - uint16_t:2; - uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ - - } B; - } TI1CYSR_t; - - typedef union uSSSR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t:1; - uint16_t SEL:2; /* static slot number */ - uint16_t:1; - uint16_t SLOTNUMBER:11; /* selector */ - } B; - } SSSR_t; - - typedef union uSSCCR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t:1; - uint16_t SEL:2; /* selector */ - uint16_t:1; - uint16_t CNTCFG:2; /* counter configuration */ - uint16_t MCY:1; /* multi cycle selection */ - uint16_t VFR:1; /* valid frame selection */ - uint16_t SYF:1; /* sync frame selection */ - uint16_t NUF:1; /* null frame selection */ - uint16_t SUF:1; /* startup frame selection */ - uint16_t STATUSMASK:4; /* slot status mask */ - } B; - } SSCCR_t; - typedef union uSSR { - uint16_t R; - struct { - uint16_t VFB:1; /* valid frame on channel B */ - uint16_t SYB:1; /* valid sync frame on channel B */ - uint16_t NFB:1; /* valid null frame on channel B */ - uint16_t SUB:1; /* valid startup frame on channel B */ - uint16_t SEB:1; /* syntax error on channel B */ - uint16_t CEB:1; /* content error on channel B */ - uint16_t BVB:1; /* boundary violation on channel B */ - uint16_t TCB:1; /* tx conflict on channel B */ - uint16_t VFA:1; /* valid frame on channel A */ - uint16_t SYA:1; /* valid sync frame on channel A */ - uint16_t NFA:1; /* valid null frame on channel A */ - uint16_t SUA:1; /* valid startup frame on channel A */ - uint16_t SEA:1; /* syntax error on channel A */ - uint16_t CEA:1; /* content error on channel A */ - uint16_t BVA:1; /* boundary violation on channel A */ - uint16_t TCA:1; /* tx conflict on channel A */ - } B; - } SSR_t; - typedef union uMTSCFR { - uint16_t R; - struct { - uint16_t MTE:1; /* media access test symbol transmission enable */ - uint16_t:1; - uint16_t CYCCNTMSK:6; /* cycle counter mask */ - uint16_t:2; - uint16_t CYCCNTVAL:6; /* cycle counter value */ - } B; - } MTSCFR_t; - - typedef union uRSBIR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t:1; - uint16_t SEL:2; /* selector */ - uint16_t:5; - uint16_t RSBIDX:7; /* receive shadow buffer index */ - } B; - } RSBIR_t; - - typedef union uRFDSR { - uint16_t R; - struct { - uint16_t FIFODEPTH:8; /* fifo depth */ - uint16_t:1; - uint16_t ENTRYSIZE:7; /* entry size */ - } B; - } RFDSR_t; - - typedef union uRFRFCFR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t IBD:1; /* interval boundary */ - uint16_t SEL:2; /* filter number */ - uint16_t:1; - uint16_t SID:11; /* slot ID */ - } B; - } RFRFCFR_t; - - typedef union uRFRFCTR { - uint16_t R; - struct { - uint16_t:4; - uint16_t F3MD:1; /* filter mode */ - uint16_t F2MD:1; /* filter mode */ - uint16_t F1MD:1; /* filter mode */ - uint16_t F0MD:1; /* filter mode */ - uint16_t:4; - uint16_t F3EN:1; /* filter enable */ - uint16_t F2EN:1; /* filter enable */ - uint16_t F1EN:1; /* filter enable */ - uint16_t F0EN:1; /* filter enable */ - } B; - } RFRFCTR_t; - typedef union uPCR0 { - uint16_t R; - struct { - uint16_t ACTION_POINT_OFFSET:6; - uint16_t STATIC_SLOT_LENGTH:10; - } B; - } PCR0_t; - - typedef union uPCR1 { - uint16_t R; - struct { - uint16_t:2; - uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; - } B; - } PCR1_t; - - typedef union uPCR2 { - uint16_t R; - struct { - uint16_t MINISLOT_AFTER_ACTION_POINT:6; - uint16_t NUMBER_OF_STATIC_SLOTS:10; - } B; - } PCR2_t; - - typedef union uPCR3 { - uint16_t R; - struct { - uint16_t WAKEUP_SYMBOL_RX_LOW:6; - uint16_t MINISLOT_ACTION_POINT_OFFSET:5; - uint16_t COLDSTART_ATTEMPTS:5; - } B; - } PCR3_t; - - typedef union uPCR4 { - uint16_t R; - struct { - uint16_t CAS_RX_LOW_MAX:7; - uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; - } B; - } PCR4_t; - - typedef union uPCR5 { - uint16_t R; - struct { - uint16_t TSS_TRANSMITTER:4; - uint16_t WAKEUP_SYMBOL_TX_LOW:6; - uint16_t WAKEUP_SYMBOL_RX_IDLE:6; - } B; - } PCR5_t; - - typedef union uPCR6 { - uint16_t R; - struct { - uint16_t:1; - uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; - uint16_t MACRO_INITIAL_OFFSET_A:7; - } B; - } PCR6_t; - - typedef union uPCR7 { - uint16_t R; - struct { - uint16_t DECODING_CORRECTION_B:9; - uint16_t MICRO_PER_MACRO_NOM_HALF:7; - } B; - } PCR7_t; - - typedef union uPCR8 { - uint16_t R; - struct { - uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; - uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; - uint16_t WAKEUP_SYMBOL_TX_IDLE:8; - } B; - } PCR8_t; - - typedef union uPCR9 { - uint16_t R; - struct { - uint16_t MINISLOT_EXISTS:1; - uint16_t SYMBOL_WINDOW_EXISTS:1; - uint16_t OFFSET_CORRECTION_OUT:14; - } B; - } PCR9_t; - - typedef union uPCR10 { - uint16_t R; - struct { - uint16_t SINGLE_SLOT_ENABLED:1; - uint16_t WAKEUP_CHANNEL:1; - uint16_t MACRO_PER_CYCLE:14; - } B; - } PCR10_t; - - typedef union uPCR11 { - uint16_t R; - struct { - uint16_t KEY_SLOT_USED_FOR_STARTUP:1; - uint16_t KEY_SLOT_USED_FOR_SYNC:1; - uint16_t OFFSET_CORRECTION_START:14; - } B; - } PCR11_t; - - typedef union uPCR12 { - uint16_t R; - struct { - uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; - uint16_t KEY_SLOT_HEADER_CRC:11; - } B; - } PCR12_t; - - typedef union uPCR13 { - uint16_t R; - struct { - uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; - uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; - } B; - } PCR13_t; - - typedef union uPCR14 { - uint16_t R; - struct { - uint16_t RATE_CORRECTION_OUT:11; - uint16_t LISTEN_TIMEOUT_H:5; - } B; - } PCR14_t; - - typedef union uPCR15 { - uint16_t R; - struct { - uint16_t LISTEN_TIMEOUT_L:16; - } B; - } PCR15_t; - - typedef union uPCR16 { - uint16_t R; - struct { - uint16_t MACRO_INITIAL_OFFSET_B:7; - uint16_t NOISE_LISTEN_TIMEOUT_H:9; - } B; - } PCR16_t; - - typedef union uPCR17 { - uint16_t R; - struct { - uint16_t NOISE_LISTEN_TIMEOUT_L:16; - } B; - } PCR17_t; - - typedef union uPCR18 { - uint16_t R; - struct { - uint16_t WAKEUP_PATTERN:6; - uint16_t KEY_SLOT_ID:10; - } B; - } PCR18_t; - - typedef union uPCR19 { - uint16_t R; - struct { - uint16_t DECODING_CORRECTION_A:9; - uint16_t PAYLOAD_LENGTH_STATIC:7; - } B; - } PCR19_t; - - typedef union uPCR20 { - uint16_t R; - struct { - uint16_t MICRO_INITIAL_OFFSET_B:8; - uint16_t MICRO_INITIAL_OFFSET_A:8; - } B; - } PCR20_t; - - typedef union uPCR21 { - uint16_t R; - struct { - uint16_t EXTERN_RATE_CORRECTION:3; - uint16_t LATEST_TX:13; - } B; - } PCR21_t; - - typedef union uPCR22 { - uint16_t R; - struct { - uint16_t:1; - uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; - uint16_t MICRO_PER_CYCLE_H:4; - } B; - } PCR22_t; - - typedef union uPCR23 { - uint16_t R; - struct { - uint16_t micro_per_cycle_l:16; - } B; - } PCR23_t; - - typedef union uPCR24 { - uint16_t R; - struct { - uint16_t CLUSTER_DRIFT_DAMPING:5; - uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; - uint16_t MICRO_PER_CYCLE_MIN_H:4; - } B; - } PCR24_t; - - typedef union uPCR25 { - uint16_t R; - struct { - uint16_t MICRO_PER_CYCLE_MIN_L:16; - } B; - } PCR25_t; - - typedef union uPCR26 { - uint16_t R; - struct { - uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; - uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; - uint16_t MICRO_PER_CYCLE_MAX_H:4; - } B; - } PCR26_t; - - typedef union uPCR27 { - uint16_t R; - struct { - uint16_t MICRO_PER_CYCLE_MAX_L:16; - } B; - } PCR27_t; - - typedef union uPCR28 { - uint16_t R; - struct { - uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; - uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; - } B; - } PCR28_t; - - typedef union uPCR29 { - uint16_t R; - struct { - uint16_t EXTERN_OFFSET_CORRECTION:3; - uint16_t MINISLOTS_MAX:13; - } B; - } PCR29_t; - - typedef union uPCR30 { - uint16_t R; - struct { - uint16_t:12; - uint16_t SYNC_NODE_MAX:4; - } B; - } PCR30_t; - - typedef struct uMSG_BUFF_CCS { - union { - uint16_t R; - struct { - uint16_t:1; - uint16_t MCM:1; /* message buffer commit mode */ - uint16_t MBT:1; /* message buffer type */ - uint16_t MTD:1; /* message buffer direction */ - uint16_t CMT:1; /* commit for transmission */ - uint16_t EDT:1; /* enable / disable trigger */ - uint16_t LCKT:1; /* lock request trigger */ - uint16_t MBIE:1; /* message buffer interrupt enable */ - uint16_t:3; - uint16_t DUP:1; /* data updated */ - uint16_t DVAL:1; /* data valid */ - uint16_t EDS:1; /* lock status */ - uint16_t LCKS:1; /* enable / disable status */ - uint16_t MBIF:1; /* message buffer interrupt flag */ - } B; - } MBCCSR; - union { - uint16_t R; - struct { - uint16_t MTM:1; /* message buffer transmission mode */ - uint16_t CHNLA:1; /* channel assignement */ - uint16_t CHNLB:1; /* channel assignement */ - uint16_t CCFE:1; /* cycle counter filter enable */ - uint16_t CCFMSK:6; /* cycle counter filter mask */ - uint16_t CCFVAL:6; /* cycle counter filter value */ - } B; - } MBCCFR; - union { - uint16_t R; - struct { - uint16_t:5; - uint16_t FID:11; /* frame ID */ - } B; - } MBFIDR; - - union { - uint16_t R; - struct { - uint16_t:9; - uint16_t MBIDX:7; /* message buffer index */ - } B; - } MBIDXR; - } MSG_BUFF_CCS_t; - typedef union uSYSBADHR { - uint16_t R; - } SYSBADHR_t; - typedef union uSYSBADLR { - uint16_t R; - } SYSBADLR_t; - typedef union uPADR { - uint16_t R; - } PADR_t; - typedef union uPDAR { - uint16_t R; - } PDAR_t; - typedef union uCASERCR { - uint16_t R; - } CASERCR_t; - typedef union uCBSERCR { - uint16_t R; - } CBSERCR_t; - typedef union uCYCTR { - uint16_t R; - } CYCTR_t; - typedef union uMTCTR { - uint16_t R; - } MTCTR_t; - typedef union uSLTCTAR { - uint16_t R; - } SLTCTAR_t; - typedef union uSLTCTBR { - uint16_t R; - } SLTCTBR_t; - typedef union uRTCORVR { - uint16_t R; - } RTCORVR_t; - typedef union uOFCORVR { - uint16_t R; - } OFCORVR_t; - typedef union uSFTOR { - uint16_t R; - } SFTOR_t; - typedef union uSFIDAFVR { - uint16_t R; - } SFIDAFVR_t; - typedef union uSFIDAFMR { - uint16_t R; - } SFIDAFMR_t; - typedef union uNMVR { - uint16_t R; - } NMVR_t; - typedef union uNMVLR { - uint16_t R; - } NMVLR_t; - typedef union uT1MTOR { - uint16_t R; - } T1MTOR_t; - typedef union uTI2CR0 { - uint16_t R; - } TI2CR0_t; - typedef union uTI2CR1 { - uint16_t R; - } TI2CR1_t; - typedef union uSSCR { - uint16_t R; - } SSCR_t; - typedef union uRFSR { - uint16_t R; - } RFSR_t; - typedef union uRFSIR { - uint16_t R; - } RFSIR_t; - typedef union uRFARIR { - uint16_t R; - } RFARIR_t; - typedef union uRFBRIR { - uint16_t R; - } RFBRIR_t; - typedef union uRFMIDAFVR { - uint16_t R; - } RFMIDAFVR_t; - typedef union uRFMIAFMR { - uint16_t R; - } RFMIAFMR_t; - typedef union uRFFIDRFVR { - uint16_t R; - } RFFIDRFVR_t; - typedef union uRFFIDRFMR { - uint16_t R; - } RFFIDRFMR_t; - typedef union uLDTXSLAR { - uint16_t R; - } LDTXSLAR_t; - typedef union uLDTXSLBR { - uint16_t R; - } LDTXSLBR_t; - - typedef struct FR_tag { - volatile MVR_t MVR; /*module version register *//*0 */ - volatile MCR_t MCR; /*module configuration register *//*2 */ - volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ - volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ - volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ - uint16_t reserved0[1]; /*A */ - volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ - volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ - uint16_t reserved1[1]; /*10 */ - uint16_t reserved2[1]; /*12 */ - volatile POCR_t POCR; /*Protocol operation control register *//*14 */ - volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ - volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ - volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ - volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ - volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ - volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ - volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ - volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ - volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ - volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ - volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ - volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ - volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ - volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ - volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ - volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ - volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ - volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ - volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ - volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ - volatile SYMATOR_t SYMATOR; /*system memory acess time-out register *//*3E */ - volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ - volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ - volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ - volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ - volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ - volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ - volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ - volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ - volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ - volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ - volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ - volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ - volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ - volatile SSSR_t SSSR; /*slot status selection register *//*64 */ - volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ - volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ - volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ - volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ - volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ - volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ - volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ - volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ - volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ - volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ - volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ - volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ - volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ - volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ - volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ - volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ - volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ - volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ - volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ - volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ - volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ - volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ - volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ - volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ - volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ - volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ - volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ - volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ - volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ - volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ - volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ - volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ - volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ - volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ - volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ - volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ - volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ - volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ - volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ - volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ - volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ - volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ - volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ - volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ - volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ - volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ - volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ - volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ - volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ - volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ - uint16_t reserved3[17]; - volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ - } FR_tag_t; - - typedef union uF_HEADER /* frame header */ - { - struct { - uint16_t:5; - uint16_t HDCRC:11; /* Header CRC */ - uint16_t:2; - uint16_t CYCCNT:6; /* Cycle Count */ - uint16_t:1; - uint16_t PLDLEN:7; /* Payload Length */ - uint16_t:1; - uint16_t PPI:1; /* Payload Preamble Indicator */ - uint16_t NUF:1; /* Null Frame Indicator */ - uint16_t SYF:1; /* Sync Frame Indicator */ - uint16_t SUF:1; /* Startup Frame Indicator */ - uint16_t FID:11; /* Frame ID */ - } B; - uint16_t WORDS[3]; - } F_HEADER_t; - typedef union uS_STSTUS /* slot status */ - { - struct { - uint16_t VFB:1; /* Valid Frame on channel B */ - uint16_t SYB:1; /* Sync Frame Indicator channel B */ - uint16_t NFB:1; /* Null Frame Indicator channel B */ - uint16_t SUB:1; /* Startup Frame Indicator channel B */ - uint16_t SEB:1; /* Syntax Error on channel B */ - uint16_t CEB:1; /* Content Error on channel B */ - uint16_t BVB:1; /* Boundary Violation on channel B */ - uint16_t CH:1; /* Channel */ - uint16_t VFA:1; /* Valid Frame on channel A */ - uint16_t SYA:1; /* Sync Frame Indicator channel A */ - uint16_t NFA:1; /* Null Frame Indicator channel A */ - uint16_t SUA:1; /* Startup Frame Indicator channel A */ - uint16_t SEA:1; /* Syntax Error on channel A */ - uint16_t CEA:1; /* Content Error on channel A */ - uint16_t BVA:1; /* Boundary Violation on channel A */ - uint16_t:1; - } RX; - struct { - uint16_t VFB:1; /* Valid Frame on channel B */ - uint16_t SYB:1; /* Sync Frame Indicator channel B */ - uint16_t NFB:1; /* Null Frame Indicator channel B */ - uint16_t SUB:1; /* Startup Frame Indicator channel B */ - uint16_t SEB:1; /* Syntax Error on channel B */ - uint16_t CEB:1; /* Content Error on channel B */ - uint16_t BVB:1; /* Boundary Violation on channel B */ - uint16_t TCB:1; /* Tx Conflict on channel B */ - uint16_t VFA:1; /* Valid Frame on channel A */ - uint16_t SYA:1; /* Sync Frame Indicator channel A */ - uint16_t NFA:1; /* Null Frame Indicator channel A */ - uint16_t SUA:1; /* Startup Frame Indicator channel A */ - uint16_t SEA:1; /* Syntax Error on channel A */ - uint16_t CEA:1; /* Content Error on channel A */ - uint16_t BVA:1; /* Boundary Violation on channel A */ - uint16_t TCA:1; /* Tx Conflict on channel A */ - } TX; - uint16_t R; - } S_STATUS_t; - - typedef struct uMB_HEADER /* message buffer header */ - { - F_HEADER_t FRAME_HEADER; - uint16_t DATA_OFFSET; - S_STATUS_t SLOT_STATUS; - } MB_HEADER_t; -/**************************************************************************/ -/* MODULE : FMPLL */ -/**************************************************************************/ - struct FMPLL_tag { - - uint32_t FMPLL_reserved0; - - union FMPLL_SYNSR_tag { /* Synthesiser Status Register */ - uint32_t R; - struct { - uint32_t:22; - uint32_t LOLF:1; - uint32_t LOC:1; - uint32_t MODE:1; - uint32_t PLLSEL:1; - uint32_t PLLREF:1; - uint32_t LOCKS:1; - uint32_t LOCK:1; - uint32_t LOCF:1; - uint32_t CALDONE:1; - uint32_t CALPASS:1; - } B; - } SYNSR; - - union FMPLL_ESYNCR1_tag { - uint32_t R; - struct { - uint32_t:1; - uint32_t CLKCFG:3; - uint32_t:8; - uint32_t EPREDIV:4; - uint32_t:8; - uint32_t EMFD:8; - } B; - } ESYNCR1; - - union FMPLL_ESYNCR2_tag { - uint32_t R; - struct { - uint32_t:8; - uint32_t LOCEN:1; - uint32_t LOLRE:1; - uint32_t LOCRE:1; - uint32_t LOLIRQ:1; - uint32_t LOCIRQ:1; - uint32_t:1; - uint32_t ERATE:2; - uint32_t:5; - uint32_t EDEPTH:3; - uint32_t:2; - uint32_t ERFD:6; - } B; - } ESYNCR2; - - }; -/*************************************************************************/ -/* MODULE : i2c */ -/*************************************************************************/ - struct I2C_tag { - union { - uint8_t R; - struct { - uint8_t AD:7; - uint8_t:1; - } B; - } IBAD; /* Module Bus Address Register */ - - union { - uint8_t R; - struct { - uint8_t MULT:2; - uint8_t ICR:6; - } B; - } IBFD; /* Module Bus Frequency Register */ - - union { - uint8_t R; - struct { - uint8_t MDIS:1; - uint8_t IBIE:1; - uint8_t MS:1; - uint8_t TX:1; - uint8_t NOACK:1; - uint8_t RSTA:1; - uint8_t DMAEN:1; - uint8_t:1; - } B; - } IBCR; /* Module Bus Control Register */ - - union { - uint8_t R; - struct { - uint8_t TCF:1; - uint8_t IAAS:1; - uint8_t IBB:1; - uint8_t IBAL:1; - uint8_t:1; - uint8_t SRW:1; - uint8_t IBIF:1; - uint8_t RXAK:1; - } B; - } IBSR; /* Module Status Register */ - - union { - uint8_t R; - struct { - uint8_t DATA:8; - } B; - } IBDR; /* Module Data Register */ - - union { - uint8_t R; - struct { - uint8_t BIIE:1; - uint8_t:7; - } B; - } IBIC; /* Module Interrupt Configuration Register */ - - }; /* end of i2c_tag */ -/*************************************************************************/ -/* MODULE : INTC */ -/*************************************************************************/ - struct INTC_tag { - union { - uint32_t R; - struct { - uint32_t:18; - uint32_t VTES_PRC1:1; - uint32_t:4; - uint32_t HVEN_PRC1:1; - uint32_t:2; - uint32_t VTES:1; - uint32_t:4; - uint32_t HVEN:1; - } B; - } MCR; /* Module Configuration Register */ - - int32_t INTC_reserved1; - - union { - uint32_t R; - struct { - uint32_t:28; - uint32_t PRI:4; - } B; - } CPR; /* Processor 0 (Z6) Current Priority Register */ - - union { - uint32_t R; - struct { - uint32_t:28; - uint32_t PRI:4; - } B; - } CPR_PRC1; /* Processor 1 (Z0) Current Priority Register */ - - union { - uint32_t R; - struct { - uint32_t VTBA:21; - uint32_t INTVEC:9; - uint32_t:2; - } B; - } IACKR; /* Processor 0 (Z6) Interrupt Acknowledge Register */ - - union { - uint32_t R; - struct { - uint32_t VTBA_PRC1:21; - uint32_t INTVEC_PRC1:9; - uint32_t:2; - } B; - } IACKR_PRC1; /* Processor 1 (Z0) Interrupt Acknowledge Register */ - - union { - uint32_t R; - struct { - uint32_t:32; - } B; - } EOIR; /* Processor 0 End of Interrupt Register */ - - union { - uint32_t R; - struct { - uint32_t:32; - } B; - } EOIR_PRC1; /* Processor 1 End of Interrupt Register */ - - union { - uint8_t R; - struct { - uint8_t:6; - uint8_t SET:1; - uint8_t CLR:1; - } B; - } SSCIR[8]; /* Software Set/Clear Interruput Register */ - - uint32_t intc_reserved2[6]; - - union { - uint8_t R; - struct { - uint8_t PRC_SEL:2; - uint8_t:2; - uint8_t PRI:4; - } B; - } PSR[316]; /* Software Set/Clear Interrupt Register */ - - }; /* end of INTC_tag */ -/*************************************************************************/ -/* MODULE : MLB */ -/*************************************************************************/ - struct MLB_tag { - - union { - uint32_t R; - struct { - uint32_t MDE:1; - uint32_t LBM:1; - uint32_t MCS:2; - uint32_t:1; - uint32_t MLK:1; - uint32_t MLE:1; - uint32_t MHRE:1; - uint32_t MRS:1; - uint32_t:15; - uint32_t MDA:8; - } B; - } DCCR; /* Device Control Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t:24; - uint32_t SSRE:1; - uint32_t SDMU:1; - uint32_t SDML:1; - uint32_t SDSC:1; - uint32_t SDCS:1; - uint32_t SDNU:1; - uint32_t SDNL:1; - uint32_t SDR:1; - } B; - } SSCR; /* MLB Blank Register */ - - union { - uint32_t R; - struct { - uint32_t MSD:32; - } B; - } SDCR; /* MLB Status Register */ - - union { - uint32_t R; - struct { - uint32_t:25; - uint32_t SMMU:1; - uint32_t SMML:1; - uint32_t SMSC:1; - uint32_t SMCS:1; - uint32_t SMNU:1; - uint32_t SMNL:1; - uint32_t SMR:1; - } B; - } SMCR; /* RX Control Channel Address Register */ - - uint32_t MLB_reserved1[3]; - - union { - uint32_t R; - struct { - uint32_t UMA:8; - uint32_t UMI:8; - uint32_t MMA:8; - uint32_t MMI:8; - } B; - } VCCR; /* Version Control Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t SRBA:16; - uint32_t STBA:16; - } B; - } SBCR; /* Sync Base Address Config Register */ - - union { - uint32_t R; - struct { - uint32_t ARBA:16; - uint32_t ATBA:16; - } B; - } ABCR; /* Async Base Address Channel Config Register */ - - union { - uint32_t R; - struct { - uint32_t CRBA:16; - uint32_t CTBA:16; - } B; - } CBCR; /* Control Base Address Config Register */ - - union { - uint32_t R; - struct { - uint32_t IRBA:16; - uint32_t ITBA:16; - } B; - } IBCR; /* Isochronous Base Address Config Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t CSU:16; - } B; - } CICR; /* Channel Interrupt Config Register */ - - uint32_t MLB_reserved2[3]; - - struct mlbch_t { - - union { - uint32_t R; - struct { - uint32_t CE:1; - uint32_t TR:1; - uint32_t CT:2; - uint32_t FSE_FCE:1; - uint32_t MDS:2; - uint32_t:2; - uint32_t MLFS:1; - uint32_t:1; - uint32_t MBE:1; - uint32_t MBS:1; - uint32_t MBD:1; - uint32_t MDB:1; - uint32_t MPE:1; - uint32_t FSCD_IPL:1; - uint32_t IPL:2; - uint32_t FSPC_IPL:5; - uint32_t CA:8; - } B; - } CECR; /* Channel Entry Config Register */ - - union { - uint32_t R; - struct { - uint32_t BM:1; - uint32_t BF:1; - uint32_t:10; - uint32_t IVB:2; - uint32_t GIRB_GB:1; - uint32_t RDY:1; - uint32_t:4; - uint32_t PBS:1; - uint32_t PBD:1; - uint32_t PBDB:1; - uint32_t PBPE:1; - uint32_t:1; - uint32_t LFS:1; - uint32_t HBE:1; - uint32_t BE:1; - uint32_t CBS:1; - uint32_t CBD:1; - uint32_t CBDB:1; - uint32_t CBPE:1; - } B; - } CSCR; /* Channel Status Config Register */ - - union { - uint32_t R; - struct { - uint32_t BCA:16; - uint32_t BFA:16; - } B; - } CCBCR; /* Channel Current Buffer Config Register */ - - union { - uint32_t R; - struct { - uint32_t BSA:16; - uint32_t BEA:16; - } B; - } CNBCR; /* Channel Next Buffer Config Register */ - - } CH[16]; - - uint32_t MLB_reserved3[80]; - - union { - uint32_t R; - struct { - uint32_t BSA:16; - uint32_t BEA:16; - } B; - } LCBCR[16]; /* Local Channel Buffer Config Register */ - - }; /* end of MLB_tag */ -/*************************************************************************/ -/* MODULE : MPU */ -/*************************************************************************/ - struct MPU_tag { - union { - uint32_t R; - struct { - uint32_t MPERR:8; - uint32_t:4; - uint32_t HRL:4; - uint32_t NSP:4; - uint32_t NGRD:4; - uint32_t:7; - uint32_t VLD:1; - } B; - } CESR; /* Module Control/Error Status Register */ - - uint32_t mpu_reserved1[3]; - - union { - uint32_t R; - struct { - uint32_t EADDR:32; - } B; - } EAR0; /* Error Address Register */ - - union { - uint32_t R; - struct { - uint32_t EACD:16; - uint32_t EPID:8; - uint32_t EMN:4; - uint32_t EATTR:3; - uint32_t ERW:1; - } B; - } EDR0; /* Error Detail Register */ - - union { - uint32_t R; - struct { - uint32_t EADDR:32; - } B; - } EAR1; - - union { - uint32_t R; - struct { - uint32_t EACD:16; - uint32_t EPID:8; - uint32_t EMN:4; - uint32_t EATTR:3; - uint32_t ERW:1; - } B; - } EDR1; - - union { - uint32_t R; - struct { - uint32_t EADDR:32; - } B; - } EAR2; - - union { - uint32_t R; - struct { - uint32_t EACD:16; - uint32_t EPID:8; - uint32_t EMN:4; - uint32_t EATTR:3; - uint32_t ERW:1; - } B; - } EDR3; - - union { - uint32_t R; - struct { - uint32_t EADDR:32; - } B; - } EAR3; - - union { - uint32_t R; - struct { - uint32_t EACD:16; - uint32_t EPID:8; - uint32_t EMN:4; - uint32_t EATTR:3; - uint32_t ERW:1; - } B; - } EDR2; - - uint32_t mpu_reserved2[244]; - - struct { - union { - uint32_t R; - struct { - uint32_t SRTADDR:27; - uint32_t:5; - } B; - } WORD0; /* Region Descriptor n Word 0 */ - - union { - uint32_t R; - struct { - uint32_t ENDADDR:27; - uint32_t:5; - } B; - } WORD1; /* Region Descriptor n Word 1 */ - - union { - uint32_t R; - struct { - uint32_t:2; - uint32_t M6RE:1; - uint32_t M6WE:1; - uint32_t M5RE:1; - uint32_t M5WE:1; - uint32_t M4RE:1; - uint32_t M4WE:1; - uint32_t:6; - uint32_t M2PE:1; - uint32_t M2SM:2; - uint32_t M2UM:3; - uint32_t M1PE:1; - uint32_t M1SM:2; - uint32_t M1UM:3; - uint32_t M0PE:1; - uint32_t M0SM:2; - uint32_t M0UM:3; - } B; - } WORD2; /* Region Descriptor n Word 2 */ - - union { - uint32_t R; - struct { - uint32_t PID:8; - uint32_t PIDMASK:8; - uint32_t:15; - uint32_t VLD:1; - } B; - } WORD3; /* Region Descriptor n Word 3 */ - - } RGD[16]; - - uint32_t mpu_reserved3[192]; - - union { - uint32_t R; - struct { - uint32_t:2; - uint32_t M6RE:1; - uint32_t M6WE:1; - uint32_t M5RE:1; - uint32_t M5WE:1; - uint32_t M4RE:1; - uint32_t M4WE:1; - uint32_t:6; - uint32_t M2PE:1; - uint32_t M2SM:2; - uint32_t M2UM:3; - uint32_t M1PE:1; - uint32_t M1SM:2; - uint32_t M1UM:3; - uint32_t M0PE:1; - uint32_t M0SM:2; - uint32_t M0UM:3; - } B; - } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */ - }; -/**************************************************************************/ -/* MODULE : pit */ -/**************************************************************************/ - struct PIT_tag { - - union PIT_MCR_tag { - uint32_t R; - struct { - uint32_t:30; - uint32_t MDIS:1; - uint32_t FRZ:1; - } B; - } PITMCR; - - uint32_t pit_reserved1[59]; - - struct PIT_CHANNEL_tag { - union { - uint32_t R; - struct { - uint32_t TSV:32; - } B; - } LDVAL; - - union { - uint32_t R; - struct { - uint32_t TVL:32; - } B; - } CVAL; - - union PIT_TCTRL_tag { - uint32_t R; - struct { - uint32_t:30; - uint32_t TIE:1; - uint32_t TEN:1; - } B; - } TCTRL; - - union PIT_TFLG_tag { - uint32_t R; - struct { - uint32_t:31; - uint32_t TIF:1; - } B; - } TFLG; - } CHANNEL[9]; - }; - - /* Compatibility with MPC5643L */ - typedef struct PIT_CHANNEL_tag PIT_RTI_CHANNEL_tag; - typedef union PIT_MCR_tag PIT_RTI_PITMCR_32B_tag; - typedef union PIT_TCTRL_tag PIT_RTI_TCTRL_32B_tag; - typedef union PIT_TFLG_tag PIT_RTI_TFLG_32B_tag; -/**************************************************************************/ -/* MODULE : sem4 */ -/**************************************************************************/ - struct SEMA4_tag { - union { - uint8_t R; - struct { - uint8_t:6; - uint8_t GTFSM:2; - } B; - } GATE[16]; /* Gate n Register */ - - uint32_t sema4_reserved1[12]; /* {0x40-0x10}/4 = 0x0C */ - - union { - uint16_t R; - struct { - uint16_t INE0:1; - uint16_t INE1:1; - uint16_t INE2:1; - uint16_t INE3:1; - uint16_t INE4:1; - uint16_t INE5:1; - uint16_t INE6:1; - uint16_t INE7:1; - uint16_t INE8:1; - uint16_t INE9:1; - uint16_t INE10:1; - uint16_t INE11:1; - uint16_t INE12:1; - uint16_t INE13:1; - uint16_t INE14:1; - uint16_t INE15:1; - } B; - } CP0INE; - - uint16_t sema4_reserved2[3]; /* {0x48-0x42}/2 = 0x03 */ - - union { - uint16_t R; - struct { - uint16_t INE0:1; - uint16_t INE1:1; - uint16_t INE2:1; - uint16_t INE3:1; - uint16_t INE4:1; - uint16_t INE5:1; - uint16_t INE6:1; - uint16_t INE7:1; - uint16_t INE8:1; - uint16_t INE9:1; - uint16_t INE10:1; - uint16_t INE11:1; - uint16_t INE12:1; - uint16_t INE13:1; - uint16_t INE14:1; - uint16_t INE15:1; - } B; - } CP1INE; - - uint16_t sema4_reserved3[27]; /* {0x80-0x4A}/2 = 0x1B */ - - union { - uint16_t R; - struct { - uint16_t GN0:1; - uint16_t GN1:1; - uint16_t GN2:1; - uint16_t GN3:1; - uint16_t GN4:1; - uint16_t GN5:1; - uint16_t GN6:1; - uint16_t GN7:1; - uint16_t GN8:1; - uint16_t GN9:1; - uint16_t GN10:1; - uint16_t GN11:1; - uint16_t GN12:1; - uint16_t GN13:1; - uint16_t GN14:1; - uint16_t GN15:1; - } B; - } CP0NTF; - - uint16_t sema4_reserved4[3]; /* {0x88-0x82}/2 = 0x03 */ - - union { - uint16_t R; - struct { - uint16_t GN0:1; - uint16_t GN1:1; - uint16_t GN2:1; - uint16_t GN3:1; - uint16_t GN4:1; - uint16_t GN5:1; - uint16_t GN6:1; - uint16_t GN7:1; - uint16_t GN8:1; - uint16_t GN9:1; - uint16_t GN10:1; - uint16_t GN11:1; - uint16_t GN12:1; - uint16_t GN13:1; - uint16_t GN14:1; - uint16_t GN15:1; - } B; - } CP1NTF; - - uint16_t sema4_reserved5[59]; /* {0x100-0x8A}/2 = 0x3B */ - - union { - uint16_t R; - struct { - uint16_t:2; - uint16_t RSTGSM:2; - uint16_t:1; - uint16_t RSTGMS:3; - uint16_t RSTGTN:8; - } B; - } RSTGT; - - uint16_t sema4_reserved6; - - union { - uint16_t R; - struct { - uint16_t:2; - uint16_t RSTNSM:2; - uint16_t:1; - uint16_t RSTNMS:3; - uint16_t RSTNTN:8; - } B; - } RSTNTF; - }; -/*************************************************************************/ -/* MODULE : SIU */ -/*************************************************************************/ - struct SIU_tag { - - int32_t SIU_reserved0; - - union { - uint32_t R; - struct { - uint32_t PARTNUM:16; - uint32_t CSP:1; - uint32_t PKG:5; - uint32_t:2; - uint32_t MASKNUM_MAJOR:4; - uint32_t MASKNUM_MINOR:4; - } B; - } MIDR; /* MCU ID Register */ - - int32_t SIU_reserved1; - - union { - uint32_t R; - struct { - uint32_t PORS:1; - uint32_t ERS:1; - uint32_t LLRS:1; - uint32_t LCRS:1; - uint32_t WDRS:1; - uint32_t CRS:1; - uint32_t:8; - uint32_t SSRS:1; - uint32_t:15; - uint32_t BOOTCFG:1; - uint32_t:1; - } B; - } RSR; /* Reset Status Register */ - - union { - uint32_t R; - struct { - uint32_t SSR:1; - uint32_t:15; - uint32_t CRE0:1; - uint32_t CRE1:1; - uint32_t:6; - uint32_t SSRL:1; - uint32_t:7; - } B; - } SRCR; /* System Reset Control Register */ - - union { - uint32_t R; - struct { - uint32_t NMI0:1; - uint32_t NMI1:1; - uint32_t:14; - uint32_t EIF15:1; - uint32_t EIF14:1; - uint32_t EIF13:1; - uint32_t EIF12:1; - uint32_t EIF11:1; - uint32_t EIF10:1; - uint32_t EIF9:1; - uint32_t EIF8:1; - uint32_t EIF7:1; - uint32_t EIF6:1; - uint32_t EIF5:1; - uint32_t EIF4:1; - uint32_t EIF3:1; - uint32_t EIF2:1; - uint32_t EIF1:1; - uint32_t EIF0:1; - } B; - } EISR; /* External Interrupt Status Register */ - - union SIU_DIRER_tag { - uint32_t R; - struct { - uint32_t:16; - uint32_t EIRE15:1; - uint32_t EIRE14:1; - uint32_t EIRE13:1; - uint32_t EIRE12:1; - uint32_t EIRE11:1; - uint32_t EIRE10:1; - uint32_t EIRE9:1; - uint32_t EIRE8:1; - uint32_t EIRE7:1; - uint32_t EIRE6:1; - uint32_t EIRE5:1; - uint32_t EIRE4:1; - uint32_t EIRE3:1; - uint32_t EIRE2:1; - uint32_t EIRE1:1; - uint32_t EIRE0:1; - } B; - } DIRER; /* DMA/Interrupt Request Enable Register */ - - union SIU_DIRSR_tag { - uint32_t R; - struct { - uint32_t:30; - uint32_t DIRS1:1; - uint32_t DIRS0:1; - } B; - } DIRSR; /* DMA/Interrupt Select Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t OVF15:1; - uint32_t OVF14:1; - uint32_t OVF13:1; - uint32_t OVF12:1; - uint32_t OVF11:1; - uint32_t OVF10:1; - uint32_t OVF9:1; - uint32_t OVF8:1; - uint32_t OVF7:1; - uint32_t OVF6:1; - uint32_t OVF5:1; - uint32_t OVF4:1; - uint32_t OVF3:1; - uint32_t OVF2:1; - uint32_t OVF1:1; - uint32_t OVF0:1; - } B; - } OSR; /* Overrun Status Register */ - - union SIU_ORER_tag { - uint32_t R; - struct { - uint32_t:16; - uint32_t ORE15:1; - uint32_t ORE14:1; - uint32_t ORE13:1; - uint32_t ORE12:1; - uint32_t ORE11:1; - uint32_t ORE10:1; - uint32_t ORE9:1; - uint32_t ORE8:1; - uint32_t ORE7:1; - uint32_t ORE6:1; - uint32_t ORE5:1; - uint32_t ORE4:1; - uint32_t ORE3:1; - uint32_t ORE2:1; - uint32_t ORE1:1; - uint32_t ORE0:1; - } B; - } ORER; /* Overrun Request Enable Register */ - - union SIU_IREER_tag { - uint32_t R; - struct { - uint32_t NREE0:1; - uint32_t NREE1:1; - uint32_t:14; - uint32_t IREE15:1; - uint32_t IREE14:1; - uint32_t IREE13:1; - uint32_t IREE12:1; - uint32_t IREE11:1; - uint32_t IREE10:1; - uint32_t IREE9:1; - uint32_t IREE8:1; - uint32_t IREE7:1; - uint32_t IREE6:1; - uint32_t IREE5:1; - uint32_t IREE4:1; - uint32_t IREE3:1; - uint32_t IREE2:1; - uint32_t IREE1:1; - uint32_t IREE0:1; - } B; - } IREER; /* External IRQ Rising-Edge Event Enable Register */ - - union SIU_IFEER_tag { - uint32_t R; - struct { - uint32_t NFEE0:1; - uint32_t NFEE1:1; - uint32_t:14; - uint32_t IFEE15:1; - uint32_t IFEE14:1; - uint32_t IFEE13:1; - uint32_t IFEE12:1; - uint32_t IFEE11:1; - uint32_t IFEE10:1; - uint32_t IFEE9:1; - uint32_t IFEE8:1; - uint32_t IFEE7:1; - uint32_t IFEE6:1; - uint32_t IFEE5:1; - uint32_t IFEE4:1; - uint32_t IFEE3:1; - uint32_t IFEE2:1; - uint32_t IFEE1:1; - uint32_t IFEE0:1; - } B; - } IFEER; /* External IRQ Falling-Edge Event Enable Register */ - - union SIU_IDFR_tag { - uint32_t R; - struct { - uint32_t:28; - uint32_t DFL:4; - } B; - } IDFR; /* External IRQ Digital Filter Register */ - - union { - uint32_t R; - struct { - uint32_t FNMI0:1; - uint32_t FNMI1:1; - uint32_t:14; - uint32_t FI15:1; - uint32_t FI14:1; - uint32_t FI13:1; - uint32_t FI12:1; - uint32_t FI11:1; - uint32_t FI10:1; - uint32_t FI9:1; - uint32_t FI8:1; - uint32_t FI7:1; - uint32_t FI6:1; - uint32_t FI5:1; - uint32_t FI4:1; - uint32_t FI3:1; - uint32_t FI2:1; - uint32_t FI1:1; - uint32_t FI0:1; - } B; - } IFIR; /* External IRQ Filtered Input Register */ - - int32_t SIU_reserved2[2]; - - union SIU_PCR_tag { - uint16_t R; - struct { - uint16_t:4; - uint16_t PA:2; - uint16_t OBE:1; - uint16_t IBE:1; - uint16_t DSC:2; - uint16_t ODE:1; - uint16_t HYS:1; - uint16_t SRC:2; - uint16_t WPE:1; - uint16_t WPS:1; - } B; - } PCR[155]; /* Pad Configuration Registers */ - - int32_t SIU_reserved3[290]; - - union { - uint8_t R; - struct { - uint8_t:7; - uint8_t PDO:1; - } B; - } GPDO[155]; /* GPIO Pin Data Output Registers */ - - int8_t SIU_reserved4[357]; - - union { - uint8_t R; - struct { - uint8_t:7; - uint8_t PDI:1; - } B; - } GPDI[155]; /* GPIO Pin Data Input Registers */ - - int32_t SIU_reserved5[26]; - - union { - uint32_t R; - struct { - uint32_t ESEL15:2; - uint32_t ESEL14:2; - uint32_t ESEL13:2; - uint32_t ESEL12:2; - uint32_t ESEL11:2; - uint32_t ESEL10:2; - uint32_t ESEL9:2; - uint32_t ESEL8:2; - uint32_t ESEL7:2; - uint32_t ESEL6:2; - uint32_t ESEL5:2; - uint32_t ESEL4:2; - uint32_t ESEL3:2; - uint32_t ESEL2:2; - uint32_t ESEL1:2; - uint32_t ESEL0:2; - } B; - } ISEL1; /* IMUX Register */ - - union { - uint32_t R; - struct { - uint32_t ESEL15:2; - uint32_t ESEL14:2; - uint32_t ESEL13:2; - uint32_t ESEL12:2; - uint32_t ESEL11:2; - uint32_t ESEL10:2; - uint32_t ESEL9:2; - uint32_t ESEL8:2; - uint32_t ESEL7:2; - uint32_t ESEL6:2; - uint32_t ESEL5:2; - uint32_t ESEL4:2; - uint32_t ESEL3:2; - uint32_t ESEL2:2; - uint32_t ESEL1:2; - uint32_t ESEL0:2; - } B; - } ISEL2; /* IMUX Register */ - - int32_t SIU_reserved6; - - union { - uint32_t R; - struct { - uint32_t:17; - uint32_t TSEL1:7; - uint32_t:1; - uint32_t TSEL0:7; - } B; - } ISEL4; /* IMUX Register */ - - int32_t SIU_reserved7[27]; - - union { - uint32_t R; - struct { - uint32_t:14; - uint32_t MATCH:1; - uint32_t DISNEX:1; - uint32_t:8; - uint32_t TESTLOCK:1; - uint32_t:7; - } B; - } CCR; /* Chip Configuration Register Register */ - - union { - uint32_t R; - struct { - uint32_t:28; - uint32_t ECEN:1; - uint32_t:1; - uint32_t ECDF:2; - } B; - } ECCR; /* External Clock Configuration Register Register */ - - union { - uint32_t R; - } GPR0; /* General Purpose Register 0 */ - - union { - uint32_t R; - } GPR1; /* General Purpose Register 1 */ - - union { - uint32_t R; - } GPR2; /* General Purpose Register 2 */ - - union { - uint32_t R; - } GPR3; /* General Purpose Register 3 */ - - int32_t SIU_reserved8[2]; - - union { - uint32_t R; - struct { - uint32_t SYSCLKSEL:2; - uint32_t SYSCLKDIV:3; - uint32_t:19; - uint32_t LPCLKDIV3:2; - uint32_t LPCLKDIV2:2; - uint32_t LPCLKDIV1:2; - uint32_t LPCLKDIV0:2; - } B; - } SYSCLK; /* System CLock Register */ - - union { - uint32_t R; - struct { - uint32_t:6; - uint32_t HLT6:1; - uint32_t HLT7:1; - uint32_t:1; - uint32_t HLT9:1; - uint32_t HLT10:1; - uint32_t HLT11:1; - uint32_t HLT12:1; - uint32_t HLT13:1; - uint32_t HLT14:1; - uint32_t HLT15:1; - uint32_t HLT16:1; - uint32_t HLT17:1; - uint32_t HLT18:1; - uint32_t HLT19:1; - uint32_t HLT20:1; - uint32_t HLT21:1; - uint32_t HLT22:1; - uint32_t HLT23:1; - uint32_t:2; - uint32_t HLT26:1; - uint32_t HLT27:1; - uint32_t HLT28:1; - uint32_t HLT29:1; - uint32_t:1; - uint32_t HLT31:1; - } B; - } HLT0; /* Halt Register 0 */ - - union { - uint32_t R; - struct { - uint32_t:3; - uint32_t HLT3:1; - uint32_t HLT4:1; - uint32_t:15; - uint32_t HLT20:1; - uint32_t HLT21:1; - uint32_t HLT22:1; - uint32_t HLT23:1; - uint32_t:2; - uint32_t HLT26:1; - uint32_t HLT27:1; - uint32_t HLT28:1; - uint32_t HLT29:1; - uint32_t:2; - } B; - } HLT1; /* Halt Register 1 */ - - union { - uint32_t R; - struct { - uint32_t:6; - uint32_t HLTACK6:1; - uint32_t HLTACK7:1; - uint32_t:1; - uint32_t HLTACK9:1; - uint32_t HLTACK10:1; - uint32_t HLTACK11:1; - uint32_t HLTACK12:1; - uint32_t HLTACK13:1; - uint32_t HLTACK14:1; - uint32_t HLTACK15:1; - uint32_t HLTACK16:1; - uint32_t HLTACK17:1; - uint32_t HLTACK18:1; - uint32_t HLTACK19:1; - uint32_t HLTACK20:1; - uint32_t HLTACK21:1; - uint32_t HLTACK22:1; - uint32_t HLTACK23:1; - uint32_t:2; - uint32_t HLTACK26:1; - uint32_t HLTACK27:1; - uint32_t HLTACK28:1; - uint32_t HLTACK29:1; - uint32_t:1; - uint32_t HLTACK31:1; - } B; - } HLTACK0; /* Halt Acknowledge Register 0 */ - - union { - uint32_t R; - struct { - uint32_t HLTACK0:1; - uint32_t HLTACK1:1; - uint32_t:1; - uint32_t HLTACK3:1; - uint32_t HLTACK4:1; - uint32_t:11; - uint32_t HLTACK20:1; - uint32_t HLTACK21:1; - uint32_t HLTACK22:1; - uint32_t HLTACK23:1; - uint32_t:2; - uint32_t HLTACK26:1; - uint32_t HLTACK27:1; - uint32_t HLTACK28:1; - uint32_t HLTACK29:1; - uint32_t:2; - } B; - } HLTACK1; /* Halt Acknowledge Register 0 */ - - union { - uint32_t R; - struct { - uint32_t EMIOSSEL31:4; - uint32_t EMIOSSEL30:4; - uint32_t EMIOSSEL29:4; - uint32_t EMIOSSEL28:4; - uint32_t EMIOSSEL27:4; - uint32_t EMIOSSEL26:4; - uint32_t EMIOSSEL25:4; - uint32_t EMIOSSEL24:4; - } B; - } EMIOS_SEL0; /* eMIOS Select Register 0 */ - - union { - uint32_t R; - struct { - uint32_t EMIOSSEL23:4; - uint32_t EMIOSSEL22:4; - uint32_t EMIOSSEL21:4; - uint32_t EMIOSSEL20:4; - uint32_t EMIOSSEL19:4; - uint32_t EMIOSSEL18:4; - uint32_t EMIOSSEL17:4; - uint32_t EMIOSSEL16:4; - } B; - } EMIOS_SEL1; /* eMIOS Select Register 1 */ - - union { - uint32_t R; - struct { - uint32_t EMIOSSEL15:4; - uint32_t EMIOSSEL14:4; - uint32_t EMIOSSEL13:4; - uint32_t EMIOSSEL12:4; - uint32_t EMIOSSEL11:4; - uint32_t EMIOSSEL10:4; - uint32_t EMIOSSEL9:4; - uint32_t EMIOSSEL8:4; - } B; - } EMIOS_SEL2; /* eMIOS Select Register 2 */ - - union { - uint32_t R; - struct { - uint32_t EMIOSSEL7:4; - uint32_t EMIOSSEL6:4; - uint32_t EMIOSSEL5:4; - uint32_t EMIOSSEL4:4; - uint32_t EMIOSSEL3:4; - uint32_t EMIOSSEL2:4; - uint32_t EMIOSSEL1:4; - uint32_t EMIOSSEL0:4; - } B; - } EMIOS_SEL3; /* eMIOS Select Register 3 */ - - union { - uint32_t R; - struct { - uint32_t ESEL15:2; - uint32_t ESEL14:2; - uint32_t ESEL13:2; - uint32_t ESEL12:2; - uint32_t ESEL11:2; - uint32_t ESEL10:2; - uint32_t ESEL9:2; - uint32_t ESEL8:2; - uint32_t ESEL7:2; - uint32_t ESEL6:2; - uint32_t ESEL5:2; - uint32_t ESEL4:2; - uint32_t ESEL3:2; - uint32_t ESEL2:2; - uint32_t ESEL1:2; - uint32_t ESEL0:2; - } B; - } ISEL2A; /* External Interrupt Select Register 2A */ - - int32_t SIU_reserved9[142]; - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t PB:16; - } B; - } PGPDO0; /* Parallel GPIO Pin Data Output Register */ - - union { - uint32_t R; - struct { - uint32_t PC:16; - uint32_t PD:16; - } B; - } PGPDO1; /* Parallel GPIO Pin Data Output Register */ - - union { - uint32_t R; - struct { - uint32_t PE:16; - uint32_t PF:16; - } B; - } PGPDO2; /* Parallel GPIO Pin Data Output Register */ - - union { - uint32_t R; - struct { - uint32_t PG:16; - uint32_t PH:16; - } B; - } PGPDO3; /* Parallel GPIO Pin Data Output Register */ - - union { - uint32_t R; - struct { - uint32_t PJ:16; - uint32_t PK:11; - uint32_t:5; - } B; - } PGPDO4; /* Parallel GPIO Pin Data Output Register */ - - int32_t SIU_reserved10[11]; - - union { - uint32_t R; - struct { - uint32_t PA:16; - uint32_t PB:16; - } B; - } PGPDI0; /* Parallel GPIO Pin Data Input Register */ - - union { - uint32_t R; - struct { - uint32_t PC:16; - uint32_t PD:16; - } B; - } PGPDI1; /* Parallel GPIO Pin Data Input Register */ - - union { - uint32_t R; - struct { - uint32_t PE:16; - uint32_t PF:16; - } B; - } PGPDI2; /* Parallel GPIO Pin Data Input Register */ - - union { - uint32_t R; - struct { - uint32_t PG:16; - uint32_t PH:16; - } B; - } PGPDI3; /* Parallel GPIO Pin Data Input Register */ - - union { - uint32_t R; - struct { - uint32_t PJ:16; - uint32_t PK:11; - uint32_t:5; - } B; - } PGPDI4; /* Parallel GPIO Pin Data Input Register */ - - int32_t SIU_reserved11[12]; - - union { - uint32_t R; - struct { - uint32_t PB_MASK:16; - uint32_t PB:16; - } B; - } MPGPDO1; /* Masked Parallel GPIO Pin Data Input Register */ - - union { - uint32_t R; - struct { - uint32_t PC_MASK:16; - uint32_t PC:16; - } B; - } MPGPDO2; /* Masked Parallel GPIO Pin Data Input Register */ - - union { - uint32_t R; - struct { - uint32_t PD_MASK:16; - uint32_t PD:16; - } B; - } MPGPDO3; /* Masked Parallel GPIO Pin Data Input Register */ - - union { - uint32_t R; - struct { - uint32_t PE_MASK:16; - uint32_t PE:16; - } B; - } MPGPDO4; /* Masked Parallel GPIO Pin Data Input Register */ - - union { - uint32_t R; - struct { - uint32_t PF_MASK:16; - uint32_t PF:16; - } B; - } MPGPDO5; /* Masked Parallel GPIO Pin Data Input Register */ - - union { - uint32_t R; - struct { - uint32_t PG_MASK:16; - uint32_t PG:16; - } B; - } MPGPDO6; /* Masked Parallel GPIO Pin Data Input Register */ - - union { - uint32_t R; - struct { - uint32_t PH_MASK:16; - uint32_t PH:16; - } B; - } MPGPDO7; /* Masked Parallel GPIO Pin Data Input Register */ - - union { - uint32_t R; - struct { - uint32_t PJ_MASK:16; - uint32_t PJ:16; - } B; - } MPGPDO8; /* Masked Parallel GPIO Pin Data Input Register */ - - union { - uint32_t R; - struct { - uint32_t PK_MASK:11; - uint32_t:5; - uint32_t PK:11; - uint32_t:5; - } B; - } MPGPDO9; /* Masked Parallel GPIO Pin Data Input Register */ - - int32_t SIU_reserved12[22]; - - union { - uint32_t R; - struct { - uint32_t MASK31:1; - uint32_t MASK30:1; - uint32_t MASK29:1; - uint32_t MASK28:1; - uint32_t MASK27:1; - uint32_t MASK26:1; - uint32_t MASK25:1; - uint32_t MASK24:1; - uint32_t MASK23:1; - uint32_t MASK22:1; - uint32_t MASK21:1; - uint32_t MASK20:1; - uint32_t MASK19:1; - uint32_t MASK18:1; - uint32_t MASK17:1; - uint32_t MASK16:1; - uint32_t DATA31:1; - uint32_t DATA30:1; - uint32_t DATA29:1; - uint32_t DATA28:1; - uint32_t DATA27:1; - uint32_t DATA26:1; - uint32_t DATA25:1; - uint32_t DATA24:1; - uint32_t DATA23:1; - uint32_t DATA22:1; - uint32_t DATA21:1; - uint32_t DATA20:1; - uint32_t DATA19:1; - uint32_t DATA18:1; - uint32_t DATA17:1; - uint32_t DATA16:1; - } B; - } DSPIAH; /* Masked Serial GPO for DSPI_A High Register */ - - union { - uint32_t R; - struct { - uint32_t MASK15:1; - uint32_t MASK14:1; - uint32_t MASK13:1; - uint32_t MASK12:1; - uint32_t MASK11:1; - uint32_t MASK10:1; - uint32_t MASK9:1; - uint32_t MASK8:1; - uint32_t MASK7:1; - uint32_t MASK6:1; - uint32_t MASK5:1; - uint32_t MASK4:1; - uint32_t MASK3:1; - uint32_t MASK2:1; - uint32_t MASK1:1; - uint32_t MASK0:1; - uint32_t DATA15:1; - uint32_t DATA14:1; - uint32_t DATA13:1; - uint32_t DATA12:1; - uint32_t DATA11:1; - uint32_t DATA10:1; - uint32_t DATA9:1; - uint32_t DATA8:1; - uint32_t DATA7:1; - uint32_t DATA6:1; - uint32_t DATA5:1; - uint32_t DATA4:1; - uint32_t DATA3:1; - uint32_t DATA2:1; - uint32_t DATA1:1; - uint32_t DATA0:1; - } B; - } DSPIAL; /* Masked Serial GPO for DSPI_A Low Register */ - - union { - uint32_t R; - struct { - uint32_t MASK31:1; - uint32_t MASK30:1; - uint32_t MASK29:1; - uint32_t MASK28:1; - uint32_t MASK27:1; - uint32_t MASK26:1; - uint32_t MASK25:1; - uint32_t MASK24:1; - uint32_t MASK23:1; - uint32_t MASK22:1; - uint32_t MASK21:1; - uint32_t MASK20:1; - uint32_t MASK19:1; - uint32_t MASK18:1; - uint32_t MASK17:1; - uint32_t MASK16:1; - uint32_t DATA31:1; - uint32_t DATA30:1; - uint32_t DATA29:1; - uint32_t DATA28:1; - uint32_t DATA27:1; - uint32_t DATA26:1; - uint32_t DATA25:1; - uint32_t DATA24:1; - uint32_t DATA23:1; - uint32_t DATA22:1; - uint32_t DATA21:1; - uint32_t DATA20:1; - uint32_t DATA19:1; - uint32_t DATA18:1; - uint32_t DATA17:1; - uint32_t DATA16:1; - } B; - } DSPIBH; /* Masked Serial GPO for DSPI_B High Register */ - - union { - uint32_t R; - struct { - uint32_t MASK15:1; - uint32_t MASK14:1; - uint32_t MASK13:1; - uint32_t MASK12:1; - uint32_t MASK11:1; - uint32_t MASK10:1; - uint32_t MASK9:1; - uint32_t MASK8:1; - uint32_t MASK7:1; - uint32_t MASK6:1; - uint32_t MASK5:1; - uint32_t MASK4:1; - uint32_t MASK3:1; - uint32_t MASK2:1; - uint32_t MASK1:1; - uint32_t MASK0:1; - uint32_t DATA15:1; - uint32_t DATA14:1; - uint32_t DATA13:1; - uint32_t DATA12:1; - uint32_t DATA11:1; - uint32_t DATA10:1; - uint32_t DATA9:1; - uint32_t DATA8:1; - uint32_t DATA7:1; - uint32_t DATA6:1; - uint32_t DATA5:1; - uint32_t DATA4:1; - uint32_t DATA3:1; - uint32_t DATA2:1; - uint32_t DATA1:1; - uint32_t DATA0:1; - } B; - } DSPIBL; /* Masked Serial GPO for DSPI_B Low Register */ - - union { - uint32_t R; - struct { - uint32_t MASK31:1; - uint32_t MASK30:1; - uint32_t MASK29:1; - uint32_t MASK28:1; - uint32_t MASK27:1; - uint32_t MASK26:1; - uint32_t MASK25:1; - uint32_t MASK24:1; - uint32_t MASK23:1; - uint32_t MASK22:1; - uint32_t MASK21:1; - uint32_t MASK20:1; - uint32_t MASK19:1; - uint32_t MASK18:1; - uint32_t MASK17:1; - uint32_t MASK16:1; - uint32_t DATA31:1; - uint32_t DATA30:1; - uint32_t DATA29:1; - uint32_t DATA28:1; - uint32_t DATA27:1; - uint32_t DATA26:1; - uint32_t DATA25:1; - uint32_t DATA24:1; - uint32_t DATA23:1; - uint32_t DATA22:1; - uint32_t DATA21:1; - uint32_t DATA20:1; - uint32_t DATA19:1; - uint32_t DATA18:1; - uint32_t DATA17:1; - uint32_t DATA16:1; - } B; - } DSPICH; /* Masked Serial GPO for DSPI_C High Register */ - - union { - uint32_t R; - struct { - uint32_t MASK15:1; - uint32_t MASK14:1; - uint32_t MASK13:1; - uint32_t MASK12:1; - uint32_t MASK11:1; - uint32_t MASK10:1; - uint32_t MASK9:1; - uint32_t MASK8:1; - uint32_t MASK7:1; - uint32_t MASK6:1; - uint32_t MASK5:1; - uint32_t MASK4:1; - uint32_t MASK3:1; - uint32_t MASK2:1; - uint32_t MASK1:1; - uint32_t MASK0:1; - uint32_t DATA15:1; - uint32_t DATA14:1; - uint32_t DATA13:1; - uint32_t DATA12:1; - uint32_t DATA11:1; - uint32_t DATA10:1; - uint32_t DATA9:1; - uint32_t DATA8:1; - uint32_t DATA7:1; - uint32_t DATA6:1; - uint32_t DATA5:1; - uint32_t DATA4:1; - uint32_t DATA3:1; - uint32_t DATA2:1; - uint32_t DATA1:1; - uint32_t DATA0:1; - } B; - } DSPICL; /* Masked Serial GPO for DSPI_C Low Register */ - - union { - uint32_t R; - struct { - uint32_t MASK31:1; - uint32_t MASK30:1; - uint32_t MASK29:1; - uint32_t MASK28:1; - uint32_t MASK27:1; - uint32_t MASK26:1; - uint32_t MASK25:1; - uint32_t MASK24:1; - uint32_t MASK23:1; - uint32_t MASK22:1; - uint32_t MASK21:1; - uint32_t MASK20:1; - uint32_t MASK19:1; - uint32_t MASK18:1; - uint32_t MASK17:1; - uint32_t MASK16:1; - uint32_t DATA31:1; - uint32_t DATA30:1; - uint32_t DATA29:1; - uint32_t DATA28:1; - uint32_t DATA27:1; - uint32_t DATA26:1; - uint32_t DATA25:1; - uint32_t DATA24:1; - uint32_t DATA23:1; - uint32_t DATA22:1; - uint32_t DATA21:1; - uint32_t DATA20:1; - uint32_t DATA19:1; - uint32_t DATA18:1; - uint32_t DATA17:1; - uint32_t DATA16:1; - } B; - } DSPIDH; /* Masked Serial GPO for DSPI_D High Register */ - - union { - uint32_t R; - struct { - uint32_t MASK15:1; - uint32_t MASK14:1; - uint32_t MASK13:1; - uint32_t MASK12:1; - uint32_t MASK11:1; - uint32_t MASK10:1; - uint32_t MASK9:1; - uint32_t MASK8:1; - uint32_t MASK7:1; - uint32_t MASK6:1; - uint32_t MASK5:1; - uint32_t MASK4:1; - uint32_t MASK3:1; - uint32_t MASK2:1; - uint32_t MASK1:1; - uint32_t MASK0:1; - uint32_t DATA15:1; - uint32_t DATA14:1; - uint32_t DATA13:1; - uint32_t DATA12:1; - uint32_t DATA11:1; - uint32_t DATA10:1; - uint32_t DATA9:1; - uint32_t DATA8:1; - uint32_t DATA7:1; - uint32_t DATA6:1; - uint32_t DATA5:1; - uint32_t DATA4:1; - uint32_t DATA3:1; - uint32_t DATA2:1; - uint32_t DATA1:1; - uint32_t DATA0:1; - } B; - } DSPIDL; /* Masked Serial GPO for DSPI_D Low Register */ - - int32_t SIU_reserved13[9]; - - union { - uint32_t R; - struct { - uint32_t EMIOS31:1; - uint32_t EMIOS30:1; - uint32_t EMIOS29:1; - uint32_t EMIOS28:1; - uint32_t EMIOS27:1; - uint32_t EMIOS26:1; - uint32_t EMIOS25:1; - uint32_t EMIOS24:1; - uint32_t EMIOS23:1; - uint32_t EMIOS22:1; - uint32_t EMIOS21:1; - uint32_t EMIOS20:1; - uint32_t EMIOS19:1; - uint32_t EMIOS18:1; - uint32_t EMIOS17:1; - uint32_t EMIOS16:1; - uint32_t EMIOS15:1; - uint32_t EMIOS14:1; - uint32_t EMIOS13:1; - uint32_t EMIOS12:1; - uint32_t EMIOS11:1; - uint32_t EMIOS10:1; - uint32_t EMIOS9:1; - uint32_t EMIOS8:1; - uint32_t EMIOS7:1; - uint32_t EMIOS6:1; - uint32_t EMIOS5:1; - uint32_t EMIOS4:1; - uint32_t EMIOS3:1; - uint32_t EMIOS2:1; - uint32_t EMIOS1:1; - uint32_t EMIOS0:1; - } B; - } EMIOSA; /* EMIOS A Select Register */ - - union { - uint32_t R; - struct { - uint32_t DSPIAH31:1; - uint32_t DSPIAH30:1; - uint32_t DSPIAH29:1; - uint32_t DSPIAH28:1; - uint32_t DSPIAH27:1; - uint32_t DSPIAH26:1; - uint32_t DSPIAH25:1; - uint32_t DSPIAH24:1; - uint32_t DSPIAH23:1; - uint32_t DSPIAH22:1; - uint32_t DSPIAH21:1; - uint32_t DSPIAH20:1; - uint32_t DSPIAH19:1; - uint32_t DSPIAH18:1; - uint32_t DSPIAH17:1; - uint32_t DSPIAH16:1; - uint32_t DSPIAL15:1; - uint32_t DSPIAL14:1; - uint32_t DSPIAL13:1; - uint32_t DSPIAL12:1; - uint32_t DSPIAL11:1; - uint32_t DSPIAL10:1; - uint32_t DSPIAL9:1; - uint32_t DSPIAL8:1; - uint32_t DSPIAL7:1; - uint32_t DSPIAL6:1; - uint32_t DSPIAL5:1; - uint32_t DSPIAL4:1; - uint32_t DSPIAL3:1; - uint32_t DSPIAL2:1; - uint32_t DSPIAL1:1; - uint32_t DSPIAL0:1; - } B; - } DSPIAHLA; /* DSPIAH/L Select Register for DSPI A */ - - int32_t SIU_reserved14[2]; - - union { - uint32_t R; - struct { - uint32_t EMIOS31:1; - uint32_t EMIOS30:1; - uint32_t EMIOS29:1; - uint32_t EMIOS28:1; - uint32_t EMIOS27:1; - uint32_t EMIOS26:1; - uint32_t EMIOS25:1; - uint32_t EMIOS24:1; - uint32_t EMIOS23:1; - uint32_t EMIOS22:1; - uint32_t EMIOS21:1; - uint32_t EMIOS20:1; - uint32_t EMIOS19:1; - uint32_t EMIOS18:1; - uint32_t EMIOS17:1; - uint32_t EMIOS16:1; - uint32_t EMIOS15:1; - uint32_t EMIOS14:1; - uint32_t EMIOS13:1; - uint32_t EMIOS12:1; - uint32_t EMIOS11:1; - uint32_t EMIOS10:1; - uint32_t EMIOS9:1; - uint32_t EMIOS8:1; - uint32_t EMIOS7:1; - uint32_t EMIOS6:1; - uint32_t EMIOS5:1; - uint32_t EMIOS4:1; - uint32_t EMIOS3:1; - uint32_t EMIOS2:1; - uint32_t EMIOS1:1; - uint32_t EMIOS0:1; - } B; - } EMIOSB; /* EMIOS B Select Register */ - - union { - uint32_t R; - struct { - uint32_t DSPIBH31:1; - uint32_t DSPIBH30:1; - uint32_t DSPIBH29:1; - uint32_t DSPIBH28:1; - uint32_t DSPIBH27:1; - uint32_t DSPIBH26:1; - uint32_t DSPIBH25:1; - uint32_t DSPIBH24:1; - uint32_t DSPIBH23:1; - uint32_t DSPIBH22:1; - uint32_t DSPIBH21:1; - uint32_t DSPIBH20:1; - uint32_t DSPIBH19:1; - uint32_t DSPIBH18:1; - uint32_t DSPIBH17:1; - uint32_t DSPIBH16:1; - uint32_t DSPIBL15:1; - uint32_t DSPIBL14:1; - uint32_t DSPIBL13:1; - uint32_t DSPIBL12:1; - uint32_t DSPIBL11:1; - uint32_t DSPIBL10:1; - uint32_t DSPIBL9:1; - uint32_t DSPIBL8:1; - uint32_t DSPIBL7:1; - uint32_t DSPIBL6:1; - uint32_t DSPIBL5:1; - uint32_t DSPIBL4:1; - uint32_t DSPIBL3:1; - uint32_t DSPIBL2:1; - uint32_t DSPIBL1:1; - uint32_t DSPIBL0:1; - } B; - } DSPIBHLB; /* DSPIBH/L Select Register for DSPI B */ - - int32_t SIU_reserved115[2]; - - union { - uint32_t R; - struct { - uint32_t EMIOS31:1; - uint32_t EMIOS30:1; - uint32_t EMIOS29:1; - uint32_t EMIOS28:1; - uint32_t EMIOS27:1; - uint32_t EMIOS26:1; - uint32_t EMIOS25:1; - uint32_t EMIOS24:1; - uint32_t EMIOS23:1; - uint32_t EMIOS22:1; - uint32_t EMIOS21:1; - uint32_t EMIOS20:1; - uint32_t EMIOS19:1; - uint32_t EMIOS18:1; - uint32_t EMIOS17:1; - uint32_t EMIOS16:1; - uint32_t EMIOS15:1; - uint32_t EMIOS14:1; - uint32_t EMIOS13:1; - uint32_t EMIOS12:1; - uint32_t EMIOS11:1; - uint32_t EMIOS10:1; - uint32_t EMIOS9:1; - uint32_t EMIOS8:1; - uint32_t EMIOS7:1; - uint32_t EMIOS6:1; - uint32_t EMIOS5:1; - uint32_t EMIOS4:1; - uint32_t EMIOS3:1; - uint32_t EMIOS2:1; - uint32_t EMIOS1:1; - uint32_t EMIOS0:1; - } B; - } EMIOSC; /* EMIOS C Select Register */ - - union { - uint32_t R; - struct { - uint32_t DSPICH31:1; - uint32_t DSPICH30:1; - uint32_t DSPICH29:1; - uint32_t DSPICH28:1; - uint32_t DSPICH27:1; - uint32_t DSPICH26:1; - uint32_t DSPICH25:1; - uint32_t DSPICH24:1; - uint32_t DSPICH23:1; - uint32_t DSPICH22:1; - uint32_t DSPICH21:1; - uint32_t DSPICH20:1; - uint32_t DSPICH19:1; - uint32_t DSPICH18:1; - uint32_t DSPICH17:1; - uint32_t DSPICH16:1; - uint32_t DSPICL15:1; - uint32_t DSPICL14:1; - uint32_t DSPICL13:1; - uint32_t DSPICL12:1; - uint32_t DSPICL11:1; - uint32_t DSPICL10:1; - uint32_t DSPICL9:1; - uint32_t DSPICL8:1; - uint32_t DSPICL7:1; - uint32_t DSPICL6:1; - uint32_t DSPICL5:1; - uint32_t DSPICL4:1; - uint32_t DSPICL3:1; - uint32_t DSPICL2:1; - uint32_t DSPICL1:1; - uint32_t DSPICL0:1; - } B; - } DSPICHLC; /* DSPIAH/L Select Register for DSPI C */ - - int32_t SIU_reserved16[2]; - - union { - uint32_t R; - struct { - uint32_t EMIOS31:1; - uint32_t EMIOS30:1; - uint32_t EMIOS29:1; - uint32_t EMIOS28:1; - uint32_t EMIOS27:1; - uint32_t EMIOS26:1; - uint32_t EMIOS25:1; - uint32_t EMIOS24:1; - uint32_t EMIOS23:1; - uint32_t EMIOS22:1; - uint32_t EMIOS21:1; - uint32_t EMIOS20:1; - uint32_t EMIOS19:1; - uint32_t EMIOS18:1; - uint32_t EMIOS17:1; - uint32_t EMIOS16:1; - uint32_t EMIOS15:1; - uint32_t EMIOS14:1; - uint32_t EMIOS13:1; - uint32_t EMIOS12:1; - uint32_t EMIOS11:1; - uint32_t EMIOS10:1; - uint32_t EMIOS9:1; - uint32_t EMIOS8:1; - uint32_t EMIOS7:1; - uint32_t EMIOS6:1; - uint32_t EMIOS5:1; - uint32_t EMIOS4:1; - uint32_t EMIOS3:1; - uint32_t EMIOS2:1; - uint32_t EMIOS1:1; - uint32_t EMIOS0:1; - } B; - } EMIOSD; /* EMIOS D Select Register */ - - union { - uint32_t R; - struct { - uint32_t DSPIDH31:1; - uint32_t DSPIDH30:1; - uint32_t DSPIDH29:1; - uint32_t DSPIDH28:1; - uint32_t DSPIDH27:1; - uint32_t DSPIDH26:1; - uint32_t DSPIDH25:1; - uint32_t DSPIDH24:1; - uint32_t DSPIDH23:1; - uint32_t DSPIDH22:1; - uint32_t DSPIDH21:1; - uint32_t DSPIDH20:1; - uint32_t DSPIDH19:1; - uint32_t DSPIDH18:1; - uint32_t DSPIDH17:1; - uint32_t DSPIDH16:1; - uint32_t DSPIDL15:1; - uint32_t DSPIDL14:1; - uint32_t DSPIDL13:1; - uint32_t DSPIDL12:1; - uint32_t DSPIDL11:1; - uint32_t DSPIDL10:1; - uint32_t DSPIDL9:1; - uint32_t DSPIDL8:1; - uint32_t DSPIDL7:1; - uint32_t DSPIDL6:1; - uint32_t DSPIDL5:1; - uint32_t DSPIDL4:1; - uint32_t DSPIDL3:1; - uint32_t DSPIDL2:1; - uint32_t DSPIDL1:1; - uint32_t DSPIDL0:1; - } B; - } DSPIDHLD; /* DSPIAH/L Select Register for DSPI D */ - - }; /* end of SIU_tag */ -/**************************************************************************/ -/* MODULE : STM */ -/**************************************************************************/ - struct STM_tag { - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t CPS:8; - uint32_t:6; - uint32_t FRZ:1; - uint32_t TEN:1; - } B; - } CR; /* STM Control Register */ - - union { - uint32_t R; - } CNT; /* STM Count Register */ - - int32_t STM_reserved[2]; - - union { - uint32_t R; - struct { - uint32_t:31; - uint32_t CEN:1; - } B; - } CCR0; /* STM Channel Control Register 0 */ - - union { - uint32_t R; - struct { - uint32_t:31; - uint32_t CIF:1; - } B; - } CIR0; /* STM Channel Interrupt Register 0 */ - - union { - uint32_t R; - } CMP0; /* STM Channel Compare Register 0 */ - - int32_t STM_reserved1; - - union { - uint32_t R; - struct { - uint32_t:31; - uint32_t CEN:1; - } B; - } CCR1; /* STM Channel Control Register 1 */ - - union { - uint32_t R; - struct { - uint32_t:31; - uint32_t CIF:1; - } B; - } CIR1; /* STM Channel Interrupt Register 1 */ - - union { - uint32_t R; - } CMP1; /* STM Channel Compare Register 1 */ - - int32_t STM_reserved2; - - union { - uint32_t R; - struct { - uint32_t:31; - uint32_t CEN:1; - } B; - } CCR2; /* STM Channel Control Register 2 */ - - union { - uint32_t R; - struct { - uint32_t:31; - uint32_t CIF:1; - } B; - } CIR2; /* STM Channel Interrupt Register 2 */ - - union { - uint32_t R; - } CMP2; /* STM Channel Compare Register 2 */ - - int32_t STM_reserved3; - - union { - uint32_t R; - struct { - uint32_t:31; - uint32_t CEN:1; - } B; - } CCR3; /* STM Channel Control Register 3 */ - - union { - uint32_t R; - struct { - uint32_t:31; - uint32_t CIF:1; - } B; - } CIR3; /* STM Channel Interrupt Register 3 */ - - union { - uint32_t R; - } CMP3; /* STM Channel Compare Register 3 */ - - }; /* end of STM_tag */ -/**************************************************************************/ -/* MODULE : SWT */ -/**************************************************************************/ - struct SWT_tag { - union { - uint32_t R; - struct { - uint32_t MAP0:1; - uint32_t MAP1:1; - uint32_t MAP2:1; - uint32_t MAP3:1; - uint32_t MAP4:1; - uint32_t MAP5:1; - uint32_t MAP6:1; - uint32_t MAP7:1; - uint32_t:14; - uint32_t KEY:1; - uint32_t RIA:1; - uint32_t WND:1; - uint32_t ITR:1; - uint32_t HLK:1; - uint32_t SLK:1; - uint32_t:2; - uint32_t FRZ:1; - uint32_t WEN:1; - } B; - } CR; /* SWT Control Register */ - - union { - uint32_t R; - struct { - uint32_t:31; - uint32_t TIF:1; - } B; - } IR; /* SWT Interrupt Register */ - - union { - uint32_t R; - struct { - uint32_t WTO:32; - } B; - } TO; /* SWT Time-Out Register */ - - union { - uint32_t R; - struct { - uint32_t WST:32; - } B; - } WN; /* SWT Window Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t WSC:16; - } B; - } SR; /* SWT Service Register */ - - union { - uint32_t R; - struct { - uint32_t CNT:32; - } B; - } CO; /* SWT Counter Output Register */ - - union { - uint32_t R; - struct { - uint32_t:16; - uint32_t SK:16; - } B; - } SK; /* SWT Service Key Register */ - - }; /* end of SWT_tag */ - -/* Define memories */ - -#define SRAM0_START 0x40000000UL -#define SRAM0_SIZE 0x80000UL -#define SRAM0_END 0x4007FFFFUL - -#define SRAM1_START 0x40080000UL -#define SRAM1_SIZE 0x14000UL -#define SRAM1_END 0x40093FFFUL - -#define FLASH_START 0x0UL -#define FLASH_SIZE 0x200000UL -#define FLASH_END 0x1FFFFFUL - -/* Define instances of modules AIPS_A */ -#define MLB (*(volatile struct MLB_tag *) 0xC3F84000UL) -#define I2C_C (*(volatile struct I2C_tag *) 0xC3F88000UL) -#define I2C_D (*(volatile struct I2C_tag *) 0xC3F8C000UL) -#define DSPI_C (*(volatile struct DSPI_tag *) 0xC3F90000UL) -#define DSPI_D (*(volatile struct DSPI_tag *) 0xC3F94000UL) -#define ESCI_J (*(volatile struct ESCI_tag *) 0xC3FA0000UL) -#define ESCI_K (*(volatile struct ESCI_tag *) 0xC3FA4000UL) -#define ESCI_L (*(volatile struct ESCI_tag *) 0xC3FA8000UL) -#define ESCI_M (*(volatile struct ESCI_tag *) 0xC3FAC000UL) -#define FR (*(volatile struct FR_tag *) 0xC3FDC000UL) - -/* Define instances of modules AIPS_B */ -#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000UL) -#define SEMA4 (*(volatile struct SEMA4_tag *) 0xFFF10000UL) -#define MPU (*(volatile struct MPU_tag *) 0xFFF14000UL) -#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL) -#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL) -#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL) -#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) -#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL) -#define FEC (*(volatile struct FEC_tag *) 0xFFF4C000UL) -#define ADC (*(volatile struct ADC_tag *) 0xFFF80000UL) -#define I2C_A (*(volatile struct I2C_tag *) 0xFFF88000UL) -#define I2C_B (*(volatile struct I2C_tag *) 0xFFF8C000UL) -#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000UL) -#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000UL) -#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFA0000UL) -#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFA4000UL) -#define ESCI_C (*(volatile struct ESCI_tag *) 0xFFFA8000UL) -#define ESCI_D (*(volatile struct ESCI_tag *) 0xFFFAC000UL) -#define ESCI_E (*(volatile struct ESCI_tag *) 0xFFFB0000UL) -#define ESCI_F (*(volatile struct ESCI_tag *) 0xFFFB4000UL) -#define ESCI_G (*(volatile struct ESCI_tag *) 0xFFFB8000UL) -#define ESCI_H (*(volatile struct ESCI_tag *) 0xFFFBC000UL) -#define CAN_A (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL) -#define CAN_B (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL) -#define CAN_C (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL) -#define CAN_D (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL) -#define CAN_E (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL) -#define CAN_F (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL) -#define CTU (*(volatile struct CTU_tag *) 0xFFFD8000UL) -#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL) -#define PIT (*(volatile struct PIT_tag *) 0xFFFE0000UL) -#define PIT_RTI (*(volatile struct PIT_tag *) 0xFFFE0000UL) -#define EMIOS (*(volatile struct EMIOS_tag *) 0xFFFE4000UL) -#define SIU (*(volatile struct SIU_tag *) 0xFFFE8000UL) -#define CRP (*(volatile struct CRP_tag *) 0xFFFEC000UL) -#define FMPLL (*(volatile struct FMPLL_tag *) 0xFFFF0000UL) -#define FLASH (*(volatile struct FLASH_tag *) 0xFFFF8000UL) - -#ifdef __MWERKS__ -#pragma pop -#endif - -#ifdef __cplusplus -} -#endif -#endif /* ASM */ -#endif /* ifdef _MPC5668_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc567x.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc567x.h deleted file mode 100644 index 31a132a096..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc567x.h +++ /dev/null @@ -1,6630 +0,0 @@ -/* - * Modifications of the original file provided by Freescale are: - * - * Copyright (c) 2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/**************************************************************************/ -/* FILE NAME: mpc5674f.h COPYRIGHT (c) Freescale 2009 */ -/* VERSION: 1.04 All Rights Reserved */ -/* */ -/* DESCRIPTION: */ -/* This file contains all of the register and bit field definitions for */ -/* MPC5674F. */ -/*========================================================================*/ -/* UPDATE HISTORY */ -/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ -/* --- ----------- --------- --------------------- */ -/* NOTE: Branch pulled at version 0.87 for mpc5674_c.h version 1.00 */ -/* 1.00 B. Terry Corrected DECFILT addresses and added */ -/* 4 additional filters for Rev. 2 */ -/* 1.01 B. Terry 16/Nov/09 Corrected bit definitions in SIUDIV */ -/* register. */ -/* 1.02 B. Terry 19/Nov/09 Added ISEL8, ISEL9, ISEL10, and ISEL11 */ -/* regs to SIU tag. (Mamba 2 features) */ -/* 1.03 B. Terry 19/Nov/09 Renamed ISEL10 and ISEL11 to DECFIL1 */ -/* and DECFIL2 to match RM. */ -/* 1.04 B. Terry 22/Jan/10 Updated bitfields of MPU RGDx Word2 */ -/* register to reflect Mamba 2. Added */ -/* MXCR and MXSR registers to DecFilt. */ -/* Removed pre-release rev history. */ -/**************************************************************************/ - -#ifndef _MPC5674F_H_ -#define _MPC5674F_H_ - -#ifndef ASM - -#include <stdint.h> - -#include <mpc55xx/regs-edma.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __MWERKS__ -#pragma push -#pragma ANSI_strict off -#endif - -/****************************************************************************/ -/* MODULE : PBRIDGE_A Peripheral Bridge */ -/****************************************************************************/ - - struct PBRIDGE_A_tag { - - union { /* Master Privilege Control Register 0*/ - uint32_t R; - struct { - uint32_t MBW0:1; /* z7 Core */ - uint32_t MTR0:1; - uint32_t MTW0:1; - uint32_t MPL0:1; - uint32_t MBW1:1; /* Nexus */ - uint32_t MTR1:1; - uint32_t MTW1:1; - uint32_t MPL1:1; - uint32_t MBW2:1; /* Reserved */ - uint32_t MTR2:1; - uint32_t MTW2:1; - uint32_t MPL2:1; - uint32_t MBW3:1; /* Reserved */ - uint32_t MTR3:1; - uint32_t MTW3:1; - uint32_t MPL3:1; - uint32_t MBW4:1; /* eDMA A */ - uint32_t MTR4:1; - uint32_t MTW4:1; - uint32_t MPL4:1; - uint32_t MBW5:1; /* eDMA B */ - uint32_t MTR5:1; - uint32_t MTW5:1; - uint32_t MPL5:1; - uint32_t MBW6:1; /* FLEXRAY */ - uint32_t MTR6:1; - uint32_t MTW6:1; - uint32_t MPL6:1; - uint32_t MBW7:1; /* EBI */ - uint32_t MTR7:1; - uint32_t MTW7:1; - uint32_t MPL7:1; - } B; - } MPCR; - - union { /* Master Privilege Control Register 1 */ - uint32_t R; - struct { - uint32_t:32; /* reserved */ - } B; - } MPCR1; - - uint32_t PBRIDGE_A_reserved0008[6]; /* 0x0008-0x001F */ - - union { /* Peripheral Access Control Register 0 */ - uint32_t R; - struct { - uint32_t BW0:1; /* PBRIDGE_A */ - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - } B; - } PACR0; - - uint32_t PBRIDGE_A_reserved0024[7]; /* 0x0024-0x003F */ - - union { /* Off-Platform Peripheral Access Control Register 0 */ - uint32_t R; - struct { - uint32_t BW0:1; /* FMPLL */ - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t BW1:1; /* EBI control */ - uint32_t SP1:1; - uint32_t WP1:1; - uint32_t TP1:1; - uint32_t BW2:1; /* Flash A control */ - uint32_t SP2:1; - uint32_t WP2:1; - uint32_t TP2:1; - uint32_t BW3:1; /* Flash B control */ - uint32_t SP3:1; - uint32_t WP3:1; - uint32_t TP3:1; - uint32_t BW4:1; /* SIU */ - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - } B; - } OPACR0; - - union { /* Off-Platform Peripheral Access Control Register 1 */ - uint32_t R; - struct { - uint32_t BW0:1; /* EMIOS */ - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t BW7:1; /* PMC */ - uint32_t SP7:1; - uint32_t WP7:1; - uint32_t TP7:1; - } B; - } OPACR1; - - union { /* Off-Platform Peripheral Access Control Register 2 */ - uint32_t R; - struct { - uint32_t BW0:1; /* eTPU */ - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t:4; /* Reserved */ - uint32_t BW2:1; /* eTPU PRAM */ - uint32_t SP2:1; - uint32_t WP2:1; - uint32_t TP2:1; - uint32_t BW3:1; /* eTPU PRAM mirror */ - uint32_t SP3:1; - uint32_t WP3:1; - uint32_t TP3:1; - uint32_t BW4:1; /* eTPU SCM */ - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - uint32_t BW5:1; /* eTPU SCM */ - uint32_t SP5:1; - uint32_t WP5:1; - uint32_t TP5:1; - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - } B; - } OPACR2; - - union { /* Off-Platform Peripheral Access Control Register 3 */ - uint32_t R; - struct { - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t BW4:1; /* PIT/RTI */ - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - } B; - } OPACR3; - - uint32_t PBRIDGE_A_reserved0050[4076]; /* 0x0050-0x3FFF */ - - }; - -/****************************************************************************/ -/* MODULE : PBRIDGE_B Peripheral Bridge */ -/****************************************************************************/ - - struct PBRIDGE_B_tag { - - union { /* Master Privilege Control Register 0 */ - uint32_t R; - struct { - uint32_t MBW0:1; /* z7 Core */ - uint32_t MTR0:1; - uint32_t MTW0:1; - uint32_t MPL0:1; - uint32_t MBW1:1; /* Nexus */ - uint32_t MTR1:1; - uint32_t MTW1:1; - uint32_t MPL1:1; - uint32_t MBW2:1; /* Reserved */ - uint32_t MTR2:1; - uint32_t MTW2:1; - uint32_t MPL2:1; - uint32_t MBW3:1; /* Reserved */ - uint32_t MTR3:1; - uint32_t MTW3:1; - uint32_t MPL3:1; - uint32_t MBW4:1; /* eDMA A */ - uint32_t MTR4:1; - uint32_t MTW4:1; - uint32_t MPL4:1; - uint32_t MBW5:1; /* eDMA B */ - uint32_t MTR5:1; - uint32_t MTW5:1; - uint32_t MPL5:1; - uint32_t MBW6:1; /* FLEXRAY */ - uint32_t MTR6:1; - uint32_t MTW6:1; - uint32_t MPL6:1; - uint32_t MBW7:1; /* EBI */ - uint32_t MTR7:1; - uint32_t MTW7:1; - uint32_t MPL7:1; - } B; - } MPCR; - - union { /* Master Privilege Control Register 1 */ - uint32_t R; - struct { - uint32_t:32; /* Reserved */ - - } B; - } MPCR1; - - uint32_t PBRIDGE_B_reserved0008[6]; /* 0x0008-0x001F */ - - union { /* Peripheral Access Control Register 0 */ - uint32_t R; - struct { - uint32_t BW0:1; /* PBRIDGE B */ - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t BW1:1; /* XBAR */ - uint32_t SP1:1; - uint32_t WP1:1; - uint32_t TP1:1; - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t BW4:1; /* MPU */ - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - } B; - } PACR0; - - union { /* Peripheral Access Control Register 1 */ - uint32_t R; - struct { - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t BW6:1; /* SWT */ - uint32_t SP6:1; - uint32_t WP6:1; - uint32_t TP6:1; - uint32_t BW7:1; /* STM */ - uint32_t SP7:1; - uint32_t WP7:1; - uint32_t TP7:1; - } B; - } PACR1; - - union { /* Peripheral Access Control Register 2 */ - uint32_t R; - struct { - uint32_t BW0:1; /* ECSM */ - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t BW1:1; /* eDMA A */ - uint32_t SP1:1; - uint32_t WP1:1; - uint32_t TP1:1; - uint32_t BW2:1; /* INTC */ - uint32_t SP2:1; - uint32_t WP2:1; - uint32_t TP2:1; - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t BW5:1; /* eDMA B */ - uint32_t SP5:1; - uint32_t WP5:1; - uint32_t TP5:1; - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - } B; - } PACR2; - - uint32_t PBRIDGE_B_reserved002C[5]; /* 0x002C-0x003F */ - - union { /* Off-Platform Peripheral Access Control Register 0 */ - uint32_t R; - struct { - uint32_t BW0:1; /* eQADC A */ - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t BW1:1; /* eQADC B */ - uint32_t SP1:1; - uint32_t WP1:1; - uint32_t TP1:1; - uint32_t BW2:1; /* Decimation Filters A, B, C, D */ - uint32_t SP2:1; - uint32_t WP2:1; - uint32_t TP2:1; - uint32_t:4; /* Reserved */ - uint32_t BW4:1; /* DSPI_A */ - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - uint32_t BW5:1; /* DSPI_B */ - uint32_t SP5:1; - uint32_t WP5:1; - uint32_t TP5:1; - uint32_t BW6:1; /* DSPI_C */ - uint32_t SP6:1; - uint32_t WP6:1; - uint32_t TP6:1; - uint32_t BW7:1; /* DSPI_D */ - uint32_t SP7:1; - uint32_t WP7:1; - uint32_t TP7:1; - } B; - } OPACR0; - - union { /* Off-Platform Peripheral Access Control Register 1 */ - uint32_t R; - struct { - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t BW4:1; /* ESCI_A */ - uint32_t SP4:1; - uint32_t WP4:1; - uint32_t TP4:1; - uint32_t BW5:1; /* ESCI_B */ - uint32_t SP5:1; - uint32_t WP5:1; - uint32_t TP5:1; - uint32_t BW6:1; /* ESCI_C */ - uint32_t SP6:1; - uint32_t WP6:1; - uint32_t TP6:1; - uint32_t:4; /* Reserved */ - } B; - } OPACR1; - - union { /* Off-Platform Peripheral Access Control Register 2 */ - uint32_t R; - struct { - uint32_t BW0:1; /* FlexCAN_A */ - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t BW1:1; /* FlexCAN_B */ - uint32_t SP1:1; - uint32_t WP1:1; - uint32_t TP1:1; - uint32_t BW2:1; /* FlexCAN_C */ - uint32_t SP2:1; - uint32_t WP2:1; - uint32_t TP2:1; - uint32_t BW3:1; /* FlexCAN_D */ - uint32_t SP3:1; - uint32_t WP3:1; - uint32_t TP3:1; - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - } B; - } OPACR2; - - union { /* Off-Platform Peripheral Access Control Register 3 */ - uint32_t R; - struct { - uint32_t BW0:1; /* FlexRAY */ - uint32_t SP0:1; - uint32_t WP0:1; - uint32_t TP0:1; - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t BW3:1; /* Temp Sensor */ - uint32_t SP3:1; - uint32_t WP3:1; - uint32_t TP3:1; - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t:4; /* Reserved */ - uint32_t BW7:1; /* BAM */ - uint32_t SP7:1; - uint32_t WP7:1; - uint32_t TP7:1; - } B; - } OPACR3; - - uint32_t PBRIDGE_B_reserved0050[4076]; /* 0x0050-0x3FFF */ - - }; - -/****************************************************************************/ -/* MODULE : FMPLL */ -/****************************************************************************/ - - struct FMPLL_tag { - - uint32_t FMPLL_reserved0000; /* 0x0000-0x0003 */ - - union FMPLL_SYNSR_tag { /* FMPLL Synthesizer Status Register */ - uint32_t R; - struct { - uint32_t:22; - uint32_t LOLF:1; - uint32_t LOC:1; - uint32_t MODE:1; - uint32_t PLLSEL:1; - uint32_t PLLREF:1; - uint32_t LOCKS:1; - uint32_t LOCK:1; - uint32_t LOCF:1; - uint32_t CALDONE:1; - uint32_t CALPASS:1; - } B; - } SYNSR; - - union FMPLL_ESYNCR1_tag {/* FMPLL Enhanced Synthesizer Control Register 1 */ - uint32_t R; - struct { - uint32_t:1; - uint32_t CLKCFG:3; - uint32_t:8; - uint32_t EPREDIV:4; - uint32_t :8; - uint32_t EMFD:8; - } B; - } ESYNCR1; - - union FMPLL_ESYNCR2_tag {/* FMPLL Enhanced Synthesizer Control Register 2 */ - uint32_t R; - struct { - uint32_t:8; - uint32_t LOCEN:1; - uint32_t LOLRE:1; - uint32_t LOCRE:1; - uint32_t LOLIRQ:1; - uint32_t LOCIRQ:1; - uint32_t:1; - uint32_t ERATE:2; - uint32_t CLKCFG_DIS:1; - uint32_t:4; - uint32_t EDEPTH:3; - uint32_t:2; - uint32_t ERFD:6; - } B; - } ESYNCR2; - - uint32_t FMPLL_reserved0010[4092]; /* 0x0010-0x3FFF */ - - }; - -/****************************************************************************/ -/* MODULE : External Bus Interface (EBI) */ -/****************************************************************************/ - - struct EBI_CS_tag { - uint32_t ebi_cs_reserved [2]; - }; - - struct EBI_CAL_CS_tag { - union { /* Calibration Base Register Bank */ - uint32_t R; - struct { - uint32_t BA:17; - uint32_t:3; - uint32_t PS:1; - uint32_t:3; - uint32_t AD_MUX:1; - uint32_t BL:1; - uint32_t WEBS:1; - uint32_t TBDIP:1; - uint32_t:1; - uint32_t SETA:1; - uint32_t BI:1; - uint32_t V:1; - } B; - } BR; - - union { /* Calibration Option Register Bank */ - uint32_t R; - struct { - uint32_t AM:17; - uint32_t:7; - uint32_t SCY:4; - uint32_t:1; - uint32_t BSCY:2; - uint32_t:1; - } B; - } OR; - }; - - struct EBI_tag { - - union EBI_MCR_tag { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t ACGE:1; - uint32_t:8; - uint32_t MDIS:1; - uint32_t:3; - uint32_t D16_31:1; - uint32_t AD_MUX:1; - uint32_t DBM:1; - } B; - } MCR; - - uint32_t EBI_reserved0004; /* 0x0004-0x0007 */ - - union { /* Transfer Error Status Register */ - uint32_t R; - struct { - uint32_t:30; - uint32_t TEAF:1; - uint32_t BMTF:1; - } B; - } TESR; - - union { /* Bus Monitor Control Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t BMT:8; - uint32_t BME:1; - uint32_t:7; - } B; - } BMCR; - - /* Base/Option registers */ - struct EBI_CS_tag CS[4]; - - uint32_t EBI_reserved0030[4]; /* 0x0030-0x003F */ - - /* Calibration registers */ - struct EBI_CAL_CS_tag CAL_CS[4]; - - uint32_t EBI_reserved0060[4000]; /* 0x0060-0x3FFF */ - - }; - -/****************************************************************************/ -/* MODULE : FLASH */ -/****************************************************************************/ - - struct FLASH_tag { - - union { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t:5; - uint32_t SIZE:3; - uint32_t:1; - uint32_t LAS:3; - uint32_t:3; - uint32_t MAS:1; - uint32_t EER:1; - uint32_t RWE:1; - uint32_t SBC:1; - uint32_t:1; - uint32_t PEAS:1; - uint32_t DONE:1; - uint32_t PEG:1; - uint32_t:4; - uint32_t PGM:1; - uint32_t PSUS:1; - uint32_t ERS:1; - uint32_t ESUS:1; - uint32_t EHV:1; - } B; - } MCR; - - union LMLR_tag { /* Low/Mid Address Space Block Locking Register */ - uint32_t R; - struct { - uint32_t LME:1; - uint32_t:10; - uint32_t SLOCK:1; - uint32_t:2; - uint32_t MLOCK:2; - uint32_t:6; - uint32_t LLOCK:10; - } B; - } LMLR; /* Legacy naming - refer to LML in Reference Manual */ - - union HLR_tag { /* High Address Space Block Locking Register */ - uint32_t R; - struct { - uint32_t HBE:1; - uint32_t:25; - uint32_t HBLOCK:6; /* Legacy naming - refer to HLOCK in Reference Manual */ - } B; - } HLR; /* Legacy naming - refer to HBL in Reference Manual */ - - union SLMLR_tag { /* Secondary Low/Mid Block Locking Register */ - uint32_t R; - struct { - uint32_t SLE:1; - uint32_t:10; - uint32_t SSLOCK:1; - uint32_t:2; - uint32_t SMLOCK:2; - uint32_t:6; - uint32_t SLLOCK:10; - } B; - } SLMLR; /* Legacy naming - refer to SLL in Reference Manual */ - - union { /* Low/Mid Address Space Block Select Register */ - uint32_t R; - struct { - uint32_t:14; - uint32_t MSEL:2; - uint32_t:6; - uint32_t LSEL:10; - } B; - } LMSR; /* Legacy naming - refer to LMS in Reference Manual */ - - union { /* High Address Space Block Select Register */ - uint32_t R; - struct { - uint32_t:26; - uint32_t HBSEL:6; /* Legacy naming - refer to HSEL in Reference Manual */ - } B; - } HSR; /* Legacy naming - refer to HBS in Reference Manual */ - - union { /* Address Register */ - uint32_t R; - struct { - uint32_t SAD:1; - uint32_t:13; - uint32_t ADDR:15; - uint32_t:3; - } B; - } AR; /* Legacy naming - refer to ADR in Reference Manual */ - - union { /* Platform Flash Configuration Register 1 */ - uint32_t R; - struct { - uint32_t:7; - uint32_t M8PFE:1; /* z7 Nexus */ - uint32_t:1; /* EBI Testing - Reserved */ - uint32_t M6PFE:1; /* FlexRay */ - uint32_t M5PFE:1; /* eDMA_B */ - uint32_t M4PFE:1; /* eDMA_A */ - uint32_t:1; /* Reserved */ - uint32_t:1; /* Reserved */ - uint32_t:1; /* Reserved */ - uint32_t M0PFE:1; /* z7 Core */ - uint32_t APC:3; - uint32_t WWSC:2; - uint32_t RWSC:3; - uint32_t:1; - uint32_t DPFEN:1; - uint32_t:1; - uint32_t IPFEN:1; - uint32_t:1; - uint32_t PFLIM:2; - uint32_t BFEN:1; - } B; - } BIUCR; /* Legacy naming - PFCR1 */ - - union { /*Platform Flash Access Protection Register */ - uint32_t R; - struct { - uint32_t:14; - uint32_t M8AP:2; /* z7 Nexus */ - uint32_t:2; /* EBI Testing - Reserved */ - uint32_t M6AP:2; /* FlexRay */ - uint32_t M5AP:2; /* eDMA_B */ - uint32_t M4AP:2; /* eDMA_A */ - uint32_t:2; /* Reserved */ - uint32_t:2; /* Reserved */ - uint32_t:2; /* Reserved */ - uint32_t M0AP:2; /* z7 Core */ - } B; - } BIUAPR; /* Legacy naming - refer to PFAPR in Reference Manual */ - - union { /* Platform Flash Configuration Register 2 */ - uint32_t R; - struct { - uint32_t LBCFG:2; - uint32_t:30; - } B; - } BIUCR2; - - uint32_t FLASH_reserved0028[4086]; /* 0x0028-0x3FFF */ - }; - -/****************************************************************************/ -/* MODULE : SIU */ -/****************************************************************************/ - struct SIU_tag { - int32_t SIU_reserved0000 /* 0x0000-0x0003 */; - - union { /* MCU ID Register */ - uint32_t R; - struct { - uint32_t PARTNUM:16; - uint32_t PKG:4; - uint32_t:4; - uint32_t MAJOR_REV:4; - uint32_t MINOR_REV:4; - } B; - } MIDR; - - int32_t SIU_reserved0008; /* 0x0008-0x000B */ - - union { /* Reset Status Register */ - uint32_t R; - struct { - uint32_t PORS:1; - uint32_t ERS:1; - uint32_t LLRS:1; - uint32_t LCRS:1; - uint32_t WDRS:1; - uint32_t CRS:1; - uint32_t SWTRS:1; - uint32_t:7; - uint32_t SSRS:1; - uint32_t SERF:1; - uint32_t WKPCFG:1; - uint32_t:11; - uint32_t ABR:1; - uint32_t BOOTCFG:2; - uint32_t RGF:1; - } B; - } RSR; - - union { /* System Reset Control Register */ - uint32_t R; - struct { - uint32_t SSR:1; - uint32_t SER:1; - uint32_t:30; // Removed CRE bit - } B; - } SRCR; - - union SIU_EISR_tag { /* External Interrupt Status Register */ - uint32_t R; - struct { - uint32_t NMI:1; - uint32_t:15; - uint32_t EIF15:1; - uint32_t EIF14:1; - uint32_t EIF13:1; - uint32_t EIF12:1; - uint32_t EIF11:1; - uint32_t EIF10:1; - uint32_t EIF9:1; - uint32_t EIF8:1; - uint32_t EIF7:1; - uint32_t EIF6:1; - uint32_t EIF5:1; - uint32_t EIF4:1; - uint32_t EIF3:1; - uint32_t EIF2:1; - uint32_t EIF1:1; - uint32_t EIF0:1; - } B; - } EISR; - - union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */ - uint32_t R; - struct { - uint32_t NMISEL8:1; - uint32_t:7; - uint32_t NMISEL0:1; - uint32_t:7; - uint32_t EIRE15:1; - uint32_t EIRE14:1; - uint32_t EIRE13:1; - uint32_t EIRE12:1; - uint32_t EIRE11:1; - uint32_t EIRE10:1; - uint32_t EIRE9:1; - uint32_t EIRE8:1; - uint32_t EIRE7:1; - uint32_t EIRE6:1; - uint32_t EIRE5:1; - uint32_t EIRE4:1; - uint32_t EIRE3:1; - uint32_t EIRE2:1; - uint32_t EIRE1:1; - uint32_t EIRE0:1; - } B; - } DIRER; - - union SIU_DIRSR_tag { /* DMA/Interrupt Request Select Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t DIRS3:1; - uint32_t DIRS2:1; - uint32_t DIRS1:1; - uint32_t DIRS0:1; - } B; - } DIRSR; - - union { /* Overrun Status Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t OVF15:1; - uint32_t OVF14:1; - uint32_t OVF13:1; - uint32_t OVF12:1; - uint32_t OVF11:1; - uint32_t OVF10:1; - uint32_t OVF9:1; - uint32_t OVF8:1; - uint32_t OVF7:1; - uint32_t OVF6:1; - uint32_t OVF5:1; - uint32_t OVF4:1; - uint32_t OVF3:1; - uint32_t OVF2:1; - uint32_t OVF1:1; - uint32_t OVF0:1; - } B; - } OSR; - - union SIU_ORER_tag { /* Overrun Request Enable Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t ORE15:1; - uint32_t ORE14:1; - uint32_t ORE13:1; - uint32_t ORE12:1; - uint32_t ORE11:1; - uint32_t ORE10:1; - uint32_t ORE9:1; - uint32_t ORE8:1; - uint32_t ORE7:1; - uint32_t ORE6:1; - uint32_t ORE5:1; - uint32_t ORE4:1; - uint32_t ORE3:1; - uint32_t ORE2:1; - uint32_t ORE1:1; - uint32_t ORE0:1; - } B; - } ORER; - - union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */ - uint32_t R; - struct { - uint32_t IREE_NMI8:1; - uint32_t:7; - uint32_t IREE_NMI0:1; - uint32_t:7; - uint32_t IREE15:1; - uint32_t IREE14:1; - uint32_t IREE13:1; - uint32_t IREE12:1; - uint32_t IREE11:1; - uint32_t IREE10:1; - uint32_t IREE9:1; - uint32_t IREE8:1; - uint32_t IREE7:1; - uint32_t IREE6:1; - uint32_t IREE5:1; - uint32_t IREE4:1; - uint32_t IREE3:1; - uint32_t IREE2:1; - uint32_t IREE1:1; - uint32_t IREE0:1; - } B; - } IREER; - - union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */ - uint32_t R; - struct { - uint32_t IFEE_NMI8:1; - uint32_t:7; - uint32_t IFEE_NMI0:1; - uint32_t:7; - uint32_t IFEE15:1; - uint32_t IFEE14:1; - uint32_t IFEE13:1; - uint32_t IFEE12:1; - uint32_t IFEE11:1; - uint32_t IFEE10:1; - uint32_t IFEE9:1; - uint32_t IFEE8:1; - uint32_t IFEE7:1; - uint32_t IFEE6:1; - uint32_t IFEE5:1; - uint32_t IFEE4:1; - uint32_t IFEE3:1; - uint32_t IFEE2:1; - uint32_t IFEE1:1; - uint32_t IFEE0:1; - } B; - } IFEER; - - union SIU_IDFR_tag { /* External IRQ Digital Filter Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t DFL:4; - } B; - } IDFR; - - union { /* External IRQ Filtered Input Register */ - uint32_t R; - struct { - uint32_t FI31:1; - uint32_t FI30:1; - uint32_t FI29:1; - uint32_t FI28:1; - uint32_t FI27:1; - uint32_t FI26:1; - uint32_t FI25:1; - uint32_t FI24:1; - uint32_t FI23:1; - uint32_t FI22:1; - uint32_t FI21:1; - uint32_t FI20:1; - uint32_t FI19:1; - uint32_t FI18:1; - uint32_t FI17:1; - uint32_t FI16:1; - uint32_t FI15:1; - uint32_t FI14:1; - uint32_t FI13:1; - uint32_t FI12:1; - uint32_t FI11:1; - uint32_t FI10:1; - uint32_t FI9:1; - uint32_t FI8:1; - uint32_t FI7:1; - uint32_t FI6:1; - uint32_t FI5:1; - uint32_t FI4:1; - uint32_t FI3:1; - uint32_t FI2:1; - uint32_t FI1:1; - uint32_t FI0:1; - } B; - } IFIR; - - int32_t SIU_reserved0038[2]; /* 0x0038-0x003F */ - - union SIU_PCR_tag { /* Pad Configuration Registers */ - uint16_t R; - struct { - uint16_t:3; - uint16_t PA:3; - uint16_t OBE:1; - uint16_t IBE:1; - uint16_t DSC:2; - uint16_t ODE:1; - uint16_t HYS:1; - uint16_t SRC:2; - uint16_t WPE:1; - uint16_t WPS:1; - } B; - } PCR[512]; - - int16_t SIU_reserved0440[224]; /* 0x0440-0x05FF */ - - union { /* GPIO Pin Data Output Registers */ - uint8_t R; - struct { - uint8_t:7; - uint8_t PDO:1; - } B; - } GPDO[512]; - - union { /* GPIO Pin Data Input Registers */ - uint8_t R; - struct { - uint8_t:7; - uint8_t PDI:1; - } B; - } GPDI[256]; - - uint32_t SIU_reserved0900; /* 0x0900-0x0903 */ - - union { /* External IRQ Input Select Register */ - uint32_t R; - struct { - uint32_t ESEL15:2; - uint32_t ESEL14:2; - uint32_t ESEL13:2; - uint32_t ESEL12:2; - uint32_t ESEL11:2; - uint32_t ESEL10:2; - uint32_t ESEL9:2; - uint32_t ESEL8:2; - uint32_t ESEL7:2; - uint32_t ESEL6:2; - uint32_t ESEL5:2; - uint32_t ESEL4:2; - uint32_t ESEL3:2; - uint32_t ESEL2:2; - uint32_t ESEL1:2; - uint32_t ESEL0:2; - } B; - } EIISR; - - union { /* DSPI Input Select Register */ - uint32_t R; - struct { - uint32_t SINSELA:2; - uint32_t SSSELA:2; - uint32_t SCKSELA:2; - uint32_t TRIGSELA:2; - uint32_t SINSELB:2; - uint32_t SSSELB:2; - uint32_t SCKSELB:2; - uint32_t TRIGSELB:2; - uint32_t SINSELC:2; - uint32_t SSSELC:2; - uint32_t SCKSELC:2; - uint32_t TRIGSELC:2; - uint32_t SINSELD:2; - uint32_t SSSELD:2; - uint32_t SCKSELD:2; - uint32_t TRIGSELD:2; - } B; - } DISR; - - int32_t SIU_reserved090C; /* 0x090C-0x090F */ - - union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */ - uint32_t R; - struct { - uint32_t:1; - uint32_t CTSEL5_0:7; - uint32_t:1; - uint32_t CTSEL4_0:7; - uint32_t:1; - uint32_t CTSEL3_0:7; - uint32_t:1; - uint32_t CTSEL2_0:7; - } B; - } ISEL4; - - union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */ - uint32_t R; - struct { - uint32_t:1; - uint32_t CTSEL1_0:7; - uint32_t:1; - uint32_t CTSEL0_0:7; - uint32_t:16; - } B; - } ISEL5; - - union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */ - uint32_t R; - struct { - uint32_t:1; - uint32_t CTSEL5_1:7; - uint32_t:1; - uint32_t CTSEL4_1:7; - uint32_t:1; - uint32_t CTSEL3_1:7; - uint32_t:1; - uint32_t CTSEL2_1:7; - } B; - } ISEL6; - - union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */ - uint32_t R; - struct { - uint32_t:1; - uint32_t CTSEL1_1:7; - uint32_t:1; - uint32_t CTSEL0_1:7; - uint32_t:16; - } B; - } ISEL7; - - union { /* eTPU Input Select Register */ - uint32_t R; - struct { - uint32_t:11; - uint32_t ETPU29:1; - uint32_t:3; - uint32_t ETPU28:1; - uint32_t:3; - uint32_t ETPU27:1; - uint32_t:3; - uint32_t ETPU26:1; - uint32_t:3; - uint32_t ETPU25:1; - uint32_t:3; - uint32_t ETPU24:1; - } B; - } ISEL8; - - union { /* eQADC Advanced Trigger Select */ - uint32_t R; - struct { - uint32_t:27; - uint32_t ETSEL0A:5; - } B; - } ISEL9; - - union { /* DecFilter Integrator Control */ - uint32_t R; - struct { - uint32_t ZSELA:4; - uint32_t HSELA:4; - uint32_t ZSELB:4; - uint32_t HSELB:4; - uint32_t ZSELC:4; - uint32_t HSELC:4; - uint32_t ZSELD:4; - uint32_t HSELD:4; - } B; - } DECFIL1; - - union { /* DecFilter Integrator Control */ - uint32_t R; - struct { - uint32_t ZSELE:4; - uint32_t HSELE:4; - uint32_t ZSELF:4; - uint32_t HSELF:4; - uint32_t ZSELG:4; - uint32_t HSELG:4; - uint32_t ZSELH:4; - uint32_t HSELH:4; - } B; - } DECFIL2; - - - int32_t SIU_reserved0920[20]; /* 0x0930-0x097F */ - - union { /* Chip Configuration Register Register */ - uint32_t R; - struct { - uint32_t:14; - uint32_t MATCH:1; - uint32_t DISNEX:1; - uint32_t:16; - } B; - } CCR; - - union { /* External Clock Configuration Register Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t ENGDIV:8; - uint32_t ECSS:1; - uint32_t:3; - uint32_t EBTS:1; - uint32_t:1; - uint32_t EBDF:2; - } B; - } ECCR; - - union { /* Compare A Register High */ - uint32_t R; - struct { - uint32_t CMPAH:32; - } B; - } CARH; - - union { /* Compare A Register Low */ - uint32_t R; - struct { - uint32_t CMPAL:32; - } B; - } CARL; - - union { /* Compare B Register High */ - uint32_t R; - struct { - uint32_t CMPBH:32; - } B; - } CBRH; - - union { /* Compare B Register Low */ - uint32_t R; - struct { - uint32_t CMPBL:32; - } B; - } CBRL; - - int32_t SIU_reserved0998[2]; /* 0x0998-0x099F */ - - union { /* System Clock Register */ - uint32_t R; - struct { - uint32_t:22; - uint32_t IPCLKDIV:2; - uint32_t:3; - uint32_t BYPASS:1; - uint32_t SYSCLKDIV:2; - uint32_t:2; - } B; - } SYSDIV; - - union { /* Halt Register */ - uint32_t R; - struct { - uint32_t CPUSTP:1; /* CPU and Platform stop request */ - uint32_t:4; /* Reserved */ - uint32_t TPUSTP:1; /* eTPU_A stop request */ - uint32_t NPCSTP:1; /* Nexus stop request */ - uint32_t EBISTP:1; /* EBI stop request*/ - uint32_t ADCSTP:1; /* eQADC stop request */ - uint32_t:1; /* Reserved */ - uint32_t MIOSSTP:1; /* eMIOS stop request */ - uint32_t DFILSTP:1; /* Decimation filter stop request */ - uint32_t:1; /* Reserved */ - uint32_t PITSTP:1; /* PIT stop request */ - uint32_t:2; /* Reserved */ - uint32_t CNDSTP:1; /* FlexCAN D stop request */ - uint32_t CNCSTP:1; /* FlexCAN C stop request */ - uint32_t CNBSTP:1; /* FlexCAN B stop request */ - uint32_t CNASTP:1; /* FlexCAN A stop request */ - uint32_t SPIDSTP:1; /* DSPI D stop request */ - uint32_t SPICSTP:1; /* DSPI C stop request */ - uint32_t SPIBSTP:1; /* DSPI B stop request */ - uint32_t SPIASTP:1; /* DSPI C stop request */ - uint32_t:5; /* Reserved */ - uint32_t SCICSTP:1; /* eSCI C stop request */ - uint32_t SCIBSTP:1; /* eSCI B stop request */ - uint32_t SCIASTP:1; /* eSCI A stop request */ - } B; - } HLT; - - union { /* Halt Acknowledge Register */ - uint32_t R; - struct { - uint32_t CPUACK:1; /* CPU and Platform stop acknowledge */ - uint32_t:4; /* Reserved */ - uint32_t TPUACK:1; /* eTPU_A stop acknowledge */ - uint32_t NPCACK:1; /* Nexus stop acknowledge */ - uint32_t EBIACK:1; /* EBI stop acknowledge*/ - uint32_t ADCACK:1; /* eQADC stop acknowledge */ - uint32_t:1; /* Reserved */ - uint32_t MIOSACK:1; /* eMIOS stop acknowledge */ - uint32_t DFILACK:1; /* Decimation filter stop acknowledge */ - uint32_t:1; /* Reserved */ - uint32_t PITACK:1; /* PIT stop acknowledge */ - uint32_t:2; /* Reserved */ - uint32_t CNDACK:1; /* FlexCAN D stop acknowledge */ - uint32_t CNCACK:1; /* FlexCAN C stop acknowledge */ - uint32_t CNBACK:1; /* FlexCAN B stop acknowledge */ - uint32_t CNAACK:1; /* FlexCAN A stop acknowledge */ - uint32_t SPIDACK:1; /* DSPI D stop acknowledge */ - uint32_t SPICACK:1; /* DSPI C stop acknowledge */ - uint32_t SPIBACK:1; /* DSPI B stop acknowledge */ - uint32_t SPIAACK:1; /* DSPI C stop acknowledge */ - uint32_t:5; /* Reserved */ - uint32_t SCICACK:1; /* eSCI C stop acknowledge */ - uint32_t SCIBACK:1; /* eSCI B stop acknowledge */ - uint32_t SCIAACK:1; /* eSCI A stop acknowledge */ - } B; - } HLTACK; - - int32_t SIU_reserved09AC[21]; /* 0x09AC-0x09FF */ - - int32_t SIU_reserved0A00[128]; /* 0x0A00-0x0BFF */ - - union { /* Parallel GPIO Pin Data Output Register */ - uint32_t R; - struct { - uint32_t PGPDO0:1; - uint32_t PGPDO1:1; - uint32_t PGPDO2:1; - uint32_t PGPDO3:1; - uint32_t PGPDO4:1; - uint32_t PGPDO5:1; - uint32_t PGPDO6:1; - uint32_t PGPDO7:1; - uint32_t PGPDO8:1; - uint32_t PGPDO9:1; - uint32_t PGPDO10:1; - uint32_t PGPDO11:1; - uint32_t PGPDO12:1; - uint32_t PGPDO13:1; - uint32_t PGPDO14:1; - uint32_t PGPDO15:1; - uint32_t PGPDO16:1; - uint32_t PGPDO17:1; - uint32_t PGPDO18:1; - uint32_t PGPDO19:1; - uint32_t PGPDO20:1; - uint32_t PGPDO21:1; - uint32_t PGPDO22:1; - uint32_t PGPDO23:1; - uint32_t PGPDO24:1; - uint32_t PGPDO25:1; - uint32_t PGPDO26:1; - uint32_t PGPDO27:1; - uint32_t PGPDO28:1; - uint32_t PGPDO29:1; - uint32_t PGPDO30:1; - uint32_t PGPDO31:1; - } B; - } PGPDO[16]; - - union { /* Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t PGPDI0:1; - uint32_t PGPDI1:1; - uint32_t PGPDI2:1; - uint32_t PGPDI3:1; - uint32_t PGPDI4:1; - uint32_t PGPDI5:1; - uint32_t PGPDI6:1; - uint32_t PGPDI7:1; - uint32_t PGPDI8:1; - uint32_t PGPDI9:1; - uint32_t PGPDI10:1; - uint32_t PGPDI11:1; - uint32_t PGPDI12:1; - uint32_t PGPDI13:1; - uint32_t PGPDI14:1; - uint32_t PGPDI15:1; - uint32_t PGPDI16:1; - uint32_t PGPDI17:1; - uint32_t PGPDI18:1; - uint32_t PGPDI19:1; - uint32_t PGPDI20:1; - uint32_t PGPDI21:1; - uint32_t PGPDI22:1; - uint32_t PGPDI23:1; - uint32_t PGPDI24:1; - uint32_t PGPDI25:1; - uint32_t PGPDI26:1; - uint32_t PGPDI27:1; - uint32_t PGPDI28:1; - uint32_t PGPDI29:1; - uint32_t PGPDI30:1; - uint32_t PGPDI31:1; - } B; - } PGPDI[16]; - - union { /* Masked Parallel GPIO Pin Data Input Register */ - uint32_t R; - struct { - uint32_t MASK0:1; - uint32_t MASK1:1; - uint32_t MASK2:1; - uint32_t MASK3:1; - uint32_t MASK4:1; - uint32_t MASK5:1; - uint32_t MASK6:1; - uint32_t MASK7:1; - uint32_t MASK8:1; - uint32_t MASK9:1; - uint32_t MASK10:1; - uint32_t MASK11:1; - uint32_t MASK12:1; - uint32_t MASK13:1; - uint32_t MASK14:1; - uint32_t MASK15:1; - uint32_t DATA0:1; - uint32_t DATA1:1; - uint32_t DATA2:1; - uint32_t DATA3:1; - uint32_t DATA4:1; - uint32_t DATA5:1; - uint32_t DATA6:1; - uint32_t DATA7:1; - uint32_t DATA8:1; - uint32_t DATA9:1; - uint32_t DATA10:1; - uint32_t DATA11:1; - uint32_t DATA12:1; - uint32_t DATA13:1; - uint32_t DATA14:1; - uint32_t DATA15:1; - } B; - } MPGPDO[32]; - - union { /* DSPI_A Mask Output High Register */ - uint32_t R; - struct { - uint32_t MASK0:1; - uint32_t MASK1:1; - uint32_t MASK2:1; - uint32_t MASK3:1; - uint32_t MASK4:1; - uint32_t MASK5:1; - uint32_t MASK6:1; - uint32_t MASK7:1; - uint32_t MASK8:1; - uint32_t MASK9:1; - uint32_t MASK10:1; - uint32_t MASK11:1; - uint32_t MASK12:1; - uint32_t MASK13:1; - uint32_t MASK14:1; - uint32_t MASK15:1; - uint32_t DATA0:1; - uint32_t DATA1:1; - uint32_t DATA2:1; - uint32_t DATA3:1; - uint32_t DATA4:1; - uint32_t DATA5:1; - uint32_t DATA6:1; - uint32_t DATA7:1; - uint32_t DATA8:1; - uint32_t DATA9:1; - uint32_t DATA10:1; - uint32_t DATA11:1; - uint32_t DATA12:1; - uint32_t DATA13:1; - uint32_t DATA14:1; - uint32_t DATA15:1; - } B; - } DSPIAH; - - union { /* DSPI_A Mask Output Low Register */ - uint32_t R; - struct { - uint32_t MASK16:1; - uint32_t MASK17:1; - uint32_t MASK18:1; - uint32_t MASK19:1; - uint32_t MASK20:1; - uint32_t MASK21:1; - uint32_t MASK22:1; - uint32_t MASK23:1; - uint32_t MASK24:1; - uint32_t MASK25:1; - uint32_t MASK26:1; - uint32_t MASK27:1; - uint32_t MASK28:1; - uint32_t MASK29:1; - uint32_t MASK30:1; - uint32_t MASK31:1; - uint32_t DATA16:1; - uint32_t DATA17:1; - uint32_t DATA18:1; - uint32_t DATA19:1; - uint32_t DATA20:1; - uint32_t DATA21:1; - uint32_t DATA22:1; - uint32_t DATA23:1; - uint32_t DATA24:1; - uint32_t DATA25:1; - uint32_t DATA26:1; - uint32_t DATA27:1; - uint32_t DATA28:1; - uint32_t DATA29:1; - uint32_t DATA30:1; - uint32_t DATA31:1; - } B; - } DSPIAL; - - union { /* DSPI_B Mask Output High Register */ - uint32_t R; - struct { - uint32_t MASK0:1; - uint32_t MASK1:1; - uint32_t MASK2:1; - uint32_t MASK3:1; - uint32_t MASK4:1; - uint32_t MASK5:1; - uint32_t MASK6:1; - uint32_t MASK7:1; - uint32_t MASK8:1; - uint32_t MASK9:1; - uint32_t MASK10:1; - uint32_t MASK11:1; - uint32_t MASK12:1; - uint32_t MASK13:1; - uint32_t MASK14:1; - uint32_t MASK15:1; - uint32_t DATA0:1; - uint32_t DATA1:1; - uint32_t DATA2:1; - uint32_t DATA3:1; - uint32_t DATA4:1; - uint32_t DATA5:1; - uint32_t DATA6:1; - uint32_t DATA7:1; - uint32_t DATA8:1; - uint32_t DATA9:1; - uint32_t DATA10:1; - uint32_t DATA11:1; - uint32_t DATA12:1; - uint32_t DATA13:1; - uint32_t DATA14:1; - uint32_t DATA15:1; - } B; - } DSPIBH; - - union { /* DSPI_B Mask Output Low Register */ - uint32_t R; - struct { - uint32_t MASK16:1; - uint32_t MASK17:1; - uint32_t MASK18:1; - uint32_t MASK19:1; - uint32_t MASK20:1; - uint32_t MASK21:1; - uint32_t MASK22:1; - uint32_t MASK23:1; - uint32_t MASK24:1; - uint32_t MASK25:1; - uint32_t MASK26:1; - uint32_t MASK27:1; - uint32_t MASK28:1; - uint32_t MASK29:1; - uint32_t MASK30:1; - uint32_t MASK31:1; - uint32_t DATA16:1; - uint32_t DATA17:1; - uint32_t DATA18:1; - uint32_t DATA19:1; - uint32_t DATA20:1; - uint32_t DATA21:1; - uint32_t DATA22:1; - uint32_t DATA23:1; - uint32_t DATA24:1; - uint32_t DATA25:1; - uint32_t DATA26:1; - uint32_t DATA27:1; - uint32_t DATA28:1; - uint32_t DATA29:1; - uint32_t DATA30:1; - uint32_t DATA31:1; - } B; - } DSPIBL; - - union { /* DSPI_C Mask Output High Register */ - uint32_t R; - struct { - uint32_t MASK0:1; - uint32_t MASK1:1; - uint32_t MASK2:1; - uint32_t MASK3:1; - uint32_t MASK4:1; - uint32_t MASK5:1; - uint32_t MASK6:1; - uint32_t MASK7:1; - uint32_t MASK8:1; - uint32_t MASK9:1; - uint32_t MASK10:1; - uint32_t MASK11:1; - uint32_t MASK12:1; - uint32_t MASK13:1; - uint32_t MASK14:1; - uint32_t MASK15:1; - uint32_t DATA0:1; - uint32_t DATA1:1; - uint32_t DATA2:1; - uint32_t DATA3:1; - uint32_t DATA4:1; - uint32_t DATA5:1; - uint32_t DATA6:1; - uint32_t DATA7:1; - uint32_t DATA8:1; - uint32_t DATA9:1; - uint32_t DATA10:1; - uint32_t DATA11:1; - uint32_t DATA12:1; - uint32_t DATA13:1; - uint32_t DATA14:1; - uint32_t DATA15:1; - } B; - } DSPICH; - - union { /* DSPI_C Mask Output Low Register */ - uint32_t R; - struct { - uint32_t MASK16:1; - uint32_t MASK17:1; - uint32_t MASK18:1; - uint32_t MASK19:1; - uint32_t MASK20:1; - uint32_t MASK21:1; - uint32_t MASK22:1; - uint32_t MASK23:1; - uint32_t MASK24:1; - uint32_t MASK25:1; - uint32_t MASK26:1; - uint32_t MASK27:1; - uint32_t MASK28:1; - uint32_t MASK29:1; - uint32_t MASK30:1; - uint32_t MASK31:1; - uint32_t DATA16:1; - uint32_t DATA17:1; - uint32_t DATA18:1; - uint32_t DATA19:1; - uint32_t DATA20:1; - uint32_t DATA21:1; - uint32_t DATA22:1; - uint32_t DATA23:1; - uint32_t DATA24:1; - uint32_t DATA25:1; - uint32_t DATA26:1; - uint32_t DATA27:1; - uint32_t DATA28:1; - uint32_t DATA29:1; - uint32_t DATA30:1; - uint32_t DATA31:1; - } B; - } DSPICL; - - union { /* DSPI_D Mask Output High Register */ - uint32_t R; - struct { - uint32_t MASK0:1; - uint32_t MASK1:1; - uint32_t MASK2:1; - uint32_t MASK3:1; - uint32_t MASK4:1; - uint32_t MASK5:1; - uint32_t MASK6:1; - uint32_t MASK7:1; - uint32_t MASK8:1; - uint32_t MASK9:1; - uint32_t MASK10:1; - uint32_t MASK11:1; - uint32_t MASK12:1; - uint32_t MASK13:1; - uint32_t MASK14:1; - uint32_t MASK15:1; - uint32_t DATA0:1; - uint32_t DATA1:1; - uint32_t DATA2:1; - uint32_t DATA3:1; - uint32_t DATA4:1; - uint32_t DATA5:1; - uint32_t DATA6:1; - uint32_t DATA7:1; - uint32_t DATA8:1; - uint32_t DATA9:1; - uint32_t DATA10:1; - uint32_t DATA11:1; - uint32_t DATA12:1; - uint32_t DATA13:1; - uint32_t DATA14:1; - uint32_t DATA15:1; - } B; - } DSPIDH; - - union { /* DSPI_D Mask Output Low Register */ - uint32_t R; - struct { - uint32_t MASK16:1; - uint32_t MASK17:1; - uint32_t MASK18:1; - uint32_t MASK19:1; - uint32_t MASK20:1; - uint32_t MASK21:1; - uint32_t MASK22:1; - uint32_t MASK23:1; - uint32_t MASK24:1; - uint32_t MASK25:1; - uint32_t MASK26:1; - uint32_t MASK27:1; - uint32_t MASK28:1; - uint32_t MASK29:1; - uint32_t MASK30:1; - uint32_t MASK31:1; - uint32_t DATA16:1; - uint32_t DATA17:1; - uint32_t DATA18:1; - uint32_t DATA19:1; - uint32_t DATA20:1; - uint32_t DATA21:1; - uint32_t DATA22:1; - uint32_t DATA23:1; - uint32_t DATA24:1; - uint32_t DATA25:1; - uint32_t DATA26:1; - uint32_t DATA27:1; - uint32_t DATA28:1; - uint32_t DATA29:1; - uint32_t DATA30:1; - uint32_t DATA31:1; - } B; - } DSPIDL; - - int32_t SIU_reserved0D20[8]; /* 0x0D20-0x0D3F */ - - union { /* ETPU B Select Register */ - uint32_t R; - struct { - uint32_t ETPUB15:1; - uint32_t ETPUB14:1; - uint32_t ETPUB13:1; - uint32_t ETPUB12:1; - uint32_t ETPUB11:1; - uint32_t ETPUB10:1; - uint32_t ETPUB9:1; - uint32_t ETPUB8:1; - uint32_t ETPUB7:1; - uint32_t ETPUB6:1; - uint32_t ETPUB5:1; - uint32_t ETPUB4:1; - uint32_t ETPUB3:1; - uint32_t ETPUB2:1; - uint32_t ETPUB1:1; - uint32_t ETPUB0:1; - uint32_t ETPUB31:1; - uint32_t ETPUB30:1; - uint32_t ETPUB29:1; - uint32_t ETPUB28:1; - uint32_t ETPUB27:1; - uint32_t ETPUB26:1; - uint32_t ETPUB25:1; - uint32_t ETPUB24:1; - uint32_t ETPUB23:1; - uint32_t ETPUB22:1; - uint32_t ETPUB21:1; - uint32_t ETPUB20:1; - uint32_t ETPUB19:1; - uint32_t ETPUB18:1; - uint32_t ETPUB17:1; - uint32_t ETPUB16:1; - } B ; - } ETPUBA; - - union { /* EMIOS A Select Register */ - uint32_t R; - struct { - uint32_t EMIOS7:1; - uint32_t EMIOS6:1; - uint32_t EMIOS5:1; - uint32_t EMIOS4:1; - uint32_t EMIOS3:1; - uint32_t EMIOS2:1; - uint32_t EMIOS1:1; - uint32_t EMIOS0:1; - uint32_t EMIOS8:1; - uint32_t EMIOS9:1; - uint32_t EMIOS10:1; - uint32_t EMIOS11:1; - uint32_t EMIOS12:1; - uint32_t EMIOS13:1; - uint32_t EMIOS14:1; - uint32_t EMIOS15:1; - uint32_t EMIOS16:1; - uint32_t EMIOS17:1; - uint32_t EMIOS18:1; - uint32_t EMIOS19:1; - uint32_t EMIOS20:1; - uint32_t EMIOS21:1; - uint32_t EMIOS22:1; - uint32_t EMIOS23:1; - uint32_t EMIOS0_0:1; - uint32_t EMIOS1_1:1; - uint32_t EMIOS2_2:1; - uint32_t EMIOS3_3:1; - uint32_t EMIOS4_4:1; - uint32_t EMIOS5_5:1; - uint32_t EMIOS6_6:1; - uint32_t EMIOS7_7:1; - } B; - } EMIOSA; - - union { /* DSPIAH/L Select Register for DSPI A */ - uint32_t R; - struct { - uint32_t DSPIAH0:1; - uint32_t DSPIAH1:1; - uint32_t DSPIAH2:1; - uint32_t DSPIAH3:1; - uint32_t DSPIAH4:1; - uint32_t DSPIAH5:1; - uint32_t DSPIAH6:1; - uint32_t DSPIAH7:1; - uint32_t DSPIAH8:1; - uint32_t DSPIAH9:1; - uint32_t DSPIAH10:1; - uint32_t DSPIAH11:1; - uint32_t DSPIAH12:1; - uint32_t DSPIAH13:1; - uint32_t DSPIAH14:1; - uint32_t DSPIAH15:1; - uint32_t DSPIAL16:1; - uint32_t DSPIAL17:1; - uint32_t DSPIAL18:1; - uint32_t DSPIAL19:1; - uint32_t DSPIAL20:1; - uint32_t DSPIAL21:1; - uint32_t DSPIAL22:1; - uint32_t DSPIAL23:1; - uint32_t DSPIAL24:1; - uint32_t DSPIAL25:1; - uint32_t DSPIAL26:1; - uint32_t DSPIAL27:1; - uint32_t DSPIAL28:1; - uint32_t DSPIAL29:1; - uint32_t DSPIAL30:1; - uint32_t DSPIAL31:1; - } B; - } DSPIAHLA; - - int32_t SIU_reserved0D4C; /* 0x0D4C-0x0D4F */ - - union { /* ETPU A Select Register */ - uint32_t R; - struct { - uint32_t ETPUA23:1; - uint32_t ETPUA22:1; - uint32_t ETPUA21:1; - uint32_t ETPUA20:1; - uint32_t ETPUA19:1; - uint32_t ETPUA18:1; - uint32_t ETPUA17:1; - uint32_t ETPUA16:1; - uint32_t ETPUA29:1; - uint32_t ETPUA28:1; - uint32_t ETPUA27:1; - uint32_t ETPUA26:1; - uint32_t ETPUA25:1; - uint32_t ETPUA24:1; - uint32_t ETPUA31:1; - uint32_t ETPUA30:1; - uint32_t ETPUA12:1; - uint32_t ETPUA13:1; - uint32_t ETPUA14:1; - uint32_t ETPUA15:1; - uint32_t ETPUA0:1; - uint32_t ETPUA1:1; - uint32_t ETPUA2:1; - uint32_t ETPUA3:1; - uint32_t ETPUA4:1; - uint32_t ETPUA5:1; - uint32_t ETPUA6:1; - uint32_t ETPUA7:1; - uint32_t ETPUA8:1; - uint32_t ETPUA9:1; - uint32_t ETPUA10:1; - uint32_t ETPUA11:1; - } B ; - } ETPUAB; - - union { /* EMIOS B Select Register */ - uint32_t R; - struct { - uint32_t EMIOS11:1; - uint32_t EMIOS10:1; - uint32_t EMIOS9:1; - uint32_t EMIOS8:1; - uint32_t EMIOS6:1; - uint32_t EMIOS5:1; - uint32_t EMIOS4:1; - uint32_t EMIOS3:1; - uint32_t EMIOS2:1; - uint32_t EMIOS1:1; - uint32_t EMIOS0:1; - uint32_t EMIOS23:1; - uint32_t EMIOS15:1; - uint32_t EMIOS14:1; - uint32_t EMIOS13:1; - uint32_t EMIOS12:1; - uint32_t EMIOS23_23:1; - uint32_t EMIOS15_15:1; - uint32_t EMIOS14_14:1; - uint32_t EMIOS13_13:1; - uint32_t EMIOS12_12:1; - uint32_t EMIOS11_11:1; - uint32_t EMIOS10_10:1; - uint32_t EMIOS9_9:1; - uint32_t EMIOS8_8:1; - uint32_t EMIOS6_6:1; - uint32_t EMIOS5_5:1; - uint32_t EMIOS4_4:1; - uint32_t EMIOS3_3:1; - uint32_t EMIOS2_2:1; - uint32_t EMIOS1_1:1; - uint32_t EMIOS0_0:1; - } B; - } EMIOSB; - - union { /* DSPIBH/L Select Register for DSPI B */ - uint32_t R; - struct { - uint32_t DSPIBH0:1; - uint32_t DSPIBH1:1; - uint32_t DSPIBH2:1; - uint32_t DSPIBH3:1; - uint32_t DSPIBH4:1; - uint32_t DSPIBH5:1; - uint32_t DSPIBH6:1; - uint32_t DSPIBH7:1; - uint32_t DSPIBH8:1; - uint32_t DSPIBH9:1; - uint32_t DSPIBH10:1; - uint32_t DSPIBH11:1; - uint32_t DSPIBH12:1; - uint32_t DSPIBH13:1; - uint32_t DSPIBH14:1; - uint32_t DSPIBH15:1; - uint32_t DSPIBL16:1; - uint32_t DSPIBL17:1; - uint32_t DSPIBL18:1; - uint32_t DSPIBL19:1; - uint32_t DSPIBL20:1; - uint32_t DSPIBL21:1; - uint32_t DSPIBL22:1; - uint32_t DSPIBL23:1; - uint32_t DSPIBL24:1; - uint32_t DSPIBL25:1; - uint32_t DSPIBL26:1; - uint32_t DSPIBL27:1; - uint32_t DSPIBL28:1; - uint32_t DSPIBL29:1; - uint32_t DSPIBL30:1; - uint32_t DSPIBL31:1; - } B; - } DSPIBHLB; - - int32_t SIU_reserved0D5C; /* 0x0D5C-0x0D5F */ - - union { /* ETPU A Select Register */ - uint32_t R; - struct { - uint32_t ETPUA12:1; - uint32_t ETPUA13:1; - uint32_t ETPUA14:1; - uint32_t ETPUA15:1; - uint32_t ETPUA0:1; - uint32_t ETPUA1:1; - uint32_t ETPUA2:1; - uint32_t ETPUA3:1; - uint32_t ETPUA4:1; - uint32_t ETPUA5:1; - uint32_t ETPUA6:1; - uint32_t ETPUA7:1; - uint32_t ETPUA8:1; - uint32_t ETPUA9:1; - uint32_t ETPUA10:1; - uint32_t ETPUA11:1; - uint32_t ETPUA23:1; - uint32_t ETPUA22:1; - uint32_t ETPUA21:1; - uint32_t ETPUA20:1; - uint32_t ETPUA19:1; - uint32_t ETPUA18:1; - uint32_t ETPUA17:1; - uint32_t ETPUA16:1; - uint32_t ETPUA29:1; - uint32_t ETPUA28:1; - uint32_t ETPUA27:1; - uint32_t ETPUA26:1; - uint32_t ETPUA25:1; - uint32_t ETPUA24:1; - uint32_t ETPUA31:1; - uint32_t ETPUA30:1; - } B ; - } ETPUAC; - - union { /* EMIOS C Select Register */ - uint32_t R; - struct { - uint32_t EMIOS12:1; - uint32_t EMIOS13:1; - uint32_t EMIOS14:1; - uint32_t EMIOS15:1; - uint32_t EMIOS23:1; - uint32_t EMIOS0:1; - uint32_t EMIOS1:1; - uint32_t EMIOS2:1; - uint32_t EMIOS3:1; - uint32_t EMIOS4:1; - uint32_t EMIOS5:1; - uint32_t EMIOS6:1; - uint32_t EMIOS8:1; - uint32_t EMIOS9:1; - uint32_t EMIOS10:1; - uint32_t EMIOS11:1; - uint32_t EMIOS23_23:1; - uint32_t EMIOS22:1; - uint32_t EMIOS21:1; - uint32_t EMIOS20:1; - uint32_t EMIOS19:1; - uint32_t EMIOS18:1; - uint32_t EMIOS17:1; - uint32_t EMIOS16:1; - uint32_t EMIOS29:1; - uint32_t EMIOS28:1; - uint32_t EMIOS27:1; - uint32_t EMIOS26:1; - uint32_t EMIOS25:1; - uint32_t EMIOS24:1; - uint32_t EMIOS31:1; - uint32_t EMIOS30:1; - } B; - } EMIOSC; - - union { /* DSPICH/L Select Register for DSPI C */ - uint32_t R; - struct { - uint32_t DSPICH0:1; - uint32_t DSPICH1:1; - uint32_t DSPICH2:1; - uint32_t DSPICH3:1; - uint32_t DSPICH4:1; - uint32_t DSPICH5:1; - uint32_t DSPICH6:1; - uint32_t DSPICH7:1; - uint32_t DSPICH8:1; - uint32_t DSPICH9:1; - uint32_t DSPICH10:1; - uint32_t DSPICH11:1; - uint32_t DSPICH12:1; - uint32_t DSPICH13:1; - uint32_t DSPICH14:1; - uint32_t DSPICH15:1; - uint32_t DSPICL16:1; - uint32_t DSPICL17:1; - uint32_t DSPICL18:1; - uint32_t DSPICL19:1; - uint32_t DSPICL20:1; - uint32_t DSPICL21:1; - uint32_t DSPICL22:1; - uint32_t DSPICL23:1; - uint32_t DSPICL24:1; - uint32_t DSPICL25:1; - uint32_t DSPICL26:1; - uint32_t DSPICL27:1; - uint32_t DSPICL28:1; - uint32_t DSPICL29:1; - uint32_t DSPICL30:1; - uint32_t DSPICL31:1; - } B; - } DSPICHLC; - - int32_t SIU_reserved0D6C; /* 0x0D6C-0x0D6F */ - - union { /* ETPU B Select Register */ - uint32_t R; - struct { - uint32_t ETPUB21:1; - uint32_t ETPUB20:1; - uint32_t ETPUB19:1; - uint32_t ETPUB18:1; - uint32_t ETPUB17:1; - uint32_t ETPUB16:1; - uint32_t:4; - uint32_t ETPUB29:1; - uint32_t ETPUB28:1; - uint32_t ETPUB27:1; - uint32_t ETPUB26:1; - uint32_t ETPUB25:1; - uint32_t ETPUB24:1; - uint32_t:16; - } B ; - } ETPUBD; - - union { /* EMIOS D Select Register */ - uint32_t R; - struct { - uint32_t:6; - uint32_t EMIOS11:1; - uint32_t EMIOS10:1; - uint32_t EMIOS13:1; - uint32_t EMIOS12:1; - uint32_t:22; - } B; - } EMIOSD; - - union { /* DSPIDH/L Select Register for DSPI D */ - uint32_t R; - struct { - uint32_t:32; - } B; - } DSPIDHLD; - - int32_t SIU_reserved0D7C; /* 0x0D7C-0x0D7F */ - - int32_t SIU_reserved0D80[32]; /* 0x0D80-0x0DFF */ - - union { /* GPIO Pin Data Input Registers */ - uint8_t R; - struct { - uint8_t:7; - uint8_t PDI:1; - } B; - } GPDI0_511[512]; - - uint32_t SIU_reserved1000[3072]; /* 0x1000-0x3FFF */ - }; - -/****************************************************************************/ -/* MODULE : EMIOS */ -/****************************************************************************/ - - struct EMIOS_tag { - - union EMIOS_MCR_tag { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t:1; - uint32_t MDIS:1; - uint32_t FRZ:1; - uint32_t GTBE:1; - uint32_t ETB:1; - uint32_t GPREN:1; - uint32_t:6; - uint32_t SRV:4; - uint32_t GPRE:8; - uint32_t:8; - } B; - } MCR; - - union { /* Global FLAG Register */ - uint32_t R; - struct { - uint32_t F31:1; - uint32_t F30:1; - uint32_t F29:1; - uint32_t F28:1; - uint32_t F27:1; - uint32_t F26:1; - uint32_t F25:1; - uint32_t F24:1; - uint32_t F23:1; - uint32_t F22:1; - uint32_t F21:1; - uint32_t F20:1; - uint32_t F19:1; - uint32_t F18:1; - uint32_t F17:1; - uint32_t F16:1; - uint32_t F15:1; - uint32_t F14:1; - uint32_t F13:1; - uint32_t F12:1; - uint32_t F11:1; - uint32_t F10:1; - uint32_t F9:1; - uint32_t F8:1; - uint32_t F7:1; - uint32_t F6:1; - uint32_t F5:1; - uint32_t F4:1; - uint32_t F3:1; - uint32_t F2:1; - uint32_t F1:1; - uint32_t F0:1; - } B; - } GFR; - - union { /* Output Update Disable Register */ - uint32_t R; - struct { - uint32_t OU31:1; - uint32_t OU30:1; - uint32_t OU29:1; - uint32_t OU28:1; - uint32_t OU27:1; - uint32_t OU26:1; - uint32_t OU25:1; - uint32_t OU24:1; - uint32_t OU23:1; - uint32_t OU22:1; - uint32_t OU21:1; - uint32_t OU20:1; - uint32_t OU19:1; - uint32_t OU18:1; - uint32_t OU17:1; - uint32_t OU16:1; - uint32_t OU15:1; - uint32_t OU14:1; - uint32_t OU13:1; - uint32_t OU12:1; - uint32_t OU11:1; - uint32_t OU10:1; - uint32_t OU9:1; - uint32_t OU8:1; - uint32_t OU7:1; - uint32_t OU6:1; - uint32_t OU5:1; - uint32_t OU4:1; - uint32_t OU3:1; - uint32_t OU2:1; - uint32_t OU1:1; - uint32_t OU0:1; - } B; - } OUDR; - - uint32_t eMIOS_reserved000C[5]; /* 0x000C-0x001F */ - - struct EMIOS_CH_tag { - union { /* Channel A Data Register */ - uint32_t R; - } CADR; - - union { /* Channel B Data Register */ - uint32_t R; - } CBDR; - - union { /* Channel Counter Register */ - uint32_t R; - } CCNTR; - - union EMIOS_CCR_tag {/* Channel Control Register */ - uint32_t R; - struct { - uint32_t FREN:1; - uint32_t ODIS:1; - uint32_t ODISSL:2; - uint32_t UCPRE:2; - uint32_t UCPREN:1; - uint32_t DMA:1; - uint32_t:1; - uint32_t IF:4; - uint32_t FCK:1; - uint32_t FEN:1; - uint32_t:3; - uint32_t FORCMA:1; - uint32_t FORCMB:1; - uint32_t:1; - uint32_t BSL:2; - uint32_t EDSEL:1; - uint32_t EDPOL:1; - uint32_t MODE:7; - } B; - } CCR; - - union EMIOS_CSR_tag {/* Channel Status Register */ - uint32_t R; - struct { - uint32_t OVR:1; - uint32_t:15; - uint32_t OVFL:1; - uint32_t:12; - uint32_t UCIN:1; - uint32_t UCOUT:1; - uint32_t FLAG:1; - } B; - } CSR; - - union { /* Alternate Channel A Data Register */ - uint32_t R; - } ALTA; - - uint32_t eMIOS_channel_reserved0018[2]; /* 0x0018-0x001F */ - - } CH[32]; - - uint32_t eMIOS_reserved0420[3832]; /* 0x0420-0x3FFF */ - - }; - -/****************************************************************************/ -/* MODULE : PMC */ -/****************************************************************************/ - - struct PMC_tag { - - union { - uint32_t R; - struct { - uint32_t LVRER:1; - uint32_t LVREH:1; - uint32_t LVRE50:1; - uint32_t LVRE33:1; - uint32_t LVREC:1; - uint32_t LVREA:1; - uint32_t:1; - uint32_t:1; - uint32_t LVIER:1; - uint32_t LVIEH:1; - uint32_t LVIE50:1; - uint32_t LVIE33:1; - uint32_t LVIEC:1; - uint32_t LVIEA:1; - uint32_t:1; - uint32_t TLK:1; - uint32_t:16; - } B; - } MCR; /* Module Configuration Register */ - - union { - uint32_t R; - struct { - uint32_t :8; - uint32_t LVDATRIM:4; - uint32_t LVDREGTRIM:4; - uint32_t VDD33TRIM:4; - uint32_t LVD33TRIM:4; - uint32_t VDDCTRIM:4; - uint32_t LVDCTRIM:4; - } B; - } TRIMR; /* Trimming register */ - - union { - uint32_t R; - struct { - uint32_t :5; - uint32_t LVFSTBY:1; - uint32_t BGRDY:1; - uint32_t BGTS:1; - uint32_t :5; - uint32_t LVFCSTBY:1; - uint32_t :2; - uint32_t LVFCR:1; - uint32_t LVFCH:1; - uint32_t LVFC50:1; - uint32_t LVFC33:1; - uint32_t LVFCC:1; - uint32_t LVFCA:1; - uint32_t :2; - uint32_t LVFR:1; - uint32_t LVFH:1; - uint32_t LVF50:1; - uint32_t LVF33:1; - uint32_t LVFC:1; - uint32_t LVFA:1; - uint32_t :2; - } B; - } SR; /* status register */ - - uint32_t PMC_reserved000C[4093]; /* 0x000C-0x3FFF */ - }; - -/****************************************************************************/ -/* MODULE :ETPU */ -/****************************************************************************/ - -/***************************Configuration Registers**************************/ - - struct ETPU_tag { - union { /* MODULE CONFIGURATION REGISTER */ - uint32_t R; - struct { - uint32_t GEC:1; /* Global Exception Clear */ - uint32_t SDMERR:1; /* SDM Read Error */ - uint32_t WDTOA:1; /* Watchdog Timeout-eTPU_A */ - uint32_t WDTOB:1; /* Watchdog Timeout-eTPU_B */ - uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */ - uint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */ - uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */ - uint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */ - uint32_t:3; - uint32_t SCMSIZE:5; /* Shared Code Memory size */ - uint32_t:4; - uint32_t SCMMISC:1; /* SCM MISC Complete/Clear */ - uint32_t SCMMISF:1; /* SCM MISC Flag */ - uint32_t SCMMISEN:1; /* SCM MISC Enable */ - uint32_t:2; - uint32_t VIS:1; /* SCM Visability */ - uint32_t:5; - uint32_t GTBE:1; /* Global Time Base Enable */ - } B; - } MCR; - - union { /* COHERENT DUAL-PARAMETER CONTROL */ - uint32_t R; - struct { - uint32_t STS:1; /* Start Status bit */ - uint32_t CTBASE:5; /* Channel Transfer Base */ - uint32_t PBASE:10; /* Parameter Buffer Base Address */ - uint32_t PWIDTH:1; /* Parameter Width */ - uint32_t PARAM0:7; /* Channel Parameter 0 */ - uint32_t WR:1; /* Read/Write selection */ - uint32_t PARAM1:7; /* Channel Parameter 1 */ - } B; - } CDCR; - - uint32_t eTPU_reserved0008; /* 0x0008-0x000B */ - - union { /* MISC Compare Register */ - uint32_t R; - struct { - uint32_t ETPUMISCCMP:32; - } B; - } MISCCMPR; - - union { /* SCM off-range Date Register */ - uint32_t R; - struct { - uint32_t ETPUSCMOFFDATA:32; - } B; - } SCMOFFDATAR; - - union { /* ETPU_A Configuration Register */ - uint32_t R; - struct { - uint32_t FEND:1; /* Force END */ - uint32_t MDIS:1; /* Low power Stop */ - uint32_t:1; - uint32_t STF:1; /* Stop Flag */ - uint32_t:4; - uint32_t HLTF:1; /* Halt Mode Flag */ - uint32_t:3; - uint32_t FCSS:1; /* Filter Clock Source Select */ - uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ - uint32_t CDFC:2; - uint32_t:1; - uint32_t ERBA:5; /* Engine Relative Base Address */ - uint32_t SPPDIS:1; /* Schedule Priority Passing Disable */ - uint32_t:2; - uint32_t ETB:5; /* Entry Table Base */ - } B; - } ECR_A; - - union { /* ETPU_B Configuration Register */ - uint32_t R; - struct { - uint32_t FEND:1; /* Force END */ - uint32_t MDIS:1; /* Low power Stop */ - uint32_t:1; - uint32_t STF:1; /* Stop Flag */ - uint32_t:4; - uint32_t HLTF:1; /* Halt Mode Flag */ - uint32_t:3; - uint32_t FCSS:1; /* Filter Clock Source Select */ - uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ - uint32_t CDFC:2; - uint32_t:1; - uint32_t ERBA:5; /* Engine Relative Base Address */ - uint32_t SPPDIS:1; /* Schedule Priority Passing Disable */ - uint32_t:2; - uint32_t ETB:5; /* Entry Table Base */ - } B; - } ECR_B; - - uint32_t eTPU_reserved001C; /* 0x001C-0x001F */ - - union { /* ETPU_A Timebase Configuration Register */ - uint32_t R; - struct { - uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ - uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ - uint32_t AM:2; /* Angle Mode */ - uint32_t:3; - uint32_t TCR2P:6; /* TCR2 Prescaler Control */ - uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ - uint32_t TCR1CS:1; /* TCR1 Clock Source */ - uint32_t:5; - uint32_t TCR1P:8; /* TCR1 Prescaler Control */ - } B; - } TBCR_A; - - union { /* ETPU_A TCR1 Visibility Register */ - uint32_t R; - struct { - uint32_t:8; - uint32_t TCR1:24; - } B; - } TB1R_A; - - union { /* ETPU_A TCR2 Visibility Register */ - uint32_t R; - struct { - uint32_t:8; - uint32_t TCR2:24; - } B; - } TB2R_A; - - union { /* ETPU_A STAC Configuration Register */ - uint32_t R; - struct { - uint32_t REN1:1; /* Resource Enable TCR1 */ - uint32_t RSC1:1; /* Resource Control TCR1 */ - uint32_t:2; - uint32_t SERVER_ID1:4; /* TCR1 Server ID */ - uint32_t:4; - uint32_t SRV1:4; /* Resource Server Slot */ - uint32_t REN2:1; /* Resource Enable TCR2 */ - uint32_t RSC2:1; /* Resource Control TCR2 */ - uint32_t:2; - uint32_t SERVER_ID2:4; /* TCR2 Server ID */ - uint32_t:4; - uint32_t SRV2:4; /* Resource Server Slot */ - } B; - } REDCR_A; - - uint32_t eTPU_reserved0030[4]; /* 0x0030-0x003F */ - - union { /* ETPU_B Timebase Configuration Register */ - uint32_t R; - struct { - uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ - uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ - uint32_t AM:2; /* Angle Mode */ - uint32_t:3; - uint32_t TCR2P:6; /* TCR2 Prescaler Control */ - uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ - uint32_t TCR1CS:1; /* TCR1 Clock Source */ - uint32_t:5; - uint32_t TCR1P:8; /* TCR1 Prescaler Control */ - } B; - } TBCR_B; - - union { /* ETPU_B TCR1 Visibility Register */ - uint32_t R; - struct { - uint32_t:8; - uint32_t TCR1:24; - } B; - } TB1R_B; - - union { /* ETPU_B TCR2 Visibility Register */ - uint32_t R; - struct { - uint32_t:8; - uint32_t TCR2:24; - } B; - } TB2R_B; - - union { /* ETPU_B STAC Configuration Register */ - uint32_t R; - struct { - uint32_t REN1:1; /* Resource Enable TCR1 */ - uint32_t RSC1:1; /* Resource Control TCR1 */ - uint32_t:2; - uint32_t SERVER_ID1:4; /* TCR1 Server ID */ - uint32_t:4; - uint32_t SRV1:4; /* Resource Server Slot */ - uint32_t REN2:1; /* Resource Enable TCR2 */ - uint32_t RSC2:1; /* Resource Control TCR2 */ - uint32_t:2; - uint32_t SERVER_ID2:4; /* TCR2 Server ID */ - uint32_t:4; - uint32_t SRV2:4; /* Resource Server Slot */ - } B; - } REDCR_B; - - uint32_t eTPU_reserved0050[4]; /* 0x0050-0x005F */ - - union { /* Watchdog Timer Register A */ - uint32_t R; - struct { - uint32_t WDM:2; /* Watchdog Mode */ - uint32_t:14; - uint32_t WDCNT:16; /* Watchdog Count */ - } B; - } WDTR_A; - - uint32_t eTPU_reserved0064; /* 0x0064-0x0067 */ - - union { /* Idle Counter Register A*/ - uint32_t R; - struct { - uint32_t IDLE_CNT:31; - uint32_t ICLR:1; /* Idle Clear */ - } B; - - } IDLE_A; - - uint32_t eTPU_reserved006C; /* 0x006C-0x006F */ - - union { /* Watchdog Timer Register B */ - uint32_t R; - struct { - uint32_t WDM:2; /* Watchdog Mode */ - uint32_t:14; - uint32_t WDCNT:16; /* Watchdog Count */ - } B; - } WDTR_B; - - uint32_t eTPU_reserved0074; /* 0x0074-0x0077 */ - - union { /* Idle Counter Register B*/ - uint32_t R; - struct { - uint32_t IDLE_CNT:31; - uint32_t ICLR:1; /* Idle Clear */ - } B; - } IDLE_B; - - uint32_t eTPU_reserved007C; /* 0x007C-0x007F */ - - uint32_t eTPU_reserved0080[96]; /* 0x0080-0x01FF */ - -/*****************************Status and Control Registers**************************/ - - union { /* ETPU_A Channel Interrut Status */ - uint32_t R; - struct { - uint32_t CIS31:1; /* Channel 31 Interrut Status */ - uint32_t CIS30:1; /* Channel 30 Interrut Status */ - uint32_t CIS29:1; /* Channel 29 Interrut Status */ - uint32_t CIS28:1; /* Channel 28 Interrut Status */ - uint32_t CIS27:1; /* Channel 27 Interrut Status */ - uint32_t CIS26:1; /* Channel 26 Interrut Status */ - uint32_t CIS25:1; /* Channel 25 Interrut Status */ - uint32_t CIS24:1; /* Channel 24 Interrut Status */ - uint32_t CIS23:1; /* Channel 23 Interrut Status */ - uint32_t CIS22:1; /* Channel 22 Interrut Status */ - uint32_t CIS21:1; /* Channel 21 Interrut Status */ - uint32_t CIS20:1; /* Channel 20 Interrut Status */ - uint32_t CIS19:1; /* Channel 19 Interrut Status */ - uint32_t CIS18:1; /* Channel 18 Interrut Status */ - uint32_t CIS17:1; /* Channel 17 Interrut Status */ - uint32_t CIS16:1; /* Channel 16 Interrut Status */ - uint32_t CIS15:1; /* Channel 15 Interrut Status */ - uint32_t CIS14:1; /* Channel 14 Interrut Status */ - uint32_t CIS13:1; /* Channel 13 Interrut Status */ - uint32_t CIS12:1; /* Channel 12 Interrut Status */ - uint32_t CIS11:1; /* Channel 11 Interrut Status */ - uint32_t CIS10:1; /* Channel 10 Interrut Status */ - uint32_t CIS9:1; /* Channel 9 Interrut Status */ - uint32_t CIS8:1; /* Channel 8 Interrut Status */ - uint32_t CIS7:1; /* Channel 7 Interrut Status */ - uint32_t CIS6:1; /* Channel 6 Interrut Status */ - uint32_t CIS5:1; /* Channel 5 Interrut Status */ - uint32_t CIS4:1; /* Channel 4 Interrut Status */ - uint32_t CIS3:1; /* Channel 3 Interrut Status */ - uint32_t CIS2:1; /* Channel 2 Interrut Status */ - uint32_t CIS1:1; /* Channel 1 Interrut Status */ - uint32_t CIS0:1; /* Channel 0 Interrut Status */ - } B; - } CISR_A; - - union { /* ETPU_B Channel Interruput Status */ - uint32_t R; - struct { - uint32_t CIS31:1; /* Channel 31 Interrut Status */ - uint32_t CIS30:1; /* Channel 30 Interrut Status */ - uint32_t CIS29:1; /* Channel 29 Interrut Status */ - uint32_t CIS28:1; /* Channel 28 Interrut Status */ - uint32_t CIS27:1; /* Channel 27 Interrut Status */ - uint32_t CIS26:1; /* Channel 26 Interrut Status */ - uint32_t CIS25:1; /* Channel 25 Interrut Status */ - uint32_t CIS24:1; /* Channel 24 Interrut Status */ - uint32_t CIS23:1; /* Channel 23 Interrut Status */ - uint32_t CIS22:1; /* Channel 22 Interrut Status */ - uint32_t CIS21:1; /* Channel 21 Interrut Status */ - uint32_t CIS20:1; /* Channel 20 Interrut Status */ - uint32_t CIS19:1; /* Channel 19 Interrut Status */ - uint32_t CIS18:1; /* Channel 18 Interrut Status */ - uint32_t CIS17:1; /* Channel 17 Interrut Status */ - uint32_t CIS16:1; /* Channel 16 Interrut Status */ - uint32_t CIS15:1; /* Channel 15 Interrut Status */ - uint32_t CIS14:1; /* Channel 14 Interrut Status */ - uint32_t CIS13:1; /* Channel 13 Interrut Status */ - uint32_t CIS12:1; /* Channel 12 Interrut Status */ - uint32_t CIS11:1; /* Channel 11 Interrut Status */ - uint32_t CIS10:1; /* Channel 10 Interrut Status */ - uint32_t CIS9:1; /* Channel 9 Interrut Status */ - uint32_t CIS8:1; /* Channel 8 Interrut Status */ - uint32_t CIS7:1; /* Channel 7 Interrut Status */ - uint32_t CIS6:1; /* Channel 6 Interrut Status */ - uint32_t CIS5:1; /* Channel 5 Interrut Status */ - uint32_t CIS4:1; /* Channel 4 Interrut Status */ - uint32_t CIS3:1; /* Channel 3 Interrut Status */ - uint32_t CIS2:1; /* Channel 2 Interrut Status */ - uint32_t CIS1:1; /* Channel 1 Interrupt Status */ - uint32_t CIS0:1; /* Channel 0 Interrupt Status */ - } B; - } CISR_B; - - uint32_t eTPU_reserved0208[2]; /* 0x0208-0x020F */ - - union { /* ETPU_A Data Transfer Request Status */ - uint32_t R; - struct { - uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ - uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ - uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ - uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ - uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ - uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ - uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ - uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ - uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ - uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ - uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ - uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ - uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ - uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ - uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ - uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ - uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ - uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ - uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ - uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ - uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ - uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ - uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ - uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ - uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ - uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ - uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ - uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ - uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ - uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ - uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ - uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ - } B; - } CDTRSR_A; - - union { /* ETPU_B Data Transfer Request Status */ - uint32_t R; - struct { - uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ - uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ - uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ - uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ - uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ - uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ - uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ - uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ - uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ - uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ - uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ - uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ - uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ - uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ - uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ - uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ - uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ - uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ - uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ - uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ - uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ - uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ - uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ - uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ - uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ - uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ - uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ - uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ - uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ - uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ - uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ - uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ - } B; - } CDTRSR_B; - - uint32_t eTPU_reserved0218[2]; /* 0x0218-0x021F */ - - union { /* ETPU_A Interruput Overflow Status */ - uint32_t R; - struct { - uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ - uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ - uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ - uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ - uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ - uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ - uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ - uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ - uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ - uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ - uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ - uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ - uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ - uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ - uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ - uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ - uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ - uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ - uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ - uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ - uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ - uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ - uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ - uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ - uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ - uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ - uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ - uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ - uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ - uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ - uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ - uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ - } B; - } CIOSR_A; - - union { /* ETPU_B Interruput Overflow Status */ - uint32_t R; - struct { - uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ - uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ - uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ - uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ - uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ - uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ - uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ - uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ - uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ - uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ - uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ - uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ - uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ - uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ - uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ - uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ - uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ - uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ - uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ - uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ - uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ - uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ - uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ - uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ - uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ - uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ - uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ - uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ - uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ - uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ - uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ - uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ - } B; - } CIOSR_B; - - uint32_t eTPU_reserved0228[2]; /* 0x0228-0x022F */ - - union { /* ETPU_A Data Transfer Overflow Status */ - uint32_t R; - struct { - uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ - uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ - uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ - uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ - uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ - uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ - uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ - uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ - uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ - uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ - uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ - uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ - uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ - uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ - uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ - uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ - uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ - uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ - uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ - uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ - uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ - uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ - uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ - uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ - uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ - uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ - uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ - uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ - uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ - uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ - uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ - uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ - } B; - } CDTROSR_A; - - union { /* ETPU_B Data Transfer Overflow Status */ - uint32_t R; - struct { - uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ - uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ - uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ - uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ - uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ - uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ - uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ - uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ - uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ - uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ - uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ - uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ - uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ - uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ - uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ - uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ - uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ - uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ - uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ - uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ - uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ - uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ - uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ - uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ - uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ - uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ - uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ - uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ - uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ - uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ - uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ - uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ - } B; - } CDTROSR_B; - - uint32_t eTPU_reserved0238[2]; /* 0x0238-0x023F */ - - union { /* ETPU_A Channel Interruput Enable */ - uint32_t R; - struct { - uint32_t CIE31:1; /* Channel 31 Interruput Enable */ - uint32_t CIE30:1; /* Channel 30 Interruput Enable */ - uint32_t CIE29:1; /* Channel 29 Interruput Enable */ - uint32_t CIE28:1; /* Channel 28 Interruput Enable */ - uint32_t CIE27:1; /* Channel 27 Interruput Enable */ - uint32_t CIE26:1; /* Channel 26 Interruput Enable */ - uint32_t CIE25:1; /* Channel 25 Interruput Enable */ - uint32_t CIE24:1; /* Channel 24 Interruput Enable */ - uint32_t CIE23:1; /* Channel 23 Interruput Enable */ - uint32_t CIE22:1; /* Channel 22 Interruput Enable */ - uint32_t CIE21:1; /* Channel 21 Interruput Enable */ - uint32_t CIE20:1; /* Channel 20 Interruput Enable */ - uint32_t CIE19:1; /* Channel 19 Interruput Enable */ - uint32_t CIE18:1; /* Channel 18 Interruput Enable */ - uint32_t CIE17:1; /* Channel 17 Interruput Enable */ - uint32_t CIE16:1; /* Channel 16 Interruput Enable */ - uint32_t CIE15:1; /* Channel 15 Interruput Enable */ - uint32_t CIE14:1; /* Channel 14 Interruput Enable */ - uint32_t CIE13:1; /* Channel 13 Interruput Enable */ - uint32_t CIE12:1; /* Channel 12 Interruput Enable */ - uint32_t CIE11:1; /* Channel 11 Interruput Enable */ - uint32_t CIE10:1; /* Channel 10 Interruput Enable */ - uint32_t CIE9:1; /* Channel 9 Interruput Enable */ - uint32_t CIE8:1; /* Channel 8 Interruput Enable */ - uint32_t CIE7:1; /* Channel 7 Interruput Enable */ - uint32_t CIE6:1; /* Channel 6 Interruput Enable */ - uint32_t CIE5:1; /* Channel 5 Interruput Enable */ - uint32_t CIE4:1; /* Channel 4 Interruput Enable */ - uint32_t CIE3:1; /* Channel 3 Interruput Enable */ - uint32_t CIE2:1; /* Channel 2 Interruput Enable */ - uint32_t CIE1:1; /* Channel 1 Interruput Enable */ - uint32_t CIE0:1; /* Channel 0 Interruput Enable */ - } B; - } CIER_A; - - union { /* ETPU_B Channel Interruput Enable */ - uint32_t R; - struct { - uint32_t CIE31:1; /* Channel 31 Interruput Enable */ - uint32_t CIE30:1; /* Channel 30 Interruput Enable */ - uint32_t CIE29:1; /* Channel 29 Interruput Enable */ - uint32_t CIE28:1; /* Channel 28 Interruput Enable */ - uint32_t CIE27:1; /* Channel 27 Interruput Enable */ - uint32_t CIE26:1; /* Channel 26 Interruput Enable */ - uint32_t CIE25:1; /* Channel 25 Interruput Enable */ - uint32_t CIE24:1; /* Channel 24 Interruput Enable */ - uint32_t CIE23:1; /* Channel 23 Interruput Enable */ - uint32_t CIE22:1; /* Channel 22 Interruput Enable */ - uint32_t CIE21:1; /* Channel 21 Interruput Enable */ - uint32_t CIE20:1; /* Channel 20 Interruput Enable */ - uint32_t CIE19:1; /* Channel 19 Interruput Enable */ - uint32_t CIE18:1; /* Channel 18 Interruput Enable */ - uint32_t CIE17:1; /* Channel 17 Interruput Enable */ - uint32_t CIE16:1; /* Channel 16 Interruput Enable */ - uint32_t CIE15:1; /* Channel 15 Interruput Enable */ - uint32_t CIE14:1; /* Channel 14 Interruput Enable */ - uint32_t CIE13:1; /* Channel 13 Interruput Enable */ - uint32_t CIE12:1; /* Channel 12 Interruput Enable */ - uint32_t CIE11:1; /* Channel 11 Interruput Enable */ - uint32_t CIE10:1; /* Channel 10 Interruput Enable */ - uint32_t CIE9:1; /* Channel 9 Interruput Enable */ - uint32_t CIE8:1; /* Channel 8 Interruput Enable */ - uint32_t CIE7:1; /* Channel 7 Interruput Enable */ - uint32_t CIE6:1; /* Channel 6 Interruput Enable */ - uint32_t CIE5:1; /* Channel 5 Interruput Enable */ - uint32_t CIE4:1; /* Channel 4 Interruput Enable */ - uint32_t CIE3:1; /* Channel 3 Interruput Enable */ - uint32_t CIE2:1; /* Channel 2 Interruput Enable */ - uint32_t CIE1:1; /* Channel 1 Interruput Enable */ - uint32_t CIE0:1; /* Channel 0 Interruput Enable */ - } B; - } CIER_B; - - uint32_t eTPU_reserved0248[2]; /* 0x0248-0x024F */ - - union { /* ETPU_A Channel Data Transfer Request Enable */ - uint32_t R; - struct { - uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ - uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ - uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ - uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ - uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ - uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ - uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ - uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ - uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ - uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ - uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ - uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ - uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ - uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ - uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ - uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ - uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ - uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ - uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ - uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ - uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ - uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ - uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ - uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ - uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ - uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ - uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ - uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ - uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ - uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ - uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ - uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CDTRER_A; - - union { /* ETPU_B Channel Data Transfer Request Enable */ - uint32_t R; - struct { - uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ - uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ - uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ - uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ - uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ - uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ - uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ - uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ - uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ - uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ - uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ - uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ - uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ - uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ - uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ - uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ - uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ - uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ - uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ - uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ - uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ - uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ - uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ - uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ - uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ - uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ - uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ - uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ - uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ - uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ - uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ - uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CDTRER_B; - - uint32_t eTPU_reserved0258[2]; /* 0x0258-0x025F */ - - union { /* Watchdog Status Register A */ - uint32_t R; - struct { - uint32_t WDS31:1; - uint32_t WDS30:1; - uint32_t WDS29:1; - uint32_t WDS28:1; - uint32_t WDS27:1; - uint32_t WDS26:1; - uint32_t WDS25:1; - uint32_t WDS24:1; - uint32_t WDS23:1; - uint32_t WDS22:1; - uint32_t WDS21:1; - uint32_t WDS20:1; - uint32_t WDS19:1; - uint32_t WDS18:1; - uint32_t WDS17:1; - uint32_t WDS16:1; - uint32_t WDS15:1; - uint32_t WDS14:1; - uint32_t WDS13:1; - uint32_t WDS12:1; - uint32_t WDS11:1; - uint32_t WDS10:1; - uint32_t WDS9:1; - uint32_t WDS8:1; - uint32_t WDS7:1; - uint32_t WDS6:1; - uint32_t WDS5:1; - uint32_t WDS4:1; - uint32_t WDS3:1; - uint32_t WDS2:1; - uint32_t WDS1:1; - uint32_t WDS0:1; - } B; - } WDSR_A; - - union { /* Watchdog Status Register B */ - uint32_t R; - struct { - uint32_t WDS31:1; - uint32_t WDS30:1; - uint32_t WDS29:1; - uint32_t WDS28:1; - uint32_t WDS27:1; - uint32_t WDS26:1; - uint32_t WDS25:1; - uint32_t WDS24:1; - uint32_t WDS23:1; - uint32_t WDS22:1; - uint32_t WDS21:1; - uint32_t WDS20:1; - uint32_t WDS19:1; - uint32_t WDS18:1; - uint32_t WDS17:1; - uint32_t WDS16:1; - uint32_t WDS15:1; - uint32_t WDS14:1; - uint32_t WDS13:1; - uint32_t WDS12:1; - uint32_t WDS11:1; - uint32_t WDS10:1; - uint32_t WDS9:1; - uint32_t WDS8:1; - uint32_t WDS7:1; - uint32_t WDS6:1; - uint32_t WDS5:1; - uint32_t WDS4:1; - uint32_t WDS3:1; - uint32_t WDS2:1; - uint32_t WDS1:1; - uint32_t WDS0:1; - } B; - } WDSR_B; - - uint32_t eTPU_reserved0268[6]; /* 0x0268-0x027F */ - - union { /* ETPU_A Channel Pending Service Status */ - uint32_t R; - struct { - uint32_t SR31:1; /* Channel 31 Pending Service Status */ - uint32_t SR30:1; /* Channel 30 Pending Service Status */ - uint32_t SR29:1; /* Channel 29 Pending Service Status */ - uint32_t SR28:1; /* Channel 28 Pending Service Status */ - uint32_t SR27:1; /* Channel 27 Pending Service Status */ - uint32_t SR26:1; /* Channel 26 Pending Service Status */ - uint32_t SR25:1; /* Channel 25 Pending Service Status */ - uint32_t SR24:1; /* Channel 24 Pending Service Status */ - uint32_t SR23:1; /* Channel 23 Pending Service Status */ - uint32_t SR22:1; /* Channel 22 Pending Service Status */ - uint32_t SR21:1; /* Channel 21 Pending Service Status */ - uint32_t SR20:1; /* Channel 20 Pending Service Status */ - uint32_t SR19:1; /* Channel 19 Pending Service Status */ - uint32_t SR18:1; /* Channel 18 Pending Service Status */ - uint32_t SR17:1; /* Channel 17 Pending Service Status */ - uint32_t SR16:1; /* Channel 16 Pending Service Status */ - uint32_t SR15:1; /* Channel 15 Pending Service Status */ - uint32_t SR14:1; /* Channel 14 Pending Service Status */ - uint32_t SR13:1; /* Channel 13 Pending Service Status */ - uint32_t SR12:1; /* Channel 12 Pending Service Status */ - uint32_t SR11:1; /* Channel 11 Pending Service Status */ - uint32_t SR10:1; /* Channel 10 Pending Service Status */ - uint32_t SR9:1; /* Channel 9 Pending Service Status */ - uint32_t SR8:1; /* Channel 8 Pending Service Status */ - uint32_t SR7:1; /* Channel 7 Pending Service Status */ - uint32_t SR6:1; /* Channel 6 Pending Service Status */ - uint32_t SR5:1; /* Channel 5 Pending Service Status */ - uint32_t SR4:1; /* Channel 4 Pending Service Status */ - uint32_t SR3:1; /* Channel 3 Pending Service Status */ - uint32_t SR2:1; /* Channel 2 Pending Service Status */ - uint32_t SR1:1; /* Channel 1 Pending Service Status */ - uint32_t SR0:1; /* Channel 0 Pending Service Status */ - } B; - } CPSSR_A; - - union { /* ETPU_B Channel Pending Service Status */ - uint32_t R; - struct { - uint32_t SR31:1; /* Channel 31 Pending Service Status */ - uint32_t SR30:1; /* Channel 30 Pending Service Status */ - uint32_t SR29:1; /* Channel 29 Pending Service Status */ - uint32_t SR28:1; /* Channel 28 Pending Service Status */ - uint32_t SR27:1; /* Channel 27 Pending Service Status */ - uint32_t SR26:1; /* Channel 26 Pending Service Status */ - uint32_t SR25:1; /* Channel 25 Pending Service Status */ - uint32_t SR24:1; /* Channel 24 Pending Service Status */ - uint32_t SR23:1; /* Channel 23 Pending Service Status */ - uint32_t SR22:1; /* Channel 22 Pending Service Status */ - uint32_t SR21:1; /* Channel 21 Pending Service Status */ - uint32_t SR20:1; /* Channel 20 Pending Service Status */ - uint32_t SR19:1; /* Channel 19 Pending Service Status */ - uint32_t SR18:1; /* Channel 18 Pending Service Status */ - uint32_t SR17:1; /* Channel 17 Pending Service Status */ - uint32_t SR16:1; /* Channel 16 Pending Service Status */ - uint32_t SR15:1; /* Channel 15 Pending Service Status */ - uint32_t SR14:1; /* Channel 14 Pending Service Status */ - uint32_t SR13:1; /* Channel 13 Pending Service Status */ - uint32_t SR12:1; /* Channel 12 Pending Service Status */ - uint32_t SR11:1; /* Channel 11 Pending Service Status */ - uint32_t SR10:1; /* Channel 10 Pending Service Status */ - uint32_t SR9:1; /* Channel 9 Pending Service Status */ - uint32_t SR8:1; /* Channel 8 Pending Service Status */ - uint32_t SR7:1; /* Channel 7 Pending Service Status */ - uint32_t SR6:1; /* Channel 6 Pending Service Status */ - uint32_t SR5:1; /* Channel 5 Pending Service Status */ - uint32_t SR4:1; /* Channel 4 Pending Service Status */ - uint32_t SR3:1; /* Channel 3 Pending Service Status */ - uint32_t SR2:1; /* Channel 2 Pending Service Status */ - uint32_t SR1:1; /* Channel 1 Pending Service Status */ - uint32_t SR0:1; /* Channel 0 Pending Service Status */ - } B; - } CPSSR_B; - - uint32_t eTPU_reserved0288[2]; /* 0x0288-0x028F */ - - union { /* ETPU_A Channel Service Status */ - uint32_t R; - struct { - uint32_t SS31:1; /* Channel 31 Service Status */ - uint32_t SS30:1; /* Channel 30 Service Status */ - uint32_t SS29:1; /* Channel 29 Service Status */ - uint32_t SS28:1; /* Channel 28 Service Status */ - uint32_t SS27:1; /* Channel 27 Service Status */ - uint32_t SS26:1; /* Channel 26 Service Status */ - uint32_t SS25:1; /* Channel 25 Service Status */ - uint32_t SS24:1; /* Channel 24 Service Status */ - uint32_t SS23:1; /* Channel 23 Service Status */ - uint32_t SS22:1; /* Channel 22 Service Status */ - uint32_t SS21:1; /* Channel 21 Service Status */ - uint32_t SS20:1; /* Channel 20 Service Status */ - uint32_t SS19:1; /* Channel 19 Service Status */ - uint32_t SS18:1; /* Channel 18 Service Status */ - uint32_t SS17:1; /* Channel 17 Service Status */ - uint32_t SS16:1; /* Channel 16 Service Status */ - uint32_t SS15:1; /* Channel 15 Service Status */ - uint32_t SS14:1; /* Channel 14 Service Status */ - uint32_t SS13:1; /* Channel 13 Service Status */ - uint32_t SS12:1; /* Channel 12 Service Status */ - uint32_t SS11:1; /* Channel 11 Service Status */ - uint32_t SS10:1; /* Channel 10 Service Status */ - uint32_t SS9:1; /* Channel 9 Service Status */ - uint32_t SS8:1; /* Channel 8 Service Status */ - uint32_t SS7:1; /* Channel 7 Service Status */ - uint32_t SS6:1; /* Channel 6 Service Status */ - uint32_t SS5:1; /* Channel 5 Service Status */ - uint32_t SS4:1; /* Channel 4 Service Status */ - uint32_t SS3:1; /* Channel 3 Service Status */ - uint32_t SS2:1; /* Channel 2 Service Status */ - uint32_t SS1:1; /* Channel 1 Service Status */ - uint32_t SS0:1; /* Channel 0 Service Status */ - } B; - } CSSR_A; - - union { /* ETPU_B Channel Service Status */ - uint32_t R; - struct { - uint32_t SS31:1; /* Channel 31 Service Status */ - uint32_t SS30:1; /* Channel 30 Service Status */ - uint32_t SS29:1; /* Channel 29 Service Status */ - uint32_t SS28:1; /* Channel 28 Service Status */ - uint32_t SS27:1; /* Channel 27 Service Status */ - uint32_t SS26:1; /* Channel 26 Service Status */ - uint32_t SS25:1; /* Channel 25 Service Status */ - uint32_t SS24:1; /* Channel 24 Service Status */ - uint32_t SS23:1; /* Channel 23 Service Status */ - uint32_t SS22:1; /* Channel 22 Service Status */ - uint32_t SS21:1; /* Channel 21 Service Status */ - uint32_t SS20:1; /* Channel 20 Service Status */ - uint32_t SS19:1; /* Channel 19 Service Status */ - uint32_t SS18:1; /* Channel 18 Service Status */ - uint32_t SS17:1; /* Channel 17 Service Status */ - uint32_t SS16:1; /* Channel 16 Service Status */ - uint32_t SS15:1; /* Channel 15 Service Status */ - uint32_t SS14:1; /* Channel 14 Service Status */ - uint32_t SS13:1; /* Channel 13 Service Status */ - uint32_t SS12:1; /* Channel 12 Service Status */ - uint32_t SS11:1; /* Channel 11 Service Status */ - uint32_t SS10:1; /* Channel 10 Service Status */ - uint32_t SS9:1; /* Channel 9 Service Status */ - uint32_t SS8:1; /* Channel 8 Service Status */ - uint32_t SS7:1; /* Channel 7 Service Status */ - uint32_t SS6:1; /* Channel 6 Service Status */ - uint32_t SS5:1; /* Channel 5 Service Status */ - uint32_t SS4:1; /* Channel 4 Service Status */ - uint32_t SS3:1; /* Channel 3 Service Status */ - uint32_t SS2:1; /* Channel 2 Service Status */ - uint32_t SS1:1; /* Channel 1 Service Status */ - uint32_t SS0:1; /* Channel 0 Service Status */ - } B; - } CSSR_B; - - uint32_t eTPU_reserved0298[2]; /* 0x0298-0x029F */ - - uint32_t eTPU_reserved02A0[88]; /* 0x02A0-0x03FF */ - -/*****************************Channels********************************/ - - struct { - union { /* Channel Configuration Register */ - uint32_t R; - struct { - uint32_t CIE:1; /* Channel Interruput Enable */ - uint32_t DTRE:1; /* Data Transfer Request Enable */ - uint32_t CPR:2; /* Channel Priority */ - uint32_t:2; - uint32_t ETPD:1; - uint32_t ETCS:1; /* Entry Table Condition Select */ - uint32_t:3; - uint32_t CFS:5; /* Channel Function Select */ - uint32_t ODIS:1; /* Output disable */ - uint32_t OPOL:1; /* output polarity */ - uint32_t:3; - uint32_t CPBA:11; /* Channel Parameter Base Address */ - } B; - } CR; - - union { /* Channel Status Control Register */ - uint32_t R; - struct { - uint32_t CIS:1; /* Channel Interruput Status */ - uint32_t CIOS:1; /* Channel Interruput Overflow Status */ - uint32_t:6; - uint32_t DTRS:1; /* Data Transfer Status */ - uint32_t DTROS:1; /* Data Transfer Overflow Status */ - uint32_t:6; - uint32_t IPS:1; /* Input Pin State */ - uint32_t OPS:1; /* Output Pin State */ - uint32_t OBE:1; /* Output Buffer Enable */ - uint32_t:11; - uint32_t FM1:1; /* Function mode */ - uint32_t FM0:1; /* Function mode */ - } B; - } SCR; - - union { /* Channel Host Service Request Register */ - uint32_t R; - struct { - uint32_t:29; /* Host Service Request */ - uint32_t HSR:3; - } B; - } HSRR; - - uint32_t eTPU_ch_reserved00C; /* channel offset 0x00C-0x00F */ - - } CHAN[127]; - - uint32_t eTPU_reserved1000[7168]; /* 0x1000-0x7FFF */ - - }; - -/****************************************************************************/ -/* MODULE : PIT / RTI */ -/****************************************************************************/ - - struct PIT_tag { - union { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t:29; - uint32_t MDIS_RTI:1; - uint32_t MDIS:1; - uint32_t FRZ:1; - } B; - } MCR; - - uint32_t PIT_reserved0004[59]; /* 0x0004-0x00EF */ - - struct { - union { - uint32_t R; /* <URM>TSVn</URM> */ - } LDVAL; /* Timer Load Value Register */ - - union { - uint32_t R; /* <URM>TVLn</URM> */ - } CVAL; /* Current Timer Value Register */ - - union { - uint32_t R; - struct { - uint32_t:30; - uint32_t TIE:1; - uint32_t TEN:1; - } B; - } TCTRL; /* Timer Control Register */ - - union { - uint32_t R; - struct { - uint32_t:31; - uint32_t TIF:1; - } B; - } TFLG; /* Timer Flag Register */ - } RTI; /* RTI Channel */ - - struct { - union { - uint32_t R; - struct { - uint32_t TSV:32; - } B; - } LDVAL; - - union { - uint32_t R; - struct { - uint32_t TVL:32; - } B; - } CVAL; - - union { - uint32_t R; - struct { - uint32_t:30; - uint32_t TIE:1; - uint32_t TEN:1; - } B; - } TCTRL; - - union { - uint32_t R; - struct { - uint32_t:31; - uint32_t TIF:1; - } B; - } TFLG; - } CH[4]; - - uint32_t PIT_reserved00140[4016]; /* 0x0140-0x3FFF */ - }; - -/****************************************************************************/ -/* MODULE : XBAR CrossBar */ -/****************************************************************************/ - - struct XBAR_tag { - - union { /* Master Priority Register for Slave Port 0 */ - uint32_t R; - struct { - uint32_t:1; - uint32_t MSTR7:3; /* EBI (development bus) */ - uint32_t:1; - uint32_t MSTR6:3; /* FlexRay */ - uint32_t:1; - uint32_t MSTR5:3; /* eDMA_B */ - uint32_t:1; - uint32_t MSTR4:3; /* eDMA_A */ - uint32_t:1; - uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ - uint32_t:1; - uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ - uint32_t:1; - uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ - uint32_t:1; - uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ - } B; - } MPR0; - - uint32_t XBAR_reserved0004[3]; /* 0x0004-0x000F */ - - union { /* General Purpose Control Register for Slave Port 0 */ - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR0; - - uint32_t XBAR_reserved0014[59]; /* 0x0014-0x00FF */ - - union { /* Master Priority Register for Slave Port 1 */ - uint32_t R; - struct { - uint32_t:1; - uint32_t MSTR7:3; /* EBI (development bus) */ - uint32_t:1; - uint32_t MSTR6:3; /* FlexRay */ - uint32_t:1; - uint32_t MSTR5:3; /* eDMA_B */ - uint32_t:1; - uint32_t MSTR4:3; /* eDMA_A */ - uint32_t:1; - uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ - uint32_t:1; - uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ - uint32_t:1; - uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ - uint32_t:1; - uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ - } B; - } MPR1; - - uint32_t XBAR_reserved0104[3]; /* 0x0104-0x010F */ - - union { /* General Purpose Control Register for Slave Port 1 */ - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR1; - - uint32_t XBAR_reserved0114[59]; /* 0x0114-0x01FF */ - - union { /* Master Priority Register for Slave Port 2 */ - uint32_t R; - struct { - uint32_t:1; - uint32_t MSTR7:3; /* EBI (development bus) */ - uint32_t:1; - uint32_t MSTR6:3; /* FlexRay */ - uint32_t:1; - uint32_t MSTR5:3; /* eDMA_B */ - uint32_t:1; - uint32_t MSTR4:3; /* eDMA_A */ - uint32_t:1; - uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ - uint32_t:1; - uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ - uint32_t:1; - uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ - uint32_t:1; - uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ - } B; - } MPR2; - - uint32_t XBAR_reserved0204[3]; /* 0x0204-0x020F */ - - union { /* General Purpose Control Register for Slave Port 2 */ - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR2; - - uint32_t XBAR_reserved0214[59]; /* 0x0214-0x02FF */ - - uint32_t XBAR_reserved0300[64]; /* 0x0300-0x03FF */ - - uint32_t XBAR_reserved0400[64]; /* 0x0400-0x04FF */ - - uint32_t XBAR_reserved0500[64]; /* 0x0500-0x05FF */ - - union { /* Master Priority Register for Slave Port 6 */ - uint32_t R; - struct { - uint32_t:1; - uint32_t MSTR7:3; /* EBI (development bus) */ - uint32_t:1; - uint32_t MSTR6:3; /* FlexRay */ - uint32_t:1; - uint32_t MSTR5:3; /* eDMA_B */ - uint32_t:1; - uint32_t MSTR4:3; /* eDMA_A */ - uint32_t:1; - uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ - uint32_t:1; - uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ - uint32_t:1; - uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ - uint32_t:1; - uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ - } B; - } MPR6; - - uint32_t XBAR_reserved604[3]; /* 0x0604-0x060F */ - - union { /* General Purpose Control Register for Slave Port 6 */ - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR6; - - uint32_t XBAR_reserved0614[59]; /* 0x0614-0x06FF */ - - union { /* Master Priority Register for Slave Port 7 */ - uint32_t R; - struct { - uint32_t:1; - uint32_t MSTR7:3; /* EBI (development bus) */ - uint32_t:1; - uint32_t MSTR6:3; /* FlexRay */ - uint32_t:1; - uint32_t MSTR5:3; /* eDMA_B */ - uint32_t:1; - uint32_t MSTR4:3; /* eDMA_A */ - uint32_t:1; - uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ - uint32_t:1; - uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ - uint32_t:1; - uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ - uint32_t:1; - uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ - } B; - } MPR7; - - uint32_t XBAR_reserved704[3]; /* 0x0704-0x070F */ - - union { - uint32_t R; - struct { - uint32_t RO:1; - uint32_t:21; - uint32_t ARB:2; - uint32_t:2; - uint32_t PCTL:2; - uint32_t:1; - uint32_t PARK:3; - } B; - } SGPCR7; /* General Purpose Control Register for Slave Port 7 */ - - uint32_t XBAR_reserved0714[59]; /* 0x0714-0x07FF */ - - uint32_t XBAR_reserved0800[3584]; /* 0x0800-0x3FFF */ - }; - -/****************************************************************************/ -/* MODULE : MPU */ -/****************************************************************************/ - - struct MPU_tag { - - union { /* Module Control/Error Status Register */ - uint32_t R; - struct { - uint32_t SPERR:8; - uint32_t:4; - uint32_t HRL:4; - uint32_t NSP:4; - uint32_t NRGD:4; - uint32_t:7; - uint32_t VLD:1; - } B; - } CESR; - - uint32_t MPU_reserved0004[3]; /* 0x0004-0x000F */ - - struct { - union { /* MPU Error Address Registers */ - uint32_t R; - struct { - uint32_t EADDR:32; - } B; - } EAR; - - union { /* MPU Error Detail Registers */ - uint32_t R; - struct { - uint32_t EACD:16; - uint32_t EPID:8; - uint32_t EMN:4; - uint32_t EATTR:3; - uint32_t ERW:1; - } B; - } EDR; - } PORT[3]; - - uint32_t MPU_reserved0028[246]; /* 0x0028-0x03FF */ - - struct { - union { /* Region Descriptor n Word 0 */ - uint32_t R; - struct { - uint32_t SRTADDR:27; - uint32_t:5; - } B; - } WORD0; - - union { /* Region Descriptor n Word 1 */ - uint32_t R; - struct { - uint32_t ENDADDR:27; - uint32_t:5; - } B; - } WORD1; - - union { /* Region Descriptor n Word 2 */ - uint32_t R; - struct { - uint32_t M7RE:1; - uint32_t M7WE:1; - uint32_t M6RE:1; - uint32_t M6WE:1; - uint32_t M5RE:1; - uint32_t M5WE:1; - uint32_t M4RE:1; - uint32_t M4WE:1; - uint32_t: 18; - uint32_t M0PE:1; - uint32_t M0SM:2; - uint32_t M0UM:3; - } B; - } WORD2; - - union { /* Region Descriptor n Word 3 */ - uint32_t R; - struct { - uint32_t PID:8; - uint32_t PIDMASK:8; - uint32_t:15; - uint32_t VLD:1; - } B; - } WORD3; - } RGD[16]; - - uint32_t MPU_reserved0500[192]; /* 0x0500-0x07FF */ - - union { /* Region Descriptor Alternate Access Control n */ - uint32_t R; - struct { - uint32_t:6; - uint32_t M4RE:1; - uint32_t M4WE:1; - uint32_t M3PE:1; - uint32_t M3SM:2; - uint32_t M3UM:3; - uint32_t M2PE:1; - uint32_t M2SM:2; - uint32_t M2UM:3; - uint32_t M1PE:1; - uint32_t M1SM:2; - uint32_t M1UM:3; - uint32_t M0PE:1; - uint32_t M0SM:2; - uint32_t M0UM:3; - } B; - } RGDAAC[16]; - - uint32_t MPU_reserved0840[3568]; /* 0x0840-0x3FFF */ - - }; - -/****************************************************************************/ -/* MODULE : SWT */ -/****************************************************************************/ - - struct SWT_tag { - - union { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t MAP0:1; - uint32_t MAP1:1; - uint32_t:1; - uint32_t:1; - uint32_t MAP4:1; - uint32_t MAP5:1; - uint32_t MAP6:1; - uint32_t MAP7:1; - uint32_t:14; - uint32_t KEY:1; - uint32_t RIA:1; - uint32_t WND:1; - uint32_t ITR:1; - uint32_t HLK:1; - uint32_t SLK:1; - uint32_t CSL:1; - uint32_t STP:1; - uint32_t FRZ:1; - uint32_t WEN:1; - } B; - } MCR; - - union { /* Interrupt register */ - uint32_t R; - struct { - uint32_t :31; - uint32_t TIF:1; - } B; - } IR; - - union { /* Timeout register */ - uint32_t R; - struct { - uint32_t WTO:32; - } B; - } TO; - - union { /* Window register */ - uint32_t R; - struct { - uint32_t WST:32; - } B; - } WN; - - union { /* Service register */ - uint32_t R; - struct { - uint32_t :16; - uint32_t WSC:16; - } B; - } SR; - - union { /* Counter output register */ - uint32_t R; - struct { - uint32_t CNT:32; - } B; - } CO; - - union { /* Service key register */ - uint32_t R; - struct { - uint32_t :16; - uint32_t SK:16; - } B; - } SK; - - uint32_t SWT_reserved001C[4089]; /* 0x001C-0x3FFF */ - - }; - -/****************************************************************************/ -/* MODULE : STM */ -/****************************************************************************/ - - struct STM_tag { - - union { /* Control Register */ - uint32_t R; - struct { - uint32_t :16; - uint32_t CPS:8; - uint32_t :6; - uint32_t FRZ:1; - uint32_t TEN:1; - } B; - } CR; - - union { /* STM Counter */ - uint32_t R; - } CNT; - - uint32_t STM_reserved0008[2]; /* 0x0008-0x000F */ - - /* channel 0 registers */ - union { - uint32_t R; - struct { - uint32_t :31; - uint32_t CEN:1; - } B; - } CCR0; /* Chan 0 Control Register */ - - union { - uint32_t R; - struct { - uint32_t :31; - uint32_t CIF:1; - } B; - } CIR0; /* Chan 0 Interrupt Register */ - - union { - uint32_t R; - } CMP0; /* Chan 0 Compare Register */ - - uint32_t STM_reserved2[1]; - -/* channel 1 registers */ - union { - uint32_t R; - struct { - uint32_t :31; - uint32_t CEN:1; - } B; - } CCR1; /* Chan 1 Control Register */ - - union { - uint32_t R; - struct { - uint32_t :31; - uint32_t CIF:1; - } B; - } CIR1; /* Chan 1 Interrupt Register */ - - union { - uint32_t R; - } CMP1; /* Chan 1 Compare Register */ - - uint32_t STM_reserved3[1]; - -/* channel 2 registers */ - union { - uint32_t R; - struct { - uint32_t :31; - uint32_t CEN:1; - } B; - } CCR2; /* Chan 2 Control Register */ - - union { - uint32_t R; - struct { - uint32_t :31; - uint32_t CIF:1; - } B; - } CIR2; /* Chan 2 Interrupt Register */ - - union { - uint32_t R; - } CMP2; /* Chan 2 Compare Register */ - - uint32_t STM_reserved4[1]; - -/* channel 3 registers */ - union { - uint32_t R; - struct { - uint32_t :31; - uint32_t CEN:1; - } B; - } CCR3; /* Chan 3 Control Register */ - - union { - uint32_t R; - struct { - uint32_t :31; - uint32_t CIF:1; - } B; - } CIR3; /* Chan 3 Interrupt Register */ - - union { - uint32_t R; - } CMP3; /* Chan 3 Compare Register */ - - uint32_t STM_reserved0050[4076]; /* 0x0050-0x3FFF */ - - }; - -/****************************************************************************/ -/* MODULE : ECSM */ -/****************************************************************************/ - - struct ECSM_tag { - - union { /* Processor core type */ - uint16_t R; - } PCT; - - union { /* Platform revision */ - uint16_t R; - } REV; - - uint32_t ECSM_reserved0004; /* 0x0004-0x0007 */ - - union { /* IPS Module Configuration */ - uint32_t R; - } IMC; - - uint8_t ECSM_reserved000C[3]; /* 0x000C-0x000E */ - - union { /* Miscellaneous Reset Status Register */ - uint8_t R; - struct { - uint8_t POR:1; - uint8_t DIR:1; - uint8_t SWTR:1; - uint8_t:5; - } B; - } MRSR; - - uint8_t ECSM_reserved0010[51]; /* 0x0010-0x0042 */ - - union { /* ECC Configuration Register */ - uint8_t R; - struct { - uint8_t:2; - uint8_t ER1BR:1; - uint8_t EF1BR:1; - uint8_t:2; - uint8_t ERNCR:1; - uint8_t EFNCR:1; - } B; - } ECR; - - uint8_t ECSM_reserved0044[3]; /* 0x0044-0x0046 */ - - union { /* ECC Status Register */ - uint8_t R; - struct { - uint8_t:2; - uint8_t R1BC:1; - uint8_t F1BC:1; - uint8_t:2; - uint8_t RNCE:1; - uint8_t FNCE:1; - } B; - } ESR; - - uint16_t ECSM_reserved0048; /* 0x0048-0x0049 */ - - union { /* ECC Error Generation Register */ - uint16_t R; - struct { - uint16_t:2; - uint16_t FRC1BI:1; - uint16_t FR11BI:1; - uint16_t:2; - uint16_t FRCNCI:1; - uint16_t FR1NCI:1; - uint16_t:1; - uint16_t ERRBIT:7; - } B; - } EEGR; - - uint32_t ECSM_reserved004C; /* 0x004C-0x004F */ - - union { /* Flash ECC Address Register */ - uint32_t R; - struct { - uint32_t FEAR:32; - } B; - } FEAR; - - uint16_t ECSM_reserved0054; /* 0x0054-0x0055 */ - - union { /* Flash ECC Master Number Register */ - uint8_t R; - struct { - uint8_t:4; - uint8_t FEMR:4; - } B; - } FEMR; - - union { /* Flash ECC Attributes Register */ - uint8_t R; - struct { - uint8_t WRITE:1; - uint8_t SIZE:3; - uint8_t PROT0:1; - uint8_t PROT1:1; - uint8_t PROT2:1; - uint8_t PROT3:1; - } B; - } FEAT; - - union { /* Flash ECC Data Register High */ - uint32_t R; - struct { - uint32_t FEDH:32; - } B; - } FEDRH; - - union { /* Flash ECC Data Register Low */ - uint32_t R; - struct { - uint32_t FEDL:32; - } B; - } FEDRL; - - union { /* RAM ECC Address Register */ - uint32_t R; - struct { - uint32_t REAR:32; - } B; - } REAR; - - uint16_t ECSM_reserved0064; /* 0x0064-0x0065 */ - - union { /* RAM ECC Master Number Register */ - uint8_t R; - struct { - uint8_t:4; - uint8_t REMR:4; - } B; - } REMR; - - union { /* RAM ECC Attributes Register */ - uint8_t R; - struct { - uint8_t WRITE:1; - uint8_t SIZE:3; - uint8_t PROT0:1; - uint8_t PROT1:1; - uint8_t PROT2:1; - uint8_t PROT3:1; - } B; - } REAT; - - union { /* RAM ECC Data Register */ - uint32_t R; - struct { - uint32_t REDH:32; - } B; - } REDRH; - - union { /* RAM ECC Data Register */ - uint32_t R; - struct { - uint32_t REDL:32; - } B; - } REDRL; - - uint32_t ECSM_reserved0070[4068]; /* 0x0070-0x3FFF */ - - }; - -/****************************************************************************/ -/* MODULE : INTC */ -/****************************************************************************/ - - struct INTC_tag { - - union { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t:26; - uint32_t VTES:1; - uint32_t:4; - uint32_t HVEN:1; - } B; - } MCR; - - uint32_t INTC_reserved0004; /* 0x0004-0x0007 */ - - union { /* Current Priority Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t PRI:4; - } B; - } CPR; - - uint32_t INTC_reserved000C; /* 0x000C-0x000F */ - - union { /* Interrupt Acknowledge Register */ - uint32_t R; - struct { - uint32_t VTBA:21; - uint32_t INTVEC:9; - uint32_t:2; - } B; - } IACKR; - - uint32_t INTC_reserved0014; /* 0x0014-0x0017 */ - - union { /* End of Interrupt Register */ - uint32_t R; - struct { - uint32_t EOIR:32; - } B; - } EOIR; - - uint32_t INTC_reserved001C; /* 0x001C-0x001F */ - - union { /* Software Set/Clear Interruput Register */ - uint8_t R; - struct { - uint8_t:6; - uint8_t SET:1; - uint8_t CLR:1; - } B; - } SSCIR[8]; - - uint32_t INTC_reserved0028[6]; /* 0x0028-0x003F */ - - union { /* Software Set/Clear Interrupt Register */ - uint8_t R; - struct { - uint8_t:4; - uint8_t PRI:4; - } B; - } PSR[480]; - - uint16_t INTC_reserved0220[7920]; /* 0x0220-0x3FFF */ - - }; - -/****************************************************************************/ -/* MODULE : EQADC */ -/****************************************************************************/ - - struct EQADC_tag { - - union EQADC_MCR_tag { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t:24; - uint32_t ICEA0:1; - uint32_t ICEA1:1; - uint32_t:1; - uint32_t ESSIE:2; - uint32_t:1; - uint32_t DBG:2; - } B; - } MCR; - - uint32_t eQADC_reserved0004; /* 0x0004-0x0007 */ - - union EQADC_NMSFR_tag { /* Null Message Send Format Register */ - uint32_t R; - struct { - uint32_t:6; - uint32_t NMF:26; - } B; - } NMSFR; - - union EQADC_ETDFR_tag { /* External Trigger Digital Filter Register */ - uint32_t R; - struct { - uint32_t:28; - uint32_t DFL:4; - } B; - } ETDFR; - - union EQADC_CFPR_tag { /* CFIFO Push Registers */ - uint32_t R; - struct { - uint32_t CFPUSH:32; - } B; - } CFPR[6]; - - uint32_t eQADC_reserved0028[2]; /* 0x0028-0x002F */ - - union EQADC_RFPR_tag { /* Result FIFO Pop Registers */ - uint32_t R; - struct { - uint32_t:16; - uint32_t RFPOP:16; - } B; - } RFPR[6]; - - uint32_t eQADC_reserved0048[2]; /* 0x0048-0x004F */ - - union EQADC_CFCR_tag { /* CFIFO Control Registers */ - uint16_t R; - struct { - uint16_t:3; - uint16_t CFEEE0:1; - uint16_t STRME0:1; - uint16_t SSE:1; - uint16_t CFINV:1; - uint16_t:1; - uint16_t MODE:4; - uint16_t AMODE0:4; - } B; - } CFCR[6]; - - uint32_t eQADC_reserved005C; /* 0x005C-0x005F */ - - union EQADC_IDCR_tag { /* Interrupt and DMA Control Registers */ - uint16_t R; - struct { - uint16_t NCIE:1; - uint16_t TORIE:1; - uint16_t PIE:1; - uint16_t EOQIE:1; - uint16_t CFUIE:1; - uint16_t:1; - uint16_t CFFE:1; - uint16_t CFFS:1; - uint16_t:4; - uint16_t RFOIE:1; - uint16_t:1; - uint16_t RFDE:1; - uint16_t RFDS:1; - } B; - } IDCR[6]; - - uint32_t eQADC_reserved006C; /* 0x006C-0x006F */ - - union { /* FIFO and Interrupt Status Registers */ - uint32_t R; - struct { - uint32_t NCF:1; - uint32_t TORF:1; - uint32_t PF:1; - uint32_t EOQF:1; - uint32_t CFUF:1; - uint32_t SSS:1; - uint32_t CFFF:1; - uint32_t:5; - uint32_t RFOF:1; - uint32_t:1; - uint32_t RFDF:1; - uint32_t:1; - uint32_t CFCTR:4; - uint32_t TNXTPTR:4; - uint32_t RFCTR:4; - uint32_t POPNXTPTR:4; - } B; - } FISR[6]; - - uint32_t eQADC_reserved0088[2]; /* 0x0088-0x008F */ - - union { /* CFIFO Transfer Counter Registers */ - uint16_t R; - struct { - uint16_t:5; - uint16_t TCCF:11; /* Legacy naming - refer to TC_CF in Reference Manual */ - } B; - } CFTCR[6]; - - uint32_t eQADC_reserved009C[1]; /* 0x009F */ - - union { /* CFIFO Status Register 0 */ - uint32_t R; - struct { - uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB0 in Reference Manual */ - uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB0 in Reference Manual */ - uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB0 in Reference Manual */ - uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB0 in Reference Manual */ - uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB0 in Reference Manual */ - uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB0 in Reference Manual */ - uint32_t:5; - uint32_t LCFTCB0:4; - uint32_t TC_LCFTCB0:11; - } B; - } CFSSR0; - - union { /* CFIFO Status Register 1 */ - uint32_t R; - struct { - uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB1 in Reference Manual */ - uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB1 in Reference Manual */ - uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB1 in Reference Manual */ - uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB1 in Reference Manual */ - uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB1 in Reference Manual */ - uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB1 in Reference Manual */ - uint32_t:5; - uint32_t LCFTCB1:4; - uint32_t TC_LCFTCB1:11; - } B; - } CFSSR1; - - union { /* CFIFO Status Register 2 */ - uint32_t R; - struct { - uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TSSI in Reference Manual */ - uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TSSI in Reference Manual */ - uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TSSI in Reference Manual */ - uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TSSI in Reference Manual */ - uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TSSI in Reference Manual */ - uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TSSI in Reference Manual */ - uint32_t:4; - uint32_t ECBNI:1; - uint32_t LCFTSSI:4; - uint32_t TC_LCFTSSI:11; - } B; - } CFSSR2; - - union { /* CFIFO Status Register */ - uint32_t R; - struct { - uint32_t CFS0:2; - uint32_t CFS1:2; - uint32_t CFS2:2; - uint32_t CFS3:2; - uint32_t CFS4:2; - uint32_t CFS5:2; - uint32_t:20; - } B; - } CFSR; - - uint32_t eQADC_reserved00B0; /* 0x00B0-0x00B3 */ - - union EQADC_SSICR_tag { /* SSI Control Register */ - uint32_t R; - struct { - uint32_t:21; - uint32_t MDT:3; - uint32_t:4; - uint32_t BR:4; - } B; - } SSICR; - - union { /* SSI Recieve Data Register */ - uint32_t R; - struct { - uint32_t RDV:1; - uint32_t:5; - uint32_t RDATA:26; - } B; - } SSIRDR; - - uint32_t eQADC_reserved00BC[17]; /* 0x00BC-0x00FF */ - - struct { - union { - uint32_t R; - struct { - uint32_t CFIFO_DATA:32; - } B; - } R[4]; - - uint32_t eQADC_cf_reserved010[12]; /* CFIFO offset 0x010-0x03F */ - - } CF[6]; - - uint32_t eQADC_reserved0280[32]; /* 0x0280-0x02FF */ - - struct { - union { - uint32_t R; - struct { - uint32_t RFIFO_DATA:32; - } B; - } R[4]; - - uint32_t eQADC_rf_reserved010[12]; /* RFIFO offset 0x010-0x03F */ - - } RF[6]; - - uint32_t eQADC_reserved0480[3808]; /* 0x0480-0x3FFF */ - }; - -/****************************************************************************/ -/* MODULE : Decimation Filter */ -/****************************************************************************/ - - struct DECFIL_tag { - - union { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t MDIS:1; - uint32_t FREN:1; - uint32_t :1; - uint32_t FRZ:1; - uint32_t SRES:1; - uint32_t CASCD:2; - uint32_t IDEN:1; - uint32_t ODEN:1; - uint32_t ERREN:1; - uint32_t :1; - uint32_t FTYPE:2; - uint32_t :1; - uint32_t SCAL:2; - uint32_t :1; - uint32_t SAT:1; - uint32_t ISEL:1; - uint32_t :1; - uint32_t DEC_RATE:4; - uint32_t :1; - uint32_t DSEL:1; - uint32_t IBIE:1; - uint32_t OBIE:1; - uint32_t EDME:1; - uint32_t TORE:1; - uint32_t TRFE:1; - uint32_t :1; - } B; - } MCR; - - union { /* Module Status Register */ - uint32_t R; - struct { - uint32_t BSY:1; - uint32_t:1; - uint32_t DEC_COUNTER:4; - uint32_t IDFC:1; - uint32_t ODFC:1; - uint32_t:1; - uint32_t IBIC:1; - uint32_t OBIC:1; - uint32_t:1; - uint32_t DIVRC:1; - uint32_t OVFC:1; - uint32_t OVRC:1; - uint32_t IVRC:1; - uint32_t:6; - uint32_t IDF:1; - uint32_t ODF:1; - uint32_t:1; - uint32_t IBIF:1; - uint32_t OBIF:1; - uint32_t:1; - uint32_t DIVR:1; - uint32_t OVF:1; - uint32_t OVR:1; - uint32_t IVR:1; - } B; - } SR; - - union { /* Module Extended Config Register */ - uint32_t R; - struct { - uint32_t SDMAE:1; - uint32_t SSIG:1; - uint32_t SSAT:1; - uint32_t SCSAT:1; - uint32_t:10; - uint32_t SRQ:1; - uint32_t SZR0:1; - uint32_t:1; - uint32_t SISEL:1; - uint32_t SZROSEL:2; - uint32_t:2; - uint32_t SHLTSEL:2; - uint32_t:1; - uint32_t SRQSEL:3; - uint32_t:2; - uint32_t SENSEL:2; - } B; - } MXCR; - - union { /* Module Extended Status Register */ - uint32_t R; - struct { - uint32_t:7; - uint32_t SDFC:1; - uint32_t:2; - uint32_t SSEC:1; - uint32_t SCEC:1; - uint32_t:1; - uint32_t SSOVFC:1; - uint32_t SCOVFC:1; - uint32_t SVRC:1; - uint32_t:7; - uint32_t SDF:1; - uint32_t:2; - uint32_t SSE:1; - uint32_t SCE:1; - uint32_t:1; - uint32_t SSOVF:1; - uint32_t SCOVF:1; - uint32_t SVR:1; - } B; - } MXSR; - - union { /* Interface Input Buffer Register */ - uint32_t R; - struct { - uint32_t:14; - uint32_t PREFILL:1; - uint32_t FLUSH:1; - uint32_t INPBUF:16; - } B; - } IB; - - union { /* Interface Output Buffer Register */ - uint32_t R; - struct { - uint32_t:9; - uint32_t TSI:1; - uint32_t:2; - uint32_t OUTTAG:4; - uint32_t OUTBUF:16; - } B; - } OB; - - uint32_t DFILT_reserved0018[2]; /* 0x0018-0x001F */ - - union { /* Coefficient n Register */ - int32_t R; - struct { - int32_t:8; - int32_t COEF:24; - } B; - } COEF[9]; - - uint32_t DFILT_reserved0044[13]; /* 0x0044-0x0077 */ - - union { /* TAP n Register */ - int32_t R; - struct { - int32_t:8; - int32_t TAP:24; - } B; - } TAP[8]; - - uint32_t DFILT_reserved0098[14]; /* 0x0098-0x00CF */ - - union { /* EDID Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t SAMP_DATA:16; - } B; - } EDID; - - uint32_t DFILT_reserved00D4[459]; /* 0x00D4-0x07FF */ - - }; - -/****************************************************************************/ -/* MODULE : DSPI */ -/****************************************************************************/ - - struct DSPI_tag { - - union DSPI_MCR_tag { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t MSTR:1; - uint32_t CONT_SCKE:1; - uint32_t DCONF:2; - uint32_t FRZ:1; - uint32_t MTFE:1; - uint32_t PCSSE:1; - uint32_t ROOE:1; - uint32_t PCSIS7:1; - uint32_t PCSIS6:1; - uint32_t PCSIS5:1; - uint32_t PCSIS4:1; - uint32_t PCSIS3:1; - uint32_t PCSIS2:1; - uint32_t PCSIS1:1; - uint32_t PCSIS0:1; - uint32_t DOZE:1; - uint32_t MDIS:1; - uint32_t DIS_TXF:1; - uint32_t DIS_RXF:1; - uint32_t CLR_TXF:1; - uint32_t CLR_RXF:1; - uint32_t SMPL_PT:2; - uint32_t:7; - uint32_t HALT:1; - } B; - } MCR; - - uint32_t DSPI_reserved0004; /* 0x0004-0x0007 */ - - union { /* Transfer Count Register */ - uint32_t R; - struct { - uint32_t TCNT:16; - uint32_t:16; - } B; - } TCR; - - union DSPI_CTAR_tag {/* Clock and Transfer Attributes Registers */ - uint32_t R; - struct { - uint32_t DBR:1; - uint32_t FMSZ:4; - uint32_t CPOL:1; - uint32_t CPHA:1; - uint32_t LSBFE:1; - uint32_t PCSSCK:2; - uint32_t PASC:2; - uint32_t PDT:2; - uint32_t PBR:2; - uint32_t CSSCK:4; - uint32_t ASC:4; - uint32_t DT:4; - uint32_t BR:4; - } B; - } CTAR[8]; - - union DSPI_SR_tag { /* Status Register */ - uint32_t R; - struct { - uint32_t TCF:1; - uint32_t TXRXS:1; - uint32_t:1; - uint32_t EOQF:1; - uint32_t TFUF:1; - uint32_t:1; - uint32_t TFFF:1; - uint32_t:5; - uint32_t RFOF:1; - uint32_t:1; - uint32_t RFDF:1; - uint32_t:1; - uint32_t TXCTR:4; - uint32_t TXNXTPTR:4; - uint32_t RXCTR:4; - uint32_t POPNXTPTR:4; - } B; - } SR; - - union DSPI_RSER_tag { /* DMA/Interrupt Request Select and Enable Register */ - uint32_t R; - struct { - uint32_t TCFRE:1; - uint32_t:2; - uint32_t EOQFRE:1; - uint32_t TFUFRE:1; - uint32_t:1; - uint32_t TFFFRE:1; - uint32_t TFFFDIRS:1; - uint32_t:4; - uint32_t RFOFRE:1; - uint32_t:1; - uint32_t RFDFRE:1; - uint32_t RFDFDIRS:1; - uint32_t:16; - } B; - } RSER; - - union DSPI_PUSHR_tag { /* PUSH TX FIFO Register */ - uint32_t R; - struct { - uint32_t CONT:1; - uint32_t CTAS:3; - uint32_t EOQ:1; - uint32_t CTCNT:1; - uint32_t:2; - uint32_t PCS7:1; - uint32_t PCS6:1; - uint32_t PCS5:1; - uint32_t PCS4:1; - uint32_t PCS3:1; - uint32_t PCS2:1; - uint32_t PCS1:1; - uint32_t PCS0:1; - uint32_t TXDATA:16; - } B; - } PUSHR; - - union DSPI_POPR_tag { /* POP RX FIFO Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t RXDATA:16; - } B; - } POPR; - - union { /* Transmit FIFO Registers */ - uint32_t R; - struct { - uint32_t TXCMD:16; - uint32_t TXDATA:16; - } B; - } TXFR[4]; - - uint32_t DSPI_reserved004C[12]; /* 0x004C-0x007B */ - - union { /* Transmit FIFO Registers */ - uint32_t R; - struct { - uint32_t:16; - uint32_t RXDATA:16; - } B; - } RXFR[4]; - - uint32_t DSPI_reserved008C[12]; /* 0x008C-0x00BB */ - - union { /* DSI Configuration Register */ - uint32_t R; - struct { - uint32_t MTOE:1; - uint32_t:1; - uint32_t MTOCNT:6; - uint32_t:3; - uint32_t TSBC:1; - uint32_t TXSS:1; - uint32_t TPOL:1; - uint32_t TRRE:1; - uint32_t CID:1; - uint32_t DCONT:1; - uint32_t DSICTAS:3; - uint32_t:4; - uint32_t DPCS7:1; - uint32_t DPCS6:1; - uint32_t DPCS5:1; - uint32_t DPCS4:1; - uint32_t DPCS3:1; - uint32_t DPCS2:1; - uint32_t DPCS1:1; - uint32_t DPCS0:1; - } B; - } DSICR; - - union { /* DSI Serialization Data Register */ - uint32_t R; - struct { - uint32_t SER_DATA:32; - } B; - } SDR; - - union { /* DSI Alternate Serialization Data Register */ - uint32_t R; - struct { - uint32_t ASER_DATA:32; - } B; - } ASDR; - - union { /* DSI Transmit Comparison Register */ - uint32_t R; - struct { - uint32_t COMP_DATA:32; - } B; - } COMPR; - - union { /* DSI deserialization Data Register */ - uint32_t R; - struct { - uint32_t DESER_DATA:32; - } B; - } DDR; - - union { - uint32_t R; - struct { - uint32_t:3; - uint32_t TSBCNT:5; - uint32_t:16; - uint32_t DPCS1_7:1; - uint32_t DPCS1_6:1; - uint32_t DPCS1_5:1; - uint32_t DPCS1_4:1; - uint32_t DPCS1_3:1; - uint32_t DPCS1_2:1; - uint32_t DPCS1_1:1; - uint32_t DPCS1_0:1; - } B; - } DSICR1; - uint32_t DSPI_reserved00D4[4043]; /* 0x00D4-0x3FFF */ - - }; - -/****************************************************************************/ -/* MODULE : eSCI */ -/****************************************************************************/ - - struct ESCI_tag { - union ESCI_CR1_tag { /* Control Register 1 */ - uint32_t R; - struct { - uint32_t:3; - uint32_t SBR:13; - uint32_t LOOPS:1; - uint32_t:1; - uint32_t RSRC:1; - uint32_t M:1; - uint32_t WAKE:1; - uint32_t ILT:1; - uint32_t PE:1; - uint32_t PT:1; - uint32_t TIE:1; - uint32_t TCIE:1; - uint32_t RIE:1; - uint32_t ILIE:1; - uint32_t TE:1; - uint32_t RE:1; - uint32_t RWU:1; - uint32_t SBK:1; - } B; - } CR1; - - union ESCI_CR2_tag { /* Control Register 2 */ - uint16_t R; - struct { - uint16_t MDIS:1; - uint16_t FBR:1; - uint16_t BSTP:1; - uint16_t IEBERR:1; - uint16_t RXDMA:1; - uint16_t TXDMA:1; - uint16_t BRK13:1; - uint16_t TXDIR:1; - uint16_t BESM13:1; - uint16_t SBSTP:1; - uint16_t RXPOL:1; - uint16_t PMSK:1; - uint16_t ORIE:1; - uint16_t NFIE:1; - uint16_t FEIE:1; - uint16_t PFIE:1; - } B; - } CR2; - - union ESCI_DR_tag { /* Data Register */ - uint16_t R; - - struct { - uint16_t RN:1; - uint16_t TN:1; - uint16_t ERR:1; - uint16_t:1; - uint16_t RD_11:4; - uint16_t D:8; - } B; - } DR; /* Legacy naming - refer to SDR in Reference Manual */ - - union ESCI_SR_tag { /* Status Register */ - uint32_t R; - struct { - uint32_t TDRE:1; - uint32_t TC:1; - uint32_t RDRF:1; - uint32_t IDLE:1; - uint32_t OR:1; - uint32_t NF:1; - uint32_t FE:1; - uint32_t PF:1; - uint32_t:3; - uint32_t BERR:1; - uint32_t:2; - uint32_t TACT:1; - uint32_t RAF:1; - uint32_t RXRDY:1; - uint32_t TXRDY:1; - uint32_t LWAKE:1; - uint32_t STO:1; - uint32_t PBERR:1; - uint32_t CERR:1; - uint32_t CKERR:1; - uint32_t FRC:1; - uint32_t:6; - uint32_t UREQ:1; - uint32_t OVFL:1; - } B; - } SR; - - union { /* LIN Control Register */ - uint32_t R; - struct { - uint32_t LRES:1; - uint32_t WU:1; - uint32_t WUD0:1; - uint32_t WUD1:1; - uint32_t :2; - uint32_t PRTY:1; - uint32_t LIN:1; - uint32_t RXIE:1; - uint32_t TXIE:1; - uint32_t WUIE:1; - uint32_t STIE:1; - uint32_t PBIE:1; - uint32_t CIE:1; - uint32_t CKIE:1; - uint32_t FCIE:1; - uint32_t:6; - uint32_t UQIE:1; - uint32_t OFIE:1; - uint32_t:8; - } B; - } LCR; - - union { /* LIN Transmit Register */ - uint8_t R; - } LTR; - - uint8_t eSCI_reserved0011[3]; /* 0x0011-0x0013 */ - - union { /* LIN Recieve Register */ - uint8_t R; - struct { - uint8_t D:8; - } B; - } LRR; - - uint8_t eSCI_reserved0015[3]; /* 0x0015-0x0017 */ - - union { /* LIN CRC Polynom Register */ - uint16_t R; - struct { - uint16_t P:16; - } B; - } LPR; - - union { /* Control Register 3 */ - uint16_t R; - struct { - uint16_t:3; - uint16_t SYNM:1; - uint16_t EROE:1; - uint16_t ERFE:1; - uint16_t ERPE:1; - uint16_t M2:1; - uint16_t:8; - } B; - } CR3; - - uint32_t eSCI_reserved001C; /* 0x001C-0x001F */ - - uint32_t eSCI_reserved0020[4088]; /* 0x0020-0x3FFF */ - - }; - -/****************************************************************************/ -/* MODULE : FlexCAN */ -/****************************************************************************/ - - struct FLEXCAN2_tag { - union { /* Module Configuration Register */ - uint32_t R; - struct { - uint32_t MDIS:1; - uint32_t FRZ:1; - uint32_t FEN:1; - uint32_t HALT:1; - uint32_t NOTRDY:1; - uint32_t WAK_MSK:1; - uint32_t SOFTRST:1; - uint32_t FRZACK:1; - uint32_t SUPV:1; - uint32_t SLF_WAK:1; - uint32_t WRNEN:1; - uint32_t MDISACK:1; - uint32_t WAK_SRC:1; - uint32_t DOZE:1; - uint32_t SRXDIS:1; - uint32_t BCC:1; - uint32_t:2; - uint32_t LPRIO_EN:1; - uint32_t AEN:1; - uint32_t:2; - uint32_t IDAM:2; - uint32_t:2; - uint32_t MAXMB:6; - } B; - } MCR; - - union { /* Control Register */ - uint32_t R; - struct { - uint32_t PRESDIV:8; - uint32_t RJW:2; - uint32_t PSEG1:3; - uint32_t PSEG2:3; - uint32_t BOFFMSK:1; - uint32_t ERRMSK:1; - uint32_t CLKSRC:1; - uint32_t LPB:1; - uint32_t TWRNMSK:1; - uint32_t RWRNMSK:1; - uint32_t:2; - uint32_t SMP:1; - uint32_t BOFFREC:1; - uint32_t TSYN:1; - uint32_t LBUF:1; - uint32_t LOM:1; - uint32_t PROPSEG:3; - } B; - } CR; /* Legacy naming - refer to CTRL in Reference Manual */ - - union { /* Free Running Timer */ - uint32_t R; - } TIMER; - - int32_t FLEXCAN_reserved000C; /* 0x000C-0x000F */ - - union { /* RX Global Mask */ - uint32_t R; - struct { - uint32_t MI31:1; - uint32_t MI30:1; - uint32_t MI29:1; - uint32_t MI28:1; - uint32_t MI27:1; - uint32_t MI26:1; - uint32_t MI25:1; - uint32_t MI24:1; - uint32_t MI23:1; - uint32_t MI22:1; - uint32_t MI21:1; - uint32_t MI20:1; - uint32_t MI19:1; - uint32_t MI18:1; - uint32_t MI17:1; - uint32_t MI16:1; - uint32_t MI15:1; - uint32_t MI14:1; - uint32_t MI13:1; - uint32_t MI12:1; - uint32_t MI11:1; - uint32_t MI10:1; - uint32_t MI9:1; - uint32_t MI8:1; - uint32_t MI7:1; - uint32_t MI6:1; - uint32_t MI5:1; - uint32_t MI4:1; - uint32_t MI3:1; - uint32_t MI2:1; - uint32_t MI1:1; - uint32_t MI0:1; - } B; - } RXGMASK; - - union { /* RX 14 Mask */ - uint32_t R; - struct { - uint32_t MI31:1; - uint32_t MI30:1; - uint32_t MI29:1; - uint32_t MI28:1; - uint32_t MI27:1; - uint32_t MI26:1; - uint32_t MI25:1; - uint32_t MI24:1; - uint32_t MI23:1; - uint32_t MI22:1; - uint32_t MI21:1; - uint32_t MI20:1; - uint32_t MI19:1; - uint32_t MI18:1; - uint32_t MI17:1; - uint32_t MI16:1; - uint32_t MI15:1; - uint32_t MI14:1; - uint32_t MI13:1; - uint32_t MI12:1; - uint32_t MI11:1; - uint32_t MI10:1; - uint32_t MI9:1; - uint32_t MI8:1; - uint32_t MI7:1; - uint32_t MI6:1; - uint32_t MI5:1; - uint32_t MI4:1; - uint32_t MI3:1; - uint32_t MI2:1; - uint32_t MI1:1; - uint32_t MI0:1; - } B; - } RX14MASK; - - union { /* RX 15 Mask */ - uint32_t R; - struct { - uint32_t MI31:1; - uint32_t MI30:1; - uint32_t MI29:1; - uint32_t MI28:1; - uint32_t MI27:1; - uint32_t MI26:1; - uint32_t MI25:1; - uint32_t MI24:1; - uint32_t MI23:1; - uint32_t MI22:1; - uint32_t MI21:1; - uint32_t MI20:1; - uint32_t MI19:1; - uint32_t MI18:1; - uint32_t MI17:1; - uint32_t MI16:1; - uint32_t MI15:1; - uint32_t MI14:1; - uint32_t MI13:1; - uint32_t MI12:1; - uint32_t MI11:1; - uint32_t MI10:1; - uint32_t MI9:1; - uint32_t MI8:1; - uint32_t MI7:1; - uint32_t MI6:1; - uint32_t MI5:1; - uint32_t MI4:1; - uint32_t MI3:1; - uint32_t MI2:1; - uint32_t MI1:1; - uint32_t MI0:1; - } B; - } RX15MASK; - - union { /* Error Counter Register */ - uint32_t R; - struct { - uint32_t:16; - uint32_t RXECNT:8; - uint32_t TXECNT:8; - } B; - } ECR; - - union { /* Error and Status Register */ - uint32_t R; - struct { - uint32_t:14; - - uint32_t TWRNINT:1; - uint32_t RWRNINT:1; - uint32_t BIT1ERR:1; - uint32_t BIT0ERR:1; - uint32_t ACKERR:1; - uint32_t CRCERR:1; - uint32_t FRMERR:1; - uint32_t STFERR:1; - uint32_t TXWRN:1; - uint32_t RXWRN:1; - uint32_t IDLE:1; - uint32_t TXRX:1; - uint32_t FLTCONF:2; - uint32_t:1; - uint32_t BOFFINT:1; - uint32_t ERRINT:1; - uint32_t WAKINT:1; - } B; - } ESR; - - union { /* Interruput Masks Register */ - uint32_t R; - struct { - uint32_t BUF63M:1; - uint32_t BUF62M:1; - uint32_t BUF61M:1; - uint32_t BUF60M:1; - uint32_t BUF59M:1; - uint32_t BUF58M:1; - uint32_t BUF57M:1; - uint32_t BUF56M:1; - uint32_t BUF55M:1; - uint32_t BUF54M:1; - uint32_t BUF53M:1; - uint32_t BUF52M:1; - uint32_t BUF51M:1; - uint32_t BUF50M:1; - uint32_t BUF49M:1; - uint32_t BUF48M:1; - uint32_t BUF47M:1; - uint32_t BUF46M:1; - uint32_t BUF45M:1; - uint32_t BUF44M:1; - uint32_t BUF43M:1; - uint32_t BUF42M:1; - uint32_t BUF41M:1; - uint32_t BUF40M:1; - uint32_t BUF39M:1; - uint32_t BUF38M:1; - uint32_t BUF37M:1; - uint32_t BUF36M:1; - uint32_t BUF35M:1; - uint32_t BUF34M:1; - uint32_t BUF33M:1; - uint32_t BUF32M:1; - } B; - } IMRH; /* Legacy naming - refer to IMASK2 in Reference Manual */ - - union { /* Interruput Masks Register */ - uint32_t R; - struct { - uint32_t BUF31M:1; - uint32_t BUF30M:1; - uint32_t BUF29M:1; - uint32_t BUF28M:1; - uint32_t BUF27M:1; - uint32_t BUF26M:1; - uint32_t BUF25M:1; - uint32_t BUF24M:1; - uint32_t BUF23M:1; - uint32_t BUF22M:1; - uint32_t BUF21M:1; - uint32_t BUF20M:1; - uint32_t BUF19M:1; - uint32_t BUF18M:1; - uint32_t BUF17M:1; - uint32_t BUF16M:1; - uint32_t BUF15M:1; - uint32_t BUF14M:1; - uint32_t BUF13M:1; - uint32_t BUF12M:1; - uint32_t BUF11M:1; - uint32_t BUF10M:1; - uint32_t BUF09M:1; - uint32_t BUF08M:1; - uint32_t BUF07M:1; - uint32_t BUF06M:1; - uint32_t BUF05M:1; - uint32_t BUF04M:1; - uint32_t BUF03M:1; - uint32_t BUF02M:1; - uint32_t BUF01M:1; - uint32_t BUF00M:1; - } B; - } IMRL; /* Legacy naming - refer to IMASK1 in Reference Manual */ - - union { /* Interruput Flag Register */ - uint32_t R; - struct { - uint32_t BUF63I:1; - uint32_t BUF62I:1; - uint32_t BUF61I:1; - uint32_t BUF60I:1; - uint32_t BUF59I:1; - uint32_t BUF58I:1; - uint32_t BUF57I:1; - uint32_t BUF56I:1; - uint32_t BUF55I:1; - uint32_t BUF54I:1; - uint32_t BUF53I:1; - uint32_t BUF52I:1; - uint32_t BUF51I:1; - uint32_t BUF50I:1; - uint32_t BUF49I:1; - uint32_t BUF48I:1; - uint32_t BUF47I:1; - uint32_t BUF46I:1; - uint32_t BUF45I:1; - uint32_t BUF44I:1; - uint32_t BUF43I:1; - uint32_t BUF42I:1; - uint32_t BUF41I:1; - uint32_t BUF40I:1; - uint32_t BUF39I:1; - uint32_t BUF38I:1; - uint32_t BUF37I:1; - uint32_t BUF36I:1; - uint32_t BUF35I:1; - uint32_t BUF34I:1; - uint32_t BUF33I:1; - uint32_t BUF32I:1; - } B; - } IFRH; /* Legacy naming - refer to IFLAG2 in Reference Manual */ - - union { /* Interruput Flag Register */ - uint32_t R; - struct { - uint32_t BUF31I:1; - uint32_t BUF30I:1; - uint32_t BUF29I:1; - uint32_t BUF28I:1; - uint32_t BUF27I:1; - uint32_t BUF26I:1; - uint32_t BUF25I:1; - uint32_t BUF24I:1; - uint32_t BUF23I:1; - uint32_t BUF22I:1; - uint32_t BUF21I:1; - uint32_t BUF20I:1; - uint32_t BUF19I:1; - uint32_t BUF18I:1; - uint32_t BUF17I:1; - uint32_t BUF16I:1; - uint32_t BUF15I:1; - uint32_t BUF14I:1; - uint32_t BUF13I:1; - uint32_t BUF12I:1; - uint32_t BUF11I:1; - uint32_t BUF10I:1; - uint32_t BUF09I:1; - uint32_t BUF08I:1; - uint32_t BUF07I:1; - uint32_t BUF06I:1; - uint32_t BUF05I:1; - uint32_t BUF04I:1; - uint32_t BUF03I:1; - uint32_t BUF02I:1; - uint32_t BUF01I:1; - uint32_t BUF00I:1; - } B; - } IFRL; /* Legacy naming - refer to IFLAG1 in Reference Manual */ - - uint32_t FLEXCAN_reserved0034[19]; /* 0x0034-0x007F */ - - struct canbuf_t { - union { - uint32_t R; - struct { - uint32_t:4; - uint32_t CODE:4; - uint32_t:1; - uint32_t SRR:1; - uint32_t IDE:1; - uint32_t RTR:1; - uint32_t LENGTH:4; - uint32_t TIMESTAMP:16; - } B; - } CS; - - union { - uint32_t R; - struct { - uint32_t PRIO:3; - uint32_t STD_ID:11; - uint32_t EXT_ID:18; - } B; - } ID; - - union { - uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ - uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ - uint32_t W[2]; /* Data buffer in words (32 bits) */ - uint32_t R[2]; /* Data buffer in words (32 bits) */ - } DATA; - - } BUF[64]; - - int32_t FLEXCAN_reserved0480[256]; /* 0x0480-0x087F */ - - union { /* RX Individual Mask Registers */ - uint32_t R; - struct { - uint32_t MI31:1; - uint32_t MI30:1; - uint32_t MI29:1; - uint32_t MI28:1; - uint32_t MI27:1; - uint32_t MI26:1; - uint32_t MI25:1; - uint32_t MI24:1; - uint32_t MI23:1; - uint32_t MI22:1; - uint32_t MI21:1; - uint32_t MI20:1; - uint32_t MI19:1; - uint32_t MI18:1; - uint32_t MI17:1; - uint32_t MI16:1; - uint32_t MI15:1; - uint32_t MI14:1; - uint32_t MI13:1; - uint32_t MI12:1; - uint32_t MI11:1; - uint32_t MI10:1; - uint32_t MI9:1; - uint32_t MI8:1; - uint32_t MI7:1; - uint32_t MI6:1; - uint32_t MI5:1; - uint32_t MI4:1; - uint32_t MI3:1; - uint32_t MI2:1; - uint32_t MI1:1; - uint32_t MI0:1; - } B; - } RXIMR[64]; - - int32_t FLEXCAN_reserved0980[3488]; /* 0x0980-0x3FFF */ - - }; - -/****************************************************************************/ -/* MODULE : FlexRay */ -/****************************************************************************/ - - typedef union uMVR { - uint16_t R; - struct { - uint16_t CHIVER:8; /* CHI Version Number */ - uint16_t PEVER:8; /* PE Version Number */ - } B; - } MVR_t; - - typedef union uMCR { - uint16_t R; - struct { - uint16_t MEN:1; /* module enable */ - uint16_t:1; - uint16_t SCMD:1; /* single channel mode */ - uint16_t CHB:1; /* channel B enable */ - uint16_t CHA:1; /* channel A enable */ - uint16_t SFFE:1; /* synchronization frame filter enable */ - uint16_t:5; - uint16_t CLKSEL:1; /* protocol engine clock source select */ - uint16_t PRESCALE:3; /* protocol engine clock prescaler */ - uint16_t:1; - } B; - } MCR_t; - - typedef union uSTBSCR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t STBSSEL:7; /* strobe signal select */ - uint16_t:3; - uint16_t ENB:1; /* strobe signal enable */ - uint16_t:2; - uint16_t STBPSEL:2; /* strobe port select */ - } B; - } STBSCR_t; - typedef union uSTBPCR { - uint16_t R; - struct { - uint16_t:12; - uint16_t STB3EN:1; /* strobe port enable */ - uint16_t STB2EN:1; /* strobe port enable */ - uint16_t STB1EN:1; /* strobe port enable */ - uint16_t STB0EN:1; /* strobe port enable */ - } B; - } STBPCR_t; - - typedef union uMBDSR { - uint16_t R; - struct { - uint16_t:1; - uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ - uint16_t:1; - uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ - } B; - } MBDSR_t; - typedef union uMBSSUTR { - uint16_t R; - struct { - - uint16_t:1; - uint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */ - uint16_t:1; - uint16_t LAST_MB_UTIL:7; /* last message buffer utilized */ - } B; - } MBSSUTR_t; - - typedef union uPOCR { - uint16_t R; - uint8_t byte[2]; - struct { - uint16_t WME:1; /* write mode external correction command */ - uint16_t:3; - uint16_t EOC_AP:2; /* external offset correction application */ - uint16_t ERC_AP:2; /* external rate correction application */ - uint16_t BSY:1; /* command write busy / write mode command */ - uint16_t:3; - uint16_t POCCMD:4; /* protocol command */ - } B; - } POCR_t; -/* protocol commands */ - typedef union uGIFER { - uint16_t R; - struct { - uint16_t MIF:1; /* module interrupt flag */ - uint16_t PRIF:1; /* protocol interrupt flag */ - uint16_t CHIF:1; /* CHI interrupt flag */ - uint16_t WKUPIF:1; /* wakeup interrupt flag */ - uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ - uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ - uint16_t RBIF:1; /* receive message buffer interrupt flag */ - uint16_t TBIF:1; /* transmit buffer interrupt flag */ - uint16_t MIE:1; /* module interrupt enable */ - uint16_t PRIE:1; /* protocol interrupt enable */ - uint16_t CHIE:1; /* CHI interrupt enable */ - uint16_t WKUPIE:1; /* wakeup interrupt enable */ - uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ - uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ - uint16_t RBIE:1; /* receive message buffer interrupt enable */ - uint16_t TBIE:1; /* transmit buffer interrupt enable */ - } B; - } GIFER_t; - typedef union uPIFR0 { - uint16_t R; - struct { - uint16_t FATLIF:1; /* fatal protocol error interrupt flag */ - uint16_t INTLIF:1; /* internal protocol error interrupt flag */ - uint16_t ILCFIF:1; /* illegal protocol configuration flag */ - uint16_t CSAIF:1; /* cold start abort interrupt flag */ - uint16_t MRCIF:1; /* missing rate correctio interrupt flag */ - uint16_t MOCIF:1; /* missing offset correctio interrupt flag */ - uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ - uint16_t MXSIF:1; /* max sync frames detected interrupt flag */ - uint16_t MTXIF:1; /* media access test symbol received flag */ - uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ - uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ - uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ - uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ - uint16_t TI2IF:1; /* timer 2 expired interrupt flag */ - uint16_t TI1IF:1; /* timer 1 expired interrupt flag */ - uint16_t CYSIF:1; /* cycle start interrupt flag */ - } B; - } PIFR0_t; - typedef union uPIFR1 { - uint16_t R; - struct { - uint16_t EMCIF:1; /* error mode changed interrupt flag */ - uint16_t IPCIF:1; /* illegal protocol command interrupt flag */ - uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ - uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ - uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ - uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ - uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ - uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ - uint16_t:2; - uint16_t EVTIF:1; /* even cycle table written interrupt flag */ - uint16_t ODTIF:1; /* odd cycle table written interrupt flag */ - uint16_t:4; - } B; - } PIFR1_t; - typedef union uPIER0 { - uint16_t R; - struct { - uint16_t FATLIE:1; /* fatal protocol error interrupt enable */ - uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ - uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ - uint16_t CSAIE:1; /* cold start abort interrupt enable */ - uint16_t MRCIE:1; /* missing rate correctio interrupt enable */ - uint16_t MOCIE:1; /* missing offset correctio interrupt enable */ - uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ - uint16_t MXSIE:1; /* max sync frames detected interrupt enable */ - uint16_t MTXIE:1; /* media access test symbol received interrupt enable */ - uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ - uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ - uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ - uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ - uint16_t TI2IE:1; /* timer 2 expired interrupt enable */ - uint16_t TI1IE:1; /* timer 1 expired interrupt enable */ - uint16_t CYSIE:1; /* cycle start interrupt enable */ - } B; - } PIER0_t; - typedef union uPIER1 { - uint16_t R; - struct { - uint16_t EMCIE:1; /* error mode changed interrupt enable */ - uint16_t IPCIE:1; /* illegal protocol command interrupt enable */ - uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ - uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ - uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ - uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ - uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ - uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ - uint16_t:2; - uint16_t EVTIE:1; /* even cycle table written interrupt enable */ - uint16_t ODTIE:1; /* odd cycle table written interrupt enable */ - uint16_t:4; - } B; - } PIER1_t; - typedef union uCHIERFR { - uint16_t R; - struct { - uint16_t FRLBEF:1; /* flame lost channel B error flag */ - uint16_t FRLAEF:1; /* frame lost channel A error flag */ - uint16_t PCMIEF:1; /* command ignored error flag */ - uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ - uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ - uint16_t MSBEF:1; /* message buffer search error flag */ - uint16_t MBUEF:1; /* message buffer utilization error flag */ - uint16_t LCKEF:1; /* lock error flag */ - uint16_t DBLEF:1; /* double transmit message buffer lock error flag */ - uint16_t SBCFEF:1; /* system bus communication failure error flag */ - uint16_t FIDEF:1; /* frame ID error flag */ - uint16_t DPLEF:1; /* dynamic payload length error flag */ - uint16_t SPLEF:1; /* static payload length error flag */ - uint16_t NMLEF:1; /* network management length error flag */ - uint16_t NMFEF:1; /* network management frame error flag */ - uint16_t ILSAEF:1; /* illegal access error flag */ - } B; - } CHIERFR_t; - typedef union uMBIVEC { - uint16_t R; - struct { - - uint16_t:1; - uint16_t TBIVEC:7; /* transmit buffer interrupt vector */ - uint16_t:1; - uint16_t RBIVEC:7; /* receive buffer interrupt vector */ - } B; - } MBIVEC_t; - - typedef union uPSR0 { - uint16_t R; - struct { - uint16_t ERRMODE:2; /* error mode */ - uint16_t SLOTMODE:2; /* slot mode */ - uint16_t:1; - uint16_t PROTSTATE:3; /* protocol state */ - uint16_t SUBSTATE:4; /* protocol sub state */ - uint16_t:1; - uint16_t WAKEUPSTATUS:3; /* wakeup status */ - } B; - } PSR0_t; - -/* protocol states */ -/* protocol sub-states */ -/* wakeup status */ - typedef union uPSR1 { - uint16_t R; - struct { - uint16_t CSAA:1; /* cold start attempt abort flag */ - uint16_t SCP:1; /* cold start path */ - uint16_t:1; - uint16_t REMCSAT:5; /* remanining coldstart attempts */ - uint16_t CPN:1; /* cold start noise path */ - uint16_t HHR:1; /* host halt request pending */ - uint16_t FRZ:1; /* freeze occured */ - uint16_t APTAC:5; /* allow passive to active counter */ - } B; - } PSR1_t; - typedef union uPSR2 { - uint16_t R; - struct { - uint16_t NBVB:1; /* NIT boundary violation on channel B */ - uint16_t NSEB:1; /* NIT syntax error on channel B */ - uint16_t STCB:1; /* symbol window transmit conflict on channel B */ - uint16_t SBVB:1; /* symbol window boundary violation on channel B */ - uint16_t SSEB:1; /* symbol window syntax error on channel B */ - uint16_t MTB:1; /* media access test symbol MTS received on channel B */ - uint16_t NBVA:1; /* NIT boundary violation on channel A */ - uint16_t NSEA:1; /* NIT syntax error on channel A */ - uint16_t STCA:1; /* symbol window transmit conflict on channel A */ - uint16_t SBVA:1; /* symbol window boundary violation on channel A */ - uint16_t SSEA:1; /* symbol window syntax error on channel A */ - uint16_t MTA:1; /* media access test symbol MTS received on channel A */ - uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ - } B; - } PSR2_t; - typedef union uPSR3 { - uint16_t R; - struct { - uint16_t:2; - uint16_t WUB:1; /* wakeup symbol received on channel B */ - uint16_t ABVB:1; /* aggregated boundary violation on channel B */ - uint16_t AACB:1; /* aggregated additional communication on channel B */ - uint16_t ACEB:1; /* aggregated content error on channel B */ - uint16_t ASEB:1; /* aggregated syntax error on channel B */ - uint16_t AVFB:1; /* aggregated valid frame on channel B */ - uint16_t:2; - uint16_t WUA:1; /* wakeup symbol received on channel A */ - uint16_t ABVA:1; /* aggregated boundary violation on channel A */ - uint16_t AACA:1; /* aggregated additional communication on channel A */ - uint16_t ACEA:1; /* aggregated content error on channel A */ - uint16_t ASEA:1; /* aggregated syntax error on channel A */ - uint16_t AVFA:1; /* aggregated valid frame on channel A */ - } B; - } PSR3_t; - typedef union uCIFRR { - uint16_t R; - struct { - uint16_t:8; - uint16_t MIFR:1; /* module interrupt flag */ - uint16_t PRIFR:1; /* protocol interrupt flag */ - uint16_t CHIFR:1; /* CHI interrupt flag */ - uint16_t WUPIFR:1; /* wakeup interrupt flag */ - uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ - uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ - uint16_t RBIFR:1; /* receive message buffer interrupt flag */ - uint16_t TBIFR:1; /* transmit buffer interrupt flag */ - } B; - } CIFRR_t; - typedef union uSFCNTR { - uint16_t R; - struct { - uint16_t SFEVB:4; /* sync frames channel B, even cycle */ - uint16_t SFEVA:4; /* sync frames channel A, even cycle */ - uint16_t SFODB:4; /* sync frames channel B, odd cycle */ - uint16_t SFODA:4; /* sync frames channel A, odd cycle */ - } B; - } SFCNTR_t; - - typedef union uSFTCCSR { - uint16_t R; - struct { - uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ - uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ - uint16_t CYCNUM:6; /* cycle number */ - uint16_t ELKS:1; /* even cycle tables lock status */ - uint16_t OLKS:1; /* odd cycle tables lock status */ - uint16_t EVAL:1; /* even cycle tables valid */ - uint16_t OVAL:1; /* odd cycle tables valid */ - uint16_t:1; - uint16_t OPT:1; /*one pair trigger */ - uint16_t SDVEN:1; /* sync frame deviation table enable */ - uint16_t SIDEN:1; /* sync frame ID table enable */ - } B; - } SFTCCSR_t; - typedef union uSFIDRFR { - uint16_t R; - struct { - uint16_t:6; - uint16_t SYNFRID:10; /* sync frame rejection ID */ - } B; - } SFIDRFR_t; - - typedef union uTICCR { - uint16_t R; - struct { - uint16_t:2; - uint16_t T2CFG:1; /* timer 2 configuration */ - uint16_t T2REP:1; /* timer 2 repetitive mode */ - uint16_t:1; - uint16_t T2SP:1; /* timer 2 stop */ - uint16_t T2TR:1; /* timer 2 trigger */ - uint16_t T2ST:1; /* timer 2 state */ - uint16_t:3; - uint16_t T1REP:1; /* timer 1 repetitive mode */ - uint16_t:1; - uint16_t T1SP:1; /* timer 1 stop */ - uint16_t T1TR:1; /* timer 1 trigger */ - uint16_t T1ST:1; /* timer 1 state */ - - } B; - } TICCR_t; - typedef union uTI1CYSR { - uint16_t R; - struct { - uint16_t:2; - uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ - uint16_t:2; - uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ - - } B; - } TI1CYSR_t; - - typedef union uSSSR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t:1; - uint16_t SEL:2; /* static slot number */ - uint16_t:1; - uint16_t SLOTNUMBER:11; /* selector */ - } B; - } SSSR_t; - - typedef union uSSCCR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t:1; - uint16_t SEL:2; /* selector */ - uint16_t:1; - uint16_t CNTCFG:2; /* counter configuration */ - uint16_t MCY:1; /* multi cycle selection */ - uint16_t VFR:1; /* valid frame selection */ - uint16_t SYF:1; /* sync frame selection */ - uint16_t NUF:1; /* null frame selection */ - uint16_t SUF:1; /* startup frame selection */ - uint16_t STATUSMASK:4; /* slot status mask */ - } B; - } SSCCR_t; - typedef union uSSR { - uint16_t R; - struct { - uint16_t VFB:1; /* valid frame on channel B */ - uint16_t SYB:1; /* valid sync frame on channel B */ - uint16_t NFB:1; /* valid null frame on channel B */ - uint16_t SUB:1; /* valid startup frame on channel B */ - uint16_t SEB:1; /* syntax error on channel B */ - uint16_t CEB:1; /* content error on channel B */ - uint16_t BVB:1; /* boundary violation on channel B */ - uint16_t TCB:1; /* tx conflict on channel B */ - uint16_t VFA:1; /* valid frame on channel A */ - uint16_t SYA:1; /* valid sync frame on channel A */ - uint16_t NFA:1; /* valid null frame on channel A */ - uint16_t SUA:1; /* valid startup frame on channel A */ - uint16_t SEA:1; /* syntax error on channel A */ - uint16_t CEA:1; /* content error on channel A */ - uint16_t BVA:1; /* boundary violation on channel A */ - uint16_t TCA:1; /* tx conflict on channel A */ - } B; - } SSR_t; - typedef union uMTSCFR { - uint16_t R; - struct { - uint16_t MTE:1; /* media access test symbol transmission enable */ - uint16_t:1; - uint16_t CYCCNTMSK:6; /* cycle counter mask */ - uint16_t:2; - uint16_t CYCCNTVAL:6; /* cycle counter value */ - } B; - } MTSCFR_t; - typedef union uRSBIR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t:1; - uint16_t SEL:2; /* selector */ - uint16_t:4; - uint16_t RSBIDX:8; /* receive shadow buffer index */ - } B; - } RSBIR_t; - typedef union uRFDSR { - uint16_t R; - struct { - uint16_t FIFODEPTH:8; /* fifo depth */ - uint16_t:1; - uint16_t ENTRYSIZE:7; /* entry size */ - } B; - } RFDSR_t; - - typedef union uRFRFCFR { - uint16_t R; - struct { - uint16_t WMD:1; /* write mode */ - uint16_t IBD:1; /* interval boundary */ - uint16_t SEL:2; /* filter number */ - uint16_t:1; - uint16_t SID:11; /* slot ID */ - } B; - } RFRFCFR_t; - - typedef union uRFRFCTR { - uint16_t R; - struct { - uint16_t:4; - uint16_t F3MD:1; /* filter mode */ - uint16_t F2MD:1; /* filter mode */ - uint16_t F1MD:1; /* filter mode */ - uint16_t F0MD:1; /* filter mode */ - uint16_t:4; - uint16_t F3EN:1; /* filter enable */ - uint16_t F2EN:1; /* filter enable */ - uint16_t F1EN:1; /* filter enable */ - uint16_t F0EN:1; /* filter enable */ - } B; - } RFRFCTR_t; - typedef union uPCR0 { - uint16_t R; - struct { - uint16_t ACTION_POINT_OFFSET:6; - uint16_t STATIC_SLOT_LENGTH:10; - } B; - } PCR0_t; - - typedef union uPCR1 { - uint16_t R; - struct { - uint16_t:2; - uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; - } B; - } PCR1_t; - - typedef union uPCR2 { - uint16_t R; - struct { - uint16_t MINISLOT_AFTER_ACTION_POINT:6; - uint16_t NUMBER_OF_STATIC_SLOTS:10; - } B; - } PCR2_t; - - typedef union uPCR3 { - uint16_t R; - struct { - uint16_t WAKEUP_SYMBOL_RX_LOW:6; - uint16_t MINISLOT_ACTION_POINT_OFFSET:5; - uint16_t COLDSTART_ATTEMPTS:5; - } B; - } PCR3_t; - - typedef union uPCR4 { - uint16_t R; - struct { - uint16_t CAS_RX_LOW_MAX:7; - uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; - } B; - } PCR4_t; - - typedef union uPCR5 { - uint16_t R; - struct { - uint16_t TSS_TRANSMITTER:4; - uint16_t WAKEUP_SYMBOL_TX_LOW:6; - uint16_t WAKEUP_SYMBOL_RX_IDLE:6; - } B; - } PCR5_t; - - typedef union uPCR6 { - uint16_t R; - struct { - uint16_t:1; - uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; - uint16_t MACRO_INITIAL_OFFSET_A:7; - } B; - } PCR6_t; - - typedef union uPCR7 { - uint16_t R; - struct { - uint16_t DECODING_CORRECTION_B:9; - uint16_t MICRO_PER_MACRO_NOM_HALF:7; - } B; - } PCR7_t; - - typedef union uPCR8 { - uint16_t R; - struct { - uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; - uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; - uint16_t WAKEUP_SYMBOL_TX_IDLE:8; - } B; - } PCR8_t; - - typedef union uPCR9 { - uint16_t R; - struct { - uint16_t MINISLOT_EXISTS:1; - uint16_t SYMBOL_WINDOW_EXISTS:1; - uint16_t OFFSET_CORRECTION_OUT:14; - } B; - } PCR9_t; - - typedef union uPCR10 { - uint16_t R; - struct { - uint16_t SINGLE_SLOT_ENABLED:1; - uint16_t WAKEUP_CHANNEL:1; - uint16_t MACRO_PER_CYCLE:14; - } B; - } PCR10_t; - - typedef union uPCR11 { - uint16_t R; - struct { - uint16_t KEY_SLOT_USED_FOR_STARTUP:1; - uint16_t KEY_SLOT_USED_FOR_SYNC:1; - uint16_t OFFSET_CORRECTION_START:14; - } B; - } PCR11_t; - - typedef union uPCR12 { - uint16_t R; - struct { - uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; - uint16_t KEY_SLOT_HEADER_CRC:11; - } B; - } PCR12_t; - - typedef union uPCR13 { - uint16_t R; - struct { - uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; - uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; - } B; - } PCR13_t; - - typedef union uPCR14 { - uint16_t R; - struct { - uint16_t RATE_CORRECTION_OUT:11; - uint16_t LISTEN_TIMEOUT_H:5; - } B; - } PCR14_t; - - typedef union uPCR15 { - uint16_t R; - struct { - uint16_t LISTEN_TIMEOUT_L:16; - } B; - } PCR15_t; - - typedef union uPCR16 { - uint16_t R; - struct { - uint16_t MACRO_INITIAL_OFFSET_B:7; - uint16_t NOISE_LISTEN_TIMEOUT_H:9; - } B; - } PCR16_t; - - typedef union uPCR17 { - uint16_t R; - struct { - uint16_t NOISE_LISTEN_TIMEOUT_L:16; - } B; - } PCR17_t; - - typedef union uPCR18 { - uint16_t R; - struct { - uint16_t WAKEUP_PATTERN:6; - uint16_t KEY_SLOT_ID:10; - } B; - } PCR18_t; - - typedef union uPCR19 { - uint16_t R; - struct { - uint16_t DECODING_CORRECTION_A:9; - uint16_t PAYLOAD_LENGTH_STATIC:7; - } B; - } PCR19_t; - - typedef union uPCR20 { - uint16_t R; - struct { - uint16_t MICRO_INITIAL_OFFSET_B:8; - uint16_t MICRO_INITIAL_OFFSET_A:8; - } B; - } PCR20_t; - - typedef union uPCR21 { - uint16_t R; - struct { - uint16_t EXTERN_RATE_CORRECTION:3; - uint16_t LATEST_TX:13; - } B; - } PCR21_t; - - typedef union uPCR22 { - uint16_t R; - struct { - uint16_t:1; - uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; - uint16_t MICRO_PER_CYCLE_H:4; - } B; - } PCR22_t; - - typedef union uPCR23 { - uint16_t R; - struct { - uint16_t micro_per_cycle_l:16; - } B; - } PCR23_t; - - typedef union uPCR24 { - uint16_t R; - struct { - uint16_t CLUSTER_DRIFT_DAMPING:5; - uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; - uint16_t MICRO_PER_CYCLE_MIN_H:4; - } B; - } PCR24_t; - - typedef union uPCR25 { - uint16_t R; - struct { - uint16_t MICRO_PER_CYCLE_MIN_L:16; - } B; - } PCR25_t; - - typedef union uPCR26 { - uint16_t R; - struct { - uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; - uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; - uint16_t MICRO_PER_CYCLE_MAX_H:4; - } B; - } PCR26_t; - - typedef union uPCR27 { - uint16_t R; - struct { - uint16_t MICRO_PER_CYCLE_MAX_L:16; - } B; - } PCR27_t; - - typedef union uPCR28 { - uint16_t R; - struct { - uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; - uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; - } B; - } PCR28_t; - - typedef union uPCR29 { - uint16_t R; - struct { - uint16_t EXTERN_OFFSET_CORRECTION:3; - uint16_t MINISLOTS_MAX:13; - } B; - } PCR29_t; - - typedef union uPCR30 { - uint16_t R; - struct { - uint16_t:12; - uint16_t SYNC_NODE_MAX:4; - } B; - } PCR30_t; - - typedef struct uMSG_BUFF_CCS { - union { - uint16_t R; - struct { - uint16_t:1; - uint16_t MCM:1; /* message buffer commit mode */ - uint16_t MBT:1; /* message buffer type */ - uint16_t MTD:1; /* message buffer direction */ - uint16_t CMT:1; /* commit for transmission */ - uint16_t EDT:1; /* enable / disable trigger */ - uint16_t LCKT:1; /* lock request trigger */ - uint16_t MBIE:1; /* message buffer interrupt enable */ - uint16_t:3; - uint16_t DUP:1; /* data updated */ - uint16_t DVAL:1; /* data valid */ - uint16_t EDS:1; /* lock status */ - uint16_t LCKS:1; /* enable / disable status */ - uint16_t MBIF:1; /* message buffer interrupt flag */ - } B; - } MBCCSR; - union { - uint16_t R; - struct { - uint16_t MTM:1; /* message buffer transmission mode */ - uint16_t CHNLA:1; /* channel assignement */ - uint16_t CHNLB:1; /* channel assignement */ - uint16_t CCFE:1; /* cycle counter filter enable */ - uint16_t CCFMSK:6; /* cycle counter filter mask */ - uint16_t CCFVAL:6; /* cycle counter filter value */ - } B; - } MBCCFR; - union { - uint16_t R; - struct { - uint16_t:5; - uint16_t FID:11; /* frame ID */ - } B; - } MBFIDR; - union { - uint16_t R; - struct { - uint16_t:8; - uint16_t MBIDX:8; /* message buffer index */ - } B; - } MBIDXR; - } MSG_BUFF_CCS_t; - typedef union uSYSBADHR { - uint16_t R; - } SYSBADHR_t; - typedef union uSYSBADLR { - uint16_t R; - } SYSBADLR_t; - typedef union uPDAR { - uint16_t R; - } PDAR_t; - typedef union uCASERCR { - uint16_t R; - } CASERCR_t; - typedef union uCBSERCR { - uint16_t R; - } CBSERCR_t; - typedef union uCYCTR { - uint16_t R; - } CYCTR_t; - typedef union uMTCTR { - uint16_t R; - } MTCTR_t; - typedef union uSLTCTAR { - uint16_t R; - } SLTCTAR_t; - typedef union uSLTCTBR { - uint16_t R; - } SLTCTBR_t; - typedef union uRTCORVR { - uint16_t R; - } RTCORVR_t; - typedef union uOFCORVR { - uint16_t R; - } OFCORVR_t; - typedef union uSFTOR { - uint16_t R; - } SFTOR_t; - typedef union uSFIDAFVR { - uint16_t R; - } SFIDAFVR_t; - typedef union uSFIDAFMR { - uint16_t R; - } SFIDAFMR_t; - typedef union uNMVR { - uint16_t R; - } NMVR_t; - typedef union uNMVLR { - uint16_t R; - } NMVLR_t; - typedef union uT1MTOR { - uint16_t R; - } T1MTOR_t; - typedef union uTI2CR0 { - uint16_t R; - } TI2CR0_t; - typedef union uTI2CR1 { - uint16_t R; - } TI2CR1_t; - typedef union uSSCR { - uint16_t R; - } SSCR_t; - typedef union uRFSR { - uint16_t R; - } RFSR_t; - typedef union uRFSIR { - uint16_t R; - } RFSIR_t; - typedef union uRFARIR { - uint16_t R; - } RFARIR_t; - typedef union uRFBRIR { - uint16_t R; - } RFBRIR_t; - typedef union uRFMIDAFVR { - uint16_t R; - } RFMIDAFVR_t; - typedef union uRFMIAFMR { - uint16_t R; - } RFMIAFMR_t; - typedef union uRFFIDRFVR { - uint16_t R; - } RFFIDRFVR_t; - typedef union uRFFIDRFMR { - uint16_t R; - } RFFIDRFMR_t; - typedef union uLDTXSLAR { - uint16_t R; - } LDTXSLAR_t; - typedef union uLDTXSLBR { - uint16_t R; - } LDTXSLBR_t; - - typedef struct FR_tag { - volatile MVR_t MVR; /*module version register *//*0 */ - volatile MCR_t MCR; /*module configuration register *//*2 */ - volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ - volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ - volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ - volatile STBPCR_t STBPCR; /*strobe port control register *//*A */ - volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ - volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ - uint16_t reserved3a[1]; /*10 */ - volatile PDAR_t PDAR; /*PE data register *//*12 */ - volatile POCR_t POCR; /*Protocol operation control register *//*14 */ - volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ - volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ - volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ - volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ - volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ - volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ - volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ - volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ - volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ - volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ - volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ - volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ - volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ - volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ - volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ - volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ - volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ - volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ - volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ - volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ - uint16_t reserved3[1]; /*3E */ - volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ - volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ - volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ - volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ - volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ - volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ - volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ - volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ - volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ - volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ - volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ - volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ - volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ - volatile SSSR_t SSSR; /*slot status selection register *//*64 */ - volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ - volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ - volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ - volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ - volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ - volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ - volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ - volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ - volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ - volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ - volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ - volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ - volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ - volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ - volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ - volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ - volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ - volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ - volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ - volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ - volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ - volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ - volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ - volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ - volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ - volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ - volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ - volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ - volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ - volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ - volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ - volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ - volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ - volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ - volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ - volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ - volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ - volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ - volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ - volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ - volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ - volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ - volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ - volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ - volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ - volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ - volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ - volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ - volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ - volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ - uint16_t reserved2[17]; - volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ - } FR_tag_t; - - typedef union uF_HEADER /* frame header */ - { - struct { - uint16_t:5; - uint16_t HDCRC:11; /* Header CRC */ - uint16_t:2; - uint16_t CYCCNT:6; /* Cycle Count */ - uint16_t:1; - uint16_t PLDLEN:7; /* Payload Length */ - uint16_t:1; - uint16_t PPI:1; /* Payload Preamble Indicator */ - uint16_t NUF:1; /* Null Frame Indicator */ - uint16_t SYF:1; /* Sync Frame Indicator */ - uint16_t SUF:1; /* Startup Frame Indicator */ - uint16_t FID:11; /* Frame ID */ - } B; - uint16_t WORDS[3]; - } F_HEADER_t; - typedef union uS_STSTUS /* slot status */ - { - struct { - uint16_t VFB:1; /* Valid Frame on channel B */ - uint16_t SYB:1; /* Sync Frame Indicator channel B */ - uint16_t NFB:1; /* Null Frame Indicator channel B */ - uint16_t SUB:1; /* Startup Frame Indicator channel B */ - uint16_t SEB:1; /* Syntax Error on channel B */ - uint16_t CEB:1; /* Content Error on channel B */ - uint16_t BVB:1; /* Boundary Violation on channel B */ - uint16_t CH:1; /* Channel */ - uint16_t VFA:1; /* Valid Frame on channel A */ - uint16_t SYA:1; /* Sync Frame Indicator channel A */ - uint16_t NFA:1; /* Null Frame Indicator channel A */ - uint16_t SUA:1; /* Startup Frame Indicator channel A */ - uint16_t SEA:1; /* Syntax Error on channel A */ - uint16_t CEA:1; /* Content Error on channel A */ - uint16_t BVA:1; /* Boundary Violation on channel A */ - uint16_t:1; - } RX; - struct { - uint16_t VFB:1; /* Valid Frame on channel B */ - uint16_t SYB:1; /* Sync Frame Indicator channel B */ - uint16_t NFB:1; /* Null Frame Indicator channel B */ - uint16_t SUB:1; /* Startup Frame Indicator channel B */ - uint16_t SEB:1; /* Syntax Error on channel B */ - uint16_t CEB:1; /* Content Error on channel B */ - uint16_t BVB:1; /* Boundary Violation on channel B */ - uint16_t TCB:1; /* Tx Conflict on channel B */ - uint16_t VFA:1; /* Valid Frame on channel A */ - uint16_t SYA:1; /* Sync Frame Indicator channel A */ - uint16_t NFA:1; /* Null Frame Indicator channel A */ - uint16_t SUA:1; /* Startup Frame Indicator channel A */ - uint16_t SEA:1; /* Syntax Error on channel A */ - uint16_t CEA:1; /* Content Error on channel A */ - uint16_t BVA:1; /* Boundary Violation on channel A */ - uint16_t TCA:1; /* Tx Conflict on channel A */ - } TX; - uint16_t R; - } S_STATUS_t; - - typedef struct uMB_HEADER /* message buffer header */ - { - F_HEADER_t FRAME_HEADER; - uint16_t DATA_OFFSET; - S_STATUS_t SLOT_STATUS; - } MB_HEADER_t; - -/* Define memories */ - -#define SRAM_START 0x40000000 -#define SRAM_SIZE 0x40000 -#define SRAM_END 0x4003FFFF - -#define FLASH_START 0x00000000 -#define FLASH_SIZE 0x400000 -#define FLASH_END 0x003FFFFF - -/* Define instances of modules */ -#define PBRIDGE_A (*( volatile struct PBRIDGE_A_tag *) 0xC3F00000) -#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000) -#define EBI (*( volatile struct EBI_tag *) 0xC3F84000) -#define FLASH_A (*( volatile struct FLASH_tag *) 0xC3F88000) -#define FLASH FLASH_A -#define FLASH_B (*( volatile struct FLASH_tag *) 0xC3F8C000) -#define SIU (*( volatile struct SIU_tag *) 0xC3F90000) - -#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000) -#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000) - -#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000) -#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) -#define ETPU_DATA_RAM_END 0xC3FC8FFC -#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) -#define CODE_RAM (*( uint32_t *) 0xC3FD0000) -#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) - -#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000) - -#define PBRIDGE_B (*( volatile struct PBRIDGE_B_tag *) 0xFFF00000) -#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000) -#define MPU (*( volatile struct MPU_tag *) 0xFFF10000) -#define SWT (*( volatile struct SWT_tag *) 0xFFF38000) -#define STM (*( volatile struct STM_tag *) 0xFFF3C000) -#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000) -#define EDMA_A (*( volatile struct EDMA_tag *) 0xFFF44000) -#define EDMA EDMA_A -#define INTC (*( volatile struct INTC_tag *) 0xFFF48000) -#define EDMA_B (*( volatile struct EDMA_tag *) 0xFFF54000) - -#define EQADC_A (*( volatile struct EQADC_tag *) 0xFFF80000) -#define EQADC EQADC_A -#define EQADC_B (*( volatile struct EQADC_tag *) 0xFFF84000) - -#define DECFIL_A (*( volatile struct DECFIL_tag *) 0xFFF88000) -#define DECFIL_B (*( volatile struct DECFIL_tag *) 0xFFF88800) -#define DECFIL_C (*( volatile struct DECFIL_tag *) 0xFFF89000) -#define DECFIL_D (*( volatile struct DECFIL_tag *) 0xFFF89800) -#define DECFIL_E (*( volatile struct DECFIL_tag *) 0xFFF8A000) -#define DECFIL_F (*( volatile struct DECFIL_tag *) 0xFFF8A800) -#define DECFIL_G (*( volatile struct DECFIL_tag *) 0xFFF8B000) -#define DECFIL_H (*( volatile struct DECFIL_tag *) 0xFFF8B800) - -#define DSPI_A (*( volatile struct DSPI_tag *) 0xFFF90000) -#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000) -#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000) -#define DSPI_D (*( volatile struct DSPI_tag *) 0xFFF9C000) - -#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000) -#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000) -#define ESCI_C (*( volatile struct ESCI_tag *) 0xFFFB8000) -#define ESCI_D (*( volatile struct ESCI_tag *) 0xFFFBC000) - -#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000) -#define CAN_B (*( volatile struct FLEXCAN2_tag *) 0xFFFC4000) -#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000) -#define CAN_D (*( volatile struct FLEXCAN2_tag *) 0xFFFCC000) - -#define FR (*( volatile struct FR_tag *) 0xFFFE0000) -#define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000) - -#ifdef __MWERKS__ -#pragma pop -#endif - -#ifdef __cplusplus -} -#endif -#endif /* ASM */ -#endif /* ifdef _MPC5674_H */ -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - * - ********************************************************************/ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/mpc55xx.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/mpc55xx.h deleted file mode 100644 index 634be30e18..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/mpc55xx.h +++ /dev/null @@ -1,155 +0,0 @@ -/** - * @file - * - * @ingroup mpc55xx - * - * @brief Documentation for this file - */ - -/* - * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/** - * @defgroup mpc55xx BSP for MPC55xx boards - */ - -/** - * @defgroup mpc55xx_config Configuration files - * - * @ingroup mpc55xx - * - * Makefiles, configure scripts etc. - */ - -/** - * @page mpc55xx_ext_doc External Documentation - * - * @section mpc55xx_ext_doc_mpc5567rm_1 MPC5567 Microcontroller Reference Manual (Rev. 1, January 2007, Volume 1 of 2) - * @section mpc55xx_ext_doc_mpc5567rm_2 MPC5567 Microcontroller Reference Manual (Rev. 1, January 2007, Volume 2 of 2) - */ - -#ifndef LIBCPU_POWERPC_MPC55XX_H -#define LIBCPU_POWERPC_MPC55XX_H - -#include <mpc55xx/regs.h> -#include <mpc55xx/regs-mmu.h> - -#include <libcpu/powerpc-utility.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -int mpc55xx_flash_copy(void *dest, const void *src, size_t nbytes); -int mpc55xx_flash_copy_op(void *rdest, const void *src, size_t nbytes, - uint32_t opmask, uint32_t *p_fail_addr); -int mpc55xx_flash_size(uint32_t *p_size); -int mpc55xx_flash_writable(void); -uint32_t mpc55xx_flash_address(void); -void mpc55xx_flash_set_read_only(void); -void mpc55xx_flash_set_read_write(void); - -int mpc55xx_physical_address(const void *addr, uint32_t *p_result); -int mpc55xx_mapped_address(const void *addr, uint32_t *p_result); - -/* Bits for opmask. */ -#define MPC55XX_FLASH_BLANK_CHECK 0x01 -#define MPC55XX_FLASH_UNLOCK 0x02 -#define MPC55XX_FLASH_ERASE 0x04 -#define MPC55XX_FLASH_PROGRAM 0x08 -#define MPC55XX_FLASH_VERIFY 0x10 - -/* Error returns. CONFIG or SIZE might mean you just - * need to check for new configuration bits. - * SIZE and RANGE mean you are outside of a known flash region. - * ERASE means the erase failed, - * PROGRAM means the program failed, - * BLANK means it wasn't blank and BLANK_CHECK was specified, - * VERIFY means VERIFY was set and it didn't match the source, - * and LOCK means either the locking failed or you needed to - * specify MPC55XX_FLASH_UNLOCK and didn't. - */ -#define MPC55XX_FLASH_CONFIG_ERR (-1) -#define MPC55XX_FLASH_SIZE_ERR (-2) -#define MPC55XX_FLASH_RANGE_ERR (-3) -#define MPC55XX_FLASH_ERASE_ERR (-4) -#define MPC55XX_FLASH_PROGRAM_ERR (-5) -#define MPC55XX_FLASH_NOT_BLANK_ERR (-6) -#define MPC55XX_FLASH_VERIFY_ERR (-7) -#define MPC55XX_FLASH_LOCK_ERR (-8) - -#define MPC55XX_CACHE_ALIGNED_MASK ((uintptr_t) 0x1f) - -#define MPC55XX_CACHE_LINE_SIZE 32 - -/** - * @brief Returns true if the buffer starting at @a s of size @a n is cache aligned. - */ -static inline int mpc55xx_is_cache_aligned( const void *s, size_t n) -{ - return !(((uintptr_t) s & MPC55XX_CACHE_ALIGNED_MASK) || (n & MPC55XX_CACHE_ALIGNED_MASK)); -} - -static inline uintptr_t mpc55xx_cache_aligned_start( const void *s) -{ - return ((uintptr_t) s & MPC55XX_CACHE_ALIGNED_MASK) ? (((uintptr_t) s & ~MPC55XX_CACHE_ALIGNED_MASK) + MPC55XX_CACHE_LINE_SIZE) : (uintptr_t)s; -} - -static inline size_t mpc55xx_non_cache_aligned_size( const void *s) -{ - return (uintptr_t) mpc55xx_cache_aligned_start( s) - (uintptr_t) s; -} - -static inline size_t mpc55xx_cache_aligned_size( const void *s, size_t n) -{ - return (n - mpc55xx_non_cache_aligned_size( s)) & ~MPC55XX_CACHE_ALIGNED_MASK; -} - -/** - * @brief Returns the number of leading zeros. - */ -static inline uint32_t mpc55xx_count_leading_zeros( uint32_t value) -{ - uint32_t count; - __asm__ ( - "cntlzw %0, %1;" - : "=r" (count) - : "r" (value) - ); - return count; -} - -static inline void mpc55xx_wait_for_interrupt(void) -{ - #ifdef MPC55XX_HAS_WAIT_INSTRUCTION - __asm__ volatile ("wait"); - #else - __asm__ volatile (""); - #endif -} - -static inline void mpc55xx_mmu_apply_config(const struct MMU_tag *config) -{ - PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS0, config->MAS0.R); - PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1, config->MAS1.R); - PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS2, config->MAS2.R); - PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS3, config->MAS3.R); - __asm__ volatile ("tlbwe"); -} - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBCPU_POWERPC_MPC55XX_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/reg-defs.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/reg-defs.h deleted file mode 100644 index 2d66f6a8d0..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/reg-defs.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - * @file - * - * @ingroup mpc55xx - * - * @brief Register definitions. - */ - -/* - * Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBCPU_POWERPC_MPC55XX_REG_DEFS_H -#define LIBCPU_POWERPC_MPC55XX_REG_DEFS_H - -#include <bspopts.h> - -#if MPC55XX_CHIP_FAMILY == 551 - #define FLASH_BIUCR 0xFFFF801C -#else - #define FLASH_BIUCR 0xC3F8801C -#endif - -/* - * Definitions for FLASH_BIUCR (Flash BIU Control Register) - */ - -/* Fields for Flash Bus Interface Control */ -/* Fields for Prefetch Control (MnPFE Master n Prefetch Enable) */ - -/* Fields for M3PFE (Master 3 (EBI) prefetch enable bit [12]) */ -#define FLASH_BUICR_EBI_PREFTCH 0x00080000 - -/* Fields for M2PFE (Master 2 (eDMA) prefetch enable bit [13]) */ -#define FLASH_BUICR_EDMA_PREFTCH 0x00040000 - -/* Fields for M1PFE (Master 1 (Nexus) prefetch enable bit [14]) */ -#define FLASH_BUICR_NEX_PREFTCH 0x00020000 - -/* Fields for M0PFE (Master 0 (e200z core) prefetch enable bit [15]) */ -#define FLASH_BUICR_CPU_PREFTCH 0x00010000 - -/* Fields for APC (access pipelining control bits [16:18]) */ -#define FLASH_BUICR_APC_0 0x00000000 -#define FLASH_BUICR_APC_1 0x00002000 -#define FLASH_BUICR_APC_2 0x00004000 -#define FLASH_BUICR_APC_3 0x00006000 -#define FLASH_BUICR_APC_4 0x00008000 -#define FLASH_BUICR_APC_5 0x0000A000 -#define FLASH_BUICR_APC_6 0x0000C000 -#define FLASH_BUICR_APC_NO 0x0000E000 - -/* Fields for WWSC (write wait state control bits [19:20]) */ -#define FLASH_BUICR_WWSC_1 0x00000800 -#define FLASH_BUICR_WWSC_2 0x00001000 -#define FLASH_BUICR_WWSC_3 0x00001800 - -/* Fields for RWSC (read wait state control bits [21:23]) */ -#define FLASH_BUICR_RWSC_0 0x00000000 -#define FLASH_BUICR_RWSC_1 0x00000100 -#define FLASH_BUICR_RWSC_2 0x00000200 -#define FLASH_BUICR_RWSC_3 0x00000300 -#define FLASH_BUICR_RWSC_4 0x00000400 -#define FLASH_BUICR_RWSC_5 0x00000500 -#define FLASH_BUICR_RWSC_6 0x00000600 -#define FLASH_BUICR_RWSC_7 0x00000700 - -/* Fields for DPFEN (data prefetch enable bits [24:25]) */ -#define FLASH_BUICR_DPFEN_0 0x00000000 -#define FLASH_BUICR_DPFEN_1 0x00000040 -#define FLASH_BUICR_DPFEN_3 0x000000C0 - -/* Fields for IPFEN (instruction prefetch enable bits [26:27]) */ -#define FLASH_BUICR_IPFEN_0 0x00000000 -#define FLASH_BUICR_IPFEN_1 0x00000010 -#define FLASH_BUICR_IPFEN_3 0x00000030 - -/* Fields for PFLIM (additional line prefetch (limit) bits [28:30]) */ -#define FLASH_BUICR_PFLIM_0 0x00000000 -#define FLASH_BUICR_PFLIM_1 0x00000002 -#define FLASH_BUICR_PFLIM_2 0x00000004 -#define FLASH_BUICR_PFLIM_3 0x00000006 -#define FLASH_BUICR_PFLIM_4 0x00000008 -#define FLASH_BUICR_PFLIM_5 0x0000000A -#define FLASH_BUICR_PFLIM_6 0x0000000C - -/* Fields for BFEN (enable line read buffer hits bit [31]) */ -#define FLASH_BUICR_BFEN 0x00000001 - -#endif /* LIBCPU_POWERPC_MPC55XX_REG_DEFS_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/regs-edma.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/regs-edma.h deleted file mode 100644 index 804730ccd8..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/regs-edma.h +++ /dev/null @@ -1,710 +0,0 @@ -/** - * @file - * - * @ingroup mpc55xx - */ - -/* - * Copyright (c) 2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - * - ********************************************************************/ - -#ifndef LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H -#define LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H - -#include <stdint.h> - -#include <bspopts.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/****************************************************************************/ -/* MODULE : eDMA */ -/****************************************************************************/ - struct EDMA_tag { - union EDMA_CR_tag { - uint32_t R; - struct { -#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 - uint32_t:14; - uint32_t CX:1; - uint32_t ECX:1; -#else - uint32_t:16; -#endif - uint32_t GRP3PRI:2; - uint32_t GRP2PRI:2; - uint32_t GRP1PRI:2; - uint32_t GRP0PRI:2; -#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 - uint32_t EMLM:1; - uint32_t CLM:1; - uint32_t HALT:1; - uint32_t HOE:1; -#else - uint32_t:4; -#endif - uint32_t ERGA:1; - uint32_t ERCA:1; - uint32_t EDBG:1; - uint32_t EBW:1; - } B; - } CR; /* Control Register */ - - union { - uint32_t R; - struct { - uint32_t VLD:1; -#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 - uint32_t:14; - uint32_t ECX:1; -#else - uint32_t:15; -#endif - uint32_t GPE:1; - uint32_t CPE:1; - uint32_t ERRCHN:6; - uint32_t SAE:1; - uint32_t SOE:1; - uint32_t DAE:1; - uint32_t DOE:1; - uint32_t NCE:1; - uint32_t SGE:1; - uint32_t SBE:1; - uint32_t DBE:1; - } B; - } ESR; /* Error Status Register */ - - union { - uint32_t R; - struct { - uint32_t ERQ63:1; - uint32_t ERQ62:1; - uint32_t ERQ61:1; - uint32_t ERQ60:1; - uint32_t ERQ59:1; - uint32_t ERQ58:1; - uint32_t ERQ57:1; - uint32_t ERQ56:1; - uint32_t ERQ55:1; - uint32_t ERQ54:1; - uint32_t ERQ53:1; - uint32_t ERQ52:1; - uint32_t ERQ51:1; - uint32_t ERQ50:1; - uint32_t ERQ49:1; - uint32_t ERQ48:1; - uint32_t ERQ47:1; - uint32_t ERQ46:1; - uint32_t ERQ45:1; - uint32_t ERQ44:1; - uint32_t ERQ43:1; - uint32_t ERQ42:1; - uint32_t ERQ41:1; - uint32_t ERQ40:1; - uint32_t ERQ39:1; - uint32_t ERQ38:1; - uint32_t ERQ37:1; - uint32_t ERQ36:1; - uint32_t ERQ35:1; - uint32_t ERQ34:1; - uint32_t ERQ33:1; - uint32_t ERQ32:1; - } B; - } ERQRH; /* DMA Enable Request Register High */ - - union { - uint32_t R; - struct { - uint32_t ERQ31:1; - uint32_t ERQ30:1; - uint32_t ERQ29:1; - uint32_t ERQ28:1; - uint32_t ERQ27:1; - uint32_t ERQ26:1; - uint32_t ERQ25:1; - uint32_t ERQ24:1; - uint32_t ERQ23:1; - uint32_t ERQ22:1; - uint32_t ERQ21:1; - uint32_t ERQ20:1; - uint32_t ERQ19:1; - uint32_t ERQ18:1; - uint32_t ERQ17:1; - uint32_t ERQ16:1; - uint32_t ERQ15:1; - uint32_t ERQ14:1; - uint32_t ERQ13:1; - uint32_t ERQ12:1; - uint32_t ERQ11:1; - uint32_t ERQ10:1; - uint32_t ERQ09:1; - uint32_t ERQ08:1; - uint32_t ERQ07:1; - uint32_t ERQ06:1; - uint32_t ERQ05:1; - uint32_t ERQ04:1; - uint32_t ERQ03:1; - uint32_t ERQ02:1; - uint32_t ERQ01:1; - uint32_t ERQ00:1; - } B; - } ERQRL; /* DMA Enable Request Register Low */ - - union { - uint32_t R; - struct { - uint32_t EEI63:1; - uint32_t EEI62:1; - uint32_t EEI61:1; - uint32_t EEI60:1; - uint32_t EEI59:1; - uint32_t EEI58:1; - uint32_t EEI57:1; - uint32_t EEI56:1; - uint32_t EEI55:1; - uint32_t EEI54:1; - uint32_t EEI53:1; - uint32_t EEI52:1; - uint32_t EEI51:1; - uint32_t EEI50:1; - uint32_t EEI49:1; - uint32_t EEI48:1; - uint32_t EEI47:1; - uint32_t EEI46:1; - uint32_t EEI45:1; - uint32_t EEI44:1; - uint32_t EEI43:1; - uint32_t EEI42:1; - uint32_t EEI41:1; - uint32_t EEI40:1; - uint32_t EEI39:1; - uint32_t EEI38:1; - uint32_t EEI37:1; - uint32_t EEI36:1; - uint32_t EEI35:1; - uint32_t EEI34:1; - uint32_t EEI33:1; - uint32_t EEI32:1; - } B; - } EEIRH; /* DMA Enable Error Interrupt Register High */ - - union { - uint32_t R; - struct { - uint32_t EEI31:1; - uint32_t EEI30:1; - uint32_t EEI29:1; - uint32_t EEI28:1; - uint32_t EEI27:1; - uint32_t EEI26:1; - uint32_t EEI25:1; - uint32_t EEI24:1; - uint32_t EEI23:1; - uint32_t EEI22:1; - uint32_t EEI21:1; - uint32_t EEI20:1; - uint32_t EEI19:1; - uint32_t EEI18:1; - uint32_t EEI17:1; - uint32_t EEI16:1; - uint32_t EEI15:1; - uint32_t EEI14:1; - uint32_t EEI13:1; - uint32_t EEI12:1; - uint32_t EEI11:1; - uint32_t EEI10:1; - uint32_t EEI09:1; - uint32_t EEI08:1; - uint32_t EEI07:1; - uint32_t EEI06:1; - uint32_t EEI05:1; - uint32_t EEI04:1; - uint32_t EEI03:1; - uint32_t EEI02:1; - uint32_t EEI01:1; - uint32_t EEI00:1; - } B; - } EEIRL; /* DMA Enable Error Interrupt Register Low */ - - union { /* DMA Set Enable Request Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t SERQ:7; - } B; - } SERQR; - - union { /* DMA Clear Enable Request Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t CERQ:7; - } B; - } CERQR; - - union { /* DMA Set Enable Error Interrupt Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t SEEI:7; - } B; - } SEEIR; - - union { /* DMA Clear Enable Error Interrupt Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t CEEI:7; - } B; - } CEEIR; - - union { /* DMA Clear Interrupt Request Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t CINT:7; - } B; - } CIRQR; - - union { /* DMA Clear error Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t CERR:7; - } B; - } CER; - - union { /* Set Start Bit Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t SSB:7; - } B; - } SSBR; - - union { /* Clear Done Status Bit Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t CDSB:7; - } B; - } CDSBR; - - union { - uint32_t R; - struct { - uint32_t INT63:1; - uint32_t INT62:1; - uint32_t INT61:1; - uint32_t INT60:1; - uint32_t INT59:1; - uint32_t INT58:1; - uint32_t INT57:1; - uint32_t INT56:1; - uint32_t INT55:1; - uint32_t INT54:1; - uint32_t INT53:1; - uint32_t INT52:1; - uint32_t INT51:1; - uint32_t INT50:1; - uint32_t INT49:1; - uint32_t INT48:1; - uint32_t INT47:1; - uint32_t INT46:1; - uint32_t INT45:1; - uint32_t INT44:1; - uint32_t INT43:1; - uint32_t INT42:1; - uint32_t INT41:1; - uint32_t INT40:1; - uint32_t INT39:1; - uint32_t INT38:1; - uint32_t INT37:1; - uint32_t INT36:1; - uint32_t INT35:1; - uint32_t INT34:1; - uint32_t INT33:1; - uint32_t INT32:1; - } B; - } IRQRH; /* DMA Interrupt Request High */ - - union { - uint32_t R; - struct { - uint32_t INT31:1; - uint32_t INT30:1; - uint32_t INT29:1; - uint32_t INT28:1; - uint32_t INT27:1; - uint32_t INT26:1; - uint32_t INT25:1; - uint32_t INT24:1; - uint32_t INT23:1; - uint32_t INT22:1; - uint32_t INT21:1; - uint32_t INT20:1; - uint32_t INT19:1; - uint32_t INT18:1; - uint32_t INT17:1; - uint32_t INT16:1; - uint32_t INT15:1; - uint32_t INT14:1; - uint32_t INT13:1; - uint32_t INT12:1; - uint32_t INT11:1; - uint32_t INT10:1; - uint32_t INT09:1; - uint32_t INT08:1; - uint32_t INT07:1; - uint32_t INT06:1; - uint32_t INT05:1; - uint32_t INT04:1; - uint32_t INT03:1; - uint32_t INT02:1; - uint32_t INT01:1; - uint32_t INT00:1; - } B; - } IRQRL; /* DMA Interrupt Request Low */ - - union { - uint32_t R; - struct { - uint32_t ERR63:1; - uint32_t ERR62:1; - uint32_t ERR61:1; - uint32_t ERR60:1; - uint32_t ERR59:1; - uint32_t ERR58:1; - uint32_t ERR57:1; - uint32_t ERR56:1; - uint32_t ERR55:1; - uint32_t ERR54:1; - uint32_t ERR53:1; - uint32_t ERR52:1; - uint32_t ERR51:1; - uint32_t ERR50:1; - uint32_t ERR49:1; - uint32_t ERR48:1; - uint32_t ERR47:1; - uint32_t ERR46:1; - uint32_t ERR45:1; - uint32_t ERR44:1; - uint32_t ERR43:1; - uint32_t ERR42:1; - uint32_t ERR41:1; - uint32_t ERR40:1; - uint32_t ERR39:1; - uint32_t ERR38:1; - uint32_t ERR37:1; - uint32_t ERR36:1; - uint32_t ERR35:1; - uint32_t ERR34:1; - uint32_t ERR33:1; - uint32_t ERR32:1; - } B; - } ERH; /* DMA Error High */ - - union { - uint32_t R; - struct { - uint32_t ERR31:1; - uint32_t ERR30:1; - uint32_t ERR29:1; - uint32_t ERR28:1; - uint32_t ERR27:1; - uint32_t ERR26:1; - uint32_t ERR25:1; - uint32_t ERR24:1; - uint32_t ERR23:1; - uint32_t ERR22:1; - uint32_t ERR21:1; - uint32_t ERR20:1; - uint32_t ERR19:1; - uint32_t ERR18:1; - uint32_t ERR17:1; - uint32_t ERR16:1; - uint32_t ERR15:1; - uint32_t ERR14:1; - uint32_t ERR13:1; - uint32_t ERR12:1; - uint32_t ERR11:1; - uint32_t ERR10:1; - uint32_t ERR09:1; - uint32_t ERR08:1; - uint32_t ERR07:1; - uint32_t ERR06:1; - uint32_t ERR05:1; - uint32_t ERR04:1; - uint32_t ERR03:1; - uint32_t ERR02:1; - uint32_t ERR01:1; - uint32_t ERR00:1; - } B; - } ERL; /* DMA Error Low */ - -#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 - union { /* hardware request status high */ - uint32_t R; - struct { - uint32_t HRS63:1; - uint32_t HRS62:1; - uint32_t HRS61:1; - uint32_t HRS60:1; - uint32_t HRS59:1; - uint32_t HRS58:1; - uint32_t HRS57:1; - uint32_t HRS56:1; - uint32_t HRS55:1; - uint32_t HRS54:1; - uint32_t HRS53:1; - uint32_t HRS52:1; - uint32_t HRS51:1; - uint32_t HRS50:1; - uint32_t HRS49:1; - uint32_t HRS48:1; - uint32_t HRS47:1; - uint32_t HRS46:1; - uint32_t HRS45:1; - uint32_t HRS44:1; - uint32_t HRS43:1; - uint32_t HRS42:1; - uint32_t HRS41:1; - uint32_t HRS40:1; - uint32_t HRS39:1; - uint32_t HRS38:1; - uint32_t HRS37:1; - uint32_t HRS36:1; - uint32_t HRS35:1; - uint32_t HRS34:1; - uint32_t HRS33:1; - uint32_t HRS32:1; - } B; - } HRSH; - - union { /* hardware request status low */ - uint32_t R; - struct { - uint32_t HRS31:1; - uint32_t HRS30:1; - uint32_t HRS29:1; - uint32_t HRS28:1; - uint32_t HRS27:1; - uint32_t HRS26:1; - uint32_t HRS25:1; - uint32_t HRS24:1; - uint32_t HRS23:1; - uint32_t HRS22:1; - uint32_t HRS21:1; - uint32_t HRS20:1; - uint32_t HRS19:1; - uint32_t HRS18:1; - uint32_t HRS17:1; - uint32_t HRS16:1; - uint32_t HRS15:1; - uint32_t HRS14:1; - uint32_t HRS13:1; - uint32_t HRS12:1; - uint32_t HRS11:1; - uint32_t HRS10:1; - uint32_t HRS09:1; - uint32_t HRS08:1; - uint32_t HRS07:1; - uint32_t HRS06:1; - uint32_t HRS05:1; - uint32_t HRS04:1; - uint32_t HRS03:1; - uint32_t HRS02:1; - uint32_t HRS01:1; - uint32_t HRS00:1; - } B; - } HRSL; - - uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */ -#else - uint32_t edma_reserved1[52]; -#endif - - union { - uint8_t R; - struct { - uint8_t ECP:1; -#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 - uint8_t DPA:1; -#else - uint8_t:1; -#endif - uint8_t GRPPRI:2; - uint8_t CHPRI:4; - } B; - } CPR[64]; - - uint32_t edma_reserved2[944]; - -/****************************************************************************/ -/* DMA2 Transfer Control Descriptor */ -/****************************************************************************/ - struct tcd_t { - uint32_t SADDR; /* source address */ - - /* Source and destination fields */ - union tcd_SDF_tag { - uint32_t R; - struct { - uint16_t SMOD:5; /* source address modulo */ - uint16_t SSIZE:3; /* source transfer size */ - uint16_t DMOD:5; /* destination address modulo */ - uint16_t DSIZE:3; /* destination transfer size */ - int16_t SOFF; /* signed source address offset */ - } B; - } SDF; - - uint32_t NBYTES; /* inner (“minor”) byte count */ - - int32_t SLAST; /* last destination address adjustment, or - scatter/gather address (if e_sg = 1) */ - - uint32_t DADDR; /* destination address */ - - /* CITER and destination fields */ - union tcd_CDF_tag { - uint32_t R; - struct { - uint16_t CITERE_LINK:1; - uint16_t CITER:15; - int16_t DOFF; /* signed destination address offset */ - } B; - struct { - uint16_t CITERE_LINK:1; - uint16_t CITERLINKCH:6; - uint16_t CITER:9; - int16_t DOFF; - } B_ALT; - struct { - uint16_t CITER; - int16_t DOFF; - } B_NOLINK; - } CDF; - - int32_t DLAST_SGA; - - /* BITER and misc fields */ - union tcd_BMF_tag { - uint32_t R; - struct { - uint32_t BITERE_LINK:1; /* beginning ("major") iteration count */ - uint32_t BITER:15; - uint32_t BWC:2; /* bandwidth control */ - uint32_t MAJORLINKCH:6; /* enable channel-to-channel link */ - uint32_t DONE:1; /* channel done */ - uint32_t ACTIVE:1; /* channel active */ - uint32_t MAJORE_LINK:1; /* enable channel-to-channel link */ - uint32_t E_SG:1; /* enable scatter/gather descriptor */ - uint32_t D_REQ:1; /* disable ipd_req when done */ - uint32_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ - uint32_t INT_MAJ:1; /* interrupt on major loop completion */ - uint32_t START:1; /* explicit channel start */ - } B; - struct { - uint32_t BITERE_LINK:1; - uint32_t BITERLINKCH:6; - uint32_t BITER:9; - uint32_t BWC:2; - uint32_t MAJORLINKCH:6; - uint32_t DONE:1; - uint32_t ACTIVE:1; - uint32_t MAJORE_LINK:1; - uint32_t E_SG:1; - uint32_t D_REQ:1; - uint32_t INT_HALF:1; - uint32_t INT_MAJ:1; - uint32_t START:1; - } B_ALT; - struct { - uint16_t BITER; - uint16_t BWC:2; - uint16_t MAJORLINKCH:6; - uint16_t DONE:1; - uint16_t ACTIVE:1; - uint16_t MAJORE_LINK:1; - uint16_t E_SG:1; - uint16_t D_REQ:1; - uint16_t INT_HALF:1; - uint16_t INT_MAJ:1; - uint16_t START:1; - } B_NOLINK; - } BMF; - } TCD[64]; /* transfer_control_descriptor */ - }; - -#ifndef __cplusplus - static const struct tcd_t EDMA_TCD_DEFAULT = { - .SADDR = 0, - .SDF = { .R = 0 }, - .NBYTES = 0, - .SLAST = 0, - .DADDR = 0, - .CDF = { .R = 0 }, - .DLAST_SGA = 0, - .BMF = { .R = 0 } - }; -#endif /* __cplusplus */ - -#define EDMA_TCD_BITER_MASK 0x7fff - -#define EDMA_TCD_BITER_SIZE (EDMA_TCD_BITER_MASK + 1) - -#define EDMA_TCD_BITER_LINKED_MASK 0x1ff - -#define EDMA_TCD_BITER_LINKED_SIZE (EDMA_TCD_BITER_LINKED_MASK + 1) - -#define EDMA_TCD_LINK_AND_BITER(link, biter) \ - (((link) << 9) + ((biter) & EDMA_TCD_BITER_LINKED_MASK)) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/regs-mmu.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/regs-mmu.h deleted file mode 100644 index e03047c4ad..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/regs-mmu.h +++ /dev/null @@ -1,200 +0,0 @@ -/** - * @file - * - * @ingroup mpc55xx - */ - -/* - * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - * - ********************************************************************/ - -#ifndef LIBCPU_POWERPC_MPC55XX_REGS_MMU_H -#define LIBCPU_POWERPC_MPC55XX_REGS_MMU_H - -#include <stdint.h> - -#include <bspopts.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/****************************************************************************/ -/* MMU */ -/****************************************************************************/ - struct MMU_tag { - union { - uint32_t R; - struct { - uint32_t : 2; - uint32_t TLBSEL : 2; - uint32_t : 7; - uint32_t ESEL : 5; - uint32_t : 11; - uint32_t NV : 5; - } B; - } MAS0; - - union { - uint32_t R; - struct { - uint32_t VALID : 1; - uint32_t IPROT : 1; - uint32_t : 6; - uint32_t TID : 8; - uint32_t : 3; - uint32_t TS : 1; - uint32_t TSIZE : 5; - uint32_t : 7; - } B; - } MAS1; - - union { - uint32_t R; - struct { - uint32_t EPN : 22; - uint32_t : 4; - uint32_t VLE : 1; - uint32_t W : 1; - uint32_t I : 1; - uint32_t M : 1; - uint32_t G : 1; - uint32_t E : 1; - } B; - } MAS2; - - union { - uint32_t R; - struct { - uint32_t RPN : 22; - uint32_t U0 : 1; - uint32_t U1 : 1; - uint32_t U2 : 1; - uint32_t U3 : 1; - uint32_t UX : 1; - uint32_t SX : 1; - uint32_t UW : 1; - uint32_t SW : 1; - uint32_t UR : 1; - uint32_t SR : 1; - } B; - } MAS3; - }; - - union MMU_MAS4_tag { - uint32_t R; - struct { - uint32_t : 2; - uint32_t TLBSELD : 2; - uint32_t : 10; - uint32_t TIDSELD : 2; - uint32_t : 4; - uint32_t TSIZED : 4; - uint32_t : 3; - uint32_t WD : 1; - uint32_t ID : 1; - uint32_t MD : 1; - uint32_t GD : 1; - uint32_t ED : 1; - } B; - }; - - union MMU_MAS6_tag { - uint32_t R; - struct { - uint32_t : 8; - uint32_t SPID : 8; - uint32_t : 15; - uint32_t SAS : 1; - } B; - }; - -#define MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addreff, addrreal, size, x, w, r, io) \ - { \ - .MAS0 = { .B = { .TLBSEL = 1, .ESEL = (idx) } }, \ - .MAS1 = { .B = { \ - .VALID = 1, .IPROT = 1, .TID = 0, .TS = 0, .TSIZE = (size) } \ - }, \ - .MAS2 = { .B = { \ - .EPN = (addreff) >> 10, .VLE = 0, \ - .W = (io) == 2, .I = (io) == 1, .M = 0, .G = (io) == 1, .E = 0 } \ - }, \ - .MAS3 = { .B = { \ - .RPN = (addrreal) >> 10, .U0 = 0, .U1 = 0, .U2 = 0, .U3 = 0, .UX = 0, \ - .SX = (x), .UW = 0, .SW = (w), .UR = 0, .SR = (r) } \ - } \ - } - -#define MPC55XX_MMU_TAG_INITIALIZER(idx, addr, size, x, w, r, io) \ - MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addr, addr, size, x, w, r, io) - -#define MPC55XX_MMU_1K 0 -#define MPC55XX_MMU_2K 1 -#define MPC55XX_MMU_4K 2 -#define MPC55XX_MMU_8K 3 -#define MPC55XX_MMU_16K 4 -#define MPC55XX_MMU_32K 5 -#define MPC55XX_MMU_64K 6 -#define MPC55XX_MMU_128K 7 -#define MPC55XX_MMU_256K 8 -#define MPC55XX_MMU_512K 9 -#define MPC55XX_MMU_1M 10 -#define MPC55XX_MMU_2M 11 -#define MPC55XX_MMU_4M 12 -#define MPC55XX_MMU_8M 13 -#define MPC55XX_MMU_16M 14 -#define MPC55XX_MMU_32M 15 -#define MPC55XX_MMU_64M 16 -#define MPC55XX_MMU_128M 17 -#define MPC55XX_MMU_256M 18 -#define MPC55XX_MMU_512M 19 -#define MPC55XX_MMU_1G 20 -#define MPC55XX_MMU_2G 21 -#define MPC55XX_MMU_4G 22 - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBCPU_POWERPC_MPC55XX_REGS_MMU_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h deleted file mode 100644 index 3a4e737f1a..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * @file - * - * @ingroup mpc55xx - * - * @brief Register definitions for the MPC55xx and MPC56xx microcontroller - * family. - */ - -/* - * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBCPU_POWERPC_MPC55XX_REGS_H -#define LIBCPU_POWERPC_MPC55XX_REGS_H - -#include <bspopts.h> - -#if MPC55XX_CHIP_FAMILY == 551 - #include <mpc55xx/fsl-mpc551x.h> - #define MPC55XX_HAS_EBI - #define MPC55XX_HAS_ESCI - #define MPC55XX_HAS_EMIOS - #define MPC55XX_HAS_FMPLL_ENHANCED - #define MPC55XX_HAS_SIU -#elif MPC55XX_CHIP_FAMILY == 555 - #include <mpc55xx/fsl-mpc555x.h> - #define MPC55XX_HAS_EBI - #define MPC55XX_HAS_ESCI - #define MPC55XX_HAS_EMIOS - #define MPC55XX_HAS_FMPLL - #define MPC55XX_HAS_UNIFIED_CACHE - #define MPC55XX_HAS_SIU -#elif MPC55XX_CHIP_FAMILY == 556 - #include <mpc55xx/fsl-mpc556x.h> - #define MPC55XX_HAS_EBI - #define MPC55XX_HAS_ESCI - #define MPC55XX_HAS_EMIOS - #define MPC55XX_HAS_FMPLL - #define MPC55XX_HAS_UNIFIED_CACHE - #define MPC55XX_HAS_SIU -#elif MPC55XX_CHIP_FAMILY == 564 - #include <mpc55xx/fsl-mpc564xL.h> - #define MPC55XX_HAS_STM - #define MPC55XX_HAS_SWT - #define MPC55XX_HAS_MODE_CONTROL - #define MPC55XX_HAS_INSTRUCTION_CACHE - #define MPC55XX_HAS_LINFLEX - #define MPC55XX_HAS_SECOND_INTERNAL_RAM_AREA - #define MPC55XX_HAS_SIU_LITE -#elif MPC55XX_CHIP_FAMILY == 566 - #include <mpc55xx/fsl-mpc5668.h> - #define MPC55XX_HAS_ESCI - #define MPC55XX_HAS_EMIOS - #define MPC55XX_HAS_FMPLL_ENHANCED - #define MPC55XX_HAS_UNIFIED_CACHE - #define MPC55XX_HAS_SIU - /* - * TODO: This e200z650n3e core has a wait instruction, but it did not wake-up - * from PIT interrupts. - */ -#elif MPC55XX_CHIP_FAMILY == 567 - #include <mpc55xx/fsl-mpc567x.h> - #define MPC55XX_HAS_EBI - #define MPC55XX_HAS_ESCI - #define MPC55XX_HAS_EMIOS - #define MPC55XX_HAS_FMPLL_ENHANCED - #define MPC55XX_HAS_INSTRUCTION_CACHE - #define MPC55XX_HAS_DATA_CACHE - #define MPC55XX_HAS_SIU - #define MPC55XX_HAS_WAIT_INSTRUCTION -#else - #error "unsupported chip type" -#endif - -#define MPC55XX_ZERO_FLAGS { .R = 0 } - -#endif /* LIBCPU_POWERPC_MPC55XX_REGS_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/siu.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/siu.h deleted file mode 100644 index 3495750145..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/siu.h +++ /dev/null @@ -1,313 +0,0 @@ -/** - * @file - * - * @ingroup mpc55xx - * - * @brief System Integration Unit Access (SIU). - */ - -/* - * Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBCPU_POWERPC_MPC55XX_SIU_H -#define LIBCPU_POWERPC_MPC55XX_SIU_H - -#include <rtems.h> - -#include <mpc55xx/regs.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -typedef enum { - #if MPC55XX_CHIP_FAMILY == 567 - PCR_MDO4_GPIO75 = 75, - PCR_MDO5_GPIO76 = 76, - PCR_MDO6_GPIO77 = 77, - PCR_MDO7_GPIO78 = 78, - PCR_MDO8_GPIO79 = 79, - PCR_MDO9_GPIO80 = 80, - PCR_MDO10_GPIO81 = 81, - PCR_MDO11_GPIO82 = 82, - PCR_CNTXA_TXDA_GPIO83 = 83, - PCR_CNRXA_RXDA_GPIO84 = 84, - PCR_CNTXB_PCSC3_GPIO85 = 85, - PCR_CNRXB_PCSC4_GPIO86 = 86, - PCR_CNTXC_PCSD3_GPIO87 = 87, - PCR_CNRXC_PCSD4_GPIO88 = 88, - PCR_TXDA_GPIO89 = 89, - PCR_RXDA_GPIO90 = 90, - PCR_TXDB_PCSD1_GPIO91 = 91, - PCR_RXDB_PCSD5_GPIO92 = 92, - PCR_SCKA_PCSC1_GPIO93 = 93, - PCR_SINA_PCSC2_GPIO94 = 94, - PCR_SOUTA_PCSC5_GPIO95 = 95, - PCR_PCSA0_PCSD2_GPIO96 = 96, - PCR_PCSA1_GPIO97 = 97, - PCR_PCSA2_GPIO98 = 98, - PCR_PCSA3_GPIO99 = 99, - PCR_PCSA4_GPIO100 = 100, - PCR_PCSA5_ETRIG1_GPIO101 = 101, - PCR_SCKB_GPIO102 = 102, - PCR_SINB_GPIO103 = 103, - PCR_SOUTB_GPIO104 = 104, - PCR_PCSB0_PCSD2_GPIO105 = 105, - PCR_PCSB1_PCSD0_GPIO106 = 106, - PCR_PCSB2_SOUTC_GPIO107 = 107, - PCR_PCSB3_SINC_GPIO108 = 108, - PCR_PCSB4_SCKC_GPIO109 = 109, - PCR_PCSB5_PCSC0_GPIO110 = 110, - PCR_TCRCLKA_IRQ7_GPIO113 = 113, - PCR_ETPUA0_ETPUA12_GPIO114 = 114, - PCR_ETPUA1_ETPUA13_GPIO115 = 115, - PCR_ETPUA2_ETPUA14_GPIO116 = 116, - PCR_ETPUA3_ETPUA15_GPIO117 = 117, - PCR_ETPUA4_ETPUA16_GPIO118 = 118, - PCR_ETPUA5_ETPUA17_GPIO119 = 119, - PCR_ETPUA6_ETPUA18_GPIO120 = 120, - PCR_ETPUA7_ETPUA19_GPIO121 = 121, - PCR_ETPUA8_ETPUA20_GPIO122 = 122, - PCR_ETPUA9_ETPUA21_GPIO123 = 123, - PCR_ETPUA10_ETPUA22_GPIO124 = 124, - PCR_ETPUA11_ETPUA23_GPIO125 = 125, - PCR_ETPUA12_PCSB1_GPIO126 = 126, - PCR_ETPUA13_PCSB3_GPIO127 = 127, - PCR_ETPUA14_PCSB4_GPIO128 = 128, - PCR_ETPUA15_PCSB5_GPIO129 = 129, - PCR_ETPUA16_PCSD1_GPIO130 = 130, - PCR_ETPUA17_PCSD2_GPIO131 = 131, - PCR_ETPUA18_PCSD3_GPIO132 = 132, - PCR_ETPUA19_PCSD4_GPIO133 = 133, - PCR_ETPUA20_IRQ8_GPIO134 = 134, - PCR_ETPUA21_IRQ9_GPIO135 = 135, - PCR_ETPUA22_IRQ10_GPIO136 = 136, - PCR_ETPUA23_IRQ11_GPIO137 = 137, - PCR_ETPUA24_IRQ12_GPIO138 = 138, - PCR_ETPUA25_IRQ13_GPIO139 = 139, - PCR_ETPUA26_IRQ14_GPIO140 = 140, - PCR_ETPUA27_IRQ15_GPIO141 = 141, - PCR_ETPUA28_PCSC1_GPIO142 = 142, - PCR_ETPUA29_PCSC2_GPIO143 = 143, - PCR_ETPUA30_PCSC3_GPIO144 = 144, - PCR_ETPUA31_PCSC4_GPIO145 = 145, - PCR_TCRCLKB_IRQ6_GPIO146 = 146, - PCR_ETPUB0_ETPUB16_GPIO147 = 147, - PCR_ETPUB1_ETPUB17_GPIO148 = 148, - PCR_ETPUB2_ETPUB18_GPIO149 = 149, - PCR_ETPUB3_ETPUB19_GPIO150 = 150, - PCR_ETPUB4_ETPUB20_GPIO151 = 151, - PCR_ETPUB5_ETPUB21_GPIO152 = 152, - PCR_ETPUB6_ETPUB22_GPIO153 = 153, - PCR_ETPUB7_ETPUB23_GPIO154 = 154, - PCR_ETPUB8_ETPUB24_GPIO155 = 155, - PCR_ETPUB9_ETPUB25_GPIO156 = 156, - PCR_ETPUB10_ETPUB26_GPIO157 = 157, - PCR_ETPUB11_ETPUB27_GPIO158 = 158, - PCR_ETPUB12_ETPUB28_GPIO159 = 159, - PCR_ETPUB13_ETPUB29_GPIO160 = 160, - PCR_ETPUB14_ETPUB30_GPIO161 = 161, - PCR_ETPUB15_ETPUB31_GPIO162 = 162, - PCR_ETPUB16_PCSA1_GPIO163 = 163, - PCR_ETPUB17_PCSA2_GPIO164 = 164, - PCR_ETPUB18_PCSA3_GPIO165 = 165, - PCR_ETPUB19_PCSA4_GPIO166 = 166, - PCR_ETPUB20_GPIO167 = 167, - PCR_ETPUB21_GPIO168 = 168, - PCR_ETPUB22_GPIO169 = 169, - PCR_ETPUB23_GPIO170 = 170, - PCR_ETPUB24_GPIO171 = 171, - PCR_ETPUB25_GPIO172 = 172, - PCR_ETPUB26_GPIO173 = 173, - PCR_ETPUB27_GPIO174 = 174, - PCR_ETPUB28_GPIO175 = 175, - PCR_ETPUB29_GPIO176 = 176, - PCR_ETPUB30_GPIO177 = 177, - PCR_ETPUB31_GPIO178 = 178, - PCR_EMIOS0_ETPUA0_GPIO179 = 179, - PCR_EMIOS1_ETPUA1_GPIO180 = 180, - PCR_EMIOS2_ETPUA2_GPIO181 = 181, - PCR_EMIOS3_ETPUA3_GPIO182 = 182, - PCR_EMIOS4_ETPUA4_GPIO183 = 183, - PCR_EMIOS5_ETPUA5_GPIO184 = 184, - PCR_EMIOS6_ETPUA6_GPIO185 = 185, - PCR_EMIOS7_ETPUA7_GPIO186 = 186, - PCR_EMIOS8_ETPUA8_GPIO187 = 187, - PCR_EMIOS9_ETPUA9_GPIO188 = 188, - PCR_EMIOS10_SCKD_GPIO189 = 189, - PCR_EMIOS11_SIND_GPIO190 = 190, - PCR_EMIOS12_SOUTC_GPIO191 = 191, - PCR_EMIOS13_SOUTD_GPIO192 = 192, - PCR_EMIOS14_IRQ0_GPIO193 = 193, - PCR_EMIOS15_IRQ1_GPIO194 = 194, - PCR_EMIOS16_ETPUB0_GPIO195 = 195, - PCR_EMIOS17_ETPUB1_GPIO196 = 196, - PCR_EMIOS18_ETPUB2_GPIO197 = 197, - PCR_EMIOS19_ETPUB3_GPIO198 = 198, - PCR_EMIOS20_ETPUB4_GPIO199 = 199, - PCR_EMIOS21_ETPUB5_GPIO200 = 200, - PCR_EMIOS22_ETPUB6_GPIO201 = 201, - PCR_EMIOS23_ETPUB7_GPIO202 = 202, - PCR_EMIOS24_PCSB0_GPIO203 = 203, - PCR_EMIOS25_PCSB1_GPIO204 = 204, - PCR_PLLCFG0_IRQ4_GPIO208 = 208, - PCR_PLLCFG1_IRQ5_GPIO209 = 209, - PCR_BOOTCFG0_IRQ2_GPIO211 = 211, - PCR_BOOTCFG1_IRQ3_GPIO212 = 212, - PCR_WKPCFG_NMI_GPIO213 = 213, - PCR_ENGCLK = 214, - PCR_MCKO = 219, - PCR_MDO0_GPIO220 = 220, - PCR_MDO1_GPIO221 = 221, - PCR_MDO2_GPIO222 = 222, - PCR_MDO3_GPIO223 = 223, - PCR_MSEO0 = 224, - PCR_MSEO1 = 225, - PCR_RDY = 226, - PCR_TDO = 228, - PCR_D_CLKOUT = 229, - PCR_RSTOUT = 230, - PCR_MDO12_GPIO231 = 231, - PCR_MDO13_GPIO232 = 232, - PCR_MDO14_GPIO233 = 233, - PCR_MDO15_GPIO234 = 234, - PCR_SCKC_SCK_C_LVDSP_GPIO235 = 235, - PCR_SINC_SCK_C_LVDSM_GPIO236 = 236, - PCR_SOUTC_SOUT_C_LVDSP_GPIO237 = 237, - PCR_PCSC0_SOUT_C_LVDSM_GPIO238 = 238, - PCR_PCSC1_GPIO239 = 239, - PCR_PCSC2_GPIO240 = 240, - PCR_PCSC3_GPIO241 = 241, - PCR_PCSC4_GPIO242 = 242, - PCR_PCSC5_GPIO243 = 243, - PCR_TXDC_ETRIG0_GPIO244 = 244, - PCR_RXDC_GPIO245 = 245, - PCR_CNTXD_GPIO246 = 246, - PCR_CNRXD_GPIO247 = 247, - PCR_FR_A_TX_GPIO248 = 248, - PCR_FR_A_RX_GPIO249 = 249, - PCR_FR_A_TX_EN_GPIO250 = 250, - PCR_FR_B_TX_GPIO251 = 251, - PCR_FR_B_RX_GPIO252 = 252, - PCR_FR_B_TX_EN_GPIO253 = 253, - PCR_D_CS0_GPIO256 = 256, - PCR_D_CS2_D_ADD_DAT31_GPIO257 = 257, - PCR_D_CS3_D_TEA_GPIO258 = 258, - PCR_D_ADD12_GPIO259 = 259, - PCR_D_ADD13_GPIO260 = 260, - PCR_D_ADD14_GPIO261 = 261, - PCR_D_ADD15_GPIO262 = 262, - PCR_D_ADD16_D_ADD_DAT16_GPIO263 = 263, - PCR_D_ADD17_D_ADD_DAT17_GPIO264 = 264, - PCR_D_ADD18_D_ADD_DAT18_GPIO265 = 265, - PCR_D_ADD19_D_ADD_DAT19_GPIO266 = 266, - PCR_D_ADD20_D_ADD_DAT20_GPIO267 = 267, - PCR_D_ADD21_D_ADD_DAT21_GPIO268 = 268, - PCR_D_ADD22_D_ADD_DAT22_GPIO269 = 269, - PCR_D_ADD23_D_ADD_DAT23_GPIO270 = 270, - PCR_D_ADD24_D_ADD_DAT24_GPIO271 = 271, - PCR_D_ADD25_D_ADD_DAT25_GPIO272 = 272, - PCR_D_ADD26_D_ADD_DAT26_GPIO273 = 273, - PCR_D_ADD27_D_ADD_DAT27_GPIO274 = 274, - PCR_D_ADD28_D_ADD_DAT28_GPIO275 = 275, - PCR_D_ADD29_D_ADD_DAT29_GPIO276 = 276, - PCR_D_ADD30_D_ADD_DAT30_GPIO277 = 277, - PCR_D_ADD_DAT0_GPIO278 = 278, - PCR_D_ADD_DAT1_GPIO279 = 279, - PCR_D_ADD_DAT2_GPIO280 = 280, - PCR_D_ADD_DAT3_GPIO281 = 281, - PCR_D_ADD_DAT4_GPIO282 = 282, - PCR_D_ADD_DAT5_GPIO283 = 283, - PCR_D_ADD_DAT6_GPIO284 = 284, - PCR_D_ADD_DAT7_GPIO285 = 285, - PCR_D_ADD_DAT8_GPIO286 = 286, - PCR_D_ADD_DAT9_GPIO287 = 287, - PCR_D_ADD_DAT10_GPIO288 = 288, - PCR_D_ADD_DAT11_GPIO289 = 289, - PCR_D_ADD_DAT12_GPIO290 = 290, - PCR_D_ADD_DAT13_GPIO291 = 291, - PCR_D_ADD_DAT14_GPIO292 = 292, - PCR_D_ADD_DAT15_GPIO293 = 293, - PCR_D_RD_WR_GPIO294 = 294, - PCR_D_WE0_GPIO295 = 295, - PCR_D_WE1_GPIO296 = 296, - PCR_D_OE_GPIO297 = 297, - PCR_D_TS_GPIO298 = 298, - PCR_D_ALE_GPIO299 = 299, - PCR_D_TA_GPIO300 = 300, - PCR_D_CS1_GPIO301 = 301, - PCR_D_BDIP_GPIO302 = 302, - PCR_D_WE2_GPIO303 = 303, - PCR_D_WE3_GPIO304 = 304, - PCR_D_ADD9_GPIO305 = 305, - PCR_D_ADD10_GPIO306 = 306, - PCR_D_ADD11_GPIO307 = 307, - PCR_EMIOS26_PCSB2_GPIO432 = 432, - PCR_EMIOS27_PCSB3_GPIO433 = 433, - PCR_EMIOS28_PCSC0_GPIO434 = 434, - PCR_EMIOS29_PCSC1_GPIO435 = 435, - PCR_EMIOS30_PCSC2_GPIO436 = 436, - PCR_EMIOS31_PCSC5_GPIO437 = 437, - PCR_TCRCLKC_GPIO440 = 440, - PCR_ETPUC0_GPIO441 = 441, - PCR_ETPUC1_GPIO442 = 442, - PCR_ETPUC2_GPIO443 = 443, - PCR_ETPUC3_GPIO444 = 444, - PCR_ETPUC4_GPIO445 = 445, - PCR_ETPUC5_GPIO446 = 446, - PCR_ETPUC6_GPIO447 = 447, - PCR_ETPUC7_GPIO448 = 448, - PCR_ETPUC8_GPIO449 = 449, - PCR_ETPUC9_IRQ0_GPIO450 = 450, - PCR_ETPUC10__IRQ1_GPIO451 = 451, - PCR_ETPUC11_IRQ2_GPIO452 = 452, - PCR_ETPUC12_IRQ3_GPIO453 = 453, - PCR_ETPUC13_3_IRQ4_GPIO454 = 454, - PCR_ETPUC14_4_IRQ5_GPIO455 = 455, - PCR_ETPUC15__GPIO456 = 456, - PCR_ETPUC16_FR_A_TX_GPIO457 = 457, - PCR_ETPUC17_FR_A_RX_GPIO458 = 458, - PCR_ETPUC18_FR_A_TX_EN_GPIO459 = 459, - PCR_ETPUC19_TXDA_GPIO460 = 460, - PCR_ETPUC20_RXDA_GPIO461 = 461, - PCR_ETPUC21_TXDB_GPIO462 = 462, - PCR_ETPUC22_RXDB_GPIO463 = 463, - PCR_ETPUC23_PCSD5_GPIO464 = 464, - PCR_ETPUC24_PCSD4_GPIO465 = 465, - PCR_ETPUC25_PCSD3_GPIO466 = 466, - PCR_ETPUC26_PCSD2_GPIO467 = 467, - PCR_ETPUC27_PCSD1_GPIO468 = 468, - PCR_ETPUC28_PCSD0_GPIO469 = 469, - PCR_ETPUC29_SCKD_GPIO470 = 470, - PCR_ETPUC30_SOUTD_GPIO471 = 471, - PCR_ETPUC31_SIND_GPIO472 = 472 - #else - PCR_TODO - #endif -} pcr_index; - -typedef struct mpc55xx_siu_pcr_entry { - uint16_t pcr_idx; /* first PCR index for this entry */ - uint16_t pcr_cnt; /* PCR count using this entry */ - union SIU_PCR_tag pcr_val; /* value to write to the PCR[idx++val] */ -} mpc55xx_siu_pcr_entry_t; - -rtems_status_code mpc55xx_siu_pcr_init(volatile struct SIU_tag *siu, - const mpc55xx_siu_pcr_entry_t *pcr_entry); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBCPU_POWERPC_MPC55XX_SIU_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/watchdog.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/watchdog.h deleted file mode 100644 index d5a8af794e..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/watchdog.h +++ /dev/null @@ -1,68 +0,0 @@ -/** - * @file - * - * @ingroup mpc55xx - * - * @brief Header file for the watchdog timer. - */ - -/* - * Copyright (c) 2008 - * Embedded Brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * rtems@embedded-brains.de - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBCPU_POWERPC_MPC55XX_WATCHDOG_H -#define LIBCPU_POWERPC_MPC55XX_WATCHDOG_H - -#include <stdbool.h> - -#include <rtems.h> - -#include <libcpu/powerpc-utility.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -static inline void mpc55xx_watchdog_clear() -{ - PPC_SET_SPECIAL_PURPOSE_REGISTER( BOOKE_TSR, BOOKE_TSR_WIS); -} - -static inline void mpc55xx_watchdog_enable_interrupt( bool enable) -{ - if (enable) { - PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( BOOKE_TCR, BOOKE_TCR_WIE); - } else { - PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( BOOKE_TCR, BOOKE_TCR_WIE); - } -} - -static inline rtems_status_code mpc55xx_watchdog_set_time_base_bit( uint32_t bit) -{ - if (bit > 63) { - return RTEMS_INVALID_NUMBER; - } - - PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED( - BOOKE_TCR, - BOOKE_TCR_WP( bit) | BOOKE_TCR_WPEXT( bit >> 2), - BOOKE_TCR_WP_MASK | BOOKE_TCR_WPEXT_MASK - ); - - return RTEMS_SUCCESSFUL; -} - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBCPU_POWERPC_MPC55XX_WATCHDOG_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h b/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h deleted file mode 100644 index dd0c483b0d..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * raw_execption.h - * - * This file contains implementation of C function to - * Instantiate mpc5xx primary exception entries. - * More detailled information can be found on the Motorola - * site and more precisely in the following book: - * - * MPC555/MPC556 User's Manual - * Motorola REF : MPC555UM/D Rev. 3, 2000 October 15 - * - * - * MPC5xx port sponsored by Defence Research and Development Canada - Suffield - * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) - * - * Derived from libcpu/powerpc/mpc8xx/exceptions/raw_exception.h: - * - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_RAW_EXCEPTION_H -#define _LIBCPU_RAW_EXCEPTION_H - -#include <libcpu/vectors.h> - -/* - * Exception Vectors as defined in the MPC555 User's Manual - */ - -#define ASM_RESET_VECTOR 0x01 -#define ASM_MACH_VECTOR 0x02 - -#define ASM_EXT_VECTOR 0x05 -#define ASM_ALIGN_VECTOR 0x06 -#define ASM_PROG_VECTOR 0x07 -#define ASM_FLOAT_VECTOR 0x08 -#define ASM_DEC_VECTOR 0x09 - -#define ASM_SYS_VECTOR 0x0C -#define ASM_TRACE_VECTOR 0x0D -#define ASM_FLOATASSIST_VECTOR 0x0E - -#define ASM_SOFTEMUL_VECTOR 0x10 - -#define ASM_IPROT_VECTOR 0x13 -#define ASM_DPROT_VECTOR 0x14 - -#define ASM_DBREAK_VECTOR 0x1C -#define ASM_IBREAK_VECTOR 0x1D -#define ASM_MEBREAK_VECTOR 0x1E -#define ASM_NMEBREAK_VECTOR 0x1F - -#define LAST_VALID_EXC ASM_NMEBREAK_VECTOR - -#ifndef ASM - -/* - * Type definition for raw exceptions. - */ - -typedef unsigned char rtems_vector; -struct __rtems_raw_except_connect_data__; -typedef unsigned char rtems_raw_except_hdl_size; - -typedef struct { - rtems_vector vector; - rtems_exception_handler_t* raw_hdl; -}rtems_raw_except_hdl; - -typedef void (*rtems_raw_except_enable) (const struct __rtems_raw_except_connect_data__*); -typedef void (*rtems_raw_except_disable) (const struct __rtems_raw_except_connect_data__*); -typedef int (*rtems_raw_except_is_enabled) (const struct __rtems_raw_except_connect_data__*); - -typedef struct __rtems_raw_except_connect_data__{ - /* - * Exception vector (As defined in the manual) - */ - rtems_vector exceptIndex; - /* - * Exception raw handler. See comment on handler properties below in function prototype. - */ - rtems_raw_except_hdl hdl; - /* - * function for enabling raw exceptions. In order to be consistent - * with the fact that the raw connexion can defined in the - * libcpu library, this library should have no knowledge of - * board specific hardware to manage exceptions and thus the - * "on" routine must enable the except at processor level only. - * - */ - rtems_raw_except_enable on; - /* - * function for disabling raw exceptions. In order to be consistent - * with the fact that the raw connexion can defined in the - * libcpu library, this library should have no knowledge of - * board specific hardware to manage exceptions and thus the - * "on" routine must disable the except both at device and PIC level. - * - */ - rtems_raw_except_disable off; - /* - * function enabling to know what exception may currently occur - */ - rtems_raw_except_is_enabled isOn; -}rtems_raw_except_connect_data; - -typedef struct { - /* - * size of all the table fields (*Tbl) described below. - */ - unsigned int exceptSize; - /* - * Default handler used when disconnecting exceptions. - */ - rtems_raw_except_connect_data defaultRawEntry; - /* - * Table containing initials/current value. - */ - rtems_raw_except_connect_data* rawExceptHdlTbl; -}rtems_raw_except_global_settings; - -/* - * C callable function enabling to set up one raw idt entry - */ -extern int mpc5xx_set_exception (const rtems_raw_except_connect_data*); - -/* - * C callable function enabling to get one current raw idt entry - */ -extern int mpc5xx_get_current_exception (rtems_raw_except_connect_data*); - -/* - * C callable function enabling to remove one current raw idt entry - */ -extern int mpc5xx_delete_exception (const rtems_raw_except_connect_data*); - -/* - * C callable function enabling to check if vector is valid - */ -extern int mpc5xx_vector_is_valid(rtems_vector vector); - -inline static void* mpc5xx_get_vector_addr(rtems_vector vector) -{ - return ((void*) (((unsigned) vector) << 8)); -} -/* - * Exception global init. - */ -extern int mpc5xx_init_exceptions (rtems_raw_except_global_settings* config); -extern int mpc5xx_get_exception_config (rtems_raw_except_global_settings** config); - -# endif /* ASM */ - -#define SIZEOF_ - -#endif diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h b/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h deleted file mode 100644 index c0633af938..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Console declarations - * - * - * MPC5xx port sponsored by Defence Research and Development Canada - Suffield - * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _MPC5XX_CONSOLE_H -#define _MPC5XX_CONSOLE_H - -#include <rtems/libio.h> -#include <rtems/termiostypes.h> - -void m5xx_uart_initialize(int minor); - -/* Termios callbacks */ -int m5xx_uart_firstOpen(int maj, int min, void *arg); -int m5xx_uart_lastClose(int maj, int min, void *arg); -int m5xx_uart_pollRead(int minor); -ssize_t m5xx_uart_pollWrite(int minor, const char* buf, size_t len); -ssize_t m5xx_uart_write (int minor, const char *buf, size_t len); -int m5xx_uart_setAttributes(int, const struct termios* t); - -#define NUM_PORTS 2 /* number of serial ports */ - -#define SCI1_MINOR 0 -#define SCI2_MINOR 1 - -#endif /* _MPC5XX_CONSOLE_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h b/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h deleted file mode 100644 index fc9b756cbf..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h +++ /dev/null @@ -1,626 +0,0 @@ -/* - * - * MPC5xx Internal I/O Definitions - */ - -/* - * MPC5xx port sponsored by Defence Research and Development Canada - Suffield - * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) - * - * Derived from c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h: - * - * Submitted By: * - * * - * W. Eric Norum * - * Saskatchewan Accelerator Laboratory * - * University of Saskatchewan * - * 107 North Road * - * Saskatoon, Saskatchewan, CANADA * - * S7N 5C6 * - * * - * eric@skatter.usask.ca * - * * - * Modified for use with the MPC860 (original code was for MC68360) * - * by * - * Jay Monkman * - * Frasca International, Inc. * - * 906 E. Airport Rd. * - * Urbana, IL, 61801 * - * * - * jmonkman@frasca.com * - * * - * Modified further for use with the MPC821 by: * - * Andrew Bray <andy@chaos.org.uk> * - * * - * With some corrections/additions by: * - * Darlene A. Stewart and * - * Charles-Antoine Gauthier * - * Institute for Information Technology * - * National Research Council of Canada * - * Ottawa, ON K1A 0R6 * - * * - * Darlene.Stewart@iit.nrc.ca * - * charles.gauthier@iit.nrc.ca * - * * - * Corrections/additions: * - * Copyright (c) 1999, National Research Council of Canada * - * - * MPC5xx port sponsored by Defence Research and Development Canada - Suffield - * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _MPC5XX_H -#define _MPC5XX_H - -#include <libcpu/spr.h> - - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Macros for accessing Special Purpose Registers (SPRs) - */ - -#define _eieio __asm__ volatile ("eieio\n"::) -#define _sync __asm__ volatile ("sync\n"::) -#define _isync __asm__ volatile ("isync\n"::) - -/* - * Core Registers (SPRs) - */ -#define DER 149 /* Debug Enable Register */ -#define IMMR 638 /* Internal Memory Map Register */ -#define IMMR_FLEN (1<<11) /* Internal flash ROM enabled */ - -/* - * Interrupt Control Registers (SPRs) - */ -#define EIE 80 /* External Interrupt Enable Register */ -#define EID 81 /* External Interrupt Disable Register */ -#define NRI 82 /* Non-Recoverable Interrupt Register */ - -#define ECR 148 /* Exception Cause Register */ - -/* - * Bus Control Registers (SPRs) - */ -#define LCTRL1 156 /* L-Bus Support Control Register 1 */ -#define LCTRL2 157 /* L-Bus Support Control Register 2 */ -#define ICTRL 158 /* I-Bus Support Control Register */ - -/* - * Burst Buffer Control Registers (SPRs) - */ -#define BBCMCR 560 /* Burst Buffer Configuration Register */ -#define BBCMCR_BE (1<<13) /* Burst enable */ -#define BBCMCR_ETRE (1<<12) /* Exception table relocation enable */ - -#define MI_RBA0 784 /* Region 0 Address Register */ -#define MI_RBA1 785 /* Region 1 Address Register */ -#define MI_RBA2 786 /* Region 2 Address Register */ -#define MI_RBA3 787 /* Region 3 Address Register */ - -#define MI_RA0 816 /* Region 0 Attribute Register */ -#define MI_RA1 817 /* Region 1 Attribute Register */ -#define MI_RA2 818 /* Region 2 Attribute Register */ -#define MI_RA3 819 /* Region 3 Attribute Register */ -#define MI_GRA 528 /* Region Global Attribute Register */ -#define MI_RA_PP (3 << 10) /* Protection bits: */ -#define MI_RA_PP_SUPV (1 << 10) /* Supervisor */ -#define MI_RA_PP_USER (2 << 10) /* User */ -#define MI_RA_G (1 << 6) /* Guarded region */ - - -/* - * L-Bus to U-Bus Interface (L2U) Registers (SPRs) - */ -#define L2U_MCR 568 /* L2U Module Configuration Register */ - -#define L2U_RBA0 792 /* L2U Region 0 Address Register */ -#define L2U_RBA1 793 /* L2U Region 1 Address Register */ -#define L2U_RBA2 794 /* L2U Region 2 Address Register */ -#define L2U_RBA3 795 /* L2U Region 3 Address Register */ - -#define L2U_RA0 824 /* L2U Region 0 Attribute Register */ -#define L2U_RA1 825 /* L2U Region 1 Attribute Register */ -#define L2U_RA2 826 /* L2U Region 2 Attribute Register */ -#define L2U_RA3 827 /* L2U Region 3 Attribute Register */ -#define L2U_GRA 536 /* L2U Global Region Attribute Register */ -#define L2U_RA_PP (3 << 10) /* Protection bits: */ -#define L2U_RA_PP_SUPV (1 << 10) /* Supervisor */ -#define L2U_RA_PP_USER (2 << 10) /* User */ -#define L2U_RA_G (1 << 6) /* Guarded region */ - - -/* - ************************************************************************* - * REGISTER SUBBLOCKS * - ************************************************************************* - */ - -/* - ************************************************************************* - * System Protection Control Register (SYPCR) * - ************************************************************************* - */ -#define USIU_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ -#define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ -#define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */ -#define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */ -#define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */ -#define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ -#define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */ - -#define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ -#define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */ -#define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */ -#define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */ -#define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ -#define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */ - -/* - ************************************************************************* - * Software Service Register (SWSR) * - ************************************************************************* - */ -#define TICKLE_WATCHDOG() \ -do { \ - usiu.swsr = 0x556C; \ - usiu.swsr = 0xAA39; \ -} while (0) \ - -/* - ************************************************************************* - * Memory Control Registers * - ************************************************************************* - */ -#define USIU_MEMC_BR_BA(x) (((uint32_t)x)&0xffff8000) - /* Base address */ -#define USIU_MEMC_BR_AT(x) ((x)<<12) /* Address type */ -#define USIU_MEMC_BR_PS8 (1<<10) /* 8 bit port */ -#define USIU_MEMC_BR_PS16 (2<<10) /* 16 bit port */ -#define USIU_MEMC_BR_PS32 (0<<10) /* 32 bit port */ -#define USIU_MEMC_BR_WP (1<<8) /* Write protect */ -#define USIU_MEMC_BR_WEBS (1<<5) /* Write enable/byte select */ -#define USIU_MEMC_BR_TBDIP (1<<4) /* Toggle-Burst data in progress*/ -#define USIU_MEMC_BR_LBDIP (1<<3) /* Late-burst data in progress */ -#define USIU_MEMC_BR_SETA (1<<2) /* External transfer acknowledge */ -#define USIU_MEMC_BR_BI (1<<1) /* Burst inhibit */ -#define USIU_MEMC_BR_V (1<<0) /* Base/Option register are valid */ - -#define USIU_MEMC_OR_32K 0xffff8000 /* Address range */ -#define USIU_MEMC_OR_64K 0xffff0000 -#define USIU_MEMC_OR_128K 0xfffe0000 -#define USIU_MEMC_OR_256K 0xfffc0000 -#define USIU_MEMC_OR_512K 0xfff80000 -#define USIU_MEMC_OR_1M 0xfff00000 -#define USIU_MEMC_OR_2M 0xffe00000 -#define USIU_MEMC_OR_4M 0xffc00000 -#define USIU_MEMC_OR_8M 0xff800000 -#define USIU_MEMC_OR_16M 0xff000000 -#define USIU_MEMC_OR_32M 0xfe000000 -#define USIU_MEMC_OR_64M 0xfc000000 -#define USIU_MEMC_OR_128 0xf8000000 -#define USIU_MEMC_OR_256M 0xf0000000 -#define USIU_MEMC_OR_512M 0xe0000000 -#define USIU_MEMC_OR_1G 0xc0000000 -#define USIU_MEMC_OR_2G 0x80000000 -#define USIU_MEMC_OR_4G 0x00000000 -#define USIU_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ -#define USIU_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ -#define USIU_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ -#define USIU_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ -#define USIU_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ -#define USIU_MEMC_OR_ETHR (1<<8) /* Extended hold time on reads */ -#define USIU_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ -#define USIU_MEMC_OR_BSCY(x) ((x)<<1) /* Burst beat length in clocks */ -#define USIU_MEMC_OR_TRLX (1<<0) /* Relaxed timing in GPCM */ - -/* - ************************************************************************* - * Clocks and Reset Controlmer * - ************************************************************************* - */ - -#define USIU_SCCR_DBCT (1<<31) /* Disable backup clock for timers */ -#define USIU_SCCR_COM(x) ((x)<<29) /* Clock output mode */ -#define USIU_SCCR_RTDIV (1<<24) /* RTC, PIT divide by 256, not 4 */ -#define USIU_PRQEN (1<<21) /* MSR[POW] controls frequency */ -#define USIU_SCCR_EBDF(x) ((x)<<17) /* External bus division factor */ -#define USIU_LME (1<<16) /* Enable limp mode */ -#define USIU_ENGDIV(x) ((x)<<9) /* Set engineering clock divisor */ - -#define USIU_PLPRCR_MF(x) (((x)-1)<<20) /* PLL mult. factor (true) */ -#define USIU_PLPRCR_SPLS (1<<16) /* System PLL locked */ -#define USIU_PLPRCR_TEXPS (1<<14) /* Assert TEXP always */ - -/* - ************************************************************************* - * Programmable Interval Timer * - ************************************************************************* - */ -#define USIU_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */ -#define USIU_PISCR_PS (1<<7) /* PIT Interrupt state */ -#define USIU_PISCR_PIE (1<<2) /* PIT interrupt enable */ -#define USIU_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */ -#define USIU_PISCR_PTE (1<<0) /* PIT enable */ - -/* - ************************************************************************* - * Time Base * - ************************************************************************* - */ -#define USIU_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ -#define USIU_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ -#define USIU_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ -#define USIU_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ -#define USIU_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ -#define USIU_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ -#define USIU_TBSCR_TBE (1<<0) /* enable TB and decrementer */ - -/* - ************************************************************************* - * SIU Interrupt Mask * - ************************************************************************* - */ -#define USIU_SIMASK_IRM0 (1<<31) -#define USIU_SIMASK_LVM0 (1<<30) -#define USIU_SIMASK_IRM1 (1<<29) -#define USIU_SIMASK_LVM1 (1<<28) -#define USIU_SIMASK_IRM2 (1<<27) -#define USIU_SIMASK_LVM2 (1<<26) -#define USIU_SIMASK_IRM3 (1<<25) -#define USIU_SIMASK_LVM3 (1<<24) -#define USIU_SIMASK_IRM4 (1<<23) -#define USIU_SIMASK_LVM4 (1<<22) -#define USIU_SIMASK_IRM5 (1<<21) -#define USIU_SIMASK_LVM5 (1<<20) -#define USIU_SIMASK_IRM6 (1<<19) -#define USIU_SIMASK_LVM6 (1<<18) -#define USIU_SIMASK_IRM7 (1<<17) -#define USIU_SIMASK_LVM7 (1<<16) - -/* - ************************************************************************* - * SIU Module Control * - ************************************************************************* - */ -#define USIU_SIUMCR_EARB (1<<31) -#define USIU_SIUMCR_EARP0 (0<<28) -#define USIU_SIUMCR_EARP1 (1<<28) -#define USIU_SIUMCR_EARP2 (2<<28) -#define USIU_SIUMCR_EARP3 (3<<28) -#define USIU_SIUMCR_EARP4 (4<<28) -#define USIU_SIUMCR_EARP5 (5<<28) -#define USIU_SIUMCR_EARP6 (6<<28) -#define USIU_SIUMCR_EARP7 (7<<28) -#define USIU_SIUMCR_DSHW (1<<23) -#define USIU_SIUMCR_DBGC0 (0<<21) -#define USIU_SIUMCR_DBGC1 (1<<21) -#define USIU_SIUMCR_DBGC2 (2<<21) -#define USIU_SIUMCR_DBGC3 (3<<21) -#define USIU_SIUMCR_DBPC (1<<20) -#define USIU_SIUMCR_ATWC (1<<19) -#define USIU_SIUMCR_GPC0 (0<<17) -#define USIU_SIUMCR_GPC1 (1<<17) -#define USIU_SIUMCR_GPC2 (2<<17) -#define USIU_SIUMCR_GPC3 (3<<17) -#define USIU_SIUMCR_DLK (1<<16) -#define USIU_SIUMCR_SC0 (0<<13) -#define USIU_SIUMCR_SC1 (1<<13) -#define USIU_SIUMCR_SC2 (2<<13) -#define USIU_SIUMCR_SC3 (3<<13) -#define USIU_SIUMCR_RCTX (1<<12) -#define USIU_SIUMCR_MLRC0 (0<<10) -#define USIU_SIUMCR_MLRC1 (1<<10) -#define USIU_SIUMCR_MLRC2 (2<<10) -#define USIU_SIUMCR_MLRC3 (3<<10) -#define USIU_SIUMCR_MTSC (1<<7) - -/* - * Value to write to a key register to unlock the corresponding SIU register - */ -#define USIU_UNLOCK_KEY 0x55CCAA33 - -/* - ************************************************************************* - * UIMB Module Control * - ************************************************************************* - */ -#define UIMB_UMCR_STOP (1<<31) -#define UIMB_UMCR_IRQMUX(x) ((x)<<29) -#define UIMB_UMCR_HSPEED (1<<28) - -/* - ************************************************************************* - * QSMCM Serial Communications Interface (SCI) * - ************************************************************************* - */ - - -#define QSMCM_ILDSCI(x) ((x)<<8) /* SCI interrupt level */ - -#define QSMCM_SCI_BAUD(x) ((x)&0x1FFF) /* Baud rate field */ - -#define QSMCM_SCI_LOOPS (1<<14) /* Loopback test mode */ -#define QSMCM_SCI_WOMS (1<<13) /* Wire-or mode select */ -#define QSMCM_SCI_ILT (1<<12) /* Idle-line detect type */ -#define QSMCM_SCI_PT (1<<11) /* Parity type */ -#define QSMCM_SCI_PE (1<<10) /* Parity enable */ -#define QSMCM_SCI_M (1<<9) /* 11-bit mode */ -#define QSMCM_SCI_WAKE (1<<8) /* Wakeup mode */ - -#define QSMCM_SCI_TIE (1<<7) /* Transmitter interrupt enable */ -#define QSMCM_SCI_TCIE (1<<6) /* Transmit complete intr. enable */ -#define QSMCM_SCI_RIE (1<<5) /* Receiver interrupt enable */ -#define QSMCM_SCI_ILIE (1<<4) /* Idle line interrupt enable */ -#define QSMCM_SCI_TE (1<<3) /* Transmitter enable */ -#define QSMCM_SCI_RE (1<<2) /* Receiver enable */ -#define QSMCM_SCI_RWU (1<<1) /* Receiver wake-up enable */ -#define QSMCM_SCI_SBK (1<<0) /* Send break */ - -#define QSMCM_SCI_TDRE (1<<8) /* Transmit data register empty */ -#define QSMCM_SCI_TC (1<<7) /* Transmit complete */ -#define QSMCM_SCI_RDRF (1<<6) /* Receive data register full */ -#define QSMCM_SCI_RAF (1<<5) /* Receiver active flag */ -#define QSMCM_SCI_IDLE (1<<4) /* Idle line detected */ -#define QSMCM_SCI_OR (1<<3) /* Receiver overrun error */ -#define QSMCM_SCI_NF (1<<2) /* Receiver noise error flag */ -#define QSMCM_SCI_FE (1<<1) /* Receiver framing error */ -#define QSMCM_SCI_PF (1<<0) /* Receiver parity error */ - -/* - ************************************************************************* - * Unified System Interface Unit * - ************************************************************************* - */ - -/* - * Memory controller registers - */ -typedef struct m5xxMEMCRegisters_ { - uint32_t _br; - uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */ -} m5xxMEMCRegisters_t; - -/* - * USIU itself - */ -typedef struct usiu_ { - /* - * SIU Block - */ - uint32_t siumcr; - uint32_t sypcr; - uint32_t _pad70; - uint16_t _pad0; - uint16_t swsr; - uint32_t sipend; - uint32_t simask; - uint32_t siel; - uint32_t sivec; - uint32_t tesr; - uint32_t sgpiodt1; - uint32_t sgpiodt2; - uint32_t sgpiocr; - uint32_t emcr; - uint8_t _pad71[0x03C-0x034]; - uint32_t pdmcr; - uint8_t _pad2[0x100-0x40]; - - /* - * MEMC Block - */ - m5xxMEMCRegisters_t memc[4]; - uint8_t _pad7[0x140-0x120]; - uint32_t dmbr; - uint32_t dmor; - uint8_t _pad8[0x178-0x148]; - uint16_t mstat; - uint8_t _pad9[0x200-0x17A]; - - /* - * System integration timers - */ - uint16_t tbscr; - uint16_t _pad10; - uint32_t tbreff0; - uint32_t tbreff1; - uint8_t _pad11[0x220-0x20c]; - uint16_t rtcsc; - uint16_t _pad12; - uint32_t rtc; - uint32_t rtsec; - uint32_t rtcal; - uint32_t _pad13[4]; - uint16_t piscr; - uint16_t _pad14; - uint16_t pitc; - uint16_t _pad_14_1; - uint16_t pitr; - uint16_t _pad_14_2; - uint8_t _pad15[0x280-0x24c]; - - /* - * Clocks and Reset - */ - uint32_t sccr; - uint32_t plprcr; - uint16_t rsr; - uint16_t _pad72; - uint16_t colir; - uint16_t _pad73; - uint16_t vsrmcr; - uint8_t _pad16[0x300-0x292]; - - /* - * System integration timers keys - */ - uint32_t tbscrk; - uint32_t tbreff0k; - uint32_t tbreff1k; - uint32_t tbk; - uint32_t _pad17[4]; - uint32_t rtcsk; - uint32_t rtck; - uint32_t rtseck; - uint32_t rtcalk; - uint32_t _pad18[4]; - uint32_t piscrk; - uint32_t pitck; - uint8_t _pad19[0x380-0x348]; - - /* - * Clocks and Reset Keys - */ - uint32_t sccrk; - uint32_t plprck; - uint32_t rsrk; - uint8_t _pad20[0x400-0x38c]; -} usiu_t; - -extern volatile usiu_t usiu; /* defined in linkcmds */ - -/* - ************************************************************************* - * Inter-Module Bus and Devices * - ************************************************************************* - */ - -/* - * Dual-Port TPU RAM (DPTRAM) - */ -typedef struct m5xxDPTRAMRegisters_ { - uint8_t pad[0x4000]; /* define later */ -} m5xxDPTRAMRegisters_t; - -/* - * Time Processor Unit (TPU) - */ -typedef struct m5xxTPU3Registers_ { - uint8_t pad[0x400]; /* define later */ -} m5xxTPU3Registers_t; - -/* - * Queued A/D Converter (QADC) - */ -typedef struct m5xxQADC64Registers_ { - uint8_t pad[0x400]; /* define later */ -} m5xxQADC64Registers_t; - -/* - * Serial Communications Interface (SCI) - */ -typedef struct m5xxSCIRegisters_ { - uint16_t sccr0; - uint16_t sccr1; - uint16_t scsr; - uint16_t scdr; -} m5xxSCIRegisters_t; - -/* - * Serial Peripheral Interface (SPI) - */ -typedef struct m5xxSPIRegisters_ { - uint16_t spcr0; - uint16_t spcr1; - uint16_t spcr2; - uint8_t spcr3; - uint8_t spsr; -} m5xxSPIRegisters_t; - -/* - * Queued Serial Multi-Channel Module (QSMCM) - */ -typedef struct m5xxQSMCMRegisters_ { - uint16_t qsmcmmcr; - uint16_t qtest; - uint16_t qdsci_il; - uint16_t qspi_il; - - m5xxSCIRegisters_t sci1; - - uint8_t _pad10[0x14-0x10]; - - uint16_t portqs; - uint16_t pqspar; - m5xxSPIRegisters_t spi; - - m5xxSCIRegisters_t sci2; - - uint16_t qsci1cr; - uint16_t qsci1sr; - uint16_t sctq[0x10]; - uint16_t scrq[0x10]; - - uint8_t _pad6C[0x140-0x06C]; - - uint16_t recram[0x20]; - uint16_t tranram[0x20]; - uint16_t comdram[0x20]; -} m5xxQSMCMRegisters_t; - -/* - * Modular Input/Output System (MIOS) - */ -typedef struct m5xxMIOS1Registers_ { - uint8_t pad[0x1000]; /* define later */ -} m5xxMIOS1Registers_t; - -/* - * Can 2.0B Controller (TouCAN) - */ -typedef struct m5xxTouCANRegisters_ { - uint8_t pad[0x400]; /* define later */ -} m5xxTouCANRegisters_t; - -/* - * U-Bus to IMB3 Bus Interface Module (UIMB) - */ -typedef struct m5xxUIMBRegisters_ { - uint32_t umcr; - uint32_t utstcreg; - uint32_t uipend; -} m5xxUIMBRegisters_t; - -/* - * IMB itself - */ -typedef struct imb_ { - m5xxDPTRAMRegisters_t dptram; - m5xxTPU3Registers_t tpu[2]; - m5xxQADC64Registers_t qadc[2]; - m5xxQSMCMRegisters_t qsmcm; - uint8_t _pad5200[0x6000-0x5200]; - m5xxMIOS1Registers_t mios; - m5xxTouCANRegisters_t toucan[2]; - uint8_t _pad7800[0x7F80-0x7800]; - m5xxUIMBRegisters_t uimb; -} imb_t; - -extern volatile imb_t imb; /* defined in linkcmds */ - - -/* - * Methods shared across libcpu and the BSP. - */ -void clockOn(void* unused); -void clockOff(void* unused); -int clockIsOn(void* unused); -rtems_isr Clock_isr(rtems_vector_number vector); - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _MPC5XX_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h deleted file mode 100644 index ab06041d24..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * irq.h - * - * This include file describe the data structure and the functions implemented - * by rtems to write interrupt handlers. - * - * - * MPC5xx port sponsored by Defence Research and Development Canada - Suffield - * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) - * - * Derived from libbsp/powerpc/mbx8xx/irq/irq.h: - * - * CopyRight (C) 1999 valette@crf.canon.fr - * - * This code is heavilly inspired by the public specification of STREAM V2 - * that can be found at : - * - * <http://www.chorus.com/Documentation/index.html> by following - * the STREAM API Specification Document link. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_IRQ_H -#define _LIBCPU_IRQ_H - -#include <rtems/irq.h> - -#define CPU_ASM_IRQ_VECTOR_BASE 0x0 - -#ifndef ASM - -extern volatile unsigned int ppc_cached_irq_mask; - -/* - * Symblolic IRQ names and related definitions. - */ - - /* - * Base vector for our USIU IRQ handlers. - */ -#define CPU_USIU_VECTOR_BASE (CPU_ASM_IRQ_VECTOR_BASE) - /* - * USIU IRQ handler related definitions - */ -#define CPU_USIU_IRQ_COUNT (16) /* 16 reserved but in the future... */ -#define CPU_USIU_IRQ_MIN_OFFSET (0) -#define CPU_USIU_IRQ_MAX_OFFSET (CPU_USIU_IRQ_MIN_OFFSET + CPU_USIU_IRQ_COUNT - 1) - /* - * UIMB IRQ handlers related definitions - */ -#define CPU_UIMB_IRQ_COUNT (32 - 8) /* first 8 overlap USIU */ -#define CPU_UIMB_IRQ_MIN_OFFSET (CPU_USIU_IRQ_COUNT + CPU_USIU_VECTOR_BASE) -#define CPU_UIMB_IRQ_MAX_OFFSET (CPU_UIMB_IRQ_MIN_OFFSET + CPU_UIMB_IRQ_COUNT - 1) - /* - * PowerPc exceptions handled as interrupt where a rtems managed interrupt - * handler might be connected - */ -#define CPU_PROC_IRQ_COUNT (1) -#define CPU_PROC_IRQ_MIN_OFFSET (CPU_UIMB_IRQ_MAX_OFFSET + 1) -#define CPU_PROC_IRQ_MAX_OFFSET (CPU_PROC_IRQ_MIN_OFFSET + CPU_PROC_IRQ_COUNT - 1) - /* - * Summary - */ -#define CPU_IRQ_COUNT (CPU_PROC_IRQ_MAX_OFFSET + 1) -#define CPU_MIN_OFFSET (CPU_USIU_IRQ_MIN_OFFSET) -#define CPU_MAX_OFFSET (CPU_PROC_IRQ_MAX_OFFSET) - /* - * USIU IRQ symbolic name definitions. - */ -#define CPU_USIU_EXT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 0) -#define CPU_USIU_INT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 1) - -#define CPU_USIU_EXT_IRQ_1 (CPU_USIU_IRQ_MIN_OFFSET + 2) -#define CPU_USIU_INT_IRQ_1 (CPU_USIU_IRQ_MIN_OFFSET + 3) - -#define CPU_USIU_EXT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 4) -#define CPU_USIU_INT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 5) - -#define CPU_USIU_EXT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 6) -#define CPU_USIU_INT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 7) - -#define CPU_USIU_EXT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 8) -#define CPU_USIU_INT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 9) - -#define CPU_USIU_EXT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 10) -#define CPU_USIU_INT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 11) - -#define CPU_USIU_EXT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 12) -#define CPU_USIU_INT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 13) - -#define CPU_USIU_EXT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 14) -#define CPU_USIU_INT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 15) - - /* - * Symbolic names for UISU interrupt sources. - */ -#define CPU_PERIODIC_TIMER (CPU_USIU_INT_IRQ_6) -#define CPU_UIMB_INTERRUPT (CPU_USIU_INT_IRQ_7) - - /* - * UIMB IRQ symbolic name definitions. The first 8 sources are aliases to - * the USIU interrupts of the same number, because they are detected in - * the USIU pending register rather than the UIMB pending register. - */ -#define CPU_UIMB_IRQ_0 (CPU_USIU_INT_IRQ_0) -#define CPU_UIMB_IRQ_1 (CPU_USIU_INT_IRQ_1) -#define CPU_UIMB_IRQ_2 (CPU_USIU_INT_IRQ_2) -#define CPU_UIMB_IRQ_3 (CPU_USIU_INT_IRQ_3) -#define CPU_UIMB_IRQ_4 (CPU_USIU_INT_IRQ_4) -#define CPU_UIMB_IRQ_5 (CPU_USIU_INT_IRQ_5) -#define CPU_UIMB_IRQ_6 (CPU_USIU_INT_IRQ_6) -#define CPU_UIMB_IRQ_7 (CPU_USIU_INT_IRQ_7) - -#define CPU_UIMB_IRQ_8 (CPU_UIMB_IRQ_MIN_OFFSET+ 0) -#define CPU_UIMB_IRQ_9 (CPU_UIMB_IRQ_MIN_OFFSET+ 1) -#define CPU_UIMB_IRQ_10 (CPU_UIMB_IRQ_MIN_OFFSET+ 2) -#define CPU_UIMB_IRQ_11 (CPU_UIMB_IRQ_MIN_OFFSET+ 3) -#define CPU_UIMB_IRQ_12 (CPU_UIMB_IRQ_MIN_OFFSET+ 4) -#define CPU_UIMB_IRQ_13 (CPU_UIMB_IRQ_MIN_OFFSET+ 5) -#define CPU_UIMB_IRQ_14 (CPU_UIMB_IRQ_MIN_OFFSET+ 6) -#define CPU_UIMB_IRQ_15 (CPU_UIMB_IRQ_MIN_OFFSET+ 7) -#define CPU_UIMB_IRQ_16 (CPU_UIMB_IRQ_MIN_OFFSET+ 8) -#define CPU_UIMB_IRQ_17 (CPU_UIMB_IRQ_MIN_OFFSET+ 9) -#define CPU_UIMB_IRQ_18 (CPU_UIMB_IRQ_MIN_OFFSET+ 0) -#define CPU_UIMB_IRQ_19 (CPU_UIMB_IRQ_MIN_OFFSET+11) -#define CPU_UIMB_IRQ_20 (CPU_UIMB_IRQ_MIN_OFFSET+12) -#define CPU_UIMB_IRQ_21 (CPU_UIMB_IRQ_MIN_OFFSET+13) -#define CPU_UIMB_IRQ_22 (CPU_UIMB_IRQ_MIN_OFFSET+14) -#define CPU_UIMB_IRQ_23 (CPU_UIMB_IRQ_MIN_OFFSET+15) -#define CPU_UIMB_IRQ_24 (CPU_UIMB_IRQ_MIN_OFFSET+16) -#define CPU_UIMB_IRQ_25 (CPU_UIMB_IRQ_MIN_OFFSET+17) -#define CPU_UIMB_IRQ_26 (CPU_UIMB_IRQ_MIN_OFFSET+18) -#define CPU_UIMB_IRQ_27 (CPU_UIMB_IRQ_MIN_OFFSET+19) -#define CPU_UIMB_IRQ_28 (CPU_UIMB_IRQ_MIN_OFFSET+20) -#define CPU_UIMB_IRQ_29 (CPU_UIMB_IRQ_MIN_OFFSET+21) -#define CPU_UIMB_IRQ_30 (CPU_UIMB_IRQ_MIN_OFFSET+22) -#define CPU_UIMB_IRQ_31 (CPU_UIMB_IRQ_MIN_OFFSET+23) - - /* - * Symbolic names for UIMB interrupt sources. - */ -#define CPU_IRQ_SCI (CPU_UIMB_IRQ_5) - - /* - * Processor exceptions handled as rtems IRQ symbolic name definitions. - */ -#define CPU_DECREMENTER (CPU_PROC_IRQ_MIN_OFFSET) - -/* - * Convert an rtems_irq_number constant to an interrupt level - * suitable for programming into an I/O device's interrupt level field. - */ -int CPU_irq_level_from_symbolic_name(const rtems_irq_number name); - -/*-------------------------------------------------------------------------+ -| Function Prototypes. -+--------------------------------------------------------------------------*/ - -extern void CPU_rtems_irq_mng_init(unsigned cpuId); - -typedef struct MPC5XX_Interrupt_frame { - uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ - uint32_t calleeLr; /* link register used by callees: SVR4/EABI */ - - /* This is what is left out of the primary contexts */ - uint32_t gpr0; - uint32_t gpr2; /* play safe */ - uint32_t gpr3; - uint32_t gpr4; - uint32_t gpr5; - uint32_t gpr6; - uint32_t gpr7; - uint32_t gpr8; - uint32_t gpr9; - uint32_t gpr10; - uint32_t gpr11; - uint32_t gpr12; - uint32_t gpr13; /* Play safe */ - uint32_t gpr28; /* For internal use by the IRQ handler */ - uint32_t gpr29; /* For internal use by the IRQ handler */ - uint32_t gpr30; /* For internal use by the IRQ handler */ - uint32_t gpr31; /* For internal use by the IRQ handler */ - uint32_t cr; /* Bits of this are volatile, so no-one may save */ - uint32_t ctr; - uint32_t xer; - uint32_t lr; - uint32_t pc; - uint32_t msr; - uint32_t pad[3]; -} MPC5XX_Interrupt_frame; - -void C_dispatch_irq_handler(MPC5XX_Interrupt_frame *frame, unsigned int excNum); - -#endif - -#endif diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h deleted file mode 100644 index 2c8914e2a4..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * vectors.h Exception frame related contant and API. - * - * This include file describe the data structure and the functions implemented - * by rtems to handle exceptions. - * - * - * MPC5xx port sponsored by Defence Research and Development Canada - Suffield - * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) - * - * Derived from libbsp/powerpc/mbx8xx/vectors/vectors.h: - * - * CopyRight (C) 1999 valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef _LIBCPU_VECTORS_H -#define _LIBCPU_VECTORS_H - - -/* - * Size of hardware vector table. - */ -#define NUM_EXCEPTIONS 0x20 - -/* - * The callee (high level exception code written in C) - * will store the Link Registers (return address) at entry r1 + 4 !!!. - * So let room for it!!!. - */ -#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 -#define SRR0_FRAME_OFFSET 8 -#define SRR1_FRAME_OFFSET 12 -#define EXCEPTION_NUMBER_OFFSET 16 -#define EXC_CR_OFFSET 20 -#define EXC_CTR_OFFSET 24 -#define EXC_XER_OFFSET 28 -#define EXC_LR_OFFSET 32 -#define GPR0_OFFSET 36 -#define GPR1_OFFSET 40 -#define GPR2_OFFSET 44 -#define GPR3_OFFSET 48 -#define GPR4_OFFSET 52 -#define GPR5_OFFSET 56 -#define GPR6_OFFSET 60 -#define GPR7_OFFSET 64 -#define GPR8_OFFSET 68 -#define GPR9_OFFSET 72 -#define GPR10_OFFSET 76 -#define GPR11_OFFSET 80 -#define GPR12_OFFSET 84 -#define GPR13_OFFSET 88 -#define GPR14_OFFSET 92 -#define GPR15_OFFSET 96 -#define GPR16_OFFSET 100 -#define GPR17_OFFSET 104 -#define GPR18_OFFSET 108 -#define GPR19_OFFSET 112 -#define GPR20_OFFSET 116 -#define GPR21_OFFSET 120 -#define GPR22_OFFSET 124 -#define GPR23_OFFSET 128 -#define GPR24_OFFSET 132 -#define GPR25_OFFSET 136 -#define GPR26_OFFSET 140 -#define GPR27_OFFSET 144 -#define GPR28_OFFSET 148 -#define GPR29_OFFSET 152 -#define GPR30_OFFSET 156 -#define GPR31_OFFSET 160 -/* - * maintain the EABI requested 8 bytes aligment - * As SVR4 ABI requires 16, make it 16 (as some - * exception may need more registers to be processed...) - */ -#define EXCEPTION_FRAME_END 176 - -#ifndef ASM - -#include <rtems.h> - -/* - * default raw exception handlers - */ - -extern void default_exception_vector_code_prolog(void); -extern int default_exception_vector_code_prolog_size; -extern void initialize_exceptions(void); - -typedef void rtems_exception_handler_t (CPU_Exception_frame* excPtr); -/*DEBUG typedef rtems_exception_handler_t cpuExcHandlerType; */ - -/* - * Exception handler table. - * - * This table contains pointers to assembly-language exception handlers. - * The common exception prologue in vectors.S looks up an entry in this - * table and jumps to it. No return address is saved, so the handlers in - * this table must return directly to the interrupted code. - * - * On entry to an exception handler, R1 points to a new exception stack - * frame in which R3, R4, and LR have been saved. R4 holds the exception - * number. - */ -extern rtems_exception_handler_t* exception_handler_table[NUM_EXCEPTIONS]; - -/* for compatability -- XXX remove */ -typedef rtems_exception_handler_t *cpuExcHandlerType; -extern cpuExcHandlerType *globalExceptHdl; - -#endif /* ASM */ - -#endif /* _LIBCPU_VECTORS_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.h b/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.h deleted file mode 100644 index bd4918fb44..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Clock Tick Device Driver - * - * This routine utilizes the Decrementer Register common to the PPC family. - * - * The tick frequency is directly programmed to the configured number of - * microseconds per tick. - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to support the MPC750. - * Modifications Copyright (c) 1999 Eric Valette valette@crf.canon.fr - */ - -#ifndef _LIBCPU_C_CLOCK_H -#define _LIBCPU_C_CLOCK_H - -#include <rtems.h> - -/* - * These functions and variables represent the API exported by the - * CPU to the BSP. - */ - -extern void clockOff (void* unused); -extern void clockOn (void* unused); -extern void clockIsr (void* unused); -/* bookE decrementer is slightly different */ -extern void clockIsrBookE (void *unused); -extern int clockIsOn (void* unused); - -/* - * These functions and variables represent the assumptions of this - * driver on the BSP. - */ - -extern int BSP_disconnect_clock_handler (void); -/* - * PCI Bus Frequency - */ -extern unsigned int BSP_bus_frequency; -/* - * processor clock frequency - */ -extern unsigned int BSP_processor_frequency; -/* - * Time base divisior (how many tick for 1 second). - */ -extern unsigned int BSP_time_base_divisor; - -#endif diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h deleted file mode 100644 index 2a27e810ee..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * bat.h - * - * This file contains declaration of C function to - * Instantiate 60x/7xx ppc Block Address Translation (BAT) registers. - * More detailed information can be found on motorola - * site and more precisely in the following book : - * - * MPC750 - * Risc Microporcessor User's Manual - * Motorola REF : MPC750UM/AD 8/97 - * - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_BAT_H -#define _LIBCPU_BAT_H - -#include <libcpu/mmu.h> -#include <libcpu/pgtable.h> - -#define IO_PAGE (_PAGE_NO_CACHE | _PAGE_GUARDED | _PAGE_RW) - -#ifndef ASM -/* Take no risks -- the essential parts of this routine run with - * interrupts disabled! - * - * The routine does basic parameter checks: - * - Index must be 0..3 (0..7 on 7455, 7457). - * If an index > 3 is requested the 745x is - * programmed to enable the higher BATs. - * - Size must be a power of two and <= 1<<28 - * (<=1<<31 on 7455, 7457. Also, on these processors - * the special value 0xffffffff is allowed which stands - * for 1<<32). - * If a size > 1<<28 is requested, the 745x is - * programmed to enable the larger block sizes. - * - Bat ranges must not overlap. - * - Physical & virtual addresses must be aligned - * to the size. - * - * RETURNS: zero on success, nonzero on failure. - */ -extern int setdbat(int bat_index, unsigned long virt, unsigned long phys, - unsigned int size, int flags); - -/* Same as setdbat but sets IBAT */ -extern int setibat(int bat_index, unsigned long virt, unsigned long phys, - unsigned int size, int flags); - -/* read DBAT # 'idx' into *pu / *pl. NULL pointers may be passed. - * If pu and pl are NULL, the bat contents are dumped to the console (printk). - * - * RETURNS: upper BAT contents or (-1) if index is invalid - */ -extern int getdbat(int bat_index, unsigned long *pu, unsigned long *pl); - -/* Same as getdbat but reads IBAT */ -extern int getibat(int bat_index, unsigned long *pu, unsigned long *pl); - -/* Do not use the asm-routines; they are obsolete; use setdbat() instead */ -extern void asm_setdbat0(unsigned int uperPart, unsigned int lowerPart); -extern void asm_setdbat1(unsigned int uperPart, unsigned int lowerPart); -extern void asm_setdbat2(unsigned int uperPart, unsigned int lowerPart); -extern void asm_setdbat3(unsigned int uperPart, unsigned int lowerPart); -#else - -/* Initialize all bats (upper and lower) to zero. This routine should *only* - * be called during early BSP initialization when no C-ABI is available - * yet. - * This routine clobbers r3 and r4. - * NOTE: on 7450 CPUs all 8 dbat/ibat units are cleared. On 601 CPUs only - * 4 ibats. - */ - .globl CPU_clear_bats_early - .type CPU_clear_bats_early,@function - -#endif - -#endif /* _LIBCPU_BAT_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h deleted file mode 100644 index a07e063f03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h +++ /dev/null @@ -1,265 +0,0 @@ -#ifndef _LIBCPU_PTE121_H -#define _LIBCPU_PTE121_H - -/* - * Authorship - * ---------- - * This software was created by - * Till Straumann <strauman@slac.stanford.edu>, 4/2002, 2003, 2004, - * Stanford Linear Accelerator Center, Stanford University. - * - * Acknowledgement of sponsorship - * ------------------------------ - * This software was produced by - * the Stanford Linear Accelerator Center, Stanford University, - * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * - * Government disclaimer of liability - * ---------------------------------- - * Neither the United States nor the United States Department of Energy, - * nor any of their employees, makes any warranty, express or implied, or - * assumes any legal liability or responsibility for the accuracy, - * completeness, or usefulness of any data, apparatus, product, or process - * disclosed, or represents that its use would not infringe privately owned - * rights. - * - * Stanford disclaimer of liability - * -------------------------------- - * Stanford University makes no representations or warranties, express or - * implied, nor assumes any liability for the use of this software. - * - * Stanford disclaimer of copyright - * -------------------------------- - * Stanford University, owner of the copyright, hereby disclaims its - * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * - * Maintenance of notices - * ---------------------- - * In the interest of clarity regarding the origin and status of this - * SLAC software, this and all the preceding Stanford University notices - * are to remain affixed to any copy or derivative of this software made - * or distributed by the recipient and are to be affixed to any copy of - * software made or distributed by the recipient that contains a copy or - * derivative of this software. - * - * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 - */ - -/* Rudimentary page/hash table support for Powerpc - * - * A simple, static (i.e. no 'per-process' virtual - * address space etc.) page table providing - * one-to-one effective <-> virtual <-> physical - * address mapping. - * - * PURPOSE: - * 1) allow write-protection of text/read-only data areas - * 2) provide more effective-address space in case - * the BATs are not enough - * 3) allow 'alias' mappings. Such aliases can only use - * the upper bits of the VSID since VSID & 0xf and the - * PI are always mapped 1:1 to the RPN. - * LIMITATIONS: - * - no PTE replacement (makes no sense in a real-time - * environment, anyway) -> the page table just MUST - * be big enough!. - * - only one page table supported. - * - no locking implemented. If multiple threads modify - * the page table, it is the user's responsibility to - * implement exclusive access. - */ - - -/* I don't include mmu.h here because it says it's derived from linux - * and I want to avoid licensing problems - */ - -/* Abstract handle for a page table */ -typedef struct Triv121PgTblRec_ *Triv121PgTbl; - -/* A PTE entry */ -typedef struct PTERec_ { - volatile unsigned long v:1, vsid:24, h:1, api: 6; - volatile unsigned long rpn:20, pad: 3, r:1, c:1, wimg:4, marked:1, pp:2; -} PTERec, *APte; - -/* Initialize a trivial page table - * using 2^ldSize bytes of memory starting at - * 'base'. - * - * RETURNS: a handle to the internal data structure - * used to manage the page table. NULL on - * error. - * - * NOTES: - 'base' must be aligned to the size - * - minimal ldSize is 16 (== 64k) - * - this routine maps the page table itself - * with read-only access. While this prevents - * the CPU from overwriting the page table, - * it can still be corrupted by PCI bus masters - * (like DMA engines, [VME] bridges etc.) and - * even by this CPU if either the MMU is off - * or if there is a DBAT mapping granting write - * access... - */ -Triv121PgTbl -triv121PgTblInit(unsigned long base, unsigned ldSize); - -/* get the log2 of the minimal page table size needed - * for mapping 'size' bytes. - * - * EXAMPLE: create a page table which maps the entire - * physical memory. The page table itself shall - * be allocated at the top of the available - * memory (assuming 'memsize' is a power of two): - * - * ldSize = triv121PgTblLdMinSize(memsize); - * memsize -= (1<<ldSize); / * reduce memory available to RTEMS * / - * pgTbl = triv121PgTblInit(memsize,ldSize); - * - */ -unsigned long -triv121PgTblLdMinSize(unsigned long size); - -/* Map an address range 1:1 in pgTbl with the given protection; - * - * RETURNS: -1 (TRIV121_MAP_SUCCESS) on success; the page index - * for which no PTE could be allocated, on failure. - * - * NOTES: - This routine returns MINUS ONE ON SUCCESS - * - (parts) of a mapping which overlap with - * already existing PTEs are silently ignored. - * - * Therefore, you can e.g. first create - * a couple of write protected maps and - * finally map the entire memory r/w. This - * will leave the write protected maps - * intact. - */ -long -triv121PgTblMap( - Triv121PgTbl pgTbl, /* handle, returned by Init or Get */ - - long vsid, /* vsid for this mapping (contains topmost 4 bits of EA); - * - * NOTE: it is allowed to pass a VSID < 0 to tell this - * routine it should use a VSID corresponding to a - * 1:1:1 effective - virtual - physical mapping - */ - - unsigned long start, /* segment offset (lowermost 28 bits of EA) of address range - * - * NOTE: if VSID < 0 (TRIV121_121_VSID), 'start' is inter- - * preted as an effective address (EA), i.e. all 32 - * bits are used - the most significant four going into - * to the VSID... - */ - - unsigned long numPages, /* number of pages to map */ - - unsigned wimgAttr, /* 'wimg' attributes - * (Write thru, cache Inhibit, coherent Memory, - * Guarded memory) - */ - - unsigned protection /* 'pp' access protection: Super User - * - * 0 r/w none - * 1 r/w ro - * 2 r/w r/w - * 3 ro ro - */ -); - -#define TRIV121_ATTR_W 8 -#define TRIV121_ATTR_I 4 -#define TRIV121_ATTR_M 2 -#define TRIV121_ATTR_G 1 - -/* for I/O pages (e.g. PCI, VME addresses) use cache inhibited - * and guarded pages. RTM about the 'eieio' instruction! - */ -#define TRIV121_ATTR_IO_PAGE (TRIV121_ATTR_I|TRIV121_ATTR_G) - -#define TRIV121_PP_RO_PAGE (1) /* read-only for key = 1, unlocked by key=0 */ -#define TRIV121_PP_RW_PAGE (2) /* read-write for key = 1/0 */ - -#define TRIV121_121_VSID (-1) /* use 1:1 effective<->virtual address mapping */ -#define TRIV121_SEG_VSID (-2) /* lookup VSID in the segment register */ - -#define TRIV121_MAP_SUCCESS (-1) /* triv121PgTblMap() returns this on SUCCESS */ - -/* get a handle to the one and only page table - * (must have been initialized/allocated) - * - * RETURNS: NULL if the page table has not been initialized/allocated. - */ -Triv121PgTbl -triv121PgTblGet(void); - -/* - * compute the SDR1 register value for the page table - */ - -unsigned long -triv121PgTblSDR1(Triv121PgTbl pgTbl); - -/* - * Activate the page table: - * - set up the segment registers for a 1:1 effective <-> virtual address mapping, - * give user and supervisor keys. - * - set up the SDR1 register - * - flush all tlbs - * - 'lock' pgTbl, i.e. prevent all further modifications. - * - * NOTE: This routine does not change any BATs. Since these - * have priority over the page table, the user - * may have to switch overlapping BATs OFF in order - * for the page table mappings to take effect. - */ -void triv121PgTblActivate(Triv121PgTbl pgTbl); - -/* Find the PTE for a EA and print its contents to stdout - * RETURNS: pte for EA or NULL if no entry was found. - */ -APte triv121DumpEa(unsigned long ea); - -/* Find and return a PTE for a vsid/pi combination - * RETURNS: pte or NULL if no entry was found - */ -APte triv121FindPte(unsigned long vsid, unsigned long pi); - -/* - * Unmap an effective address - * - * RETURNS: pte that mapped the ea or NULL if no - * mapping existed. - */ -APte triv121UnmapEa(unsigned long ea); - -/* - * Change the WIMG and PP attributes of the page containing 'ea' - * - * NOTES: The 'wimg' and 'pp' may be <0 to indicate that no - * change is desired. - * - * RETURNS: Pointer to modified PTE or NULL if 'ea' is not mapped. - */ -APte triv121ChangeEaAttributes(unsigned long ea, int wimg, int pp); - -/* Make the whole page table writable - * NOTES: If the page table has not been initialized yet, - * this routine has no effect (i.e., after - * initialization the page table will still be read-only). - */ -void triv121MakePgTblRW(void); - -/* Make the whole page table read-only - */ -void triv121MakePgTblRO(void); - -/* Dump a pte to stdout */ -long triv121DumpPte(APte pte); - -#endif diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/console.h b/c/src/lib/libcpu/powerpc/mpc8260/include/console.h deleted file mode 100644 index 049cef6d89..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc8260/include/console.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef _MPC8260_CONSOLE_H -#define _MPC8260_CONSOLE_H - -#include <rtems/libio.h> - -void m8xx_uart_initialize(void); -void m8xx_uart_interrupts_initialize(void); -void m8xx_uart_scc_initialize (int minor); -void m8xx_uart_smc_initialize (int minor); - -/* Termios callbacks */ -int m8xx_uart_pollRead(int minor); -ssize_t m8xx_uart_pollWrite(int minor, const char* buf, size_t len); -ssize_t m8xx_uart_write(int minor, const char *buf, size_t len); -int m8xx_uart_setAttributes(int, const struct termios* t); - - -#if 0 -int m8260_smc_set_attributes(int, const struct termios*); -int m8260_scc_set_attributes(int, const struct termios*); -void m8260_scc_initialize(int); -void m8260_smc_initialize(int); -int m8260_char_poll_read(int); -int m8260_char_poll_write(int, const char*, int); -rtems_isr m8260_scc1_console_interrupt_handler(rtems_vector_number); -rtems_isr m8260_scc2_console_interrupt_handler(rtems_vector_number); -rtems_isr m8260_scc3_console_interrupt_handler(rtems_vector_number); -rtems_isr m8260_scc4_console_interrupt_handler(rtems_vector_number); -rtems_isr m8260_smc1_console_interrupt_handler(rtems_vector_number); -rtems_isr m8260_smc2_console_interrupt_handler(rtems_vector_number); -int m8260_buf_poll_read(int, char**); -int m8260_buf_poll_write(int, char*, int); -void m8260_console_initialize(void); -rtems_device_driver m8260_console_read(rtems_device_major_number, - rtems_device_minor_number, - void*); -rtems_device_driver m8260_console_write(rtems_device_major_number, - rtems_device_minor_number, - void*); - - -typedef struct Buf_t_ { - struct Buf_t_ *next; - volatile char *buf; - volatile int len; - int pos; -} Buf_t; -#endif - -#define NUM_PORTS 6 - -#define SMC1_MINOR 0 -#define SMC2_MINOR 1 -#define SCC1_MINOR 2 -#define SCC2_MINOR 3 -#define SCC3_MINOR 4 -#define SCC4_MINOR 5 - - -#endif diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h b/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h deleted file mode 100644 index 31708a4199..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * cpm.h - * - * This include file contains definitions pertaining - * to the Communications Processor Module (CPM) on the MPC8xx. - * - * Copyright (c) 1999, National Research Council of Canada - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _MPC8260_CPM_H -#define _MPC8260_CPM_H - -#ifdef __cplusplus -extern "C" { -#endif - - -#define M8xx_BRG_1 (1U << 0) -#define M8xx_BRG_2 (1U << 1) -#define M8xx_BRG_3 (1U << 2) -#define M8xx_BRG_4 (1U << 3) -#define M8xx_BRG_5 (1U << 4) -#define M8xx_BRG_6 (1U << 5) -#define M8xx_BRG_7 (1U << 6) -#define M8xx_BRG_8 (1U << 7) - - -#define M8260_SCC_BRGS (M8xx_BRG_1 | M8xx_BRG_2 | M8xx_BRG_3 | M8xx_BRG_4) -#define M8260_FCC_BRGS (M8xx_BRG_5 | M8xx_BRG_6 | M8xx_BRG_7 | M8xx_BRG_8) -#define M8260_SMC1_BRGS (M8xx_BRG_1|M8xx_BRG_7) -#define M8260_SMC2_BRGS (M8xx_BRG_2|M8xx_BRG_8) - - -#define M8xx_CLK_1 (1U << 0) -#define M8xx_CLK_2 (1U << 1) -#define M8xx_CLK_3 (1U << 2) -#define M8xx_CLK_4 (1U << 3) -#define M8xx_CLK_5 (1U << 4) -#define M8xx_CLK_6 (1U << 5) -#define M8xx_CLK_7 (1U << 6) -#define M8xx_CLK_8 (1U << 7) -#define M8xx_CLK_9 (1U << 8) -#define M8xx_CLK_10 (1U << 9) -#define M8xx_CLK_11 (1U << 10) -#define M8xx_CLK_12 (1U << 11) -#define M8xx_CLK_13 (1U << 12) -#define M8xx_CLK_14 (1U << 13) -#define M8xx_CLK_15 (1U << 14) -#define M8xx_CLK_16 (1U << 15) -#define M8xx_CLK_17 (1U << 16) -#define M8xx_CLK_18 (1U << 17) -#define M8xx_CLK_19 (1U << 18) -#define M8xx_CLK_20 (1U << 19) - -#define M8260_BRG1_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) -#define M8260_BRG2_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) -#define M8260_BRG3_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) -#define M8260_BRG4_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) -#define M8260_BRG5_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) -#define M8260_BRG6_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) -#define M8260_BRG7_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) -#define M8260_BRG8_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) - -#define M8260_SCC1_CLKS (M8xx_CLK_3 | M8xx_CLK_4 | M8xx_CLK_11 | M8xx_CLK_12) -#define M8260_SCC2_CLKS (M8xx_CLK_3 | M8xx_CLK_4 | M8xx_CLK_11 | M8xx_CLK_12) -#define M8260_SCC3_CLKS (M8xx_CLK_5 | M8xx_CLK_6 | M8xx_CLK_7 | M8xx_CLK_8 ) -#define M8260_SCC4_CLKS (M8xx_CLK_5 | M8xx_CLK_6 | M8xx_CLK_7 | M8xx_CLK_8 ) - -#define M8260_FCC1_CLKS (M8xx_CLK_9 | M8xx_CLK_10 | M8xx_CLK_11 | M8xx_CLK_12) -#define M8260_FCC2_CLKS (M8xx_CLK_13 | M8xx_CLK_14 | M8xx_CLK_15 | M8xx_CLK_16) -#define M8260_FCC3_CLKS (M8xx_CLK_13 | M8xx_CLK_14 | M8xx_CLK_15 | M8xx_CLK_16) - -#define M8260_TDM_RXA1 (M8xx_CLK_1 | M8xx_CLK_19 ) -#define M8260_TDM_RXB1 (M8xx_CLK_3 | M8xx_CLK_9 ) -#define M8260_TDM_RXC1 (M8xx_CLK_5 | M8xx_CLK_13 ) -#define M8260_TDM_RXD1 (M8xx_CLK_7 | M8xx_CLK_15 ) -#define M8260_TDM_TXA1 (M8xx_CLK_2 | M8xx_CLK_20 ) -#define M8260_TDM_TXB1 (M8xx_CLK_4 | M8xx_CLK_10 ) -#define M8260_TDM_TXC1 (M8xx_CLK_6 | M8xx_CLK_14 ) -#define M8260_TDM_TXD1 (M8xx_CLK_8 | M8xx_CLK_16 ) - -#define M8260_TDM_RXA2 (M8xx_CLK_13 | M8xx_CLK_5 ) -#define M8260_TDM_RXB2 (M8xx_CLK_15 | M8xx_CLK_17 ) -#define M8260_TDM_RXC2 (M8xx_CLK_3 | M8xx_CLK_17 ) -#define M8260_TDM_RXD2 (M8xx_CLK_1 | M8xx_CLK_19 ) -#define M8260_TDM_TXA2 (M8xx_CLK_14 | M8xx_CLK_6 ) -#define M8260_TDM_TXB2 (M8xx_CLK_16 | M8xx_CLK_18 ) -#define M8260_TDM_TXC2 (M8xx_CLK_4 | M8xx_CLK_18 ) -#define M8260_TDM_TXD2 (M8xx_CLK_2 | M8xx_CLK_20 ) - - - -/* Functions */ - -void m8xx_cp_execute_cmd( uint32_t command ); -void *m8xx_dpram_allocate( unsigned int byte_count ); - -#define m8xx_bd_allocate(count) \ - m8xx_dpram_allocate( (count) * sizeof(m8260BufferDescriptor_t) ) -#define m8xx_RISC_timer_table_allocate(count) \ - m8xx_dpram_allocate( (count) * 4 ) - - - -int m8xx_get_brg_cd (int baud); -int m8xx_get_brg(unsigned brgmask, int baud); -void m8xx_free_brg(int brg_num); - - -int m8xx_get_clk( unsigned clkmask ); -void m8xx_free_clk( int clk_num ); - - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h b/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h deleted file mode 100644 index 9445dde3bc..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * mmu.h - * - * This include file contains definitions pertaining - * to the MMU on the MPC8xx. - * - * Copyright (c) 1999, National Research Council of Canada - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _MPC8260_MMU_H -#define _MPC8260_MMU_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * The MMU_TLB_table is used to statically initialize the Table Lookaside - * Buffers in the MMU of an MPC8260. - */ -typedef struct { - uint32_t mmu_epn; /* Effective Page Number */ - uint32_t mmu_twc; /* Tablewalk Control Register */ - uint32_t mmu_rpn; /* Real Page Number */ -} MMU_TLB_table_t; - -/* - * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be - * supplied by the BSP. - */ -extern MMU_TLB_table_t MMU_TLB_table[]; /* MMU TLB table supplied by BSP */ -extern int MMU_N_TLB_Table_Entries; /* Number of entries in MMU TLB table */ - -/* Functions */ - -void mmu_init( void ); - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h b/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h deleted file mode 100644 index ea088ebae8..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h +++ /dev/null @@ -1,1510 +0,0 @@ -/* buggy version of CPU */ -#define REV_0_2 - -/* -************************************************************************** -************************************************************************** -** ** -** MOTOROLA MPC8260 POWER QUAD INTEGRATED COMMUNICATIONS CONTROLLER ** -** POWERQUICC II ** -** ** -** HARDWARE DECLARATIONS ** -** ** -** ** -** Submitted by: ** -** Andy Dachs ** ** -** Surrey Satellite Technology Limited ** ** -** http://www.sstl.co.uk ** ** -** a.dachs@sstl.co.uk ** ** -** ** -** Based on previous submissions for other PPC variants by: ** -** ** -** Submitted By: ** -** ** -** W. Eric Norum ** -** Saskatchewan Accelerator Laboratory ** -** University of Saskatchewan ** -** 107 North Road ** -** Saskatoon, Saskatchewan, CANADA ** -** S7N 5C6 ** -** ** -** eric@skatter.usask.ca ** -** ** -** Modified for use with the MPC860 (original code was for MC68360) ** -** by ** -** Jay Monkman ** -** Frasca International, Inc. ** -** 906 E. Airport Rd. ** -** Urbana, IL, 61801 ** -** ** -** jmonkman@frasca.com ** -** ** -** ** -************************************************************************** -************************************************************************** -*/ - -#ifndef _MPC8260_H -#define _MPC8260_H - -#ifndef ASM -/* - Macros for SPRs -*/ - - - - -/* -************************************************************************* -* REGISTER SUBBLOCKS * -************************************************************************* -*/ - - -/* - * Memory controller registers - */ -typedef struct m8260MEMCRegisters_ { - uint32_t br; - uint32_t _or; /* or is a C++ keyword :( */ -} m8260MEMCRegisters_t; - - -/* - * Fast Communication Controller Registers -*/ -typedef struct m8260FCCRegisters_ { - uint32_t gfmr; - uint32_t fpsmr; - uint16_t ftodr; - uint8_t fcc_pad0[2]; - uint16_t fdsr; - uint8_t fcc_pad1[2]; - uint32_t fcce; - uint32_t fccm; - uint8_t fccs; - uint8_t fcc_pad2[3]; - uint8_t ftirr_phy0; /* n/a on FCC3 */ - uint8_t ftirr_phy1; /* n/a on FCC3 */ - uint8_t ftirr_phy2; /* n/a on FCC3 */ - uint8_t ftirr_phy3; /* n/a on FCC3 */ -} m8260FCCRegisters_t; - - -/* - * Serial Communications Controller registers - */ -typedef struct m8260SCCRegisters_ { - uint32_t gsmr_l; - uint32_t gsmr_h; - uint16_t psmr; - uint8_t scc_pad0[2]; - uint16_t todr; - uint16_t dsr; - uint16_t scce; - uint8_t scc_pad2[2]; - uint16_t sccm; - uint8_t scc_pad3[1]; - uint8_t sccs; - uint8_t scc_pad1[8]; -} m8260SCCRegisters_t; - -/* - * Serial Management Controller registers - */ -typedef struct m8260SMCRegisters_ { - uint8_t smc_pad0[2]; - uint16_t smcmr; - uint8_t smc_pad2[2]; - uint8_t smce; - uint8_t smc_pad3[3]; - uint8_t smcm; - uint8_t smc_pad1[5]; -} m8260SMCRegisters_t; - - -/* - * Serial Interface With Time Slot Assigner Registers - */ -typedef struct m8260SIRegisters_ { - uint16_t siamr; - uint16_t sibmr; - uint16_t sicmr; - uint16_t sidmr; - uint8_t sigmr; - uint8_t si_pad0[1]; - uint8_t sicmdr; - uint8_t si_pad1[1]; - uint8_t sistr; - uint8_t si_pad2[1]; - uint16_t sirsr; -} m8260SIRegisters_t; - - -/* - * Multi Channel Controller registers - */ -typedef struct m8260MCCRegisters_ { - uint16_t mcce; - uint8_t mcc_pad2[2]; - uint16_t mccm; - uint16_t mcc_pad0; - uint8_t mccf; - uint8_t mcc_pad1[7]; -} m8260MCCRegisters_t; - - -/* -************************************************************************* -* RISC Timers * -************************************************************************* -*/ -/* -typedef struct m8260TimerParms_ { - uint16_t tm_base; - uint16_t _tm_ptr; - uint16_t _r_tmr; - uint16_t _r_tmv; - uint32_t tm_cmd; - uint32_t tm_cnt; -} m8260TimerParms_t; -*/ - -/* - * RISC Controller Configuration Register (RCCR) - * All other bits in this register are reserved. - */ -#define M8260_RCCR_TIME (1<<31) /* Enable timer */ -#define M8260_RCCR_TIMEP(x) ((x)<<24) /* Timer period */ -#define M8260_RCCR_DR1M (1<<23) /* IDMA Rqst 1 Mode */ -#define M8260_RCCR_DR2M (1<<22) /* IDMA Rqst 2 Mode */ -#define M8260_RCCR_DR1QP(x) ((x)<<20) /* IDMA1 Rqst Priority */ -#define M8260_RCCR_EIE (1<<19) /* External Interrupt Enable */ -#define M8260_RCCR_SCD (1<<18) /* Scheduler Configuration */ -#define M8260_RCCR_DR2QP(x) ((x)<<16) /* IDMA2 Rqst Priority */ -#define M8260_RCCR_ERAM(x) ((x)<<13) /* Enable RAM Microcode */ -#define M8260_RCCR_EDM1 (1<<11) /* DRQ1 Edge detect mode */ -#define M8260_RCCR_EDM2 (1<<10) /* DRQ2 Edge detect mode */ -#define M8260_RCCR_EDM3 (1<<9) /* DRQ3 Edge detect mode */ -#define M8260_RCCR_EDM4 (1<<8) /* DRQ4 Edge detect mode */ -#define M8260_RCCR_DR3M (1<<7) /* IDMA Rqst 1 Mode */ -#define M8260_RCCR_DR4M (1<<6) /* IDMA Rqst 2 Mode */ -#define M8260_RCCR_DR3QP(x) ((x)<<4) /* IDMA3 Rqst Priority */ -#define M8260_RCCR_DEM12 (1<<3) /* DONE1,2 Edge detect mode */ -#define M8260_RCCR_DEM34 (1<<2) /* DONE3,4 Edge detect mode */ -#define M8260_RCCR_DR4QP(x) (x) /* IDMA4 Rqst Priority */ - - - -/* - * Command register - * Set up this register before issuing a M8260_CR_OP_SET_TIMER command. - */ -#if 0 -#define M8260_TM_CMD_V (1<<31) /* Set to enable timer */ -#define M8260_TM_CMD_R (1<<30) /* Set for automatic restart */ -#define M8260_TM_CMD_PWM (1<<29) /* Set for PWM operation */ -#define M8260_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ -#define M8260_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ -#endif - -/* -************************************************************************* -* DMA Controllers * -************************************************************************* -*/ -typedef struct m8260IDMAparms_ { - uint16_t ibase; - uint16_t dcm; - uint16_t ibdptr; - uint16_t dpr_buf; - uint16_t _buf_inv; - uint16_t ssmax; - uint16_t _dpr_in_ptr; - uint16_t sts; - uint16_t _dpr_out_ptr; - uint16_t seob; - uint16_t deob; - uint16_t dts; - uint16_t _ret_add; - uint16_t reserved; - uint32_t _bd_cnt; - uint32_t _s_ptr; - uint32_t _d_ptr; - uint32_t istate; -} m8260IDMAparms_t; - - -/* -************************************************************************* -* Serial Communication Controllers * -************************************************************************* -*/ - - -typedef struct m8260SCCparms_ { - uint16_t rbase; - uint16_t tbase; - uint8_t rfcr; - uint8_t tfcr; - uint16_t mrblr; - uint32_t _rstate; - uint32_t _pad0; - uint16_t _rbptr; - uint16_t _pad1; - uint32_t _pad2; - uint32_t _tstate; - uint32_t _pad3; - uint16_t _tbptr; - uint16_t _pad4; - uint32_t _pad5; - uint32_t _rcrc; - uint32_t _tcrc; - union { - struct { - uint32_t _res0; - uint32_t _res1; - uint16_t max_idl; - uint16_t idlc; - uint16_t brkcr; - uint16_t parec; - uint16_t frmec; - uint16_t nosec; - uint16_t brkec; - uint16_t brklen; - uint16_t uaddr[2]; - uint16_t rtemp; - uint16_t toseq; - uint16_t character[8]; - uint16_t rccm; - uint16_t rccr; - uint16_t rlbc; - } uart; - struct { - uint32_t _pad0; - uint32_t c_mask; - uint32_t c_pres; - uint16_t disfc; - uint16_t crcec; - uint16_t abtsc; - uint16_t nmarc; - uint16_t retrc; - uint16_t mflr; - uint16_t _max_cnt; - uint16_t rfthr; - uint16_t _rfcnt; - uint16_t hmask; - uint16_t haddr1; - uint16_t haddr2; - uint16_t haddr3; - uint16_t haddr4; - uint16_t _tmp; - uint16_t _tmp_mb; - } hdlc; - struct { - uint32_t _pad0; - uint32_t crcc; - uint16_t prcrc; - uint16_t ptcrc; - uint16_t parec; - uint16_t bsync; - uint16_t bdle; - uint16_t character[8]; - uint16_t rccm; - } bisync; - struct { - uint32_t _crc_p; - uint32_t _crc_c; - } transparent; - struct { - uint32_t c_pres; - uint32_t c_mask; - uint32_t crcec; - uint32_t alec; - uint32_t disfc; - uint16_t pads; - uint16_t ret_lim; - uint16_t _ret_cnt; - uint16_t mflr; - uint16_t minflr; - uint16_t maxd1; - uint16_t maxd2; - uint16_t _maxd; - uint16_t _dma_cnt; - uint16_t _max_b; - uint16_t gaddr1; - uint16_t gaddr2; - uint16_t gaddr3; - uint16_t gaddr4; - uint32_t _tbuf0data0; - uint32_t _tbuf0data1; - uint32_t _tbuf0rba0; - uint32_t _tbuf0crc; - uint16_t _tbuf0bcnt; - uint16_t paddr_h; - uint16_t paddr_m; - uint16_t paddr_l; - uint16_t p_per; - uint16_t _rfbd_ptr; - uint16_t _tfbd_ptr; - uint16_t _tlbd_ptr; - uint32_t _tbuf1data0; - uint32_t _tbuf1data1; - uint32_t _tbuf1rba0; - uint32_t _tbuf1crc; - uint16_t _tbuf1bcnt; - uint16_t _tx_len; - uint16_t iaddr1; - uint16_t iaddr2; - uint16_t iaddr3; - uint16_t iaddr4; - uint16_t _boff_cnt; - uint16_t taddr_l; - uint16_t taddr_m; - uint16_t taddr_h; - } ethernet; - } un; -} m8260SCCparms_t; - - -/* - * Event and mask registers (SCCE, SCCM) - */ -#define M8260_SCCE_BRKE (1<<6) -#define M8260_SCCE_BRK (1<<5) -#define M8260_SCCE_TXE (1<<4) -#define M8260_SCCE_RXF (1<<3) -#define M8260_SCCE_BSY (1<<2) -#define M8260_SCCE_TX (1<<1) -#define M8260_SCCE_RX (1<<0) - - -/* -************************************************************************* -* Fast Serial Communication Controllers * -************************************************************************* -*/ - - -typedef struct m8260FCCparms_ { - uint16_t riptr; - uint16_t tiptr; - uint16_t _pad0; - uint16_t mrblr; - uint32_t rstate; - uint32_t rbase; - uint16_t _rbdstat; - uint16_t _rbdlen; - uint32_t _rdptr; - uint32_t tstate; - uint32_t tbase; - uint16_t _tbdstat; - uint16_t _tbdlen; - uint32_t _tdptr; - uint32_t _rbptr; - uint32_t _tbptr; - uint32_t _rcrc; - uint32_t _pad1; - uint32_t _tcrc; - - union { - struct { - uint32_t _pad0; - uint32_t _pad1; - uint32_t c_mask; - uint32_t c_pres; - uint16_t disfc; - uint16_t crcec; - uint16_t abtsc; - uint16_t nmarc; - uint32_t _max_cnt; - uint16_t mflr; - uint16_t rfthr; - uint16_t rfcnt; - uint16_t hmask; - uint16_t haddr1; - uint16_t haddr2; - uint16_t haddr3; - uint16_t haddr4; - uint16_t _ts_tmp; - uint16_t _tmp_mb; - } hdlc; - struct { - uint32_t _pad0; - uint32_t _pad1; - uint32_t c_mask; - uint32_t c_pres; - uint16_t disfc; - uint16_t crcec; - uint16_t abtsc; - uint16_t nmarc; - uint32_t _max_cnt; - uint16_t mflr; - uint16_t rfthr; - uint16_t rfcnt; - uint16_t hmask; - uint16_t haddr1; - uint16_t haddr2; - uint16_t haddr3; - uint16_t haddr4; - uint16_t _ts_tmp; - uint16_t _tmp_mb; - } transparent; - struct { - uint32_t _stat_buf; - uint32_t cam_ptr; - uint32_t c_mask; - uint32_t c_pres; - uint32_t crcec; - uint32_t alec; - uint32_t disfc; - uint16_t ret_lim; - uint16_t _ret_cnt; - uint16_t p_per; - uint16_t _boff_cnt; - uint32_t gaddr_h; - uint32_t gaddr_l; - uint16_t tfcstat; - uint16_t tfclen; - uint32_t tfcptr; - uint16_t mflr; - uint16_t paddr1_h; - uint16_t paddr1_m; - uint16_t paddr1_l; - uint16_t _ibd_cnt; - uint16_t _ibd_start; - uint16_t _ibd_end; - uint16_t _tx_len; - uint16_t _ibd_base; - uint32_t iaddr_h; - uint32_t iaddr_l; - uint16_t minflr; - uint16_t taddr_h; - uint16_t taddr_m; - uint16_t taddr_l; - uint16_t pad_ptr; - uint16_t _pad0; - uint16_t _cf_range; - uint16_t _max_b; - uint16_t maxd1; - uint16_t maxd2; - uint16_t _maxd; - uint16_t _dma_cnt; - uint32_t octc; - uint32_t colc; - uint32_t broc; - uint32_t mulc; - uint32_t uspc; - uint32_t frgc; - uint32_t ospc; - uint32_t jbrc; - uint32_t p64c; - uint32_t p65c; - uint32_t p128c; - uint32_t p256c; - uint32_t p512c; - uint32_t p1024c; - uint32_t _cam_buf; - uint32_t _pad1; - } ethernet; - } un; -} m8260FCCparms_t; - - -/* - * Receive and transmit function code register bits - * These apply to the function code registers of all devices, not just SCC. - */ -#define M8260_RFCR_BO(x) ((x)<<3) -#define M8260_RFCR_MOT (2<<3) -#define M8260_RFCR_LOCAL_BUS (2) -#define M8260_RFCR_60X_BUS (0) -#define M8260_TFCR_BO(x) ((x)<<3) -#define M8260_TFCR_MOT (2<<3) -#define M8260_TFCR_LOCAL_BUS (2) -#define M8260_TFCR_60X_BUS (0) - -/* -************************************************************************* -* Serial Management Controllers * -************************************************************************* -*/ -typedef struct m8260SMCparms_ { - uint16_t rbase; - uint16_t tbase; - uint8_t rfcr; - uint8_t tfcr; - uint16_t mrblr; - uint32_t _rstate; - uint32_t _pad0; - uint16_t _rbptr; - uint16_t _pad1; - uint32_t _pad2; - uint32_t _tstate; - uint32_t _pad3; - uint16_t _tbptr; - uint16_t _pad4; - uint32_t _pad5; - union { - struct { - uint16_t max_idl; - uint16_t _idlc; - uint16_t _brkln; - uint16_t brkec; - uint16_t brkcr; - uint16_t _r_mask; - } uart; - struct { - uint16_t _pad0[6]; - } transparent; - } un; - uint32_t _pad6; -} m8260SMCparms_t; - -/* - * Mode register - */ -#define M8260_SMCMR_CLEN(x) ((x)<<11) /* Character length */ -#define M8260_SMCMR_2STOP (1<<10) /* 2 stop bits */ -#define M8260_SMCMR_PARITY (1<<9) /* Enable parity */ -#define M8260_SMCMR_EVEN (1<<8) /* Even parity */ -#define M8260_SMCMR_SM_GCI (0<<4) /* GCI Mode */ -#define M8260_SMCMR_SM_UART (2<<4) /* UART Mode */ -#define M8260_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ -#define M8260_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ -#define M8260_SMCMR_DM_ECHO (2<<2) /* Echo mode */ -#define M8260_SMCMR_TEN (1<<1) /* Enable transmitter */ -#define M8260_SMCMR_REN (1<<0) /* Enable receiver */ - -/* - * Event and mask registers (SMCE, SMCM) - */ -#define M8260_SMCE_TXE (1<<4) -#define M8260_SMCE_BSY (1<<2) -#define M8260_SMCE_TX (1<<1) -#define M8260_SMCE_RX (1<<0) - -/* -************************************************************************* -* Serial Peripheral Interface * -************************************************************************* -*/ -typedef struct m8260SPIparms_ { - uint16_t rbase; - uint16_t tbase; - uint8_t rfcr; - uint8_t tfcr; - uint16_t mrblr; - uint32_t _rstate; - uint32_t _pad0; - uint16_t _rbptr; - uint16_t _pad1; - uint32_t _pad2; - uint32_t _tstate; - uint32_t _pad3; - uint16_t _tbptr; - uint16_t _pad4; - uint32_t _pad5; -} m8260SPIparms_t; - -/* - * Mode register (SPMODE) - */ -#define M8260_SPMODE_LOOP (1<<14) /* Local loopback mode */ -#define M8260_SPMODE_CI (1<<13) /* Clock invert */ -#define M8260_SPMODE_CP (1<<12) /* Clock phase */ -#define M8260_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ -#define M8260_SPMODE_REV (1<<10) /* Reverse data */ -#define M8260_SPMODE_MASTER (1<<9) /* SPI is master */ -#define M8260_SPMODE_EN (1<<8) /* Enable SPI */ -#define M8260_SPMODE_CLEN(x) ((x)<<4) /* Character length */ -#define M8260_SPMODE_PM(x) (x) /* Prescaler modulus */ - -/* - * Mode register (SPCOM) - */ -#define M8260_SPCOM_STR (1<<7) /* Start transmit */ - -/* - * Event and mask registers (SPIE, SPIM) - */ -#define M8260_SPIE_MME (1<<5) /* Multi-master error */ -#define M8260_SPIE_TXE (1<<4) /* Tx error */ -#define M8260_SPIE_BSY (1<<2) /* Busy condition*/ -#define M8260_SPIE_TXB (1<<1) /* Tx buffer */ -#define M8260_SPIE_RXB (1<<0) /* Rx buffer */ - -/* -************************************************************************* -* SDMA (SCC, SMC, SPI) Buffer Descriptors * -************************************************************************* -*/ -typedef struct m8260BufferDescriptor_ { - uint16_t status; - uint16_t length; - volatile void *buffer; -} m8260BufferDescriptor_t; - -/* - * Bits in receive buffer descriptor status word - */ -#define M8260_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8260_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8260_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8260_BD_LAST (1<<11) /* Ethernet, SPI */ -#define M8260_BD_CONTROL_CHAR (1<<11) /* SCC UART */ -#define M8260_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ -#define M8260_BD_ADDRESS (1<<10) /* SCC UART */ -#define M8260_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ -#define M8260_BD_MISS (1<<8) /* Ethernet */ -#define M8260_BD_IDLE (1<<8) /* SCC UART, SMC UART */ -#define M8260_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ -#define M8260_BD_LONG (1<<5) /* Ethernet, SCC HDLC */ -#define M8260_BD_BREAK (1<<5) /* SCC UART, SMC UART */ -#define M8260_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */ -#define M8260_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ -#define M8260_BD_SHORT (1<<3) /* Ethernet */ -#define M8260_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ -#define M8260_BD_ABORT (1<<3) /* SCC HDLC */ -#define M8260_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */ -#define M8260_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8260_BD_COLLISION (1<<0) /* Ethernet */ -#define M8260_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ -#define M8260_BD_MASTER_ERROR (1<<0) /* SPI */ - -#define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */ -#define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */ -#define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ -#define M8xx_BD_ADDRESS (1<<10) /* SCC UART */ -#define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ -#define M8xx_BD_MISS (1<<8) /* Ethernet */ -#define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */ -#define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ -#define M8xx_BD_LONG (1<<5) /* Ethernet, SCC HDLC */ -#define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */ -#define M8xx_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */ -#define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ -#define M8xx_BD_SHORT (1<<3) /* Ethernet */ -#define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ -#define M8xx_BD_ABORT (1<<3) /* SCC HDLC */ -#define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */ -#define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8xx_BD_COLLISION (1<<0) /* Ethernet */ -#define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ -#define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */ - -/* - * Bits in transmit buffer descriptor status word - * Many bits have the same meaning as those in receiver buffer descriptors. - */ -#define M8260_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8260_BD_PAD (1<<14) /* Ethernet */ -#define M8260_BD_CTS_REPORT (1<<11) /* SCC UART */ -#define M8260_BD_TX_CRC (1<<10) /* Ethernet */ -#define M8260_BD_DEFER (1<<9) /* Ethernet */ -#define M8260_BD_HEARTBEAT (1<<8) /* Ethernet */ -#define M8260_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ -#define M8260_BD_LATE_COLLISION (1<<7) /* Ethernet */ -#define M8260_BD_NO_STOP_BIT (1<<7) /* SCC UART */ -#define M8260_BD_RETRY_LIMIT (1<<6) /* Ethernet */ -#define M8260_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ -#define M8260_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */ -#define M8260_BD_CARRIER_LOST (1<<0) /* Ethernet */ -#define M8260_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */ - -#define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8xx_BD_PAD (1<<14) /* Ethernet */ -#define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */ -#define M8xx_BD_TX_CRC (1<<10) /* Ethernet */ -#define M8xx_BD_DEFER (1<<9) /* Ethernet */ -#define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */ -#define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ -#define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */ -#define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */ -#define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */ -#define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ -#define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */ -#define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */ -#define M8xx_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */ - -/* -************************************************************************* -* IDMA Buffer Descriptors * -************************************************************************* -*/ -typedef struct m8260IDMABufferDescriptor_ { - uint16_t status; - uint8_t dfcr; - uint8_t sfcr; - uint32_t length; - void *source; - void *destination; -} m8260IDMABufferDescriptor_t; - -/* -************************************************************************* -* RISC Communication Processor Module Command Register (CR) * -************************************************************************* -*/ -#define M8260_CR_RST (1<<31) /* Reset communication processor */ - -#define M8260_CR_FCC1 ((4<<26)|(16<<21)) /* FCC1 page and code */ -#define M8260_CR_FCC1_ATM ((4<<26)|(14<<21)) /* FCC1 ATM mode page and code */ -#define M8260_CR_FCC2 ((5<<26)|(17<<21)) /* FCC2 page and code */ -#define M8260_CR_FCC2_ATM ((5<<26)|(14<<21)) /* FCC2 ATM mode page and code */ -#define M8260_CR_FCC3 ((6<<26)|(18<<21)) /* FCC3 page and code */ -#define M8260_CR_SCC1 ((0<<26)|(4<<21)) /* SCC1 page and code */ -#define M8260_CR_SCC2 ((1<<26)|(5<<21)) /* SCC2 page and code */ -#define M8260_CR_SCC3 ((2<<26)|(6<<21)) /* SCC3 page and code */ -#define M8260_CR_SCC4 ((3<<26)|(7<<21)) /* SCC4 page and code */ -#define M8260_CR_SMC1 ((7<<26)|(8<<21)) /* SMC1 page and code */ -#define M8260_CR_SMC2 ((8<<26)|(9<<21)) /* SMC2 page and code */ -#define M8260_CR_RAND ((10<<26)|(14<<21)) /* SMC2 page and code */ -#define M8260_CR_SPI ((9<<26)|(10<<21)) /* SPI page and code */ -#define M8260_CR_I2C ((10<<26)|(11<<21)) /* I2C page and code */ -#define M8260_CR_TMR ((10<<26)|(15<<21)) /* Timer page and code */ -#define M8260_CR_MCC1 ((7<<26)|(28<<21)) /* MCC1 page and code */ -#define M8260_CR_MCC2 ((8<<26)|(29<<21)) /* MCC2 page and code */ -#define M8260_CR_IDMA1 ((7<<26)|(20<<21)) /* IDMA1 page and code */ -#define M8260_CR_IDMA2 ((8<<26)|(21<<21)) /* IDMA2 page and code */ -#define M8260_CR_IDMA3 ((9<<26)|(22<<21)) /* IDMA3 page and code */ -#define M8260_CR_IDMA4 ((10<<26)|(23<<21)) /* IDMA4 page and code */ - -#define M8260_CR_FLG (1<<16) /* Command sempahore flag */ - -#define M8260_CR_MCC_CHAN(x) ((x)<<6) /* MCC channel number */ -#define M8260_CR_FCC_HDLC (0<<6) /* FCC HDLC/Transparent protocol code */ -#define M8260_CR_FCC_ATM (10<<6) /* FCC ATM protocol code */ -#define M8260_CR_FCC_ETH (12<<6) /* FCC Ethernet protocol code */ - -#define M8260_CR_OP_INIT_RX_TX (0) /* FCC, SCC, SMC UART, SMC GCI, SPI, I2C, MCC */ -#define M8260_CR_OP_INIT_RX (1) /* FCC, SCC, SMC UART, SPI, I2C, MCC */ -#define M8260_CR_OP_INIT_TX (2) /* FCC, SCC, SMC UART, SPI, I2C, MCC */ -#define M8260_CR_OP_INIT_HUNT (3) /* FCC, SCC, SMC UART */ -#define M8260_CR_OP_STOP_TX (4) /* FCC, SCC, SMC UART, MCC */ -#define M8260_CR_OP_GR_STOP_TX (5) /* FCC, SCC */ -#define M8260_CR_OP_RESTART_TX (6) /* FCC, SCC, SMC UART */ -#define M8260_CR_OP_CLOSE_RX_BD (7) /* FCC, SCC, SMC UART, SPI, I2C */ -#define M8260_CR_OP_SET_GRP_ADDR (8) /* FCC, SCC */ -#define M8260_CR_OP_SET_TIMER (8) /* Timer */ -#define M8260_CR_OP_GCI_TIMEOUT (9) /* SMC GCI */ -#define M8260_CR_OP_START_IDMA (9) /* IDMA */ -#define M8260_CR_OP_STOP_RX (9) /* MCC */ -#define M8260_CR_OP_ATM_TX (10) /* FCC */ -#define M8260_CR_OP_RESET_BCS (10) /* SCC */ -#define M8260_CR_OP_GCI_ABORT (10) /* SMC GCI */ -#define M8260_CR_OP_STOP_IDMA (11) /* IDMA */ -#define M8260_CR_OP_RANDOM (12) /* RAND */ - -/* -************************************************************************* -* System Protection Control Register (SYPCR) * -************************************************************************* -*/ -#define M8260_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ -#define M8260_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ -#define M8260_SYPCR_BME (1<<7) /* Bus monitor enable */ -#define M8260_SYPCR_SWF (1<<3) /* Software watchdog freeze */ -#define M8260_SYPCR_SWE (1<<2) /* Software watchdog enable */ -#define M8260_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ -#define M8260_SYPCR_SWP (1<<0) /* Software watchdog prescale */ - -/* -************************************************************************* -* Memory Control Registers * -************************************************************************* -*/ -#define M8260_UPM_AMX_8col (0<<20) /* 8 column DRAM */ -#define M8260_UPM_AMX_9col (1<<20) /* 9 column DRAM */ -#define M8260_UPM_AMX_10col (2<<20) /* 10 column DRAM */ -#define M8260_UPM_AMX_11col (3<<20) /* 11 column DRAM */ -#define M8260_UPM_AMX_12col (4<<20) /* 12 column DRAM */ -#define M8260_UPM_AMX_13col (5<<20) /* 13 column DRAM */ -#define M8260_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */ -#define M8260_MSR_WPER (1<<7) /* Write protection error */ -#define M8260_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */ -#define M8260_BR_BA(x) ((x)&0xffff8000) /* Base address */ -#define M8260_BR_AT(x) ((x)<<12) /* Address type */ -#define M8260_BR_PS8 (1<<10) /* 8 bit port */ -#define M8260_BR_PS16 (2<<10) /* 16 bit port */ -#define M8260_BR_PS32 (0<<10) /* 32 bit port */ -#define M8260_BR_PARE (1<<9) /* Parity checking enable */ -#define M8260_BR_WP (1<<8) /* Write protect */ -#define M8260_BR_MS_GPCM (0<<6) /* GPCM */ -#define M8260_BR_MS_UPMA (2<<6) /* UPM A */ -#define M8260_BR_MS_UPMB (3<<6) /* UPM B */ -#define M8260_MEMC_BR_V (1<<0) /* Base/Option register are valid */ - -#define M8260_MEMC_OR_32K 0xffff8000 /* Address range */ -#define M8260_MEMC_OR_64K 0xffff0000 -#define M8260_MEMC_OR_128K 0xfffe0000 -#define M8260_MEMC_OR_256K 0xfffc0000 -#define M8260_MEMC_OR_512K 0xfff80000 -#define M8260_MEMC_OR_1M 0xfff00000 -#define M8260_MEMC_OR_2M 0xffe00000 -#define M8260_MEMC_OR_4M 0xffc00000 -#define M8260_MEMC_OR_8M 0xff800000 -#define M8260_MEMC_OR_16M 0xff000000 -#define M8260_MEMC_OR_32M 0xfe000000 -#define M8260_MEMC_OR_64M 0xfc000000 -#define M8260_MEMC_OR_128 0xf8000000 -#define M8260_MEMC_OR_256M 0xf0000000 -#define M8260_MEMC_OR_512M 0xe0000000 -#define M8260_MEMC_OR_1G 0xc0000000 -#define M8260_MEMC_OR_2G 0x80000000 -#define M8260_MEMC_OR_4G 0x00000000 -#define M8260_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ -#define M8260_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ -#define M8260_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */ -#define M8260_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ -#define M8260_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ -#define M8260_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ -#define M8260_MEMC_OR_BI (1<8) /* Burst inhibit */ -#define M8260_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ -#define M8260_MEMC_OR_SETA (1<<3) /* *TA generated externally */ -#define M8260_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */ -#define M8260_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */ - -/* -************************************************************************* -* UPM Registers (MxMR) * -************************************************************************* -*/ -#define M8260_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */ -#define M8260_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */ -#define M8260_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */ -#define M8260_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */ -#define M8260_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */ -#define M8260_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */ -#define M8260_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */ -#define M8260_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */ -/* -************************************************************************* -* Memory Command Register (MCR) * -************************************************************************* -*/ -#define M8260_MEMC_MCR_WRITE (0<<30) /* WRITE command */ -#define M8260_MEMC_MCR_READ (1<<30) /* READ command */ -#define M8260_MEMC_MCR_RUN (2<<30) /* RUN command */ -#define M8260_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */ -#define M8260_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */ -#define M8260_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */ -#define M8260_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */ -#define M8260_MEMC_MCR_MAD(x) (x) /* Machine address */ - - - -/* -************************************************************************* -* SI Mode Register (SIMODE) * -************************************************************************* -*/ -#define M8260_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ -#define M8260_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ -#define M8260_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ -#define M8260_SI_SMC2_BRG2 (1<<28) -#define M8260_SI_SMC2_BRG3 (2<<28) -#define M8260_SI_SMC2_BRG4 (3<<28) -#define M8260_SI_SMC2_CLK5 (0<<28) -#define M8260_SI_SMC2_CLK6 (1<<28) -#define M8260_SI_SMC2_CLK7 (2<<28) -#define M8260_SI_SMC2_CLK8 (3<<28) -#define M8260_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ -#define M8260_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ -#define M8260_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ -#define M8260_SI_SMC1_BRG2 (1<<12) -#define M8260_SI_SMC1_BRG3 (2<<12) -#define M8260_SI_SMC1_BRG4 (3<<12) -#define M8260_SI_SMC1_CLK1 (0<<12) -#define M8260_SI_SMC1_CLK2 (1<<12) -#define M8260_SI_SMC1_CLK3 (2<<12) -#define M8260_SI_SMC1_CLK4 (3<<12) - -/* -************************************************************************* -* SDMA Configuration Register (SDCR) * -************************************************************************* -*/ -#define M8260_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */ -#define M8260_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */ - -/* -************************************************************************* -* SDMA Status Register (SDSR) * -************************************************************************* -*/ -#define M8260_SDSR_SBER (1<<7) /* SDMA Channel bus error */ -#define M8260_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */ -#define M8260_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */ - -/* -************************************************************************* -* Baud (sic) Rate Generators * -************************************************************************* -*/ -#define M8260_BRG_RST (1<<17) /* Reset generator */ -#define M8260_BRG_EN (1<<16) /* Enable generator */ -#define M8260_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ -#define M8260_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ -#define M8260_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ -#define M8260_BRG_ATB (1<<13) /* Autobaud */ -#define M8260_BRG_115200 (21<<1) /* Assume 40 MHz clock */ -#define M8260_BRG_57600 (32<<1) -#define M8260_BRG_38400 (64<<1) -#define M8260_BRG_19200 (129<<1) -#define M8260_BRG_9600 (259<<1) -#define M8260_BRG_4800 (520<<1) -#define M8260_BRG_2400 (1040<<1) -#define M8260_BRG_1200 (2082<<1) -#define M8260_BRG_600 ((259<<1) | 1) -#define M8260_BRG_300 ((520<<1) | 1) -#define M8260_BRG_150 ((1040<<1) | 1) -#define M8260_BRG_75 ((2080<<1) | 1) - -#define M8xx_BRG_RST (1<<17) /* Reset generator */ -#define M8xx_BRG_EN (1<<16) /* Enable generator */ -#define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ - -#define M8260_BRG1 (1<<7) -#define M8260_BRG2 (1<<6) -#define M8260_BRG3 (1<<5) -#define M8260_BRG4 (1<<4) -#define M8260_BRG5 (1<<3) -#define M8260_BRG6 (1<<2) -#define M8260_BRG7 (1<<1) -#define M8260_BRG8 (1<<0) - - - -#define M8260_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */ -#define M8260_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */ -#define M8260_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */ -#define M8260_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */ -#define M8260_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */ -#define M8260_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */ -#define M8260_TGCR_STP1 (1<<1) /* Stop timer */ -#define M8260_TGCR_STP2 (1<<5) /* Stop timer */ -#define M8260_TGCR_STP3 (1<<9) /* Stop timer */ -#define M8260_TGCR_STP4 (1<<13) /* Stop timer */ -#define M8260_TGCR_RST1 (1<<0) /* Enable timer */ -#define M8260_TGCR_RST2 (1<<4) /* Enable timer */ -#define M8260_TGCR_RST3 (1<<8) /* Enable timer */ -#define M8260_TGCR_RST4 (1<<12) /* Enable timer */ -#define M8260_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */ -#define M8260_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */ - -#define M8260_TMR_PS(x) ((x)<<8) /* Timer prescaler */ -#define M8260_TMR_CE_RISE (1<<6) /* Capture on rising edge */ -#define M8260_TMR_CE_FALL (2<<6) /* Capture on falling edge */ -#define M8260_TMR_CE_ANY (3<<6) /* Capture on any edge */ -#define M8260_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */ -#define M8260_TMR_ORI (1<<4) /* Interrupt on reaching reference */ -#define M8260_TMR_RESTART (1<<3) /* Restart timer after reference */ -#define M8260_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */ -#define M8260_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */ -#define M8260_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */ -#define M8260_TMR_TGATE (1<<0) /* TGATE controls timer */ - -#ifdef REV_0_2 -#define M8260_PISCR_PS (1<<6) /* PIT Interrupt state */ -#else -#define M8260_PISCR_PS (1<<7) /* PIT Interrupt state */ -#endif -#define M8260_PISCR_PIE (1<<2) /* PIT interrupt enable */ -#define M8260_PISCR_PTF (1<<1) /* Stop timer when freeze asserted */ -#define M8260_PISCR_PTE (1<<0) /* PIT enable */ - -#if 0 -#define M8260_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ -#define M8260_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ -#define M8260_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ -#define M8260_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ -#define M8260_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ -#define M8260_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ -#define M8260_TBSCR_TBE (1<<0) /* enable TB and decrementer */ -#endif - -#define M8260_TMCNTSC_SEC (1<<7) /* per second flag */ -#define M8260_TMCNTSC_ALR (1<<6) /* Alarm interrupt flag */ -#define M8260_TMCNTSC_SIE (1<<3) /* per second interrupt enable */ -#define M8260_TMCNTSC_ALE (1<<2) /* Alarm interrupt enable */ -#define M8260_TMCNTSC_TCF (1<<1) /* Time count frequency */ -#define M8260_TMCNTSC_TCE (1<<0) /* Time count enable */ - -#define M8260_SIMASK_PC0 (1<<31) -#define M8260_SIMASK_PC1 (1<<30) -#define M8260_SIMASK_PC2 (1<<29) -#define M8260_SIMASK_PC3 (1<<28) -#define M8260_SIMASK_PC4 (1<<27) -#define M8260_SIMASK_PC5 (1<<26) -#define M8260_SIMASK_PC6 (1<<25) -#define M8260_SIMASK_PC7 (1<<24) -#define M8260_SIMASK_PC8 (1<<23) -#define M8260_SIMASK_PC9 (1<<22) -#define M8260_SIMASK_PC10 (1<<21) -#define M8260_SIMASK_PC11 (1<<20) -#define M8260_SIMASK_PC12 (1<<19) -#define M8260_SIMASK_PC13 (1<<18) -#define M8260_SIMASK_PC14 (1<<17) -#define M8260_SIMASK_PC15 (1<<16) -#define M8260_SIMASK_IRQ1 (1<<14) -#define M8260_SIMASK_IRQ2 (1<<13) -#define M8260_SIMASK_IRQ3 (1<<12) -#define M8260_SIMASK_IRQ4 (1<<11) -#define M8260_SIMASK_IRQ5 (1<<10) -#define M8260_SIMASK_IRQ6 (1<<9) -#define M8260_SIMASK_IRQ7 (1<<8) -#define M8260_SIMASK_TMCNT (1<<2) -#define M8260_SIMASK_PIT (1<<1) - -#define M8260_SIMASK_FCC1 (1<<31) -#define M8260_SIMASK_FCC2 (1<<30) -#define M8260_SIMASK_FCC3 (1<<29) -#define M8260_SIMASK_MCC1 (1<<27) -#define M8260_SIMASK_MCC2 (1<<26) -#define M8260_SIMASK_SCC1 (1<<23) -#define M8260_SIMASK_SCC2 (1<<22) -#define M8260_SIMASK_SCC3 (1<<21) -#define M8260_SIMASK_SCC4 (1<<20) -#define M8260_SIMASK_I2C (1<<15) -#define M8260_SIMASK_SPI (1<<14) -#define M8260_SIMASK_RTT (1<<13) -#define M8260_SIMASK_SMC1 (1<<12) -#define M8260_SIMASK_SMC2 (1<<11) -#define M8260_SIMASK_IDMA1 (1<<10) -#define M8260_SIMASK_IDMA2 (1<<9) -#define M8260_SIMASK_IDMA3 (1<<8) -#define M8260_SIMASK_IDMA4 (1<<7) -#define M8260_SIMASK_SDMA (1<<6) -#define M8260_SIMASK_TIMER1 (1<<4) -#define M8260_SIMASK_TIMER2 (1<<3) -#define M8260_SIMASK_TIMER3 (1<<2) -#define M8260_SIMASK_TIMER4 (1<<1) - -#define M8260_SIUMCR_EARB (1<<31) -#define M8260_SIUMCR_EARP0 (0<<28) -#define M8260_SIUMCR_EARP1 (1<<28) -#define M8260_SIUMCR_EARP2 (2<<28) -#define M8260_SIUMCR_EARP3 (3<<28) -#define M8260_SIUMCR_EARP4 (4<<28) -#define M8260_SIUMCR_EARP5 (5<<28) -#define M8260_SIUMCR_EARP6 (6<<28) -#define M8260_SIUMCR_EARP7 (7<<28) -#define M8260_SIUMCR_DSHW (1<<23) -#define M8260_SIUMCR_DBGC0 (0<<21) -#define M8260_SIUMCR_DBGC1 (1<<21) -#define M8260_SIUMCR_DBGC2 (2<<21) -#define M8260_SIUMCR_DBGC3 (3<<21) -#define M8260_SIUMCR_DBPC0 (0<<19) -#define M8260_SIUMCR_DBPC1 (1<<19) -#define M8260_SIUMCR_DBPC2 (2<<19) -#define M8260_SIUMCR_DBPC3 (3<<19) -#define M8260_SIUMCR_FRC (1<<17) -#define M8260_SIUMCR_DLK (1<<16) -#define M8260_SIUMCR_PNCS (1<<15) -#define M8260_SIUMCR_OPAR (1<<14) -#define M8260_SIUMCR_DPC (1<<13) -#define M8260_SIUMCR_MPRE (1<<12) -#define M8260_SIUMCR_MLRC0 (0<<10) -#define M8260_SIUMCR_MLRC1 (1<<10) -#define M8260_SIUMCR_MLRC2 (2<<10) -#define M8260_SIUMCR_MLRC3 (3<<10) -#define M8260_SIUMCR_AEME (1<<9) -#define M8260_SIUMCR_SEME (1<<8) -#define M8260_SIUMCR_BSC (1<<7) -#define M8260_SIUMCR_GB5E (1<<6) -#define M8260_SIUMCR_B2DD (1<<5) -#define M8260_SIUMCR_B3DD (1<<4) - -/* -************************************************************************* -* MPC8260 DUAL-PORT RAM AND REGISTERS * -************************************************************************* -*/ -typedef struct m8260_ { - - /* - * CPM Dual-Port RAM - */ - uint8_t dpram1[16384]; /* 0x0000 - 0x3FFF BD/data/ucode */ - uint8_t cpm_pad0[16384]; /* 0x4000 - 0x7FFF Reserved */ - - m8260SCCparms_t scc1p; - uint8_t pad_scc1[256-sizeof(m8260SCCparms_t)]; - m8260SCCparms_t scc2p; - uint8_t pad_scc2[256-sizeof(m8260SCCparms_t)]; - m8260SCCparms_t scc3p; - uint8_t pad_scc3[256-sizeof(m8260SCCparms_t)]; - m8260SCCparms_t scc4p; - uint8_t pad_scc4[256-sizeof(m8260SCCparms_t)]; - - m8260FCCparms_t fcc1p; - uint8_t pad_fcc1[256-sizeof(m8260FCCparms_t)]; - m8260FCCparms_t fcc2p; - uint8_t pad_fcc2[256-sizeof(m8260FCCparms_t)]; - m8260FCCparms_t fcc3p; - uint8_t pad_fcc3[256-sizeof(m8260FCCparms_t)]; - - uint8_t mcc1p[128]; - uint8_t pad_mcc1[124]; - uint16_t smc1_base; - uint16_t idma1_base; - uint8_t mcc2p[128]; - uint8_t pad_mcc2[124]; - uint16_t smc2_base; - uint16_t idma2_base; - uint8_t pad_spi[252]; - uint16_t spi_base; - uint16_t idma3_base; - uint8_t pad_risc[224]; - uint8_t risc_timers[16]; - uint16_t rev_num; - uint16_t cpm_pad7; - uint32_t cpm_pad8; - uint16_t rand; - uint16_t i2c_base; - uint16_t idma4_base; - uint8_t cpm_pad9[1282]; - - uint8_t cpm_pad1[8192]; /* 0x9000 - 0xAFFF Reserved */ - - m8260SMCparms_t smc1p; - m8260SMCparms_t smc2p; - uint8_t dpram3[4096-2*sizeof(m8260SMCparms_t)]; - - uint8_t cpm_pad2[16384]; /* 0xC000 - 0xFFFF Reserved */ - - - /* - * General SIU Block - */ - uint32_t siumcr; - uint32_t sypcr; - uint8_t siu_pad0[6]; - uint16_t swsr; - uint8_t siu_pad1[20]; - uint32_t bcr; - uint8_t ppc_acr; - uint8_t siu_pad4[3]; - uint32_t ppc_alrh; - uint32_t ppc_alr1; - uint8_t lcl_acr; - uint8_t siu_pad5[3]; - uint32_t lcl_alrh; - uint32_t lcl_alr1; - uint32_t tescr1; - uint32_t tescr2; - uint32_t l_tescr1; - uint32_t l_tescr2; - uint32_t pdtea; - uint8_t pdtem; - uint8_t siu_pad2[3]; - uint32_t ldtea; - uint8_t ldtem; - uint8_t siu_pad3[163]; - - - /* - * Memory Controller Block - */ - m8260MEMCRegisters_t memc[12]; - uint8_t mem_pad0[8]; - uint32_t mar; - uint8_t mem_pad1[4]; - uint32_t mamr; - uint32_t mbmr; - uint32_t mcmr; - uint32_t mdmr; - uint8_t mem_pad2[4]; - uint16_t mptpr; - uint8_t mem_pad5[2]; - uint32_t mdr; - uint8_t mem_pad3[4]; - uint32_t psdmr; - uint32_t lsdmr; - uint8_t purt; - uint8_t mem_pad6[3]; - uint8_t psrt; - uint8_t mem_pad7[3]; - uint8_t lurt; - uint8_t mem_pad8[3]; - uint8_t lsrt; - uint8_t mem_pad9[3]; - uint32_t immr; - uint8_t mem_pad4[84]; - - - /* - * System integration timers - */ - uint8_t sit_pad0[32]; - uint16_t tmcntsc; - uint8_t sit_pad6[2]; - uint32_t tmcnt; - uint32_t tmcntsec; - uint32_t tmcntal; - uint8_t sit_pad2[16]; - uint16_t piscr; - uint8_t sit_pad5[2]; - uint32_t pitc; - uint32_t pitr; - uint8_t sit_pad3[94]; - uint8_t sit_pad4[2390]; - - - /* - * Interrupt Controller - */ - uint16_t sicr; - uint8_t ict_pad1[2]; - uint32_t sivec; - uint32_t sipnr_h; - uint32_t sipnr_l; - uint32_t siprr; - uint32_t scprr_h; - uint32_t scprr_l; - uint32_t simr_h; - uint32_t simr_l; - uint32_t siexr; - uint8_t ict_pad0[88]; - - - /* - * Clocks and Reset - */ - uint32_t sccr; - uint8_t clr_pad1[4]; - uint32_t scmr; - uint8_t clr_pad2[4]; - uint32_t rsr; - uint32_t rmr; - uint8_t clr_pad0[104]; - - - /* - * Input/ Output Port - */ - uint32_t pdira; - uint32_t ppara; - uint32_t psora; - uint32_t podra; - uint32_t pdata; - uint8_t iop_pad0[12]; - uint32_t pdirb; - uint32_t pparb; - uint32_t psorb; - uint32_t podrb; - uint32_t pdatb; - uint8_t iop_pad1[12]; - uint32_t pdirc; - uint32_t pparc; - uint32_t psorc; - uint32_t podrc; - uint32_t pdatc; - uint8_t iop_pad2[12]; - uint32_t pdird; - uint32_t ppard; - uint32_t psord; - uint32_t podrd; - uint32_t pdatd; - uint8_t iop_pad3[12]; - - - /* - * CPM Timers - */ - uint8_t tgcr1; - uint8_t cpt_pad0[3]; - uint8_t tgcr2; - uint8_t cpt_pad1[11]; - uint16_t tmr1; - uint16_t tmr2; - uint16_t trr1; - uint16_t trr2; - uint16_t tcr1; - uint16_t tcr2; - uint16_t tcn1; - uint16_t tcn2; - uint16_t tmr3; - uint16_t tmr4; - uint16_t trr3; - uint16_t trr4; - uint16_t tcr3; - uint16_t tcr4; - uint16_t tcn3; - uint16_t tcn4; - uint16_t ter1; - uint16_t ter2; - uint16_t ter3; - uint16_t ter4; - uint8_t cpt_pad2[608]; - - - /* - * DMA Block - */ - uint8_t sdsr; - uint8_t dma_pad0[3]; - uint8_t sdmr; - uint8_t dma_pad1[3]; - - uint8_t idsr1; - uint8_t dma_pad2[3]; - uint8_t idmr1; - uint8_t dma_pad3[3]; - uint8_t idsr2; - uint8_t dma_pad4[3]; - uint8_t idmr2; - uint8_t dma_pad5[3]; - uint8_t idsr3; - uint8_t dma_pad6[3]; - uint8_t idmr3; - uint8_t dma_pad7[3]; - uint8_t idsr4; - uint8_t dma_pad8[3]; - uint8_t idmr4; - uint8_t dma_pad9[707]; - - - /* - * FCC Block - */ - m8260FCCRegisters_t fcc1; - m8260FCCRegisters_t fcc2; - m8260FCCRegisters_t fcc3; - - uint8_t fcc_pad0[656]; - - /* - * BRG 5-8 Block - */ - uint32_t brgc5; - uint32_t brgc6; - uint32_t brgc7; - uint32_t brgc8; - uint8_t brg_pad0[608]; - - - /* - * I2C - */ - uint8_t i2mod; - uint8_t i2m_pad0[3]; - uint8_t i2add; - uint8_t i2m_pad1[3]; - uint8_t i2brg; - uint8_t i2m_pad2[3]; - uint8_t i2com; - uint8_t i2m_pad3[3]; - uint8_t i2cer; - uint8_t i2m_pad4[3]; - uint8_t i2cmr; - uint8_t i2m_pad5[331]; - - - /* - * CPM Block - */ - uint32_t cpcr; - uint32_t rccr; - uint8_t cpm_pad3[14]; - uint16_t rter; - uint8_t cpm_pad[2]; - uint16_t rtmr; - uint16_t rtscr; - uint8_t cpm_pad4[2]; - uint32_t rtsr; - uint8_t cpm_pad5[12]; - - - /* - * BRG 1-4 Block - */ - uint32_t brgc1; - uint32_t brgc2; - uint32_t brgc3; - uint32_t brgc4; - - - /* - * SCC Block - */ - m8260SCCRegisters_t scc1; - m8260SCCRegisters_t scc2; - m8260SCCRegisters_t scc3; - m8260SCCRegisters_t scc4; - - - /* - * SMC Block - */ - m8260SMCRegisters_t smc1; - m8260SMCRegisters_t smc2; - - - /* - * SPI Block - */ - uint16_t spmode; - uint8_t spi_pad0[4]; - uint8_t spie; - uint8_t spi_pad1[3]; - uint8_t spim; - uint8_t spi_pad2[2]; - uint8_t spcom; - uint8_t spi_pad3[82]; - - - /* - * CPM Mux Block - */ - uint8_t cmxsi1cr; - uint8_t cmx_pad0[1]; - uint8_t cmxsi2cr; - uint8_t cmx_pad1[1]; - uint32_t cmxfcr; - uint32_t cmxscr; - uint8_t cmxsmr; - uint8_t cmx_pad2[1]; - uint16_t cmxuar; - uint8_t cmx_pad3[16]; - - - /* - * SI & MCC Blocks - */ - m8260SIRegisters_t si1; - m8260MCCRegisters_t mcc1; - m8260SIRegisters_t si2; - m8260MCCRegisters_t mcc2; - - uint8_t mcc_pad0[1152]; - - /* - * SI1 RAM - */ - uint8_t si1txram[512]; - uint8_t ram_pad0[512]; - uint8_t si1rxram[512]; - uint8_t ram_pad1[512]; - - - /* - * SI2 RAM - */ - uint8_t si2txram[512]; - uint8_t ram_pad2[512]; - uint8_t si2rxram[512]; - uint8_t ram_pad3[512]; - - -} m8260_t; - -extern volatile m8260_t m8260; -#endif /* ASM */ - -#endif /* _MPC8260_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h b/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h deleted file mode 100644 index 206cb87cb4..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h +++ /dev/null @@ -1,68 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS support for MPC83xx | -+-----------------------------------------------------------------+ -| Copyright (c) 2007 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file contains the MPC83xx I2C driver declarations | -\*===============================================================*/ -#ifndef _MPC83XX_I2CDRV_H -#define _MPC83XX_I2CDRV_H - -#include <rtems/libi2c.h> -#include <rtems/irq.h> - -#include <bsp.h> - -#ifdef LIBBSP_POWERPC_GEN83XX_BSP_H - #include <mpc83xx/mpc83xx.h> -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef LIBBSP_POWERPC_MPC55XXEVB_BSP_H - typedef struct { - volatile uint8_t i2cadr; - volatile uint8_t i2cfdr; - volatile uint8_t i2ccr; - volatile uint8_t i2csr; - volatile uint8_t i2cdr; - volatile uint8_t i2cdfsrr; - } m83xxI2CRegisters_t; -#endif - -typedef struct mpc83xx_i2c_softc { - m83xxI2CRegisters_t *reg_ptr; /* ptr to HW registers */ - int initialized; /* TRUE: module is initialized */ - rtems_irq_number irq_number; /* IRQ number used for this module */ - uint32_t base_frq; /* input frq for baud rate divider */ - rtems_id irq_sema_id; /* SEMA used for IRQ signalling */ - void (*probe)(struct mpc83xx_i2c_softc *self); -} mpc83xx_i2c_softc_t ; - -typedef struct { - rtems_libi2c_bus_t bus_desc; - struct mpc83xx_i2c_softc softc; -} mpc83xx_i2c_desc_t; - - -extern rtems_libi2c_bus_ops_t mpc83xx_i2c_ops; - -#ifdef __cplusplus -} -#endif - - -#endif /* _MPC83XX_I2CDRV_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/include/gtm.h b/c/src/lib/libcpu/powerpc/mpc83xx/include/gtm.h deleted file mode 100644 index a17510ed10..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc83xx/include/gtm.h +++ /dev/null @@ -1,67 +0,0 @@ -/** - * @file - * - * @brief Header file for timer functions. - */ - -/* - * Copyright (c) 2008 - * Embedded Brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * rtems@embedded-brains.de - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_MPC83XX_TIMER_H -#define LIBBSP_POWERPC_MPC83XX_TIMER_H - -#include <stdint.h> -#include <stdbool.h> - -#include <rtems.h> - -#define MPC83XX_GTM_NUMBER 8 - -#define MPC83XX_GTM_CLOCK_CASCADED 0x0000 -#define MPC83XX_GTM_CLOCK_SYSTEM 0x0002 -#define MPC83XX_GTM_CLOCK_SYSTEM_SLOW 0x0004 -#define MPC83XX_GTM_CLOCK_EXTERN 0x0006 - -rtems_status_code mpc83xx_gtm_initialize( int timer, int clock); - -rtems_status_code mpc83xx_gtm_enable_restart( int timer, bool enable); - -rtems_status_code mpc83xx_gtm_set_clock( int timer, int clock); - -rtems_status_code mpc83xx_gtm_get_clock( int timer, int *clock); - -rtems_status_code mpc83xx_gtm_start( int timer); - -rtems_status_code mpc83xx_gtm_stop( int timer); - -rtems_status_code mpc83xx_gtm_set_value( int timer, uint16_t value); - -rtems_status_code mpc83xx_gtm_get_value( int timer, uint16_t *value); - -rtems_status_code mpc83xx_gtm_set_reference( int timer, uint16_t reference); - -rtems_status_code mpc83xx_gtm_get_reference( int timer, uint16_t *reference); - -rtems_status_code mpc83xx_gtm_set_prescale( int timer, uint8_t prescale); - -rtems_status_code mpc83xx_gtm_get_prescale( int timer, uint8_t *prescale); - -rtems_status_code mpc83xx_gtm_interrupt_get_vector( int timer, rtems_vector_number *vector); - -rtems_status_code mpc83xx_gtm_interrupt_enable( int timer); - -rtems_status_code mpc83xx_gtm_interrupt_disable( int timer); - -rtems_status_code mpc83xx_gtm_interrupt_clear( int timer); - -#endif /* LIBBSP_POWERPC_MPC83XX_TIMER_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h deleted file mode 100644 index 6f7417af1c..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h +++ /dev/null @@ -1,1014 +0,0 @@ -#ifndef _MPC83XX_MPC83XX_H -#define _MPC83XX_MPC83XX_H - -#include <bspopts.h> - -#if MPC83XX_CHIP_TYPE == 8343 -#define M83xx_HAS_PCI TRUE -#define M83xx_HAS_USB1 TRUE -#elif MPC83XX_CHIP_TYPE == 8347 -#define M83xx_HAS_PCI TRUE -#define M83xx_HAS_USB1 TRUE -#define M83xx_HAS_USB2 TRUE -#elif MPC83XX_CHIP_TYPE == 8349 -#define M83xx_HAS_PCI TRUE -#define M83xx_HAS_WIDE_PCI TRUE -#define M83xx_HAS_USB1 TRUE -#define M83xx_HAS_USB2 TRUE -#elif MPC83XX_CHIP_TYPE == 8360 -#define M83xx_HAS_PCI TRUE -#define M83xx_HAS_QE TRUE -#endif - -#if !defined(ASM) - -#include <rtems.h> -#include <bsp/tsec.h> - -/* Offset Register Access Reset Section/Page */ -/* System Configuration Registers */ -typedef struct m83xxSysConRegisters_ { - volatile uint32_t immrbar; /* 0x0_00000 Internal memory map base address register R/W 0xFF40_0000 5.2.4.1/5-5 */ - uint8_t reserved0_0004[0x00008-0x00004];/* 0x0_0004 Reserved, should be cleared */ - volatile uint32_t altcbar; /* 0x0_0008 Alternate configuration base address register R/W 0x0000_0000 5.2.4.2/5-7 */ - uint8_t reserved0_000C[0x00020-0x0000C];/* 0x0_000C--0x0_001C Reserved, should be cleared */ - volatile uint32_t lblawbar0; /* 0x0_0020 LBC local access window 0 base address register R/W 0x0000_00001 5.2.4.3/5-7 */ - volatile uint32_t lblawar0; /* 0x0_0024 LBC local access window 0 attribute register R/W 0x0000_00002 5.2.4.4/5-8 */ - volatile uint32_t lblawbar1; /* 0x0_0028 LBC local access window 1 base address register R/W 0x0000_0000 5.2.4.3/5-7 */ - volatile uint32_t lblawar1; /* 0x0_002C LBC local access window 1 attribute register R/W 0x0000_0000 5.2.4.4/5-8 */ - volatile uint32_t lblawbar2; /* 0x0_0030 LBC local access window 2 base address register R/W 0x0000_0000 5.2.4.3/5-7 */ - volatile uint32_t lblawar2; /* 0x0_0034 LBC local access window 2 attribute register R/W 0x0000_0000 5.2.4.4/5-8 */ - volatile uint32_t lblawbar3; /* 0x0_0038 LBC local access window 3 base address register R/W 0x0000_0000 5.2.4.3/5-7 */ - volatile uint32_t lblawar3; /* 0x0_003C LBC local access window 3 attribute register R/W 0x0000_0000 5.2.4.4/5-8 */ - uint8_t reserved0_0040[0x00060-0x00040];/* 0x0_0040--0x0_005C Reserved, should be cleared */ - volatile uint32_t pcilawbar0; /* 0x0_0060 PCI local access window0 base address register R/W 0x0000_00003 5.2.4.5/5-9 */ - volatile uint32_t pcilawar0; /* 0x0_0064 PCI local access window0 attribute register R/W 0x0000_00004 5.2.4.6/5-10 */ - volatile uint32_t pcilawbar1; /* 0x0_0068 PCI local access window1 base address register R/W 0x0000_0000 5.2.4.5/5-9 */ - volatile uint32_t pcilawar1; /* 0x0_006C PCI local access window1 attribute register R/W 0x0000_0000 5.2.4.6/5-10 */ - uint8_t reserved0_0070[0x000A0-0x00070];/* 0x0_0070--0x0_009C Reserved, should be cleared */ - volatile uint32_t ddrlawbar0; /* 0x0_00A0 DDR local access window0 base address register R/W 0x0000_00005 5.2.4.7/5-12 */ - volatile uint32_t ddrlawar0; /* 0x0_00A4 DDR local access window0 attribute register R/W 0x0000_00006 5.2.4.8/5-13 */ - volatile uint32_t ddrlawbar1; /* 0x0_00A8 DDR local access window1 base address register R/W 0x0000_0000 5.2.4.7/5-12 */ - volatile uint32_t ddrlawar1; /* 0x0_00AC DDR local access window1 attribute register R/W 0x0000_0000 5.2.4.8/5-13 */ - uint8_t reserved0_00B0[0x00100-0x000B0];/* 0x0_00B0--0x0_0100 Reserved, should be cleared */ - volatile uint32_t sgprl; /* 0x0_0100 general purpose register low (SGPRL) R/W 0x0000_0000 5.3.2.1/5-17 */ - volatile uint32_t sgprh; /* 0x0_0104 general purpose register high (SGPRH) R/W 0x0000_0000 5.3.2.2/5-17 */ - volatile uint32_t spridr; /* 0x0_0108 part and revision ID register (SPRIDR) R 0x0000_0000 5.3.2.3/5-18 */ - uint8_t reserved0_010C[0x00110-0x0010C];/* 0x0_010C--0x0_0110 Reserved, should be cleared */ - volatile uint32_t spcr; /* 0x0_0110 priority configuration register (SPCR) R/W 0x0000_0000 5.3.2.4/5-19 */ - volatile uint32_t sicrl; /* 0x0_0114 I/O configuration register low (SICRL) R/W 0x0000_0000 5.3.2.5/5-21 */ - volatile uint32_t sicrh; /* 0x0_0118 I/O configuration register high (SICRH) R/W 0x0000_00007 5.3.2.6/5-24 */ - uint8_t reserved0_011C[0x00128-0x0011C];/* 0x0_011C--0x0_0128 Reserved */ - volatile uint32_t ddrcdr; /* 0x0_0128 control driver register (DDRCDR) R/W 0x7304_0001 5.3.2.8/5-28 */ - volatile uint32_t ddrdsr; /* 0x0_012C debug status register (DDRDSR) R 0x3300_0000 5.3.2.9/5-30 */ - uint8_t reserved0_0130[0x00150-0x00130];/* 0x0_0130--0x0_015C Reserved */ - volatile uint32_t gpr_1; /* 0x0_0150 General Purpose Register 1 (GPR_1) */ - uint8_t reserved0_0154[0x00200-0x00154];/* 0x0_0154--0x0_01FC Reserved */ -} m83xxSysConRegisters_t; -#define M83xx_SYSCON_SPCR_TBEN (1 << (31-9)) - -/* Watchdog Timer (WDT) Registers */ -typedef struct m83xxWDTRegisters_ { - uint8_t reserved0_0200[0x00204-0x00200];/* 0x0_0200 Reserved, should be cleared */ - volatile uint32_t swcrr; /* 0x0_0204 System watchdog control register R/W 0x0000_0007 5.4.4.1/5-33 */ - volatile uint32_t swcnr; /* 0x0_0208 System watchdog count register R 0x0000_FFFF 5.4.4.2/5-34 */ - uint8_t reserved0_020C[(0x0020E)-0x0020C];/* 0x0_020C Reserved, should be cleared */ - volatile uint16_t swsrr; /* 0x0_020E System watchdog service register R/W 0x0000_0000 5.4.4.3/5-34 */ -} m83xxWDTRegisters_t; - -/* Real Time Clock Module Registers (RTC) */ -typedef struct m83xxRTCRegisters_ { - volatile uint32_t rtcnr; /* 0x0_0300 Real time counter control register R/W 0x0000_0000 5.5.5.1/5-40 */ - volatile uint32_t rtldr; /* 0x0_0304 Real time counter load register R/W 0x0000_0000 5.5.5.2/5-41 */ - volatile uint32_t rtpsr; /* 0x0_0308 Real time counter prescale register R/W 0x0000_0000 5.5.5.3/5-41 */ - volatile uint32_t rtctr; /* 0x0_030C Real time counter register R 0x0000_0000 5.5.5.4/5-42 */ - volatile uint32_t rtevr; /* 0x0_0310 Real time counter event register R/W 0x0000_0000 5.5.5.5/5-42 */ - volatile uint32_t rtalr; /* 0x0_0314 Real time counter alarm register R/W 0xFFFF_FFFF 5.5.5.6/5-43 */ - uint8_t reserved0_0314[0x00320-0x00318];/* 0x0_0318--0x0_031F Reserved; should be cleared */ -} m83xxRTCRegisters_t; - - /* Periodic Interval Timer (PIT) Registers */ -typedef struct m83xxPITRegisters_ { - volatile uint32_t ptcnr; /* 0x0_0400 Periodic interval timer control register R/W 0x0000_0000 5.6.5.1/5-47 */ - volatile uint32_t ptldr; /* 0x0_0404 Periodic interval timer load register R/W 0x0000_0000 5.6.5.2/5-48 */ - volatile uint32_t ptpsr; /* 0x0_0408 Periodic interval timer prescale register R/W 0x0000_0000 5.6.5.3/5-49 */ - volatile uint32_t ptctr; /* 0x0_040C Periodic interval timer counter register R 0x0000_0000 5.6.5.4/5-49 */ - volatile uint32_t ptevr; /* 0x0_0410 Periodic interval timer event register R/W 0x0000_0000 5.6.5.5/5-50 */ - uint8_t reserved0_0414[0x00500-0x00414]; /* 0x0_0414--0x0_041F Reserved, should be cleared */ -} m83xxPITRegisters_t; - - /* Global Timers Module 1/2 */ -#define M83xxGTIdx(n) (n&3) -#define M83xxGTLowIdx(n) (n&1) -#define M83xxGTHighIdx(n) (((n)>>1)&1) -#define M83xxGTModIdx(n) (((n)>>2)&1) - -#define M83xxGTIdxCnt (4) -#define M83xxGTLowCnt (2) -#define M83xxGTHighCnt (2) -#define M83xxGTModCnt (2) - -typedef struct m83xxGTMRegisters_ { - struct { - volatile uint8_t reg; /* 0x0_0500 Timer 1+2/3+4 global timers configuration register R/W 0x00 5.7.5.1/5-57 */ - uint8_t reserved0_0501[0x00504-0x00501]; /* 0x0_0501--0x0_0503 Reserved, should be cleared */ - } gtcfr[M83xxGTHighCnt]; - uint8_t reserved0_0508[0x00510-0x00508]; /* 0x0_0508--0x0_050f Reserved, should be cleared */ - struct { - volatile uint16_t gtmdr[M83xxGTLowCnt]; /* 0x0_0510 Timer 1/2 global timers mode register R/W 0x0000 5.7.5.2/5-60 */ - volatile uint16_t gtrfr[M83xxGTLowCnt]; /* 0x0_0514 Timer 1/2 global timers reference register R/W 0x0000 5.7.5.3/5-62 */ - volatile uint16_t gtcpr[M83xxGTLowCnt]; /* 0x0_0518 Timer 1/2 global timers capture register R/W 0x0000 5.7.5.4/5-62 */ - volatile uint16_t gtcnr[M83xxGTLowCnt]; /* 0x0_051C Timer 1/2 global timers counter register R/W 0x0000 5.7.5.5/5-63 */ - } gt_tim_regs[M83xxGTHighCnt]; - volatile uint16_t gtevr[M83xxGTIdxCnt]; /* 0x0_0530 Timer 1-4 global timers event register Special 0x0000 5.7.5.6/5-63 */ - volatile uint16_t gtpsr[M83xxGTIdxCnt]; /* 0x0_0538 Timer 1-4 global timers prescale register R/W 0x0003 5.7.5.7/5-64 */ - uint8_t reserved0_0540[0x00600-0x00540]; /* 0x0_0540--0x0_05fc Reserved */ -} m83xxGTMRegisters_t; - - /* Integrated Programmable Interrupt Controller (IPIC) */ -typedef struct m83xxIPICRegisters_ { - volatile uint32_t sicfr; /* 0x0_0700 System global interrupt configuration register R/W 0x0000_0000 8.5.1/8-8 */ - volatile uint32_t sivcr; /* 0x0_0704 System global interrupt vector register R 0x0000_0000 8.5.2/8-9 */ - volatile uint32_t sipnr[2]; /* 0x0_0708 System internal interrupt pending register H/L R 0x0000_0000 8.5.3/8-11 */ - volatile uint32_t siprr[4]; /* 0x0_0710 System internal interrupt group A-D priority register R/W 0x0530_9770 8.5.4/8-14 */ - volatile uint32_t simsr[2]; /* 0x0_0720 System internal interrupt mask register H/L R/W 0x0000_0000 8.5.6/8-15 */ - uint8_t reserved0_0728[0x0072C-0x00728]; /* 0x0_072C--0x0_0728 Reserved, should be cleared */ - volatile uint32_t sepnr; /* 0x0_072C System external interrupt pending register R/W Special 8.5.8/8-18 */ - volatile uint32_t smprr[2]; /* 0x0_0730 System mixed interrupt group A/B priority register R/W 0x0530_9770 8.5.9/8-18 */ - volatile uint32_t semsr; /* 0x0_0738 System external interrupt mask register R/W 0x0000_0000 8.5.11/8-20 */ - volatile uint32_t secnr; /* 0x0_073C System external interrupt control register R/W 0x0000_0000 8.5.12/8-21 */ - volatile uint32_t sersr; /* 0x0_0740 System error status register R/W 0x0000_0000 8.5.13/8-22 */ - volatile uint32_t sermr; /* 0x0_0744 System error mask register R/W $ 8.5.14/8-23 */ - volatile uint32_t sercr; /* 0x0_0748 System error control register R/W 0x0000_0000 8.5.15/8-24 */ - uint8_t reserved0_074C[0x00750-0x0074C]; /* 0x0_074C--0x0_074F Reserved, should be cleared */ - volatile uint32_t sifcr[2]; /* 0x0_0750 System internal interrupt force register H/L R/W 0x0000_0000 8.5.16/8-25 */ - volatile uint32_t sefcr; /* 0x0_0758 System external interrupt force register R/W 0x0000_0000 8.5.17/8-26 */ - volatile uint32_t serfr; /* 0x0_075C System error force register R/W 0x0000_0000 8.5.18/8-26 */ - volatile uint32_t scvcr; /* 0x0_0760 System critical interrupt vector register R 0x0000_0000 8.5.19/8-27 */ - volatile uint32_t smvcr; /* 0x0_0764 System management interrupt vector register R 0x0000_0000 8.5.20/8-27 */ - uint8_t reserved0_0760[0x00800-0x00768]; /* 0x0_0768--0x0_07FF Reserved, should be cleared */ -} m83xxIPICRegisters_t; - -/* get vector number from vector register content */ -#define MPC83xx_VCR_TO_VEC(regval) ((regval) & 0x7f) - - - /* System Arbiter Registers */ -typedef struct m83xxARBRegisters_ { - volatile uint32_t acr; /* 0x0_0800 Arbiter configuration register R/W 0x0000_0000 6.2.1/6-2 */ - volatile uint32_t atr; /* 0x0_0804 Arbiter timers register R/W 0x00FF_00FF 6.2.2/6-4 */ - uint8_t reserved0_0808[0x0080C-0x00808]; /* 0x0_0808 Reserved, should be cleared R 0x0000_0000 */ - volatile uint32_t aer; /* 0x0_080C Arbiter event register R/W 0x0000_0000 6.2.3/6-5 */ - volatile uint32_t aidr; /* 0x0_0810 Arbiter interrupt definition register R/W 0x0000_0000 6.2.4/6-6 */ - volatile uint32_t amr; /* 0x0_0814 Arbiter mask register R/W 0x0000_0000 6.2.5/6-7 */ - volatile uint32_t aeatr; /* 0x0_0818 Arbiter event attributes register R 0x0000_0000 6.2.6/6-7 */ - volatile uint32_t aeadr; /* 0x0_081C Arbiter event address register R 0x0000_0000 6.2.7/6-9 */ - volatile uint32_t aerr; /* 0x0_0820 Arbiter event response register R/W 0x0000_0000 6.2.8/6-10 */ - uint8_t reserved0_0824[0x00900-0x00824]; /* 0x0_0824--0x0_08FF Reserved, should be cleared */ -} m83xxARBRegisters_t; - - /* Reset Module */ -typedef struct m83xxRESRegisters_ { - volatile uint32_t rcwlr; /* 0x0_0900 Reset configuration word low register R 0x0000_0000 4.5.1.1/4-32 */ - volatile uint32_t rcwhr; /* 0x0_0904 Reset configuration word high register R 0x0000_0000 4.5.1.2/4-32 */ - uint8_t reserved0_0908[0x00910-0x00908]; /* 0x0_0908--0x0_090C Reserved, should be cleared */ - volatile uint32_t rsr; /* 0x0_0910 Reset status register R/W 0x0000_0000 4.5.1.3/4-33 */ - volatile uint32_t rmr; /* 0x0_0914 Reset mode register R/W 0x0000_0000 4.5.1.4/4-34 */ - volatile uint32_t rpr; /* 0x0_0918 Reset protection register R/W 0x0000_0000 4.5.1.5/4-35 */ - volatile uint32_t rcr; /* 0x0_091C Reset control register R/W 0x0000_0000 4.5.1.6/4-36 */ - volatile uint32_t rcer; /* 0x0_0920 Reset control enable register R/W 0x0000_0000 4.5.1.7/4-36 */ - uint8_t reserved0_0924[0x00A00-0x00924]; /* 0x0_0924--0x0_09FC Reserved, should be cleared */ -} m83xxRESRegisters_t; - - /* Clock Module */ -typedef struct m83xxCLKRegisters_ { - volatile uint32_t spmr; /* 0x0_0A00 System PLL mode register R 0x0000_0000 4.5.2.1/4-37 */ - volatile uint32_t occr; /* 0x0_0A04 Output clock control register R/W 0x0000_0000 4.5.2.2/4-38 */ - volatile uint32_t sccr; /* 0x0_0A08 System clock control register R/W 0xFFFF_FFFF 4.5.2.3/4-40 */ - uint8_t reserved0_0A08[0x00B00-0x00A0C]; /* 0x0_0A0C--0x0_0AFC Reserved, should be cleared */ -} m83xxCLKRegisters_t; - /* Power Management Control Module */ -typedef struct m83xxPMCRegisters_ { - volatile uint32_t pmccr; /* 0x0_0B00 Power management controller configuration register R/W 0x0000_0000 5.8.3.1/5-69 */ - volatile uint32_t pmcer; /* 0x0_0B04 Power management controller event register R/W 0x0000_0000 5.8.3.2/5-70 */ - volatile uint32_t pmcmr; /* 0x0_0B08 Power management controller mask register R/W 0x0000_0000 5.8.3.3/5-71 */ - uint8_t reserved0_0B10[0x00C00-0x00B0C]; /* 0x0_0B0C--0x0_0BFC Reserved, should be cleared */ -} m83xxPMCRegisters_t; - /* GPIO1 Registers */ -typedef struct m83xxGPIORegisters_ { - volatile uint32_t gpdir; /* 0x0_0C00 GPIO1/2 direction register R/W 0x0000_0000 21.3.1/21-3 */ - volatile uint32_t gpdr; /* 0x0_0C04 GPIO1/2 open drain register R/W 0x0000_0000 21.3.2/21-4 */ - volatile uint32_t gpdat; /* 0x0_0C08 GPIO1/2 data register R/W 0x0000_0000 21.3.3/21-4 */ - volatile uint32_t gpier; /* 0x0_0C0C GPIO1/2 interrupt event register R/W Undefined 21.3.4/21-5 */ - volatile uint32_t gpimr; /* 0x0_0C10 GPIO1/2 interrupt mask register R/W 0x0000_0000 21.3.5/21-5 */ - volatile uint32_t gpicr; /* 0x0_0C14 GPIO1/2 external interrupt control register R/W 0x0000_0000 21.3.6/21-6 */ - uint8_t reserved0_0C1C[0x00D00-0x00C18]; /* 0x0_0C18--0x0_0CFF Reserved, should be cleared */ -} m83xxGPIORegisters_t; - - /* DLL */ -typedef struct m83xxDLLRegisters_ { - uint8_t reserved0_1000[0x01010-0x01000]; /* 0x0_1000--0x0_100F Reserved, should be cleared */ - volatile uint32_t mckenr; /* 0x0_1010 MCK enable register (MCKENR) R/W 0xFC00_0000 4.5.3/4-41 */ - uint8_t reserved0_1014[0x01100-0x01014]; /* 0x0_1014--0x0_10FF Reserved, should be cleared */ - volatile uint32_t reserved0_1100; /* 0x0_1100 Reserved. Reset value should be preserved. R/W 0x0500_0280 */ - volatile uint32_t reserved0_1104; /* 0x0_1104 Reserved. Reset value should be preserved. R/W 0x8004_0810 */ - volatile uint32_t dllovr; /* 0x0_1108 DLL override register (DLLOVR) R/W 0x0000_0000 22.4.1/22-4 */ - volatile uint32_t dllsr; /* 0x0_110C DLL status register (DLLSR) R 0x0000_0000 22.4.2/22-4 */ - volatile uint32_t dllck; /* 0x0_1110 DLL clock register (DLLCK) R/W 0xFC00_0000 22.4.3/22-5 */ - uint8_t reserved0_1110[0x01200-0x01114]; /* 0x0_1114--0x0_11FF Reserved, should be cleared */ -} m83xxDLLRegisters_t; - - /* DDR Memory Controller Memory Map */ -typedef struct m83xxDDRRegisters_ { - volatile uint32_t cs0_bnds; /* 0x0_2000 Chip select 0 memory bounds R/W 0x0000_0000 9.4.1.1/9-10 */ - uint8_t reserved0_2004[0x02008-0x02004]; /* 0x0_2004--0x0_2008 Reserved, should be cleared */ - volatile uint32_t cs1_bnds; /* 0x0_2008 Chip select 1 memory bounds R/W 0x0000_0000 */ - uint8_t reserved0_200C[0x02010-0x0200C]; /* 0x0_200C--0x0_2010 Reserved, should be cleared */ - volatile uint32_t cs2_bnds; /* 0x0_2010 Chip select 2 memory bounds R/W 0x0000_0000 */ - uint8_t reserved0_2014[0x02018-0x02014]; /* 0x0_2014--0x0_2018 Reserved, should be cleared */ - volatile uint32_t cs3_bnds; /* 0x0_2018 Chip select 3 memory bounds R/W 0x0000_0000 */ - uint8_t reserved0_201C[0x02080-0x0201C]; /* 0x0_201C--0x0_207F Reserved, should be cleared */ - volatile uint32_t cs0_config; /* 0x0_2080 Chip select 0 configuration R/W 0x0000_0000 9.4.1.2/9-11 */ - volatile uint32_t cs1_config; /* 0x0_2084 Chip select 1 configuration R/W 0x0000_0000 */ - volatile uint32_t cs2_config; /* 0x0_2088 Chip select 2 configuration R/W 0x0000_0000 */ - volatile uint32_t cs3_config; /* 0x0_208C Chip select 3 configuration R/W 0x0000_0000 */ - uint8_t reserved0_2090[0x02100-0x02090]; /* 0x0_2090--0x0_2100 Reserved, should be cleared */ - volatile uint32_t timing_cfg_3; /* 0x0_2100 DDR SDRAM timing configuration 3 R/W 0x0000_0000 9.4.1.3/9-13 */ - volatile uint32_t timing_cfg_0; /* 0x0_2104 DDR SDRAM timing configuration 0 R/W 0x0011_0105 9.4.1.4/9-14 */ - volatile uint32_t timing_cfg_1; /* 0x0_2108 DDR SDRAM timing configuration 1 R/W 0x0000_0000 9.4.1.5/9-16 */ - volatile uint32_t timing_cfg_2; /* 0x0_210C DDR SDRAM timing configuration 2 R/W 0x0000_0000 9.4.1.6/9-18 */ - volatile uint32_t ddr_sdram_cfg; /* 0x0_2110 DDR SDRAM control configuration R/W 0x0200_0000 9.4.1.7/9-20 */ - volatile uint32_t ddr_sdram_cfg_2; /* 0x0_2114 DDR SDRAM control configuration 2 R/W 0x0000_0000 9.4.1.8/9-22 */ - volatile uint32_t ddr_sdram_mode; /* 0x0;_2118 DDR SDRAM mode configuration R/W 0x0000_0000 9.4.1.9/9-24 */ - volatile uint32_t ddr_sdram_mode_2; /* 0x0_211C DDR SDRAM mode configuration 2 R/W 0x0000_0000 9.4.1.10/9-24 */ - volatile uint32_t ddr_sdram_md_cntl; /* 0x0_2120 DDR SDRAM mode control R/W 0x0000_0000 9.4.1.11/9-25 */ - volatile uint32_t ddr_sdram_interval; /* 0x0_2124 DDR SDRAM interval configuration R/W 0x0000_0000 9.4.1.12/9-27 */ - volatile uint32_t ddr_data_init; /* 0x0_2128 DDR SDRAM data initialization R/W 0x0000_0000 9.4.1.13/9-28 */ - uint8_t reserved0_212C[0x02130-0x0212C]; /* 0x0_212C Reserved $ $ */ - volatile uint32_t ddr_sdram_clk_cntl; /* 0x0_2130 DDR SDRAM clock control R/W 0x0200_0000 9.4.1.14/9-28 */ - uint8_t reserved0_2134[0x02148-0x02134]; /* 0x0_2140 Reserved $ $ */ - volatile uint32_t ddr_init_address; /* 0x0_2148 DDR training initialization address R/W 0x0000_0000 9.4.1.15/9-29 */ - uint8_t reserved0_214C[0x02BF8-0x0214C]; /* 0x0_214C Reserved $ $ */ - volatile uint32_t ddr_ip_rev1; /* 0x0_2BF8 DDR IP block revision 1 R 0x0002_0200 9.4.1.16/9-30 */ - volatile uint32_t ddr_ip_rev2; /* 0x0_2BFC DDR IP block revision 2 R 0x0000_0000 9.4.1.17/9-30 */ - uint8_t reserved0_2C00[0x02E00-0x02C00]; /* 0x0_2C00 Reserved $ $ */ - volatile uint32_t data_err_inject_hi; /* 0x0_2E00 Memory data path error injection mask high R/W 0x0000_0000 9.4.1.18/9-31 */ - volatile uint32_t data_err_inject_lo; /* 0x0_2E04 Memory data path error injection mask low R/W 0x0000_0000 9.4.1.19/9-31 */ - volatile uint32_t ecc_err_inject; /* 0x0_2E08 Memory data path error injection mask ECC R/W 0x0000_0000 9.4.1.20/9-32 */ - uint8_t reserved0_2E0C[0x02E20-0x02E0C]; /* 0x0_2E0C Reserved $ $ */ - volatile uint32_t capture_data_hi; /* 0x0_2E20 Memory data path read capture high R/W 0x0000_0000 9.4.1.21/9-32 */ - volatile uint32_t capture_data_lo; /* 0x0_2E24 Memory data path read capture low R/W 0x0000_0000 9.4.1.22/9-33 */ - volatile uint32_t capture_ecc; /* 0x0_2E28 Memory data path read capture ECC R/W 0x0000_0000 9.4.1.23/9-33 */ - uint8_t reserved0_2E2C[0x02E40-0x02E2C]; /* 0x0_2E2C Reserved $ $ */ - volatile uint32_t err_detect; /* 0x0_2E40 Memory error detect w1c 0x0000_0000 9.4.1.24/9-33 */ - volatile uint32_t err_disable; /* 0x0_2E44 Memory error disable R/W 0x0000_0000 9.4.1.25/9-34 */ - volatile uint32_t err_int_en; /* 0x0_2E48 Memory error interrupt enable R/W 0x0000_0000 9.4.1.26/9-35 */ - volatile uint32_t capture_attributes; /* 0x0_2E4C Memory error attributes capture R/W 0x0000_0000 9.4.1.27/9-36 */ - volatile uint32_t capture_address; /* 0x0_2E50 Memory error address capture R/W 0x0000_0000 9.4.1.28/9-37 */ - uint8_t reserved0_2E54[0x02E58-0x02E54]; /* 0x0_2E54 Reserved $ $ */ - volatile uint32_t err_sbe; /* 0x0_2E58 Single-Bit ECC memory error management R/W 0x0000_0000 9.4.1.29/9-37 */ - uint8_t reserved0_2E5C[0x2F00-0x2E5C]; -} m83xxDDRRegisters_t; - - /* I2C Controller */ -typedef struct m83xxI2CRegisters_ { - volatile uint8_t i2cadr; /* 0x0_3000 I2C1 address register R/W 0x00 17.3.1.1/17-5 */ - uint8_t reserved0_3001[0x03004-0x03001]; - volatile uint8_t i2cfdr; /* 0x0_3004 I2C1 frequency divider register R/W 0x00 17.3.1.2/17-5 */ - uint8_t reserved0_3005[0x03008-0x03005]; - volatile uint8_t i2ccr; /* 0x0_3008 I2C1 control register R/W 0x00 17.3.1.3/17-6 */ - uint8_t reserved0_3009[0x0300C-0x03009]; - volatile uint8_t i2csr; /* 0x0_300C I2C1 status register R/W 0x81 17.3.1.4/17-8 */ - uint8_t reserved0_300D[0x03010-0x0300D]; - volatile uint8_t i2cdr; /* 0x0_3010 I2C1 data register R/W 0x00 17.3.1.5/17-9 */ - uint8_t reserved0_3011[0x03014-0x03011]; - volatile uint8_t i2cdfsrr; /* 0x0_3014 I2C1 digital filter sampling rate register R/W 0x0001_0000 17.3.1.6/17-10 */ - uint8_t reserved0_3015[0x03018-0x03015]; - uint8_t reserved0_3018[0x03100-0x03018]; /* 0x0_3018-30FF Reserved, should be cleared */ -} m83xxI2CRegisters_t; - - /* DUART */ -typedef struct m83xxDUARTRegisters_ { - union { - volatile uint8_t urbr; /* 0x0_4500 ULCR[DLAB] = 0 UART1 receiver buffer register R 0x00 18.3.1.1/18-6 */ - volatile uint8_t uthr; /* 0x0_4500 ULCR[DLAB] = 0 UART1 transmitter holding register W 0x00 18.3.1.2/18-6 */ - volatile uint8_t udlb; /* 0x0_4500 ULCR[DLAB] = 1 UART1 divisor least significant byte register R/W 0x00 18.3.1.3/18-7 */ - } urbr_uthr_udlb; - union { - volatile uint8_t uier; /* 0x0_4501 ULCR[DLAB] = 0 UART1 interrupt enable register R/W 0x00 18.3.1.4/18-8 */ - volatile uint8_t udmb; /* 0x0_4501 ULCR[DLAB] = 1 UART1 divisor most significant byte register R/W 0x00 18.3.1.3/18-7 */ - } uier_udmb; - union { - volatile uint8_t uiir; /* 0x0_4502 ULCR[DLAB] = 0 UART1 interrupt ID register R 0x01 18.3.1.5/18-9 */ - volatile uint8_t ufcr; /* 0x0_4502 ULCR[DLAB] = 0 UART1 FIFO control register W 0x00 18.3.1.6/18-10 */ - volatile uint8_t uafr; /* 0x0_4502 ULCR[DLAB] = 1 UART1 alternate function register R/W 0x00 18.3.1.12/18-16 */ - } uiir_ufcr_uafr; - volatile uint8_t ulcr; /* 0x0_4503 ULCR[DLAB] = x UART1 line control register R/W 0x00 18.3.1.7/18-11 */ - volatile uint8_t umcr; /* 0x0_4504 ULCR[DLAB] = x UART1 MODEM control register R/W 0x00 18.3.1.8/18-13 */ - volatile uint8_t ulsr; /* 0x0_4505 ULCR[DLAB] = x UART1 line status register R 0x60 18.3.1.9/18-14 */ - volatile uint8_t umsr; /* 0x0_4506 ULCR[DLAB] = x UART1 MODEM status register R 0x00 18.3.1.10/18-15 */ - volatile uint8_t uscr; /* 0x0_4507 ULCR[DLAB] = x UART1 scratch register R/W 0x00 18.3.1.11/18-16 */ - uint8_t reserved0_4508[0x04510-0x04508];/* 0x0_4508-450F Reserved */ - volatile uint8_t udsr; /* 0x0_4510 ULCR[DLAB] = x UART1 DMA status register R 0x01 18.3.1.13/18-17 */ - uint8_t reserved0_4511[0x04600-0x04511];/* 0x0_4511-45FF Reserved */ -} m83xxDUARTRegisters_t; - - /* Local Bus Controller (LBC) Registers */ -typedef struct m83xxLBCRegisters_ { - struct { - volatile uint32_t br; /* 0x0_5000 Base register 0 ,R/W 0x0000_RR01 10.3.1.1/10-11 */ - volatile uint32_t optionsr; /* 0x0_5004 Options register 0 R/W 0x0000_0FF7 10.3.1.2/10-12 */ - } bor[8]; - uint8_t reserved0_5040[0x05068-0x05040];/* 0x0_5040-5067 Reserved */ - volatile uint32_t mar; /* 0x0_5068 UPM address register R/W 0x0000_0000 10.3.1.3/10-18 */ - uint8_t reserved0_506C[0x05070-0x0506C];/* 0x0_506C-506F Reserved */ - volatile uint32_t mamr; /* 0x0_5070 UPMA mode register R/W 0x0000_0000 10.3.1.4/10-19 */ - volatile uint32_t mbmr; /* 0x0_5074 UPMB mode register R/W 0x0000_0000 10.3.1.4/10-19 */ - volatile uint32_t mcmr; /* 0x0_5078 UPMC mode register R/W 0x0000_0000 10.3.1.4/10-19 */ - uint8_t reserved0_507C[0x05084-0x0507C];/* 0x0_507C-5083 Reserved */ - volatile uint32_t mrtpr; /* 0x0_5084 Memory refresh timer prescaler register R/W 0x0000_0000 10.3.1.5/10-21 */ - volatile uint32_t mdr; /* 0x0_5088 UPM data register R/W 0x0000_0000 10.3.1.6/10-22 */ - uint8_t reserved0_508C[0x05094-0x0508C];/* 0x0_508C-5093 Reserved */ - volatile uint32_t lsdmr; /* 0x0_5094 SDRAM mode register R/W 0x0000_0000 10.3.1.7/10-22 */ - uint8_t reserved0_5098[0x050A0-0x05098];/* 0x0_5098-509F Reserved */ - volatile uint32_t lurt; /* 0x0_50A0 UPM refresh timer R/W 0x0000_0000 10.3.1.8/10-24 */ - volatile uint32_t lsrt; /* 0x0_50A4 SDRAM refresh timer R/W 0x0000_0000 10.3.1.9/10-25 */ - uint8_t reserved0_50A8[0x050B0-0x050A8];/* 0x0_50A8-50AF Reserved */ - volatile uint32_t ltesr; /* 0x0_50B0 Transfer error status register Read/ bit-reset 0x0000_0000 10.3.1.10/10-26 */ - volatile uint32_t ltedr; /* 0x0_50B4 Transfer error check disable register R/W 0x0000_0000 10.3.1.11/10-27 */ - volatile uint32_t lteir; /* 0x0_50B8 Transfer error interrupt enable register R/W 0x0000_0000 10.3.1.12/10-27 */ - volatile uint32_t lteatr; /* 0x0_50BC Transfer error attributes register R/W 0x0000_0000 10.3.1.13/10-28 */ - volatile uint32_t ltear; /* 0x0_50C0 Transfer error address register R/W 0x0000_0000 10.3.1.14/10-29 */ - uint8_t reserved0_50C4[0x050D0-0x050C4];/* 0x0_50C4-50CF Reserved */ - volatile uint32_t lbcr; /* 0x0_50D0 Local bus configuration register R/W 0x0000_0000 10.3.1.15/10-29 */ - volatile uint32_t lcrr; /* 0x0_50D4 Clock ratio register R/W 0x8000_0008 10.3.1.16/10-30 */ - uint8_t reserved0_50D8[0x05100-0x050D8];/* 0x0_50D8-50FF Reserved */ -} m83xxLBCRegisters_t; - - /* Serial Peripheral Interface (SPI) */ -typedef struct m83xxSPIRegisters_ { - uint8_t reserved0_7000[0x07020-0x07000];/* 0x0_7000-7020 Reserved, should be cleared */ - volatile uint32_t spmode; /* 0x0_7020 SPI mode register R/W 0x0000_0000 19.4.1.1/19-9 */ - volatile uint32_t spie; /* 0x0_7024 SPI event register R/W 0x0000_0000 19.4.1.2/19-11 */ - volatile uint32_t spim; /* 0x0_7028 SPI mask register R/W 0x0000_0000 19.4.1.3/19-13 */ - volatile uint32_t spcom; /* 0x0_702C SPI command register R/W 0x0000_0000 19.4.1.4/19-14 */ - volatile uint32_t spitd; /* 0x0_7030 SPI transmit register R/W 0x0000_0000 19.4.1.5/19-14 */ - volatile uint32_t spird; /* 0x0_7034 SPI receive register R 0xFFFF_FFFF 19.4.1.6/19-15 */ - uint8_t reserved0_7038[0x07100-0x07038];/* 0x0_7038-70FF Reserved */ -} m83xxSPIRegisters_t; - /* SPIMODE register fields */ -#define MPC83XX_SPIMODE_LOOP (1 << (31- 1)) /* loopback */ -#define MPC83XX_SPIMODE_CI (1 << (31- 2)) /* clock invert */ -#define MPC83XX_SPIMODE_CP (1 << (31- 3)) /* clock phase */ -#define MPC83XX_SPIMODE_DIV16 (1 << (31- 4)) /* divide by 16 */ -#define MPC83XX_SPIMODE_REV (1 << (31- 5)) /* LSB first */ -#define MPC83XX_SPIMODE_M_S (1 << (31- 6)) /* master/slave */ -#define MPC83XX_SPIMODE_EN (1 << (31- 7)) /* enable */ -#define MPC83XX_SPIMODE_LEN(n) ((n) << (31-11)) /* length code */ -#define MPC83XX_SPIMODE_PM(n) ((n) << (31-15)) /* prescaler */ -#define MPC83XX_SPIMODE_OD (1 << (31-19)) /* open drain */ - - /* SPCOM register fields */ -#define MPC83XX_SPCOM_LST (1 << (31- 9)) /* last transfer */ - - /* SPIE/M register fields */ -#define MPC83XX_SPIE_LT (1 << (31-17)) /* last character transmitted */ -#define MPC83XX_SPIE_DNR (1 << (31-18)) /* data not ready */ -#define MPC83XX_SPIE_OV (1 << (31-19)) /* overrun */ -#define MPC83XX_SPIE_UN (1 << (31-20)) /* unterrun */ -#define MPC83XX_SPIE_MME (1 << (31-21)) /* multi-master error */ -#define MPC83XX_SPIE_NE (1 << (31-22)) /* not empty */ -#define MPC83XX_SPIE_NF (1 << (31-23)) /* not full */ - -typedef struct m83xxDMARegisters_ { - /* DMA Registers */ - uint8_t reserved0_8000[0x08030-0x08000];/* 0x0_8000-0x0_802f Reserved */ - volatile uint32_t omisr; /* 0x0_8030 Outbound message interrupt status register Special 0x0000_0000 12.4.1/12-4 */ - volatile uint32_t omimr; /* 0x0_8034 Outbound message interrupt mask register R/W 0x0000_0000 12.4.2/12-6 */ - uint8_t reserved0_8038[0x08050-0x08038];/* 0x0_8038-0x0_804f Reserved */ - volatile uint32_t imr0; /* 0x0_8050 Inbound message register 0 R/W 0x0000_0000 12.4.3/12-7 */ - volatile uint32_t imr1; /* 0x0_8054 Inbound message register 1 R/W 0x0000_0000 12.4.3/12-7 */ - volatile uint32_t omr0; /* 0x0_8058 Outbound message register 0 R/W 0x0000_0000 12.4.4/12-7 */ - volatile uint32_t omr1; /* 0x0_805C Outbound message register 1 R/W 0x0000_0000 12.4.4/12-7 */ - volatile uint32_t odr; /* 0x0_8060 Outbound doorbell register R/W 0x0000_0000 12.4.5/12-8 */ - uint8_t reserved0_8064[0x08068-0x08064];/* 0x0_8064-0x0_8067 Reserved */ - volatile uint32_t idr; /* 0x0_8068 Inbound doorbell register R/W 0x0000_0000 12.4.5/12-8 */ - uint8_t reserved0_806C[0x08080-0x0806C];/* 0x0_806C-0x0_807F Reserved */ - volatile uint32_t imisr; /* 0x0_8080 Inbound message interrupt status register R/W 0x0000_0000 12.4.6/12-9 */ - volatile uint32_t imimr; /* 0x0_8084 Inbound message interrupt mask register R/W 0x0000_0000 12.4.7/12-11 */ - uint8_t reserved0_8088[0x080A8-0x08088];/* 0x0_8088-0x0_80A7 Reserved */ - struct m83xxDMAChannelRegisters_ { - uint8_t reserved0_80A8[0x08100-0x080A8];/* 0x0_80A8-0x0_80FF Reserved */ - volatile uint32_t dmamr0; /* 0x0_8100 DMA 0 mode register R/W 0x0000_0000 12.4.8.1/12-12 */ - volatile uint32_t dmasr0; /* 0x0_8104 DMA 0 status register R/W 0x0000_0000 12.4.8.2/12-14 */ - volatile uint32_t dmacdar0; /* 0x0_8108 DMA 0 current descriptor address register R/W 0x0000_0000 12.4.8.3/12-15 */ - uint8_t reserved0_810C[0x08110-0x0810C];/* 0x0_810C-0x0_810F Reserved */ - volatile uint32_t dmasar0; /* 0x0_8110 DMA 0 source address register R/W 0x0000_0000 12.4.8.4/12-16 */ - uint8_t reserved0_8114[0x08118-0x08114];/* 0x0_8114-0x0_8117 Reserved */ - volatile uint32_t dmadar0; /* 0x0_8118 DMA 0 destination address register R/W 0x0000_0000 12.4.8.5/12-16 */ - uint8_t reserved0_811C[0x08120-0x0811C];/* 0x0_8120-0x0_811C Reserved */ - volatile uint32_t dmabcr0; /* 0x0_8120 DMA 0 byte count register R/W 0x0000_0000 12.4.8.6/12-17 */ - volatile uint32_t dmandar0; /* 0x0_8124 DMA 0 next descriptor address register R/W 0x0000_0000 12.4.8.7/12-17 */ - }chan[4]; - volatile uint32_t dmagsr; /* 0x0_82A8 DMA general status register R 0x0000_0000 12.4.8.8/12-18 */ - uint8_t reserved0_82AC[0x082FF-0x082AC]; /* 0x0_82AC-0x0_82FF Reserved, should be cleared */ -} m83xxDMARegisters_t; - -/* Registers in DMA section use little-endian byte order */ - -/* DMA mode register */ -#define MPC83XX_DMAMR_DRCNT_1 (5 << 24) -#define MPC83XX_DMAMR_DRCNT_2 (6 << 24) -#define MPC83XX_DMAMR_DRCNT_4 (7 << 24) -#define MPC83XX_DMAMR_DRCNT_8 (8 << 24) -#define MPC83XX_DMAMR_DRCNT_16 (9 << 24) -#define MPC83XX_DMAMR_DRCNT_32 (0xA << 24) - -#define MPC83XX_DMAMR_BWC_1 (0 << 21) -#define MPC83XX_DMAMR_BWC_2 (1 << 21) -#define MPC83XX_DMAMR_BWC_4 (2 << 21) -#define MPC83XX_DMAMR_BWC_8 (3 << 21) -#define MPC83XX_DMAMR_BWC_16 (4 << 21) - -#define MPC83XX_DMAMR_DMSEN (1 << 20) -#define MPC83XX_DMAMR_IRQS (1 << 19) -#define MPC83XX_DMAMR_EMSEN (1 << 18) - -#define MPC83XX_DMAMR_DAHTS_1 (0 << 16) -#define MPC83XX_DMAMR_DAHTS_2 (1 << 16) -#define MPC83XX_DMAMR_DAHTS_4 (2 << 16) -#define MPC83XX_DMAMR_DAHTS_8 (3 << 16) - -#define MPC83XX_DMAMR_SAHTS_1 (0 << 14) -#define MPC83XX_DMAMR_SAHTS_2 (1 << 14) -#define MPC83XX_DMAMR_SAHTS_4 (2 << 14) -#define MPC83XX_DMAMR_SAHTS_8 (3 << 14) - -#define MPC83XX_DMAMR_DAHE (1 << 13) -#define MPC83XX_DMAMR_SAHE (1 << 12) - -#define MPC83XX_DMAMR_PRC_PCI_READ (0 << 10) -#define MPC83XX_DMAMR_PRC_PCI_READ_LINE (1 << 10) -#define MPC83XX_DMAMR_PRC_PCI_READ_MULTIPLE (2 << 10) - -#define MPC83XX_DMAMR_EOIIE (1 << 7) -#define MPC83XX_DMAMR_TEM (1 << 3) -#define MPC83XX_DMAMR_CTM (1 << 2) -#define MPC83XX_DMAMR_CC (1 << 1) -#define MPC83XX_DMAMR_CS (1 << 0) - -/* DMA status register */ -#define MPC83XX_DMASR_TE (1 << 7) -#define MPC83XX_DMASR_CB (1 << 2) -#define MPC83XX_DMASR_EOSI (1 << 1) -#define MPC83XX_DMASR_EOCDI (1 << 0) - -/* DMA current descriptor address register */ -#define MPC83XX_DMACDAR_SNEN (1 << 4) -#define MPC83XX_DMACDAR_EOSIE (1 << 3) - -/* DMA next descriptor address register */ -#define MPC83XX_DMANDAR_NSNEN (1 << 4) -#define MPC83XX_DMANDAR_NEOSIE (1 << 3) -#define MPC83XX_DMANDAR_EOTD (1 << 0) - - -typedef struct m83xxPCICfgRegisters_ { - /* PCI1 Software Configuration Registers */ - volatile uint32_t config_address; /* 0x0_8300 PCI1 CONFIG_ADDRESS W 13.3.1.1/13-16 */ - volatile uint32_t config_data; /* 0x0_8304 PCI1 CONFIG_DATA R/W 13.3.1.2/13-18 */ - volatile uint32_t int_ack; /* 0x0_8308 PCI1 INT_ACK R 13.3.1.3/13-18 */ - uint8_t reserved0_830C[0x08380-0x0830C]; /* 0x0_830C-0x0_837F Reserved */ -} m83xxPCICfgRegisters_t; - -typedef struct m83xxPCIIosRegisters_ { - /* Sequencer (IOS) */ - volatile uint32_t potar0; /* 0x0_8400 PCI outbound translation address register 0 R/W 0x0000_0000 11.4.1/11-3 */ - uint8_t reserved0_8404[0x08408-0x08404];/* 0x0_8404 Reserved */ - volatile uint32_t pobar0; /* 0x0_8408 PCI outbound base address register 0 R/W 0x0000_0000 11.4.2/11-3 */ - uint8_t reserved0_840C[0x08410-0x0840C];/* 0x0_840C Reserved */ - volatile uint32_t pocmr0; /* 0x0_8410 PCI outbound comparison mask register 0 R/W 0x0000_0000 11.4.3/11-4 */ - uint8_t reserved0_8414[0x08418-0x08414];/* 0x0_8414 Reserved */ - volatile uint32_t potar1; /* 0x0_8418 PCI outbound translation address register 1 R/W 0x0000_0000 11.4.1/11-3 */ - uint8_t reserved0_841C[0x08420-0x0841C];/* 0x0_841C Reserved */ - volatile uint32_t pobar1; /* 0x0_8420 PCI outbound base address register 1 R/W 0x0000_0000 11.4.2/11-3 */ - uint8_t reserved0_8424[0x08428-0x08424];/* 0x0_8424 Reserved */ - volatile uint32_t pocmr1; /* 0x0_8428 PCI outbound comparison mask register 1 R/W 0x0000_0000 11.4.3/11-4 */ - uint8_t reserved0_842C[0x08430-0x0842C];/* 0x0_842C Reserved */ - volatile uint32_t potar2; /* 0x0_8430 PCI outbound translation address register 2 R/W 0x0000_0000 11.4.1/11-3 */ - uint8_t reserved0_8434[0x08438-0x08434];/* 0x0_8434 Reserved */ - volatile uint32_t pobar2; /* 0x0_8438 PCI outbound base address register 2 R/W 0x0000_0000 11.4.2/11-3 */ - uint8_t reserved0_843C[0x08440-0x0843C];/* 0x0_843C Reserved */ - volatile uint32_t pocmr2; /* 0x0_8440 PCI outbound comparison mask register 2 R/W 0x0000_0000 11.4.3/11-4 */ - uint8_t reserved0_8444[0x08448-0x08444];/* 0x0_8444 Reserved */ - volatile uint32_t potar3; /* 0x0_8448 PCI outbound translation address register 3 R/W 0x0000_0000 11.4.1/11-3 */ - uint8_t reserved0_844C[0x08450-0x0844C];/* 0x0_844C Reserved */ - volatile uint32_t pobar3; /* 0x0_8450 PCI outbound base address register 3 R/W 0x0000_0000 11.4.2/11-3 */ - uint8_t reserved0_8454[0x08458-0x08454];/* 0x0_8454 Reserved */ - volatile uint32_t pocmr3; /* 0x0_8458 PCI outbound comparison mask register 3 R/W 0x0000_0000 11.4.3/11-4 */ - uint8_t reserved0_845C[0x08460-0x0845C];/* 0x0_845C Reserved */ - volatile uint32_t potar4; /* 0x0_8460 PCI outbound translation address register 4 R/W 0x0000_0000 11.4.1/11-3 */ - uint8_t reserved0_8464[0x08468-0x08464];/* 0x0_8464 Reserved */ - volatile uint32_t pobar4; /* 0x0_8468 PCI outbound base address register 4 R/W 0x0000_0000 11.4.2/11-3 */ - uint8_t reserved0_846C[0x08470-0x0846C];/* 0x0_846C Reserved */ - volatile uint32_t pocmr4; /* 0x0_8470 PCI outbound comparison mask register 4 R/W 0x0000_0000 11.4.3/11-4 */ - uint8_t reserved0_8474[0x08478-0x08474];/* 0x0_8474 Reserved */ - volatile uint32_t potar5; /* 0x0_8478 PCI outbound translation address register 5 R/W 0x0000_0000 11.4.1/11-3 */ - uint8_t reserved0_847C[0x08480-0x0847C];/* 0x0_847C Reserved */ - volatile uint32_t pobar5; /* 0x0_8480 PCI outbound base address register 5 R/W 0x0000_0000 11.4.2/11-3 */ - uint8_t reserved0_8484[0x08488-0x08484];/* 0x0_8484 Reserved */ - volatile uint32_t pocmr5; /* 0x0_8488 PCI outbound comparison mask register 5 R/W 0x0000_0000 11.4.3/11-4 */ - uint8_t reserved0_848C[0x084F0-0x0848C];/* 0x0_848C Reserved */ - volatile uint32_t pmcr; /* 0x0_84F0 Power management control register R/W 0x0000_0000 11.4.4/11-5 */ - uint8_t reserved0_84F4[0x084F8-0x084F4];/* 0x0_84F4 Reserved */ - volatile uint32_t dtcr; /* 0x0_84F8 Discard timer control register R/W 0x0000_0000 11.4.5/11-6 */ - uint8_t reserved0_84FC[0x08500-0x084FC];/* 0x0_84FC Reserved */ -} m83xxPCIIosRegisters_t; - -typedef struct m83xxPCICtrlRegisters_ { - /* PCI1 Error Management Registers */ - volatile uint32_t pci_esr; /* 0x0_8500 PCI error status register R / w1c 0x0000_0000 13.3.2.1/13-18 */ - volatile uint32_t pci_ecdr; /* 0x0_8504 PCI error capture disable register R/W 0x0000_0000 13.3.2.2/13-19 */ - volatile uint32_t pci_eer; /* 0x0_8508 PCI error enable register R/W 0x0000_0000 13.3.2.3/13-20 */ - volatile uint32_t pci_eatcr; /* 0x0_850C PCI error attributes capture register R/W 0x0000_0000 13.3.2.4/13-21 */ - volatile uint32_t pci_eacr; /* 0x0_8510 PCI error address capture register R 0x0000_0000 13.3.2.5/13-23 */ - volatile uint32_t pci_eeacr; /* 0x0_8514 PCI error extended address capture register R 0x0000_0000 13.3.2.6/13-23 */ - volatile uint32_t pci_edlcr; /* 0x0_8518 PCI error data low capture register R 0x0000_0000 13.3.2.7/13-24 */ - volatile uint32_t pci_edhcr; /* 0x0_851C PCI error data high capture register R 0x0000_0000 13.3.2.8/13-24 */ - /* PCI1 Control and Status Registers */ - volatile uint32_t pci_gcr; /* 0x0_8520 PCI general control register R/W 0x0000_0000 13.3.2.9/13-24 */ - volatile uint32_t pci_ecr; /* 0x0_8524 PCI error control register R/W 0x0000_0000 13.3.2.10/13-25 */ - volatile uint32_t pci_gsr; /* 0x0_8528 PCI general status register R 0x0000_0000 13.3.2.11/13-26 */ - uint8_t reserved0_852C[0x08538-0x0852C];/* 0x0_852C Reserved */ - /* PCI1 Inbound ATU Registers */ - volatile uint32_t pitar2; /* 0x0_8538 PCI inbound translation address register 2 R/W 0x0000_0000 13.3.2.12/13-26 */ - uint8_t reserved0_853C[0x08540-0x0853C];/* 0x0_853C Reserved, should be cleared $ $ */ - volatile uint32_t pibar2; /* 0x0_8540 PCI inbound base address register 2 R/W 0x0000_0000 13.3.2.13/13-27 */ - volatile uint32_t piebar2; /* 0x0_8544 PCI inbound extended base address register 2 R/W 0x0000_0000 13.3.2.14/13-27 */ - volatile uint32_t piwar2; /* 0x0_8548 PCI inbound window attributes register 2 R/W 0x0000_0000 13.3.2.15/13-28 */ - uint8_t reserved0_854C[0x08550-0x0854C];/* 0x0_854C Reserved */ - volatile uint32_t pitar1; /* 0x0_8550 PCI inbound translation address register 1 R/W 0x0000_0000 13.3.2.12/13-26 */ - uint8_t reserved0_8550[0x08558-0x08554];/* 0x0_8554 Reserved, should be cleared $ $ */ - volatile uint32_t pibar1; /* 0x0_8558 PCI inbound base address register 1 R/W 0x0000_0000 13.3.2.13/13-27 */ - volatile uint32_t piebar1; /* 0x0_855C PCI inbound extended base address register 1 R/W 0x0000_0000 13.3.2.14/13-27 */ - volatile uint32_t piwar1; /* 0x0_8560 PCI inbound window attributes register 1 R/W 0x0000_0000 13.3.2.15/13-28 */ - uint8_t reserved0_8564[0x08568-0x08564];/* 0x0_8564 Reserved */ - volatile uint32_t pitar0; /* 0x0_8568 PCI inbound translation address register 0 R/W 0x0000_0000 13.3.2.12/13-26 */ - uint8_t reserved0_856c[0x08570-0x0856c];/* 0x0_856C Reserved, should be cleared $ $ */ - volatile uint32_t pibar0; /* 0x0_8570 PCI inbound base address register 0 R/W 0x0000_0000 13.3.2.13/13-27 */ - uint8_t reserved0_8574[0x08578-0x08574];/* 0x0_8574 Reserved */ - volatile uint32_t piwar0; /* 0x0_8578 PCI inbound window attributes register 0 R/W 0x0000_0000 13.3.2.14/13-27 */ - uint8_t reserved0_857c[0x08580-0x0857c];/* 0x0_857C Reserved, should be cleared $ $ */ - uint8_t reserved0_8580[0x08600-0x08580];/* 0x0_8580 Reserved */ -} m83xxPCICtrlRegisters_t; - -typedef struct m83xxUSB_MPHRegisters_ { - /* USB MPH Controller Registers */ - uint8_t reserved0x2_2000[0x22100-0x22000]; /* 0x2_2000--0x2_20FF Reserved, should be cleared */ - volatile uint16_t caplength; /* 0x2_2100 Capability register length R 0x40 16.3.1.1/16-19 */ - volatile uint16_t hciversion; /* 0x2_2102 Host interface version number R 0x0100 16.3.1.2/16-19 */ - volatile uint32_t hcsparams; /* 0x2_2104 Host crtl. structural parameters R 0x0121_0012 16.3.1.3/16-20 */ - volatile uint32_t hccparams; /* 0x2_2108 Host crtl. capability parameters R 0x0000_0006 16.3.1.4/16-21 */ - uint8_t reserved0x2_210C[0x22140-0x2210C]; /* Reserved */ - volatile uint32_t usbcmd; /* 0x2_2140 USB command R/W 0x0008_nBn0 16.3.2.1/16-23 */ - volatile uint32_t usbsts; /* 0x2_2144 USB status R/W 0x0000_0000 16.3.2.2/16-26 */ - volatile uint32_t usbintr; /* 0x2_2148 USB interrupt enable R/W 0x0000_0000 16.3.2.3/16-28 */ - volatile uint32_t frindex; /* 0x2_214C USB frame index R/W 0x0000_nnnn 16.3.2.4/16-30 */ - uint8_t reserved0x2_2150[0x22154-0x22150]; /* Reserved */ - volatile uint32_t periodiclistbase; /* 0x2_2154 Frame list base address R/W 0xnnnn_0000 16.3.2.6/16-31 */ - volatile uint32_t asynclistaddr; /* 0x2_2158 Next asynchronous list addr R/W 0x0000_0000 16.3.2.8/16-32 */ - volatile uint32_t asyncttsts; /* 0x2_215C Asynchronous buffer status for embedded TT TBD 0x0000_0000 16.3.2.10/16-34 */ - volatile uint32_t burstsize; /* 0x2_2160 Programmable burst size R/W 0x000_1010 16.3.2.11/16-34 */ - volatile uint32_t txfilltuning; /* 0x2_2164 Host TT transmit pre-buffer packet tuning R/W 0x0002_0000 16.3.2.12/16-35 */ - volatile uint32_t txttfilltuning; /* 0x2_2168 Host TT transmit pre-buffer packet tuning R/W 0x0000_0000 16.3.2.13/16-37 */ - uint8_t reserved0x2_216c[0x22170-0x2216c]; /* Reserved */ - volatile uint32_t viewport; /* 0x2_2170 ULPI ULPI Register Access R/W 0x0000_0000 16.3.2.14/16-37 */ - uint8_t reserved0x2_2174[0x22180-0x22174]; /* Reserved */ - volatile uint32_t configflag; /* 0x2_2180 Configured flag register R 0x0000_0001 16.3.2.15/16-39 */ - volatile uint32_t portsc1; /* 0x2_2184 Port status/control 1 R/W 0x8C00_0001 16.3.2.16/16-39 */ - volatile uint32_t portsc2; /* 0x2_2188 Port status/control 2 R/W 0x8C00_0001 16.3.2.16/16-39 */ - uint8_t reserved0x2_218c[0x221A8-0x2218c]; /* Reserved */ - volatile uint32_t usbmode; /* 0x2_21A8 USB device mode R/W 0x0000_0003 16.3.2.18/16-47 */ - uint8_t reserved0x2_21AC[0x22400-0x221AC]; /* Reserved */ - volatile uint32_t snoop1; /* 0x2_2400 Snoop 1 R/W 0x0000_0000 16.3.2.26/16-53 */ - volatile uint32_t snoop2; /* 0x2_2404 Snoop 2 R/W 0x0000_0000 16.3.2.26/16-53 */ - volatile uint32_t age_cnt_thresh; /* 0x2_2408 Age count threshold R/W 0x0000_0000 16.3.2.27/16-54 */ - volatile uint32_t si_ctrl; /* 0x2_240C System interface control R/W 0x0000_0000 16.3.2.28/16-56 */ - volatile uint32_t pri_ctrl; /* 0x2_2410 Priority control R/W 0x0000_0000 16.3.2.29/16-56 */ - uint8_t reserved0x2_2414[0x22500-0x22414]; /* Reserved */ - volatile uint32_t control; /* 0x2_2500 Control R/W 0x0000_0000 16.3.2.30/16-57 */ - uint8_t reserved0x2_2504[0x23000-0x22504]; /* 0x2_2504--0x2_2FFF Reserved, should be cleared */ -} m83xxUSB_MPHRegisters_t; - -typedef struct m83xxUSB_DRRegisters_ { - /* USB DR Controller Registers */ - uint8_t reserved0x2_3000[0x23100-0x23000]; /* 0x2_3000--0x2_30FF Reserved, should be cleared */ - volatile uint16_t caplength; /* 0x2_3100 Capability register length R 0x40 16.3.1.1/16-19 */ - volatile uint16_t hciversion; /* 0x2_3102 Host interface version number R 0x0100 16.3.1.2/16-19 */ - volatile uint32_t hcsparams; /* 0x2_3104 Host crtl. structural parameters R 0x0111_0011 16.3.1.3/16-20 */ - volatile uint32_t hccparams; /* 0x2_3108 Host crtl. capability parameters R 0x0000_0006 16.3.1.4/16-21 */ - uint8_t reserved0x2_310c[0x23120-0x2310C]; /* 0x2_310c--0x2_311f Reserved */ - volatile uint32_t dciversion; /* 0x2_3120 Device interface version number R 0x0001 16.3.1.5/16-22 */ - volatile uint32_t dccparams; /* 0x2_3124 Device controller parameters R 0x0000_0186 16.3.1.6/16-22 */ - uint8_t reserved0x2_3128[0x23140-0x23128]; /* 0x2_3128--0x2_313f Reserved */ - volatile uint32_t usbcmd; /* 0x2_3140 USB command R/W 0x0008_nBn0 16.3.2.1/16-23 */ - volatile uint32_t usbsts; /* 0x2_3144 USB status R/W 0x0000_0000 16.3.2.2/16-26 */ - volatile uint32_t usbintr; /* 0x2_3148 USB interrupt enable R/W 0x0000_0000 16.3.2.3/16-28 */ - volatile uint32_t frindex; /* 0x2_314C USB frame index R/W 0x0000_nnnn 16.3.2.4/16-30 */ - uint8_t reserved0x2_3150[0x23154-0x23150]; /* 0x2_3150--0x2_3153 Reserved */ - union { - volatile uint32_t periodiclistbase; /* 0x2_3154 Frame list base address R/W 0xnnnn_0000 16.3.2.6/16-31 */ - volatile uint32_t deviceaddr; /* 0x2_3154 USB device address R/W 0x0000_0000 16.3.2.7/16-32 */ - } perbase_devaddr; - union { - volatile uint32_t asynclistaddr; /* 0x2_3158 Next asynchronous list addr (host mode) R/W 0x0000_0000 16.3.2.8/16-32 */ - volatile uint32_t addr; /* 0x2_3158 ENDPOINT Address at endpoint list (device mode) R/W 0x0000_0000 16.3.2.9/16-33 */ - } async_addr; - uint8_t reserved0x2_315c[0x23160-0x2315c]; /* 0x2_315c--0x2_315f Reserved */ - volatile uint32_t burstsize; /* 0x2_3160 Programmable burst size R/W 0x0000_1010 16.3.2.11/16-34 */ - volatile uint32_t txfilltuning; /* 0x2_3164 Host TT transmit pre-buffer packet tuning R/W 0x0002_0000 16.3.2.12/16-35 */ - uint8_t reserved0x2_3168[0x23170-0x23168]; /* 0x2_3168--0x2_316f Reserved */ - volatile uint32_t viewport; /* 0x2_3170 ULPI ULPI Register Access R/W 0x0000_0000 16.3.2.14/16-37 */ - uint8_t reserved0x2_3174[0x23180-0x23174]; /* 0x2_3174--0x2_317F Reserved */ - volatile uint32_t configflag; /* 0x2_3180 Configured flag register R 0x0000_0001 16.3.2.15/16-39 */ - volatile uint32_t portsc1; /* 0x2_3184 Port status/control R/W 0x9C00_0000 16.3.2.16/16-39 */ - uint8_t reserved0x2_3188[0x231A4-0x23188]; /* 0x2_3188--0x2_31A3 Reserved */ - volatile uint32_t otgsc; /* 0x2_31A4 On-the-Go status and control R/W 0x0000_0001 16.3.2.17/16-44 */ - volatile uint32_t usbmode; /* 0x2_31A8 USB device mode R/W 0x0000_0000 16.3.2.18/16-47 */ - volatile uint32_t endptsetupstat; /* 0x2_31AC Endpoint setup status R/W 0x0000_0000 16.3.2.19/16-48 */ - volatile uint32_t endpointprime; /* 0x2_31B0 Endpoint initialization R/W 0x0000_0000 16.3.2.20/16-48 */ - volatile uint32_t endptflush; /* 0x2_31B4 Endpoint de-initialize R/W 0x0000_0000 16.3.2.21/16-49 */ - volatile uint32_t endptstatus; /* 0x2_31B8 Endpoint status R 0x0000_0000 16.3.2.22/16-50 */ - volatile uint32_t endptcomplete; /* 0x2_31BC Endpoint complete R/W 0x0000_0000 16.3.2.23/16-50 */ - volatile uint32_t endptctrl[6]; /* 0x2_31C0 Endpoint control 0 R/W 0x0080_0080 16.3.2.24/16-51 */ - uint8_t reserved0x2_31D8[0x23400-0x231D8]; /* 0x2_31D8--0x2_33ff Reserved */ - volatile uint32_t snoop1; /* 0x2_3400 Snoop 1 R/W 0x0000_0000 16.3.2.26/16-53 */ - volatile uint32_t snoop2; /* 0x2_3404 Snoop 2 R/W 0x0000_0000 16.3.2.26/16-53 */ - volatile uint32_t age_cnt_thresh; /* 0x2_3408 Age count threshold R/W 0x0000_0000 16.3.2.27/16-54 */ - volatile uint32_t pri_ctrl; /* 0x2_340C Priority control R/W 0x0000_0000 16.3.2.29/16-56 */ - volatile uint32_t si_ctrl; /* 0x2_3410 System interface control R/W 0x0000_0000 16.3.2.28/16-56 */ - uint8_t reserved0x2_3414[0x23500-0x23414]; /* 0x2_3414--0x2_34ff Reserved */ - volatile uint32_t control; /* 0x2_3500 Control R/W 0x0000_0000 16.3.2.30/16-57 */ - uint8_t reserved0x2_3504[0x24000-0x23504]; /* 0x2_3504--0x2_3FFF Reserved, should be cleared */ -} m83xxUSB_DRRegisters_t; - -#if 0 /* FIXME: to be formatted soon */ - /* Security Engine Address Map Registers */ - /* Controller Registers */ - volatile uint32_t reserved;## /* 0x3_0000--0x3_0FFF Reserved, should be cleared */ - volatile uint32_t imr; /* 0x3_1008 Interrupt mask register R/W 0x0000_0000_0000_0000 14.7.2.1/14-94 */ - volatile uint32_t isr; /* 0x3_1010 Interrupt status register R 0x0000_0000_0000_0000 14.7.2.2/14-96 */ - volatile uint32_t icr; /* 0x3_1018 Interrupt clear register W 0x0000_0000_0000_0000 14.7.2.3/14-96 */ - volatile uint32_t id; /* 0x3_1020 Identification register R 0x0000_0000_0000_00400x 14.7.2.4/14-98 */ - volatile uint32_t euasr; /* 0x3_1028 EU assignment status register R 0xF0F0_F0F0_00FF_F0F0 14.7.2/14-93 */ - volatile uint32_t mcr; /* 0x3_1030 Master control register R/W 0000_0000_0000_0000 14.7.2.5/14-98 */ - /* Channel 1 */ - volatile uint32_t cccr1; /* 0x3_1108 Crypto-channel 1 configuration register R/W 0x0000_0000_0000_0000 14.6.1.1/14-82 */ - volatile uint32_t ccpsr1; /* 0x3_1110 Crypto-channel 1 pointer status register R 0x0000_0000_0000_0007 14.6.1.2/14-85 */ - volatile uint32_t cdpr1; /* 0x3_1140 Crypto-channel 1 current descriptor pointer register R 0x0000_0000_0000_0000 14.6.1.3/14-90 */ - volatile uint32_t */ -0x3_1180--0x3_11BF - DBn /* volatile; uint32_t ff1, /* 0x3_1148 Crypto-channel 1 fetch FIFO address register W 0x0000_0000_0000_0000 14.6.1.4/14-90 Crypto-channel 1 descriptor buffers [0–7] R 0x0000_0000_0000_0000 14.6.1.5/14-91 */ - /* Channel 2-4: FIXME: same layout as channel 1*/ - /* Data Encryption Standard Execution Unit (DEU) */ - volatile uint32_t deumr; /* 0x3_2000 DEU mode register R/W 0x0000_0000_0000_0000 14.5.2.1/14-35 */ - volatile uint32_t deuksr; /* 0x3_2008 DEU key size register R/W 0x0000_0000_0000_0000 14.5.2.2/14-36 */ - volatile uint32_t deudsr; /* 0x3_2010 DEU data size register R/W 0x0000_0000_0000_0000 14.5.2.3/14-36 */ - volatile uint32_t deurcr; /* 0x3_2018 DEU reset control register R/W 0x0000_0000_0000_0000 14.5.2.4/14-37 */ - volatile uint32_t deusr; /* 0x3_2028 DEU status register R 0x0000_0000_0000_0000 14.5.2.5/14-37 */ - volatile uint32_t deuisr; /* 0x3_2030 DEU interrupt status register R 0x0000_0000_0000_0000 14.5.2.6/14-38 */ - volatile uint32_t deuicr; /* 0x3_2038 DEU interrupt control register R/W 0x0000_0000_0000_3000 14.5.2.7/14-40 */ - volatile uint32_t deueug; /* 0x3_2050 DEU EU-Go register W 0x0000_0000_0000_0000 14.5.2.8/14-41 */ - volatile uint32_t deuiv; /* 0x3_2100 DEU initialization vector register R/W 0x0000_0000_0000_0000 14.5.2.9/14-42 */ - volatile uint32_t deuk1; /* 0x3_2400 DEU key 1 register W $ 14.5.2.10/14-42 */ - volatile uint32_t deuk2; /* 0x3_2408 DEU key 2 register W $ 14.5.2.10/14-42 */ - volatile uint32_t deuk3; /* 0x3_2410 DEU key 3 register W $ 14.5.2.10/14-42 */ -0x3_2800--0x3_2FFF -DEU FIFO R/W 0x0000_0000_0000_0000 14.5.2.11/14-42 - /* Advanced Encryption Standard Execution Unit (AESU) */ - volatile uint32_t aesumr; /* 0x3_4000 AESU mode register R/W 0x0000_0000_0000_0000 14.5.6.1/14-68 */ - volatile uint32_t aesuksr; /* 0x3_4008 AESU key size register R/W 0x0000_0000_0000_0000 14.5.6.2/14-71 */ - volatile uint32_t aesudsr; /* 0x3_4010 AESU data size register R/W 0x0000_0000_0000_0000 14.5.6.3/14-71 */ - volatile uint32_t aesurcr; /* 0x3_4018 AESU reset control register R/W 0x0000_0000_0000_0000 14.5.6.4/14-72 */ - volatile uint32_t aesusr; /* 0x3_4028 AESU status register R 0x0000_0000_0000_0000 14.5.6.5/14-73 */ - volatile uint32_t aesuisr; /* 0x3_4030 AESU interrupt status register R 0x0000_0000_0000_0000 14.5.6.6/14-74 */ - volatile uint32_t aesuicr; /* 0x3_4038 AESU interrupt control register R/W 0x0000_0000_0000_1000 14.5.6.7/14-75 */ - volatile uint32_t aesuemr; /* 0x3_4050 AESU end-of-message register W 0x0000_0000_0000_0000 14.5.6.8/14-76 */ -0x3_4100 AESU context memory registers R/W 0x0000_0000_0000_0000 14.5.6.9/14-77 -0x3_4400--0x3_4408 -AESU key memory R/W 0x0000_0000_0000_0000 14.5.6.9.5/14-81 -0x3_4800--0x3_4FFF -AESU FIFO R/W 0x0000_0000_0000_0000 14.5.6.9.6/14-81 - /* Message Digest Execution Unit (MDEU) */ - volatile uint32_t mdeumr; /* 0x3_6000 MDEU mode register R/W 0x0000_0000_0000_0000 14.5.4.1/14-51 */ - volatile uint32_t mdeuksr; /* 0x3_6008 MDEU key size register R/W 0x0000_0000_0000_0000 14.5.4.3/14-55 */ - volatile uint32_t mdeudsr; /* 0x3_6010 MDEU data size register R/W 0x0000_0000_0000_0000 14.5.4.4/14-56 */ - volatile uint32_t mdeurcr; /* 0x3_6018 MDEU reset control register R/W 0x0000_0000_0000_0000 14.5.4.5/14-56 */ - volatile uint32_t mdeusr; /* 0x3_6028 MDEU status register R 0x0000_0000_0000_0000 14.5.4.6/14-57 */ - volatile uint32_t mdeuisr; /* 0x3_6030 MDEU interrupt status register R 0x0000_0000_0000_0000 14.5.4.7/14-58 */ - volatile uint32_t mdeuicr; /* 0x3_6038 MDEU interrupt control register R/W 0x0000_0000_0000_1000 14.5.4.8/14-59 */ - volatile uint32_t mdeueug; /* 0x3_6050 MDEU EU-Go register W 0x0000_0000_0000_0000 14.5.4.10/14-61 */ -0x3_6100--0x3_6120 -MDEU context memory registers R/W 0x0000_0000_0000_0000 14.5.4.11/14-61 -0x3_6400--0x3_647F -MDEU key memory W 0x0000_0000_0000_0000 14.5.4.12/14-62 -0x3_6800--0x3_6FFF -MDEU FIFO W 0x0000_0000_0000_0000 14.5.4.13/14-63 - /* ARC Four Execution Unit (AFEU) */ - volatile uint32_t afeumr; /* 0x3_8000 AFEU mode register R/W 0x0000_0000_0000_0000 14.5.3.1/14-43 */ - volatile uint32_t afeuksr; /* 0x3_8008 AFEU key size register R/W 0x0000_0000_0000_0000 14.5.3.3/14-44 */ - volatile uint32_t afeudsr; /* 0x3_8010 AFEU data size register R/W 0x0000_0000_0000_0000 14.5.3.4/14-45 */ - volatile uint32_t afeurcr; /* 0x3_8018 AFEU reset control register R/W 0x0000_0000_0000_0000 14.5.3.5/14-46 */ - volatile uint32_t afeusr; /* 0x3_8028 AFEU status register R 0x0000_0000_0000_0000 14.5.3.6/14-46 */ - volatile uint32_t afeuisr; /* 0x3_8030 AFEU interrupt status register R 0x0000_0000_0000_0000 14.5.3.7/14-47 */ - volatile uint32_t afeuicr; /* 0x3_8038 AFEU interrupt control register R/W 0x0000_0000_0000_1000 14.5.3.8/14-49 */ - volatile uint32_t afeuemr; /* 0x3_8050 AFEU end of message register W 0x0000_0000_0000_0000 14.5.3.9/14-50 */ -0x3_8100--0x3_81FF -AFEU context memory registers R/W 0x0000_0000_0000_0000 14.5.3.10.1/14-50 -0x3_8200 AFEU context memory pointers R/W 0x0000_0000_0000_0000 14.5.3.10.2/14-51 - volatile uint32_t afeuk0; /* 0x3_8400 AFEU key register 0 W $ 14.5.3.11/14-51 */ - volatile uint32_t afeuk1; /* 0x3_848 AFEU key register 1 W $ 14.5.3.11/14-51 */ -0x3_8800--0x3_8FFF -AFEU FIFO R/W 0x0000_0000_0000_0000 14.5.3.11.1/14-51 - /* Random Number Generator (RNG) */ - volatile uint32_t rngmr; /* 0x3_A000 RNG mode register R/W 0x0000_0000_0000_0000 14.5.5.1/14-63 */ - volatile uint32_t rngdsr; /* 0x3_A010 RNG data size register R/W 0x0000_0000_0000_0000 14.5.5.2/14-64 */ - volatile uint32_t rngrcr; /* 0x3_A018 RNG reset control register R/W 0x0000_0000_0000_0000 14.5.5.3/14-65 */ - volatile uint32_t rngsr; /* 0x3_A028 RNG status register R 0x0000_0000_0000_0000 14.5.5.4/14-65 */ - volatile uint32_t rngisr; /* 0x3_A030 RNG interrupt status register R 0x0000_0000 */ -_0000_0000 -14.5.5.5/14-66 - volatile uint32_t rngicr; /* 0x3_A038 RNG interrupt control register R/W 0x0000_0000 */ -_0000_1000 -14.5.5.6/14-67 - volatile uint32_t rngeug; /* 0x3_A050 RNG EU-Go register W 0x0000_0000 */ -_0000_0000 -14.5.5.7/14-68 -0x3_A800--0x3_AFFF -RNG FIFO R 0x0000_0000 -_0000_0000 -14.5.5.8/14-68 - /* Public Key Execution Unit (PKEU) */ - volatile uint32_t pkeumr; /* 0x3_C000 PKEU mode register R/W 0x0000_0000_0000_0000 14.5.1.1/14-26 */ - volatile uint32_t pkeuksr; /* 0x3_C008 PKEU key size register R/W 0x0000_0000_0000_0000 14.5.1.2/14-28 */ - volatile uint32_t pkeudsr; /* 0x3_C010 PKEU data size register R/W 0x0000_0000_0000_0000 14.5.1.3/14-28 */ - volatile uint32_t pkeurcr; /* 0x3_C018 PKEU reset control register R/W 0x0000_0000_0000_0000 14.5.1.5/14-29 */ - volatile uint32_t pkeusr; /* 0x3_C028 PKEU status register R 0x0000_0000_0000_0000 14.5.1.6/14-30 */ - volatile uint32_t pkeuisr; /* 0x3_C030 PKEU interrupt status register R 0x0000_0000_0000_0000 14.5.1.7/14-31 */ - volatile uint32_t pkeuicr; /* 0x3_C038 PKEU interrupt control register R/W 0x0000_0000_0000_1000 14.5.1.8/14-32 */ - volatile uint32_t pkeuabs; /* 0x3_C040 PKEU AB size register R/W 0x0000_0000_0000_0000 14.5.1.3/14-28 */ - volatile uint32_t pkeueug; /* 0x3_C050 PKEU EU-Go W 0x0000_0000_0000_0000 14.5.1.9/14-33 */ -0x3_C200--0x3_C23F -PKEU parameter memory A0 R/W 0x0000_0000_0000_0000 14.5.1.10/14-34 -0x3_C240--0x3_C27F -PKEU parameter memory A1 R/W 0x0000_0000_0000_0000 -0x3_C280--0x3_C2BF -PKEU parameter memory A2 R/W 0x0000_0000_0000_0000 -0x3_C2C0--0x3_C2FF -PKEU parameter memory A3 R/W 0x0000_0000_0000_0000 -0x3_C300--0x3_C33F -PKEU parameter memory B0 R/W 0x0000_0000_0000_0000 -0x3_C340--0x3_C37F -PKEU parameter memory B1 R/W 0x0000_0000_0000_0000 -0x3_C380--0x3_C3BF -PKEU parameter memory B2 R/W 0x0000_0000_0000_0000 -0x3_C3C0--0x3_C3FF -PKEU parameter memory B3 R/W 0x0000_0000_0000_0000 -0x3_C400--0x3_C4FF -PKEU parameter memory E W 0x0000_0000_0000_0000 -0x3_C800--0x3_C8FF -PKEU parameter memory N R/W 0x0000_0000_0000_0000 -#endif - -typedef struct m83xxRegisters_ { - m83xxSysConRegisters_t syscon; - m83xxWDTRegisters_t wdt; - uint8_t reserved0_0210[0x0300-0x0210]; - m83xxRTCRegisters_t rtc; - uint8_t reserved0_0320[0x0400-0x0320]; - m83xxPITRegisters_t pit; - m83xxGTMRegisters_t gtm[M83xxGTModCnt]; - m83xxIPICRegisters_t ipic; - m83xxARBRegisters_t arb; - m83xxRESRegisters_t res; - m83xxCLKRegisters_t clk; - m83xxPMCRegisters_t pmc; - m83xxGPIORegisters_t gpio[2]; - uint8_t reserved0_0E00[0x1000-0x0E00]; - m83xxDLLRegisters_t dll; - uint8_t reserved0_1200[0x2000-0x1200]; - m83xxDDRRegisters_t ddr; - uint8_t reserved0_2F00[0x3000-0x2F00]; - m83xxI2CRegisters_t i2c[2]; - uint8_t reserved0_3200[0x4000-0x3200]; - uint8_t reserved0_4000[0x4500-0x4000]; - m83xxDUARTRegisters_t duart[2]; - uint8_t reserved0_4700[0x5000-0x4700]; - m83xxLBCRegisters_t lbc; - uint8_t reserved0_5100[0x7000-0x5100]; - m83xxSPIRegisters_t spi; - uint8_t reserved0_7100[0x8000-0x7100]; - m83xxDMARegisters_t dma; - m83xxPCICfgRegisters_t pcicfg[2]; - m83xxPCIIosRegisters_t pciios; - m83xxPCICtrlRegisters_t pcictrl[2]; - uint8_t reserved0_8700[0x22000-0x8700]; - m83xxUSB_MPHRegisters_t usb_mph; - m83xxUSB_DRRegisters_t usb_dr; - volatile tsec_registers tsec[TSEC_COUNT]; -} m83xxRegisters_t; - -extern m83xxRegisters_t mpc83xx; - -static inline void mpc83xx_reset(void) -{ - _ISR_Set_level( 0 ); - - /* Set Reset Protection Register (RPR) to "RSTE" */ - mpc83xx.res.rpr = 0x52535445; - - /* - * Wait for Control Register Enabled in the - * Reset Control Enable Register (RCER). - */ - while (mpc83xx.res.rcer != 0x00000001) { - /* Wait */ - } - - /* Set Software Hard Reset in the Reset Control Register (RCR) */ - mpc83xx.res.rcr = 0x00000002; -} - -#endif /* !defined ASM */ -/* - * some definitions used in assembler startup - */ -/* - * default address of IMMRBAR - */ -#define IMMRBAR_DEFAULT 0xFF400000 -/* - * offsets of some registers - */ -#define LBLAWBAR0_OFF 0x00020 -#define LBLAWAR0_OFF 0x00024 -#define LBLAWBAR1_OFF 0x00028 -#define LBLAWAR1_OFF 0x0002C -#define LBLAWBAR2_OFF 0x00030 -#define LBLAWAR2_OFF 0x00034 -#define LBLAWBAR3_OFF 0x00038 -#define LBLAWAR3_OFF 0x0003C -#define PCILAWBAR0_OFF 0x00060 -#define PCILAWAR0_OFF 0x00064 -#define PCILAWBAR1_OFF 0x00068 -#define PCILAWAR1_OFF 0x0006C -#define DDRLAWBAR0_OFF 0x000A0 -#define DDRLAWAR0_OFF 0x000A4 -#define DDRLAWBAR1_OFF 0x000A8 -#define DDRLAWAR1_OFF 0x000AC - -#define BR0_OFF 0x05000 -#define OR0_OFF 0x05004 -#define BR1_OFF 0x05008 -#define OR1_OFF 0x0500C -#define BR2_OFF 0x05010 -#define OR2_OFF 0x05014 -#define BR3_OFF 0x05018 -#define OR3_OFF 0x0501C -#define BR4_OFF 0x05020 -#define OR4_OFF 0x05024 -#define BR5_OFF 0x05028 -#define OR5_OFF 0x0502C -#define BR6_OFF 0x05030 -#define OR6_OFF 0x05034 -#define BR7_OFF 0x05038 -#define OR7_OFF 0x0503C - -#define MRPTR_OFF 0x05084 -#define LSDMR_OFF 0x05094 -#define LSRT_OFF 0x050A4 -#define LCRR_OFF 0x050d4 - - -#define CS0_BNDS_OFF 0x02000 -#define CS1_BNDS_OFF 0x02008 -#define CS2_BNDS_OFF 0x02010 -#define CS3_BNDS_OFF 0x02018 -#define CS0_CONFIG_OFF 0x02080 -#define CS1_CONFIG_OFF 0x02084 -#define CS2_CONFIG_OFF 0x02088 -#define CS3_CONFIG_OFF 0x0208C -#define TIMING_CFG_3_OFF 0x02100 -#define TIMING_CFG_0_OFF 0x02104 -#define TIMING_CFG_1_OFF 0x02108 -#define TIMING_CFG_2_OFF 0x0210C -#define DDR_SDRAM_CFG_OFF 0x02110 -#define DDR_SDRAM_CFG_2_OFF 0x02114 -#define DDR_SDRAM_MODE_OFF 0x02118 -#define DDR_SDRAM_MODE_2_OFF 0x0211C -#define DDR_SDRAM_MD_CNTL_OFF 0x02120 -#define DDR_SDRAM_INTERVAL_OFF 0x02124 -#define DDR_SDRAM_DATA_INIT_OFF 0x02128 -#define DDRCDR_OFF 0x0012C -#define DDR_SDRAM_CLK_CNTL_OFF 0x02130 -#define DDR_SDRAM_INIT_ADDR_OFF 0x02148 -#define DDR_ERR_DISABLE_OFF 0x02E44 - -/* - * some bits in DDR_SDRAM_CFG register - */ -#define DDR_SDRAM_CFG_MEM_EN (1 << (31- 0)) /* enable memory */ -/* - * bits in DDR_SDRAM_CFG_2 register - */ -#define DDR_SDRAM_CFG_2_D_FRC_SR (1 << (31- 0)) /* force self refresh */ -#define DDR_SDRAM_CFG_2_D_SR_IE (1 << (31- 1)) /* self refresh interrupt en */ -#define DDR_SDRAM_CFG_2_D_DLL_RST_DIS (1 << (31- 2)) /* DLL reset disable */ -#define DDR_SDRAM_CFG_2_D_DQS_CFG_DIF (1 << (31- 5)) /* use diff. DQS */ -#define DDR_SDRAM_CFG_2_D_INIT (1 << (31-27)) /* Init DRAM with pattern */ - -/* - * bits in reset configuration words/registers - */ - /* Local bus clocking mode */ -#define RCWLR_LBIUCM_1_1 (0 << (31- 0)) /* 1:1 */ -#define RCWLR_LBIUCM_2_1 (1 << (31- 0)) /* 2:1 */ - /* DDR clocking mode */ -#define RCWLR_DDRCM_1_1 (0 << (31- 1)) /* 1:1 */ -#define RCWLR_DDRCM_2_1 (1 << (31- 1)) /* 2:1 */ - /* System PLL mult. factor */ -#define RCWLR_SPMF(n) (((n)&0xf)<<(31- 7)) - /* Core PLL mult. factor */ -#define RCWLR_COREPLL(n) (((n)&0xff)<<(31-15)) - -/* for MPC8309: */ -#define RCWLR_CEVCOD_1_8 (2<<(31-25)) /* QUICC internal PLL divider 1:8 */ -#define RCWLR_CEVCOD_1_4 (1<<(31-25)) /* QUICC internal PLL divider 1:4 */ -#define RCWLR_CEVCOD_1_2 (0<<(31-25)) /* QUICC internal PLL divider 1:2 */ - /* QUICC Engine PLL mult. factor */ -#define RCWLR_CEPDF_2 (1<<(31-26)) /* QUICC Engine divide PLL out by 2*/ - /* QUICC Engine PLL mult. factor */ -#define RCWLR_CEPMF(n) (((n)&0x1f)<<(31-31)) - - /* PCI host mode */ -#define RCWHR_PCI_AGENT (0 << (31- 0)) /* agent mode */ -#define RCWHR_PCI_HOST (1 << (31- 0)) /* host mode */ - -#define RCWHR_PCI_32 (0 << (31- 1)) /* PCI bus width 32 bit */ -#define RCWHR_PCI_64 (1 << (31- 1)) /* PCI bus width 64 bit */ - -#define RCWHR_PCI1ARB_DIS (0 << (31- 2)) /* PCI1 arbiter disabled */ -#define RCWHR_PCI1ARB_EN (1 << (31- 2)) /* PCI1 arbiter enabled */ -#define RCWHR_PCI2ARB_DIS (0 << (31- 3)) /* PCI2 arbiter disabled */ -#define RCWHR_PCI2ARB_EN (1 << (31- 3)) /* PCI2 arbiter enabled */ - -#define RCWHR_CORE_DIS (1 << (31- 4)) /* CPU core disabled */ -#define RCWHR_CORE_EN (0 << (31- 4)) /* CPU core enabled */ - -#define RCWHR_BMS_LOW (0 << (31- 5)) /* Boot from low addr 0x00000100 */ -#define RCWHR_BMS_HIGH (1 << (31- 5)) /* Boot from high addr 0xFFF00100 */ - -#define RCWHR_BOOTSEQ_NONE (0 <<(31- 7)) /* Bootsequencer off */ -#define RCWHR_BOOTSEQ_NORM (1 <<(31- 7)) /* Bootsequencer normal I2C */ -#define RCWHR_BOOTSEQ_EXTD (2 <<(31- 7)) /* Bootsequencer extended I2C */ -#define RCWHR_BOOTSEQ_RSRV (3 <<(31- 7)) /* Bootsequencer reserved */ - -#define RCWHR_SW_DIS (0 << (31- 8)) /* Watchdog disabled */ -#define RCWHR_SW_EN (1 << (31- 8)) /* Watchdog enabled */ - -#define RCWHR_ROMLOC_DDR (0 << (31-11)) /* Initial ROM location:DDR Ram */ -#define RCWHR_ROMLOC_PCI1 (1 << (31-11)) /* Initial ROM location:PCI 1 */ -#define RCWHR_ROMLOC_PCI2 (2 << (31-11)) /* Initial ROM location:PCI 2 */ -#define RCWHR_ROMLOC_RSV1 (3 << (31-11)) /* Initial ROM location:Reserved */ -#define RCWHR_ROMLOC_RSV2 (4 << (31-11)) /* Initial ROM location:Reserved */ -#define RCWHR_ROMLOC_LB08 (5 << (31-11)) /* Initial ROM location:LBus 8bit*/ -#define RCWHR_ROMLOC_LB16 (6 << (31-11)) /* Initial ROM location:LBus 16bit*/ -#define RCWHR_ROMLOC_LB32 (7 << (31-11)) /* Initial ROM location:LBus 32bit*/ - -#define RCWHR_TSEC1M_RGMII (0 << (31-17)) /* TSEC1 Mode: RGMII */ -#define RCWHR_TSEC1M_RTBI (1 << (31-17)) /* TSEC1 Mode: RTBI */ -#define RCWHR_TSEC1M_GMII (2 << (31-17)) /* TSEC1 Mode: GMII */ -#define RCWHR_TSEC1M_TBI (3 << (31-17)) /* TSEC1 Mode: TBI */ - -#define RCWHR_TSEC2M_RGMII (0 << (31-19)) /* TSEC2 Mode: RGMII */ -#define RCWHR_TSEC2M_RTBI (1 << (31-19)) /* TSEC2 Mode: RTBI */ -#define RCWHR_TSEC2M_GMII (2 << (31-19)) /* TSEC2 Mode: GMII */ -#define RCWHR_TSEC2M_TBI (3 << (31-19)) /* TSEC2 Mode: TBI */ - -#define RCWHR_ENDIAN_BIG (0 << (31-28)) /* Big Endian Mode */ -#define RCWHR_ENDIAN_LIT (1 << (31-28)) /* True Little Endian Mode */ - -#define RCWHR_LALE_NORM (0 << (31-29)) /* normal LALE timing */ -#define RCWHR_LALE_EARLY (1 << (31-29)) /* early LALE negation */ - -#define RCWHR_LDP_PAR (0 << (31-30)) /* LDP0-3 are parity pins */ -#define RCWHR_LDP_SPC (1 << (31-30)) /* LDP0-3 are special pins */ - -/* - * For MPC8309: - */ -#define RCWHR_RLEXT_LGCY (0 << (31-13)) /* Boot ROM loc. extension: Legacy */ -#define RCWHR_RLEXT_NAND (1 << (31-13)) /* Boot ROM loc. extension: NAND Fl.*/ -#define RCWHR_RLEXT_RSV2 (2 << (31-13)) /* Boot ROM loc. extension: resrvd */ -#define RCWHR_RLEXT_RSV3 (3 << (31-13)) /* Boot ROM loc. extension: resrvd */ -#endif /* _MPC83XX_MPC83XX_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.h b/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.h deleted file mode 100644 index 4efbfa2ab0..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.h +++ /dev/null @@ -1,380 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS support for MPC83xx | -+-----------------------------------------------------------------+ -| Copyright (c) 2007 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file declares the MPC83xx TSEC networking driver | -\*===============================================================*/ - -#ifndef LIBCPU_POWERPC_TSEC_H -#define LIBCPU_POWERPC_TSEC_H - -#include <stdint.h> - -#include <bsp/irq.h> -#include <bsp/tsec-config.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - - /* - * this enumeration defines the index - * of a given rmon mib counter - * in the tsec_rmon_mib array - */ -typedef enum { - /* TSEC1 Transmit and Receive Counters */ - TSEC_RMON_TR64, /* 0x2_4680 Transmit and receive 64-byte frame counter register R/W 0x0000_0000 15.5.3.7.1/15-60 */ - TSEC_RMON_TR127, /* 0x2_4684 Transmit and receive 65- to 127-byte frame counter register R/W 0x0000_0000 15.5.3.7.2/15-61 */ - TSEC_RMON_TR255, /* 0x2_4688 Transmit and receive 128- to 255-byte frame counter register R/W 0x0000_0000 15.5.3.7.3/15-61 */ - TSEC_RMON_TR511, /* 0x2_468C Transmit and receive 256- to 511-byte frame counter register R/W 0x0000_0000 15.5.3.7.4/15-62 */ - TSEC_RMON_TR1K, /* 0x2_4690 Transmit and receive 512- to 1023-byte frame counter register R/W 0x0000_0000 15.5.3.7.5/15-62 */ - TSEC_RMON_TRMAX, /* 0x2_4694 Transmit and receive 1024- to 1518-byte frame counter register R/W 0x0000_0000 15.5.3.7.6/15-63 */ - TSEC_RMON_TRMGV, /* 0x2_4698 Transmit and receive 1519- to 1522-byte good VLAN frame count register R/W 0x0000_0000 15.5.3.7.7/15-63 */ - /* TSEC1 Receive Counters */ - TSEC_RMON_RBYT, /* 0x2_469C Receive byte counter register R/W 0x0000_0000 15.5.3.7.8/15-64 */ - TSEC_RMON_RPKT, /* 0x2_46A0 Receive packet counter register R/W 0x0000_0000 15.5.3.7.9/15-64 */ - TSEC_RMON_RFCS, /* 0x2_46A4 Receive FCS error counter register R/W 0x0000_0000 15.5.3.7.10/15-65 */ - TSEC_RMON_RMCA, /* 0x2_46A8 Receive multicast packet counter register R/W 0x0000_0000 15.5.3.7.11/15-65 */ - TSEC_RMON_RBCA, /* 0x2_46AC Receive broadcast packet counter register R/W 0x0000_0000 15.5.3.7.12/15-66 */ - TSEC_RMON_RXCF, /* 0x2_46B0 Receive control frame packet counter register R/W 0x0000_0000 15.5.3.7.13/15-66 */ - TSEC_RMON_RXPF, /* 0x2_46B4 Receive PAUSE frame packet counter register R/W 0x0000_0000 15.5.3.7.14/15-67 */ - TSEC_RMON_RXUO, /* 0x2_46B8 Receive unknown OP code counter register R/W 0x0000_0000 15.5.3.7.15/15-67 */ - TSEC_RMON_RALN, /* 0x2_46BC Receive alignment error counter register R/W 0x0000_0000 15.5.3.7.16/15-68 */ - TSEC_RMON_RFLR, /* 0x2_46C0 Receive frame length error counter register R/W 0x0000_0000 15.5.3.7.17/15-68 */ - TSEC_RMON_RCDE, /* 0x2_46C4 Receive code error counter register R/W 0x0000_0000 15.5.3.7.18/15-69 */ - TSEC_RMON_RCSE, /* 0x2_46C8 Receive carrier sense error counter register R/W 0x0000_0000 15.5.3.7.19/15-69 */ - TSEC_RMON_RUND, /* 0x2_46CC Receive undersize packet counter register R/W 0x0000_0000 15.5.3.7.20/15-70 */ - TSEC_RMON_ROVR, /* 0x2_46D0 Receive oversize packet counter register R/W 0x0000_0000 15.5.3.7.21/15-70 */ - TSEC_RMON_RFRG, /* 0x2_46D4 Receive fragments counter register R/W 0x0000_0000 15.5.3.7.22/15-71 */ - TSEC_RMON_RJBR, /* 0x2_46D8 Receive jabber counter register R/W 0x0000_0000 15.5.3.7.23/15-71 */ - TSEC_RMON_RDRP, /* 0x2_46DC Receive drop register R/W 0x0000_0000 15.5.3.7.24/15-72 */ - /* TSEC1 Transmit Counters */ - TSEC_RMON_TBYT, /* 0x2_46E0 Transmit byte counter register R/W 0x0000_0000 15.5.3.7.25/15-72 */ - TSEC_RMON_TPKT, /* 0x2_46E4 Transmit packet counter register R/W 0x0000_0000 15.5.3.7.26/15-73 */ - TSEC_RMON_TMCA, /* 0x2_46E8 Transmit multicast packet counter register R/W 0x0000_0000 15.5.3.7.27/15-73 */ - TSEC_RMON_TBCA, /* 0x2_46EC Transmit broadcast packet counter register R/W 0x0000_0000 15.5.3.7.28/15-74 */ - TSEC_RMON_TXPF, /* 0x2_46F0 Transmit PAUSE control frame counter register R/W 0x0000_0000 15.5.3.7.29/15-74 */ - TSEC_RMON_TDFR, /* 0x2_46F4 Transmit deferral packet counter register R/W 0x0000_0000 15.5.3.7.30/15-75 */ - TSEC_RMON_TEDF, /* 0x2_46F8 Transmit excessive deferral packet counter register R/W 0x0000_0000 15.5.3.7.31/15-75 */ - TSEC_RMON_TSCL, /* 0x2_46FC Transmit single collision packet counter register R/W 0x0000_0000 15.5.3.7.32/15-76 */ - TSEC_RMON_TMCL, /* 0x2_4700 Transmit multiple collision packet counter register R/W 0x0000_0000 15.5.3.7.33/15-76 */ - TSEC_RMON_TLCL, /* 0x2_4704 Transmit late collision packet counter register R/W 0x0000_0000 15.5.3.7.34/15-77 */ - TSEC_RMON_TXCL, /* 0x2_4708 Transmit excessive collision packet counter register R/W 0x0000_0000 15.5.3.7.35/15-77 */ - TSEC_RMON_TNCL, /* 0x2_470C Transmit total collision counter register R/W 0x0000_0000 15.5.3.7.36/15-78 */ - TSEC_RESERVED1, /* 0x2_4710 Reserved, should be cleared R 0x0000_0000 */ - TSEC_RMON_TDRP, /* 0x2_4714 Transmit drop frame counter register R/W 0x0000_0000 15.5.3.7.37/15-78 */ - TSEC_RMON_TJBR, /* 0x2_4718 Transmit jabber frame counter register R/W 0x0000_0000 15.5.3.7.38/15-79 */ - TSEC_RMON_TFCS, /* 0x2_471C Transmit FCS error counter register R/W 0x0000_0000 15.5.3.7.39/15-79 */ - TSEC_RMON_TXCF, /* 0x2_4720 Transmit control frame counter register R/W 0x0000_0000 15.5.3.7.40/15-80 */ - TSEC_RMON_TOVR, /* 0x2_4724 Transmit oversize frame counter register R/W 0x0000_0000 15.5.3.7.41/15-80 */ - TSEC_RMON_TUND, /* 0x2_4728 Transmit undersize frame counter register R/W 0x0000_0000 15.5.3.7.42/15-81 */ - TSEC_RMON_TFRG, /* 0x2_472C Transmit fragments frame counter register R/W 0x0000_0000 15.5.3.7.43/15-81 */ - TSEC_RMON_CNT -} tsec_rmon_idx; - - /* TSEC1/2 General Control and Status Registers */ -typedef struct { - uint8_t reserved0x2_4000[0x24010-0x24000]; /* 0x2_4000--0x2_400F Reserved, should be cleared */ - uint32_t ievent; /* 0x2_4010 Interrupt event register R/W 0x0000_0000 15.5.3.1.1/15-19 */ - uint32_t imask; /* 0x2_4014 Interrupt mask register R/W 0x0000_0000 15.5.3.1.2/15-22 */ - uint32_t edis; /* 0x2_4018 Error disabled register R/W 0x0000_0000 15.5.3.1.3/15-24 */ - uint8_t reserved0x2_401c[0x24020-0x2401c]; /* 0x2_401c--0x2_401f Reserved, should be cleared */ - uint32_t ecntrl; /* 0x2_4020 Ethernet control register R/W 0x0000_0000 15.5.3.1.4/15-25 */ - uint32_t minflr; /* 0x2_4024 Minimum frame length register R/W 0x0000_0040 15.5.3.1.5/15-26 */ - uint32_t ptv; /* 0x2_4028 Pause time value register R/W 0x0000_0000 15.5.3.1.6/15-27 */ - uint32_t dmactrl; /* 0x2_402C DMA control register R/W 0x0000_0000 15.5.3.1.7/15-28 */ - uint32_t tbipa; /* 0x2_4030 TBI PHY address register R/W 0x0000_0000 15.5.3.1.8/15-29 */ - uint8_t reserved0x2_4034[0x2408c-0x24034]; /* 0x2_4034--0x2_408b Reserved, should be cleared */ - /* TSEC1 FIFO Control and Status Registers */ - uint32_t fifo_tx_thr; /* 0x2_408C FIFO transmit threshold register R/W 0x0000_0100 15.5.3.2.1/15-30 */ - uint8_t reserved0x2_4090[0x24094-0x24090]; /* 0x2_4090--0x2_4093 Reserved, should be cleared */ - uint32_t fifo_tx_sp; /* 0x2_4094 FIFO transmit space available register R/W 0x0000_0010 15.5.3.2.2/15-31 */ - uint32_t fifo_tx_starve; /* 0x2_4098 FIFO transmit starve register R/W 0x0000_0080 15.5.3.2.3/15-31 */ - uint32_t fifo_tx_starve_shutoff; /* 0x2_409C FIFO transmit starve shutoff register R/W 0x0000_0100 15.5.3.2.4/15-32 */ - uint8_t reserved0x2_40A0[0x24100-0x240A0]; /* 0x2_40A0--0x2_40ff Reserved, should be cleared */ - /* TSEC1 Transmit Control and Status Registers */ - uint32_t tctrl; /* 0x2_4100 Transmit control register R/W 0x0000_0000 15.5.3.3.1/15-33 */ - uint32_t tstat; /* 0x2_4104 Transmit status register R/W 0x0000_0000 15.5.3.3.2/15-34 */ - uint8_t reserved0x2_4108[0x24110-0x24108]; /* 0x2_4108 Reserved, should be cleared R 0x0000_0000 */ - uint32_t txic; /* 0x2_4110 Transmit interrupt coalescing configuration register R/W 0x0000_0000 */ - uint8_t reserved0x2_4114[0x24124-0x24114]; /* 0x2_4114--0x2_4120 Reserved, should be cleared */ - uint32_t ctbptr; /* 0x2_4124 Current TxBD pointer register R 0x0000_0000 15.5.3.3.5/15-36 */ - uint8_t reserved0x2_4128[0x24184-0x24128]; /* 0x2_4128--0x2_4180 Reserved, should be cleared */ - uint32_t tbptr; /* 0x2_4184 TxBD pointer register R/W 0x0000_0000 15.5.3.3.6/15-36 */ - uint8_t reserved0x2_4188[0x24204-0x24188]; /* 0x2_4188--0x2_4200 Reserved, should be cleared */ - uint32_t tbase; /* 0x2_4204 TxBD base address register R/W 0x0000_0000 15.5.3.3.7/15-37 */ - uint8_t reserved0x2_4208[0x242B0-0x24208]; /* 0x2_4208--0x2_42AC Reserved, should be cleared */ - uint32_t ostbd; /* 0x2_42B0 Out-of-sequence TxBD register R/W 0x0800_0000 15.5.3.3.8/15-37 */ - uint32_t ostbdp; /* 0x2_42B4 Out-of-sequence Tx data buffer pointer register R/W 0x0000_0000 15.5.3.3.9/15-39 */ - uint8_t reserved0x2_42B8[0x24300-0x242B8]; /* 0x2_42B8--0x2_42FC Reserved, should be cleared */ - /* TSEC1 Receive Control and Status Registers */ - uint32_t rctrl; /* 0x2_4300 Receive control register R/W 0x0000_0000 15.5.3.4.1/15-40 */ - uint32_t rstat; /* 0x2_4304 Receive status register R/W 0x0000_0000 15.5.3.4.2/15-41 */ - uint8_t reserved0x2_4308[0x2430C-0x24308]; /* 0x2_4308 Reserved, should be cleared R 0x0000_0000 */ - uint32_t rbdlen; /* 0x2_430C RxBD data length register R 0x0000_0000 15.5.3.4.3/15-41 */ - uint32_t rxic; /* 0x2_4310 Receive interrupt coalescing configuration register R/W 0x0000_0000 15.5.3.4.4/15-42 */ - uint8_t reserved0x2_4314[0x24324-0x24314]; /* 0x2_4314--0x2_4320 Reserved, should be cleared */ - uint32_t crbptr; /* 0x2_4324 Current RxBD pointer register R 0x0000_0000 15.5.3.4.5/15-43 */ - uint8_t reserved0x2_4328[0x24340-0x24328]; /* 0x2_4328--0x2_433C Reserved, should be cleared */ - uint32_t mrblr; /* 0x2_4340 Maximum receive buffer length register R/W 0x0000_0000 15.5.3.4.6/15-43 */ - uint8_t reserved0x2_4344[0x24384-0x24344]; /* 0x2_4344--0x2_4380 Reserved, should be cleared */ - uint32_t rbptr; /* 0x2_4384 RxBD pointer register R/W 0x0000_0000 15.5.3.4.7/15-44 */ - uint8_t reserved0x2_4388[0x24404-0x24388]; /* 0x2_4388--0x2_4400 Reserved, should be cleared */ - uint32_t rbase; /* 0x2_4404 RxBD base address register R/W 0x0000_0000 15.5.3.4.8/15-44 */ - uint8_t reserved0x2_4408[0x24500-0x24408]; /* 0x2_4408--0x2_44FC Reserved, should be cleared */ - /* TSEC1 MAC Registers */ - uint32_t maccfg1; /* 0x2_4500 MAC configuration register 1 R/W, R 0x0000_0000 15.5.3.6.1/15-48 */ - uint32_t maccfg2; /* 0x2_4504 MAC configuration register 2 R/W 0x0000_7000 15.5.3.6.2/15-49 */ - uint32_t ipgifg; /* 0x2_4508 Inter-packet gap/inter-frame gap register R/W 0x4060_5060 15.5.3.6.3/15-51 */ - uint32_t hafdup; /* 0x2_450C Half-duplex register R/W 0x00A1_F037 15.5.3.6.4/15-52 */ - uint32_t maxfrm; /* 0x2_4510 Maximum frame length register R/W 0x0000_0600 15.5.3.6.5/15-53 */ - uint8_t reserved0x2_4514[0x24520-0x24514]; /* 0x2_4514--0x2_451C Reserved, should be cleared */ - uint32_t miimcfg; /* 0x2_4520 MII management configuration register R/W 0x0000_0000 15.5.3.6.6/15-53 */ - uint32_t miimcom; /* 0x2_4524 MII management command register R/W 0x0000_0000 15.5.3.6.7/15-54 */ - uint32_t miimadd; /* 0x2_4528 MII management address register R/W 0x0000_0000 15.5.3.6.8/15-55 */ - uint32_t miimcon; /* 0x2_452C MII management control register W 0x0000_0000 15.5.3.6.9/15-56 */ - uint32_t miimstat; /* 0x2_4530 MII management status register R 0x0000_0000 15.5.3.6.10/15-56 */ - uint32_t miimind; /* 0x2_4534 MII management indicator register R 0x0000_0000 15.5.3.6.11/15-57 */ - uint8_t reserved0x2_4538[0x2453c-0x24538]; /* 0x2_4538 Reserved, should be cleared $ $ */ - uint32_t ifstat; /* 0x2_453C Interface status register Special 0x0000_0001 15.5.3.6.12/15-58 */ - uint32_t macstnaddr[2]; /* 0x2_4540 Station address register, part 1/2 R/W 0x0000_0000 15.5.3.6.13/15-58 */ - uint8_t reserved0x2_4548[0x24680-0x24548]; /* 0x2_4548--0x2_467C Reserved, should be cleared */ - - /* TSEC1 RMON MIB Registers */ - uint32_t rmon_mib[TSEC_RMON_CNT]; - - /* TSEC1 General Registers */ - uint32_t car[2]; /* 0x2_4730 Carry register one/two register R 0x0000_0000 15.5.3.7.44/15-82 */ - uint32_t cam[2]; /* 0x2_4738 Carry register one/two mask register R/W 0xFE01_FFFF 15.5.3.7.46/15-85 */ - uint8_t reserved0x2_4740[0x24800-0x24740]; /* 0x2_4740--0x2_47FC Reserved, should be cleared */ - - /* TSEC1 Hash Function Registers */ - uint32_t iaddr[8]; /* 0x2_4800 Individual address register 0-7 R/W 0x0000_0000 15.5.3.8.1/15-87 */ - uint8_t reserved0x2_4820[0x24880-0x24820]; /* 0x2_4820--0x2_487C Reserved, should be cleared */ - uint32_t gaddr[8]; /* 0x2_4880 Group address register 0-7 R/W 0x0000_0000 15.5.3.8.2/15-88 */ - uint8_t reserved0x2_48A0[0x24B00-0x248A0]; /* 0x2_48A0--0x2_4AFF Reserved, should be cleared */ - - /* TSEC1 Attribute Registers */ - uint8_t reserved0x2_4B00[0x24BF8-0x24B00]; /* 0x2_4B00--0x2_4BF4 Reserved, should be cleared */ - uint32_t attr; /* 0x2_4BF8 Attribute register R 0x0000_0000 */ - uint32_t attreli; /* 0x2_4BFC Attribute extract length and extract index register R/W 0x0000_0000 */ - uint8_t reserved0x2_4C00[0x25000-0x24C00]; /* 0x2_4C00--0x2_4FFF Reserved, should be cleared */ -} tsec_registers; - -/* - * TSEC IEVENT/IMASK bit definitions - */ -#define TSEC_IEVENT_BABR (1<<(31- 0)) -#define TSEC_IEVENT_RXC (1<<(31- 1)) -#define TSEC_IEVENT_BSY (1<<(31- 2)) -#define TSEC_IEVENT_EBERR (1<<(31- 3)) -#define TSEC_IEVENT_MSRO (1<<(31- 5)) -#define TSEC_IEVENT_GTSC (1<<(31- 6)) -#define TSEC_IEVENT_BABT (1<<(31- 7)) -#define TSEC_IEVENT_TXC (1<<(31- 8)) -#define TSEC_IEVENT_TXE (1<<(31- 9)) -#define TSEC_IEVENT_TXB (1<<(31-10)) -#define TSEC_IEVENT_TXF (1<<(31-11)) -#define TSEC_IEVENT_LC (1<<(31-13)) -#define TSEC_IEVENT_CRL_XDA (1<<(31-14)) -#define TSEC_IEVENT_XFUN (1<<(31-15)) -#define TSEC_IEVENT_RXB (1<<(31-16)) -#define TSEC_IEVENT_MMRD (1<<(31-21)) -#define TSEC_IEVENT_MMWR (1<<(31-22)) -#define TSEC_IEVENT_GRSC (1<<(31-23)) -#define TSEC_IEVENT_RXF (1<<(31-24)) - -/* - * TSEC DMACTRL bit definitions - */ -#define TSEC_DMACTL_TDSEN (1<<(31-24)) -#define TSEC_DMACTL_TBDSEN (1<<(31-25)) -#define TSEC_DMACTL_GRS (1<<(31-27)) -#define TSEC_DMACTL_GTS (1<<(31-28)) -#define TSEC_DMACTL_WWR (1<<(31-30)) -#define TSEC_DMACTL_WOP (1<<(31-31)) - -/* - * TSEC TSTAT bit definitions - */ -#define TSEC_TSTAT_THLT (1<<(31-0)) - -/* - * TSEC RSTAT bit definitions - */ -#define TSEC_RSTAT_QHLT (1<<(31-8)) - /* - * TSEC ECNTRL bit positions - */ -#define TSEC_ECNTRL_CLRCNT (1 << (31-17)) /* Clear stat counters */ -#define TSEC_ECNTRL_AUTOZ (1 << (31-18)) /* auto-zero read counters */ -#define TSEC_ECNTRL_STEN (1 << (31-19)) /* enable statistics */ -#define TSEC_ECNTRL_TBIM (1 << (31-26)) /* ten-bit-interface */ -#define TSEC_ECNTRL_RPM (1 << (31-27)) /* reduced signal mode */ -#define TSEC_ECNTRL_R100M (1 << (31-28)) /* RGMII100 mode */ - /* - * TSEC EDIS bit positions - */ -#define TSEC_EDIS_BSYDIS (1 << (31- 2)) /* Busy disable */ -#define TSEC_EDIS_EBERRDIS (1 << (31- 3)) /* bus error disable */ -#define TSEC_EDIS_TXEDIS (1 << (31- 9)) /* Tx error disable */ -#define TSEC_EDIS_LCDIS (1 << (31-13)) /* Late collision disable */ -#define TSEC_EDIS_CRLXDADIS (1 << (31-14)) /* Collision Retry disable */ -#define TSEC_EDIS_FUNDIS (1 << (31-15)) /* Tx FIFO underrun disable*/ - - /* - * TSEC RCTRL bit positions - */ -#define TSEC_RCTRL_BC_REJ (1 << (31-27)) /* Broadcast Reject */ -#define TSEC_RCTRL_PROM (1 << (31-28)) /* Promiscuous */ -#define TSEC_RCTRL_RSF (1 << (31-29)) /* Receive short frames */ - - /* - * TSEC TXIC bit positions - */ -#define TSEC_TXIC_ICEN (1 << (31- 0)) /* Irq coalescing enable */ -#define TSEC_TXIC_ICFCT(n) (((n)&0xff) << (31-10)) /* Frame coal. cnt */ -#define TSEC_TXIC_ICTT(n) (((n)&0xffff) << (31-31)) /* Buf. coal. cnt */ - - /* - * TSEC RXIC bit positions - */ -#define TSEC_RXIC_ICEN (1 << (31- 0)) /* Irq coalescing enable */ -#define TSEC_RXIC_ICFCT(n) (((n)&0xff) << (31-10)) /* Frame coal. cnt */ -#define TSEC_RXIC_ICTT(n) (((n)&0xffff) << (31-31)) /* Buf. coal. cnt */ - - /* - * TSEC MACCFG1 bit positions - */ -#define TSEC_MACCFG1_SOFTRST (1 << (31- 0)) /* Soft Reset */ -#define TSEC_MACCFG1_RES_RXMC (1 << (31-12)) /* Reset Rx MAC block */ -#define TSEC_MACCFG1_RES_TXMC (1 << (31-13)) /* Reset Tx MAC block */ -#define TSEC_MACCFG1_RES_RXFUN (1 << (31-14)) /* Reset Rx function blk*/ -#define TSEC_MACCFG1_RES_TXFUN (1 << (31-15)) /* Reset Tx function blk*/ -#define TSEC_MACCFG1_LOOPBACK (1 << (31-23)) /* Loopback mode */ -#define TSEC_MACCFG1_RX_FLOW (1 << (31-26)) /* Receive Flow Ctrl */ -#define TSEC_MACCFG1_TX_FLOW (1 << (31-27)) /* Transmit Flow Ctrl */ -#define TSEC_MACCFG1_SYNVRXEN (1 << (31-28)) /* Sync Receive Enable */ -#define TSEC_MACCFG1_RXEN (1 << (31-29)) /* Receive Enable */ -#define TSEC_MACCFG1_SYNVTXEN (1 << (31-30)) /* Sync Transmit Enable */ -#define TSEC_MACCFG1_TXEN (1 << (31-31)) /* Transmit Enable */ - - /* - * TSEC MACCFG2 bit positions - */ -#define TSEC_MACCFG2_PRELEN(n) (((n)&0x0f) << (31-19)) /* Preamble len*/ - -#define TSEC_MACCFG2_IFMODE_MSK (3 << (31-23)) /* mode mask */ -#define TSEC_MACCFG2_IFMODE_NIB (1 << (31-23)) /* nibble mode */ -#define TSEC_MACCFG2_IFMODE_BYT (2 << (31-23)) /* byte mode */ - -#define TSEC_MACCFG2_HUGE_FRAME (1 << (31-26)) /* Huge Frame */ -#define TSEC_MACCFG2_LENGTH_CHK (1 << (31-27)) /* Length Check */ -#define TSEC_MACCFG2_PAD_CRC (1 << (31-29)) /* MAC adds PAD/CRC */ -#define TSEC_MACCFG2_CRC_EN (1 << (31-30)) /* CRC enable */ -#define TSEC_MACCFG2_FULLDUPLEX (1 << (31-31)) /* Full Duplex Mode */ - - /* - * TSEC MIIMADD bit positions - */ -#define TSEC_MIIMADD_PHY(n) (((n) & 0x3f)<<(31- 23)) /* PHY addr */ -#define TSEC_MIIMADD_REGADDR(n) (((n) & 0x3f)<<(31- 31)) /* PHY addr */ - - /* - * TSEC MIIMCOM bit positions - */ -#define TSEC_MIIMCOM_SCAN (1 << (31-30)) /* Scan command */ -#define TSEC_MIIMCOM_READ (1 << (31-31)) /* Read command */ - - /* - * TSEC MIIMIND bit positions - */ -#define TSEC_MIIMIND_NVAL (1 << (31-29)) /* not valid */ -#define TSEC_MIIMIND_SCAN (1 << (31-30)) /* Scan in progress */ -#define TSEC_MIIMIND_BUSY (1 << (31-31)) /* Acc. in progress */ - - /* - * TSEC ATTR bit positions - */ -#define TSEC_ATTR_RDSEN (1 << (31-24)) /* read data snoop */ -#define TSEC_ATTR_RBDSEN (1 << (31-25)) /* read BD snoop */ - -typedef struct { - volatile uint16_t status; - volatile uint16_t length; - volatile void *buffer; -} PQBufferDescriptor_t; - -/* - * Bits in receive buffer descriptor status word - */ -#define BD_EMPTY (1<<15) -#define BD_RO1 (1<<14) -#define BD_WRAP (1<<13) -#define BD_INTERRUPT (1<<12) -#define BD_LAST (1<<11) -#define BD_CONTROL_CHAR (1<<11) -#define BD_FIRST_IN_FRAME (1<<10) -#define BD_MISS (1<<8) -#define BD_BROADCAST (1<<7) -#define BD_MULTICAST (1<<6) -#define BD_LONG (1<<5) -#define BD_NONALIGNED (1<<4) -#define BD_SHORT (1<<3) -#define BD_CRC_ERROR (1<<2) -#define BD_OVERRUN (1<<1) -#define BD_COLLISION (1<<0) - -/* - * Bits in transmit buffer descriptor status word - * Many bits have the same meaning as those in receiver buffer descriptors. - */ -#define BD_READY (1<<15) -#define BD_PAD_CRC (1<<14) -/* WRAP/Interrupt as in Rx BDs */ -#define BD_TX_CRC (1<<10) -#define BD_DEFER (1<<9) -#define BD_TO1 (1<<8) -#define BD_HFE_ (1<<7) -#define BD_LATE_COLLISION (1<<7) -#define BD_RETRY_LIMIT (1<<6) -#define BD_RETRY_COUNT(x) (((x)&0x3C)>>2) -#define BD_UNDERRUN (1<<1) -#define BD_TXTRUNC (1<<0) - -struct rtems_bsdnet_ifconfig; - -typedef struct { - int unit_number; - char *unit_name; - volatile tsec_registers *reg_ptr; - volatile tsec_registers *mdio_ptr; - rtems_irq_number irq_num_tx; - rtems_irq_number irq_num_rx; - rtems_irq_number irq_num_err; - int phy_default; -} tsec_config; - -int tsec_driver_attach_detach( - struct rtems_bsdnet_ifconfig *config, - int attaching -); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBCPU_POWERPC_TSEC_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h b/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h deleted file mode 100644 index 92fe66831a..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h +++ /dev/null @@ -1,172 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS support for MPC83xx | -+-----------------------------------------------------------------+ -| Copyright (c) 2007 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file contains the MPC83xx SPI driver declarations | -| NOTE: this driver has the same API as a I2C driver | -\*===============================================================*/ -#ifndef _MPC83XX_SPIDRV_H -#define _MPC83XX_SPIDRV_H - -#include <mpc83xx/mpc83xx.h> -#include <rtems/libi2c.h> -#include <rtems/irq.h> - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct mpc83xx_spi_softc { - m83xxSPIRegisters_t *reg_ptr; - int initialized; - rtems_irq_number irq_number; - uint32_t base_frq; /* input frq for baud rate divider */ - rtems_id irq_sema_id; - uint32_t curr_addr; /* current spi address */ - uint32_t idle_char; - uint8_t bytes_per_char; - uint8_t bit_shift; -} mpc83xx_spi_softc_t ; - -typedef struct { - rtems_libi2c_bus_t bus_desc; - mpc83xx_spi_softc_t softc; -} mpc83xx_spi_desc_t; - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -rtems_status_code mpc83xx_spi_init -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| initialize the driver | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - rtems_libi2c_bus_t *bh /* bus specifier structure */ - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| o = ok or error code | -\*=========================================================================*/ - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -int mpc83xx_spi_read_write_bytes -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| transmit/receive some bytes from SPI device | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - rtems_libi2c_bus_t *bh, /* bus specifier structure */ - unsigned char *rbuf, /* buffer to store bytes */ - const unsigned char *tbuf, /* buffer to send bytes */ - int len /* number of bytes to transceive */ - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| number of bytes received or (negative) error code | -\*=========================================================================*/ - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -int mpc83xx_spi_read_bytes -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| receive some bytes from SPI device | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - rtems_libi2c_bus_t *bh, /* bus specifier structure */ - unsigned char *buf, /* buffer to store bytes */ - int len /* number of bytes to receive */ - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| number of bytes received or (negative) error code | -\*=========================================================================*/ - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -int mpc83xx_spi_write_bytes -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| send some bytes to SPI device | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - rtems_libi2c_bus_t *bh, /* bus specifier structure */ - unsigned char *buf, /* buffer to send */ - int len /* number of bytes to send */ - - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| number of bytes sent or (negative) error code | -\*=========================================================================*/ - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -rtems_status_code mpc83xx_spi_set_tfr_mode -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| set SPI to desired baudrate/clock mode/character mode | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - rtems_libi2c_bus_t *bh, /* bus specifier structure */ - const rtems_libi2c_tfr_mode_t *tfr_mode /* transfer mode info */ - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| rtems_status_code | -\*=========================================================================*/ - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -int mpc83xx_spi_ioctl -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| perform selected ioctl function for SPI | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - rtems_libi2c_bus_t *bh, /* bus specifier structure */ - int cmd, /* ioctl command code */ - void *arg /* additional argument array */ - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| rtems_status_code | -\*=========================================================================*/ - -#ifdef __cplusplus -} -#endif - - -#endif /* _MPC83XX_I2CDRV_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/include/console.h b/c/src/lib/libcpu/powerpc/mpc8xx/include/console.h deleted file mode 100644 index eea561e7eb..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc8xx/include/console.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef _MPC8XX_CONSOLE_H -#define _MPC8XX_CONSOLE_H - -#include <rtems/libio.h> - -void m8xx_uart_initialize(void); -void m8xx_uart_interrupts_initialize(void); -void m8xx_uart_scc_initialize (int minor); -void m8xx_uart_smc_initialize (int minor); - -/* Termios callbacks */ -int m8xx_uart_pollRead(int minor); -ssize_t m8xx_uart_pollWrite(int minor, const char* buf, size_t len); -ssize_t m8xx_uart_write(int minor, const char *buf, size_t len); -int m8xx_uart_setAttributes(int, const struct termios* t); - - -#ifdef mpc860 -#define NUM_PORTS 6 /* number of serial ports for mpc860 */ -#else -#define NUM_PORTS 4 /* number of serial ports for mpc821 */ -#endif - -#define SMC1_MINOR 0 -#define SMC2_MINOR 1 -#define SCC1_MINOR 2 -#define SCC2_MINOR 3 -#define SCC3_MINOR 4 -#define SCC4_MINOR 5 - - -#endif diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h b/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h deleted file mode 100644 index 49889bdc32..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * cpm.h - * - * This include file contains definitions pertaining - * to the Communications Processor Module (CPM) on the MPC8xx. - * - * Copyright (c) 1999, National Research Council of Canada - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _MPC8XX_CPM_H -#define _MPC8XX_CPM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Functions */ - -void m8xx_cp_execute_cmd( uint16_t command ); -void *m8xx_dpram_allocate( unsigned int byte_count ); - -#define m8xx_bd_allocate(count) \ - m8xx_dpram_allocate( (count) * sizeof(m8xxBufferDescriptor_t) ) -#define m8xx_RISC_timer_table_allocate(count) \ - m8xx_dpram_allocate( (count) * 4 ) - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h b/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h deleted file mode 100644 index f818b14be1..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * mmu.h - * - * This include file contains definitions pertaining - * to the MMU on the MPC8xx. - * - * Copyright (c) 1999, National Research Council of Canada - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _MPC8XX_MMU_H -#define _MPC8XX_MMU_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * The MMU_TLB_table is used to statically initialize the Table Lookaside - * Buffers in the MMU of an MPC8xx. - */ -typedef struct { - uint32_t mmu_epn; /* Effective Page Number */ - uint32_t mmu_twc; /* Tablewalk Control Register */ - uint32_t mmu_rpn; /* Real Page Number */ -} MMU_TLB_table_t; - -/* - * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be - * supplied by the BSP. - */ -extern MMU_TLB_table_t MMU_TLB_table[]; /* MMU TLB table supplied by BSP */ -extern int MMU_N_TLB_Table_Entries; /* Number of entries in MMU TLB table */ - -/* Functions */ - -void mmu_init( void ); - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h b/c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h deleted file mode 100644 index 3222e7fd03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h +++ /dev/null @@ -1,1499 +0,0 @@ -/* -************************************************************************** -************************************************************************** -** ** -** MOTOROLA MPC860/MPC821 PORTABLE SYSTEMS MICROPROCESSOR ** -** ** -** HARDWARE DECLARATIONS ** -** ** -** ** -** Submitted By: ** -** ** -** W. Eric Norum ** -** Saskatchewan Accelerator Laboratory ** -** University of Saskatchewan ** -** 107 North Road ** -** Saskatoon, Saskatchewan, CANADA ** -** S7N 5C6 ** -** ** -** eric@skatter.usask.ca ** -** ** -** Modified for use with the MPC860 (original code was for MC68360) ** -** by ** -** Jay Monkman ** -** Frasca International, Inc. ** -** 906 E. Airport Rd. ** -** Urbana, IL, 61801 ** -** ** -** jmonkman@frasca.com ** -** ** -** Modified further for use with the MPC821 by: ** -** Andrew Bray <andy@chaos.org.uk> ** -** ** -** With some corrections/additions by: ** -** Darlene A. Stewart and ** -** Charles-Antoine Gauthier ** -** Institute for Information Technology ** -** National Research Council of Canada ** -** Ottawa, ON K1A 0R6 ** -** ** -** Darlene.Stewart@iit.nrc.ca ** -** charles.gauthier@iit.nrc.ca ** -** ** -** Corrections/additions: ** -** Copyright (c) 1999, National Research Council of Canada ** -************************************************************************** -************************************************************************** -*/ -#ifndef _MPC8XX_H -#define _MPC8XX_H - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Macros for accessing Special Purpose Registers (SPRs) - */ -#define _mtspr(_spr,_reg) __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) ) -#define _mfspr(_reg,_spr) __asm__ volatile ( "mfspr %0, %1\n" : "=r" ((_reg)) : "i" ((_spr)) ) - -#define _isync __asm__ volatile ("isync\n"::) - -/* - * Core Registers (SPRs) - */ -#define M8xx_DEC 22 /* Decrementer Register */ -#define M8xx_DER 149 /* Debug Enable Register */ -#define M8xx_ICTRL 158 /* Instruction Support Control Register */ -#define M8xx_TBL_WR 284 /* Timebase Lower Write Register */ -#define M8xx_TBU_WR 285 /* Timebase Upper Write Register */ -#define M8xx_IMMR 638 /* Internal Memory Map Register */ - -/* - * Cache Control Registers (SPRs) - */ -#define M8xx_IC_CST 560 /* Instruction Cache Control and Status Register */ -#define M8xx_DC_CST 568 /* Data Cache Control and Status Register */ -#define M8xx_IC_ADR 561 /* Instruction Cache Address Register */ -#define M8xx_DC_ADR 569 /* Data Cache Address Register */ -#define M8xx_IC_DAT 562 /* Instruction Cache Data Port Register */ -#define M8xx_DC_DAT 570 /* Data Cache Data Port Register */ - -/* - * MMU Registers (SPRs) - */ -/* Control Registers */ -#define M8xx_MI_CTR 784 /* IMMU Control Register */ -#define M8xx_MD_CTR 792 /* DMMU Control Register */ -/* TLB Source Registers */ -#define M8xx_MI_EPN 787 /* IMMU Effective Page Number Register (EPN) */ -#define M8xx_MD_EPN 795 /* DMMU Effective Page Number Register (EPN) */ -#define M8xx_MI_TWC 789 /* IMMU Tablewalk Control Register (TWC) */ -#define M8xx_MD_TWC 797 /* DMMU Tablewalk Control Register (TWC) */ -#define M8xx_MI_RPN 790 /* IMMU Real (physical) Page Number Register (RPN) */ -#define M8xx_MD_RPN 798 /* DMMU Real (physical) Page Number Register (RPN) */ -/* Tablewalk Assist Registers */ -#define M8xx_M_TWB 796 /* MMU Tablewalk Base Register (TWB) */ -/* Protection Registers */ -#define M8xx_M_CASID 793 /* MMU Current Address Space ID Register */ -#define M8xx_MI_AP 786 /* IMMU Access Protection Register */ -#define M8xx_MD_AP 794 /* DMMU Access Protection Register */ -/* Scratch Register */ -#define M8xx_M_TW 799 /* MMU Tablewalk Special Register */ -/* Debug Registers */ -#define M8xx_MI_CAM 816 /* IMMU CAM Entry Read Register */ -#define M8xx_MI_RAM0 817 /* IMMU RAM Entry Read Register 0 */ -#define M8xx_MI_RAM1 818 /* IMMU RAM Entry Read Register 1 */ -#define M8xx_MD_CAM 824 /* DMMU CAM Entry Read Register */ -#define M8xx_MD_RAM0 825 /* DMMU RAM Entry Read Register 0 */ -#define M8xx_MD_RAM1 826 /* DMMU RAM Entry Read Register 1 */ - -#define M8xx_MI_CTR_GPM (1<<31) -#define M8xx_MI_CTR_PPM (1<<30) -#define M8xx_MI_CTR_CIDEF (1<<29) -#define M8xx_MI_CTR_RSV4I (1<<27) -#define M8xx_MI_CTR_PPCS (1<<25) -#define M8xx_MI_CTR_ITLB_INDX(x) ((x)<<8) /* ITLB index */ - -#define M8xx_MD_CTR_GPM (1<<31) -#define M8xx_MD_CTR_PPM (1<<30) -#define M8xx_MD_CTR_CIDEF (1<<29) -#define M8xx_MD_CTR_WTDEF (1<<28) -#define M8xx_MD_CTR_RSV4D (1<<27) -#define M8xx_MD_CTR_TWAM (1<<26) -#define M8xx_MD_CTR_PPCS (1<<25) -#define M8xx_MD_CTR_DTLB_INDX(x) ((x)<<8) /* DTLB index */ - -#define M8xx_MI_EPN_VALID (1<<9) - -#define M8xx_MD_EPN_VALID (1<<9) - -#define M8xx_MI_TWC_G (1<<4) -#define M8xx_MI_TWC_PSS (0<<2) -#define M8xx_MI_TWC_PS512 (1<<2) -#define M8xx_MI_TWC_PS8 (3<<2) -#define M8xx_MI_TWC_VALID (1) - -#define M8xx_MD_TWC_G (1<<4) -#define M8xx_MD_TWC_PSS (0<<2) -#define M8xx_MD_TWC_PS512 (1<<2) -#define M8xx_MD_TWC_PS8 (3<<2) -#define M8xx_MD_TWC_WT (1<<1) -#define M8xx_MD_TWC_VALID (1) - -#define M8xx_MI_RPN_F (0xf<<4) -#define M8xx_MI_RPN_16K (1<<3) -#define M8xx_MI_RPN_SHARED (1<<2) -#define M8xx_MI_RPN_CI (1<<1) -#define M8xx_MI_RPN_VALID (1) - -#define M8xx_MD_RPN_CHANGE (1<<8) -#define M8xx_MD_RPN_F (0xf<<4) -#define M8xx_MD_RPN_16K (1<<3) -#define M8xx_MD_RPN_SHARED (1<<2) -#define M8xx_MD_RPN_CI (1<<1) -#define M8xx_MD_RPN_VALID (1) - -#define M8xx_MI_AP_Kp (1) - -#define M8xx_MD_AP_Kp (1) - -#define M8xx_CACHE_CMD_SFWT (0x1<<24) -#define M8xx_CACHE_CMD_ENABLE (0x2<<24) -#define M8xx_CACHE_CMD_CFWT (0x3<<24) -#define M8xx_CACHE_CMD_DISABLE (0x4<<24) -#define M8xx_CACHE_CMD_STLES (0x5<<24) -#define M8xx_CACHE_CMD_LLCB (0x6<<24) -#define M8xx_CACHE_CMD_CLES (0x7<<24) -#define M8xx_CACHE_CMD_UNLOCK (0x8<<24) -#define M8xx_CACHE_CMD_UNLOCKALL (0xa<<24) -#define M8xx_CACHE_CMD_INVALIDATE (0xc<<24) -#define M8xx_CACHE_CMD_FLUSH (0xe<<24) - -/* -************************************************************************* -* REGISTER SUBBLOCKS * -************************************************************************* -*/ - -/* - * Memory controller registers - */ -typedef struct m8xxMEMCRegisters_ { - uint32_t _br; - uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */ -} m8xxMEMCRegisters_t; - -/* - * Serial Communications Controller registers - */ -typedef struct m8xxSCCRegisters_ { - uint32_t gsmr_l; - uint32_t gsmr_h; - uint16_t psmr; - uint16_t _pad0; - uint16_t todr; - uint16_t dsr; - uint16_t scce; - uint16_t _pad1; - uint16_t sccm; - uint8_t _pad2; - uint8_t sccs; - uint32_t _pad3[2]; -} m8xxSCCRegisters_t; - -/* - * Serial Management Controller registers - */ -typedef struct m8xxSMCRegisters_ { - uint16_t _pad0; - uint16_t smcmr; - uint16_t _pad1; - uint8_t smce; - uint8_t _pad2; - uint16_t _pad3; - uint8_t smcm; - uint8_t _pad4; - uint32_t _pad5; -} m8xxSMCRegisters_t; - -/* - * Fast Ethernet Controller registers (Only on MPC8xxT) - */ -typedef struct m8xxFECRegisters_ { - uint32_t addr_low; - uint32_t addr_high; - uint32_t hash_table_high; - uint32_t hash_table_low; - uint32_t r_des_start; - uint32_t x_des_start; - uint32_t r_buf_size; - uint32_t _pad0[9]; - uint32_t ecntrl; - uint32_t ievent; - uint32_t imask; - uint32_t ivec; - uint32_t r_des_active; - uint32_t x_des_active; - uint32_t _pad1[10]; - uint32_t mii_data; - uint32_t mii_speed; - uint32_t _pad2[17]; - uint32_t r_bound; - uint32_t r_fstart; - uint32_t _pad3[6]; - uint32_t x_fstart; - uint32_t _pad4[17]; - uint32_t fun_code; - uint32_t _pad5[3]; - uint32_t r_cntrl; - uint32_t r_hash; - uint32_t _pad6[14]; - uint32_t x_cntrl; - uint32_t _pad7[30]; - -} m8xxFECRegisters_t; - -#define M8xx_FEC_IEVENT_HBERR (1 << 31) -#define M8xx_FEC_IEVENT_BABR (1 << 30) -#define M8xx_FEC_IEVENT_BABT (1 << 29) -#define M8xx_FEC_IEVENT_GRA (1 << 28) -#define M8xx_FEC_IEVENT_TFINT (1 << 27) -#define M8xx_FEC_IEVENT_TXB (1 << 26) -#define M8xx_FEC_IEVENT_RFINT (1 << 25) -#define M8xx_FEC_IEVENT_RXB (1 << 24) -#define M8xx_FEC_IEVENT_MII (1 << 23) -#define M8xx_FEC_IEVENT_EBERR (1 << 22) -#define M8xx_FEC_IMASK_HBEEN (1 << 31) -#define M8xx_FEC_IMASK_BREEN (1 << 30) -#define M8xx_FEC_IMASK_BTEN (1 << 29) -#define M8xx_FEC_IMASK_GRAEN (1 << 28) -#define M8xx_FEC_IMASK_TFIEN (1 << 27) -#define M8xx_FEC_IMASK_TBIEN (1 << 26) -#define M8xx_FEC_IMASK_RFIEN (1 << 25) -#define M8xx_FEC_IMASK_RBIEN (1 << 24) -#define M8xx_FEC_IMASK_MIIEN (1 << 23) -#define M8xx_FEC_IMASK_EBERREN (1 << 22) - - /* - * access macros to write to mii_data register - */ -#define M8xx_FEC_MII_DATA_ST ( 1 << (31- 1)) -#define M8xx_FEC_MII_DATA_OP_RD ( 2 << (31- 3)) -#define M8xx_FEC_MII_DATA_OP_WR ( 1 << (31- 3)) -#define M8xx_FEC_MII_DATA_PHYAD(n) (((n) & 0x3f) << (31- 8)) -#define M8xx_FEC_MII_DATA_PHYRA(n) (((n) & 0x3f) << (31-13)) -#define M8xx_FEC_MII_DATA_TA ( 2 << (31-15)) -#define M8xx_FEC_MII_DATA_WDATA(n) ((n) & 0xffff ) -#define M8xx_FEC_MII_DATA_RDATA(reg) ((reg) & 0xffff ) - /* - * bits for FEC X_CNTRL register - */ -#define M8xx_FEC_X_CNTRL_FDEN ( 1 << (31-29)) -#define M8xx_FEC_X_CNTRL_HBC ( 1 << (31-30)) -#define M8xx_FEC_X_CNTRL_GTS ( 1 << (31-31)) -/* -************************************************************************* -* Miscellaneous Parameters * -************************************************************************* -*/ -typedef struct m8xxMiscParms_ { - uint16_t rev_num; - uint16_t _res1; - uint32_t _res2; - uint32_t _res3; -} m8xxMiscParms_t; - -/* -************************************************************************* -* RISC Timers * -************************************************************************* -*/ -typedef struct m8xxTimerParms_ { - uint16_t tm_base; - uint16_t _tm_ptr; - uint16_t _r_tmr; - uint16_t _r_tmv; - uint32_t tm_cmd; - uint32_t tm_cnt; -} m8xxTimerParms_t; - -/* - * RISC Controller Configuration Register (RCCR) - * All other bits in this register are reserved. - */ -#define M8xx_RCCR_TIME (1<<15) /* Enable timer */ -#define M8xx_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ -#define M8xx_RCCR_DR1M (1<<7) /* IDMA Rqst 1 Mode */ -#define M8xx_RCCR_DR0M (1<<6) /* IDMA Rqst 0 Mode */ -#define M8xx_RCCR_DRQP(x) ((x)<<4) /* IDMA Rqst Priority */ -#define M8xx_RCCR_EIE (1<<3) /* External Interrupt Enable */ -#define M8xx_RCCR_SCD (1<<2) /* Scheduler Configuration */ -#define M8xx_RCCR_ERAM(x) (x) /* Enable RAM Microcode */ - -/* - * Command register - * Set up this register before issuing a M8xx_CR_OP_SET_TIMER command. - */ -#define M8xx_TM_CMD_V (1<<31) /* Set to enable timer */ -#define M8xx_TM_CMD_R (1<<30) /* Set for automatic restart */ -#define M8xx_TM_CMD_PWM (1<<29) /* Set for PWM operation */ -#define M8xx_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ -#define M8xx_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ - -/* -************************************************************************* -* DMA Controllers * -************************************************************************* -*/ -typedef struct m8xxIDMAparms_ { - uint16_t ibase; - uint16_t dcmr; - uint32_t _sapr; - uint32_t _dapr; - uint16_t ibptr; - uint16_t _write_sp; - uint32_t _s_byte_c; - uint32_t _d_byte_c; - uint32_t _s_state; - uint32_t _itemp[4]; - uint32_t _sr_mem; - uint16_t _read_sp; - uint16_t _res0; - uint16_t _res1; - uint16_t _res2; - uint32_t _d_state; -} m8xxIDMAparms_t; - - -/* -************************************************************************* -* DSP * -************************************************************************* -*/ -typedef struct m8xxDSPparms_ { - uint32_t fdbase; - uint32_t _fd_ptr; - uint32_t _dstate; - uint32_t _pad0; - uint16_t _dstatus; - uint16_t _i; - uint16_t _tap; - uint16_t _cbase; - uint16_t _pad1; - uint16_t _xptr; - uint16_t _pad2; - uint16_t _yptr; - uint16_t _m; - uint16_t _pad3; - uint16_t _n; - uint16_t _pad4; - uint16_t _k; - uint16_t _pad5; -} m8xxDSPparms_t; - -/* -************************************************************************* -* Serial Communication Controllers * -************************************************************************* -*/ -typedef struct m8xxSCCparms_ { - uint16_t rbase; - uint16_t tbase; - uint8_t rfcr; - uint8_t tfcr; - uint16_t mrblr; - uint32_t _rstate; - uint32_t _pad0; - uint16_t _rbptr; - uint16_t _pad1; - uint32_t _pad2; - uint32_t _tstate; - uint32_t _pad3; - uint16_t _tbptr; - uint16_t _pad4; - uint32_t _pad5; - uint32_t _rcrc; - uint32_t _tcrc; - union { - struct { - uint32_t _res0; - uint32_t _res1; - uint16_t max_idl; - uint16_t _idlc; - uint16_t brkcr; - uint16_t parec; - uint16_t frmec; - uint16_t nosec; - uint16_t brkec; - uint16_t brkln; - uint16_t uaddr[2]; - uint16_t _rtemp; - uint16_t toseq; - uint16_t character[8]; - uint16_t rccm; - uint16_t rccr; - uint16_t rlbc; - } uart; - } un; -} m8xxSCCparms_t; - -typedef struct m8xxSCCENparms_ { - uint16_t rbase; - uint16_t tbase; - uint8_t rfcr; - uint8_t tfcr; - uint16_t mrblr; - uint32_t _rstate; - uint32_t _pad0; - uint16_t _rbptr; - uint16_t _pad1; - uint32_t _pad2; - uint32_t _tstate; - uint32_t _pad3; - uint16_t _tbptr; - uint16_t _pad4; - uint32_t _pad5; - uint32_t _rcrc; - uint32_t _tcrc; - union { - struct { - uint32_t _res0; - uint32_t _res1; - uint16_t max_idl; - uint16_t _idlc; - uint16_t brkcr; - uint16_t parec; - uint16_t frmec; - uint16_t nosec; - uint16_t brkec; - uint16_t brkln; - uint16_t uaddr[2]; - uint16_t _rtemp; - uint16_t toseq; - uint16_t character[8]; - uint16_t rccm; - uint16_t rccr; - uint16_t rlbc; - } uart; - struct { - uint32_t c_pres; - uint32_t c_mask; - uint32_t crcec; - uint32_t alec; - uint32_t disfc; - uint16_t pads; - uint16_t ret_lim; - uint16_t _ret_cnt; - uint16_t mflr; - uint16_t minflr; - uint16_t maxd1; - uint16_t maxd2; - uint16_t _maxd; - uint16_t dma_cnt; - uint16_t _max_b; - uint16_t gaddr1; - uint16_t gaddr2; - uint16_t gaddr3; - uint16_t gaddr4; - uint32_t _tbuf0data0; - uint32_t _tbuf0data1; - uint32_t _tbuf0rba0; - uint32_t _tbuf0crc; - uint16_t _tbuf0bcnt; - uint16_t paddr_h; - uint16_t paddr_m; - uint16_t paddr_l; - uint16_t p_per; - uint16_t _rfbd_ptr; - uint16_t _tfbd_ptr; - uint16_t _tlbd_ptr; - uint32_t _tbuf1data0; - uint32_t _tbuf1data1; - uint32_t _tbuf1rba0; - uint32_t _tbuf1crc; - uint16_t _tbuf1bcnt; - uint16_t _tx_len; - uint16_t iaddr1; - uint16_t iaddr2; - uint16_t iaddr3; - uint16_t iaddr4; - uint16_t _boff_cnt; - uint16_t taddr_m; - uint16_t taddr_l; - uint16_t taddr_h; - } ethernet; - } un; -} m8xxSCCENparms_t; - -/* - * Receive and transmit function code register bits - * These apply to the function code registers of all devices, not just SCC. - */ -#define M8xx_RFCR_BO(x) ((x)<<3) -#define M8xx_RFCR_MOT (2<<3) -#define M8xx_RFCR_DMA_SPACE(x) (x) -#define M8xx_TFCR_BO(x) ((x)<<3) -#define M8xx_TFCR_MOT (2<<3) -#define M8xx_TFCR_DMA_SPACE(x) (x) - -/* - * Event and mask registers (SCCE, SCCM) - */ -#define M8xx_SCCE_BRKE (1<<6) -#define M8xx_SCCE_BRK (1<<4) -#define M8xx_SCCE_BSY (1<<2) -#define M8xx_SCCE_TX (1<<1) -#define M8xx_SCCE_RX (1<<0) - -/* -************************************************************************* -* Serial Management Controllers * -************************************************************************* -*/ -typedef struct m8xxSMCparms_ { - uint16_t rbase; - uint16_t tbase; - uint8_t rfcr; - uint8_t tfcr; - uint16_t mrblr; - uint32_t _rstate; - uint32_t _pad0; - uint16_t _rbptr; - uint16_t _pad1; - uint32_t _pad2; - uint32_t _tstate; - uint32_t _pad3; - uint16_t _tbptr; - uint16_t _pad4; - uint32_t _pad5; - union { - struct { - uint16_t max_idl; - uint16_t _idlc; - uint16_t brkln; - uint16_t brkec; - uint16_t brkcr; - uint16_t _r_mask; - } uart; - struct { - uint16_t _pad0[5]; - } transparent; - } un; -} m8xxSMCparms_t; - -/* - * Mode register - */ -#define M8xx_SMCMR_CLEN(x) ((x)<<11) /* Character length */ -#define M8xx_SMCMR_2STOP (1<<10) /* 2 stop bits */ -#define M8xx_SMCMR_PARITY (1<<9) /* Enable parity */ -#define M8xx_SMCMR_EVEN (1<<8) /* Even parity */ -#define M8xx_SMCMR_SM_GCI (0<<4) /* GCI Mode */ -#define M8xx_SMCMR_SM_UART (2<<4) /* UART Mode */ -#define M8xx_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ -#define M8xx_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ -#define M8xx_SMCMR_DM_ECHO (2<<2) /* Echo mode */ -#define M8xx_SMCMR_TEN (1<<1) /* Enable transmitter */ -#define M8xx_SMCMR_REN (1<<0) /* Enable receiver */ - -/* - * Event and mask registers (SMCE, SMCM) - */ -#define M8xx_SMCE_BRKE (1<<6) -#define M8xx_SMCE_BRK (1<<4) -#define M8xx_SMCE_BSY (1<<2) -#define M8xx_SMCE_TX (1<<1) -#define M8xx_SMCE_RX (1<<0) - -/* -************************************************************************* -* Serial Peripheral Interface * -************************************************************************* -*/ -typedef struct m8xxSPIparms_ { - uint16_t rbase; - uint16_t tbase; - uint8_t rfcr; - uint8_t tfcr; - uint16_t mrblr; - uint32_t _rstate; - uint32_t _pad0; - uint16_t _rbptr; - uint16_t _pad1; - uint32_t _pad2; - uint32_t _tstate; - uint32_t _pad3; - uint16_t _tbptr; - uint16_t _pad4; - uint32_t _pad5; -} m8xxSPIparms_t; - -/* - * Mode register (SPMODE) - */ -#define M8xx_SPMODE_LOOP (1<<14) /* Local loopback mode */ -#define M8xx_SPMODE_CI (1<<13) /* Clock invert */ -#define M8xx_SPMODE_CP (1<<12) /* Clock phase */ -#define M8xx_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ -#define M8xx_SPMODE_REV (1<<10) /* Reverse data */ -#define M8xx_SPMODE_MASTER (1<<9) /* SPI is master */ -#define M8xx_SPMODE_EN (1<<8) /* Enable SPI */ -#define M8xx_SPMODE_CLEN(x) ((x)<<4) /* Character length */ -#define M8xx_SPMODE_PM(x) (x) /* Prescaler modulus */ - -/* - * Mode register (SPCOM) - */ -#define M8xx_SPCOM_STR (1<<7) /* Start transmit */ - -/* - * Event and mask registers (SPIE, SPIM) - */ -#define M8xx_SPIE_MME (1<<5) /* Multi-master error */ -#define M8xx_SPIE_TXE (1<<4) /* Tx error */ -#define M8xx_SPIE_BSY (1<<2) /* Busy condition*/ -#define M8xx_SPIE_TXB (1<<1) /* Tx buffer */ -#define M8xx_SPIE_RXB (1<<0) /* Rx buffer */ - -/* -************************************************************************* -* SDMA (SCC, SMC, SPI) Buffer Descriptors * -************************************************************************* -*/ -typedef struct m8xxBufferDescriptor_ { - volatile uint16_t status; - uint16_t length; - volatile void *buffer; -} m8xxBufferDescriptor_t; - -/* - * Bits in receive buffer descriptor status word - */ -#define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */ -#define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */ -#define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ -#define M8xx_BD_ADDRESS (1<<10) /* SCC UART */ -#define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ -#define M8xx_BD_MISS (1<<8) /* Ethernet */ -#define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */ -#define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ -#define M8xx_BD_LONG (1<<5) /* Ethernet */ -#define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */ -#define M8xx_BD_NONALIGNED (1<<4) /* Ethernet */ -#define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ -#define M8xx_BD_SHORT (1<<3) /* Ethernet */ -#define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ -#define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet */ -#define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8xx_BD_COLLISION (1<<0) /* Ethernet */ -#define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ -#define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */ - -/* - * Bits in transmit buffer descriptor status word - * Many bits have the same meaning as those in receiver buffer descriptors. - */ -#define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M8xx_BD_PAD (1<<14) /* Ethernet */ -#define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */ -#define M8xx_BD_TX_CRC (1<<10) /* Ethernet */ -#define M8xx_BD_DEFER (1<<9) /* Ethernet */ -#define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */ -#define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ -#define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */ -#define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */ -#define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */ -#define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ -#define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ -#define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */ -#define M8xx_BD_CTS_LOST (1<<0) /* SCC UART */ - -/* -************************************************************************* -* IDMA Buffer Descriptors * -************************************************************************* -*/ -typedef struct m8xxIDMABufferDescriptor_ { - uint16_t status; - uint8_t dfcr; - uint8_t sfcr; - uint32_t length; - void *source; - void *destination; -} m8xxIDMABufferDescriptor_t; - -/* -************************************************************************* -* RISC Communication Processor Module Command Register (CR) * -************************************************************************* -*/ -#define M8xx_CR_RST (1<<15) /* Reset communication processor */ -#define M8xx_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ -#define M8xx_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ -#define M8xx_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ -#define M8xx_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ -#define M8xx_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ -#define M8xx_CR_OP_GR_STOP_TX (5<<8) /* SCC */ -#define M8xx_CR_OP_INIT_IDMA (5<<8) /* IDMA */ -#define M8xx_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ -#define M8xx_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ -#define M8xx_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ -#define M8xx_CR_OP_SET_TIMER (8<<8) /* Timer */ -#define M8xx_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ -#define M8xx_CR_OP_RESERT_BCS (10<<8) /* SCC */ -#define M8xx_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ -#define M8xx_CR_OP_STOP_IDMA (11<<8) /* IDMA */ -#define M8xx_CR_OP_START_DSP (12<<8) /* DSP */ -#define M8xx_CR_OP_INIT_DSP (13<<8) /* DSP */ - -#define M8xx_CR_CHAN_SCC1 (0<<4) /* Channel selection */ -#define M8xx_CR_CHAN_I2C (1<<4) -#define M8xx_CR_CHAN_IDMA1 (1<<4) -#define M8xx_CR_CHAN_SCC2 (4<<4) -#define M8xx_CR_CHAN_SPI (5<<4) -#define M8xx_CR_CHAN_IDMA2 (5<<4) -#define M8xx_CR_CHAN_TIMER (5<<4) -#define M8xx_CR_CHAN_SCC3 (8<<4) -#define M8xx_CR_CHAN_SMC1 (9<<4) -#define M8xx_CR_CHAN_DSP1 (9<<4) -#define M8xx_CR_CHAN_SCC4 (12<<4) -#define M8xx_CR_CHAN_SMC2 (13<<4) -#define M8xx_CR_CHAN_DSP2 (13<<4) -#define M8xx_CR_FLG (1<<0) /* Command flag */ - -/* -************************************************************************* -* System Protection Control Register (SYPCR) * -************************************************************************* -*/ -#define M8xx_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ -#define M8xx_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ -#define M8xx_SYPCR_BME (1<<7) /* Bus monitor enable */ -#define M8xx_SYPCR_SWF (1<<3) /* Software watchdog freeze */ -#define M8xx_SYPCR_SWE (1<<2) /* Software watchdog enable */ -#define M8xx_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ -#define M8xx_SYPCR_SWP (1<<0) /* Software watchdog prescale */ - -/* -************************************************************************* -* PCMCIA Control Registers -************************************************************************* -*/ -#define M8xx_PCMCIA_POR_BSIZE_1B (0x00 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_2B (0x01 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_4B (0x03 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_8B (0x02 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_16B (0x06 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_32B (0x07 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_64B (0x05 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_128B (0x04 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_256B (0x0C << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_512B (0x0D << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_1KB (0x0F << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_2KB (0x0E << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_4KB (0x0A << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_8KB (0x0B << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_16KB (0x09 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_32KB (0x08 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_64KB (0x18 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_128KB (0x19 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_256KB (0x1B << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_512KB (0x1A << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_1MB (0x1E << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_2MB (0x1F << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_4MB (0x1D << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_8MB (0x1C << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_16MB (0x14 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_32MB (0x15 << (31-4)) -#define M8xx_PCMCIA_POR_BSIZE_64MB (0x17 << (31-4)) - -#define M8xx_PCMCIA_POR_PSHT(x) (((x) & 0x0f) << (31-15)) -#define M8xx_PCMCIA_POR_PSST(x) (((x) & 0x0f) << (31-19)) -#define M8xx_PCMCIA_POR_PSL(x) (((x) & 0x1f) << (31-24)) -#define M8xx_PCMCIA_POR_PPS_8 ((0) << (31-19)) -#define M8xx_PCMCIA_POR_PPS_16 ((1) << (31-19)) - -#define M8xx_PCMCIA_POR_PRS_MEM ((0) << (31-28)) -#define M8xx_PCMCIA_POR_PRS_ATT ((2) << (31-28)) -#define M8xx_PCMCIA_POR_PRS_IO ((3) << (31-28)) -#define M8xx_PCMCIA_POR_PRS_DMA ((4) << (31-28)) -#define M8xx_PCMCIA_POR_PRS_DML ((5) << (31-28)) - -#define M8xx_PCMCIA_POR_PSLOT_A ((0) << (31-29)) -#define M8xx_PCMCIA_POR_PSLOT_B ((1) << (31-29)) - -#define M8xx_PCMCIA_POR_WP ((1) << (31-30)) -#define M8xx_PCMCIA_POR_VALID ((1) << (31-31)) - -#define M8xx_PCMCIA_PGCR_CIRQLVL(x) (((x) & 0xff) << (31- 7)) -#define M8xx_PCMCIA_PGCR_CSCHLVL(x) (((x) & 0xff) << (31-15)) -#define M8xx_PCMCIA_PGCR_CDRQ_OFF ((0) << (31-17)) -#define M8xx_PCMCIA_PGCR_CDRQ_IOIS16 ((2) << (31-17)) -#define M8xx_PCMCIA_PGCR_CDRQ_SPKR ((3) << (31-17)) -#define M8xx_PCMCIA_PGCR_COE ((1) << (31-24)) -#define M8xx_PCMCIA_PGCR_CRESET ((1) << (31-25)) - -#define M8xx_PCMCIA_PIPR_CAVS1 ((1) << (31- 0)) -#define M8xx_PCMCIA_PIPR_CAVS2 ((1) << (31- 1)) -#define M8xx_PCMCIA_PIPR_CAWP ((1) << (31- 2)) -#define M8xx_PCMCIA_PIPR_CACD2 ((1) << (31- 3)) -#define M8xx_PCMCIA_PIPR_CACD1 ((1) << (31- 4)) -#define M8xx_PCMCIA_PIPR_CABVD2 ((1) << (31- 5)) -#define M8xx_PCMCIA_PIPR_CABVD1 ((1) << (31- 6)) -#define M8xx_PCMCIA_PIPR_CARDY ((1) << (31- 7)) -#define M8xx_PCMCIA_PIPR_CBVS1 ((1) << (31-16)) -#define M8xx_PCMCIA_PIPR_CBVS2 ((1) << (31-17)) -#define M8xx_PCMCIA_PIPR_CBWP ((1) << (31-18)) -#define M8xx_PCMCIA_PIPR_CBCD2 ((1) << (31-19)) -#define M8xx_PCMCIA_PIPR_CBCD1 ((1) << (31-20)) -#define M8xx_PCMCIA_PIPR_CBBVD2 ((1) << (31-21)) -#define M8xx_PCMCIA_PIPR_CBBVD1 ((1) << (31-22)) -#define M8xx_PCMCIA_PIPR_CBRDY ((1) << (31-23)) - - -#define M8xx_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ -#define M8xx_SYPCR_BME (1<<7) /* Bus monitor enable */ -#define M8xx_SYPCR_SWF (1<<3) /* Software watchdog freeze */ -#define M8xx_SYPCR_SWE (1<<2) /* Software watchdog enable */ -#define M8xx_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ -#define M8xx_SYPCR_SWP (1<<0) /* Software watchdog prescale */ - -/* -************************************************************************* -* Memory Control Registers * -************************************************************************* -*/ -#define M8xx_UPM_AMX_8col (0<<20) /* 8 column DRAM */ -#define M8xx_UPM_AMX_9col (1<<20) /* 9 column DRAM */ -#define M8xx_UPM_AMX_10col (2<<20) /* 10 column DRAM */ -#define M8xx_UPM_AMX_11col (3<<20) /* 11 column DRAM */ -#define M8xx_UPM_AMX_12col (4<<20) /* 12 column DRAM */ -#define M8xx_UPM_AMX_13col (5<<20) /* 13 column DRAM */ -#define M8xx_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */ -#define M8xx_MSR_WPER (1<<7) /* Write protection error */ -#define M8xx_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */ -#define M8xx_BR_BA(x) ((x)&0xffff8000) /* Base address */ -#define M8xx_BR_AT(x) ((x)<<12) /* Address type */ -#define M8xx_BR_PS8 (1<<10) /* 8 bit port */ -#define M8xx_BR_PS16 (2<<10) /* 16 bit port */ -#define M8xx_BR_PS32 (0<<10) /* 32 bit port */ -#define M8xx_BR_PARE (1<<9) /* Parity checking enable */ -#define M8xx_BR_WP (1<<8) /* Write protect */ -#define M8xx_BR_MS_GPCM (0<<6) /* GPCM */ -#define M8xx_BR_MS_UPMA (2<<6) /* UPM A */ -#define M8xx_BR_MS_UPMB (3<<6) /* UPM B */ -#define M8xx_MEMC_BR_V (1<<0) /* Base/Option register are valid */ - -#define M8xx_MEMC_OR_32K 0xffff8000 /* Address range */ -#define M8xx_MEMC_OR_64K 0xffff0000 -#define M8xx_MEMC_OR_128K 0xfffe0000 -#define M8xx_MEMC_OR_256K 0xfffc0000 -#define M8xx_MEMC_OR_512K 0xfff80000 -#define M8xx_MEMC_OR_1M 0xfff00000 -#define M8xx_MEMC_OR_2M 0xffe00000 -#define M8xx_MEMC_OR_4M 0xffc00000 -#define M8xx_MEMC_OR_8M 0xff800000 -#define M8xx_MEMC_OR_16M 0xff000000 -#define M8xx_MEMC_OR_32M 0xfe000000 -#define M8xx_MEMC_OR_64M 0xfc000000 -#define M8xx_MEMC_OR_128 0xf8000000 -#define M8xx_MEMC_OR_256M 0xf0000000 -#define M8xx_MEMC_OR_512M 0xe0000000 -#define M8xx_MEMC_OR_1G 0xc0000000 -#define M8xx_MEMC_OR_2G 0x80000000 -#define M8xx_MEMC_OR_4G 0x00000000 -#define M8xx_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ -#define M8xx_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ -#define M8xx_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */ -#define M8xx_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ -#define M8xx_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ -#define M8xx_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ -#define M8xx_MEMC_OR_BI (1<<8) /* Burst inhibit */ -#define M8xx_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ -#define M8xx_MEMC_OR_SETA (1<<3) /* *TA generated externally */ -#define M8xx_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */ -#define M8xx_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */ - -/* -************************************************************************* -* UPM Registers (MxMR) * -************************************************************************* -*/ -#define M8xx_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */ -#define M8xx_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */ -#define M8xx_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */ -#define M8xx_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */ -#define M8xx_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */ -#define M8xx_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */ -#define M8xx_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */ -#define M8xx_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */ -/* -************************************************************************* -* Memory Command Register (MCR) * -************************************************************************* -*/ -#define M8xx_MEMC_MCR_WRITE (0<<30) /* WRITE command */ -#define M8xx_MEMC_MCR_READ (1<<30) /* READ command */ -#define M8xx_MEMC_MCR_RUN (2<<30) /* RUN command */ -#define M8xx_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */ -#define M8xx_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */ -#define M8xx_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */ -#define M8xx_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */ -#define M8xx_MEMC_MCR_MAD(x) (x) /* Machine address */ - - - -/* -************************************************************************* -* SI Mode Register (SIMODE) * -************************************************************************* -*/ -#define M8xx_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ -#define M8xx_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ -#define M8xx_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ -#define M8xx_SI_SMC2_BRG2 (1<<28) -#define M8xx_SI_SMC2_BRG3 (2<<28) -#define M8xx_SI_SMC2_BRG4 (3<<28) -#define M8xx_SI_SMC2_CLK5 (0<<28) -#define M8xx_SI_SMC2_CLK6 (1<<28) -#define M8xx_SI_SMC2_CLK7 (2<<28) -#define M8xx_SI_SMC2_CLK8 (3<<28) -#define M8xx_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ -#define M8xx_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ -#define M8xx_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ -#define M8xx_SI_SMC1_BRG2 (1<<12) -#define M8xx_SI_SMC1_BRG3 (2<<12) -#define M8xx_SI_SMC1_BRG4 (3<<12) -#define M8xx_SI_SMC1_CLK1 (0<<12) -#define M8xx_SI_SMC1_CLK2 (1<<12) -#define M8xx_SI_SMC1_CLK3 (2<<12) -#define M8xx_SI_SMC1_CLK4 (3<<12) - -/* -************************************************************************* -* SDMA Configuration Register (SDCR) * -************************************************************************* -*/ -#define M8xx_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */ -#define M8xx_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */ - -/* -************************************************************************* -* SDMA Status Register (SDSR) * -************************************************************************* -*/ -#define M8xx_SDSR_SBER (1<<7) /* SDMA Channel bus error */ -#define M8xx_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */ -#define M8xx_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */ - -/* -************************************************************************* -* Baud (sic) Rate Generators * -************************************************************************* -*/ -#define M8xx_BRG_RST (1<<17) /* Reset generator */ -#define M8xx_BRG_EN (1<<16) /* Enable generator */ -#define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ -#define M8xx_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ -#define M8xx_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ -#define M8xx_BRG_ATB (1<<13) /* Autobaud */ -#define M8xx_BRG_115200 (21<<1) /* Assume 40 MHz clock */ -#define M8xx_BRG_57600 (32<<1) -#define M8xx_BRG_38400 (64<<1) -#define M8xx_BRG_19200 (129<<1) -#define M8xx_BRG_9600 (259<<1) -#define M8xx_BRG_4800 (520<<1) -#define M8xx_BRG_2400 (1040<<1) -#define M8xx_BRG_1200 (2082<<1) -#define M8xx_BRG_600 ((259<<1) | 1) -#define M8xx_BRG_300 ((520<<1) | 1) -#define M8xx_BRG_150 ((1040<<1) | 1) -#define M8xx_BRG_75 ((2080<<1) | 1) - -#define M8xx_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */ -#define M8xx_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */ -#define M8xx_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */ -#define M8xx_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */ -#define M8xx_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */ -#define M8xx_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */ -#define M8xx_TGCR_STP1 (1<<1) /* Stop timer */ -#define M8xx_TGCR_STP2 (1<<5) /* Stop timer */ -#define M8xx_TGCR_STP3 (1<<9) /* Stop timer */ -#define M8xx_TGCR_STP4 (1<<13) /* Stop timer */ -#define M8xx_TGCR_RST1 (1<<0) /* Enable timer */ -#define M8xx_TGCR_RST2 (1<<4) /* Enable timer */ -#define M8xx_TGCR_RST3 (1<<8) /* Enable timer */ -#define M8xx_TGCR_RST4 (1<<12) /* Enable timer */ -#define M8xx_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */ -#define M8xx_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */ - -#define M8xx_TMR_PS(x) ((x)<<8) /* Timer prescaler */ -#define M8xx_TMR_CE_RISE (1<<6) /* Capture on rising edge */ -#define M8xx_TMR_CE_FALL (2<<6) /* Capture on falling edge */ -#define M8xx_TMR_CE_ANY (3<<6) /* Capture on any edge */ -#define M8xx_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */ -#define M8xx_TMR_ORI (1<<4) /* Interrupt on reaching reference */ -#define M8xx_TMR_RESTART (1<<3) /* Restart timer after reference */ -#define M8xx_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */ -#define M8xx_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */ -#define M8xx_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */ -#define M8xx_TMR_TGATE (1<<0) /* TGATE controls timer */ - -#define M8xx_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */ -#define M8xx_PISCR_PS (1<<7) /* PIT Interrupt state */ -#define M8xx_PISCR_PIE (1<<2) /* PIT interrupt enable */ -#define M8xx_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */ -#define M8xx_PISCR_PTE (1<<0) /* PIT enable */ - -#define M8xx_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ -#define M8xx_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ -#define M8xx_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ -#define M8xx_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ -#define M8xx_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ -#define M8xx_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ -#define M8xx_TBSCR_TBE (1<<0) /* enable TB and decrementer */ - -#define M8xx_SIMASK_IRM0 (1<<31) -#define M8xx_SIMASK_LVM0 (1<<30) -#define M8xx_SIMASK_IRM1 (1<<29) -#define M8xx_SIMASK_LVM1 (1<<28) -#define M8xx_SIMASK_IRM2 (1<<27) -#define M8xx_SIMASK_LVM2 (1<<26) -#define M8xx_SIMASK_IRM3 (1<<25) -#define M8xx_SIMASK_LVM3 (1<<24) -#define M8xx_SIMASK_IRM4 (1<<23) -#define M8xx_SIMASK_LVM4 (1<<22) -#define M8xx_SIMASK_IRM5 (1<<21) -#define M8xx_SIMASK_LVM5 (1<<20) -#define M8xx_SIMASK_IRM6 (1<<19) -#define M8xx_SIMASK_LVM6 (1<<18) -#define M8xx_SIMASK_IRM7 (1<<17) -#define M8xx_SIMASK_LVM7 (1<<16) - -#define M8xx_SIUMCR_EARB (1<<31) -#define M8xx_SIUMCR_EARP0 (0<<28) -#define M8xx_SIUMCR_EARP1 (1<<28) -#define M8xx_SIUMCR_EARP2 (2<<28) -#define M8xx_SIUMCR_EARP3 (3<<28) -#define M8xx_SIUMCR_EARP4 (4<<28) -#define M8xx_SIUMCR_EARP5 (5<<28) -#define M8xx_SIUMCR_EARP6 (6<<28) -#define M8xx_SIUMCR_EARP7 (7<<28) -#define M8xx_SIUMCR_DSHW (1<<23) -#define M8xx_SIUMCR_DBGC0 (0<<21) -#define M8xx_SIUMCR_DBGC1 (1<<21) -#define M8xx_SIUMCR_DBGC2 (2<<21) -#define M8xx_SIUMCR_DBGC3 (3<<21) -#define M8xx_SIUMCR_DBPC0 (0<<19) -#define M8xx_SIUMCR_DBPC1 (1<<19) -#define M8xx_SIUMCR_DBPC2 (2<<19) -#define M8xx_SIUMCR_DBPC3 (3<<19) -#define M8xx_SIUMCR_FRC (1<<17) -#define M8xx_SIUMCR_DLK (1<<16) -#define M8xx_SIUMCR_PNCS (1<<15) -#define M8xx_SIUMCR_OPAR (1<<14) -#define M8xx_SIUMCR_DPC (1<<13) -#define M8xx_SIUMCR_MPRE (1<<12) -#define M8xx_SIUMCR_MLRC0 (0<<10) -#define M8xx_SIUMCR_MLRC1 (1<<10) -#define M8xx_SIUMCR_MLRC2 (2<<10) -#define M8xx_SIUMCR_MLRC3 (3<<10) -#define M8xx_SIUMCR_AEME (1<<9) -#define M8xx_SIUMCR_SEME (1<<8) -#define M8xx_SIUMCR_BSC (1<<7) -#define M8xx_SIUMCR_GB5E (1<<6) -#define M8xx_SIUMCR_B2DD (1<<5) -#define M8xx_SIUMCR_B3DD (1<<4) - -/* - * Value to write to a key register to unlock the corresponding SIU register - */ -#define M8xx_UNLOCK_KEY 0x55CCAA33 - -/* -************************************************************************* -* MPC8xx INTERNAL MEMORY MAP REGISTERS (IMMR provides base address) * -************************************************************************* -*/ -typedef struct m8xx_ { - - /* - * SIU Block - */ - uint32_t siumcr; - uint32_t sypcr; -#if defined(mpc860) - uint32_t swt; -#elif defined(mpc821) - uint32_t _pad70; -#endif - uint16_t _pad0; - uint16_t swsr; - uint32_t sipend; - uint32_t simask; - uint32_t siel; - uint32_t sivec; - uint32_t tesr; - uint32_t _pad1[3]; - uint32_t sdcr; - uint8_t _pad2[0x80-0x34]; - - /* - * PCMCIA Block - */ - uint32_t pbr0; - uint32_t por0; - uint32_t pbr1; - uint32_t por1; - uint32_t pbr2; - uint32_t por2; - uint32_t pbr3; - uint32_t por3; - uint32_t pbr4; - uint32_t por4; - uint32_t pbr5; - uint32_t por5; - uint32_t pbr6; - uint32_t por6; - uint32_t pbr7; - uint32_t por7; - uint8_t _pad3[0xe0-0xc0]; - uint32_t pgcra; - uint32_t pgcrb; - uint32_t pscr; - uint32_t _pad4; - uint32_t pipr; - uint32_t _pad5; - uint32_t per; - uint32_t _pad6; - - /* - * MEMC Block - */ - m8xxMEMCRegisters_t memc[8]; - uint8_t _pad7[0x164-0x140]; - uint32_t mar; - uint32_t mcr; - uint32_t _pad8; - uint32_t mamr; - uint32_t mbmr; - uint16_t mstat; - uint16_t mptpr; - uint32_t mdr; - uint8_t _pad9[0x200-0x180]; - - /* - * System integration timers - */ - uint16_t tbscr; - uint16_t _pad10; - uint32_t tbreff0; - uint32_t tbreff1; - uint8_t _pad11[0x220-0x20c]; - uint16_t rtcsc; - uint16_t _pad12; - uint32_t rtc; - uint32_t rtsec; - uint32_t rtcal; - uint32_t _pad13[4]; - uint16_t piscr; - uint16_t _pad14; - uint16_t pitc; - uint16_t _pad_14_1; - uint16_t pitr; - uint16_t _pad_14_2; - uint8_t _pad15[0x280-0x24c]; - - - /* - * Clocks and Reset - */ - uint32_t sccr; - uint32_t plprcr; - uint32_t rsr; - uint8_t _pad16[0x300-0x28c]; - - - /* - * System integration timers keys - */ - uint32_t tbscrk; - uint32_t tbreff0k; - uint32_t tbreff1k; - uint32_t tbk; - uint32_t _pad17[4]; - uint32_t rtcsk; - uint32_t rtck; - uint32_t rtseck; - uint32_t rtcalk; - uint32_t _pad18[4]; - uint32_t piscrk; - uint32_t pitck; - uint8_t _pad19[0x380-0x348]; - - /* - * Clocks and Reset Keys - */ - uint32_t sccrk; - uint32_t plprck; - uint32_t rsrk; - uint8_t _pad20[0x400-0x38c]; - uint8_t _pad21[0x800-0x400]; - uint8_t _pad22[0x860-0x800]; - - - /* - * I2C - */ - uint8_t i2mod; - uint8_t _pad23[3]; - uint8_t i2add; - uint8_t _pad24[3]; - uint8_t i2brg; - uint8_t _pad25[3]; - uint8_t i2com; - uint8_t _pad26[3]; - uint8_t i2cer; - uint8_t _pad27[3]; - uint8_t i2cmr; - uint8_t _pad28[0x900-0x875]; - - /* - * DMA Block - */ - uint32_t _pad29; - uint32_t sdar; - uint8_t sdsr; - uint8_t _pad30[3]; - uint8_t sdmr; - uint8_t _pad31[3]; - uint8_t idsr1; - uint8_t _pad32[3]; - uint8_t idmr1; - uint8_t _pad33[3]; - uint8_t idsr2; - uint8_t _pad34[3]; - uint8_t idmr2; - uint8_t _pad35[0x930-0x91d]; - - /* - * CPM Interrupt Control Block - */ - uint16_t civr; - uint8_t _pad36[14]; - uint32_t cicr; - uint32_t cipr; - uint32_t cimr; - uint32_t cisr; - - /* - * I/O Port Block - */ - uint16_t padir; - uint16_t papar; - uint16_t paodr; - uint16_t padat; - uint8_t _pad37[8]; - uint16_t pcdir; - uint16_t pcpar; - uint16_t pcso; - uint16_t pcdat; - uint16_t pcint; - uint8_t _pad39[6]; - uint16_t pddir; - uint16_t pdpar; - uint16_t _pad40; - uint16_t pddat; - uint8_t _pad41[8]; - - /* - * CPM Timers Block - */ - uint16_t tgcr; - uint8_t _pad42[14]; - uint16_t tmr1; - uint16_t tmr2; - uint16_t trr1; - uint16_t trr2; - uint16_t tcr1; - uint16_t tcr2; - uint16_t tcn1; - uint16_t tcn2; - uint16_t tmr3; - uint16_t tmr4; - uint16_t trr3; - uint16_t trr4; - uint16_t tcr3; - uint16_t tcr4; - uint16_t tcn3; - uint16_t tcn4; - uint16_t ter1; - uint16_t ter2; - uint16_t ter3; - uint16_t ter4; - uint8_t _pad43[8]; - - /* - * CPM Block - */ - uint16_t cpcr; - uint16_t _pad44; - uint16_t rccr; - uint8_t _pad45; - uint8_t rmds; - uint32_t rmdr; - uint16_t rctr1; - uint16_t rctr2; - uint16_t rctr3; - uint16_t rctr4; - uint16_t _pad46; - uint16_t rter; - uint16_t _pad47; - uint16_t rtmr; - uint8_t _pad48[0x9f0-0x9dc]; - - /* - * BRG Block - */ - uint32_t brgc1; - uint32_t brgc2; - uint32_t brgc3; - uint32_t brgc4; - - /* - * SCC Block - */ - m8xxSCCRegisters_t scc1; - m8xxSCCRegisters_t scc2; -#if defined(mpc860) - m8xxSCCRegisters_t scc3; - m8xxSCCRegisters_t scc4; -#elif defined(mpc821) - uint8_t _pad72[0xa80-0xa40]; -#endif - - /* - * SMC Block - */ - m8xxSMCRegisters_t smc1; - m8xxSMCRegisters_t smc2; - - /* - * SPI Block - */ - uint16_t spmode; - uint16_t _pad49[2]; - uint8_t spie; - uint8_t _pad50; - uint16_t _pad51; - uint8_t spim; - uint8_t _pad52[2]; - uint8_t spcom; - uint16_t _pad53[2]; - - /* - * PIP Block - */ - uint16_t pipc; - uint16_t _pad54; - uint16_t ptpr; - uint32_t pbdir; - uint32_t pbpar; - uint16_t _pad55; - uint16_t pbodr; - uint32_t pbdat; - uint32_t _pad56[6]; - - /* - * SI Block - */ - uint32_t simode; - uint8_t sigmr; - uint8_t _pad57; - uint8_t sistr; - uint8_t sicmr; - uint32_t _pad58; - uint32_t sicr; - uint16_t sirp[2]; - uint32_t _pad59[3]; - uint8_t _pad60[0xc00-0xb00]; - uint8_t siram[512]; -#if defined(mpc860) - /* - * This is only used on the MPC8xxT - for the Fast Ethernet Controller (FEC) - */ - m8xxFECRegisters_t fec; -#elif defined(mpc821) - uint8_t lcdram[512]; -#endif - uint8_t _pad62[0x2000-0x1000]; - - /* - * Dual-port RAM - */ - uint8_t dpram0[0x200]; /* BD/DATA/UCODE */ - uint8_t dpram1[0x200]; /* BD/DATA/UCODE */ - uint8_t dpram2[0x400]; /* BD/DATA/UCODE */ - uint8_t dpram3[0x600]; /* BD/DATA*/ - uint8_t dpram4[0x200]; /* BD/DATA/UCODE */ - uint8_t _pad63[0x3c00-0x3000]; - - /* When using SCC1 for ethernet, we lose the use of I2C since - * their parameters would overlap. Motorola has a microcode - * patch to move parameters around so that both can be used - * together. It is available on their web site somewhere - * under http://www.mot.com/mpc8xx. If ethernet is used on - * one (or more) of the other SCCs, then other CPM features - * will be unavailable: - * SCC2 -> lose SPI - * SCC3 -> lose SMC1 - * SCC4 -> lose SMC2 - * However, Ethernet only works on SCC1 on the 8xx. - */ - m8xxSCCENparms_t scc1p; - uint8_t _rsv1[0xCB0-0xC00-sizeof(m8xxSCCENparms_t)]; - m8xxMiscParms_t miscp; - uint8_t _rsv2[0xcc0-0xCB0-sizeof(m8xxMiscParms_t)]; - m8xxIDMAparms_t idma1p; - uint8_t _rsv3[0xd00-0xcc0-sizeof(m8xxIDMAparms_t)]; - - m8xxSCCparms_t scc2p; - uint8_t _rsv4[0xD80-0xD00-sizeof(m8xxSCCparms_t)]; - m8xxSPIparms_t spip; - uint8_t _rsv5[0xDB0-0xD80-sizeof(m8xxSPIparms_t)]; - m8xxTimerParms_t tmp; - uint8_t _rsv6[0xDC0-0xDB0-sizeof(m8xxTimerParms_t)]; - m8xxIDMAparms_t idma2p; - uint8_t _rsv7[0xE00-0xDC0-sizeof(m8xxIDMAparms_t)]; - - m8xxSCCparms_t scc3p; /* Not available on MPC821 */ - uint8_t _rsv8[0xE80-0xE00-sizeof(m8xxSCCparms_t)]; - m8xxSMCparms_t smc1p; - uint8_t _rsv9[0xEC0-0xE80-sizeof(m8xxSMCparms_t)]; - m8xxDSPparms_t dsp1p; - uint8_t _rsv10[0xF00-0xEC0-sizeof(m8xxDSPparms_t)]; - - m8xxSCCparms_t scc4p; /* Not available on MPC821 */ - uint8_t _rsv11[0xF80-0xF00-sizeof(m8xxSCCparms_t)]; - m8xxSMCparms_t smc2p; - uint8_t _rsv12[0xFC0-0xF80-sizeof(m8xxSMCparms_t)]; - m8xxDSPparms_t dsp2p; - uint8_t _rsv13[0x1000-0xFC0-sizeof(m8xxDSPparms_t)]; -} m8xx_t; - -extern volatile m8xx_t m8xx; - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _MPC8XX_H */ diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq_supp.h b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq_supp.h deleted file mode 100644 index 65af48c87f..0000000000 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq_supp.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef IRQ_SHARED_IRQ_C_GLUE_H -#define IRQ_SHARED_IRQ_C_GLUE_H -/* - * This header describes the routines that are needed by the shared - * version of 'irq.c' (implementing the RTEMS irq API). They - * must be provided by the BSP. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef BSP_SHARED_HANDLER_SUPPORT -#define BSP_SHARED_HANDLER_SUPPORT 1 -#endif - -#include <rtems.h> -#include <rtems/irq.h> - -#include <bsp/vectors.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * PIC-independent functions to enable/disable interrupt lines at - * the pic. - * - * NOTE: the routines must ignore requests for enabling/disabling - * interrupts that are outside of the range handled by the - * PIC(s). - */ -extern void BSP_enable_irq_at_pic(const rtems_irq_number irqLine); -/* - * RETURNS: nonzero (> 0 ) if irq was enabled originally, zero if irq - * was off and negative value if there was an error. - */ -extern int BSP_disable_irq_at_pic(const rtems_irq_number irqLine); - -/* - * Initialize the PIC. - */ -extern int BSP_setup_the_pic(rtems_irq_global_settings* config); - -/* IRQ dispatcher to be defined by the PIC driver; note that it MUST - * implement shared interrupts. - * Note also that the exception frame passed to this handler is not very - * meaningful. Only the volatile registers and vector info are stored. - * - ******************************************************************* - * The routine must return zero if the interrupt was handled. If a - * nonzero value is returned the dispatcher may panic and flag an - * uncaught exception. - ******************************************************************* - */ -int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum); - -/* - * Snippet to be used by PIC drivers and by bsp_irq_dispatch_list - * traverses list of shared handlers for a given interrupt - * - */ - -static inline void -bsp_irq_dispatch_list_base( - rtems_irq_connect_data *tbl, - unsigned irq, - rtems_irq_hdl sentinel -) -{ - rtems_irq_connect_data* vchain; - for( vchain = &tbl[irq]; - ((intptr_t)vchain != -1 && vchain->hdl != sentinel); - vchain = (rtems_irq_connect_data*)vchain->next_handler ) - { - vchain->hdl(vchain->handle); - } -} - - -/* - * Snippet to be used by PIC drivers; - * enables interrupts, traverses list of - * shared handlers for a given interrupt - * and restores original irq level - * - * Note that _ISR_Get_level() & friends are preferable to - * manipulating MSR directly. - */ - -static inline void -bsp_irq_dispatch_list( - rtems_irq_connect_data *tbl, - unsigned irq, - rtems_irq_hdl sentinel -) -{ - register uint32_t l_orig; - - l_orig = _ISR_Get_level(); - - /* Enable all interrupts */ - _ISR_Set_level(0); - - - bsp_irq_dispatch_list_base( tbl, irq, sentinel ); - - /* Restore original level */ - _ISR_Set_level(l_orig); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h deleted file mode 100644 index 81526eb4b0..0000000000 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - * @file - * - * @ingroup ppc_exc - * @ingroup ppc_exc_frame - * - * @brief PowerPC Exceptions API. - */ - -/* - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu> - * - * Copyright (C) 2009 embedded brains GmbH. - * - * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com> - * to support 603, 603e, 604, 604e exceptions - * - * Moved to "libcpu/powerpc/new-exceptions" and consolidated - * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> - * to be common for all PPCs with new exceptions. - * - * Derived from file "libcpu/powerpc/new-exceptions/raw_exception.h". - * Derived from file "libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h". - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* DO NOT INTRODUCE #ifdef <cpu_flavor> in this file */ - -#ifndef LIBCPU_VECTORS_H -#define LIBCPU_VECTORS_H - -#include <bspopts.h> -#include <rtems/score/cpuimpl.h> -#include <libcpu/powerpc-utility.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup ppc_exc PowerPC Exceptions - * - * @brief XXX - * - * @{ - */ - -#define ASM_RESET_VECTOR 0x01 -#define ASM_MACH_VECTOR 0x02 -#define ASM_PROT_VECTOR 0x03 -#define ASM_ISI_VECTOR 0x04 -#define ASM_EXT_VECTOR 0x05 -#define ASM_ALIGN_VECTOR 0x06 -#define ASM_PROG_VECTOR 0x07 -#define ASM_FLOAT_VECTOR 0x08 -#define ASM_DEC_VECTOR 0x09 -#define ASM_SYS_VECTOR 0x0C -#define ASM_TRACE_VECTOR 0x0D - -#define ASM_PPC405_APU_UNAVAIL_VECTOR ASM_60X_VEC_ASSIST_VECTOR - -#define ASM_8XX_FLOATASSIST_VECTOR 0x0E -#define ASM_8XX_SOFTEMUL_VECTOR 0x10 -#define ASM_8XX_ITLBMISS_VECTOR 0x11 -#define ASM_8XX_DTLBMISS_VECTOR 0x12 -#define ASM_8XX_ITLBERROR_VECTOR 0x13 -#define ASM_8XX_DTLBERROR_VECTOR 0x14 -#define ASM_8XX_DBREAK_VECTOR 0x1C -#define ASM_8XX_IBREAK_VECTOR 0x1D -#define ASM_8XX_PERIFBREAK_VECTOR 0x1E -#define ASM_8XX_DEVPORT_VECTOR 0x1F - -#define ASM_5XX_FLOATASSIST_VECTOR 0x0E -#define ASM_5XX_SOFTEMUL_VECTOR 0x10 -#define ASM_5XX_IPROT_VECTOR 0x13 -#define ASM_5XX_DPROT_VECTOR 0x14 -#define ASM_5XX_DBREAK_VECTOR 0x1C -#define ASM_5XX_IBREAK_VECTOR 0x1D -#define ASM_5XX_MEBREAK_VECTOR 0x1E -#define ASM_5XX_NMEBREAK_VECTOR 0x1F - -#define ASM_60X_VEC_VECTOR 0x0A -#define ASM_60X_PERFMON_VECTOR 0x0F -#define ASM_60X_IMISS_VECTOR 0x10 -#define ASM_60X_DLMISS_VECTOR 0x11 -#define ASM_60X_DSMISS_VECTOR 0x12 -#define ASM_60X_ADDR_VECTOR 0x13 -#define ASM_60X_SYSMGMT_VECTOR 0x14 -#define ASM_60X_VEC_ASSIST_VECTOR 0x16 -#define ASM_60X_ITM_VECTOR 0x17 - -/* Book E */ -#define ASM_BOOKE_CRIT_VECTOR 0x01 -/* We could use the std. decrementer vector # on bookE, too, - * but the bookE decrementer has slightly different semantics - * so we use a different vector (which happens to be - * the PIT vector on the 405 which is like the booke decrementer) - */ -#define ASM_BOOKE_DEC_VECTOR 0x10 -#define ASM_BOOKE_ITLBMISS_VECTOR 0x11 -#define ASM_BOOKE_DTLBMISS_VECTOR 0x12 -#define ASM_BOOKE_FIT_VECTOR 0x13 -#define ASM_BOOKE_WDOG_VECTOR 0x14 -#define ASM_BOOKE_APU_VECTOR 0x18 -#define ASM_BOOKE_DEBUG_VECTOR ASM_TRACE_VECTOR - -/* e200 and e500 */ -#define ASM_E500_SPE_UNAVAILABLE_VECTOR ASM_60X_VEC_VECTOR -#define ASM_E500_EMB_FP_DATA_VECTOR 0x19 -#define ASM_E500_EMB_FP_ROUND_VECTOR 0x1A -#define ASM_E500_PERFMON_VECTOR ASM_60X_PERFMON_VECTOR - -/* e300 */ -#define ASM_E300_CRIT_VECTOR 0x0A -#define ASM_E300_PERFMON_VECTOR ASM_60X_PERFMON_VECTOR -#define ASM_E300_IMISS_VECTOR ASM_60X_IMISS_VECTOR /* Special case: Shadowed GPRs */ -#define ASM_E300_DLMISS_VECTOR ASM_60X_DLMISS_VECTOR /* Special case: Shadowed GPRs */ -#define ASM_E300_DSMISS_VECTOR ASM_60X_DSMISS_VECTOR /* Special case: Shadowed GPRs */ -#define ASM_E300_ADDR_VECTOR ASM_60X_ADDR_VECTOR -#define ASM_E300_SYSMGMT_VECTOR ASM_60X_SYSMGMT_VECTOR - -/* - * If you change that number make sure to adjust the wrapper code in ppc_exc.S - * and that ppc_exc_handler_table will be correctly initialized. - */ -#define LAST_VALID_EXC 0x1F - -/* DO NOT USE -- this symbol is DEPRECATED - * (only used by libbsp/shared/vectors/vectors.S - * which should not be used by new BSPs). - */ -#define ASM_60X_VEC_VECTOR_OFFSET 0xf20 - -#define ASM_PPC405_FIT_VECTOR_OFFSET 0x1010 -#define ASM_PPC405_WDOG_VECTOR_OFFSET 0x1020 -#define ASM_PPC405_TRACE_VECTOR_OFFSET 0x2000 - -/** @} */ - -/** - * @defgroup ppc_exc_frame PowerPC Exception Frame - * - * @brief XXX - * - * @{ - */ - -/* - * The callee (high level exception code written in C) - * will store the Link Registers (return address) at entry r1 + 4 !!!. - * So let room for it!!!. - */ -#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 - -#define EXC_GENERIC_SIZE (PPC_EXC_FRAME_SIZE + PPC_STACK_RED_ZONE_SIZE) - -#define PPC_EXC_INTERRUPT_FRAME_SIZE CPU_INTERRUPT_FRAME_SIZE - -#if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC) -#define EXC_VEC_OFFSET EXC_GENERIC_SIZE -#ifndef PPC_CACHE_ALIGNMENT -#error "Missing include file!" -#endif -/* 20 volatile registers - * + cache-aligned area for vcsr, vrsave - * + area for alignment - */ -#define EXC_VEC_SIZE (16*20 + 2*PPC_CACHE_ALIGNMENT) -#else -#define EXC_VEC_SIZE (0) -#endif - -/* - * maintain the EABI requested 8 bytes aligment - * As SVR4 ABI requires 16, make it 16 (as some - * exception may need more registers to be processed...) - */ -#define EXCEPTION_FRAME_END (EXC_GENERIC_SIZE + EXC_VEC_SIZE) - -/** @} */ - -#ifndef ASM - -/** - * @ingroup ppc_exc_frame - * - * @{ - */ - -typedef CPU_Exception_frame BSP_Exception_frame; - -/** @} */ - -/** - * @ingroup ppc_exc - * - * @{ - */ - -/** - * @brief Global exception handler type. - */ -typedef void (*exception_handler_t)(BSP_Exception_frame*); - -/** - * @brief Default global exception handler. - */ -void C_exception_handler(BSP_Exception_frame* excPtr); - -void BSP_printStackTrace(const BSP_Exception_frame *excPtr); - -/** - * @brief Exception categories. - * - * Exceptions of different categories use different SRR registers to save the - * machine state and do different things in the prologue and epilogue. - * - * For now, the CPU descriptions assume this fits into 8 bits. - */ -typedef enum { - PPC_EXC_INVALID = 0, - PPC_EXC_ASYNC = 1, - PPC_EXC_CLASSIC = 2, - PPC_EXC_CLASSIC_ASYNC = PPC_EXC_CLASSIC | PPC_EXC_ASYNC, - PPC_EXC_405_CRITICAL = 4, - PPC_EXC_405_CRITICAL_ASYNC = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC, - PPC_EXC_BOOKE_CRITICAL = 6, - PPC_EXC_BOOKE_CRITICAL_ASYNC = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC, - PPC_EXC_E500_MACHCHK = 8, - PPC_EXC_E500_MACHCHK_ASYNC = PPC_EXC_E500_MACHCHK | PPC_EXC_ASYNC, - PPC_EXC_NAKED = 10 -} ppc_exc_category; - -/** - * @brief Categorie set type. - */ -typedef uint8_t ppc_exc_categories [LAST_VALID_EXC + 1]; - -static inline bool ppc_exc_is_valid_category(ppc_exc_category category) -{ - return (unsigned) category <= (unsigned) PPC_EXC_NAKED; -} - -/** - * @brief Returns the entry address of the vector. - * - * @param[in] vector The vector number. - * @param[in] vector_base The vector table base address. - */ -void *ppc_exc_vector_address(unsigned vector, void *vector_base); - -/** - * @brief Returns the category set for a CPU of type @a cpu, or @c NULL if - * there is no category set available for this CPU. - */ -const ppc_exc_categories *ppc_exc_categories_for_cpu(ppc_cpu_id_t cpu); - -/** - * @brief Returns the category set for the current CPU, or @c NULL if there is - * no category set available for this CPU. - */ -static inline const ppc_exc_categories *ppc_exc_current_categories(void) -{ - return ppc_exc_categories_for_cpu(ppc_cpu_current()); -} - -/** - * @brief Returns the category for the vector @a vector using the category set - * @a categories. - */ -ppc_exc_category ppc_exc_category_for_vector( - const ppc_exc_categories *categories, - unsigned vector -); - -/** - * @brief Makes a minimal prologue for the vector @a vector with the category - * @a category. - * - * The minimal prologue will be copied to @a prologue. Not more than - * @a prologue_size bytes will be copied. Returns the actual minimal prologue - * size in bytes in @a prologue_size. - * - * @retval RTEMS_SUCCESSFUL Minimal prologue successfully made. - * @retval RTEMS_INVALID_ID Invalid vector number. - * @retval RTEMS_INVALID_NUMBER Invalid category. - * @retval RTEMS_INVALID_SIZE Prologue size to small. - */ -rtems_status_code ppc_exc_make_prologue( - unsigned vector, - void *vector_base, - ppc_exc_category category, - uint32_t *prologue, - size_t *prologue_size -); - -static inline void ppc_exc_initialize_interrupt_stack( - uintptr_t stack_begin, - uintptr_t stack_size -) -{ - uintptr_t stack_end = stack_begin + stack_size; - uintptr_t stack_pointer = stack_end - PPC_MINIMUM_STACK_FRAME_SIZE; - - /* Ensure proper interrupt stack alignment */ - stack_pointer &= ~((uintptr_t) CPU_STACK_ALIGNMENT - 1); - - /* Tag interrupt stack bottom */ - *(uint32_t *) stack_pointer = 0; - - /* Move interrupt stack values to special purpose registers */ - PPC_SET_SPECIAL_PURPOSE_REGISTER(SPRG1, stack_pointer); - PPC_SET_SPECIAL_PURPOSE_REGISTER(SPRG2, stack_begin); -} - -/** - * @brief Initializes the exception handling. - * - * @see ppc_exc_initialize(). - */ -void ppc_exc_initialize_with_vector_base( - uintptr_t interrupt_stack_begin, - uintptr_t interrupt_stack_size, - void *vector_base -); - -/** - * @brief Initializes the exception handling. - * - * If the initialization fails, then this is a fatal error. The fatal error - * source is RTEMS_FATAL_SOURCE_BSP and the fatal error code is - * PPC_FATAL_EXCEPTION_INITIALIZATION. - * - * Possible error reasons are - * - no category set available for the current CPU, - * - the register r13 does not point to the small data area anchor required by - * SVR4/EABI, or - * - the minimal prologue creation failed. - */ -static inline void ppc_exc_initialize( - uintptr_t interrupt_stack_begin, - uintptr_t interrupt_stack_size -) -{ - ppc_exc_initialize_with_vector_base( - interrupt_stack_begin, - interrupt_stack_size, - NULL - ); -} - -/** - * @brief High-level exception handler type. - * - * @retval 0 The exception was handled and normal execution may resume. - * @retval -1 Reject the exception resulting in a call of the global exception - * handler. - * @retval other Reserved, do not use. - */ -typedef int (*ppc_exc_handler_t)(BSP_Exception_frame *f, unsigned vector); - -/** - * @brief Default high-level exception handler. - * - * @retval -1 Always. - */ -int ppc_exc_handler_default(BSP_Exception_frame *f, unsigned int vector); - -#ifndef PPC_EXC_CONFIG_BOOKE_ONLY - -/** - * @brief Bits for MSR update. - * - * Bits in MSR that are enabled during execution of exception handlers / ISRs - * (on classic PPC these are DR/IR/RI [default], on bookE-style CPUs they should - * be set to 0 during initialization) - * - * By default, the setting of these bits that is in effect when exception - * handling is initialized is used. - */ -extern uint32_t ppc_exc_msr_bits; - -#endif /* PPC_EXC_CONFIG_BOOKE_ONLY */ - -/** - * @brief Cache write back check flag. - * - * (See README under CAVEATS). During initialization - * a check is performed to assert that write-back - * caching is enabled for memory accesses. If a BSP - * runs entirely without any caching then it should - * set this variable to zero prior to initializing - * exceptions in order to skip the test. - * NOTE: The code does NOT support mapping memory - * with cache-attributes other than write-back - * (unless the entire cache is physically disabled) - */ -extern uint32_t ppc_exc_cache_wb_check; - -#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER - /** - * @brief High-level exception handler table. - */ - extern ppc_exc_handler_t ppc_exc_handler_table [LAST_VALID_EXC + 1]; - - /** - * @brief Global exception handler. - */ - extern exception_handler_t globalExceptHdl; -#else /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ - /** - * @brief High-level exception handler table. - */ - extern const ppc_exc_handler_t ppc_exc_handler_table [LAST_VALID_EXC + 1]; - - /** - * @brief Interrupt dispatch routine provided by BSP. - */ - void bsp_interrupt_dispatch(uintptr_t exception_number); -#endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ - -/** - * @brief Set high-level exception handler. - * - * Hook C exception handlers. - * - handlers for asynchronous exceptions run on the ISR stack - * with thread-dispatching disabled. - * - handlers for synchronous exceptions run on the task stack - * with thread-dispatching enabled. - * - * If a particular slot is NULL then the traditional 'globalExcHdl' is used. - * - * ppc_exc_set_handler() registers a handler (returning 0 on success, - * -1 if the vector argument is too big). - * - * It is legal to set a NULL handler. This leads to the globalExcHdl - * being called if an exception for 'vector' occurs. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_INVALID_ID Invalid vector number. - * @retval RTEMS_RESOURCE_IN_USE Handler table is read-only and handler does - * not match. - */ -rtems_status_code ppc_exc_set_handler(unsigned vector, ppc_exc_handler_t hdl); - -/** - * @brief Returns the currently active high-level exception handler. - */ -ppc_exc_handler_t ppc_exc_get_handler(unsigned vector); - -/** - * @brief Function for DAR access. - * - * CPU support may store the address of a function here - * that can be used by the default exception handler to - * obtain fault-address info which is helpful. Unfortunately, - * the SPR holding this information is not uniform - * across PPC families so we need assistance from - * CPU support - */ -extern uint32_t (*ppc_exc_get_DAR)(void); - -void -ppc_exc_wrapup(BSP_Exception_frame *f); - -/** - * @brief Standard aligment handler. - * - * @retval 0 Performed a dcbz instruction. - * @retval -1 Otherwise. - */ -int ppc_exc_alignment_handler(BSP_Exception_frame *frame, unsigned excNum); - -/** @} */ - -/* - * Compatibility with pc386 - */ -typedef exception_handler_t cpuExcHandlerType; - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* LIBCPU_VECTORS_H */ diff --git a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h deleted file mode 100644 index 98ebbe28a2..0000000000 --- a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - -Constants for manipulating system registers of PPC 405EX in C - -Michael Hamel ADInstruments May 2008 - -*/ - -#include <libcpu/powerpc-utility.h> -/* Indirect access to Clocking/Power-On registers */ -#define CPR0_DCR_BASE 0x0C -#define cprcfga (CPR0_DCR_BASE+0x0) -#define cprcfgd (CPR0_DCR_BASE+0x1) - -#define mtcpr(reg, d) \ - do { \ - PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ - PPC_SET_DEVICE_CONTROL_REGISTER(cprcfgd,d); \ - } while (0) - -#define mfcpr(reg, d) \ - do { \ - PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ - d = PPC_DEVICE_CONTROL_REGISTER(cprcfgd); \ - } while (0) - - -/* Indirect access to System registers */ -#define SDR_DCR_BASE 0x0E -#define sdrcfga (SDR_DCR_BASE+0x0) -#define sdrcfgd (SDR_DCR_BASE+0x1) - -#define mtsdr(reg, d) \ - do { \ - PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ - PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfgd,d); \ - } while (0) - -#define mfsdr(reg, d) \ - do { \ - PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ - d = PPC_DEVICE_CONTROL_REGISTER(sdrcfgd); \ - } while (0) - -/* Indirect access to EBC registers */ -#define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) -#define ebccfgd (EBC_DCR_BASE+0x1) - -#define mtebc(reg, d) \ - do { \ - PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ - PPC_SET_DEVICE_CONTROL_REGISTER(ebccfgd,d); \ - } while (0) - -#define mfebc(reg, d) \ - do { \ - PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ - d = PPC_DEVICE_CONTROL_REGISTER(ebccfgd); \ - } while (0) - -/* EBC DCRs */ -enum { - /* - EBC0_B0CR = 0, - EBC0_B1CR = 1, - EBC0_B2CR = 2, - EBC0_B3CR = 3, - EBC0_B0AP = 0x10, - EBC0_B1AP = 0x11, - EBC0_B2AP = 0x12, - EBC0_B3AP = 0x13, - EBC0_BEAR = 0x20, - EBC0_BESR = 0x21, - EBC0_CFG = 0x23, - */ - EBC0_CID = 0x24 -}; - -enum { - SDR0_PINSTP = 0x40, - SDR0_UART0 = 0x120, - SDR0_UART1 = 0x121, - SDR0_C405 = 0x180, - SDR0_SRST0 = 0x200, - SDR0_MALTBL = 0x280, - SDR0_MALRBL = 0x2A0, - SDR0_MALTBS = 0x2C0, - SDR0_MALRBS = 0x2E0, - SDR0_PFC2 = 0x4102, - SDR0_MFR = 0x4300, - SDR0_EMAC0RXST = 0x4301, - SDR0_HSF = 0x4400 -}; - -enum { - CPR0_CLKUPD = 0x20, - CPR0_PLLC = 0x40, - CPR0_PLLD = 0x60, - CPR0_CPUD = 0x80, - CPR0_PLBD = 0xA0, - CPR0_OPBD = 0xC0, - CPR0_PERD = 0xE0, - CPR0_AHBD = 0x100, - CPR0_ICFG = 0x140 -}; - -/* Memory-mapped registers */ - - -/*======================= Ethernet =================== */ - -enum { - EMAC0EXAddress = 0xEF600900, - EMAC1EXAddress = 0xEF600A00, - - /* 405EX-specific bits in EMAC_MR1 */ - keEMAC1000Mbps = 0x00800000, - keEMAC16KRxFIFO = 0x00280000, - keEMAC8KRxFIFO = 0x00200000, - keEMAC4KRxFIFO = 0x00180000, - keEMAC2KRxFIFO = 0x00100000, - keEMAC1KRxFIFO = 0x00080000, - keEMAC16KTxFIFO = 0x00050000, - keEMAC8KTxFIFO = 0x00040000, - keEMAC4KTxFIFO = 0x00030000, - keEMAC2KTxFIFO = 0x00020000, - keEMAC1KTxFIFO = 0x00010000, - keEMACJumbo = 0x00000800, - keEMACIPHYAddr4 = 0x180, - keEMACOPB50MHz = 0x00, - keEMACOPB66MHz = 0x08, - keEMACOPB83MHz = 0x10, - keEMACOPB100MHz = 0x18, - keEMACOPBGt100 = 0x20, - - /* 405EX-specific bits in MAL0_CFG */ - keMALRdMaxBurst4 = 0, - keMALRdMaxBurst8 = 0x00100000, - keMALRdMaxBurst16 = 0x00200000, - keMALRdMaxBurst32 = 0x00300000, - - keMALWrLowPriority = 0, - keMALWrMedLowPriority = 0x00040000, - keMALWrMedHiPriority = 0x00080000, - keMALWrHighPriority = 0x000C0000, - - keMALWrMaxBurst4 = 0, - keMALWrMaxBurst8 = 0x00010000, - keMALWrMaxBurst16 = 0x00020000, - keMALWrMaxBurst32 = 0x00030000, - - /* 405EX-specific STA bits */ - keSTARun = 0x8000, - keSTADirectRd = 0x1000, - keSTADirectWr = 0x0800, - keSTAIndirAddr = 0x2000, - keSTAIndirRd = 0x3000, - keSTAIndirWr = 0x2800 -}; - -typedef struct GPIORegisters { - uint32_t OR; - uint32_t GPIO_TCR; /* Note that TCR is defined as a DCR name */ - uint32_t OSRL; - uint32_t OSRH; - uint32_t TSRL; - uint32_t TSRH; - uint32_t ODR; - uint32_t IR; - uint32_t RR1; - uint32_t RR2; - uint32_t RR3; - uint32_t unknown; - uint32_t ISR1L; - uint32_t ISR1H; - uint32_t ISR2L; - uint32_t ISR2H; - uint32_t ISR3L; - uint32_t ISR3H; -} GPIORegisters; - -enum { GPIOAddress = 0xEF600800 }; - -typedef struct RGMIIRegisters { - uint32_t FER; - uint32_t SSR; -} RGMIIRegisters; - -enum { RGMIIAddress = 0xEF600B00 }; - diff --git a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h deleted file mode 100644 index 9cf46a780a..0000000000 --- a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h +++ /dev/null @@ -1,214 +0,0 @@ - -/* SDRAM DCRs */ -enum { - SDRAM0_BESR0 = 0, - SDRAM0_BESR1 = 8, - SDRAM0_BEAR = 0x10, - SDRAM0_CFG = 0x20, - SDRAM0_STATUS = 0x24, - SDRAM0_RTR = 0x30, - SDRAM0_PMIT = 0x34, - SDRAM0_TR = 0x80 -}; - - -/* EBC DCRs */ -enum { - EBC0_B0CR = 0, - EBC0_B1CR = 1, - EBC0_B2CR = 2, - EBC0_B3CR = 3, - EBC0_B4CR = 4, - EBC0_B5CR = 5, - EBC0_B6CR = 6, - EBC0_B7CR = 7, - EBC0_B0AP = 0x10, - EBC0_B1AP = 0x11, - EBC0_B2AP = 0x12, - EBC0_B3AP = 0x13, - EBC0_B4AP = 0x14, - EBC0_B5AP = 0x15, - EBC0_B6AP = 0x16, - EBC0_B7AP = 0x17, - EBC0_BEAR = 0x20, - EBC0_BESR0 = 0x21, - EBC0_BESR1 = 0x22, - EBC0_CFG = 0x23 -}; - -/* MAL DCRs, have to be #defines */ -#define MAL0_CFG 0x180 -#define MAL0_ESR 0x181 -#define MAL0_IER 0x182 -#define MAL0_TXCASR 0x184 -#define MAL0_TXCARR 0x185 -#define MAL0_TXEOBISR 0x186 -#define MAL0_TXDEIR 0x187 -#define MAL0_RXCASR 0x190 -#define MAL0_RXCARR 0x191 -#define MAL0_RXEOBISR 0x192 -#define MAL0_RXDEIR 0x193 -#define MAL0_TXCTP0R 0x1A0 -#define MAL0_TXCTP1R 0x1A1 -#define MAL0_RXCTP0R 0x1C0 -#define MAL0_RXCTP1R 0x1C1 -#define MAL0_RCBS0 0x1E0 -#define MAL0_RCBS1 0x1E1 - -/* Memory-mapped registers */ - -typedef struct EthernetRegisters_GP { - uint32_t mode0; - uint32_t mode1; - uint32_t xmtMode0; - uint32_t xmtMode1; - uint32_t rcvMode; - uint32_t intStatus; - uint32_t intEnable; - uint32_t addrHi; - uint32_t addrLo; - uint32_t VLANTPID; - uint32_t VLANTCI; - uint32_t pauseTimer; - uint32_t g_indivHash[4]; /* EX non-IP multicast addr/mask */ - uint32_t g_groupHash[4]; - uint32_t lastSrcLo; - uint32_t lastSrcHi; - uint32_t IPGap; - uint32_t STAcontrol; - uint32_t xmtReqThreshold; - uint32_t rcvWatermarks; - uint32_t bytesXmtd; - uint32_t bytesRcvd; - uint32_t e_unused2; - uint32_t e_revID; - uint32_t e_unused3[2]; - uint32_t e_indivHash[8]; - uint32_t e_groupHash[8]; - uint32_t e_xmtPause; -} EthernetRegisters_GP; - -typedef struct EthernetRegisters_GP EthernetRegisters_EX; - -enum { EMACAddress = 0xEF600800 }; -enum { EMAC0GPAddress = 0xEF600800 }; - -enum { - // Mode 0 bits - kEMACRxIdle = 0x80000000, - kEMACTxIdle = 0x40000000, - kEMACSoftRst = 0x20000000, - kEMACTxEnable = 0x10000000, - kEMACRxEnable = 0x08000000, - - // Mode 1 bits - kEMACFullDuplex = 0x80000000, - kEMACDoFlowControl = 0x10000000, - kEMACIgnoreSQE = 0x01000000, - kEMAC100MBbps = 0x00400000, - kEMAC4KRxFIFO = 0x00300000, - kEMAC2KTxFIFO = 0x00080000, - kEMACTx0Multi = 0x00008000, - kEMACTxDependent= 0x00014000, - kEMAC100Mbps = 0x00400000, - kgEMAC4KRxFIFO = 0x00300000, - kgEMAC2KTxFIFO = 0x00080000, - kgEMACTx0Multi = 0x00008000, - kgEMACTxDependent= 0x00014000, - - - // Tx mode bits - kEMACNewPacket0 = 0x80000000, - kEMACNewPacket1 = 0x40000000, - - // Receive mode bits - kEMACStripPadding = 0x80000000, - kEMACStripFCS = 0x40000000, - kEMACRcvRunts = 0x20000000, - kEMACRcvFCSErrs = 0x10000000, - kEMACRcvOversize = 0x08000000, - kEMACPromiscRcv = 0x01000000, - kEMACPromMultRcv = 0x00800000, - kEMACIndivRcv = 0x00400000, - kEMACHashRcv = 0x00200000, - kEMACBrcastRcv = 0x00100000, - kEMACMultcastRcv = 0x00080000, - keEMACNonIPMultcast = 0x00040000, - keEMACRxFIFOAFMax = 7, - - // EMAC_STACR bits - kgSTAComplete = 0x8000, - kSTAErr = 0x4000, - - // Interrupt status bits - kEMACIOverrun = 0x02000000, - kEMACIPause = 0x01000000, - kEMACIBadPkt = 0x00800000, - kEMACIRuntPkt = 0x00400000, - kEMACIShortEvt= 0x00200000, - kEMACIAlignErr= 0x00100000, - kEMACIBadFCS = 0x00080000, - kEMACIOverSize= 0x00040000, - kEMACILLCRange= 0x00020000, - kEMACISQEErr = 0x00000080, - kEMACITxErr = 0x00000040, - - // Buffer descriptor control bits - kMALTxReady = 0x8000, - kMALRxEmpty = 0x8000, - kMALWrap = 0x4000, - kMALContinuous = 0x2000, - kMALLast = 0x1000, - kMALRxFirst = 0x0800, - kMALInterrupt = 0x0400, - - kMALReset = 0x80000000, - kMALLowPriority = 0, - kMALMedLowPriority = 0x00400000, - kMALMedHiPriority = 0x00800000, - kMALHighPriority = 0x00C00000, - kMALLatency8 = 0x00040000, - kMALLockErr = 0x8000, - kMALCanBurst = 0x4000, - kMALLocksOPB = 0x80, - kMALLocksErrs = 0x2, - - // MAL channel masks - kMALChannel0 = 0x80000000, - kMALChannel1 = 0x40000000, - - // EMAC Tx descriptor bits sent - kEMACGenFCS = 0x200, - kEMACGenPad = 0x100, - kEMACInsSrcAddr = 0x080, - kEMACRepSrcAddr = 0x040, - kEMACInsVLAN = 0x020, - kEMACRepVLAN = 0x010, - - // EMAC TX descriptor bits returned - kEMACErrMask = 0x3FF, - kEMACFCSWrong = 0x200, - kEMACBadPrev = 0x100, - kEMACLostCarrier = 0x080, - kEMACDeferred = 0x040, - kEMACCollFail = 0x020, - kEMACLateColl = 0x010, - kEMACMultColl = 0x008, - kEMACOneColl = 0x004, - kEMACUnderrun = 0x002, - kEMACSQEFail = 0x001, - - // EMAC Rx descriptor bits returned - kEMACOverrun = 0x200, - kEMACPausePkt = 0x100, - kEMACBadPkt = 0x080, - kEMACRuntPkt = 0x040, - kEMACShortEvt = 0x020, - kEMACAlignErr = 0x010, - kEMACBadFCS = 0x008, - kEMACPktLong = 0x004, - kEMACPktOOR = 0x002, - kEMACPktIRL = 0x001 -}; - - diff --git a/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.h b/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.h deleted file mode 100644 index d2024c89d7..0000000000 --- a/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifdef ppc405 -#ifndef __tty_drv__ -#define __tty_drv__ - -/* functions */ -#ifdef __cplusplus -extern "C" { -#endif - - -/* ttyS1 entry points */ -rtems_device_driver tty0_initialize( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -rtems_device_driver tty0_open( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -rtems_device_driver tty0_control( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - - -/* tty1 & tty2 shared entry points */ -rtems_device_driver tty0_close( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - - -rtems_device_driver tty0_read( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -rtems_device_driver tty0_write( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - - -#define TTY0_DRIVER_TABLE_ENTRY \ - { tty0_initialize, tty0_open, tty0_close, \ - tty0_read, tty0_write, tty0_control } - - -#ifdef __cplusplus -} -#endif -/* end of include file */ - -#endif /* __tty_drv__ */ -#endif /* ppc405 */ diff --git a/c/src/lib/libcpu/powerpc/preinstall.am b/c/src/lib/libcpu/powerpc/preinstall.am deleted file mode 100644 index 178763b3ab..0000000000 --- a/c/src/lib/libcpu/powerpc/preinstall.am +++ /dev/null @@ -1,320 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE) - @: > $(PROJECT_INCLUDE)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/powerpc - @: > $(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/powerpc/cache.h: rtems/powerpc/cache.h $(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/powerpc/cache.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/powerpc/cache.h - -$(PROJECT_INCLUDE)/rtems/powerpc/debugmod.h: rtems/powerpc/debugmod.h $(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/powerpc/debugmod.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/powerpc/debugmod.h - -$(PROJECT_INCLUDE)/rtems/powerpc/powerpc.h: rtems/powerpc/powerpc.h $(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/powerpc/powerpc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/powerpc/powerpc.h - -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score - @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) - -$(PROJECT_INCLUDE)/libcpu/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu - @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - -$(PROJECT_INCLUDE)/libcpu/powerpc-utility.h: shared/include/powerpc-utility.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/powerpc-utility.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/powerpc-utility.h - -$(PROJECT_INCLUDE)/bsp/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp - @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) - -$(PROJECT_INCLUDE)/bsp/irq_supp.h: new-exceptions/bspsupport/irq_supp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h - -$(PROJECT_INCLUDE)/bsp/vectors.h: new-exceptions/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h - -$(PROJECT_INCLUDE)/mpc83xx/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/mpc83xx - @: > $(PROJECT_INCLUDE)/mpc83xx/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mpc83xx/$(dirstamp) - -$(PROJECT_INCLUDE)/mpc83xx/mpc83xx_i2cdrv.h: mpc83xx/i2c/mpc83xx_i2cdrv.h $(PROJECT_INCLUDE)/mpc83xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc83xx/mpc83xx_i2cdrv.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc83xx/mpc83xx_i2cdrv.h - -if !mpc5xx -endif -if shared -$(PROJECT_INCLUDE)/libcpu/io.h: shared/include/io.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/io.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/io.h - -$(PROJECT_INCLUDE)/libcpu/mmu.h: shared/include/mmu.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h - -$(PROJECT_INCLUDE)/libcpu/page.h: shared/include/page.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/page.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/page.h - -$(PROJECT_INCLUDE)/libcpu/byteorder.h: shared/include/byteorder.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/byteorder.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/byteorder.h - -$(PROJECT_INCLUDE)/libcpu/pgtable.h: shared/include/pgtable.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/pgtable.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/pgtable.h - -$(PROJECT_INCLUDE)/libcpu/cpuIdent.h: shared/include/cpuIdent.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cpuIdent.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cpuIdent.h - -$(PROJECT_INCLUDE)/libcpu/spr.h: shared/include/spr.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/spr.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/spr.h - -$(PROJECT_INCLUDE)/libcpu/stackTrace.h: shared/src/stackTrace.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/stackTrace.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/stackTrace.h -endif -if ppc4xx -if ppc405 -$(PROJECT_INCLUDE)/tty_drv.h: ppc403/tty_drv/tty_drv.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tty_drv.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/tty_drv.h -endif -endif # ppc4xx -if ppc405 -$(PROJECT_INCLUDE)/ppc4xx/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/ppc4xx - @: > $(PROJECT_INCLUDE)/ppc4xx/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/ppc4xx/$(dirstamp) - -$(PROJECT_INCLUDE)/ppc4xx/ppc405gp.h: ppc403/include/ppc405gp.h $(PROJECT_INCLUDE)/ppc4xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/ppc4xx/ppc405gp.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/ppc4xx/ppc405gp.h - -$(PROJECT_INCLUDE)/ppc4xx/ppc405ex.h: ppc403/include/ppc405ex.h $(PROJECT_INCLUDE)/ppc4xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/ppc4xx/ppc405ex.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/ppc4xx/ppc405ex.h -endif # ppc405 -if mpc5xx -$(PROJECT_INCLUDE)/mpc5xx/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/mpc5xx - @: > $(PROJECT_INCLUDE)/mpc5xx/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mpc5xx/$(dirstamp) - -$(PROJECT_INCLUDE)/mpc5xx.h: mpc5xx/include/mpc5xx.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc5xx.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc5xx.h - -$(PROJECT_INCLUDE)/mpc5xx/console.h: mpc5xx/include/console.h $(PROJECT_INCLUDE)/mpc5xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc5xx/console.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc5xx/console.h - -$(PROJECT_INCLUDE)/libcpu/raw_exception.h: mpc5xx/exceptions/raw_exception.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/raw_exception.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/raw_exception.h - -$(PROJECT_INCLUDE)/libcpu/irq.h: mpc5xx/irq/irq.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/irq.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/irq.h - -$(PROJECT_INCLUDE)/libcpu/vectors.h: mpc5xx/vectors/vectors.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/vectors.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/vectors.h -endif -if mpc505 -$(PROJECT_INCLUDE)/ictrl.h: mpc505/ictrl/ictrl.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/ictrl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/ictrl.h -endif -if mpc6xx -$(PROJECT_INCLUDE)/libcpu/bat.h: mpc6xx/mmu/bat.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/bat.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/bat.h - -$(PROJECT_INCLUDE)/libcpu/pte121.h: mpc6xx/mmu/pte121.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/pte121.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/pte121.h - -$(PROJECT_INCLUDE)/libcpu/c_clock.h: mpc6xx/clock/c_clock.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/c_clock.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/c_clock.h -endif -if e500_clock -$(PROJECT_INCLUDE)/libcpu/c_clock.h: mpc6xx/clock/c_clock.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/c_clock.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/c_clock.h -endif -if e500_mmu -$(PROJECT_INCLUDE)/libcpu/e500_mmu.h: e500/mmu/e500_mmu.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/e500_mmu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/e500_mmu.h -endif -if mpc8xx -$(PROJECT_INCLUDE)/mpc8xx/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/mpc8xx - @: > $(PROJECT_INCLUDE)/mpc8xx/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mpc8xx/$(dirstamp) - -$(PROJECT_INCLUDE)/mpc8xx.h: mpc8xx/include/mpc8xx.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc8xx.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc8xx.h - -$(PROJECT_INCLUDE)/mpc8xx/console.h: mpc8xx/include/console.h $(PROJECT_INCLUDE)/mpc8xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc8xx/console.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc8xx/console.h - -$(PROJECT_INCLUDE)/mpc8xx/cpm.h: mpc8xx/include/cpm.h $(PROJECT_INCLUDE)/mpc8xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc8xx/cpm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc8xx/cpm.h - -$(PROJECT_INCLUDE)/mpc8xx/mmu.h: mpc8xx/include/mmu.h $(PROJECT_INCLUDE)/mpc8xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc8xx/mmu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc8xx/mmu.h -endif -if mpc8260 -$(PROJECT_INCLUDE)/mpc8260/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/mpc8260 - @: > $(PROJECT_INCLUDE)/mpc8260/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mpc8260/$(dirstamp) - -$(PROJECT_INCLUDE)/mpc8260.h: mpc8260/include/mpc8260.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc8260.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc8260.h - -$(PROJECT_INCLUDE)/mpc8260/console.h: mpc8260/include/console.h $(PROJECT_INCLUDE)/mpc8260/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc8260/console.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc8260/console.h - -$(PROJECT_INCLUDE)/mpc8260/cpm.h: mpc8260/include/cpm.h $(PROJECT_INCLUDE)/mpc8260/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc8260/cpm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc8260/cpm.h - -$(PROJECT_INCLUDE)/mpc8260/mmu.h: mpc8260/include/mmu.h $(PROJECT_INCLUDE)/mpc8260/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc8260/mmu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc8260/mmu.h -endif -if mpc83xx -$(PROJECT_INCLUDE)/mpc83xx/mpc83xx.h: mpc83xx/include/mpc83xx.h $(PROJECT_INCLUDE)/mpc83xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc83xx/mpc83xx.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc83xx/mpc83xx.h - -$(PROJECT_INCLUDE)/bsp/tsec.h: mpc83xx/network/tsec.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tsec.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tsec.h - -$(PROJECT_INCLUDE)/mpc83xx/mpc83xx_spidrv.h: mpc83xx/spi/mpc83xx_spidrv.h $(PROJECT_INCLUDE)/mpc83xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc83xx/mpc83xx_spidrv.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc83xx/mpc83xx_spidrv.h - -$(PROJECT_INCLUDE)/mpc83xx/gtm.h: mpc83xx/include/gtm.h $(PROJECT_INCLUDE)/mpc83xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc83xx/gtm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc83xx/gtm.h -endif -if mpc55xx -$(PROJECT_INCLUDE)/mpc55xx/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/mpc55xx - @: > $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - -$(PROJECT_INCLUDE)/mpc55xx/regs.h: mpc55xx/include/regs.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/regs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/regs.h - -$(PROJECT_INCLUDE)/mpc55xx/reg-defs.h: mpc55xx/include/reg-defs.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/reg-defs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/reg-defs.h - -$(PROJECT_INCLUDE)/mpc55xx/dspi.h: mpc55xx/include/dspi.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/dspi.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/dspi.h - -$(PROJECT_INCLUDE)/mpc55xx/edma.h: mpc55xx/include/edma.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/edma.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/edma.h - -$(PROJECT_INCLUDE)/mpc55xx/emios.h: mpc55xx/include/emios.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/emios.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/emios.h - -$(PROJECT_INCLUDE)/mpc55xx/mpc55xx.h: mpc55xx/include/mpc55xx.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/mpc55xx.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/mpc55xx.h - -$(PROJECT_INCLUDE)/mpc55xx/siu.h: mpc55xx/include/siu.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/siu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/siu.h - -$(PROJECT_INCLUDE)/mpc55xx/watchdog.h: mpc55xx/include/watchdog.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/watchdog.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/watchdog.h - -$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc551x.h: mpc55xx/include/fsl-mpc551x.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc551x.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc551x.h - -$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc555x.h: mpc55xx/include/fsl-mpc555x.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc555x.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc555x.h - -$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc556x.h: mpc55xx/include/fsl-mpc556x.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc556x.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc556x.h - -$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc564xL.h: mpc55xx/include/fsl-mpc564xL.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc564xL.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc564xL.h - -$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc5668.h: mpc55xx/include/fsl-mpc5668.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc5668.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc5668.h - -$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc567x.h: mpc55xx/include/fsl-mpc567x.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc567x.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc567x.h - -$(PROJECT_INCLUDE)/mpc55xx/regs-edma.h: mpc55xx/include/regs-edma.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/regs-edma.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/regs-edma.h - -$(PROJECT_INCLUDE)/mpc55xx/regs-mmu.h: mpc55xx/include/regs-mmu.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/regs-mmu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/regs-mmu.h -endif -if qoriq -$(PROJECT_INCLUDE)/bsp/tsec.h: mpc83xx/network/tsec.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tsec.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tsec.h - -endif diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h deleted file mode 100644 index 1fdc75ae8b..0000000000 --- a/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef _RTEMS_POWERPC_CACHE_H -#define _RTEMS_POWERPC_CACHE_H - -#include <rtems/powerpc/powerpc.h> /* for PPC_D_CACHE */ - -#ifdef _OLD_EXCEPTIONS - -#if (PPC_D_CACHE != 0) -#define _CPU_Data_Cache_Block_Flush( _address ) \ - do { register void *__address = (_address); \ - register uint32_t _zero = 0; \ - __asm__ volatile ( "dcbf %0,%1" : \ - "=r" (_zero), "=r" (__address) : \ - "0" (_zero), "1" (__address) \ - ); \ - } while (0) -#else -#define _CPU_Data_Cache_Block_Flush( _address ) /* nop */ -#endif - -/* - * FIXME: This is not used anywhere. - */ -#if (PPC_D_CACHE != 0) -#define _CPU_Data_Cache_Block_Invalidate( _address ) \ - do { register void *__address = (_address); \ - register uint32_t _zero = 0; \ - __asm__ volatile ( "dcbi %0,%1" : \ - "=r" (_zero), "=r" (__address) : \ - "0" (_zero), "1" (__address) \ - ); \ - } while (0) -#else -#define _CPU_Data_Cache_Block_Invalidate( _address ) /* nop */ -#endif -#endif - -#endif diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h deleted file mode 100644 index 61b650695c..0000000000 --- a/c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h +++ /dev/null @@ -1,124 +0,0 @@ -/* debugmod.h - * - * This file contains definitions for the IBM/Motorola PowerPC - * family members. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * MPC860 support code was added by Jay Monkman <jmonkman@frasca.com> - * MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk> - * Surrey Satellite Technology Limited - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * - * Note: - * This file is included by both C and assembler code ( -DASM ) - */ - -/* - * FIXME: This file is not used anywhere inside of RTEMS source-tree. - * Notify OAR if you actually use it, otherwise it might be removed in - * future versions of RTEMS - */ - -#ifndef _RTEMS_POWERPC_DEBUGMOD_H -#define _RTEMS_POWERPC_DEBUGMOD_H - -#warning "please read the FIXME inside of this file" - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the PowerPC family. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - * - * The following architectural feature definitions are defaulted - * unless specifically set by the model definition: - * - * + PPC_DEBUG_MODEL - PPC_DEBUG_MODEL_STANDARD - */ - -/* - * Define the debugging assistance models found in the PPC family. - * - * Standard: single step and branch trace - * Single Step Only: single step only - * IBM 4xx: debug exception - */ - -#define PPC_DEBUG_MODEL_STANDARD 1 -#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2 -#define PPC_DEBUG_MODEL_IBM4xx 3 - -#elif defined(ppc403) || defined(ppc405) || defined(ppc440) - -#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_IBM4xx - -#elif defined(ppc601) - -#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY - -#endif - -/* - * Use the default debug scheme defined in the architectural specification - * if another model has not been specified. - */ - -#ifndef PPC_DEBUG_MODEL -#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD -#endif - -/* - * Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming - * Environments" and the manuals for various PPC models. - */ - -#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD) -#define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */ -#define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */ -#define PPC_MSR_SE 0x000000400 /* bit 21 - single step trace enable */ -#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY) -#define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */ -#define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */ -#define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */ -#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx) -#define PPC_MSR_DE 0x000000200 /* bit 22 - debug exception enable */ -#define PPC_MSR_BE 0x000000000 /* bit 22 - branch trace enable */ -#define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */ -#else -#error "MSR constants -- unknown PPC_DEBUG_MODEL!!" -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_POWERPC_DEBUGMOD_H */ -/* end of include file */ diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h deleted file mode 100644 index 8b2cf1e371..0000000000 --- a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h +++ /dev/null @@ -1,644 +0,0 @@ -/** - * @file rtems/powerpc/powerpc.h - */ - -/* - * This file contains definitions for the IBM/Motorola PowerPC - * family members. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * MPC860 support code was added by Jay Monkman <jmonkman@frasca.com> - * MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk> - * Surrey Satellite Technology Limited - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * - * Note: - * This file is included by both C and assembler code ( -DASM ) - */ - - -#ifndef _RTEMS_POWERPC_POWERPC_H -#define _RTEMS_POWERPC_POWERPC_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Till S. 2008/07/10: - * - * Using the macros/definitions which depend on a preprocessor - * symbol defining the CPU flavor is discouraged. - * I recommend to not use definitions from this file and - * in particular - not to add more bits and pieces. - * - * Instead, try to use run-time detection (see e.g. cpuIdent.c/cpuIdent.h) - * of features etc. - */ - -#include <rtems/score/powerpc.h> - -/* - * Unfortunately it is very inefficient to use run-time detection for the cache - * line size, so give the BSP the opportunity to define it here. - */ -#include <bspopts.h> - -/* - * This file contains the information required to build - * RTEMS for a particular member of the PowerPC family. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - * - * The following architectural feature definitions are defaulted - * unless specifically set by the model definition: - * - * + PPC_INTERRUPT_MAX - 16 - * + PPC_CACHE_ALIGNMENT - * + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE - * + PPC_HAS_EXCEPTION_PREFIX - 1 - * + PPC_USE_MULTIPLE - 0 - */ - -/* - * Define the low power mode models - * - * Standard: as defined for 603e - * Nap Mode: nap mode only (604) - * XXX 403GB, 603, 603e, 604, 821 - */ - -#define PPC_LOW_POWER_MODE_NONE 0 -#define PPC_LOW_POWER_MODE_STANDARD 1 - -/** - * @brief For boards with no cache set PPC_CACHE_ALIGNMENT to this value. - */ -#define PPC_NO_CACHE_ALIGNMENT 4 - -/** - * @brief Used to define PPC_CACHE_ALIGN_POWER for boards with no cache (and - * PPC_NO_CACHE_ALIGNMENT defined). - */ -#define PPC_NO_CACHE_ALIGNMENT_POWER 2 - -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#if defined(ppc403) -/* - * IBM 403 - * - * Developed for 403GA. Book checked for 403GB. - * - * Does not have user mode. - */ - -#define PPC_CACHE_ALIGNMENT 16 -#define PPC_HAS_RI 0 -#define PPC_HAS_RFCI 1 -#define PPC_USE_MULTIPLE 1 -#define PPC_I_CACHE 2048 -#define PPC_D_CACHE 1024 - -#define PPC_HAS_EXCEPTION_PREFIX 0 -#define PPC_HAS_EVPR 1 - -#elif defined (ppc405) - -#define PPC_CACHE_ALIGNMENT 32 -#define PPC_HAS_RI 0 -#define PPC_HAS_RFCI 1 -#define PPC_USE_MULTIPLE 1 -#define PPC_I_CACHE 16384 -#define PPC_D_CACHE 16384 /* except GP/CR */ -#define PPC_HAS_EXCEPTION_PREFIX 0 -#define PPC_HAS_EVPR 1 - -#elif defined (ppc440) - -#define PPC_CACHE_ALIGNMENT 32 -#define PPC_HAS_RI 0 -#define PPC_HAS_RFCI 1 -#define PPC_USE_MULTIPLE 1 -#define PPC_I_CACHE 32768 -#define PPC_D_CACHE 32768 -#define PPC_HAS_EXCEPTION_PREFIX 0 -#define PPC_HAS_EVPR 1 - -#elif defined(mpc555) - -/* Copied from mpc505 */ -#define PPC_CACHE_ALIGNMENT PPC_NO_CACHE_ALIGNMENT - -/* Added by querbach@realtime.bc.ca */ -#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD - -/* Based on comments by Sergei Organov <osv@Javad.RU> */ -#define PPC_I_CACHE 0 -#define PPC_D_CACHE 0 - -#elif defined(mpc505) || defined(mpc509) -/* - * Submitted by Sergei Organov <osv@Javad.RU> as a patch against - * 3.6.0 long after 4.0 was released. This is just an attempt - * to get the setting correct. - */ - -#define CPU_MODEL_NAME "PowerPC 505/509" - -#define PPC_CACHE_ALIGNMENT PPC_NO_CACHE_ALIGNMENT -#define PPC_I_CACHE 4096 -#define PPC_D_CACHE 0 - - -#elif defined(ppc601) - -/* - * Submitted with original port -- book checked only. - */ - -#define PPC_USE_MULTIPLE 1 -#define PPC_I_CACHE 0 -#define PPC_D_CACHE 32768 - -#elif defined(ppc603) -/* - * Submitted with original port -- book checked only. - */ - -#define PPC_I_CACHE 8192 -#define PPC_D_CACHE 8192 - -#elif defined(ppc603e) - -/* - * Submitted with original port. - * - * Known to work on real hardware. - */ - -#define PPC_I_CACHE 16384 -#define PPC_D_CACHE 16384 - -#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD - -#elif defined(mpc604) -/* - * Submitted with original port -- book checked only. - */ - -#define PPC_I_CACHE 16384 -#define PPC_D_CACHE 16384 - -#elif defined(mpc860) -/* - * Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 - * with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca) - */ -#define PPC_I_CACHE 4096 -#define PPC_D_CACHE 4096 -#define PPC_CACHE_ALIGNMENT 16 -#define PPC_INTERRUPT_MAX 71 -#define PPC_USE_MULTIPLE 1 - -#define PPC_MSR_0 0x00009000 -#define PPC_MSR_1 0x00001000 -#define PPC_MSR_2 0x00001000 -#define PPC_MSR_3 0x00000000 - -#elif defined(mpc821) -/* - * Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999 - */ -#define PPC_I_CACHE 4096 -#define PPC_D_CACHE 4096 -#define PPC_CACHE_ALIGNMENT 16 -#define PPC_INTERRUPT_MAX 71 - -#define PPC_MSR_0 0x00009000 -#define PPC_MSR_1 0x00001000 -#define PPC_MSR_2 0x00001000 -#define PPC_MSR_3 0x00000000 - -#elif defined(mpc750) - -#define PPC_I_CACHE 16384 -#define PPC_D_CACHE 16384 - -#elif defined(mpc7400) - -#define PPC_I_CACHE 32768 -#define PPC_D_CACHE 32768 - -#elif defined(mpc7455) -/* - * Added by S.K. Feng <feng1@bnl.gov> 10/03 - */ - -#define PPC_CACHE_ALIGNMENT 32 -#define PPC_I_CACHE 32768 -#define PPC_D_CACHE 32768 - -#elif defined(mpc8260) -/* - * Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000 - */ -#define PPC_I_CACHE 16384 -#define PPC_D_CACHE 16384 -#define PPC_CACHE_ALIGNMENT 32 -#define PPC_INTERRUPT_MAX 125 -#define PPC_USE_MULTIPLE 1 - -#elif defined(__ppc_generic) - -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * If the maximum number of exception sources has not been defined, - * then default it to 16. - */ - -#ifndef PPC_INTERRUPT_MAX -#define PPC_INTERRUPT_MAX 16 -#endif - -#ifndef PPC_CACHE_ALIGNMENT -#define PPC_CACHE_ALIGNMENT PPC_DEFAULT_CACHE_LINE_SIZE -#endif - -#if (PPC_CACHE_ALIGNMENT == 16) -#define PPC_CACHE_ALIGN_POWER 4 -#elif (PPC_CACHE_ALIGNMENT == 32) -#define PPC_CACHE_ALIGN_POWER 5 -#elif (PPC_CACHE_ALIGNMENT == 64) -#define PPC_CACHE_ALIGN_POWER 6 -#elif (PPC_CACHE_ALIGNMENT == PPC_NO_CACHE_ALIGNMENT) -#define PPC_CACHE_ALIGN_POWER PPC_NO_CACHE_ALIGNMENT_POWER -#else -#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT" -#endif - -/* - * Unless otherwise specified, assume the model has an IP/EP bit to - * set the exception address prefix. - */ - -#ifndef PPC_HAS_EXCEPTION_PREFIX -#define PPC_HAS_EXCEPTION_PREFIX 1 -#endif -/* - * Unless otherwise specified, assume the model has an RI bit to - * identify non-recoverable interrupts - */ - -#ifndef PPC_HAS_RI -#define PPC_HAS_RI 1 -#endif - -/* - * Unless otherwise specified, assume the model does NOT have - * 403 style EVPR register to set the exception address prefix. - */ - -#ifndef PPC_HAS_EVPR -#define PPC_HAS_EVPR 0 -#endif - -/* - * If no low power mode model was specified, then assume there is none. - */ - -#ifndef PPC_LOW_POWER_MODE -#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE -#endif - -/* - * Unless specified above, then assume the model does NOT have critical - * interrupt support. - */ - -#ifndef PPC_HAS_RFCI -#define PPC_HAS_RFCI 0 -#endif - -/* - * Unless specified above, do not use the load/store multiple instructions - * in a context switch. - */ - -#ifndef PPC_USE_MULTIPLE -#define PPC_USE_MULTIPLE 0 -#endif - -/* - * The following exceptions are not maskable, and are not - * necessarily predictable, so cannot be offered to RTEMS: - * Alignment exception - handled by the CPU module - * Data exceptions. - * Instruction exceptions. - */ - -/* - * Base Interrupt vectors supported on all models. - */ -#define PPC_IRQ_SYSTEM_RESET 0 /* 0x00100 - System reset. */ -#define PPC_IRQ_MCHECK 1 /* 0x00200 - Machine check */ -#define PPC_IRQ_PROTECT 2 /* 0x00300 - Protection violation */ -#define PPC_IRQ_ISI 3 /* 0x00400 - Instruction Fetch error */ -#define PPC_IRQ_EXTERNAL 4 /* 0x00500 - External interrupt */ -#define PPC_IRQ_ALIGNMENT 5 /* 0X00600 - Alignment exception */ -#define PPC_IRQ_PROGRAM 6 /* 0x00700 - Program exception */ -#define PPC_IRQ_NOFP 7 /* 0x00800 - Floating point unavailable */ -#define PPC_IRQ_DECREMENTER 8 /* 0x00900 - Decrementer interrupt */ -#define PPC_IRQ_RESERVED_A 9 /* 0x00a00 - Implementation Reserved */ -#define PPC_IRQ_RESERVED_B 10 /* 0x00b00 - Implementation Reserved */ -#define PPC_IRQ_SCALL 11 /* 0x00c00 - System call */ -#define PPC_IRQ_TRACE 12 /* 0x00d00 - Trace Exception */ -#define PPC_IRQ_FP_ASST 13 /* ox00e00 - Floating point assist */ -#define PPC_STD_IRQ_LAST PPC_IRQ_FP_ASST - -#define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET - -#if defined(ppc403) || defined(ppc405) || defined(ppc440) - -#define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ -#define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ -#define PPC_IRQ_FIT (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer */ -#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer */ -#define PPC_IRQ_DEBUG (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions */ -#define PPC_IRQ_LAST PPC_IRQ_DEBUG - -#elif defined(mpc505) || defined(mpc509) -#define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */ -#define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+ 2) -#define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+ 3) -#define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+ 4) -#define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+ 5) - -#elif defined(mpc555) -#define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */ -#define PPC_IRQ_INST_PE (PPC_STD_IRQ_LAST+2) /* Insn protection error */ -#define PPC_IRQ_DATA_PE (PPC_STD_IRQ_LAST+3) /* Data protection error */ -#define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+4) /* Data breakpoint */ -#define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+5) /* Insn breakpoint */ -#define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+6) /* Maskable ext bkpt */ -#define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+7) /* Non-maskable ext bkpt */ -#define PPC_IRQ_LAST PPC_IRQ_NMEXT_BP - -#elif defined(ppc601) -#undef PPC_IRQ_TRACE -#define PPC_IRQ_TRACE (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/ -#define PPC_IRQ_LAST PPC_IRQ_TRACE - -#elif defined(ppc602) -#define PPC_IRQ_LAST (PPC_STD_IRQ_LAST) - -#elif defined(ppc603) || defined(ppc603e) -#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/ -#define PPC_IRQ_DATA_LOAD (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/ -#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss */ -#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */ -#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ -#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT - -#elif defined(mpc604) -#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break */ -#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */ -#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT - -#elif defined(mpc860) || defined(mpc821) -#define PPC_IRQ_EMULATE (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation */ -#define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/ -#define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */ -#define PPC_IRQ_INST_ERR (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */ -#define PPC_IRQ_DATA_ERR (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */ -#define PPC_IRQ_DATA_BPNT (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */ -#define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */ -#define PPC_IRQ_IO_BPNT (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */ -#define PPC_IRQ_DEV_PORT (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */ -#define PPC_IRQ_IRQ0 (PPC_STD_IRQ_LAST + 10) -#define PPC_IRQ_LVL0 (PPC_STD_IRQ_LAST + 11) -#define PPC_IRQ_IRQ1 (PPC_STD_IRQ_LAST + 12) -#define PPC_IRQ_LVL1 (PPC_STD_IRQ_LAST + 13) -#define PPC_IRQ_IRQ2 (PPC_STD_IRQ_LAST + 14) -#define PPC_IRQ_LVL2 (PPC_STD_IRQ_LAST + 15) -#define PPC_IRQ_IRQ3 (PPC_STD_IRQ_LAST + 16) -#define PPC_IRQ_LVL3 (PPC_STD_IRQ_LAST + 17) -#define PPC_IRQ_IRQ4 (PPC_STD_IRQ_LAST + 18) -#define PPC_IRQ_LVL4 (PPC_STD_IRQ_LAST + 19) -#define PPC_IRQ_IRQ5 (PPC_STD_IRQ_LAST + 20) -#define PPC_IRQ_LVL5 (PPC_STD_IRQ_LAST + 21) -#define PPC_IRQ_IRQ6 (PPC_STD_IRQ_LAST + 22) -#define PPC_IRQ_LVL6 (PPC_STD_IRQ_LAST + 23) -#define PPC_IRQ_IRQ7 (PPC_STD_IRQ_LAST + 24) -#define PPC_IRQ_LVL7 (PPC_STD_IRQ_LAST + 25) -#define PPC_IRQ_CPM_ERROR (PPC_STD_IRQ_LAST + 26) -#define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 27) -#define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 28) -#define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 29) -#define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 30) -#define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 31) -#define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 32) -#define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 33) -#define PPC_IRQ_CPM_RESERVED_8 (PPC_STD_IRQ_LAST + 34) -#define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 35) -#define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 36) -#define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 37) -#define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 38) -#define PPC_IRQ_CPM_RESERVED_D (PPC_STD_IRQ_LAST + 39) -#define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 40) -#define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 41) -#define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 42) -#define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 43) -#define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 44) -#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45) -#define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 46) -#define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 47) -#define PPC_IRQ_CPM_SDMA_ERROR (PPC_STD_IRQ_LAST + 48) -#define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 49) -#define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 50) -#define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 51) -#define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 52) -#define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 53) -#define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 54) -#define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 55) -#define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 56) -#define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 57) - -#define PPC_IRQ_LAST PPC_IRQ_CPM_PC15 - -#elif defined(mpc8260) - -#define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/ -#define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */ -#define PPC_IRQ_DATA_L_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */ -#define PPC_IRQ_DATA_S_MISS (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */ -#define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */ -#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */ -/* 0x1600 - 0x2F00 reserved */ -#define PPC_IRQ_CPM_NONE (PPC_STD_IRQ_LAST + 50) -#define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 51) -#define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 52) -#define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 53) -#define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 54) -#define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 55) -#define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 56) -#define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 57) -#define PPC_IRQ_CPM_IDMA3 (PPC_STD_IRQ_LAST + 58) -#define PPC_IRQ_CPM_IDMA4 (PPC_STD_IRQ_LAST + 59) -#define PPC_IRQ_CPM_SDMA (PPC_STD_IRQ_LAST + 60) -#define PPC_IRQ_CPM_RES_A (PPC_STD_IRQ_LAST + 61) -#define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 62) -#define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 63) -#define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 64) -#define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 65) -#define PPC_IRQ_CPM_TMCNT (PPC_STD_IRQ_LAST + 66) -#define PPC_IRQ_CPM_PIT (PPC_STD_IRQ_LAST + 67) -#define PPC_IRQ_CPM_RES_B (PPC_STD_IRQ_LAST + 68) -#define PPC_IRQ_CPM_IRQ1 (PPC_STD_IRQ_LAST + 69) -#define PPC_IRQ_CPM_IRQ2 (PPC_STD_IRQ_LAST + 70) -#define PPC_IRQ_CPM_IRQ3 (PPC_STD_IRQ_LAST + 71) -#define PPC_IRQ_CPM_IRQ4 (PPC_STD_IRQ_LAST + 72) -#define PPC_IRQ_CPM_IRQ5 (PPC_STD_IRQ_LAST + 73) -#define PPC_IRQ_CPM_IRQ6 (PPC_STD_IRQ_LAST + 74) -#define PPC_IRQ_CPM_IRQ7 (PPC_STD_IRQ_LAST + 75) -#define PPC_IRQ_CPM_RES_C (PPC_STD_IRQ_LAST + 76) -#define PPC_IRQ_CPM_RES_D (PPC_STD_IRQ_LAST + 77) -#define PPC_IRQ_CPM_RES_E (PPC_STD_IRQ_LAST + 78) -#define PPC_IRQ_CPM_RES_F (PPC_STD_IRQ_LAST + 79) -#define PPC_IRQ_CPM_RES_G (PPC_STD_IRQ_LAST + 80) -#define PPC_IRQ_CPM_RES_H (PPC_STD_IRQ_LAST + 81) -#define PPC_IRQ_CPM_FCC1 (PPC_STD_IRQ_LAST + 82) -#define PPC_IRQ_CPM_FCC2 (PPC_STD_IRQ_LAST + 83) -#define PPC_IRQ_CPM_FCC3 (PPC_STD_IRQ_LAST + 84) -#define PPC_IRQ_CPM_RES_I (PPC_STD_IRQ_LAST + 85) -#define PPC_IRQ_CPM_MCC1 (PPC_STD_IRQ_LAST + 86) -#define PPC_IRQ_CPM_MCC2 (PPC_STD_IRQ_LAST + 87) -#define PPC_IRQ_CPM_RES_J (PPC_STD_IRQ_LAST + 88) -#define PPC_IRQ_CPM_RES_K (PPC_STD_IRQ_LAST + 89) -#define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 90) -#define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 91) -#define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 92) -#define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 93) -#define PPC_IRQ_CPM_RES_L (PPC_STD_IRQ_LAST + 94) -#define PPC_IRQ_CPM_RES_M (PPC_STD_IRQ_LAST + 95) -#define PPC_IRQ_CPM_RES_N (PPC_STD_IRQ_LAST + 96) -#define PPC_IRQ_CPM_RES_O (PPC_STD_IRQ_LAST + 97) -#define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 98) -#define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 99) -#define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 100) -#define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 101) -#define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 102) -#define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 103) -#define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 104) -#define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 105) -#define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 106) -#define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 107) -#define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 108) -#define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 109) -#define PPC_IRQ_CPM_PC3 (PPC_STD_IRQ_LAST + 110) -#define PPC_IRQ_CPM_PC2 (PPC_STD_IRQ_LAST + 111) -#define PPC_IRQ_CPM_PC1 (PPC_STD_IRQ_LAST + 112) -#define PPC_IRQ_CPM_PC0 (PPC_STD_IRQ_LAST + 113) - -#define PPC_IRQ_LAST PPC_IRQ_CPM_PC0 - -#endif - - -/* - * If the maximum number of exception sources is too low, - * then fix it - */ - -#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST -#undef PPC_INTERRUPT_MAX -#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1) -#endif - -/* - * Machine Status Register (MSR) Constants Used by RTEMS - */ - -#if PPC_HAS_RI -#define PPC_MSR_RI 0x000000002 /* bit 30 - recoverable exception */ -#endif - -#define PPC_MSR_DR 0x000000010 /* bit 27 - data address translation */ -#define PPC_MSR_IR 0x000000020 /* bit 26 - instruction addr translation*/ - -/* - * Some PPC model manuals refer to the Exception Prefix (EP) bit as - * IP for no apparent reason. - */ -#if (PPC_HAS_EXCEPTION_PREFIX) -#define PPC_MSR_EP 0x000000040 /* bit 25 - exception prefix */ -#else -#define PPC_MSR_EP 0x000000000 /* bit 25 - exception prefix */ -#endif - -#if (PPC_HAS_FPU) -#define PPC_MSR_FP 0x000002000 /* bit 18 - floating point enable */ -#else -#define PPC_MSR_FP 0x000000000 /* bit 18 - floating point enable */ -#endif - -#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE) -#define PPC_MSR_POW 0x000000000 /* bit 13 - power management enable */ -#else -#define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */ -#endif - -#define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */ -#define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */ - -#if (PPC_HAS_RFCI) -#define PPC_MSR_CE 0x000020000 /* bit 14 - critical interrupt enable */ -#else -#define PPC_MSR_CE 0x000000000 /* bit 14 - critical interrupt enable */ -#endif - -#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE) - -#if defined(__powerpc64__) -#define PPC_MINIMUM_STACK_FRAME_SIZE 32 -#else -#define PPC_MINIMUM_STACK_FRAME_SIZE PPC_STACK_ALIGNMENT -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_POWERPC_POWERPC_H */ diff --git a/c/src/lib/libcpu/powerpc/shared/include/byteorder.h b/c/src/lib/libcpu/powerpc/shared/include/byteorder.h deleted file mode 100644 index 0654fefb58..0000000000 --- a/c/src/lib/libcpu/powerpc/shared/include/byteorder.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * byteorder.h - * - * This file contains inline implementation of function to - * deal with endian conversion. - * - * It is a stripped down version of linux ppc file... - * - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_BYTEORDER_H -#define _LIBCPU_BYTEORDER_H - -#ifdef __cplusplus -extern "C" { -#endif - -static inline unsigned ld_le16(volatile uint16_t *addr) -{ - unsigned val; - - __asm__ volatile ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); - return val; -} - -static inline void st_le16(volatile uint16_t *addr, unsigned val) -{ - __asm__ volatile ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); -} - -static inline unsigned ld_le32(volatile uint32_t *addr) -{ - unsigned val; - - __asm__ volatile ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); - return val; -} - -static inline void st_le32(volatile uint32_t *addr, unsigned val) -{ - __asm__ volatile ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _LIBCPU_BYTEORDER_H */ diff --git a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h deleted file mode 100755 index e051deba92..0000000000 --- a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk> - * Surrey Satellite Technology Limited - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_CPUIDENT_H -#define _LIBCPU_CPUIDENT_H - -#include <stdbool.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef ASM -typedef enum -{ - PPC_601 = 0x1, - PPC_5XX = 0x2, - PPC_603 = 0x3, - PPC_604 = 0x4, - PPC_603e = 0x6, - PPC_603ev = 0x7, - PPC_750 = 0x8, - PPC_750_IBM = 0x7000, - PPC_604e = 0x9, - PPC_604r = 0xA, - PPC_7400 = 0xC, - PPC_405 = 0x2001, /* Xilinx Virtex-II Pro or -4 */ - PPC_405EX = 0x1291, /* + 405EXr */ - PPC_405GP = 0x4011, /* + 405CR */ - PPC_405GPr = 0x5091, - PPC_405EZ = 0x4151, - PPC_405EP = 0x5121, - PPC_440 = 0x7ff2, /* Xilinx Virtex-5*/ - PPC_7455 = 0x8001, /* Kate Feng */ - PPC_7457 = 0x8002, - PPC_620 = 0x16, - PPC_860 = 0x50, - PPC_821 = PPC_860, - PPC_823 = PPC_860, - PPC_8260 = 0x81, - PPC_8240 = PPC_8260, - PPC_8245 = 0x8081, - PPC_8540 = 0x8020, - PPC_e500v2 = 0x8021, - PPC_e6500 = 0x8040, - PPC_603le = 0x8082, /* 603le core, in MGT5100 and MPC5200 */ - PPC_e300c1 = 0x8083, /* e300c1 core, in MPC83xx*/ - PPC_e300c2 = 0x8084, /* e300c2 core */ - PPC_e300c3 = 0x8085, /* e300c3 core */ - PPC_e200z0 = 0x8170, - PPC_e200z1 = 0x8140, - PPC_e200z4 = 0x8150, - PPC_e200z6 = 0x8110, - PPC_e200z7 = 0x8160, - PPC_PSIM = 0xfffe, /* GDB PowerPC simulator -- fake version */ - PPC_UNKNOWN = 0xffff -} ppc_cpu_id_t; - -/* Bitfield of for identifying features or groups of cpu flavors. - * DO NOT USE DIRECTLY (as implementation may change) - * only use the 'ppc_is_xxx() / ppc_has_xxx()' macros/inlines - * below. - */ - -typedef struct { - unsigned has_altivec : 1; - unsigned has_fpu : 1; - unsigned has_hw_ptbl_lkup : 1; -#define PPC_BOOKE_405 1 /* almost like booke but with some significant differences */ -#define PPC_BOOKE_STD 2 -#define PPC_BOOKE_E500 3 /* bookE with extensions */ - unsigned is_bookE : 2; - unsigned has_16byte_clne : 1; - unsigned is_60x : 1; - unsigned has_8_bats : 1; - unsigned has_epic : 1; - unsigned has_shadowed_gprs : 1; -} ppc_feature_t; - -extern ppc_feature_t current_ppc_features; -extern ppc_cpu_id_t current_ppc_cpu; - -typedef unsigned short ppc_cpu_revision_t; - -extern ppc_cpu_id_t get_ppc_cpu_type (void); -extern const char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu); -extern ppc_cpu_revision_t get_ppc_cpu_revision (void); -extern ppc_cpu_revision_t current_ppc_revision; - -/* PUBLIC ACCESS ROUTINES */ -#define _PPC_FEAT_DECL(x) \ -static inline unsigned ppc_cpu_##x(void) { \ - if ( PPC_UNKNOWN == current_ppc_cpu ) \ - get_ppc_cpu_type(); \ - return current_ppc_features.x; \ -} - -_PPC_FEAT_DECL(has_altivec) -/* has_fpu not implemented yet */ -_PPC_FEAT_DECL(has_hw_ptbl_lkup) -_PPC_FEAT_DECL(is_bookE) -_PPC_FEAT_DECL(is_60x) -_PPC_FEAT_DECL(has_8_bats) -_PPC_FEAT_DECL(has_epic) -_PPC_FEAT_DECL(has_shadowed_gprs) - -#undef _PPC_FEAT_DECL - -static inline ppc_cpu_id_t ppc_cpu_current(void) -{ - return current_ppc_cpu; -} - -static inline bool ppc_cpu_is_e200(void) -{ - return (ppc_cpu_current() & 0xff80) == 0x8100; -} - -static inline bool ppc_cpu_is_specific_e200(ppc_cpu_id_t id) -{ - return (ppc_cpu_current() & 0xfff0) == id; -} - -static inline bool ppc_cpu_is_e300(void) -{ - return ppc_cpu_current() == PPC_e300c1 - || ppc_cpu_current() == PPC_e300c2 - || ppc_cpu_current() == PPC_e300c3; -} - -static inline bool ppc_cpu_is_e500(void) -{ - return ppc_cpu_current() == PPC_8540 - || ppc_cpu_current() == PPC_e500v2; -} - -static inline bool ppc_cpu_is(ppc_cpu_id_t cpu) -{ - return ppc_cpu_current() == cpu; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libcpu/powerpc/shared/include/io.h b/c/src/lib/libcpu/powerpc/shared/include/io.h deleted file mode 100644 index 841df81f47..0000000000 --- a/c/src/lib/libcpu/powerpc/shared/include/io.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * io.h - * - * This file contains inline implementation of function to - * deal with IO. - * - * It is a stripped down version of linux ppc file... - * - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef _LIBCPU_IO_H -#define _LIBCPU_IO_H - - -#define PREP_ISA_IO_BASE 0x80000000 -#define PREP_ISA_MEM_BASE 0xc0000000 -#define PREP_PCI_DRAM_OFFSET 0x80000000 - -#define CHRP_ISA_IO_BASE 0xfe000000 -#define CHRP_ISA_MEM_BASE 0xfd000000 -#define CHRP_PCI_DRAM_OFFSET 0x00000000 - -/* _IO_BASE, _ISA_MEM_BASE, PCI_DRAM_OFFSET are now defined by bsp.h */ - -#ifndef ASM - -#include <bsp.h> /* for _IO_BASE & friends */ -#include <stdint.h> - -/* NOTE: The use of these macros is DISCOURAGED. - * you should consider e.g. using in_xxx / out_xxx - * with a device specific base address that is - * defined by the BSP. This makes drivers easier - * to port. - */ -#define inb(port) in_8((uint8_t *)((port)+_IO_BASE)) -#define outb(val, port) out_8((uint8_t *)((port)+_IO_BASE), (val)) -#define inw(port) in_le16((uint16_t *)((port)+_IO_BASE)) -#define outw(val, port) out_le16((uint16_t *)((port)+_IO_BASE), (val)) -#define inl(port) in_le32((uint32_t *)((port)+_IO_BASE)) -#define outl(val, port) out_le32((uint32_t *)((port)+_IO_BASE), (val)) - -/* - * Enforce In-order Execution of I/O: - * Acts as a barrier to ensure all previous I/O accesses have - * completed before any further ones are issued. - */ -static inline void eieio(void) -{ - __asm__ __volatile__ ("eieio"); -} - - -/* Enforce in-order execution of data I/O. - * No distinction between read/write on PPC; use eieio for all three. - */ -#define iobarrier_rw() eieio() -#define iobarrier_r() eieio() -#define iobarrier_w() eieio() - -/* - * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. - */ -static inline uint8_t in_8(const volatile uint8_t *addr) -{ - uint8_t ret; - - __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; -} - -static inline void out_8(volatile uint8_t *addr, uint8_t val) -{ - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} - -static inline uint16_t in_le16(const volatile uint16_t *addr) -{ - uint16_t ret; - - __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -static inline uint16_t in_be16(const volatile uint16_t *addr) -{ - uint16_t ret; - - __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; -} - -static inline void out_le16(volatile uint16_t *addr, uint16_t val) -{ - __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -static inline void out_be16(volatile uint16_t *addr, uint16_t val) -{ - __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} - -static inline uint32_t in_le32(const volatile uint32_t *addr) -{ - uint32_t ret; - - __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -static inline uint32_t in_be32(const volatile uint32_t *addr) -{ - uint32_t ret; - - __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; -} - -static inline void out_le32(volatile uint32_t *addr, uint32_t val) -{ - __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -static inline void out_be32(volatile uint32_t *addr, uint32_t val) -{ - __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} - -#endif /* ASM */ -#endif /* _LIBCPU_IO_H */ diff --git a/c/src/lib/libcpu/powerpc/shared/include/mmu.h b/c/src/lib/libcpu/powerpc/shared/include/mmu.h deleted file mode 100644 index d3081316eb..0000000000 --- a/c/src/lib/libcpu/powerpc/shared/include/mmu.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * mmu.h - * - * PowerPC memory management structures - * - * It is a stripped down version of linux ppc file... - * - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_MMU_H -#define _LIBCPU_MMU_H - -#ifndef ASM -/* Hardware Page Table Entry */ -typedef struct _PTE { - unsigned long v:1; /* Entry is valid */ - unsigned long vsid:24; /* Virtual segment identifier */ - unsigned long h:1; /* Hash algorithm indicator */ - unsigned long api:6; /* Abbreviated page index */ - unsigned long rpn:20; /* Real (physical) page number */ - unsigned long :3; /* Unused */ - unsigned long r:1; /* Referenced */ - unsigned long c:1; /* Changed */ - unsigned long w:1; /* Write-thru cache mode */ - unsigned long i:1; /* Cache inhibited */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page protection */ -} PTE; - -/* Values for PP (assumes Ks=0, Kp=1) */ -#define PP_RWXX 0 /* Supervisor read/write, User none */ -#define PP_RWRX 1 /* Supervisor read/write, User read */ -#define PP_RWRW 2 /* Supervisor read/write, User read/write */ -#define PP_RXRX 3 /* Supervisor read, User read */ - -/* Segment Register */ -typedef struct _SEGREG { - unsigned long t:1; /* Normal or I/O type */ - unsigned long ks:1; /* Supervisor 'key' (normally 0) */ - unsigned long kp:1; /* User 'key' (normally 1) */ - unsigned long n:1; /* No-execute */ - unsigned long :4; /* Unused */ - unsigned long vsid:24; /* Virtual Segment Identifier */ -} SEGREG; - -/* Block Address Translation (BAT) Registers */ -typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ - unsigned long bepi:15; /* Effective page index (virtual address) */ - unsigned long :8; /* unused */ - unsigned long w:1; - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long ks:1; /* Supervisor key (normally 0) */ - unsigned long kp:1; /* User key (normally 1) */ - unsigned long pp:2; /* Page access protections */ -} P601_BATU; - -typedef struct _BATU { /* Upper part of BAT (all except 601) */ - unsigned long bepi:15; /* Effective page index (virtual address) */ - unsigned long :4; /* Unused */ - unsigned long bl:11; /* Block size mask */ - unsigned long vs:1; /* Supervisor valid */ - unsigned long vp:1; /* User valid */ -} BATU; - -typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ - unsigned long brpn:15; /* Real page index (physical address) */ - unsigned long :10; /* Unused */ - unsigned long v:1; /* Valid bit */ - unsigned long bl:6; /* Block size mask */ -} P601_BATL; - -typedef struct _BATL { /* Lower part of BAT (all except 601) */ - unsigned long brpn:15; /* Real page index (physical address) */ - unsigned long :10; /* Unused */ - unsigned long w:1; /* Write-thru cache */ - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded (MBZ in IBAT) */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page access protections */ -} BATL; - -typedef struct _BAT { - BATU batu; /* Upper register */ - BATL batl; /* Lower register */ -} BAT; - -typedef struct _P601_BAT { - P601_BATU batu; /* Upper register */ - P601_BATL batl; /* Lower register */ -} P601_BAT; - -/* Block size masks */ -#define BL_128K 0x000 -#define BL_256K 0x001 -#define BL_512K 0x003 -#define BL_1M 0x007 -#define BL_2M 0x00F -#define BL_4M 0x01F -#define BL_8M 0x03F -#define BL_16M 0x07F -#define BL_32M 0x0FF -#define BL_64M 0x1FF -#define BL_128M 0x3FF -#define BL_256M 0x7FF - -/* BAT Access Protection */ -#define BPP_XX 0x00 /* No access */ -#define BPP_RX 0x01 /* Read only */ -#define BPP_RW 0x02 /* Read/write */ - -/* - * Simulated two-level MMU. This structure is used by the kernel - * to keep track of MMU mappings and is used to update/maintain - * the hardware HASH table which is really a cache of mappings. - * - * The simulated structures mimic the hardware available on other - * platforms, notably the 80x86 and 680x0. - */ - -typedef struct _pte { - unsigned long page_num:20; - unsigned long flags:12; /* Page flags (some unused bits) */ -} pte; - -#define PD_SHIFT (10+12) /* Page directory */ -#define PD_MASK 0x03FF -#define PT_SHIFT (12) /* Page Table */ -#define PT_MASK 0x03FF -#define PG_SHIFT (12) /* Page Entry */ - - -/* MMU context */ - -typedef struct _MMU_context { - SEGREG segs[16]; /* Segment registers */ - pte **pmap; /* Two-level page-map structure */ -} MMU_context; - -/* Used to set up SDR1 register */ -#define HASH_TABLE_SIZE_64K 0x00010000 -#define HASH_TABLE_SIZE_128K 0x00020000 -#define HASH_TABLE_SIZE_256K 0x00040000 -#define HASH_TABLE_SIZE_512K 0x00080000 -#define HASH_TABLE_SIZE_1M 0x00100000 -#define HASH_TABLE_SIZE_2M 0x00200000 -#define HASH_TABLE_SIZE_4M 0x00400000 -#define HASH_TABLE_MASK_64K 0x000 -#define HASH_TABLE_MASK_128K 0x001 -#define HASH_TABLE_MASK_256K 0x003 -#define HASH_TABLE_MASK_512K 0x007 -#define HASH_TABLE_MASK_1M 0x00F -#define HASH_TABLE_MASK_2M 0x01F -#define HASH_TABLE_MASK_4M 0x03F - -/* invalidate a TLB entry */ -static inline void _tlbie(unsigned long va) -{ - asm volatile ("tlbie %0" : : "r"(va)); -} - -extern void _tlbia(void); /* invalidate all TLB entries */ -#endif /* ASM */ - -/* Control/status registers for the MPC8xx. - * A write operation to these registers causes serialized access. - * During software tablewalk, the registers used perform mask/shift-add - * operations when written/read. A TLB entry is created when the Mx_RPN - * is written, and the contents of several registers are used to - * create the entry. - */ -#define MI_CTR 784 /* Instruction TLB control register */ -#define MI_GPM 0x80000000 /* Set domain manager mode */ -#define MI_PPM 0x40000000 /* Set subpage protection */ -#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MI_RESETVAL 0x00000000 /* Value of register at reset */ - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define MI_AP 786 -#define MI_Ks 0x80000000 /* Should not be set */ -#define MI_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MI_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define MI_EPN 787 -#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MI_EVALID 0x00000200 /* Entry is valid */ -#define MI_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the instruction TLB, it contains bits that get loaded into the - * TLB entry when the MI_RPN is written. - */ -#define MI_TWC 789 -#define MI_APG 0x000001e0 /* Access protection group (0) */ -#define MI_GUARDED 0x00000010 /* Guarded storage */ -#define MI_PSMASK 0x0000000c /* Mask of page size bits */ -#define MI_PS8MEG 0x0000000c /* 8M page size */ -#define MI_PS512K 0x00000004 /* 512K page size */ -#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MI_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the instruction TLB, using - * additional information from the MI_EPN, and MI_TWC registers. - */ -#define MI_RPN 790 - -/* Define an RPN value for mapping kernel memory to large virtual - * pages for boot initialization. This has real page number of 0, - * large page size, shared page, cache enabled, and valid. - * Also mark all subpages valid and write access. - */ -#define MI_BOOTINIT 0x000001fd - -#define MD_CTR 792 /* Data TLB control register */ -#define MD_GPM 0x80000000 /* Set domain manager mode */ -#define MD_PPM 0x40000000 /* Set subpage protection */ -#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ -#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ -#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MD_RESETVAL 0x04000000 /* Value of register at reset */ - -#define M_CASID 793 /* Address space ID (context) to match */ -#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ - - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define MD_AP 794 -#define MD_Ks 0x80000000 /* Should not be set */ -#define MD_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MD_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define MD_EPN 795 -#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MD_EVALID 0x00000200 /* Entry is valid */ -#define MD_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* The pointer to the base address of the first level page table. - * During a software tablewalk, reading this register provides the address - * of the entry associated with MD_EPN. - */ -#define M_TWB 796 -#define M_L1TB 0xfffff000 /* Level 1 table base address */ -#define M_L1INDX 0x00000ffc /* Level 1 index, when read */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the data TLB, it contains bits that get loaded into the TLB entry - * when the MD_RPN is written. It is also provides the hardware assist - * for finding the PTE address during software tablewalk. - */ -#define MD_TWC 797 -#define MD_L2TB 0xfffff000 /* Level 2 table base address */ -#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ -#define MD_APG 0x000001e0 /* Access protection group (0) */ -#define MD_GUARDED 0x00000010 /* Guarded storage */ -#define MD_PSMASK 0x0000000c /* Mask of page size bits */ -#define MD_PS8MEG 0x0000000c /* 8M page size */ -#define MD_PS512K 0x00000004 /* 512K page size */ -#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MD_WT 0x00000002 /* Use writethrough page attribute */ -#define MD_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the data TLB, using - * additional information from the MD_EPN, and MD_TWC registers. - */ -#define MD_RPN 798 - -/* This is a temporary storage register that could be used to save - * a processor working register during a tablewalk. - */ -#define M_TW 799 -#endif /* _LIBCPU_MMU_H */ diff --git a/c/src/lib/libcpu/powerpc/shared/include/page.h b/c/src/lib/libcpu/powerpc/shared/include/page.h deleted file mode 100644 index 3efbdef5bc..0000000000 --- a/c/src/lib/libcpu/powerpc/shared/include/page.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * page.h - * - * PowerPC memory management structures - * - * It is a stripped down version of linux ppc file... - * - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_PAGE_H -#define _LIBCPU_PAGE_H - -/* PAGE_SHIFT determines the page size */ -#define PAGE_SHIFT 12 -#define PAGE_SIZE (1UL << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#define PAGE_OFFSET 0xc0000000 - - -#ifndef ASM -/* - * .. while these make it easier on the compiler - */ -typedef unsigned long pte_t; -typedef unsigned long pmd_t; -typedef unsigned long pgd_t; -typedef unsigned long pgprot_t; - -#define pte_val(x) (x) -#define pmd_val(x) (x) -#define pgd_val(x) (x) -#define pgprot_val(x) (x) - -#define __pte(x) (x) -#define __pmd(x) (x) -#define __pgd(x) (x) -#define __pgprot(x) (x) - - -/* align addr on a size boundry - adjust address up if needed -- Cort */ -#define _ALIGN(addr,size) (((addr)+size-1)&(~(size-1))) - -/* to align the pointer to the (next) page boundary */ -#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) - - -#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) -#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) -/* map phys->virtual and virtual->phys for RAM pages */ - -#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET) -#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET)) - -#define MAP_NR(addr) (((unsigned long)addr-PAGE_OFFSET) >> PAGE_SHIFT) -#define MAP_PAGE_RESERVED (1<<15) - -extern unsigned long get_zero_page_fast(void); -#endif /* ASM */ -#endif /* _LIBCPU_PAGE_H */ diff --git a/c/src/lib/libcpu/powerpc/shared/include/pgtable.h b/c/src/lib/libcpu/powerpc/shared/include/pgtable.h deleted file mode 100644 index 5be5874b4f..0000000000 --- a/c/src/lib/libcpu/powerpc/shared/include/pgtable.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * pgtable.h - * - * PowerPC memory management structures - * - * It is a stripped down version of linux ppc file... - * - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_PGTABLE_H -#define _LIBCPU_PGTABLE_H - -/* - * The PowerPC MMU uses a hash table containing PTEs, together with - * a set of 16 segment registers (on 32-bit implementations), to define - * the virtual to physical address mapping. - * - * We use the hash table as an extended TLB, i.e. a cache of currently - * active mappings. We maintain a two-level page table tree, much like - * that used by the i386, for the sake of the Linux memory management code. - * Low-level assembler code in head.S (procedure hash_page) is responsible - * for extracting ptes from the tree and putting them into the hash table - * when necessary, and updating the accessed and modified bits in the - * page table tree. - * - * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk. - * We also use the two level tables, but we can put the real bits in them - * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0, - * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has - * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit - * based upon user/super access. The TLB does not have accessed nor write - * protect. We assume that if the TLB get loaded with an entry it is - * accessed, and overload the changed bit for write protect. We use - * two bits in the software pte that are supposed to be set to zero in - * the TLB entry (24 and 25) for these indicators. Although the level 1 - * descriptor contains the guarded and writethrough/copyback bits, we can - * set these at the page level since they get copied from the Mx_TWC - * register when the TLB entry is loaded. We will use bit 27 for guard, since - * that is where it exists in the MD_TWC, and bit 26 for writethrough. - * These will get masked from the level 2 descriptor at TLB load time, and - * copied to the MD_TWC before it gets loaded. - */ - -/* PMD_SHIFT determines the size of the area mapped by the second-level page tables */ -#define PMD_SHIFT 22 -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) - -/* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define PGDIR_SHIFT 22 -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) - -/* - * entries per page directory level: our page-table tree is two-level, so - * we don't really have any PMD directory. - */ -#define PTRS_PER_PTE 1024 -#define PTRS_PER_PMD 1 -#define PTRS_PER_PGD 1024 -#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) - -/* Just any arbitrary offset to the start of the vmalloc VM area: the - * current 64MB value just means that there will be a 64MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - * - * We no longer map larger than phys RAM with the BATs so we don't have - * to worry about the VMALLOC_OFFSET causing problems. We do have to worry - * about clashes between our early calls to ioremap() that start growing down - * from ioremap_base being run into the VM area allocations (growing upwards - * from VMALLOC_START). For this reason we have ioremap_bot to check when - * we actually run into our mappings setup in the early boot with the VM - * system. This really does become a problem for machines with good amounts - * of RAM. -- Cort - */ -#define VMALLOC_OFFSET (0x4000000) /* 64M */ -#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) -#define VMALLOC_END ioremap_bot - -/* - * Bits in a linux-style PTE. These match the bits in the - * (hardware-defined) PowerPC PTE as closely as possible. - */ -#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ -#define _PAGE_USER 0x002 /* matches one of the PP bits */ -#define _PAGE_RW 0x004 /* software: user write access allowed */ -#define _PAGE_GUARDED 0x008 -#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ -#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ -#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */ -#define _PAGE_DIRTY 0x080 /* C: page changed */ -#define _PAGE_ACCESSED 0x100 /* R: page referenced */ -#define _PAGE_HWWRITE 0x200 /* software: _PAGE_RW & _PAGE_DIRTY */ -#define _PAGE_SHARED 0 - -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) - -#define _PAGE_BASE _PAGE_PRESENT | _PAGE_ACCESSED -#define _PAGE_WRENABLE _PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE - -#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) - -#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | \ - _PAGE_SHARED) -#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) -#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) -#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED) -#define PAGE_KERNEL_CI __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | \ - _PAGE_NO_CACHE ) - -/* - * The PowerPC can only do execute protection on a segment (256MB) basis, - * not on a page basis. So we consider execute permission the same as read. - * Also, write permissions imply read permissions. - * This is the closest we can get.. - */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_READONLY -#define __P101 PAGE_READONLY -#define __P110 PAGE_COPY -#define __P111 PAGE_COPY - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY -#define __S101 PAGE_READONLY -#define __S110 PAGE_SHARED -#define __S111 PAGE_SHARED -#endif /* _LIBCPU_PGTABLE_H */ diff --git a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h b/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h deleted file mode 100644 index 4d6af38485..0000000000 --- a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h +++ /dev/null @@ -1,985 +0,0 @@ -/** - * @file - * - * @ingroup powerpc_shared - * - * @brief General purpose assembler macros, linker command file support and - * some inline functions for direct register access. - */ - -/* - * Copyright (c) 2008-2015 embedded brains GmbH. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * access function for Device Control Registers inspired by "ppc405common.h" - * from Michael Hamel ADInstruments May 2008 - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/** - * @defgroup powerpc_shared Shared PowerPC Code - */ - -#ifndef __LIBCPU_POWERPC_UTILITY_H -#define __LIBCPU_POWERPC_UTILITY_H - -#if !defined(ASM) - #include <rtems.h> -#endif - -#include <rtems/score/cpu.h> -#include <rtems/powerpc/registers.h> -#include <rtems/powerpc/powerpc.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(ASM) - -#include <rtems/bspIo.h> -#include <rtems/system.h> - -#include <libcpu/cpuIdent.h> - -#define LINKER_SYMBOL(sym) extern char sym []; - -/** - * @brief Read one byte from @a src. - */ -static inline uint8_t ppc_read_byte(const volatile void *src) -{ - uint8_t value; - - __asm__ volatile ( - "lbz %0, 0(%1)" - : "=r" (value) - : "b" (src) - ); - - return value; -} - -/** - * @brief Read one half word from @a src. - */ -static inline uint16_t ppc_read_half_word(const volatile void *src) -{ - uint16_t value; - - __asm__ volatile ( - "lhz %0, 0(%1)" - : "=r" (value) - : "b" (src) - ); - - return value; -} - -/** - * @brief Read one word from @a src. - */ -static inline uint32_t ppc_read_word(const volatile void *src) -{ - uint32_t value; - - __asm__ volatile ( - "lwz %0, 0(%1)" - : "=r" (value) - : "b" (src) - ); - - return value; -} - -/** - * @brief Write one byte @a value to @a dest. - */ -static inline void ppc_write_byte(uint8_t value, volatile void *dest) -{ - __asm__ volatile ( - "stb %0, 0(%1)" - : - : "r" (value), "b" (dest) - ); -} - -/** - * @brief Write one half word @a value to @a dest. - */ -static inline void ppc_write_half_word(uint16_t value, volatile void *dest) -{ - __asm__ volatile ( - "sth %0, 0(%1)" - : - : "r" (value), "b" (dest) - ); -} - -/** - * @brief Write one word @a value to @a dest. - */ -static inline void ppc_write_word(uint32_t value, volatile void *dest) -{ - __asm__ volatile ( - "stw %0, 0(%1)" : - : "r" (value), "b" (dest) - ); -} - - -static inline void *ppc_stack_pointer(void) -{ - void *sp; - - __asm__ volatile ( - "mr %0, 1" - : "=r" (sp) - ); - - return sp; -} - -static inline void ppc_set_stack_pointer(void *sp) -{ - __asm__ volatile ( - "mr 1, %0" - : - : "r" (sp) - ); -} - -static inline void *ppc_link_register(void) -{ - void *lr; - - __asm__ volatile ( - "mflr %0" - : "=r" (lr) - ); - - return lr; -} - -static inline void ppc_set_link_register(void *lr) -{ - __asm__ volatile ( - "mtlr %0" - : - : "r" (lr) - ); -} - -static inline uint32_t ppc_machine_state_register(void) -{ - uint32_t msr; - - __asm__ volatile ( - "mfmsr %0" - : "=r" (msr) - ); - - return msr; -} - -static inline void ppc_set_machine_state_register(uint32_t msr) -{ - __asm__ volatile ( - "mtmsr %0" - : - : "r" (msr) - ); -} - -static inline void ppc_synchronize_data(void) -{ - RTEMS_COMPILER_MEMORY_BARRIER(); - - __asm__ volatile ("sync"); -} - -static inline void ppc_light_weight_synchronize(void) -{ - RTEMS_COMPILER_MEMORY_BARRIER(); - - __asm__ volatile ("lwsync"); -} - -static inline void ppc_synchronize_instructions(void) -{ - RTEMS_COMPILER_MEMORY_BARRIER(); - - __asm__ volatile ("isync"); -} - -static inline void ppc_enforce_in_order_execution_of_io(void) -{ - RTEMS_COMPILER_MEMORY_BARRIER(); - - __asm__ volatile ("eieio"); -} - -static inline void ppc_data_cache_block_flush(void *addr) -{ - __asm__ volatile ( - "dcbf 0, %0" - : - : "r" (addr) - : "memory" - ); -} - -static inline void ppc_data_cache_block_flush_2( - void *base, - uintptr_t offset -) -{ - __asm__ volatile ( - "dcbf %0, %1" - : - : "b" (base), "r" (offset) - : "memory" - ); -} - -static inline void ppc_data_cache_block_invalidate(void *addr) -{ - __asm__ volatile ( - "dcbi 0, %0" - : - : "r" (addr) - : "memory" - ); -} - -static inline void ppc_data_cache_block_invalidate_2( - void *base, - uintptr_t offset -) -{ - __asm__ volatile ( - "dcbi %0, %1" - : - : "b" (base), "r" (offset) - : "memory" - ); -} - -static inline void ppc_data_cache_block_store(const void *addr) -{ - __asm__ volatile ( - "dcbst 0, %0" - : - : "r" (addr) - ); -} - -static inline void ppc_data_cache_block_store_2( - const void *base, - uintptr_t offset -) -{ - __asm__ volatile ( - "dcbst %0, %1" - : - : "b" (base), "r" (offset) - ); -} - -static inline void ppc_data_cache_block_touch(const void *addr) -{ - __asm__ volatile ( - "dcbt 0, %0" - : - : "r" (addr) - ); -} - -static inline void ppc_data_cache_block_touch_2( - const void *base, - uintptr_t offset -) -{ - __asm__ volatile ( - "dcbt %0, %1" - : - : "b" (base), "r" (offset) - ); -} - -static inline void ppc_data_cache_block_touch_for_store(const void *addr) -{ - __asm__ volatile ( - "dcbtst 0, %0" - : - : "r" (addr) - ); -} - -static inline void ppc_data_cache_block_touch_for_store_2( - const void *base, - uintptr_t offset -) -{ - __asm__ volatile ( - "dcbtst %0, %1" - : - : "b" (base), "r" (offset) - ); -} - -static inline void ppc_data_cache_block_clear_to_zero(void *addr) -{ - __asm__ volatile ( - "dcbz 0, %0" - : - : "r" (addr) - : "memory" - ); -} - -static inline void ppc_data_cache_block_clear_to_zero_2( - void *base, - uintptr_t offset -) -{ - __asm__ volatile ( - "dcbz %0, %1" - : - : "b" (base), "r" (offset) - : "memory" - ); -} - -static inline void ppc_instruction_cache_block_invalidate(void *addr) -{ - __asm__ volatile ( - "icbi 0, %0" - : - : "r" (addr) - ); -} - -static inline void ppc_instruction_cache_block_invalidate_2( - void *base, - uintptr_t offset -) -{ - __asm__ volatile ( - "icbi %0, %1" - : - : "b" (base), "r" (offset) - ); -} - -/** - * @brief Enables external exceptions. - * - * You can use this function to enable the external exceptions and restore the - * machine state with ppc_external_exceptions_disable() later. - */ -static inline uint32_t ppc_external_exceptions_enable(void) -{ - uint32_t current_msr; - uint32_t new_msr; - - RTEMS_COMPILER_MEMORY_BARRIER(); - - __asm__ volatile ( - "mfmsr %0;" - "ori %1, %0, 0x8000;" - "mtmsr %1" - : "=r" (current_msr), "=r" (new_msr) - ); - - return current_msr; -} - -/** - * @brief Restores machine state. - * - * @see ppc_external_exceptions_enable() - */ -static inline void ppc_external_exceptions_disable(uint32_t msr) -{ - ppc_set_machine_state_register(msr); - - RTEMS_COMPILER_MEMORY_BARRIER(); -} - -static inline uint32_t ppc_count_leading_zeros(uint32_t value) -{ - uint32_t count; - - __asm__ ( - "cntlzw %0, %1;" - : "=r" (count) - : "r" (value) - ); - - return count; -} - -/* - * Simple spin delay in microsecond units for device drivers. - * This is very dependent on the clock speed of the target. - */ - -#if defined(mpx8xx) || defined(mpc860) || defined(mpc821) -/* Wonderful bookE doesn't have mftb/mftbu; they only - * define the TBRU/TBRL SPRs so we use these. Luckily, - * we run in supervisory mode so that should work on - * all CPUs. In user mode we'd have a problem... - * 2007/11/30, T.S. - * - * OTOH, PSIM currently lacks support for reading - * SPRs 268/269. You need GDB patch sim/2376 to avoid - * a crash... - * OTOH, the MPC8xx do not allow to read the timebase registers via mfspr. - * we NEED a mftb to access the time base. - * 2009/10/30 Th. D. - */ -#define CPU_Get_timebase_low( _value ) \ - __asm__ volatile( "mftb %0" : "=r" (_value) ) -#else -#define CPU_Get_timebase_low( _value ) \ - __asm__ volatile( "mfspr %0,268" : "=r" (_value) ) -#endif - -/* Must be provided for rtems_bsp_delay to work */ -extern uint32_t bsp_clicks_per_usec; - -#define rtems_bsp_delay( _microseconds ) \ - do { \ - uint32_t start, ticks, now; \ - CPU_Get_timebase_low( start ) ; \ - ticks = (_microseconds) * bsp_clicks_per_usec; \ - do \ - CPU_Get_timebase_low( now ) ; \ - while (now - start < ticks); \ - } while (0) - -#define rtems_bsp_delay_in_bus_cycles( _cycles ) \ - do { \ - uint32_t start, now; \ - CPU_Get_timebase_low( start ); \ - do \ - CPU_Get_timebase_low( now ); \ - while (now - start < (_cycles)); \ - } while (0) - -/* - * Routines to access the decrementer register - */ - -#define PPC_Set_decrementer( _clicks ) \ - do { \ - __asm__ volatile( "mtdec %0" : : "r" ((_clicks)) ); \ - } while (0) - -#define PPC_Get_decrementer( _clicks ) \ - __asm__ volatile( "mfdec %0" : "=r" (_clicks) ) - -/* - * Routines to access the time base register - */ - -static inline uint64_t PPC_Get_timebase_register( void ) -{ - uint32_t tbr_low; - uint32_t tbr_high; - uint32_t tbr_high_old; - uint64_t tbr; - - do { -#if defined(mpx8xx) || defined(mpc860) || defined(mpc821) -/* See comment above (CPU_Get_timebase_low) */ - __asm__ volatile( "mftbu %0" : "=r" (tbr_high_old)); - __asm__ volatile( "mftb %0" : "=r" (tbr_low)); - __asm__ volatile( "mftbu %0" : "=r" (tbr_high)); -#else - __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high_old)); - __asm__ volatile( "mfspr %0, 268" : "=r" (tbr_low)); - __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high)); -#endif - } while ( tbr_high_old != tbr_high ); - - tbr = tbr_high; - tbr <<= 32; - tbr |= tbr_low; - return tbr; -} - -static inline void PPC_Set_timebase_register (uint64_t tbr) -{ - uint32_t tbr_low; - uint32_t tbr_high; - - tbr_low = (uint32_t) tbr; - tbr_high = (uint32_t) (tbr >> 32); - __asm__ volatile( "mtspr 284, %0" : : "r" (tbr_low)); - __asm__ volatile( "mtspr 285, %0" : : "r" (tbr_high)); - -} - -static inline uint32_t ppc_decrementer_register(void) -{ - uint32_t dec; - - PPC_Get_decrementer(dec); - - return dec; -} - -static inline void ppc_set_decrementer_register(uint32_t dec) -{ - PPC_Set_decrementer(dec); -} - -/** - * @brief Preprocessor magic for stringification of @a x. - */ -#define PPC_STRINGOF(x) #x - -/** - * @brief Returns the value of the Special Purpose Register with number @a spr. - * - * @note This macro uses a GNU C extension. - */ -#define PPC_SPECIAL_PURPOSE_REGISTER(spr) \ - ({ \ - uint32_t val; \ - __asm__ volatile (\ - "mfspr %0, " PPC_STRINGOF(spr) \ - : "=r" (val) \ - ); \ - val;\ - } ) - -/** - * @brief Sets the Special Purpose Register with number @a spr to the value in - * @a val. - */ -#define PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val) \ - do { \ - __asm__ volatile (\ - "mtspr " PPC_STRINGOF(spr) ", %0" \ - : \ - : "r" (val) \ - ); \ - } while (0) - -/** - * @brief Sets in the Special Purpose Register with number @a spr all bits - * which are set in @a bits. - * - * Interrupts are disabled throughout this operation. - */ -#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \ - do { \ - ISR_Level level; \ - uint32_t val; \ - uint32_t mybits = bits; \ - _ISR_Local_disable(level); \ - val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ - val |= mybits; \ - PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ - _ISR_Local_enable(level); \ - } while (0) - -/** - * @brief Sets in the Special Purpose Register with number @a spr all bits - * which are set in @a bits. The previous register value will be masked with - * @a mask. - * - * Interrupts are disabled throughout this operation. - */ -#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED(spr, bits, mask) \ - do { \ - ISR_Level level; \ - uint32_t val; \ - uint32_t mybits = bits; \ - uint32_t mymask = mask; \ - _ISR_Local_disable(level); \ - val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ - val &= ~mymask; \ - val |= mybits; \ - PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ - _ISR_Local_enable(level); \ - } while (0) - -/** - * @brief Clears in the Special Purpose Register with number @a spr all bits - * which are set in @a bits. - * - * Interrupts are disabled throughout this operation. - */ -#define PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \ - do { \ - ISR_Level level; \ - uint32_t val; \ - uint32_t mybits = bits; \ - _ISR_Local_disable(level); \ - val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ - val &= ~mybits; \ - PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ - _ISR_Local_enable(level); \ - } while (0) - -/** - * @brief Returns the value of the Thread Management Register with number @a tmr. - * - * @note This macro uses a GNU C extension. - */ -#define PPC_THREAD_MGMT_REGISTER(tmr) \ - ({ \ - uint32_t val; \ - __asm__ volatile (\ - "mftmr %0, " PPC_STRINGOF(tmr) \ - : "=r" (val) \ - ); \ - val;\ - } ) - -/** - * @brief Sets the Thread Management Register with number @a tmr to the value in - * @a val. - */ -#define PPC_SET_THREAD_MGMT_REGISTER(tmr, val) \ - do { \ - __asm__ volatile (\ - "mttmr " PPC_STRINGOF(tmr) ", %0" \ - : \ - : "r" (val) \ - ); \ - } while (0) - -/** - * @brief Returns the value of the Device Control Register with number @a dcr. - * - * The PowerPC 4XX family has Device Control Registers. - * - * @note This macro uses a GNU C extension. - */ -#define PPC_DEVICE_CONTROL_REGISTER(dcr) \ - ({ \ - uint32_t val; \ - __asm__ volatile (\ - "mfdcr %0, " PPC_STRINGOF(dcr) \ - : "=r" (val) \ - ); \ - val;\ - } ) - -/** - * @brief Sets the Device Control Register with number @a dcr to the value in - * @a val. - * - * The PowerPC 4XX family has Device Control Registers. - */ -#define PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val) \ - do { \ - __asm__ volatile (\ - "mtdcr " PPC_STRINGOF(dcr) ", %0" \ - : \ - : "r" (val) \ - ); \ - } while (0) - -/** - * @brief Sets in the Device Control Register with number @a dcr all bits - * which are set in @a bits. - * - * Interrupts are disabled throughout this operation. - */ -#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \ - do { \ - ISR_Level level; \ - uint32_t val; \ - uint32_t mybits = bits; \ - _ISR_Local_disable(level); \ - val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ - val |= mybits; \ - PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ - _ISR_Local_enable(level); \ - } while (0) - -/** - * @brief Sets in the Device Control Register with number @a dcr all bits - * which are set in @a bits. The previous register value will be masked with - * @a mask. - * - * Interrupts are disabled throughout this operation. - */ -#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS_MASKED(dcr, bits, mask) \ - do { \ - ISR_Level level; \ - uint32_t val; \ - uint32_t mybits = bits; \ - uint32_t mymask = mask; \ - _ISR_Local_disable(level); \ - val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ - val &= ~mymask; \ - val |= mybits; \ - PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ - _ISR_Local_enable(level); \ - } while (0) - -/** - * @brief Clears in the Device Control Register with number @a dcr all bits - * which are set in @a bits. - * - * Interrupts are disabled throughout this operation. - */ -#define PPC_CLEAR_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \ - do { \ - ISR_Level level; \ - uint32_t val; \ - uint32_t mybits = bits; \ - _ISR_Local_disable(level); \ - val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ - val &= ~mybits; \ - PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ - _ISR_Local_enable(level); \ - } while (0) - -static inline uint32_t ppc_time_base(void) -{ - uint32_t val; - - CPU_Get_timebase_low(val); - - return val; -} - -static inline void ppc_set_time_base(uint32_t val) -{ - PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWL, val); -} - -static inline uint32_t ppc_time_base_upper(void) -{ - return PPC_SPECIAL_PURPOSE_REGISTER(TBRU); -} - -static inline void ppc_set_time_base_upper(uint32_t val) -{ - PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWU, val); -} - -static inline uint64_t ppc_time_base_64(void) -{ - return PPC_Get_timebase_register(); -} - -static inline void ppc_set_time_base_64(uint64_t val) -{ - PPC_Set_timebase_register(val); -} - -static inline uint32_t ppc_alternate_time_base(void) -{ - return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBL); -} - -static inline uint32_t ppc_alternate_time_base_upper(void) -{ - return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBU); -} - -static inline uint64_t ppc_alternate_time_base_64(void) -{ - uint32_t atbl; - uint32_t atbu_0; - uint32_t atbu_1; - - do { - atbu_0 = ppc_alternate_time_base_upper(); - atbl = ppc_alternate_time_base(); - atbu_1 = ppc_alternate_time_base_upper(); - } while (atbu_0 != atbu_1); - - return (((uint64_t) atbu_1) << 32) | ((uint64_t) atbl); -} - -static inline uint32_t ppc_processor_id(void) -{ - return PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR); -} - -static inline void ppc_set_processor_id(uint32_t val) -{ - PPC_SET_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR, val); -} - -static inline uint32_t ppc_fsl_system_version(void) -{ - return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_SVR); -} - -static inline uint32_t ppc_fsl_system_version_cid(uint32_t svr) -{ - return (svr >> 28) & 0xf; -} - -static inline uint32_t ppc_fsl_system_version_sid(uint32_t svr) -{ - return (svr >> 16) & 0xfff; -} - -static inline uint32_t ppc_fsl_system_version_proc(uint32_t svr) -{ - return (svr >> 12) & 0xf; -} - -static inline uint32_t ppc_fsl_system_version_mfg(uint32_t svr) -{ - return (svr >> 8) & 0xf; -} - -static inline uint32_t ppc_fsl_system_version_mjrev(uint32_t svr) -{ - return (svr >> 4) & 0xf; -} - -static inline uint32_t ppc_fsl_system_version_mnrev(uint32_t svr) -{ - return (svr >> 0) & 0xf; -} - -void ppc_code_copy(void *dest, const void *src, size_t n); - -/* FIXME: Do not use this function */ -void printBAT(int bat, uint32_t upper, uint32_t lower); - -/* FIXME: Do not use this function */ -void ShowBATS(void); - -#endif /* ifndef ASM */ - -#if defined(ASM) -#include <rtems/asm.h> - -.macro LA reg, addr -#if defined(__powerpc64__) - lis \reg, (\addr)@highest - ori \reg, \reg, (\addr)@higher - rldicr \reg, \reg, 32, 31 - oris \reg, \reg, (\addr)@h - ori \reg, \reg, (\addr)@l -#else - lis \reg, (\addr)@h - ori \reg, \reg, (\addr)@l -#endif -.endm - -.macro LA32 reg, addr - lis \reg, (\addr)@h - ori \reg, \reg, (\addr)@l -.endm - -.macro LWI reg, value - lis \reg, (\value)@h - ori \reg, \reg, (\value)@l -.endm - -.macro LW reg, addr - lis \reg, \addr@ha - lwz \reg, \addr@l(\reg) -.endm - -/* - * Tests the bits in reg1 against the bits set in mask. A match is indicated - * by EQ = 0 in CR0. A mismatch is indicated by EQ = 1 in CR0. The register - * reg2 is used to load the mask. - */ -.macro TSTBITS reg1, reg2, mask - LWI \reg2, \mask - and \reg1, \reg1, \reg2 - cmplw \reg1, \reg2 -.endm - -.macro SETBITS reg1, reg2, mask - LWI \reg2, \mask - or \reg1, \reg1, \reg2 -.endm - -.macro CLRBITS reg1, reg2, mask - LWI \reg2, \mask - andc \reg1, \reg1, \reg2 -.endm - -.macro GLOBAL_FUNCTION name - .global \name - .type \name, @function -\name: -.endm - -/* - * Obtain interrupt mask - */ -.macro GET_INTERRUPT_MASK mask - lis \mask, _PPC_INTERRUPT_DISABLE_MASK@h - ori \mask, \mask, _PPC_INTERRUPT_DISABLE_MASK@l -.endm - -/* - * Disables all asynchronous exeptions (interrupts) which may cause a context - * switch. - */ -.macro INTERRUPT_DISABLE level, mask - mfmsr \level - GET_INTERRUPT_MASK mask=\mask - andc \mask, \level, \mask - mtmsr \mask -.endm - -/* - * Restore previous machine state. - */ -.macro INTERRUPT_ENABLE level - mtmsr \level -.endm - -.macro SET_SELF_CPU_CONTROL reg_0, reg_1 -#if defined(RTEMS_SMP) - /* Use Book E Processor ID Register (PIR) */ - mfspr \reg_0, 286 - slwi \reg_0, \reg_0, PER_CPU_CONTROL_SIZE_LOG2 -#if defined(__powerpc64__) - LA \reg_1, _Per_CPU_Information - add \reg_0, \reg_0, \reg_1 -#else - addis \reg_0, \reg_0, _Per_CPU_Information@ha - addi \reg_0, \reg_0, _Per_CPU_Information@l -#endif - mtspr PPC_PER_CPU_CONTROL_REGISTER, \reg_0 -#endif -.endm - -.macro GET_SELF_CPU_CONTROL reg -#if defined(RTEMS_SMP) - mfspr \reg, PPC_PER_CPU_CONTROL_REGISTER -#else - lis \reg, _Per_CPU_Information@h - ori \reg, \reg, _Per_CPU_Information@l -#endif -.endm - -#define LINKER_SYMBOL(sym) .extern sym - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LIBCPU_POWERPC_UTILITY_H */ diff --git a/c/src/lib/libcpu/powerpc/shared/include/spr.h b/c/src/lib/libcpu/powerpc/shared/include/spr.h deleted file mode 100644 index 6c81d0ee91..0000000000 --- a/c/src/lib/libcpu/powerpc/shared/include/spr.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * spr.h -- Access to special purpose registers. - * - * Copyright (C) 1998 Gabriel Paubert, paubert@iram.es - * - * Modified to compile in RTEMS development environment - * by Eric Valette - * - * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - - -#ifndef _LIBCPU_SPR_H -#define _LIBCPU_SPR_H - -#include <rtems/powerpc/registers.h> - -#define __MFSPR(reg, val) \ - __asm__ __volatile__("mfspr %0,"#reg : "=r" (val)) - -#define __MTSPR(val, reg) \ - __asm__ __volatile__("mtspr "#reg",%0" : : "r" (val)) - - -#define SPR_RW(reg) \ -static inline unsigned long _read_##reg(void) \ -{\ - unsigned long val;\ - __MFSPR(reg, val);\ - return val;\ -}\ -static inline void _write_##reg(unsigned long val)\ -{\ - __MTSPR(val,reg);\ - return;\ -} - -#define SPR_RO(reg) \ -static inline unsigned long _read_##reg(void) \ -{\ - unsigned long val;\ - __MFSPR(reg,val);\ - return val;\ -} - -static inline unsigned long _read_MSR(void) -{ - unsigned long val; - asm volatile("mfmsr %0" : "=r" (val)); - return val; -} - -static inline void _write_MSR(unsigned long val) -{ - asm volatile("mtmsr %0" : : "r" (val)); - return; -} - -static inline unsigned long _read_SR(void * va) -{ - unsigned long val; - asm volatile("mfsrin %0,%1" : "=r" (val): "r" (va)); - return val; -} - -static inline void _write_SR(unsigned long val, void * va) -{ - asm volatile("mtsrin %0,%1" : : "r"(val), "r" (va): "memory"); - return; -} - - -#endif diff --git a/c/src/lib/libcpu/powerpc/shared/src/stackTrace.h b/c/src/lib/libcpu/powerpc/shared/src/stackTrace.h deleted file mode 100644 index f73dc2eff2..0000000000 --- a/c/src/lib/libcpu/powerpc/shared/src/stackTrace.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _LIBCPU_STACKTRACE_H -#define _LIBCPU_STACKTRACE_H - -void CPU_stack_take_snapshot(void **stack, int size, void *pc, void *lr, void *r1); - -void CPU_print_stack(void); - -#endif diff --git a/c/src/lib/libcpu/sparc/Makefile.am b/c/src/lib/libcpu/sparc/Makefile.am index 67a35ee4b8..4d957dac04 100644 --- a/c/src/lib/libcpu/sparc/Makefile.am +++ b/c/src/lib/libcpu/sparc/Makefile.am @@ -4,10 +4,6 @@ include $(top_srcdir)/../../../automake/compile.am noinst_PROGRAMS = -include_libcpudir = $(includedir)/libcpu -include_libcpu_HEADERS = -include_libcpu_HEADERS += include/libcpu/access.h - noinst_PROGRAMS += cache.rel cache_rel_SOURCES = cache/cache_.h \ ../shared/src/cache_manager.c @@ -33,5 +29,4 @@ access_rel_SOURCES = access/access.S access/access_le.c access_rel_CPPFLAGS = $(AM_CPPFLAGS) access_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/sparc/configure.ac b/c/src/lib/libcpu/sparc/configure.ac index 40085add95..98b2ce8c4b 100644 --- a/c/src/lib/libcpu/sparc/configure.ac +++ b/c/src/lib/libcpu/sparc/configure.ac @@ -4,6 +4,8 @@ AC_PREREQ([2.69]) AC_INIT([rtems-c-src-lib-libcpu-sparc],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([reg_win]) RTEMS_TOP([../../../../..],[../../..]) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP RTEMS_CANONICAL_TARGET_CPU diff --git a/c/src/lib/libcpu/sparc/include/libcpu/access.h b/c/src/lib/libcpu/sparc/include/libcpu/access.h deleted file mode 100644 index cdf6b77122..0000000000 --- a/c/src/lib/libcpu/sparc/include/libcpu/access.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * access.h - access routines for SPARC. SPARC is big endian only. - * - * COPYRIGHT (c) 2011 - * Aeroflex Gaisler. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_ACCESS_H -#define _LIBCPU_ACCESS_H - -#include <rtems/system.h> -#include <rtems/score/cpu.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* "Raw" access */ -extern uint8_t _ld8(uint8_t *addr); -extern void _st8(uint8_t *addr, uint8_t val); -extern uint16_t _ld16(uint16_t *addr); -extern void _st16(uint16_t *addr, uint16_t val); -extern uint32_t _ld32(uint32_t *addr); -extern void _st32(uint32_t *addr, uint32_t val); -extern uint64_t _ld64(uint64_t *addr); -extern void _st64(uint64_t *addr, uint64_t val); - -/* Aliases for Big Endian */ -extern uint16_t _ld_be16(uint16_t *addr); -extern void _st_be16(uint16_t *addr, uint16_t val); -extern uint32_t _ld_be32(uint32_t *addr); -extern void _st_be32(uint32_t *addr, uint32_t val); -extern uint64_t _ld_be64(uint64_t *addr); -extern void _st_be64(uint64_t *addr, uint64_t val); - -/* Little endian */ -extern uint16_t _ld_le16(uint16_t *addr); -extern void _st_le16(uint16_t *addr, uint16_t val); -extern uint32_t _ld_le32(uint32_t *addr); -extern void _st_le32(uint32_t *addr, uint32_t val); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libcpu/sparc/preinstall.am b/c/src/lib/libcpu/sparc/preinstall.am deleted file mode 100644 index ec35254581..0000000000 --- a/c/src/lib/libcpu/sparc/preinstall.am +++ /dev/null @@ -1,24 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES = $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -$(PROJECT_INCLUDE)/libcpu/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu - @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - -$(PROJECT_INCLUDE)/libcpu/access.h: include/libcpu/access.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/access.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/access.h - diff --git a/c/src/lib/libcpu/sparc64/Makefile.am b/c/src/lib/libcpu/sparc64/Makefile.am index f7b3beb350..81d07d4617 100644 --- a/c/src/lib/libcpu/sparc64/Makefile.am +++ b/c/src/lib/libcpu/sparc64/Makefile.am @@ -56,5 +56,4 @@ endif #endif ### End of example. -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/sparc64/configure.ac b/c/src/lib/libcpu/sparc64/configure.ac index 5604c4215c..08607a53e7 100644 --- a/c/src/lib/libcpu/sparc64/configure.ac +++ b/c/src/lib/libcpu/sparc64/configure.ac @@ -4,6 +4,8 @@ AC_PREREQ([2.69]) AC_INIT([rtems-c-src-lib-libcpu-sparc64],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([shared]) RTEMS_TOP([../../../../..],[../../..]) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP RTEMS_CANONICAL_TARGET_CPU diff --git a/c/src/lib/libcpu/sparc64/preinstall.am b/c/src/lib/libcpu/sparc64/preinstall.am deleted file mode 100644 index dba6cc4d81..0000000000 --- a/c/src/lib/libcpu/sparc64/preinstall.am +++ /dev/null @@ -1,7 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - |