diff options
Diffstat (limited to 'bsps/riscv')
40 files changed, 3163 insertions, 185 deletions
diff --git a/bsps/riscv/griscv/clock/clockdrv.c b/bsps/riscv/griscv/clock/clockdrv.c index a5b7b15760..3174bae468 100644 --- a/bsps/riscv/griscv/clock/clockdrv.c +++ b/bsps/riscv/griscv/clock/clockdrv.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * Clock Tick Device Driver * @@ -13,16 +15,33 @@ * COPYRIGHT (c) 2004. * Gaisler Research. * - * Copyright (c) 2014, 2018 embedded brains GmbH + * Copyright (C) 2014, 2018 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> #include <amba.h> -#include <bsp/irq.h> +#include <bsp/irq-generic.h> #include <bspopts.h> #include <bsp/fatal.h> #include <rtems/rtems/intr.h> @@ -201,7 +220,7 @@ CPU_Counter_ticks _CPU_Counter_read( void ) #define Clock_driver_support_initialize_hardware() \ grlib_clock_initialize() -#define Clock_driver_timecounter_tick() grlib_tc_do_tick() +#define Clock_driver_timecounter_tick(arg) grlib_tc_do_tick() #include "../../../shared/dev/clock/clockimpl.h" diff --git a/bsps/riscv/griscv/console/console.c b/bsps/riscv/griscv/console/console.c index c0e19cddfe..0627be5ee3 100644 --- a/bsps/riscv/griscv/console/console.c +++ b/bsps/riscv/griscv/console/console.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * This file contains the TTY driver for the GRLIB APBUART * @@ -10,9 +12,26 @@ * COPYRIGHT (c) 2004. * Gaisler Research. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ /* Define CONSOLE_USE_INTERRUPTS to enable APBUART interrupt handling instead @@ -63,7 +82,7 @@ static int find_matching_apbuart(struct ambapp_dev *dev, int index, void *arg) struct ambapp_apb_info *apb = (struct ambapp_apb_info *)dev->devinfo; /* Extract needed information of one APBUART */ - apbuarts[uarts].regs = (struct apbuart_regs *)apb->start; + apbuarts[uarts].regs = (apbuart *)apb->start; apbuarts[uarts].irq = apb->common.irq; /* Get APBUART core frequency, it is assumed that it is the same * as Bus frequency where the UART is situated diff --git a/bsps/riscv/griscv/console/printk_support.c b/bsps/riscv/griscv/console/printk_support.c index f232203520..f3af16be4d 100644 --- a/bsps/riscv/griscv/console/printk_support.c +++ b/bsps/riscv/griscv/console/printk_support.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * This file contains the TTY driver for the GRLIb APBUART * @@ -10,9 +12,26 @@ * COPYRIGHT (c) 2011. * Aeroflex Gaisler. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> @@ -24,9 +43,10 @@ #include <stdio.h> #include <grlib/apbuart.h> #include <grlib/ambapp.h> +#include <grlib/io.h> int grlib_debug_uart_index __attribute__((weak)) = 0; -struct apbuart_regs *grlib_debug_uart = NULL; +apbuart *grlib_debug_uart = NULL; /* Before UART driver has registered (or when no UART is available), calls to * printk that gets to bsp_out_char() will be filling data into the @@ -68,13 +88,17 @@ static void bsp_debug_uart_init(void) VENDOR_GAISLER, GAISLER_APBUART, ambapp_find_by_idx, (void *)&i); if (adev) { + uint32_t ctrl; + /* Found a matching debug console, initialize debug uart if present * for printk */ apb = (struct ambapp_apb_info *)adev->devinfo; - grlib_debug_uart = (struct apbuart_regs *)apb->start; - grlib_debug_uart->ctrl |= APBUART_CTRL_RE | APBUART_CTRL_TE; - grlib_debug_uart->status = 0; + grlib_debug_uart = (apbuart *)apb->start; + ctrl = grlib_load_32(&grlib_debug_uart->ctrl); + ctrl |= APBUART_CTRL_RE | APBUART_CTRL_TE; + grlib_store_32(&grlib_debug_uart->ctrl, ctrl); + grlib_store_32(&grlib_debug_uart->status, 0); } } @@ -88,10 +112,14 @@ RTEMS_SYSINIT_ITEM( static void bsp_out_char(char c) { if (grlib_debug_uart == NULL) { + uint32_t ctrl; + /* Try to assign standard UART address to debug driver to pass some tests */ - grlib_debug_uart = (struct apbuart_regs *) 0x80000100; - grlib_debug_uart->ctrl |= APBUART_CTRL_RE | APBUART_CTRL_TE; - grlib_debug_uart->status = 0; + grlib_debug_uart = (apbuart *) 0x80000100; + ctrl = grlib_load_32(&grlib_debug_uart->ctrl); + ctrl |= APBUART_CTRL_RE | APBUART_CTRL_TE; + grlib_store_32(&grlib_debug_uart->ctrl, ctrl); + grlib_store_32(&grlib_debug_uart->status, 0); /* Local debug buffer when UART driver has not registered */ /* pre_printk_dbgbuf[pre_printk_pos++] = c; diff --git a/bsps/riscv/griscv/include/amba.h b/bsps/riscv/griscv/include/amba.h index 292660d5c1..cff3a53d9e 100644 --- a/bsps/riscv/griscv/include/amba.h +++ b/bsps/riscv/griscv/include/amba.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -12,9 +14,26 @@ * COPYRIGHT (c) 2004. * Gaisler Research * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AMBA_H__ diff --git a/bsps/riscv/griscv/include/bsp.h b/bsps/riscv/griscv/include/bsp.h index 9d6fb2a16f..a0aec4f130 100644 --- a/bsps/riscv/griscv/include/bsp.h +++ b/bsps/riscv/griscv/include/bsp.h @@ -69,12 +69,6 @@ extern "C" { /* Maximum supported APBUARTs by BSP */ #define BSP_NUMBER_OF_TERMIOS_PORTS 8 -/* GRLIB driver functions */ - -extern void BSP_shared_interrupt_mask(int irq); -extern void BSP_shared_interrupt_clear(int irq); -extern void BSP_shared_interrupt_unmask(int irq); - /* * Network driver configuration for greth */ diff --git a/bsps/riscv/griscv/include/bsp/irq.h b/bsps/riscv/griscv/include/bsp/irq.h index 634fee4d01..43ee019620 100644 --- a/bsps/riscv/griscv/include/bsp/irq.h +++ b/bsps/riscv/griscv/include/bsp/irq.h @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> @@ -40,9 +40,6 @@ #ifndef ASM #include <bsp.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> -#include <rtems/score/processormask.h> #define RISCV_INTERRUPT_VECTOR_SOFTWARE 0 @@ -56,16 +53,6 @@ #define BSP_INTERRUPT_VECTOR_COUNT RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS) -rtems_status_code bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -); - -rtems_status_code bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -); - #endif /* ASM */ #endif /* LIBBSP_RISCV_GRISCV_IRQ_H */ diff --git a/bsps/riscv/griscv/irq/irq.c b/bsps/riscv/griscv/irq/irq.c index ea19797565..12af7d7b3d 100644 --- a/bsps/riscv/griscv/irq/irq.c +++ b/bsps/riscv/griscv/irq/irq.c @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> @@ -34,7 +34,6 @@ * SUCH DAMAGE. */ -#include <bsp/irq.h> #include <bsp/fatal.h> #include <bsp/irq-generic.h> #include <amba.h> diff --git a/bsps/riscv/griscv/start/bsp_fatal_halt.c b/bsps/riscv/griscv/start/bsp_fatal_halt.c index 5b1eed3e8f..8af9b37709 100644 --- a/bsps/riscv/griscv/start/bsp_fatal_halt.c +++ b/bsps/riscv/griscv/start/bsp_fatal_halt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> diff --git a/bsps/riscv/griscv/start/bspsmp.c b/bsps/riscv/griscv/start/bspsmp.c index 0e5fd9903b..0c75c25c2b 100644 --- a/bsps/riscv/griscv/start/bspsmp.c +++ b/bsps/riscv/griscv/start/bspsmp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/riscv/griscv/start/bspstart.c b/bsps/riscv/griscv/start/bspstart.c index 26c214caac..62813a1c28 100644 --- a/bsps/riscv/griscv/start/bspstart.c +++ b/bsps/riscv/griscv/start/bspstart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/riscv/include/grlib/io.h b/bsps/riscv/include/grlib/io.h new file mode 100644 index 0000000000..4d5f7d3791 --- /dev/null +++ b/bsps/riscv/include/grlib/io.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief This header file defines the register load/store interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/bsp/riscv/if/grlib-io-header */ + +#ifndef _GRLIB_IO_H +#define _GRLIB_IO_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/bsp/riscv/if/grlib-io-group */ + +/** + * @defgroup RTEMSDeviceGRLIBIO Register Load/Store + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRLIB register load/store API. + */ + +/* Generated from spec:/bsp/riscv/if/grlib-load-08 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 8-bit register. + * + * @param address is the address of the memory-mapped unsigned 8-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint8_t grlib_load_8( const volatile uint8_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/riscv/if/grlib-load-16 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 16-bit register. + * + * @param address is the address of the memory-mapped unsigned 16-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint16_t grlib_load_16( const volatile uint16_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/riscv/if/grlib-load-32 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 32-bit register. + * + * @param address is the address of the memory-mapped unsigned 32-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint32_t grlib_load_32( const volatile uint32_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/riscv/if/grlib-load-64 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 64-bit register. + * + * @param address is the address of the memory-mapped unsigned 64-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint64_t grlib_load_64( const volatile uint64_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/riscv/if/grlib-store-08 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 8-bit register. + * + * @param address is the address of the memory-mapped unsigned 8-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_8( volatile uint8_t *address, uint8_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/riscv/if/grlib-store-16 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 16-bit register. + * + * @param address is the address of the memory-mapped unsigned 16-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_16( volatile uint16_t *address, uint16_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/riscv/if/grlib-store-32 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 32-bit register. + * + * @param address is the address of the memory-mapped unsigned 32-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_32( volatile uint32_t *address, uint32_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/riscv/if/grlib-store-64 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 64-bit register. + * + * @param address is the address of the memory-mapped unsigned 64-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_64( volatile uint64_t *address, uint64_t value ) +{ + *address = value; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_IO_H */ diff --git a/bsps/riscv/noel/console/console-config.c b/bsps/riscv/noel/console/console-config.c new file mode 100644 index 0000000000..c2f8aaa8b3 --- /dev/null +++ b/bsps/riscv/noel/console/console-config.c @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsRISCVNOEL + * + * @brief This source file contains NOEL-V/APBUART definitions of + * ::BSP_output_char_function_type and :: BSP_output_char and an + * implementation of console_initialize(). + */ + +/* + * Copyright (c) 2021 Cobham Gaisler AB. + * + * Copyright (C) 2018 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/bspIo.h> +#include <rtems/console.h> +#include <rtems/sysinit.h> +#include <rtems/termiostypes.h> + +#include <bsp/fatal.h> +#include <bsp/fdt.h> +#include <bsp/irq.h> +#include <bsp/riscv.h> + +#include <libfdt.h> + +#include <grlib/apbuart.h> +#include <grlib/apbuart_termios.h> +static struct apbuart_context apbuarts[RISCV_CONSOLE_MAX_APBUART_DEVICES]; +static size_t apbuart_devices = 0; + +static struct { + rtems_termios_device_context *context; + void (*putchar)(rtems_termios_device_context *base, char c); + int (*getchar)(rtems_termios_device_context *base); +} riscv_console; + +static void riscv_output_char(char c) +{ + (*riscv_console.putchar)(riscv_console.context, c); +} + +static void apbuart_putchar(rtems_termios_device_context *base, char c) +{ + struct apbuart_context *ctx = (struct apbuart_context *) base; + apbuart_outbyte_polled(ctx->regs, c); +} + +static int apbuart_getchar(rtems_termios_device_context *base) +{ + struct apbuart_context *ctx = (struct apbuart_context *) base; + return apbuart_inbyte_nonblocking(ctx->regs); +} + +#define RISCV_CONSOLE_IS_COMPATIBLE(actual, actual_len, desired) \ + (actual_len == sizeof(desired) \ + && memcmp(actual, desired, sizeof(desired) - 1) == 0) + +static uint32_t get_core_frequency(void) +{ + uint32_t node; + const char *fdt; + int len; + const fdt32_t *val; + + fdt = bsp_fdt_get(); + node = fdt_node_offset_by_compatible(fdt, -1, "fixed-clock"); + + val = fdt_getprop(fdt, node, "clock-frequency", &len); + if (val == NULL && len != 4) { + bsp_fatal(RISCV_FATAL_NO_APBUART_CLOCK_FREQUENCY_IN_DEVICE_TREE); + } + + return fdt32_to_cpu(*val); +} + +static void riscv_console_probe(void) +{ + const void *fdt; + int node; + + fdt = bsp_fdt_get(); + + node = fdt_next_node(fdt, -1, NULL); + + while (node >= 0) { + const char *compat; + int compat_len; + + compat = fdt_getprop(fdt, node, "compatible", &compat_len); + if (compat == NULL) { + compat_len = 0; + } + + if ( + RISCV_CONSOLE_IS_COMPATIBLE(compat, compat_len, "gaisler,apbuart") + && (apbuart_devices < RISCV_CONSOLE_MAX_APBUART_DEVICES) + ) { + struct apbuart_context *ctx; + fdt32_t *val; + int len; + + ctx = &apbuarts[apbuart_devices]; + + ctx->regs = riscv_fdt_get_address(fdt, node); + if (ctx->regs == NULL) { + bsp_fatal(RISCV_FATAL_NO_APBUART_REG_IN_DEVICE_TREE); + } + + ctx->freq_hz = get_core_frequency(); + + val = (fdt32_t *) fdt_getprop(fdt, node, "interrupts", &len); + if (val == NULL || len != 4) { + bsp_fatal(RISCV_FATAL_NO_APBUART_INTERRUPTS_IN_DEVICE_TREE); + } + ctx->irq = RISCV_INTERRUPT_VECTOR_EXTERNAL(fdt32_to_cpu(val[0])); + + if (apbuart_devices == 0) { + riscv_console.context = &ctx->base; + riscv_console.putchar = apbuart_putchar; + riscv_console.getchar = apbuart_getchar; + } + + rtems_termios_device_context_initialize(&ctx->base, "APBUART"); + + apbuart_devices++; + }; + + node = fdt_next_node(fdt, node, NULL); + } + + BSP_output_char = riscv_output_char; +} + +static void riscv_output_char_init(char c) +{ + riscv_console_probe(); + riscv_output_char(c); +} + +BSP_output_char_function_type BSP_output_char = riscv_output_char_init; + +BSP_polling_getchar_function_type BSP_poll_char = NULL; + +rtems_status_code console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + char path[] = "/dev/ttyS?"; + + rtems_termios_initialize(); + + const rtems_termios_device_handler *handler = &apbuart_handler_polled; + + if (BSP_CONSOLE_USE_INTERRUPTS) { + handler = &apbuart_handler_interrupt; + } + for (size_t i = 0; i < apbuart_devices; ++i) { + struct apbuart_context *ctx; + + ctx = &apbuarts[i]; + path[sizeof(path) - 2] = (char) ('0' + i); + rtems_termios_device_install(path, handler, NULL, &ctx->base); + + if (&ctx->base == riscv_console.context) { + link(path, CONSOLE_DEVICE_NAME); + } + } + + return RTEMS_SUCCESSFUL; +} + +RTEMS_SYSINIT_ITEM( + riscv_console_probe, + RTEMS_SYSINIT_BSP_START, + RTEMS_SYSINIT_ORDER_LAST_BUT_5 +); diff --git a/bsps/riscv/noel/include/bsp.h b/bsps/riscv/noel/include/bsp.h new file mode 100644 index 0000000000..8cad281b6a --- /dev/null +++ b/bsps/riscv/noel/include/bsp.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsRISCVNOEL + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2021 Cobham Gaisler AB. + * + * Copyright (c) 2015 University of York. + * Hesham Almatary <hesham@alumni.york.ac.uk> + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef LIBBSP_RISCV_NOEL_H +#define LIBBSP_RISCV_NOEL_H + +/** + * @defgroup RTEMSBSPsRISCVNOEL NOEL-V + * + * @ingroup RTEMSBSPsRISCV + * + * @brief NOEL-V RISC-V Board Support Package. + * + * @{ + */ + +#include <rtems.h> +#include <rtems/clockdrv.h> +#include <rtems/console.h> + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems/devnull.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_FDT_IS_SUPPORTED + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* LIBBSP_RISCV_NOEL_H */ diff --git a/bsps/riscv/noel/include/bsp/irq.h b/bsps/riscv/noel/include/bsp/irq.h new file mode 100644 index 0000000000..3bbea3edfe --- /dev/null +++ b/bsps/riscv/noel/include/bsp/irq.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RISCV_IRQ + * + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2018 embedded brains GmbH & Co. KG + * + * Copyright (c) 2015 University of York. + * Hesham Almatary <hesham@alumni.york.ac.uk> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef LIBBSP_GENERIC_RISCV_IRQ_H +#define LIBBSP_GENERIC_RISCV_IRQ_H + +#ifndef ASM + +#include <bsp.h> + +#define RISCV_INTERRUPT_VECTOR_SOFTWARE 0 + +#define RISCV_INTERRUPT_VECTOR_TIMER 1 + +#define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2) + +#define RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(x) ((x) >= 2) + +#define RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(x) ((x) - 2) + +#define BSP_INTERRUPT_VECTOR_COUNT RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS) + +#define BSP_INTERRUPT_CUSTOM_VALID_VECTOR + +#endif /* ASM */ + +#endif /* LIBBSP_GENERIC_RISCV_IRQ_H */ diff --git a/bsps/riscv/noel/include/bsp/riscv.h b/bsps/riscv/noel/include/bsp/riscv.h new file mode 100644 index 0000000000..42e0f47ae8 --- /dev/null +++ b/bsps/riscv/noel/include/bsp/riscv.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (c) 2018 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef BSP_RISCV_H +#define BSP_RISCV_H + +#include <bsp.h> + +#include <rtems/score/cpuimpl.h> + +#ifdef __cplusplus +extern "C" { +#endif + +extern volatile RISCV_CLINT_regs *riscv_clint; + +void *riscv_fdt_get_address(const void *fdt, int node); + +uint32_t riscv_get_core_frequency(void); + +#ifdef RTEMS_SMP +extern uint32_t riscv_hart_count; +#else +#define riscv_hart_count 1 +#endif + +uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle); + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_RISCV_H */ diff --git a/bsps/riscv/noel/include/tm27.h b/bsps/riscv/noel/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/riscv/noel/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/riscv/noel/start/bsp_fatal_halt.c b/bsps/riscv/noel/start/bsp_fatal_halt.c new file mode 100644 index 0000000000..93c4ee42b5 --- /dev/null +++ b/bsps/riscv/noel/start/bsp_fatal_halt.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2021 Cobham Gaisler AB + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp/riscv.h> + +/* From bsps/arm/fvp/include/bsp/semihosting.h */ +#define TARGET_SYS_EXIT_EXTENDED 0x20 +#define ADP_Stopped_ApplicationExit 0x20026 + +void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ) +{ + uint64_t args[2] = {ADP_Stopped_ApplicationExit, error}; + __asm__ volatile ("li a0, %0" ::"i"(TARGET_SYS_EXIT_EXTENDED)); + __asm__ volatile ("mv a1, %0" ::"r"(&args)); + __asm__ volatile ("slli zero, zero, 0x1f"); + __asm__ volatile ("ebreak"); + __asm__ volatile ("srai zero, zero, 0x7"); + + while (true) { + ; + } +} diff --git a/bsps/riscv/riscv/clock/clockdrv.c b/bsps/riscv/riscv/clock/clockdrv.c index 65bc7c80ef..d2f8f5da54 100644 --- a/bsps/riscv/riscv/clock/clockdrv.c +++ b/bsps/riscv/riscv/clock/clockdrv.c @@ -1,13 +1,14 @@ /** * @file * - * @ingroup bsp_clock + * @ingroup RTEMSDriverClockImpl * - * @brief riscv clock support. + * @brief This source file contains the implementation of the riscv Clock + * Driver. */ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (C) 2018, 2023 embedded brains GmbH & Co. KG * COPYRIGHT (c) 2015 Hesham Alatary <hesham@alumni.york.ac.uk> * * Redistribution and use in source and binary forms, with or without @@ -40,14 +41,12 @@ #include <rtems/sysinit.h> #include <rtems/timecounter.h> #include <rtems/score/cpuimpl.h> +#include <rtems/score/percpu.h> #include <rtems/score/riscv-utility.h> #include <rtems/score/smpimpl.h> #include <libfdt.h> -/* This is defined in dev/clock/clockimpl.h */ -void Clock_isr(void *arg); - typedef struct { struct timecounter base; volatile RISCV_CLINT_regs *clint; @@ -91,19 +90,19 @@ static uint64_t riscv_clock_read_mtime(volatile RISCV_CLINT_timer_reg *mtime) static void riscv_clock_at_tick(riscv_timecounter *tc) { - volatile RISCV_CLINT_regs *clint; + Per_CPU_Control *cpu_self; + volatile RISCV_CLINT_timer_reg *mtimecmp; uint64_t value; - uint32_t cpu = rtems_scheduler_get_processor(); - clint = tc->clint; - - value = clint->mtimecmp[cpu].val_64; + cpu_self = _Per_CPU_Get(); + mtimecmp = cpu_self->cpu_per_cpu.clint_mtimecmp; + value = mtimecmp->val_64; value += tc->interval; - riscv_clock_write_mtimecmp(&clint->mtimecmp[cpu], value); + riscv_clock_write_mtimecmp(mtimecmp, value); } -static void riscv_clock_handler_install(void) +static void riscv_clock_handler_install(rtems_interrupt_handler handler) { rtems_status_code sc; @@ -111,8 +110,8 @@ static void riscv_clock_handler_install(void) RISCV_INTERRUPT_VECTOR_TIMER, "Clock", RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) Clock_isr, - NULL + handler, + &riscv_clock_tc ); if (sc != RTEMS_SUCCESSFUL) { bsp_fatal(RISCV_FATAL_CLOCK_IRQ_INSTALL); @@ -150,16 +149,12 @@ static uint32_t riscv_clock_get_timebase_frequency(const void *fdt) return fdt32_to_cpu(*val); } -static void riscv_clock_clint_init( - volatile RISCV_CLINT_regs *clint, - uint64_t cmpval, - uint32_t cpu -) +static void riscv_clock_clint_init(uint64_t cmpval) { - riscv_clock_write_mtimecmp( - &clint->mtimecmp[cpu], - cmpval - ); + Per_CPU_Control *cpu_self; + + cpu_self = _Per_CPU_Get(); + riscv_clock_write_mtimecmp(cpu_self->cpu_per_cpu.clint_mtimecmp, cmpval); /* Enable mtimer interrupts */ set_csr(mie, MIP_MTIP); @@ -168,11 +163,7 @@ static void riscv_clock_clint_init( #if defined(RTEMS_SMP) && !defined(CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR) static void riscv_clock_secondary_action(void *arg) { - volatile RISCV_CLINT_regs *clint = riscv_clint; - uint64_t *cmpval = arg; - uint32_t cpu = _CPU_SMP_Get_current_processor(); - - riscv_clock_clint_init(clint, *cmpval, cpu); + riscv_clock_clint_init(*(uint64_t *) arg); } #endif @@ -214,7 +205,7 @@ static void riscv_clock_initialize(void) cmpval = riscv_clock_read_mtime(&clint->mtime); cmpval += interval; - riscv_clock_clint_init(clint, cmpval, 0); + riscv_clock_clint_init(cmpval); riscv_clock_secondary_initialization(clint, cmpval, interval); /* Initialize timecounter */ @@ -248,11 +239,11 @@ RTEMS_SYSINIT_ITEM( RTEMS_SYSINIT_ORDER_FIRST ); -#define Clock_driver_support_at_tick() riscv_clock_at_tick(&riscv_clock_tc) +#define Clock_driver_support_at_tick(arg) riscv_clock_at_tick(arg) #define Clock_driver_support_initialize_hardware() riscv_clock_initialize() #define Clock_driver_support_install_isr(isr) \ - riscv_clock_handler_install() + riscv_clock_handler_install(isr) #include "../../../shared/dev/clock/clockimpl.h" diff --git a/bsps/riscv/riscv/config/kendrytek210.cfg b/bsps/riscv/riscv/config/kendrytek210.cfg new file mode 100644 index 0000000000..b04e78b0e9 --- /dev/null +++ b/bsps/riscv/riscv/config/kendrytek210.cfg @@ -0,0 +1,9 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv + +CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d -mcmodel=medany + +LDFLAGS = -Wl,--gc-sections + +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv/config/mpfs64imafdc.cfg b/bsps/riscv/riscv/config/mpfs64imafdc.cfg new file mode 100644 index 0000000000..b04e78b0e9 --- /dev/null +++ b/bsps/riscv/riscv/config/mpfs64imafdc.cfg @@ -0,0 +1,9 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv + +CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d -mcmodel=medany + +LDFLAGS = -Wl,--gc-sections + +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv/console/console-config.c b/bsps/riscv/riscv/console/console-config.c index d962a5a418..df9828cf27 100644 --- a/bsps/riscv/riscv/console/console-config.c +++ b/bsps/riscv/riscv/console/console-config.c @@ -11,7 +11,7 @@ */ /* - * Copyright (C) 2018 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -55,12 +55,12 @@ #include <libfdt.h> #include <string.h> -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 +#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0 #include <bsp/fe310-uart.h> static fe310_uart_context fe310_uart_instance; #endif -#if RISCV_ENABLE_HTIF_SUPPORT != 0 +#ifdef RISCV_ENABLE_HTIF_SUPPORT static htif_console_context htif_console_instance; #endif @@ -139,10 +139,6 @@ static void riscv_console_set_reg_32(uintptr_t addr, uint8_t i, uint8_t val) } #endif -#define RISCV_CONSOLE_IS_COMPATIBLE(actual, actual_len, desired) \ - (actual_len == sizeof(desired) \ - && memcmp(actual, desired, sizeof(desired) - 1) == 0) - static void riscv_console_probe(void) { const void *fdt; @@ -169,8 +165,9 @@ static void riscv_console_probe(void) compat_len = 0; } -#if RISCV_ENABLE_HTIF_SUPPORT != 0 - if (RISCV_CONSOLE_IS_COMPATIBLE(compat, compat_len, "ucb,htif0")) { +#ifdef RISCV_ENABLE_HTIF_SUPPORT + /* Search for HTIF (eg. on Spike) and use it if found */ + if (fdt_stringlist_contains(compat, compat_len, "ucb,htif0")) { htif_console_context_init(&htif_console_instance.base, node); riscv_console.context = &htif_console_instance.base; @@ -181,8 +178,8 @@ static void riscv_console_probe(void) #if RISCV_CONSOLE_MAX_NS16550_DEVICES > 0 if ( - (RISCV_CONSOLE_IS_COMPATIBLE(compat, compat_len, "ns16550a") - || RISCV_CONSOLE_IS_COMPATIBLE(compat, compat_len, "ns16750")) + (fdt_stringlist_contains(compat, compat_len, "ns16550a") + || fdt_stringlist_contains(compat, compat_len, "ns16750")) && ns16550_devices < RISCV_CONSOLE_MAX_NS16550_DEVICES ) { ns16550_context *ctx; @@ -203,7 +200,7 @@ static void riscv_console_probe(void) ctx->set_reg = riscv_console_set_reg_8; } - if (RISCV_CONSOLE_IS_COMPATIBLE(compat, compat_len, "ns16750")) { + if (fdt_stringlist_contains(compat, compat_len, "ns16750")) { ctx->has_precision_clock_synthesizer = true; } @@ -242,8 +239,8 @@ static void riscv_console_probe(void) } #endif -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 - if (RISCV_CONSOLE_IS_COMPATIBLE(compat, compat_len, "sifive,uart0")) { +#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0 + if (fdt_stringlist_contains(compat, compat_len, "sifive,uart0")) { fe310_uart_context *ctx; ctx = &fe310_uart_instance; @@ -258,7 +255,7 @@ static void riscv_console_probe(void) riscv_console.getchar = fe310_uart_read; } - rtems_termios_device_context_initialize(&ctx->base, "FE310UART"); + rtems_termios_device_context_initialize(&ctx->base, "SIFIVEUART"); } #endif @@ -284,7 +281,7 @@ rtems_status_code console_initialize( void *arg ) { -#if RISCV_ENABLE_HTIF_SUPPORT != 0 +#ifdef RISCV_ENABLE_HTIF_SUPPORT rtems_termios_device_context *base; char htif_path[] = "/dev/ttyShtif"; #endif @@ -293,14 +290,14 @@ rtems_status_code console_initialize( size_t i; #endif -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 +#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0 fe310_uart_context *ctx; char fe310_path[] = "/dev/ttyS0"; #endif rtems_termios_initialize(); -#if RISCV_ENABLE_HTIF_SUPPORT != 0 +#ifdef RISCV_ENABLE_HTIF_SUPPORT base = &htif_console_instance.base; rtems_termios_device_install(htif_path, &htif_console_handler, NULL, base); @@ -329,7 +326,7 @@ rtems_status_code console_initialize( } #endif -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 +#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0 ctx = &fe310_uart_instance; rtems_termios_device_install( fe310_path, diff --git a/bsps/riscv/riscv/console/fe310-uart.c b/bsps/riscv/riscv/console/fe310-uart.c index 4ae62d7176..ddabcff4c8 100644 --- a/bsps/riscv/riscv/console/fe310-uart.c +++ b/bsps/riscv/riscv/console/fe310-uart.c @@ -34,11 +34,13 @@ int fe310_uart_read(rtems_termios_device_context *base) { fe310_uart_context * ctx = (fe310_uart_context*) base; + int32_t rxdata; - if ((ctx->regs->rxdata & TXRXREADY) != 0) { + rxdata = ctx->regs->rxdata; + if ((rxdata & TXRXREADY) != 0) { return -1; } else { - return ctx->regs->rxdata; + return rxdata & 0xFF; } } @@ -51,7 +53,7 @@ static void fe310_uart_write ( fe310_uart_context * ctx = (fe310_uart_context*) base; size_t i; - ctx->regs->div = riscv_get_core_frequency() / 115200 - 1; + ctx->regs->div = (riscv_get_core_frequency() / 115200 - 1) & 0xFFFF; ctx->regs->txctrl |= 1; ctx->regs->rxctrl |= 1; @@ -91,6 +93,7 @@ static bool fe310_uart_first_open ( (ctx->regs)->div = riscv_get_core_frequency() / 115200 - 1; (ctx->regs)->txctrl |= 1; (ctx->regs)->rxctrl |= 1; + (ctx->regs)->ie = 0; return true; }; diff --git a/bsps/riscv/riscv/console/htif.c b/bsps/riscv/riscv/console/htif.c index bcfe6a5db5..159d9d72fb 100644 --- a/bsps/riscv/riscv/console/htif.c +++ b/bsps/riscv/riscv/console/htif.c @@ -29,7 +29,7 @@ #include <bsp/riscv.h> -#if RISCV_ENABLE_HTIF_SUPPORT != 0 +#ifdef RISCV_ENABLE_HTIF_SUPPORT #include <dev/serial/htif.h> diff --git a/bsps/riscv/riscv/dts/kendryte-k210.dts b/bsps/riscv/riscv/dts/kendryte-k210.dts new file mode 100644 index 0000000000..cad413dc81 --- /dev/null +++ b/bsps/riscv/riscv/dts/kendryte-k210.dts @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) Alan Cudmore + * Copyright (C) Padmarao Begari + * Copyright (C) 2022 Microchip Technology Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + /* This is a device tree for the Kendryte K210 SoC. It is a simplified tree + * to support the current RTEMS BSP, but it is not sufficient enough for + * full linux or u-boot support. + * The file structure is based on the device tree source for the + * Polarfire SoC created by Padmaro Begari. The K210 device trees from + * u-boot were originally used to bring up the RTEMS BSP and were + * referenced to develop this file. + */ + +/dts-v1/; + +/ { + /* 32 bit address bus - upper 32 bits are ignored */ + #address-cells = <1>; + #size-cells = <1>; + + model = "Kendtryte K210 generic"; + compatible = "canaan,kendryte-k210"; + + aliases { + serial0 = &uarths0; + serial1 = &uart1; + /* serial2 = &uart2; */ + /* serial3 = &uart3; */ + }; + + chosen { + stdout-path = "serial0"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + timebase-frequency = <7800000>; + + cpu0: cpu@0 { + compatible = "canaan,k210", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa = "rv64imafdc"; + i-cache-block-size = <64>; + i-cache-size = <0x8000>; + d-cache-block-size = <64>; + d-cache-size = <0x8000>; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "canaan,k210", "riscv"; + device_type = "cpu"; + reg = <1>; + riscv,isa = "rv64imafdc"; + i-cache-block-size = <64>; + i-cache-size = <0x8000>; + d-cache-block-size = <64>; + d-cache-size = <0x8000>; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + }; + + clocks { + in0: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + }; + + sram: memory@80000000 { + device_type = "memory"; + compatible = "canaan,k210-sram"; + reg = <0x80000000 0x400000>, + <0x80400000 0x200000>, + <0x80600000 0x200000>; + reg-names = "sram0", + "sram1", + "aisram"; + + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&plic0>; + + rom0: nvmem@1000 { + reg = <0x1000 0x1000>; + read-only; + }; + + clint0: timer@2000000 { + compatible = "riscv,clint0","sifive,clint0"; + reg = <0x2000000 0xC000>; + interrupts-extended = <&cpu0_intc 3>,<&cpu0_intc 7>, + <&cpu1_intc 3>,<&cpu1_intc 7>; + }; + + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + #address-cells = <0>; + compatible = "riscv,plic0","sifive,plic-1.0.0"; + reg = <0xC000000 0x4000000>; + riscv,ndev = <65>; + interrupt-controller; + interrupts-extended = + <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>; + }; + + uarths0: serial@38000000 { + compatible = "canaan,k210-uarths","sifive,uart0"; + reg = <0x38000000 0x1000>; + interrupts = <33>; + clocks = <&sysclk 0>; + + }; + + /* apb0 has gpio1 and additional uarts */ + apb0: bus@50200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk 8>; + + uart1: serial@50210000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50210000 0x100>; + interrupts = <11>; + clocks = <&sysclk 30>, + <&sysclk 8>; + clock-namees = "baudclk", "abp_pclk"; + resets = <&sysrst 16>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + }; + }; + + apb1: bus@50400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk 9>; + + sysctl: syscon@50440000 { + compatible = "canaan,k210-sysctl","syscon", + "simple-mfd"; + reg = <0x50440000 0x100>; + clocks = <&sysclk 9>; + clock-names = "pclk"; + sysclk: clock-controller { + #clock-cells = <1>; + compatible = "canaan,k210-rst"; + clock = <&in0>; + }; + sysrst: reset-coontroller { + compatible = "canaan,k210-rst"; + #reset-cells = <1>; + }; + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&sysctl>; + offset = <48>; + mask = <1>; + value = <1>; + }; + }; + }; + + }; +}; diff --git a/bsps/riscv/riscv/dts/mpfs.dts b/bsps/riscv/riscv/dts/mpfs.dts new file mode 100644 index 0000000000..7b19701b02 --- /dev/null +++ b/bsps/riscv/riscv/dts/mpfs.dts @@ -0,0 +1,365 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) Padmarao Begari <padmarao.begari@microchip.com> + * Copyright (C) 2022 Microchip Technology Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + + model = "Microchip PolarFire-SoC Icicle Kit"; + compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; + + aliases { + serial1 = &uart1; + ethernet0 = &emac1; + }; + + chosen { + stdout-path = "serial1"; + }; + + cpucomplex: cpus { + #address-cells = <1>; + #size-cells = <0>; + + timebase-frequency = <1000000>; + + cpu0: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + cpu1intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + cpu2intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + cpu3intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu4: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + cpu4intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + clock-output-names = "msspllclk"; + }; + + ddr: memory@1000000000 { + device_type = "memory"; + reg = <0x00000010 0x00000000 0x00000000 0x10000000>; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "microchip,mpfs-soc", "simple-bus"; + ranges; + + clint0: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&cpu0intc 3 &cpu0intc 7 + &cpu1intc 3 &cpu1intc 7 + &cpu2intc 3 &cpu2intc 7 + &cpu3intc 3 &cpu3intc 7 + &cpu4intc 3 &cpu4intc 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + reg-names = "control"; + clock-frequency = <1000000>; + }; + + cachecontroller: cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + + plic: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,max-priority = <7>; + riscv,ndev = <186>; + interrupt-controller; + interrupts-extended = < + &cpu0intc 11 + &cpu1intc 11 &cpu1intc 9 + &cpu2intc 11 &cpu2intc 9 + &cpu3intc 11 &cpu3intc 9 + &cpu4intc 11 &cpu4intc 9>; + }; + + clkcfg: clkcfg@20002000 { + compatible = "microchip,mpfs-clkcfg"; + reg = <0x0 0x20002000 0x0 0x1000>; + reg-names = "mss_sysreg"; + clocks = <&refclk>; + #clock-cells = <1>; + clock-output-names = "cpu", "axi", "ahb", "envm", + "mac0", "mac1", "mmc", "timer", + "mmuart0", "mmuart1", "mmuart2", + "mmuart3", "mmuart4", "spi0", "spi1", + "i2c0", "i2c1", "can0", "can1", "usb", + "reserved", "rtc", "qspi", "gpio0", + "gpio1", "gpio2", "ddrc", "fic0", + "fic1", "fic2", "fic3", "athena", + "cfm"; + }; + + /* Common node entry for eMMC/SD */ + mmc: mmc@20008000 { + compatible = "microchip,mpfs-sd4hc","cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + clocks = <&clkcfg 6>; + interrupt-parent = <&plic>; + interrupts = <88 89>; + max-frequency = <200000000>; + bus-width = <4>; + disable-wp; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "disabled"; + }; + + uart1: serial@20100000 { + compatible = "ns16550a"; + reg = <0x0 0x20100000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <91>; + clock-frequency = <150000000>; + clocks = <&clkcfg 9>; + status = "okay"; + }; + + spi0: spi@20108000 { + compatible = "microchip,mpfs-spi"; + reg = <0x0 0x20108000 0x0 0x1000>; + clocks = <&clkcfg 13>; + interrupt-parent = <&plic>; + interrupts = <54>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@2010b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,mpfs-i2c"; + reg = <0x0 0x2010b000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <61>; + clocks = <&clkcfg 16>; + clock-frequency = <100000>; + status = "okay"; + pac193x@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + samp-rate = <64>; + status = "disabled"; + ch1: channel0 { + uohms-shunt-res = <10000>; + rail-name = "VDD"; + channel_enabled; + }; + ch2: channel1 { + uohms-shunt-res = <10000>; + rail-name = "VDDA25"; + channel_enabled; + }; + ch3: channel2 { + uohms-shunt-res = <10000>; + rail-name = "VDD25"; + channel_enabled; + }; + ch4: channel3 { + uohms-shunt-res = <10000>; + rail-name = "VDDA"; + channel_enabled; + }; + }; + }; + + emac1: ethernet@20112000 { + compatible = "microchip,mpfs-macb","cdns,gem"; + reg = <0x0 0x20112000 0x0 0x2000>; + interrupt-parent = <&plic>; + interrupts = <70 71 72 73>; + local-mac-address = [00 04 A3 00 00 02]; + phy-mode = "sgmii"; + clocks = <&clkcfg 5>, <&clkcfg 1>; + clock-names = "pclk", "hclk"; + clock-frequency = <150000000>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&phy1>; + phy1: ethernet-phy@9 { + reg = <9>; + }; + }; + + gpio: gpio@20122000 { + compatible = "microchip,mpfs-gpio"; + interrupt-parent = <&plic>; + interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26 + 27 28 29 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44>; + gpio-controller; + clocks = <&clkcfg 25>; + reg = <0x00 0x20122000 0x0 0x1000>; + reg-names = "control"; + #gpio-cells = <2>; + status = "disabled"; + }; + }; +}; diff --git a/bsps/riscv/riscv/include/bsp.h b/bsps/riscv/riscv/include/bsp.h index d19f0d03a5..c33de42aa7 100644 --- a/bsps/riscv/riscv/include/bsp.h +++ b/bsps/riscv/riscv/include/bsp.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -58,6 +60,10 @@ #include <rtems/devnull.h> +#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0 + #include <bsp/k210.h> +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/bsps/riscv/riscv/include/bsp/irq.h b/bsps/riscv/riscv/include/bsp/irq.h index 1b67c4e046..3bbea3edfe 100644 --- a/bsps/riscv/riscv/include/bsp/irq.h +++ b/bsps/riscv/riscv/include/bsp/irq.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -7,7 +9,7 @@ */ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> @@ -40,9 +42,6 @@ #ifndef ASM #include <bsp.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> -#include <rtems/score/processormask.h> #define RISCV_INTERRUPT_VECTOR_SOFTWARE 0 @@ -56,15 +55,7 @@ #define BSP_INTERRUPT_VECTOR_COUNT RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS) -rtems_status_code bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -); - -rtems_status_code bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -); +#define BSP_INTERRUPT_CUSTOM_VALID_VECTOR #endif /* ASM */ diff --git a/bsps/riscv/riscv/include/bsp/k210.h b/bsps/riscv/riscv/include/bsp/k210.h new file mode 100644 index 0000000000..d5ae062863 --- /dev/null +++ b/bsps/riscv/riscv/include/bsp/k210.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup k210_regs + * + * @brief k210 RISC-V CPU defines. + */ + +/* + * Copyright (c) 2022 Alan Cudmore + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_RISCV_RISCV_K210_H +#define LIBBSP_RISCV_RISCV_K210_H + +#include <bspopts.h> +#include <stdint.h> +#include <bsp/utility.h> + +/** + * @defgroup K210 RISC V Register Definitions + * + * @ingroup RTEMSBSPsriscv + * + * @brief Register Definitions + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* For PLL / Clocks */ +#define K210_SYSCTL_BASE 0x50440000 + +#define PLL_CLK_R(n) (n & 0x00000F) +#define PLL_CLK_F(n) ((n & 0x0003F0) >> 4) +#define PLL_CLK_OD(n) ((n & 0x003C00) >> 10) +#define CLKSEL0_ACLK_SEL(n) (n & 0x00000001) + +typedef struct { + uint32_t git_id; + uint32_t clk_freq; + uint32_t pll0; + uint32_t pll1; + uint32_t pll2; + uint32_t resv5; + uint32_t pll_lock; + uint32_t rom_error; + uint32_t clk_sel0; + uint32_t clk_sel1; + uint32_t clk_en_cent; + uint32_t clk_en_peri; + uint32_t soft_reset; + uint32_t peri_reset; + uint32_t clk_th0; + uint32_t clk_th1; + uint32_t clk_th2; + uint32_t clk_th3; + uint32_t clk_th4; + uint32_t clk_th5; + uint32_t clk_th6; + uint32_t misc; + uint32_t peri; + uint32_t spi_sleep; + uint32_t reset_status; + uint32_t dma_sel0; + uint32_t dma_sel1; + uint32_t power_sel; + uint32_t resv28; + uint32_t resv29; + uint32_t resv30; + uint32_t resv31; +} k210_sysctl_t; + +#ifdef __cplusplus +} +#endif + +/** @} */ +#endif /* LIBBSP_RISCV_RISCV_K210_H */ diff --git a/bsps/riscv/riscv/include/bsp/kendryte-k210-dtb.h b/bsps/riscv/riscv/include/bsp/kendryte-k210-dtb.h new file mode 100644 index 0000000000..f1693f891b --- /dev/null +++ b/bsps/riscv/riscv/include/bsp/kendryte-k210-dtb.h @@ -0,0 +1,315 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Declarations for C structure representing binary file system.dtb + * + * WARNING: Automatically generated -- do not edit! + */ + +/* + * Copyright (C) Alan Cudmore + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __kendryte_k210_dtb_h +#define __kendryte_k210_dtb_h + +#include <rtems/score/basedefs.h> +#include <sys/types.h> + +const unsigned char system_dtb[] RTEMS_ALIGNED(8) = { + 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x0c, 0xa7, 0x00, 0x00, 0x00, 0x38, + 0x00, 0x00, 0x0a, 0xb4, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11, + 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf3, + 0x00, 0x00, 0x0a, 0x7c, 0x00, 0x00, 0x00, 0x00, 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b/bsps/riscv/riscv/include/bsp/mpfs-dtb.h @@ -0,0 +1,602 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Declarations for C structure representing binary file mpfs.dtb + * + * WARNING: Automatically generated -- do not edit! + */ + +/* + * Copyright (C) Padmarao Begari <padmarao.begari@microchip.com> + * Copyright (C) 2022 Microchip Technology Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __system_dtb_h +#define __system_dtb_h + +#include <rtems/score/basedefs.h> +#include <sys/types.h> + +const unsigned char system_dtb[] RTEMS_ALIGNED(8) = { + 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x1a, 0x1f, 0x00, 0x00, 0x00, 0x38, + 0x00, 0x00, 0x16, 0xe8, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11, + 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x37, + 0x00, 0x00, 0x16, 0xb0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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+#endif /* __system_dtb_h */ diff --git a/bsps/riscv/riscv/include/bsp/riscv.h b/bsps/riscv/riscv/include/bsp/riscv.h index a469155865..5f8edb650d 100644 --- a/bsps/riscv/riscv/include/bsp/riscv.h +++ b/bsps/riscv/riscv/include/bsp/riscv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -40,18 +40,26 @@ void *riscv_fdt_get_address(const void *fdt, int node); uint32_t riscv_get_core_frequency(void); +#if RISCV_ENABLE_MPFS_SUPPORT != 0 +extern uint32_t riscv_hart_count; +#else #ifdef RTEMS_SMP extern uint32_t riscv_hart_count; #else #define riscv_hart_count 1 #endif +#endif uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle); -#if RISCV_ENABLE_HTIF_SUPPORT != 0 +#ifdef RISCV_ENABLE_HTIF_SUPPORT void htif_poweroff(void); #endif +#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0 +uint32_t k210_get_frequency(void); +#endif + #ifdef __cplusplus } #endif diff --git a/bsps/riscv/riscv/include/dev/serial/htif.h b/bsps/riscv/riscv/include/dev/serial/htif.h index 4b16d87468..48a3782e31 100644 --- a/bsps/riscv/riscv/include/dev/serial/htif.h +++ b/bsps/riscv/riscv/include/dev/serial/htif.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/riscv/riscv/include/tm27.h b/bsps/riscv/riscv/include/tm27.h index 0dfa7bf628..239e860dc8 100644 --- a/bsps/riscv/riscv/include/tm27.h +++ b/bsps/riscv/riscv/include/tm27.h @@ -1 +1,134 @@ -#include <rtems/tm27-default.h> +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsRISCVGeneric + * + * @brief This header file contains the generic RISC-V tm27 support + * implementation. + */ + +/* + * Copyright (C) 2022 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include <bsp/irq-generic.h> +#include <rtems/score/assert.h> +#include <rtems/score/riscv-utility.h> +#include <rtems/score/percpu.h> + +#define MUST_WAIT_FOR_INTERRUPT 1 + +static bool riscv_tm27_can_use_mtime; + +static rtems_interrupt_entry riscv_tm27_interrupt_entry; + +static inline void Install_tm27_vector( rtems_interrupt_handler handler ) +{ + rtems_vector_number irq; + bool enabled; + + irq = RISCV_INTERRUPT_VECTOR_TIMER; + enabled = false; + rtems_interrupt_vector_is_enabled( irq, &enabled ); + + if ( enabled ) { + irq = RISCV_INTERRUPT_VECTOR_SOFTWARE; + } else { + riscv_tm27_can_use_mtime = true; + } + + rtems_interrupt_entry_initialize( + &riscv_tm27_interrupt_entry, + handler, + NULL, + "tm27" + ); + + (void) rtems_interrupt_entry_install( + irq, + RTEMS_INTERRUPT_SHARED, + &riscv_tm27_interrupt_entry + ); +} + +static inline void Cause_tm27_intr( void ) +{ + if ( riscv_tm27_can_use_mtime ) { + rtems_interrupt_level level; + Per_CPU_Control *cpu_self; + + rtems_interrupt_local_disable( level ); + cpu_self = _Per_CPU_Get(); + cpu_self->cpu_per_cpu.clint_mtimecmp->val_64 = 0; + rtems_interrupt_local_enable( level ); + } else { + (void) rtems_interrupt_raise( RISCV_INTERRUPT_VECTOR_SOFTWARE ); + } +} + +static inline void Clear_tm27_intr( void ) +{ + if ( riscv_tm27_can_use_mtime ) { + rtems_interrupt_level level; + Per_CPU_Control *cpu_self; + + rtems_interrupt_local_disable( level ); + cpu_self = _Per_CPU_Get(); + cpu_self->cpu_per_cpu.clint_mtimecmp->val_64 = UINT64_MAX; + rtems_interrupt_local_enable( level ); + } else { + (void) rtems_interrupt_clear( RISCV_INTERRUPT_VECTOR_SOFTWARE ); + } +} + +static inline void Lower_tm27_intr( void ) +{ + rtems_vector_number irq; + + /* + * This is an ugly hack just to for tm27. The support for nested interrupts + * is currently quite bad on RISC-V. + */ + irq = RISCV_INTERRUPT_VECTOR_SOFTWARE; + + if ( bsp_interrupt_dispatch_table[ irq ] == NULL ) { + _Assert( riscv_tm27_can_use_mtime ); + bsp_interrupt_dispatch_table[ irq ] = &riscv_tm27_interrupt_entry; + (void) rtems_interrupt_vector_enable( irq ); + } + + _ISR_Set_level( 0 ); + (void) rtems_interrupt_raise( irq ); +} + +#endif diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c index 1b632289a6..ada418b7fb 100644 --- a/bsps/riscv/riscv/irq/irq.c +++ b/bsps/riscv/riscv/irq/irq.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -7,7 +9,7 @@ */ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (C) 2018, 2022 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> @@ -34,7 +36,6 @@ * SUCH DAMAGE. */ -#include <bsp/irq.h> #include <bsp/fatal.h> #include <bsp/fdt.h> #include <bsp/irq-generic.h> @@ -42,12 +43,16 @@ #include <rtems/score/percpu.h> #include <rtems/score/riscv-utility.h> +#include <rtems/score/scheduler.h> #include <rtems/score/smpimpl.h> #include <libfdt.h> +static volatile RISCV_PLIC_regs *riscv_plic; + volatile RISCV_CLINT_regs *riscv_clint; +#ifdef RTEMS_SMP /* * The lovely PLIC has an interrupt enable bit per hart for each interrupt * source. This makes the interrupt enable/disable a bit difficult. We have @@ -61,6 +66,7 @@ volatile RISCV_CLINT_regs *riscv_clint; */ static volatile uint32_t * riscv_plic_irq_to_cpu[RISCV_MAXIMUM_EXTERNAL_INTERRUPTS]; +#endif RTEMS_INTERRUPT_LOCK_DEFINE(static, riscv_plic_lock, "PLIC") @@ -73,7 +79,7 @@ void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self) mcause <<= 1; if (mcause == (RISCV_INTERRUPT_TIMER_MACHINE << 1)) { - bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_TIMER); + bsp_interrupt_handler_dispatch_unchecked(RISCV_INTERRUPT_VECTOR_TIMER); } else if (mcause == (RISCV_INTERRUPT_EXTERNAL_MACHINE << 1)) { volatile RISCV_PLIC_hart_regs *plic_hart_regs; uint32_t interrupt_index; @@ -95,7 +101,6 @@ void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self) __asm__ volatile ("fence o, i" : : : "memory"); } } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) { -#ifdef RTEMS_SMP /* * Clear the software interrupt on this processor. Synchronization of * inter-processor interrupts is done via Per_CPU_Control::message in @@ -103,15 +108,76 @@ void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self) */ *cpu_self->cpu_per_cpu.clint_msip = 0; +#ifdef RTEMS_SMP _SMP_Inter_processor_interrupt_handler(cpu_self); + bsp_interrupt_handler_dispatch_unlikely(RISCV_INTERRUPT_VECTOR_SOFTWARE); #else - bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE); + bsp_interrupt_handler_dispatch_unchecked(RISCV_INTERRUPT_VECTOR_SOFTWARE); #endif } else { bsp_fatal(RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION); } } +static void riscv_clint_per_cpu_init( + volatile RISCV_CLINT_regs *clint, + Per_CPU_Control *cpu, + uint32_t index +) +{ + cpu->cpu_per_cpu.clint_msip = &clint->msip[index]; + cpu->cpu_per_cpu.clint_mtimecmp = &clint->mtimecmp[index]; +} + +static void riscv_plic_per_cpu_init( + volatile RISCV_PLIC_regs *plic, + uint32_t enable_register_count, + Per_CPU_Control *cpu, + uint32_t index +) +{ + volatile uint32_t *enable; + uint32_t i; + + plic->harts[index].priority_threshold = 0; + + enable = &plic->enable[index][0]; + cpu->cpu_per_cpu.plic_m_ie = enable; + cpu->cpu_per_cpu.plic_hart_regs = &plic->harts[index]; + + for (i = 0; i < enable_register_count; ++i) { + enable[i] = 0; + } +} + +static void riscv_plic_cpu_0_init( + volatile RISCV_PLIC_regs *plic, + uint32_t interrupt_last +) +{ +#ifdef RTEMS_SMP + Per_CPU_Control *cpu; +#endif + uint32_t i; + +#ifdef RTEMS_SMP + cpu = _Per_CPU_Get_by_index(0); +#endif + + for (i = 1; i <= interrupt_last; ++i) { + plic->priority[i] = 1; +#ifdef RTEMS_SMP + riscv_plic_irq_to_cpu[i - 1] = cpu->cpu_per_cpu.plic_m_ie; +#endif + } + + /* + * External M-mode interrupts on secondary processors are enabled in + * bsp_start_on_secondary_processor(). + */ + set_csr(mie, MIP_MEIP); +} + static void riscv_clint_init(const void *fdt) { volatile RISCV_CLINT_regs *clint; @@ -133,16 +199,37 @@ static void riscv_clint_init(const void *fdt) for (i = 0; i < len; i += 16) { uint32_t hart_index; - Per_CPU_Control *cpu; + uint32_t cpu_index; hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4])); - if (hart_index >= rtems_configuration_get_maximum_processors()) { + +#ifdef RTEMS_SMP + cpu_index = _RISCV_Map_hardid_to_cpu_index(hart_index); + if (cpu_index >= rtems_configuration_get_maximum_processors()) { + continue; + } + + if ( _Scheduler_Initial_assignments[ cpu_index ].scheduler == NULL ) { + /* Skip not configured processor */ + continue; + } +#else + if (hart_index != RISCV_BOOT_HARTID) { continue; } - cpu = _Per_CPU_Get_by_index(hart_index); - cpu->cpu_per_cpu.clint_msip = &clint->msip[i / 16]; - cpu->cpu_per_cpu.clint_mtimecmp = &clint->mtimecmp[i / 16]; + cpu_index = 0; +#endif + + riscv_clint_per_cpu_init( + clint, + _Per_CPU_Get_by_index(cpu_index), + (uint32_t) (i / 16) + ); + +#ifndef RTEMS_SMP + break; +#endif } } @@ -155,20 +242,28 @@ static void riscv_plic_init(const void *fdt) int len; uint32_t interrupt_index; uint32_t ndev; - Per_CPU_Control *cpu; node = fdt_node_offset_by_compatible(fdt, -1, "riscv,plic0"); plic = riscv_fdt_get_address(fdt, node); + if (plic == NULL) { -#if RISCV_ENABLE_HTIF_SUPPORT != 0 +#ifdef RISCV_ENABLE_HTIF_SUPPORT + node = fdt_node_offset_by_compatible(fdt, -1, "ucb,htif0"); + /* Spike platform has HTIF and does not have a PLIC */ - return; + if (node >= 0) { + return; + } else { + bsp_fatal(RISCV_FATAL_NO_PLIC_REG_IN_DEVICE_TREE); + } #else bsp_fatal(RISCV_FATAL_NO_PLIC_REG_IN_DEVICE_TREE); #endif } + riscv_plic = plic; + val = fdt_getprop(fdt, node, "riscv,ndev", &len); if (val == NULL || len != 4) { bsp_fatal(RISCV_FATAL_INVALID_PLIC_NDEV_IN_DEVICE_TREE); @@ -183,36 +278,55 @@ static void riscv_plic_init(const void *fdt) for (i = 0; i < len; i += 8) { uint32_t hart_index; + uint32_t enable_register_count; + uint32_t cpu_index; + + /* + * Each interrupt enable register contains exactly 32 enable bits. + * Calculate the enable register count based on the number of interrupts + * supported by the PLIC. Take the reserved interrupt ID zero into + * account. + */ + enable_register_count = RTEMS_ALIGN_UP(ndev + 1, 32) / 32; hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4])); - if (hart_index >= rtems_configuration_get_maximum_processors()) { + +#ifdef RTEMS_SMP + cpu_index = _RISCV_Map_hardid_to_cpu_index(hart_index); + if (cpu_index >= rtems_configuration_get_maximum_processors()) { continue; } - interrupt_index = fdt32_to_cpu(val[i / 4 + 1]); - if (interrupt_index != RISCV_INTERRUPT_EXTERNAL_MACHINE) { + if ( _Scheduler_Initial_assignments[ cpu_index ].scheduler == NULL ) { + /* Skip not configured processor */ + continue; + } +#else + if (hart_index != RISCV_BOOT_HARTID) { continue; } - plic->harts[i / 8].priority_threshold = 0; + cpu_index = 0; +#endif - cpu = _Per_CPU_Get_by_index(hart_index); - cpu->cpu_per_cpu.plic_hart_regs = &plic->harts[i / 8]; - cpu->cpu_per_cpu.plic_m_ie = &plic->enable[i / 8][0]; - } + interrupt_index = fdt32_to_cpu(val[i / 4 + 1]); + if (interrupt_index != RISCV_INTERRUPT_EXTERNAL_MACHINE) { + continue; + } - cpu = _Per_CPU_Get_by_index(0); + riscv_plic_per_cpu_init( + plic, + enable_register_count, + _Per_CPU_Get_by_index(cpu_index), + (uint32_t) (i / 8) + ); - for (interrupt_index = 1; interrupt_index <= ndev; ++interrupt_index) { - plic->priority[interrupt_index] = 1; - riscv_plic_irq_to_cpu[interrupt_index - 1] = cpu->cpu_per_cpu.plic_m_ie; +#ifndef RTEMS_SMP + break; +#endif } - /* - * External M-mode interrupts on secondary processors are enabled in - * bsp_start_on_secondary_processor(). - */ - set_csr(mie, MIP_MEIP); + riscv_plic_cpu_0_init(plic, ndev); } void bsp_interrupt_facility_initialize(void) @@ -224,11 +338,39 @@ void bsp_interrupt_facility_initialize(void) riscv_plic_init(fdt); } +bool bsp_interrupt_is_valid_vector(rtems_vector_number vector) +{ + /* + * The PLIC interrupt ID of zero is reserved. For example, this ID is used + * to indicate that no interrupt was claimed. + */ + if (vector == RISCV_INTERRUPT_VECTOR_EXTERNAL(0)) { + return false; + } + + return vector < (rtems_vector_number) BSP_INTERRUPT_VECTOR_COUNT; +} + rtems_status_code bsp_interrupt_get_attributes( rtems_vector_number vector, rtems_interrupt_attributes *attributes ) { + attributes->is_maskable = true; + attributes->can_enable = true; + attributes->maybe_enable = true; + attributes->can_disable = true; + attributes->maybe_disable = true; + attributes->can_raise = (vector == RISCV_INTERRUPT_VECTOR_SOFTWARE); + attributes->can_raise_on = attributes->can_raise; + attributes->cleared_by_acknowledge = true; + attributes->can_get_affinity = RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector); + attributes->can_set_affinity = attributes->can_get_affinity; + + if (vector == RISCV_INTERRUPT_VECTOR_SOFTWARE) { + attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL; + } + return RTEMS_SUCCESSFUL; } @@ -239,14 +381,50 @@ rtems_status_code bsp_interrupt_is_pending( { bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); bsp_interrupt_assert(pending != NULL); - *pending = false; - return RTEMS_UNSATISFIED; + + if (RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector)) { + uint32_t interrupt_index; + uint32_t group; + uint32_t bit; + + interrupt_index = RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(vector); + group = interrupt_index / 32; + bit = UINT32_C(1) << (interrupt_index % 32); + *pending = ((riscv_plic->pending[group] & bit) != 0); + return RTEMS_SUCCESSFUL; + } + + if (vector == RISCV_INTERRUPT_VECTOR_TIMER) { + *pending = (read_csr(mip) & MIP_MTIP) != 0; + return RTEMS_SUCCESSFUL; + } + + _Assert(vector == RISCV_INTERRUPT_VECTOR_SOFTWARE); + *pending = (read_csr(mip) & MIP_MSIP) != 0; + return RTEMS_SUCCESSFUL; } -rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) +static inline rtems_status_code riscv_raise_on( + rtems_vector_number vector, + uint32_t cpu_index +) { + Per_CPU_Control *cpu; + bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); - return RTEMS_UNSATISFIED; + + if (vector != RISCV_INTERRUPT_VECTOR_SOFTWARE) { + return RTEMS_UNSATISFIED; + } + + cpu = _Per_CPU_Get_by_index(cpu_index); + *cpu->cpu_per_cpu.clint_msip = 0x1; + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) +{ + return riscv_raise_on(vector, rtems_scheduler_get_processor()); } #if defined(RTEMS_SMP) @@ -255,8 +433,7 @@ rtems_status_code bsp_interrupt_raise_on( uint32_t cpu_index ) { - bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); - return RTEMS_UNSATISFIED; + return riscv_raise_on(vector, cpu_index); } #endif @@ -273,8 +450,53 @@ rtems_status_code bsp_interrupt_vector_is_enabled( { bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); bsp_interrupt_assert(enabled != NULL); - *enabled = false; - return RTEMS_UNSATISFIED; + + if (RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector)) { + uint32_t interrupt_index; + uint32_t group; + uint32_t bit; + Per_CPU_Control *cpu; +#ifdef RTEMS_SMP + uint32_t cpu_max; + uint32_t cpu_index; +#endif + + interrupt_index = RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(vector); + group = interrupt_index / 32; + bit = UINT32_C(1) << (interrupt_index % 32); + +#ifdef RTEMS_SMP + cpu_max = _SMP_Get_processor_maximum(); + + for (cpu_index = 0; cpu_index < cpu_max; ++cpu_index) { + volatile uint32_t *enable; + + cpu = _Per_CPU_Get_by_index(cpu_index); + enable = cpu->cpu_per_cpu.plic_m_ie; + + if (enable != NULL && (enable[group] & bit) != 0) { + *enabled = true; + return RTEMS_SUCCESSFUL; + } + } + + *enabled = false; +#else + cpu = _Per_CPU_Get_by_index(0); + *enabled = (cpu->cpu_per_cpu.plic_m_ie[group] & bit) != 0; +#endif + + return RTEMS_SUCCESSFUL; + } + + if (vector == RISCV_INTERRUPT_VECTOR_TIMER) { + *enabled = (read_csr(mie) & MIP_MTIP) != 0; + return RTEMS_SUCCESSFUL; + } + + _Assert(vector == RISCV_INTERRUPT_VECTOR_SOFTWARE); + *enabled = (read_csr(mie) & MIP_MSIP) != 0; + return RTEMS_SUCCESSFUL; } rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) @@ -283,18 +505,24 @@ rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) if (RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector)) { uint32_t interrupt_index; - volatile uint32_t *enable; uint32_t group; uint32_t bit; rtems_interrupt_lock_context lock_context; + Per_CPU_Control *cpu; +#ifdef RTEMS_SMP + volatile uint32_t *enable; +#endif interrupt_index = RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(vector); - enable = riscv_plic_irq_to_cpu[interrupt_index - 1]; group = interrupt_index / 32; bit = UINT32_C(1) << (interrupt_index % 32); +#ifdef RTEMS_SMP + enable = riscv_plic_irq_to_cpu[interrupt_index - 1]; +#endif rtems_interrupt_lock_acquire(&riscv_plic_lock, &lock_context); +#ifdef RTEMS_SMP if (enable != NULL) { enable[group] |= bit; } else { @@ -304,8 +532,6 @@ rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) cpu_max = _SMP_Get_processor_maximum(); for (cpu_index = 0; cpu_index < cpu_max; ++cpu_index) { - Per_CPU_Control *cpu; - cpu = _Per_CPU_Get_by_index(cpu_index); enable = cpu->cpu_per_cpu.plic_m_ie; @@ -314,10 +540,22 @@ rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) } } } +#else + cpu = _Per_CPU_Get_by_index(0); + cpu->cpu_per_cpu.plic_m_ie[group] |= bit; +#endif rtems_interrupt_lock_release(&riscv_plic_lock, &lock_context); + return RTEMS_SUCCESSFUL; } + if (vector == RISCV_INTERRUPT_VECTOR_TIMER) { + set_csr(mie, MIP_MTIP); + return RTEMS_SUCCESSFUL; + } + + _Assert(vector == RISCV_INTERRUPT_VECTOR_SOFTWARE); + set_csr(mie, MIP_MSIP); return RTEMS_SUCCESSFUL; } @@ -327,18 +565,24 @@ rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) if (RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector)) { uint32_t interrupt_index; - volatile uint32_t *enable; uint32_t group; uint32_t bit; rtems_interrupt_lock_context lock_context; + Per_CPU_Control *cpu; +#ifdef RTEMS_SMP + volatile uint32_t *enable; +#endif interrupt_index = RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(vector); - enable = riscv_plic_irq_to_cpu[interrupt_index - 1]; group = interrupt_index / 32; bit = UINT32_C(1) << (interrupt_index % 32); +#ifdef RTEMS_SMP + enable = riscv_plic_irq_to_cpu[interrupt_index - 1]; +#endif rtems_interrupt_lock_acquire(&riscv_plic_lock, &lock_context); +#ifdef RTEMS_SMP if (enable != NULL) { enable[group] &= ~bit; } else { @@ -348,8 +592,6 @@ rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) cpu_max = _SMP_Get_processor_maximum(); for (cpu_index = 0; cpu_index < cpu_max; ++cpu_index) { - Per_CPU_Control *cpu; - cpu = _Per_CPU_Get_by_index(cpu_index); enable = cpu->cpu_per_cpu.plic_m_ie; @@ -358,13 +600,26 @@ rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) } } } +#else + cpu = _Per_CPU_Get_by_index(0); + cpu->cpu_per_cpu.plic_m_ie[group] &= ~bit; +#endif rtems_interrupt_lock_release(&riscv_plic_lock, &lock_context); + return RTEMS_SUCCESSFUL; } + if (vector == RISCV_INTERRUPT_VECTOR_TIMER) { + clear_csr(mie, MIP_MTIP); + return RTEMS_SUCCESSFUL; + } + + _Assert(vector == RISCV_INTERRUPT_VECTOR_SOFTWARE); + clear_csr(mie, MIP_MSIP); return RTEMS_SUCCESSFUL; } +#ifdef RTEMS_SMP rtems_status_code bsp_interrupt_set_affinity( rtems_vector_number vector, const Processor_mask *affinity @@ -393,7 +648,7 @@ rtems_status_code bsp_interrupt_set_affinity( return RTEMS_SUCCESSFUL; } - bsp_fatal(RISCV_FATAL_INVALID_INTERRUPT_AFFINITY); + return RTEMS_INVALID_NUMBER; } return RTEMS_UNSATISFIED; @@ -404,8 +659,6 @@ rtems_status_code bsp_interrupt_get_affinity( Processor_mask *affinity ) { - _Processor_mask_Zero(affinity); - if (RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector)) { uint32_t interrupt_index; volatile uint32_t *enable; @@ -432,7 +685,10 @@ rtems_status_code bsp_interrupt_get_affinity( } else { _Processor_mask_Assign(affinity, _SMP_Get_online_processors()); } + + return RTEMS_SUCCESSFUL; } - return RTEMS_SUCCESSFUL; + return RTEMS_UNSATISFIED; } +#endif diff --git a/bsps/riscv/riscv/start/bsp_fatal_halt.c b/bsps/riscv/riscv/start/bsp_fatal_halt.c index d9708661a7..06fffad6df 100644 --- a/bsps/riscv/riscv/start/bsp_fatal_halt.c +++ b/bsps/riscv/riscv/start/bsp_fatal_halt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> @@ -38,11 +38,20 @@ void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ) int node; volatile uint32_t *sifive_test; -#if RISCV_ENABLE_HTIF_SUPPORT != 0 - htif_poweroff(); + fdt = bsp_fdt_get(); + +#ifdef RISCV_ENABLE_HTIF_SUPPORT + node = fdt_node_offset_by_compatible(fdt, -1, "ucb,htif0"); + + if (node >= 0) { + htif_poweroff(); + } +#endif + +#if RISCV_ENABLE_MPFS_SUPPORT != 0 + for(;;); #endif - fdt = bsp_fdt_get(); node = fdt_node_offset_by_compatible(fdt, -1, "sifive,test0"); sifive_test = riscv_fdt_get_address(fdt, node); diff --git a/bsps/riscv/riscv/start/bspsmp.c b/bsps/riscv/riscv/start/bspsmp.c index 4f1b3c93cc..a6884299a0 100644 --- a/bsps/riscv/riscv/start/bspsmp.c +++ b/bsps/riscv/riscv/start/bspsmp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -36,10 +36,7 @@ void bsp_start_on_secondary_processor(Per_CPU_Control *cpu_self) cpu_index_self = _Per_CPU_Get_index(cpu_self); - if ( - cpu_index_self < rtems_configuration_get_maximum_processors() - && _SMP_Should_start_processor(cpu_index_self) - ) { + if (_SMP_Should_start_processor(cpu_index_self)) { set_csr(mie, MIP_MSIP | MIP_MEIP); _SMP_Start_multitasking_on_secondary_processor(cpu_self); } else { diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c index d33e9965f8..d65741b13f 100644 --- a/bsps/riscv/riscv/start/bspstart.c +++ b/bsps/riscv/riscv/start/bspstart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -74,6 +74,10 @@ void *riscv_fdt_get_address(const void *fdt, int node) return (void *)(uintptr_t) addr; } +#if RISCV_ENABLE_MPFS_SUPPORT != 0 +uint32_t riscv_hart_count; +static uint32_t riscv_hart_phandles[5]; +#else #ifdef RTEMS_SMP uint32_t riscv_hart_count; @@ -81,6 +85,7 @@ static uint32_t riscv_hart_phandles[CPU_MAXIMUM_PROCESSORS]; #else static uint32_t riscv_hart_phandles[1]; #endif +#endif static void riscv_find_harts(void) { @@ -106,6 +111,14 @@ static void riscv_find_harts(void) hart_index = fdt32_to_cpu(val[0]); +#if RISCV_BOOT_HARTID != 0 + if (hart_index < RISCV_BOOT_HARTID) { + continue; + } + + hart_index -= RISCV_BOOT_HARTID; +#endif + if (hart_index >= RTEMS_ARRAY_SIZE(riscv_hart_phandles)) { continue; } @@ -146,9 +159,13 @@ static void riscv_find_harts(void) riscv_hart_phandles[hart_index] = phandle; } +#if RISCV_ENABLE_MPFS_SUPPORT != 0 + riscv_hart_count = max_hart_index + 1; +#else #ifdef RTEMS_SMP riscv_hart_count = max_hart_index + 1; #endif +#endif } uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle) @@ -157,7 +174,7 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle) for (hart_index = 0; hart_index < riscv_hart_count; ++hart_index) { if (riscv_hart_phandles[hart_index] == phandle) { - return hart_index; + return hart_index + RISCV_BOOT_HARTID; } } @@ -166,7 +183,7 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle) static uint32_t get_core_frequency(void) { -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 +#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 || RISCV_ENABLE_MPFS_SUPPORT != 0 uint32_t node; const char *fdt; const char *tlclk; @@ -177,7 +194,13 @@ static uint32_t get_core_frequency(void) node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock"); tlclk = fdt_getprop(fdt, node, "clock-output-names", &len); - if (strcmp(tlclk,"tlclk") != 0) { +#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 + if (strcmp(tlclk,"tlclk") != 0) +#endif +#if RISCV_ENABLE_MPFS_SUPPORT != 0 + if (strcmp(tlclk,"msspllclk") != 0) +#endif + { bsp_fatal(RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE); } @@ -186,7 +209,16 @@ static uint32_t get_core_frequency(void) return fdt32_to_cpu(*val); } #endif + +#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0 + uint32_t cpu_clock; + + cpu_clock = k210_get_frequency(); + return cpu_clock; +#else return 0; +#endif + } uint32_t riscv_get_core_frequency(void) @@ -197,9 +229,43 @@ uint32_t riscv_get_core_frequency(void) uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells) { (void) icells; - return intr[0]; + return RISCV_INTERRUPT_VECTOR_EXTERNAL(intr[0]); } +#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0 +uint32_t k210_get_frequency(void) +{ + k210_sysctl_t *sysctl = (k210_sysctl_t *)K210_SYSCTL_BASE; + uint32_t cpu_clock = 0; + uint32_t clk_freq; + uint32_t pll0, nr, nf, od; + uint32_t node; + const char *fdt; + const fdt32_t *val; + int len; + + fdt = bsp_fdt_get(); + node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock"); + val = fdt_getprop(fdt, node, "clock-frequency", &len); + if (val != NULL && len == 4) { + clk_freq = fdt32_to_cpu(*val); + + if (CLKSEL0_ACLK_SEL(sysctl->clk_sel0) == 1) { + /* PLL0 selected */ + pll0 = sysctl->pll0; + nr = PLL_CLK_R(pll0) + 1; + nf = PLL_CLK_F(pll0) + 1; + od = PLL_CLK_OD(pll0) + 1; + cpu_clock = (clk_freq / nr * nf / od)/2; + } else { + /* OSC selected */ + cpu_clock = clk_freq; + } + } + return cpu_clock; +} +#endif + void bsp_start(void) { riscv_find_harts(); diff --git a/bsps/riscv/shared/doxygen.h b/bsps/riscv/shared/doxygen.h index dc95013d05..1f206ad638 100644 --- a/bsps/riscv/shared/doxygen.h +++ b/bsps/riscv/shared/doxygen.h @@ -1,4 +1,12 @@ /** + * @file + * + * @ingroup RTEMSImplDoxygen + * + * @brief This header file defines riscv-specific groups. + */ + +/** * @defgroup RTEMSBSPsRISCV RISC-V * * @ingroup RTEMSBSPs diff --git a/bsps/riscv/shared/start/bspgetworkarea.c b/bsps/riscv/shared/start/bspgetworkarea.c new file mode 100644 index 0000000000..d802ffea42 --- /dev/null +++ b/bsps/riscv/shared/start/bspgetworkarea.c @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @brief BSP specific initialization support routines + * + */ + +/* + * COPYRIGHT (c) 1989-2020. + * On-Line Applications Research Corporation (OAR). + * Cobham Gaisler AB. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp.h> +#include <bsp/fdt.h> + +#include <rtems/sysinit.h> + +#include <libfdt.h> + +/* + * These are provided by the linkcmds for ALL of the BSPs which use this file. + */ +extern char WorkAreaBase[]; +extern char RamEnd[]; + +static Memory_Area _Memory_Areas[ 1 ]; + +static const char memory_path[] = "/memory"; + +static void* get_end_of_memory_from_fdt(void) +{ + const void *fdt; + const void *val; + int node; + int parent; + int ac; + int sc; + int len; + uintptr_t start; + uintptr_t size; + + fdt = bsp_fdt_get(); + + node = fdt_path_offset_namelen( + fdt, + memory_path, + (int) sizeof(memory_path) - 1 + ); + + if (node < 0) { + return NULL; + } + + parent = fdt_parent_offset(fdt, node); + if (parent < 0) { + return NULL; + } + + ac = fdt_address_cells(fdt, parent); + if (ac != 1 && ac != 2) { + return NULL; + } + + sc = fdt_size_cells(fdt, parent); + if (sc != 1 && sc != 2) { + return NULL; + } + + if (sc > ac) { + return NULL; + } + + val = fdt_getprop(fdt, node, "reg", &len); + if (len < sc + ac) { + return NULL; + } + + if (ac == 1) { + start = fdt32_to_cpu(((fdt32_t *)val)[0]); + size = fdt32_to_cpu(((fdt32_t *)val)[1]); + } + + if (ac == 2) { + start = fdt64_to_cpu(((fdt64_t *)val)[0]); + + if (sc == 1) + size = fdt32_to_cpu(((fdt32_t *)(val+8))[0]); + else + size = fdt64_to_cpu(((fdt64_t *)val)[1]); + } + + return (void*) (start + size); +} + +static void bsp_memory_initialize( void ) +{ + void *end; + + /* get end of memory from the "/memory" node in the fdt */ + end = get_end_of_memory_from_fdt(); + if (end == NULL) { + /* fall back to linker symbol if "/memory" node not found or invalid */ + end = RamEnd; + } + _Memory_Initialize( &_Memory_Areas[ 0 ], WorkAreaBase, end ); +} + +RTEMS_SYSINIT_ITEM( + bsp_memory_initialize, + RTEMS_SYSINIT_MEMORY, + RTEMS_SYSINIT_ORDER_MIDDLE +); + +static const Memory_Information _Memory_Information = + MEMORY_INFORMATION_INITIALIZER( _Memory_Areas ); + +const Memory_Information *_Memory_Get( void ) +{ + return &_Memory_Information; +} diff --git a/bsps/riscv/shared/start/start.S b/bsps/riscv/shared/start/start.S index 3702f8ac2f..f31d89335c 100644 --- a/bsps/riscv/shared/start/start.S +++ b/bsps/riscv/shared/start/start.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> @@ -40,6 +40,7 @@ PUBLIC(_start) .section .bsp_start_text, "wax", @progbits .align 2 .option arch, +zicsr + .option norelax TYPE_FUNC(_start) SYM(_start): @@ -65,6 +66,17 @@ SYM(_start): LADDR sp, _ISR_Stack_area_begin LADDR t2, _ISR_Stack_size csrr s0, mhartid + li t3, RISCV_BOOT_HARTID + sub s0, s0, t3 + + /* + * Check that this is a configured processor. If not, then there is + * not much that can be done since we do not have a stack available for + * this processor. Just loop forever in this case. + */ + LREG t3, _SMP_Processor_configured_maximum + bgeu s0, t3, .Lwfi + LADDR t0, _Per_CPU_Information slli t1, s0, PER_CPU_CONTROL_SIZE_LOG2 add s1, t0, t1 @@ -97,6 +109,9 @@ SYM(_start): tail boot_card #ifdef RTEMS_SMP +.Lwfi: + wfi + j .Lwfi .Lstart_on_secondary_processor: @@ -128,9 +143,15 @@ SYM(_start): mv a0, s1 call bsp_start_on_secondary_processor + .section .bsp_start_data, "aw" + + .type .Lsecondary_processor_go, @object + #if __riscv_xlen == 32 + .size .Lsecondary_processor_go, 4 .align 2 #elif __riscv_xlen == 64 + .size .Lsecondary_processor_go, 8 .align 3 #endif |