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-rw-r--r--bsps/riscv/riscv/start/bspstart.c76
1 files changed, 71 insertions, 5 deletions
diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c
index d33e9965f8..d65741b13f 100644
--- a/bsps/riscv/riscv/start/bspstart.c
+++ b/bsps/riscv/riscv/start/bspstart.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -74,6 +74,10 @@ void *riscv_fdt_get_address(const void *fdt, int node)
return (void *)(uintptr_t) addr;
}
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+uint32_t riscv_hart_count;
+static uint32_t riscv_hart_phandles[5];
+#else
#ifdef RTEMS_SMP
uint32_t riscv_hart_count;
@@ -81,6 +85,7 @@ static uint32_t riscv_hart_phandles[CPU_MAXIMUM_PROCESSORS];
#else
static uint32_t riscv_hart_phandles[1];
#endif
+#endif
static void riscv_find_harts(void)
{
@@ -106,6 +111,14 @@ static void riscv_find_harts(void)
hart_index = fdt32_to_cpu(val[0]);
+#if RISCV_BOOT_HARTID != 0
+ if (hart_index < RISCV_BOOT_HARTID) {
+ continue;
+ }
+
+ hart_index -= RISCV_BOOT_HARTID;
+#endif
+
if (hart_index >= RTEMS_ARRAY_SIZE(riscv_hart_phandles)) {
continue;
}
@@ -146,9 +159,13 @@ static void riscv_find_harts(void)
riscv_hart_phandles[hart_index] = phandle;
}
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+ riscv_hart_count = max_hart_index + 1;
+#else
#ifdef RTEMS_SMP
riscv_hart_count = max_hart_index + 1;
#endif
+#endif
}
uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle)
@@ -157,7 +174,7 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle)
for (hart_index = 0; hart_index < riscv_hart_count; ++hart_index) {
if (riscv_hart_phandles[hart_index] == phandle) {
- return hart_index;
+ return hart_index + RISCV_BOOT_HARTID;
}
}
@@ -166,7 +183,7 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle)
static uint32_t get_core_frequency(void)
{
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 || RISCV_ENABLE_MPFS_SUPPORT != 0
uint32_t node;
const char *fdt;
const char *tlclk;
@@ -177,7 +194,13 @@ static uint32_t get_core_frequency(void)
node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock");
tlclk = fdt_getprop(fdt, node, "clock-output-names", &len);
- if (strcmp(tlclk,"tlclk") != 0) {
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+ if (strcmp(tlclk,"tlclk") != 0)
+#endif
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+ if (strcmp(tlclk,"msspllclk") != 0)
+#endif
+ {
bsp_fatal(RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE);
}
@@ -186,7 +209,16 @@ static uint32_t get_core_frequency(void)
return fdt32_to_cpu(*val);
}
#endif
+
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+ uint32_t cpu_clock;
+
+ cpu_clock = k210_get_frequency();
+ return cpu_clock;
+#else
return 0;
+#endif
+
}
uint32_t riscv_get_core_frequency(void)
@@ -197,9 +229,43 @@ uint32_t riscv_get_core_frequency(void)
uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
{
(void) icells;
- return intr[0];
+ return RISCV_INTERRUPT_VECTOR_EXTERNAL(intr[0]);
}
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+uint32_t k210_get_frequency(void)
+{
+ k210_sysctl_t *sysctl = (k210_sysctl_t *)K210_SYSCTL_BASE;
+ uint32_t cpu_clock = 0;
+ uint32_t clk_freq;
+ uint32_t pll0, nr, nf, od;
+ uint32_t node;
+ const char *fdt;
+ const fdt32_t *val;
+ int len;
+
+ fdt = bsp_fdt_get();
+ node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock");
+ val = fdt_getprop(fdt, node, "clock-frequency", &len);
+ if (val != NULL && len == 4) {
+ clk_freq = fdt32_to_cpu(*val);
+
+ if (CLKSEL0_ACLK_SEL(sysctl->clk_sel0) == 1) {
+ /* PLL0 selected */
+ pll0 = sysctl->pll0;
+ nr = PLL_CLK_R(pll0) + 1;
+ nf = PLL_CLK_F(pll0) + 1;
+ od = PLL_CLK_OD(pll0) + 1;
+ cpu_clock = (clk_freq / nr * nf / od)/2;
+ } else {
+ /* OSC selected */
+ cpu_clock = clk_freq;
+ }
+ }
+ return cpu_clock;
+}
+#endif
+
void bsp_start(void)
{
riscv_find_harts();