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Diffstat (limited to 'bsps/include')
65 files changed, 12959 insertions, 0 deletions
diff --git a/bsps/include/bsp/VME.h b/bsps/include/bsp/VME.h new file mode 100644 index 0000000000..bdaa45870e --- /dev/null +++ b/bsps/include/bsp/VME.h @@ -0,0 +1,133 @@ +/** + * @file + * + * @ingroup shared_vme + * + * @brief SVGM et al. BSP's VME support + */ + +#ifndef RTEMS_BSP_VME_API_H +#define RTEMS_BSP_VME_API_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2002, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include <stdio.h> + +/* address modifiers & friends */ +#include <bsp/vme_am_defs.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_vme VME related declarations + * + * @ingroup shared_vmeuniverse + * + * @brief BSP-specific configuration routine; sets up + * VME windows and installs the VME interrupt manager. + */ + +void BSP_vme_config(); + +/* translate through host bridge and vme master window of vme bridge */ +int +BSP_vme2local_adrs(unsigned long am, unsigned long vmeaddr, unsigned long *plocaladdr); + +/* how a CPU address is mapped to the VME bus (if at all) */ +int +BSP_local2vme_adrs(unsigned long am, unsigned long localaddr, unsigned long *pvmeaddr); + +/* interrupt handlers and levels */ +typedef void (*BSP_VME_ISR_t)(void *usrArg, unsigned long vector); + +int +BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *arg); +int +BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *arg); + +/* retrieve the currently installed ISR for a given vector */ +BSP_VME_ISR_t +BSP_getVME_isr(unsigned long vector, void **parg); + +int +BSP_enableVME_int_lvl(unsigned int level); + +int +BSP_disableVME_int_lvl(unsigned int level); + +int +BSP_VMEOutboundPortCfg( + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long pci_address, + unsigned long size); + +int +BSP_VMEInboundPortCfg( + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long pci_address, + unsigned long size); + +void +BSP_VMEOutboundPortsShow(FILE *f); + +void +BSP_VMEInboundPortsShow(FILE *f); + +/* Assert VME SYSRESET */ +void +BSP_VMEResetBus(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/VMEDMA.h b/bsps/include/bsp/VMEDMA.h new file mode 100644 index 0000000000..636f6d365c --- /dev/null +++ b/bsps/include/bsp/VMEDMA.h @@ -0,0 +1,309 @@ +/** + * @file + * + * @ingroup shared_vmedma + * + * @brief Public interface of DMA routines + */ + +#ifndef BSP_VME_DMA_H +#define BSP_VME_DMA_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2006, 2007 + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_vmedma VMEDMA Support + * + * @ingroup shared_vmeuniverse + * + * @brief VMEDMA Support Package + */ + + +/* NOTE: Access to DMA Channels is *not* protected / thread-safe. + * It is the responsability of the user to provide appropriate + * locking/serialization. + */ + +/* Simple abstraction of DMA controller setup / bus utilization: */ + +/* Since VME is the bottleneck, the settings for PCI are always + * chosen aggressively. + */ + + +/* Optimize for throughput; accept longer latencies: + * Choose a large block size (1k) and immediately re-request + * the bus at block boundaries. + */ +#define BSP_VMEDMA_OPT_THROUGHPUT 1 +/* Optimize for latency, accept throughput penalty: + * Choose a small block size (32b) and immediately re-request + * the bus at block boundaries. + */ +#define BSP_VMEDMA_OPT_LOWLATENCY 2 + +/* Optimize for bus sharing with other devices: + * Choose relatively small block size (128) and back off for 64us + * at each block boundary. + */ +#define BSP_VMEDMA_OPT_SHAREDBUS 3 + +/* Choose bridge default/reset configuration: + * (see manual) + */ +#define BSP_VMEDMA_OPT_DEFAULT 4 + +/* Provide custom configuration pass pointer to array + * with as many 32-bit words the particular bridge chip + * expects. + */ +#define BSP_VMEDMA_OPT_CUSTOM 5 + +/* VME Transfer modes */ + +/* Bitwise OR of the VME address-modifier/transfer-type + * with driver specific (no standard AM code for 2eVME and + * 2eSST defined) and optional special flags (see below) + */ + +/* Additional qualifiers: */ + +/* Don't increment VME address */ +#define BSP_VMEDMA_MODE_NOINC_VME (1<<20) +/* Don't increment PCI address */ +#define BSP_VMEDMA_MODE_NOINC_PCI (1<<21) + +/* Direction */ +#define BSP_VMEDMA_MODE_PCI2VME (1<<31) + +typedef void *BSP_VMEDmaListDescriptor; + +/* Program the device for the selected mode; + * + * 'bus_mode': one of the ...VMEDMA_OPT... choices + * listed above. + * 'xfer_mode': VME address-modifier optionally ORed with + * ...VMEDMA_MODE... bits listed above. + * 'custom': (only used if bus_mode is VMEDMA_OPT_CUSTOM) + * pointer to a list of setup parameters (chip-driver + * specific). + * + * RETURNS: 0 on success, nonzero on error (mode or channel + * unsupported). + * + * NOTES: The setup is preserved across multiple DMA transfers. + * It is the responsibility of the driver to reprogram + * the setup if the hardware does not preserve it. + * However - in linked list mode, some fields may be + * read from the list descriptors. + * + * Usually this routine must be used even in linked-list + * mode to program the 'bus_mode'. + * + * Direction of transfer is specified by a bit in the + * 'xfer_mode' (BSP_VMEDMA_MODE_PCI2VME). + */ +int +BSP_VMEDmaSetup(int channel, uint32_t bus_mode, uint32_t xfer_mode, void *custom_setup); + +/* Start direct (not linked-list) transfer. + * + * RETURNS: 0 on success, nonzero on failure + */ +int +BSP_VMEDmaStart(int channel, uint32_t pci_addr, uint32_t vme_addr, uint32_t n_bytes); + +/* Transfer status/result */ +#define BSP_VMEDMA_STATUS_OK 0 +/* Unsupported channel */ +#define BSP_VMEDMA_STATUS_UNSUP (-1) +/* Bus error on VME */ +#define BSP_VMEDMA_STATUS_BERR_VME 1 +/* Bus error on PCI */ +#define BSP_VMEDMA_STATUS_BERR_PCI 2 +/* Channel busy */ +#define BSP_VMEDMA_STATUS_BUSY 3 +/* Setup/programming error */ +#define BSP_VMEDMA_STATUS_PERR 4 +/* Other/unspecified error */ +#define BSP_VMEDMA_STATUS_OERR 5 + +/* Retrieve status of last transfer. + * + * RETURNS: 0 if the transfer was successful, + * nonzero on error (e.g., one of the + * values defined above). + * + * NOTE: Driver is allowed to pass other, + * device specific codes + */ + +uint32_t +BSP_VMEDmaStatus(int channel); + +/* + * Hook a callback (executed from ISR context) to DMA interrupt and + * enable it. + * If called with NULL callback then an existing callback is removed + * and the interrupt disabled. + * + * RETURNS: 0 on success, nonzero on failure (IRQ in use, unsupported + * channel). + */ +typedef void (*BSP_VMEDmaIRQCallback)(void *usr_arg); + +int +BSP_VMEDmaInstallISR(int channel, BSP_VMEDmaIRQCallback cb, void *usr_arg); + +/* + * DMA List operations. + * + * Note that the list is totally unprotected, i.e., the user is + * responsible for maintaining coherency against concurrent + * access by multiple threads or hardware. + * We assume the user builds/updates a list, hands it over to + * the hardware (list start command) and leaves it alone until + * the DMA controller is done with it. + */ + +/* Modify a list entry. If the list element pointer is NULL + * then a new list element is allocated. + * Only the fields with its corresponding bit set in the mask + * argument are touched. + * + * RETURNS: 'd' or newly allocated descriptor or NULL (no memory, + * or invalid setup). + */ +#define BSP_VMEDMA_MSK_ATTR (1<<0) +#define BSP_VMEDMA_MSK_PCIA (1<<1) +#define BSP_VMEDMA_MSK_VMEA (1<<2) +#define BSP_VMEDMA_MSK_BCNT (1<<3) +#define BSP_VMEDMA_MSK_ALL (0xf) +BSP_VMEDmaListDescriptor +BSP_VMEDmaListDescriptorSetup( + BSP_VMEDmaListDescriptor d, + uint32_t attr_mask, + uint32_t xfer_mode, + uint32_t pci_addr, + uint32_t vme_addr, + uint32_t n_bytes); + +/* De-allocate a list descriptor previously obtained by + * BSP_VMEDmaListDescriptorSetup(0,...); + * + * RETURNS: 0 on success, nonzero on failure (d currently on a list) + */ +int +BSP_VMEDmaListDescriptorDestroy(BSP_VMEDmaListDescriptor d); + +/* Traverse a list of descriptors and destroy all elements */ +int +BSP_VMEDmaListDestroy(BSP_VMEDmaListDescriptor anchor); + +/* Enqueue a list descriptor 'd' after 'tail' + * + * If 'tail' is NULL then 'd' is removed from + * the list it is currently on. + * + * RETURNS: 0 on success, nonzero if 'd' is already + * on a list (enqueue) or if it is not currently + * on a list (dequeue). + * + * NOTE: it is obviously the user's responsibility to update + * list queue/tail pointers when changing the + * structure of the list. + */ +int +BSP_VMEDmaListDescriptorEnq( + BSP_VMEDmaListDescriptor tail, + BSP_VMEDmaListDescriptor d); + +/* Obtain next and previous descriptors */ +BSP_VMEDmaListDescriptor +BSP_VMEDmaListDescriptorNext(BSP_VMEDmaListDescriptor d); + +BSP_VMEDmaListDescriptor +BSP_VMEDmaListDescriptorPrev(BSP_VMEDmaListDescriptor d); + +/* Set and get a 'usrData' pointer in the descriptor */ +void +BSP_VMEDmaListDescriptorSetUsr(BSP_VMEDmaListDescriptor d, void *usrData); + +void * +BSP_VMEDmaListDescriptorGetUsr(BSP_VMEDmaListDescriptor d); + +/* Refresh an entire list. Some DMA controllers modify certain + * fields (e.g., byte count) and this command restores the original + * setup. + */ + +int +BSP_VMEDmaListRefresh(BSP_VMEDmaListDescriptor anchor); + +/* Start linked-list operation. + * + * RETURNS: 0 on success, nonzero on failure + */ +int +BSP_VMEDmaListStart(int channel, BSP_VMEDmaListDescriptor list); + +#ifdef DEBUG +void +BSP_VMEDmaListDump(BSP_VMEDmaListDescriptor p); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/bootcard.h b/bsps/include/bsp/bootcard.h new file mode 100644 index 0000000000..aaac42e8e2 --- /dev/null +++ b/bsps/include/bsp/bootcard.h @@ -0,0 +1,188 @@ +/** + * @file + * + * @ingroup bsp_bootcard + * + * @brief Standard system startup. + */ + +/* + * Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_BOOTCARD_H +#define LIBBSP_SHARED_BOOTCARD_H + +#include <string.h> + +#include <rtems/config.h> +#include <rtems/bspIo.h> +#include <rtems/malloc.h> +#include <rtems/score/wkspace.h> + +#include <bspopts.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup shared_bootcard Bootcard + * + * @ingroup bsp_shared + * + * @brief Standard system startup. + * + * @{ + */ + +/** + * @brief Global pointer to the command line of boot_card(). + */ +extern const char *bsp_boot_cmdline; + +void bsp_start(void); + +void bsp_predriver_hook(void); + +void bsp_reset(void); + +/** + * @brief Standard system initialization procedure. + * + * You may pass a command line in @a cmdline. It is later available via the + * global @ref bsp_boot_cmdline variable. + * + * This is the C entry point for ALL RTEMS BSPs. It is invoked from the + * assembly language initialization file usually called @c start.S which does + * the basic CPU setup (stack, C runtime environment, zero BSS, load other + * sections) and calls afterwards boot_card(). The boot card function provides + * the framework for the BSP initialization sequence. For the basic flow of + * initialization see RTEMS C User's Guide, Initialization Manager. + * + * This style of initialization ensures that the C++ global constructors are + * executed after RTEMS is initialized. + */ +void boot_card(const char *cmdline) RTEMS_NO_RETURN; + +#ifdef CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK + /** + * @brief Gives the BSP a chance to reduce the work area size with sbrk() + * adding more later. + * + * bsp_sbrk_init() may reduce the work area size passed in. The routine + * returns the 'sbrk_amount' to be used when extending the heap. Note that + * the return value may be zero. + * + * In case the @a area size is altered, then the remaining size of the + * @a area must be greater than or equal to @a min_size. + */ + ptrdiff_t bsp_sbrk_init(Heap_Area *area, uintptr_t min_size); +#endif + +static inline void bsp_work_area_initialize_default( + void *area_begin, + uintptr_t area_size +) +{ + Heap_Area area = { + .begin = area_begin, + .size = area_size + }; + + #if BSP_DIRTY_MEMORY == 1 + memset(area.begin, 0xCF, area.size); + #endif + + #ifdef CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK + { + uintptr_t overhead = _Heap_Area_overhead(CPU_HEAP_ALIGNMENT); + uintptr_t work_space_size = rtems_configuration_get_work_space_size(); + ptrdiff_t sbrk_amount = bsp_sbrk_init( + &area, + work_space_size + + overhead + + (rtems_configuration_get_unified_work_area() ? 0 : overhead) + ); + + rtems_heap_set_sbrk_amount(sbrk_amount); + } + #endif + + /* + * The following may be helpful in debugging what goes wrong when + * you are allocating the Work Area in a new BSP. + */ + #ifdef BSP_GET_WORK_AREA_DEBUG + { + void *sp = __builtin_frame_address(0); + void *end = (char *) area.begin + area.size; + printk( + "work_area_start = 0x%p\n" + "work_area_size = %lu 0x%08lx\n" + "end = 0x%p\n" + "current stack pointer = 0x%p%s\n", + area.begin, + (unsigned long) area.size, /* decimal */ + (unsigned long) area.size, /* hexadecimal */ + end, + sp, + (uintptr_t) sp >= (uintptr_t) area.begin + && (uintptr_t) sp <= (uintptr_t) end ? + " OVERLAPS!" : "" + ); + } + #endif + + _Workspace_Handler_initialization(&area, 1, NULL); + + #ifdef BSP_GET_WORK_AREA_DEBUG + printk( + "heap_start = 0x%p\n" + "heap_size = %lu\n", + area.begin, + (unsigned long) area.size + ); + #endif + + RTEMS_Malloc_Initialize(&area, 1, NULL); +} + +static inline void bsp_work_area_initialize_with_table( + Heap_Area *areas, + size_t area_count +) +{ + _Workspace_Handler_initialization(areas, area_count, _Heap_Extend); + RTEMS_Malloc_Initialize(areas, area_count, _Heap_Extend); +} + +void bsp_work_area_initialize(void); + +/** + * @brief Standard start routine for secondary processors. + * + * This function is usually called by low-level startup code of secondary + * processors or boot loaders starting a secondary processor. The final step + * of this function is a call to + * _SMP_Start_multitasking_on_secondary_processor(). + */ +void bsp_start_on_secondary_processor(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_BOOTCARD_H */ diff --git a/bsps/include/bsp/bspVmeDmaList.h b/bsps/include/bsp/bspVmeDmaList.h new file mode 100644 index 0000000000..414afab5c9 --- /dev/null +++ b/bsps/include/bsp/bspVmeDmaList.h @@ -0,0 +1,140 @@ +/** + * @file + * + * @ingroup shared_bspvmedmalist + * + * @brief This header should only be used inside a BSP + * chosing to use bspVmeDmaList for implementing VMEDMA.h + */ + +#ifndef BSP_VME_DMA_LIST_H +#define BSP_VME_DMA_LIST_H + + + +/* + * The bspVmeDmaList utility implements part of the API defined by + * 'VMEDMA.h' namely all 'VMEDmaListDescriptor' related entry points: + * + * BSP_VMEDmaListDescriptorDestroy(), + * BSP_VMEDmaListDestroy(), + * BSP_VMEDmaListDescriptorEnq(), + * BSP_VMEDmaListDescriptorNext(), + * BSP_VMEDmaListDescriptorPrev(), + * BSP_VMEDmaListDescriptorSetUsr(), + * BSP_VMEDmaListDescriptorGetUsr(), + * BSP_VMEDmaListRefresh() + * + * Also, it provides helper routines to assist BSPs with implementing + * + * BSP_VMEDmaListDescriptorSetup() + * + * and + * + * BSP_VMEDmaListStart() + * + * by providing + * + * BSP_VMEDmaListDescriptorNewTool(), + * BSP_VMEDmaListDescriptorSetupTool(), + * + * and + * + * BSP_VMEDmaListDescriptorStartTool() + */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2006, 2007 + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ +#include <stdint.h> + +#include <bsp/VMEDMA.h> + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct VMEDmaListNodeRec_ *VMEDmaListNode; + +typedef struct VMEDmaListClassRec_ *VMEDmaListClass; + +/** + * @defgroup shared_bspvmedmalist Create and setup a new descriptor. + * + * @ingroup shared_vmeuniverse + * + * @brief The BSP must supply the appropriate controller class. + */ + +VMEDmaListNode +BSP_VMEDmaListDescriptorNewTool( + VMEDmaListClass pc, + uint32_t attr_mask, + uint32_t xfer_mode, + uint32_t pci_addr, + uint32_t vme_addr, + uint32_t n_bytes); + +/* Setup an existing descriptor */ +VMEDmaListNode +BSP_VMEDmaListDescriptorSetupTool( + VMEDmaListNode n, + uint32_t attr_mask, + uint32_t xfer_mode, + uint32_t pci_addr, + uint32_t vme_addr, + uint32_t n_bytes); + + +/* Start a list DMA transfer on 'controller'. The 'controller' information + * must be provided by the BSP. + */ +int +BSP_VMEDmaListDescriptorStartTool(volatile void *controller, int channel, VMEDmaListNode n); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/console-polled.h b/bsps/include/bsp/console-polled.h new file mode 100644 index 0000000000..09a99c30cb --- /dev/null +++ b/bsps/include/bsp/console-polled.h @@ -0,0 +1,43 @@ +/** + * @file + * + * @ingroup Console + * + * This file defines the interfaces between the single port + * polled console framework and the BSP. + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __BSP_CONSOLE_POLLED_h +#define __BSP_CONSOLE_POLLED_h + +/** + * This method polls the specified character @a ch to the specified + * console @a port. + * + * @param[in] port is the output port + * @param[in] ch is the character to print + */ +void console_outbyte_polled(int port, char ch); + +/** + * This method polls the specified @a port for an input character. + * console @a port. + * + * @param[in] port is the input port + * + * @return This method returns the character read of -1 if there is no data. + */ +int console_inbyte_nonblocking(int port); + +/** + * This method is invoked to initialize the console hardware device(s). + */ +void console_initialize_hardware(void); + +#endif diff --git a/bsps/include/bsp/console-termios.h b/bsps/include/bsp/console-termios.h new file mode 100644 index 0000000000..413dde4663 --- /dev/null +++ b/bsps/include/bsp/console-termios.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef BSP_CONSOLE_TERMIOS_H +#define BSP_CONSOLE_TERMIOS_H + +#include <rtems/termiostypes.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup ConsoleTermios Termios Console Driver + * + * @ingroup TermiostypesSupport + * + * @brief Console driver for Termios devices. + * + * In order to use this driver add the following lines to the Makefile.am of + * the BSP: + * + * @code + * libbsp_a_SOURCES += ../../shared/console-termios-init.c + * libbsp_a_SOURCES += ../../shared/console-termios.c + * libbsp_a_SOURCES += console/console-config.c + * @endcode + * + * Define the console_device_table and console_device_count in the + * console-config.c file of the BSP. + * + * @{ + */ + +/** + * @brief Console device probe function type. + * + * @param[in] context The Termios device context. + * + * @retval true Install this device. + * @retval false Otherwise. + */ +typedef bool (*console_device_probe)(rtems_termios_device_context *context); + +/** + * @brief Console device information. + */ +typedef struct { + /** + * @brief The device file path. + * + * The "/dev/console" device will be automatically installed as the first + * device of console_device_table with a successful probe. + */ + const char *device_file; + + /** + * @brief The device probe function. + */ + console_device_probe probe; + + /** + * @brief The Termios device handler. + */ + const rtems_termios_device_handler *handler; + + /** + * @brief The Termios device flow control handler. + */ + const rtems_termios_device_flow *flow; + + /** + * @brief The Termios device context. + */ + rtems_termios_device_context *context; +} console_device; + +/** + * @brief Returns true and does nothing else. + */ +bool console_device_probe_default(rtems_termios_device_context *context); + +/** + * @brief Table for console devices installed via console_initialize() during + * system initialization. + * + * It must be provided by the BSP. + * + * @see console_device_count. + */ +extern const console_device console_device_table[]; + +/** + * @brief Count of entries in the console_device_table. + * + * It must be provided by the BSP. + */ +extern const size_t console_device_count; + +/** @{ */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* BSP_CONSOLE_TERMIOS_H */ diff --git a/bsps/include/bsp/default-initial-extension.h b/bsps/include/bsp/default-initial-extension.h new file mode 100644 index 0000000000..1c795b7278 --- /dev/null +++ b/bsps/include/bsp/default-initial-extension.h @@ -0,0 +1,53 @@ +/** + * @file + * + * @ingroup shared_defaultinitialextension + * + * @brief DEFAULT_INITIAL_EXTENSION Support + */ + +/* + * Copyright (c) 2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_DEFAULT_INITIAL_EXTENSION_H +#define LIBBSP_SHARED_DEFAULT_INITIAL_EXTENSION_H + +#include <rtems.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup shared_defaultinitialextension DEFAULT_INITIAL_EXTENSION Support + * + * @ingroup shared_include + * + * @brief DEFAULT_INITIAL_EXTENSION Support Package + */ + +void bsp_fatal_extension( + rtems_fatal_source source, + bool always_set_to_false, + rtems_fatal_code error +); + +#define BSP_INITIAL_EXTENSION \ + { NULL, NULL, NULL, NULL, NULL, NULL, NULL, bsp_fatal_extension, NULL } + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_DEFAULT_INITIAL_EXTENSION_H */ diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h new file mode 100644 index 0000000000..ca2e39aba8 --- /dev/null +++ b/bsps/include/bsp/fatal.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2012, 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_BSP_FATAL_H +#define LIBBSP_SHARED_BSP_FATAL_H + +#include <rtems.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FATAL_CODE_BLOCK(idx) ((unsigned long) (idx) * 256UL) + +/** + * @brief BSP fatal error codes. + */ +typedef enum { + /* Generic BSP fatal codes */ + BSP_FATAL_INTERRUPT_INITIALIZATION = BSP_FATAL_CODE_BLOCK(0), + BSP_FATAL_SPURIOUS_INTERRUPT, + BSP_FATAL_CONSOLE_MULTI_INIT, + BSP_FATAL_CONSOLE_NO_MEMORY_0, + BSP_FATAL_CONSOLE_NO_MEMORY_1, + BSP_FATAL_CONSOLE_NO_MEMORY_2, + BSP_FATAL_CONSOLE_NO_MEMORY_3, + BSP_FATAL_CONSOLE_REGISTER_DEV_0, + BSP_FATAL_CONSOLE_REGISTER_DEV_1, + BSP_FATAL_CONSOLE_NO_DEV, + BSP_FATAL_CONSOLE_INSTALL_0, + BSP_FATAL_CONSOLE_INSTALL_1, + BSP_FATAL_CONSOLE_REGISTER_DEV_2, + + /* ARM fatal codes */ + BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(1), + BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE, + BSP_ARM_PL111_FATAL_REGISTER_DEV, + BSP_ARM_PL111_FATAL_SEM_CREATE, + BSP_ARM_PL111_FATAL_SEM_RELEASE, + BSP_ARM_A9MPCORE_FATAL_CLOCK_SMP_INIT, + BSP_ARM_ARMV7M_CPU_COUNTER_INIT, + BSP_ARM_FATAL_GENERIC_TIMER_CLOCK_IRQ_INSTALL, + + /* LEON3 fatal codes */ + LEON3_FATAL_NO_IRQMP_CONTROLLER = BSP_FATAL_CODE_BLOCK(2), + LEON3_FATAL_CONSOLE_REGISTER_DEV, + LEON3_FATAL_CLOCK_INITIALIZATION, + LEON3_FATAL_INVALID_CACHE_CONFIG_MAIN_PROCESSOR, + LEON3_FATAL_INVALID_CACHE_CONFIG_SECONDARY_PROCESSOR, + LEON3_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT, + + /* LPC24XX fatal codes */ + LPC24XX_FATAL_PL111_SET_UP = BSP_FATAL_CODE_BLOCK(3), + LPC24XX_FATAL_PL111_PINS_SET_UP, + LPC24XX_FATAL_PL111_PINS_TEAR_DOWN, + LPC24XX_FATAL_PL111_TEAR_DOWN, + + /* MPC5200 fatal codes */ + MPC5200_FATAL_PCF8563_INVALID_YEAR = BSP_FATAL_CODE_BLOCK(4), + MPC5200_FATAL_SLICETIMER_0_IRQ_INSTALL, + MPC5200_FATAL_SLICETIMER_1_IRQ_INSTALL, + MPC5200_FATAL_TM27_IRQ_INSTALL, + MPC5200_FATAL_MSCAN_A_INIT, + MPC5200_FATAL_MSCAN_B_INIT, + MPC5200_FATAL_MSCAN_A_SET_MODE, + MPC5200_FATAL_MSCAN_B_SET_MODE, + MPC5200_FATAL_ATA_DISK_IO_INIT, + MPC5200_FATAL_ATA_DISK_CREATE, + MPC5200_FATAL_ATA_DMA_SINGLE_IRQ_INSTALL, + MPC5200_FATAL_ATA_LOCK_CREATE, + MPC5200_FATAL_ATA_LOCK_DESTROY, + + /* MPC55XX fatal codes */ + MPC55XX_FATAL_FMPLL_LOCK = BSP_FATAL_CODE_BLOCK(5), + MPC55XX_FATAL_CLOCK_EMIOS_IRQ_INSTALL, + MPC55XX_FATAL_CLOCK_EMIOS_PRESCALER, + MPC55XX_FATAL_CLOCK_EMIOS_INTERVAL, + MPC55XX_FATAL_CLOCK_PIT_IRQ_INSTALL, + MPC55XX_FATAL_CONSOLE_GENERIC_COUNT, + MPC55XX_FATAL_CONSOLE_GENERIC_REGISTER, + MPC55XX_FATAL_CONSOLE_GENERIC_REGISTER_CONSOLE, + MPC55XX_FATAL_CONSOLE_ESCI_BAUD, + MPC55XX_FATAL_CONSOLE_ESCI_ATTRIBUTES, + MPC55XX_FATAL_CONSOLE_ESCI_IRQ_INSTALL, + MPC55XX_FATAL_CONSOLE_LINFLEX_BAUD, + MPC55XX_FATAL_CONSOLE_LINFLEX_ATTRIBUTES, + MPC55XX_FATAL_CONSOLE_LINFLEX_RX_IRQ_INSTALL, + MPC55XX_FATAL_CONSOLE_LINFLEX_TX_IRQ_INSTALL, + MPC55XX_FATAL_CONSOLE_LINFLEX_ERR_IRQ_INSTALL, + MPC55XX_FATAL_CONSOLE_LINFLEX_RX_IRQ_REMOVE, + MPC55XX_FATAL_CONSOLE_LINFLEX_TX_IRQ_REMOVE, + MPC55XX_FATAL_CONSOLE_LINFLEX_ERR_IRQ_REMOVE, + MPC55XX_FATAL_EDMA_IRQ_INSTALL, + MPC55XX_FATAL_EDMA_IRQ_REMOVE, + + /* MRM332 fatal codes */ + MRM332_FATAL_SPURIOUS_INTERRUPT = BSP_FATAL_CODE_BLOCK(6), + + /* PowerPC fatal codes */ + PPC_FATAL_EXCEPTION_INITIALIZATION = BSP_FATAL_CODE_BLOCK(7), + + /* Libchip fatal codes */ + DWMAC_FATAL_TOO_MANY_RBUFS_CONFIGURED = BSP_FATAL_CODE_BLOCK(8), + + /* ARM fatal codes */ + ARM_FATAL_L2C_310_UNEXPECTED_ID = BSP_FATAL_CODE_BLOCK(9), + ARM_FATAL_L2C_310_UNEXPECTED_NUM_WAYS, + ARM_FATAL_L2C_310_EXCLUSIVE_CONFIG, + + /* QorIQ fatal codes */ + QORIQ_FATAL_SMP_IPI_HANDLER_INSTALL = BSP_FATAL_CODE_BLOCK(10), + QORIQ_FATAL_FDT_NO_BUS_FREQUENCY, + QORIQ_FATAL_FDT_NO_CLOCK_FREQUENCY, + QORIQ_FATAL_FDT_NO_TIMEBASE_FREQUENCY, + QORIQ_FATAL_RESTART_FAILED, + QORIQ_FATAL_RESTART_INSTALL_INTERRUPT, + QORIQ_FATAL_RESTART_INTERRUPT_FAILED, + + /* ATSAM fatal codes */ + ATSAM_FATAL_XDMA_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(11), + ATSAM_FATAL_PIO_IRQ_A, + ATSAM_FATAL_PIO_IRQ_B, + ATSAM_FATAL_PIO_IRQ_C, + ATSAM_FATAL_PIO_IRQ_D, + ATSAM_FATAL_PIO_IRQ_E, + ATSAM_FATAL_PIO_CONFIGURE_IT, + + /* i.MX fatal codes */ + IMX_FATAL_GENERIC_TIMER_FREQUENCY = BSP_FATAL_CODE_BLOCK(12) +} bsp_fatal_code; + +RTEMS_NO_RETURN static inline void +bsp_fatal( bsp_fatal_code code ) +{ + rtems_fatal( RTEMS_FATAL_SOURCE_BSP, (rtems_fatal_code) code ); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_BSP_FATAL_H */ diff --git a/bsps/include/bsp/fdt.h b/bsps/include/bsp/fdt.h new file mode 100644 index 0000000000..4ed05b136c --- /dev/null +++ b/bsps/include/bsp/fdt.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_FDT_H +#define LIBBSP_SHARED_FDT_H + +#include <bsp.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * BSPs that implement the FDT support functions must define + * BSP_FDT_IS_SUPPORTED. + */ + +/** + * @brief Copies the specified source FDT to a dedicated global data area. + * + * The source FDT is usually provided by a bootloader and may be located in a + * memory area that is used by the program. The low-level initialization + * should copy the FDT for later use. + * + * The copy can be accessed by bsp_fdt_get(). + * + * @param[in] src The source FDT. + */ +void bsp_fdt_copy(const void *src); + +/** + * @brief Returns the FDT of the BSP. + * + * @return The FDT of the BSP. + */ +const void *bsp_fdt_get(void); + +/** + * @brief Maps the interrupt number of the FDT to the interrupt vector used by + * the interrupt management. + * + * This function is used by the libbsd to implement the OFW_BUS_MAP_INTR bus + * method. + * + * @param[in] intr The FDT interrupt number cells. + * @param[in] icells The FDT interrupt cell count. + * + * @return The interrupt vector of the FDT interrupt number. + */ +uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_FDT_H */ diff --git a/bsps/include/bsp/gpio.h b/bsps/include/bsp/gpio.h new file mode 100644 index 0000000000..64a877ae7a --- /dev/null +++ b/bsps/include/bsp/gpio.h @@ -0,0 +1,955 @@ +/** + * @file gpio.h + * + * @ingroup rtems_gpio + * + * @brief RTEMS GPIO API definition. + */ + +/* + * Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_GPIO_H +#define LIBBSP_SHARED_GPIO_H + +#include <bsp.h> +#include <rtems.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if !defined(BSP_GPIO_PIN_COUNT) || !defined(BSP_GPIO_PINS_PER_BANK) + #error "BSP_GPIO_PIN_COUNT or BSP_GPIO_PINS_PER_BANK is not defined." +#endif + +#if BSP_GPIO_PIN_COUNT <= 0 || BSP_GPIO_PINS_PER_BANK <= 0 + #error "Invalid BSP_GPIO_PIN_COUNT or BSP_GPIO_PINS_PER_BANK." +#endif + +#if BSP_GPIO_PINS_PER_BANK > 32 + #error "Invalid BSP_GPIO_PINS_PER_BANK. Must be in the range of 1 to 32." +#endif + +#define GPIO_LAST_BANK_PINS BSP_GPIO_PIN_COUNT % BSP_GPIO_PINS_PER_BANK + +#if GPIO_LAST_BANK_PINS > 0 + #define GPIO_BANK_COUNT (BSP_GPIO_PIN_COUNT / BSP_GPIO_PINS_PER_BANK) + 1 +#else + #define GPIO_BANK_COUNT BSP_GPIO_PIN_COUNT / BSP_GPIO_PINS_PER_BANK + #undef GPIO_LAST_BANK_PINS + #define GPIO_LAST_BANK_PINS BSP_GPIO_PINS_PER_BANK +#endif + +#if defined(BSP_GPIO_PINS_PER_SELECT_BANK) && BSP_GPIO_PINS_PER_SELECT_BANK > 32 + #error "Invalid BSP_GPIO_PINS_PER_SELECT_BANK. Must under and including 32." +#elif defined(BSP_GPIO_PINS_PER_SELECT_BANK) <= 32 + #define GPIO_SELECT_BANK_COUNT \ + BSP_GPIO_PINS_PER_BANK / BSP_GPIO_PINS_PER_SELECT_BANK +#endif + +#define INTERRUPT_SERVER_PRIORITY 1 +#define INTERRUPT_SERVER_STACK_SIZE 2 * RTEMS_MINIMUM_STACK_SIZE +#define INTERRUPT_SERVER_MODES RTEMS_TIMESLICE | RTEMS_PREEMPT +#define INTERRUPT_SERVER_ATTRIBUTES RTEMS_DEFAULT_ATTRIBUTES + +#define GPIO_INPUT_ERROR ~0 + +/** + * @name GPIO data structures + * + * @{ + */ + +/** + * @brief The set of possible configurations for a GPIO pull-up resistor. + * + * Enumerated type to define the possible pull-up resistor configurations + * for a GPIO pin. + */ +typedef enum +{ + PULL_UP = 1, + PULL_DOWN, + NO_PULL_RESISTOR +} rtems_gpio_pull_mode; + +/** + * @brief The set of possible functions a pin can have. + * + * Enumerated type to define a pin function. + */ +typedef enum +{ + DIGITAL_INPUT = 0, + DIGITAL_OUTPUT, + BSP_SPECIFIC, + NOT_USED +} rtems_gpio_function; + +/** + * @brief The set of possible interrupts a GPIO pin can generate. + * + * Enumerated type to define a GPIO pin interrupt. + */ +typedef enum +{ + FALLING_EDGE = 0, + RISING_EDGE, + LOW_LEVEL, + HIGH_LEVEL, + BOTH_EDGES, + BOTH_LEVELS, + NONE +} rtems_gpio_interrupt; + +/** + * @brief The set of possible handled states an user-defined interrupt + * handler can return. + * + * Enumerated type to define an interrupt handler handled state. + */ +typedef enum +{ + IRQ_HANDLED, + IRQ_NONE +} rtems_gpio_irq_state; + +/** + * @brief The set of flags to specify an user-defined interrupt handler + * uniqueness on a GPIO pin. + * + * Enumerated type to define an interrupt handler shared flag. + */ +typedef enum +{ + SHARED_HANDLER, + UNIQUE_HANDLER +} rtems_gpio_handler_flag; + +/** + * @brief Object containing relevant information for assigning a BSP specific + * function to a pin. + * + * Encapsulates relevant data for a BSP specific GPIO function. + */ +typedef struct +{ + /* The BSP defined function code. */ + uint32_t io_function; + + void *pin_data; +} rtems_gpio_specific_data; + +/** + * @brief Object containing configuration information + * regarding interrupts. + */ +typedef struct +{ + rtems_gpio_interrupt active_interrupt; + + rtems_gpio_handler_flag handler_flag; + + bool threaded_interrupts; + + /* Interrupt handler function. */ + rtems_gpio_irq_state (*handler) (void *arg); + + /* Interrupt handler function arguments. */ + void *arg; + + /* Software switch debounce settings. It should contain the amount of clock + * ticks that must pass between interrupts to ensure that the interrupt + * was not caused by a switch bounce. + * If set to 0 this feature is disabled . */ + uint32_t debounce_clock_tick_interval; +} rtems_gpio_interrupt_configuration; + +/** + * @brief Object containing configuration information + * to request/update a GPIO pin. + */ +typedef struct +{ + /* Processor pin number. */ + uint32_t pin_number; + rtems_gpio_function function; + + /* Pull resistor setting. */ + rtems_gpio_pull_mode pull_mode; + + /* If digital out pin, set to TRUE to set the pin to logical high, + * or FALSE for logical low. If not a digital out then this + * is ignored. */ + bool output_enabled; + + /* If true inverts digital in/out applicational logic. */ + bool logic_invert; + + /* Pin interrupt configuration. Should be NULL if not used. */ + rtems_gpio_interrupt_configuration *interrupt; + + /* Structure with BSP specific data, to use during the pin request. + * If function == BSP_SPECIFIC this should have a pointer to + * a rtems_gpio_specific_data structure. + * + * If not this field may be NULL. This is passed to the BSP function + * so any BSP specific data can be passed to it through this pointer. */ + void *bsp_specific; +} rtems_gpio_pin_conf; + +/** + * @brief Object containing configuration information + * to assign GPIO functions to multiple pins + * at the same time. To be used by BSP code only. + */ +typedef struct +{ + /* Global GPIO pin number. */ + uint32_t pin_number; + + /* RTEMS GPIO pin function code. */ + rtems_gpio_function function; + + /* BSP specific function code. Only used if function == BSP_SPECIFIC */ + uint32_t io_function; + + /* BSP specific data. */ + void *bsp_specific; +} rtems_gpio_multiple_pin_select; + +/** + * @brief Object containing configuration information + * to request a GPIO pin group. + */ +typedef struct +{ + const rtems_gpio_pin_conf *digital_inputs; + uint32_t input_count; + + const rtems_gpio_pin_conf *digital_outputs; + uint32_t output_count; + + const rtems_gpio_pin_conf *bsp_specifics; + uint32_t bsp_specific_pin_count; +} rtems_gpio_group_definition; + +/** + * @brief Opaque type for a GPIO pin group. + */ +typedef struct rtems_gpio_group rtems_gpio_group; + +/** @} */ + +/** + * @name gpio Usage + * + * @{ + */ + +/** + * @brief Initializes the GPIO API. + * + * @retval RTEMS_SUCCESSFUL API successfully initialized. + * @retval * @see rtems_semaphore_create(). + */ +extern rtems_status_code rtems_gpio_initialize(void); + +/** + * @brief Instantiates a GPIO pin group. + * To define the group @see rtems_gpio_define_pin_group(). + * + * @retval rtems_gpio_group pointer. + */ +extern rtems_gpio_group *rtems_gpio_create_pin_group(void); + +/** + * @brief Requests a GPIO pin group configuration. + * + * @param[in] group_definition rtems_gpio_group_definition structure filled with + * the group pins configurations. + * @param[out] group Reference to the created group. + * + * @retval RTEMS_SUCCESSFUL Pin group was configured successfully. + * @retval RTEMS_UNSATISFIED @var group_definition or @var group is NULL, + * the @var pins are not from the same bank, + * no pins were defined or could not satisfy at + * least one given configuration. + * @retval RTEMS_RESOURCE_IN_USE At least one pin is already being used. + * @retval * @see rtems_semaphore_create(). + */ +extern rtems_status_code rtems_gpio_define_pin_group( + const rtems_gpio_group_definition *group_definition, + rtems_gpio_group *group +); + +/** + * @brief Writes a value to the group's digital outputs. The pins order + * is as defined in the group definition. + * + * @param[in] data Data to write/send. + * @param[in] group Reference to the group. + * + * @retval RTEMS_SUCCESSFUL Data successfully written. + * @retval RTEMS_NOT_DEFINED Group has no output pins. + * @retval RTEMS_UNSATISFIED Could not operate on at least one of the pins. + */ +extern rtems_status_code rtems_gpio_write_group( + uint32_t data, + rtems_gpio_group *group +); + +/** + * @brief Reads the value/level of the group's digital inputs. The pins order + * is as defined in the group definition. + * + * @param[in] group Reference to the group. + * + * @retval The function returns a 32-bit bitmask with the group's input pins + * current logical values. + * @retval GPIO_INPUT_ERROR Group has no input pins. + */ +extern uint32_t rtems_gpio_read_group(rtems_gpio_group *group); + +/** + * @brief Performs a BSP specific operation on a group of pins. The pins order + * is as defined in the group definition. + * + * @param[in] group Reference to the group. + * @param[in] arg Pointer to a BSP defined structure with BSP-specific + * data. This field is handled by the BSP. + * + * @retval RTEMS_SUCCESSFUL Operation completed with success. + * @retval RTEMS_NOT_DEFINED Group has no BSP specific pins, or the BSP does not + * support BSP specific operations for groups. + * @retval RTEMS_UNSATISFIED Could not operate on at least one of the pins. + */ +extern rtems_status_code rtems_gpio_group_bsp_specific_operation( + rtems_gpio_group *group, + void *arg +); + +/** + * @brief Requests a GPIO pin configuration. + * + * @param[in] conf rtems_gpio_pin_conf structure filled with the pin information + * and desired configurations. + * + * @retval RTEMS_SUCCESSFUL Pin was configured successfully. + * @retval RTEMS_UNSATISFIED Could not satisfy the given configuration. + */ +extern rtems_status_code rtems_gpio_request_configuration( + const rtems_gpio_pin_conf *conf +); + +/** + * @brief Updates the current configuration of a GPIO pin . + * + * @param[in] conf rtems_gpio_pin_conf structure filled with the pin information + * and desired configurations. + * + * @retval RTEMS_SUCCESSFUL Pin configuration was updated successfully. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED The pin is not being used. + * @retval RTEMS_UNSATISFIED Could not update the pin's configuration. + */ +extern rtems_status_code rtems_gpio_update_configuration( + const rtems_gpio_pin_conf *conf +); + +/** + * @brief Sets multiple output GPIO pins with the logical high. + * + * @param[in] pin_numbers Array with the GPIO pin numbers to set. + * @param[in] count Number of GPIO pins to set. + * + * @retval RTEMS_SUCCESSFUL All pins were set successfully. + * @retval RTEMS_INVALID_ID At least one pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED At least one of the received pins + * is not configured as a digital output. + * @retval RTEMS_UNSATISFIED Could not set the GPIO pins. + */ +extern rtems_status_code rtems_gpio_multi_set( + uint32_t *pin_numbers, + uint32_t pin_count +); + +/** + * @brief Sets multiple output GPIO pins with the logical low. + * + * @param[in] pin_numbers Array with the GPIO pin numbers to clear. + * @param[in] count Number of GPIO pins to clear. + * + * @retval RTEMS_SUCCESSFUL All pins were cleared successfully. + * @retval RTEMS_INVALID_ID At least one pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED At least one of the received pins + * is not configured as a digital output. + * @retval RTEMS_UNSATISFIED Could not clear the GPIO pins. + */ +extern rtems_status_code rtems_gpio_multi_clear( + uint32_t *pin_numbers, + uint32_t pin_count +); + +/** + * @brief Returns the value (level) of multiple GPIO input pins. + * + * @param[in] pin_numbers Array with the GPIO pin numbers to read. + * @param[in] count Number of GPIO pins to read. + * + * @retval Bitmask with the values of the corresponding pins. + * 0 for logical low and 1 for logical high. + * @retval GPIO_INPUT_ERROR Could not read at least one pin level. + */ +extern uint32_t rtems_gpio_multi_read( + uint32_t *pin_numbers, + uint32_t pin_count +); + +/** + * @brief Sets an output GPIO pin with the logical high. + * + * @param[in] pin_number GPIO pin number. + * + * @retval RTEMS_SUCCESSFUL Pin was set successfully. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED The received pin is not configured + * as a digital output. + * @retval RTEMS_UNSATISFIED Could not set the GPIO pin. + */ +extern rtems_status_code rtems_gpio_set(uint32_t pin_number); + +/** + * @brief Sets an output GPIO pin with the logical low. + * + * @param[in] pin_number GPIO pin number. + * + * @retval RTEMS_SUCCESSFUL Pin was cleared successfully. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED The received pin is not configured + * as a digital output. + * @retval RTEMS_UNSATISFIED Could not clear the GPIO pin. + */ +extern rtems_status_code rtems_gpio_clear(uint32_t pin_number); + +/** + * @brief Returns the value (level) of a GPIO input pin. + * + * @param[in] pin_number GPIO pin number. + * + * @retval The function returns 0 or 1 depending on the pin current + * logical value. + * @retval -1 Pin number is invalid, or not a digital input pin. + */ +extern int rtems_gpio_get_value(uint32_t pin_number); + +/** + * @brief Requests multiple GPIO pin configurations. If the BSP provides + * support for parallel selection each call to this function will + * result in a single call to the GPIO hardware, else each pin + * configuration will be done in individual and sequential calls. + * All pins must belong to the same GPIO bank. + * + * @param[in] pins Array of rtems_gpio_pin_conf structures filled with the pins + * information and desired configurations. All pins must belong + * to the same GPIO bank. + * @param[in] pin_count Number of pin configurations in the @var pins array. + * + * @retval RTEMS_SUCCESSFUL All pins were configured successfully. + * @retval RTEMS_INVALID_ID At least one pin number in the @var pins array + * is invalid. + * @retval RTEMS_RESOURCE_IN_USE At least one pin is already being used. + * @retval RTEMS_UNSATISFIED Could not satisfy at least one given configuration. + */ +extern rtems_status_code rtems_gpio_multi_select( + const rtems_gpio_pin_conf *pins, + uint8_t pin_count +); + +/** + * @brief Assigns a certain function to a GPIO pin. + * + * @param[in] pin_number GPIO pin number. + * @param[in] function The new function for the pin. + * @param[in] output_enabled If TRUE and @var function is DIGITAL_OUTPUT, + * then the pin is set with the logical high. + * Otherwise it is set with logical low. + * @param[in] logic_invert Reverses the digital I/O logic for DIGITAL_INPUT + * and DIGITAL_OUTPUT pins. + * @param[in] bsp_specific Pointer to a BSP defined structure with BSP-specific + * data. This field is handled by the BSP. + * + * @retval RTEMS_SUCCESSFUL Pin was configured successfully. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_RESOURCE_IN_USE The received pin is already being used. + * @retval RTEMS_UNSATISFIED Could not assign the GPIO function. + * @retval RTEMS_NOT_DEFINED GPIO function not defined, or NOT_USED. + */ +extern rtems_status_code rtems_gpio_request_pin( + uint32_t pin_number, + rtems_gpio_function function, + bool output_enable, + bool logic_invert, + void *bsp_specific +); + +/** + * @brief Configures a single GPIO pin pull resistor. + * + * @param[in] pin_number GPIO pin number. + * @param[in] mode The pull resistor mode. + * + * @retval RTEMS_SUCCESSFUL Pull resistor successfully configured. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_UNSATISFIED Could not set the pull mode. + */ +extern rtems_status_code rtems_gpio_resistor_mode( + uint32_t pin_number, + rtems_gpio_pull_mode mode +); + +/** + * @brief Releases a GPIO pin, making it available to be used again. + * + * @param[in] pin_number GPIO pin number. + * + * @retval RTEMS_SUCCESSFUL Pin successfully disabled. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval * Could not disable an active interrupt on this pin, + * @see rtems_gpio_disable_interrupt(). + */ +extern rtems_status_code rtems_gpio_release_pin(uint32_t pin_number); + +/** + * @brief Releases a GPIO pin, making it available to be used again. + * + * @param[in] conf GPIO pin configuration to be released. + * + * @retval RTEMS_SUCCESSFUL Pin successfully disabled. + * @retval RTEMS_UNSATISFIED Pin configuration is NULL. + * @retval * @see rtems_gpio_release_pin(). + */ +extern rtems_status_code rtems_gpio_release_configuration( + const rtems_gpio_pin_conf *conf +); + +/** + * @brief Releases multiple GPIO pins, making them available to be used again. + * + * @param[in] pins Array of rtems_gpio_pin_conf structures. + * @param[in] pin_count Number of pin configurations in the @var pins array. + * + * @retval RTEMS_SUCCESSFUL Pins successfully disabled. + * @retval RTEMS_UNSATISFIED @var pins array is NULL. + * @retval * @see rtems_gpio_release_pin(). + */ +extern rtems_status_code rtems_gpio_release_multiple_pins( + const rtems_gpio_pin_conf *pins, + uint32_t pin_count +); + +/** + * @brief Releases a GPIO pin group, making the pins used available to be + * repurposed. + * + * @param[in] conf GPIO pin configuration to be released. + * + * @retval RTEMS_SUCCESSFUL Pins successfully disabled. + * @retval * @see rtems_gpio_release_pin(), @see rtems_semaphore_delete() or + * @see rtems_semaphore_flush(). + */ +extern rtems_status_code rtems_gpio_release_pin_group( + rtems_gpio_group *group +); + +/** + * @brief Attaches a debouncing function to a given pin/switch. + * Debouncing is done by requiring a certain number of clock ticks to + * pass between interrupts. Any interrupt fired too close to the last + * will be ignored as it is probably the result of an involuntary + * switch/button bounce after being released. + * + * @param[in] pin_number GPIO pin number. + * @param[in] ticks Minimum number of clock ticks that must pass between + * interrupts so it can be considered a legitimate + * interrupt. + * + * @retval RTEMS_SUCCESSFUL Debounce function successfully attached to the pin. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED The current pin is not configured as a digital + * input, hence it can not be connected to a switch, + * or interrupts are not enabled for this pin. + */ +extern rtems_status_code rtems_gpio_debounce_switch( + uint32_t pin_number, + int ticks +); + +/** + * @brief Connects a new user-defined interrupt handler to a given pin. + * + * @param[in] pin_number GPIO pin number. + * @param[in] handler Pointer to a function that will be called every time + * the enabled interrupt for the given pin is generated. + * This function must return information about its + * handled/unhandled state. + * @param[in] arg Void pointer to the arguments of the user-defined handler. + * + * @retval RTEMS_SUCCESSFUL Handler successfully connected to this pin. + * @retval RTEMS_NO_MEMORY Could not connect more user-defined handlers to + * the given pin. + * @retval RTEMS_NOT_CONFIGURED The given pin has no interrupt configured. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_TOO_MANY The pin's current handler is set as unique. + * @retval RTEMS_RESOURCE_IN_USE The current user-defined handler for this pin + * is unique. + */ +extern rtems_status_code rtems_gpio_interrupt_handler_install( + uint32_t pin_number, + rtems_gpio_irq_state (*handler) (void *arg), + void *arg +); + +/** + * @brief Enables interrupts to be generated on a given GPIO pin. + * When fired that interrupt will call the given handler. + * + * @param[in] pin_number GPIO pin number. + * @param[in] interrupt Type of interrupt to enable for the pin. + * @param[in] flag Defines the uniqueness of the interrupt handler for the pin. + * @param[in] threaded_handling Defines if the handler should be called from a + * thread/task or from normal ISR contex. + * @param[in] handler Pointer to a function that will be called every time + * @var interrupt is generated. This function must return + * information about its handled/unhandled state. + * @param[in] arg Void pointer to the arguments of the user-defined handler. + * + * @retval RTEMS_SUCCESSFUL Interrupt successfully enabled for this pin. + * @retval RTEMS_UNSATISFIED Could not install the GPIO ISR, create/start + * the handler task, or enable the interrupt + * on the pin. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED The received pin is not configured + * as a digital input, the pin is on a + * pin grouping. + * @retval RTEMS_RESOURCE_IN_USE The pin already has an enabled interrupt, + * or the handler threading policy does not match + * the bank's policy. + * @retval RTEMS_NO_MEMORY Could not store the pin's interrupt configuration. + */ +extern rtems_status_code rtems_gpio_enable_interrupt( + uint32_t pin_number, + rtems_gpio_interrupt interrupt, + rtems_gpio_handler_flag flag, + bool threaded_handling, + rtems_gpio_irq_state (*handler) (void *arg), + void *arg +); + +/** + * @brief Disconnects an user-defined interrupt handler from the given pin. + * If in the end there are no more user-defined handlers connected + * to the pin, interrupts are disabled on the given pin. + * + * @param[in] pin_number GPIO pin number. + * @param[in] handler Pointer to the user-defined handler + * @param[in] arg Void pointer to the arguments of the user-defined handler. + * + * @retval RTEMS_SUCCESSFUL Handler successfully disconnected from this pin. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED Pin has no active interrupts. + * @retval * @see rtems_gpio_disable_interrupt() + */ +extern rtems_status_code rtems_gpio_interrupt_handler_remove( + uint32_t pin_number, + rtems_gpio_irq_state (*handler) (void *arg), + void *arg +); + +/** + * @brief Stops interrupts from being generated on a given GPIO pin + * and removes the corresponding handler. + * + * @param[in] pin_number GPIO pin number. + * + * @retval RTEMS_SUCCESSFUL Interrupt successfully disabled for this pin. + * @retval RTEMS_INVALID_ID Pin number is invalid. + * @retval RTEMS_NOT_CONFIGURED Pin has no active interrupts. + * @retval RTEMS_UNSATISFIED Could not remove the current interrupt handler, + * could not recognize the current active interrupt + * on this pin or could not disable interrupts on + * this pin. + */ +extern rtems_status_code rtems_gpio_disable_interrupt(uint32_t pin_number); + +/** + * @brief Sets multiple output GPIO pins with the logical high. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] bitmask Bitmask of GPIO pins to set in the given bank. + * + * @retval RTEMS_SUCCESSFUL All pins were set successfully. + * @retval RTEMS_UNSATISFIED Could not set at least one of the pins. + */ +extern rtems_status_code rtems_gpio_bsp_multi_set( + uint32_t bank, + uint32_t bitmask +); + +/** + * @brief Sets multiple output GPIO pins with the logical low. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] bitmask Bitmask of GPIO pins to clear in the given bank. + * + * @retval RTEMS_SUCCESSFUL All pins were cleared successfully. + * @retval RTEMS_UNSATISFIED Could not clear at least one of the pins. + */ +extern rtems_status_code rtems_gpio_bsp_multi_clear( + uint32_t bank, + uint32_t bitmask +); + +/** + * @brief Returns the value (level) of multiple GPIO input pins. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] bitmask Bitmask of GPIO pins to read in the given bank. + * + * @retval The function must return a bitmask with the values of the + * corresponding pins. 0 for logical low and 1 for logical high. + * @retval GPIO_INPUT_ERROR Could not read at least one pin level. + */ +extern uint32_t rtems_gpio_bsp_multi_read(uint32_t bank, uint32_t bitmask); + +/** + * @brief Performs a BSP specific operation on a group of pins. + * The implementation for this function may be omitted if the target + * does not support the feature, by returning RTEMS_NOT_DEFINED. + * + * @param[in] bank GPIO bank number. + * @param[in] pins Array filled with BSP specific pin numbers. All pins belong + * to the same select bank. + * @param[in] pin_count Number of pin configurations in the @var pins array. + * @param[in] arg Pointer to a BSP defined structure with BSP-specific + * data. This field is handled by the BSP. + * + * @retval RTEMS_SUCCESSFUL Operation completed with success. + * @retval RTEMS_NOT_DEFINED Group has no BSP specific pins, or the BSP does not + * support BSP specific operations for groups. + * @retval RTEMS_UNSATISFIED Could not operate on at least one of the pins. + */ +extern rtems_status_code rtems_gpio_bsp_specific_group_operation( + uint32_t bank, + uint32_t *pins, + uint32_t pin_count, + void *arg +); + +/** + * @brief Assigns GPIO functions to all the given pins in a single register + * operation. + * The implementation for this function may be omitted if the target + * does not support the feature, by returning RTEMS_NOT_DEFINED. + * + * @param[in] pins Array of rtems_gpio_multiple_pin_select structures filled + * with the pins desired functions. All pins belong to the + * same select bank. + * @param[in] pin_count Number of pin configurations in the @var pins array. + * @param[in] select_bank Select bank number of the received pins. + * + * @retval RTEMS_SUCCESSFUL Functions were assigned successfully. + * @retval RTEMS_NOT_DEFINED The BSP does not support multiple pin function + * assignment. + * @retval RTEMS_UNSATISFIED Could not assign the functions to the pins. + */ +extern rtems_status_code rtems_gpio_bsp_multi_select( + rtems_gpio_multiple_pin_select *pins, + uint32_t pin_count, + uint32_t select_bank +); + +/** + * @brief Sets an output GPIO pin with the logical high. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * + * @retval RTEMS_SUCCESSFUL Pin was set successfully. + * @retval RTEMS_UNSATISFIED Could not set the given pin. + */ +extern rtems_status_code rtems_gpio_bsp_set(uint32_t bank, uint32_t pin); + +/** + * @brief Sets an output GPIO pin with the logical low. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * + * @retval RTEMS_SUCCESSFUL Pin was cleared successfully. + * @retval RTEMS_UNSATISFIED Could not clear the given pin. + */ +extern rtems_status_code rtems_gpio_bsp_clear(uint32_t bank, uint32_t pin); + +/** + * @brief Returns the value (level) of a GPIO input pin. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * + * @retval The function must return 0 if the pin level is a logical low, + * or non zero if it has a logical high. + * @retval GPIO_INPUT_ERROR Could not read the pin level. + */ +extern uint32_t rtems_gpio_bsp_get_value(uint32_t bank, uint32_t pin); + +/** + * @brief Assigns the digital input function to the given pin. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * @param[in] bsp_specific Pointer to a BSP defined structure with BSP-specific + * data. + * + * @retval RTEMS_SUCCESSFUL Function was assigned successfully. + * @retval RTEMS_UNSATISFIED Could not assign the function to the pin. + */ +extern rtems_status_code rtems_gpio_bsp_select_input( + uint32_t bank, + uint32_t pin, + void *bsp_specific +); + +/** + * @brief Assigns the digital output function to the given pin. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * @param[in] bsp_specific Pointer to a BSP defined structure with BSP-specific + * data. + * + * @retval RTEMS_SUCCESSFUL Function was assigned successfully. + * @retval RTEMS_UNSATISFIED Could not assign the function to the pin. + */ +extern rtems_status_code rtems_gpio_bsp_select_output( + uint32_t bank, + uint32_t pin, + void *bsp_specific +); + +/** + * @brief Assigns a BSP specific function to the given pin. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * @param[in] function BSP defined GPIO function. + * @param[in] pin_data Pointer to a BSP defined structure with BSP-specific + * data. + * + * @retval RTEMS_SUCCESSFUL Function was assigned successfully. + * @retval RTEMS_UNSATISFIED Could not assign the function to the pin. + */ +extern rtems_status_code rtems_gpio_bsp_select_specific_io( + uint32_t bank, + uint32_t pin, + uint32_t function, + void *pin_data +); + +/** + * @brief Configures a single GPIO pin pull resistor. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * @param[in] mode The pull resistor mode. + * + * @retval RTEMS_SUCCESSFUL Pull resistor successfully configured. + * @retval RTEMS_UNSATISFIED Could not set the pull mode. + */ +extern rtems_status_code rtems_gpio_bsp_set_resistor_mode( + uint32_t bank, + uint32_t pin, + rtems_gpio_pull_mode mode +); + +/** + * @brief Reads and returns a vector/bank interrupt event line. + * The bitmask should indicate with a 1 if the corresponding pin + * as a pending interrupt, or 0 if otherwise. The function + * should clear the interrupt event line before returning. + * This must be implemented by each BSP. + * + * @param[in] vector GPIO vector/bank. + * + * @retval Bitmask (max 32-bit) representing a GPIO bank, where a bit set + * indicates an active interrupt on that pin. + */ +extern uint32_t rtems_gpio_bsp_interrupt_line(rtems_vector_number vector); + +/** + * @brief Calculates a vector number for a given GPIO bank. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * + * @retval The corresponding rtems_vector_number. + */ +extern rtems_vector_number rtems_gpio_bsp_get_vector(uint32_t bank); + +/** + * @brief Enables interrupts to be generated on a given GPIO pin. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * @param[in] interrupt Type of interrupt to enable for the pin. + * + * @retval RTEMS_SUCCESSFUL Interrupt successfully enabled for this pin. + * @retval RTEMS_UNSATISFIED Could not enable the interrupt on the pin. + */ +extern rtems_status_code rtems_gpio_bsp_enable_interrupt( + uint32_t bank, + uint32_t pin, + rtems_gpio_interrupt interrupt +); + +/** + * @brief Stops interrupts from being generated on a given GPIO pin. + * This must be implemented by each BSP. + * + * @param[in] bank GPIO bank number. + * @param[in] pin GPIO pin number within the given bank. + * @param[in] active_interrupt Interrupt type currently active on this pin. + * + * @retval RTEMS_SUCCESSFUL Interrupt successfully disabled for this pin. + * @retval RTEMS_UNSATISFIED Could not disable interrupts on this pin. + */ +extern rtems_status_code rtems_gpio_bsp_disable_interrupt( + uint32_t bank, + uint32_t pin, + rtems_gpio_interrupt interrupt +); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_GPIO_H */ diff --git a/bsps/include/bsp/irq-generic.h b/bsps/include/bsp/irq-generic.h new file mode 100644 index 0000000000..187aea84d1 --- /dev/null +++ b/bsps/include/bsp/irq-generic.h @@ -0,0 +1,304 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief Generic BSP interrupt support API. + */ + +/* + * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette. + * + * Copyright (c) 2008, 2017 embedded brains GmbH. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * Copyright (c) 2016 Chris Johns <chrisj@rtems.org> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_IRQ_GENERIC_H +#define LIBBSP_SHARED_IRQ_GENERIC_H + +#include <stdbool.h> + +#include <rtems/irq-extension.h> +#include <rtems/score/assert.h> + +#ifdef RTEMS_SMP + #include <rtems/score/atomic.h> +#endif + +#include <bsp/irq.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if !defined(BSP_INTERRUPT_VECTOR_MIN) || !defined(BSP_INTERRUPT_VECTOR_MAX) || (BSP_INTERRUPT_VECTOR_MAX + 1) < BSP_INTERRUPT_VECTOR_MIN + #error "invalid BSP_INTERRUPT_VECTOR_MIN or BSP_INTERRUPT_VECTOR_MAX" +#endif + +#if defined(BSP_INTERRUPT_USE_INDEX_TABLE) && !defined(BSP_INTERRUPT_HANDLER_TABLE_SIZE) + #error "if you define BSP_INTERRUPT_USE_INDEX_TABLE, you have to define BSP_INTERRUPT_HANDLER_TABLE_SIZE etc. as well" +#endif + +#if defined(BSP_INTERRUPT_NO_HEAP_USAGE) && !defined(BSP_INTERRUPT_USE_INDEX_TABLE) + #error "if you define BSP_INTERRUPT_NO_HEAP_USAGE, you have to define BSP_INTERRUPT_USE_INDEX_TABLE etc. as well" +#endif + +#define BSP_INTERRUPT_VECTOR_NUMBER \ + (BSP_INTERRUPT_VECTOR_MAX - BSP_INTERRUPT_VECTOR_MIN + 1) + +#ifndef BSP_INTERRUPT_HANDLER_TABLE_SIZE + #define BSP_INTERRUPT_HANDLER_TABLE_SIZE BSP_INTERRUPT_VECTOR_NUMBER +#endif + +/* Internal macros for SMP support, do not use externally */ +#ifdef RTEMS_SMP + #define bsp_interrupt_disable(level) do { (void) level; } while (0) + #define bsp_interrupt_enable(level) do { } while (0) + #define bsp_interrupt_fence(order) _Atomic_Fence(order) +#else + #define bsp_interrupt_disable(level) rtems_interrupt_disable(level) + #define bsp_interrupt_enable(level) rtems_interrupt_enable(level) + #define bsp_interrupt_fence(order) do { } while (0) +#endif + +#define bsp_interrupt_assert(e) _Assert(e) + +struct bsp_interrupt_handler_entry { + rtems_interrupt_handler handler; + void *arg; + const char *info; + struct bsp_interrupt_handler_entry *next; +}; + +typedef struct bsp_interrupt_handler_entry bsp_interrupt_handler_entry; + +extern bsp_interrupt_handler_entry bsp_interrupt_handler_table []; + +#ifdef BSP_INTERRUPT_USE_INDEX_TABLE + #if BSP_INTERRUPT_HANDLER_TABLE_SIZE < 0x100 + typedef uint8_t bsp_interrupt_handler_index_type; + #elif BSP_INTERRUPT_HANDLER_TABLE_SIZE < 0x10000 + typedef uint16_t bsp_interrupt_handler_index_type; + #else + typedef uint32_t bsp_interrupt_handler_index_type; + #endif + extern bsp_interrupt_handler_index_type bsp_interrupt_handler_index_table []; +#endif + +static inline rtems_vector_number bsp_interrupt_handler_index( + rtems_vector_number vector +) +{ + #ifdef BSP_INTERRUPT_USE_INDEX_TABLE + return bsp_interrupt_handler_index_table [vector - BSP_INTERRUPT_VECTOR_MIN]; + #else + return vector - BSP_INTERRUPT_VECTOR_MIN; + #endif +} + +/** + * @defgroup bsp_interrupt BSP Interrupt Support + * + * @ingroup bsp_shared + * + * @brief Generic BSP Interrupt Support + * + * The BSP interrupt support manages a sequence of interrupt vector numbers + * ranging from @ref BSP_INTERRUPT_VECTOR_MIN to @ref BSP_INTERRUPT_VECTOR_MAX + * including the end points. It provides methods to + * @ref bsp_interrupt_handler_install() "install", + * @ref bsp_interrupt_handler_remove() "remove" and + * @ref bsp_interrupt_handler_dispatch() "dispatch" interrupt handlers for each + * vector number. It implements parts of the RTEMS interrupt manager. + * + * The entry points to a list of interrupt handlers are stored in a table + * (= handler table). + * + * You have to configure the BSP interrupt support in the <bsp/irq.h> file + * for each BSP. For a minimum configuration you have to provide + * @ref BSP_INTERRUPT_VECTOR_MIN and @ref BSP_INTERRUPT_VECTOR_MAX. + * + * For boards with small memory requirements you can define + * @ref BSP_INTERRUPT_USE_INDEX_TABLE. With an enabled index table the handler + * table will be accessed via a small index table. You can define the size of + * the handler table with @ref BSP_INTERRUPT_HANDLER_TABLE_SIZE. + * + * Normally new list entries are allocated from the heap. You may define + * @ref BSP_INTERRUPT_NO_HEAP_USAGE, if you do not want to use the heap. For + * this option you have to define @ref BSP_INTERRUPT_USE_INDEX_TABLE as well. + * + * You have to provide some special routines in your BSP (follow the links for + * the details): + * - bsp_interrupt_facility_initialize() + * - bsp_interrupt_vector_enable() + * - bsp_interrupt_vector_disable() + * - bsp_interrupt_handler_default() + * + * The following now deprecated functions are provided for backward + * compatibility: + * - BSP_get_current_rtems_irq_handler() + * - BSP_install_rtems_irq_handler() + * - BSP_install_rtems_shared_irq_handler() + * - BSP_remove_rtems_irq_handler() + * - BSP_rtems_irq_mngt_set() + * - BSP_rtems_irq_mngt_get() + * + * @{ + */ + +#ifdef BSP_INTERRUPT_CUSTOM_VALID_VECTOR + bool bsp_interrupt_is_valid_vector(rtems_vector_number vector); +#else + /** + * @brief Returns true if the interrupt vector with number @a vector is + * valid. + */ + static inline bool bsp_interrupt_is_valid_vector(rtems_vector_number vector) + { + return (rtems_vector_number) BSP_INTERRUPT_VECTOR_MIN <= vector + && vector <= (rtems_vector_number) BSP_INTERRUPT_VECTOR_MAX; + } +#endif + +/** + * @brief Default interrupt handler. + * + * This routine will be called from bsp_interrupt_handler_dispatch() with the + * current vector number @a vector when the handler list for this vector is + * empty or the vector number is out of range. + * + * @note This function must cope with arbitrary vector numbers @a vector. + */ +void bsp_interrupt_handler_default(rtems_vector_number vector); + +/** + * @brief Initialize BSP interrupt support. + * + * You must call this function before you can install, remove and dispatch + * interrupt handlers. There is no protection against concurrent + * initialization. This function must be called at most once. The BSP + * specific bsp_interrupt_facility_initialize() function will be called after + * all internals are initialized. If the BSP specific initialization fails, + * then this is a fatal error. The fatal error source is + * RTEMS_FATAL_SOURCE_BSP and the fatal error code is + * BSP_FATAL_INTERRUPT_INITIALIZATION. + */ +void bsp_interrupt_initialize(void); + +/** + * @brief BSP specific initialization. + * + * This routine will be called form bsp_interrupt_initialize() and shall do the + * following: + * - Initialize the facilities that call bsp_interrupt_handler_dispatch(). For + * example on PowerPC the external exception handler. + * - Initialize the interrupt controller. You shall set the interrupt + * controller in a state such that interrupts are disabled for all vectors. + * The vectors will be enabled with your bsp_interrupt_vector_enable() function + * and disabled via your bsp_interrupt_vector_disable() function. These + * functions have to work afterwards. + * + * @return On success RTEMS_SUCCESSFUL shall be returned. + */ +rtems_status_code bsp_interrupt_facility_initialize(void); + +/** + * @brief Enables the interrupt vector with number @a vector. + * + * This function shall enable the vector at the corresponding facility (in most + * cases the interrupt controller). It will be called then the first handler + * is installed for the vector in bsp_interrupt_handler_install() for example. + * + * @note The implementation should use + * bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)) to valdiate the + * vector number. + * + * @note You must not install or remove an interrupt handler in this function. + * This may result in a deadlock. + */ +void bsp_interrupt_vector_enable(rtems_vector_number vector); + +/** + * @brief Disables the interrupt vector with number @a vector. + * + * This function shall disable the vector at the corresponding facility (in + * most cases the interrupt controller). It will be called then the last + * handler is removed for the vector in bsp_interrupt_handler_remove() for + * example. + * + * @note The implementation should use + * bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)) to valdiate the + * vector number. + * + * @note You must not install or remove an interrupt handler in this function. + * This may result in a deadlock. + */ +void bsp_interrupt_vector_disable(rtems_vector_number vector); + +/** + * @brief Sequencially calls all interrupt handlers for the vector number @a + * vector. + * + * If the vector number is out of range or the handler list is empty + * bsp_interrupt_handler_default() will be called with argument @a vector. + * + * You can call this function within every context which can be disabled via + * rtems_interrupt_disable(). + */ +static inline void bsp_interrupt_handler_dispatch(rtems_vector_number vector) +{ + if (bsp_interrupt_is_valid_vector(vector)) { + const bsp_interrupt_handler_entry *e = + &bsp_interrupt_handler_table [bsp_interrupt_handler_index(vector)]; + + do { + rtems_interrupt_handler handler; + void *arg; + + arg = e->arg; + bsp_interrupt_fence(ATOMIC_ORDER_ACQUIRE); + handler = e->handler; + (*handler)(arg); + + e = e->next; + } while (e != NULL); + } else { + bsp_interrupt_handler_default(vector); + } +} + +/** + * @brief Is interrupt handler empty. + * + * This routine returns true if the handler is empty and has not been + * initialised else false is returned. The interrupt lock is not used + * so this call can be used from within interrupts. + * + * @return If empty true shall be returned else false is returned. + */ +bool bsp_interrupt_handler_is_empty(rtems_vector_number vector); + +/** @} */ + +/* For internal use only */ +void bsp_interrupt_lock(void); + +/* For internal use only */ +void bsp_interrupt_unlock(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_IRQ_GENERIC_H */ diff --git a/bsps/include/bsp/irq-info.h b/bsps/include/bsp/irq-info.h new file mode 100644 index 0000000000..ea6d629e76 --- /dev/null +++ b/bsps/include/bsp/irq-info.h @@ -0,0 +1,56 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief Generic BSP interrupt information API. + */ + +/* + * Copyright (c) 2008, 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_IRQ_INFO_H +#define LIBBSP_SHARED_IRQ_INFO_H + +#include <rtems/shell.h> +#include <rtems/print.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Prints interrupt information via the printk plugin @a print with the + * context @a context. + */ +void bsp_interrupt_report_with_plugin( + const rtems_printer *printer +); + +/** + * @brief Prints interrupt information via the default printk plugin. + */ +void bsp_interrupt_report(void); + +/** + * @brief Shell command entry for interrupt information. + */ +extern struct rtems_shell_cmd_tt bsp_interrupt_shell_command; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_IRQ_INFO_H */ diff --git a/bsps/include/bsp/mm.h b/bsps/include/bsp/mm.h new file mode 100644 index 0000000000..2152f686ba --- /dev/null +++ b/bsps/include/bsp/mm.h @@ -0,0 +1,41 @@ +/** + * @file + * + * @ingroup shared_mm + * + * @brief MM Support + */ + +/* + * Copyright (c) 2013 Hesham AL-Matary. + * Copyright (c) 2013 Gedare Bloom. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __LIBBSP_MM_H +#define __LIBBSP_MM_H + +#include <stdint.h> +#include <stdlib.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_mm MM Support + * + * @ingroup shared_include + * + * @brief MM Support Package + */ + +void bsp_memory_management_initialize(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsps/include/bsp/stackalloc.h b/bsps/include/bsp/stackalloc.h new file mode 100644 index 0000000000..89414c8e6e --- /dev/null +++ b/bsps/include/bsp/stackalloc.h @@ -0,0 +1,94 @@ +/** + * @file + * + * @ingroup bsp_stack + * + * @brief Task stack initialization, allocation and free functions. + */ + +/* + * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_STACK_ALLOC_H +#define LIBBSP_SHARED_STACK_ALLOC_H + +#include <stddef.h> +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup bsp_stack Task Stack Allocator + * + * @ingroup bsp_shared + * + * @brief Task stack initialization, allocation and free functions. + * + * Initialize the task stack allocator with bsp_stack_initialize(). To enable + * the task stack allocator use the following in the system configuration: + * + * @code + * #include <bsp/stackalloc.h> + * + * #define CONFIGURE_INIT + * + * #include <confdefs.h> + * @endcode + * + * @{ + */ + +/** + * @brief Task stack allocator initialization for + * @ref CONFIGURE_TASK_STACK_ALLOCATOR_INIT. + */ +void bsp_stack_allocate_init(size_t stack_space_size); + +/** + * @brief Task stack allocator for @ref CONFIGURE_TASK_STACK_ALLOCATOR. + * + * In case the designated task stack space from bsp_stack_initialize() is + * completely in use the work space will be used to allocate the stack. + */ +void *bsp_stack_allocate(size_t size); + +/** + * @brief Task stack free function for @ref CONFIGURE_TASK_STACK_DEALLOCATOR. + */ +void bsp_stack_free(void *stack); + +/** + * @brief Task stack allocator initialization configuration option. + */ +#define CONFIGURE_TASK_STACK_ALLOCATOR_INIT bsp_stack_allocate_init + +/** + * @brief Task stack allocator configuration option. + */ +#define CONFIGURE_TASK_STACK_ALLOCATOR bsp_stack_allocate + +/** + * @brief Task stack deallocator configuration option. + */ +#define CONFIGURE_TASK_STACK_DEALLOCATOR bsp_stack_free + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_STACK_ALLOC_H */ diff --git a/bsps/include/bsp/u-boot.h b/bsps/include/bsp/u-boot.h new file mode 100644 index 0000000000..866cd9bbb0 --- /dev/null +++ b/bsps/include/bsp/u-boot.h @@ -0,0 +1,66 @@ +/** + * @file + * + * @ingroup shared_uboot + * + * @brief U_BOOT Support + */ + +/* + * Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_U_BOOT_H +#define LIBBSP_SHARED_U_BOOT_H + +#include <bsp/u-boot-config.h> + +#include <sys/types.h> +#include <stdint.h> + +#ifdef U_BOOT_64_BIT_PHYS_SIZE + typedef uint64_t phys_size_t; +#else + typedef unsigned long phys_size_t; +#endif + +#ifdef U_BOOT_GENERIC_BOARD_INFO + #include <bsp/u-boot-generic-board-info.h> +#else + #include <bsp/u-boot-board-info.h> +#endif + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +extern bd_t bsp_uboot_board_info; + +/** + * @defgroup shared_uboot U_BOOT Support + * + * @ingroup shared_include + * + * @brief U_BOOT Support Package + */ + +void bsp_uboot_copy_board_info(const bd_t *src); + +/* FIXME: Do not use this function */ +void dumpUBootBDInfo(bd_t *u); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_U_BOOT_H */ diff --git a/bsps/include/bsp/uart-output-char.h b/bsps/include/bsp/uart-output-char.h new file mode 100644 index 0000000000..a6648d1ad4 --- /dev/null +++ b/bsps/include/bsp/uart-output-char.h @@ -0,0 +1,60 @@ +/** + * @file + * + * @ingroup bsp_kit + * + * @brief Output character definitions for standard UARTs. + */ + +/* + * Copyright (c) 2010 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_UART_OUTPUT_CHAR_H +#define LIBBSP_SHARED_UART_OUTPUT_CHAR_H + +#include <stdint.h> + +#include <bsp.h> + +#define CONSOLE_RBR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x00)) +#define CONSOLE_THR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x00)) +#define CONSOLE_DLL (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x00)) +#define CONSOLE_DLM (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x04)) +#define CONSOLE_IER (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x04)) +#define CONSOLE_IIR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x08)) +#define CONSOLE_FCR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x08)) +#define CONSOLE_LCR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x0C)) +#define CONSOLE_MCR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x10)) +#define CONSOLE_LSR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x14)) +#define CONSOLE_SCR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x1C)) +#define CONSOLE_ACR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x20)) +#define CONSOLE_ICR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x24)) +#define CONSOLE_FDR (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x28)) +#define CONSOLE_TER (*(volatile uint32_t *) (BSP_CONSOLE_UART_BASE + 0x30)) + +#define CONSOLE_LSR_RDR 0x1 +#define CONSOLE_LSR_THRE 0x20 +#define CONSOLE_LSR_TEMT 0x40 + +#define BSP_CONSOLE_UART_INIT(dll) \ + do { \ + CONSOLE_LCR = 0x00; \ + CONSOLE_IER = 0x00; \ + CONSOLE_LCR = 0x80; \ + CONSOLE_DLL = (dll & 0xFF); \ + CONSOLE_DLM = (dll >> 8); \ + CONSOLE_LCR = 0x03; \ + CONSOLE_FCR = 0x07; \ + } while (0) + +#endif /* LIBBSP_SHARED_UART_OUTPUT_CHAR_H */ diff --git a/bsps/include/bsp/utility.h b/bsps/include/bsp/utility.h new file mode 100644 index 0000000000..fee28f445a --- /dev/null +++ b/bsps/include/bsp/utility.h @@ -0,0 +1,156 @@ +/** + * @file + * + * @ingroup bsp_kit + * + * @brief Utility macros. + */ + +/* + * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_SHARED_UTILITY_H +#define LIBCPU_SHARED_UTILITY_H + +#include <stdint.h> + +#define BSP_BIT8(bit) \ + ((uint8_t) (((unsigned int) 1) << (bit))) + +#define BSP_MSK8(first_bit, last_bit) \ + ((uint8_t) ((BSP_BIT8((last_bit) - (first_bit) + 1) - 1) << (first_bit))) + +#define BSP_FLD8(val, first_bit, last_bit) \ + ((uint8_t) \ + ((((unsigned int) (val)) << (first_bit)) & BSP_MSK8(first_bit, last_bit))) + +#define BSP_FLD8GET(reg, first_bit, last_bit) \ + ((uint8_t) (((reg) & BSP_MSK8(first_bit, last_bit)) >> (first_bit))) + +#define BSP_FLD8SET(reg, val, first_bit, last_bit) \ + ((uint8_t) (((reg) & ~BSP_MSK8(first_bit, last_bit)) \ + | BSP_FLD8(val, first_bit, last_bit))) + +#define BSP_BIT16(bit) \ + ((uint16_t) (((unsigned int) 1) << (bit))) + +#define BSP_MSK16(first_bit, last_bit) \ + ((uint16_t) ((BSP_BIT16((last_bit) - (first_bit) + 1) - 1) << (first_bit))) + +#define BSP_FLD16(val, first_bit, last_bit) \ + ((uint16_t) \ + ((((unsigned int) (val)) << (first_bit)) & BSP_MSK16(first_bit, last_bit))) + +#define BSP_FLD16GET(reg, first_bit, last_bit) \ + ((uint16_t) (((reg) & BSP_MSK16(first_bit, last_bit)) >> (first_bit))) + +#define BSP_FLD16SET(reg, val, first_bit, last_bit) \ + ((uint16_t) (((reg) & ~BSP_MSK16(first_bit, last_bit)) \ + | BSP_FLD16(val, first_bit, last_bit))) + +#define BSP_BIT32(bit) \ + ((uint32_t) (((uint32_t) 1) << (bit))) + +#define BSP_MSK32(first_bit, last_bit) \ + ((uint32_t) ((BSP_BIT32((last_bit) - (first_bit) + 1) - 1) << (first_bit))) + +#define BSP_FLD32(val, first_bit, last_bit) \ + ((uint32_t) \ + ((((uint32_t) (val)) << (first_bit)) & BSP_MSK32(first_bit, last_bit))) + +#define BSP_FLD32GET(reg, first_bit, last_bit) \ + ((uint32_t) (((reg) & BSP_MSK32(first_bit, last_bit)) >> (first_bit))) + +#define BSP_FLD32SET(reg, val, first_bit, last_bit) \ + ((uint32_t) (((reg) & ~BSP_MSK32(first_bit, last_bit)) \ + | BSP_FLD32(val, first_bit, last_bit))) + +#define BSP_BIT64(bit) \ + ((uint64_t) (((uint64_t) 1) << (bit))) + +#define BSP_MSK64(first_bit, last_bit) \ + ((uint64_t) ((BSP_BIT64((last_bit) - (first_bit) + 1) - 1) << (first_bit))) + +#define BSP_FLD64(val, first_bit, last_bit) \ + ((uint64_t) \ + ((((uint64_t) (val)) << (first_bit)) & BSP_MSK64(first_bit, last_bit))) + +#define BSP_FLD64GET(reg, first_bit, last_bit) \ + ((uint64_t) (((reg) & BSP_MSK64(first_bit, last_bit)) >> (first_bit))) + +#define BSP_FLD64SET(reg, val, first_bit, last_bit) \ + ((uint64_t) (((reg) & ~BSP_MSK64(first_bit, last_bit)) \ + | BSP_FLD64(val, first_bit, last_bit))) + +#define BSP_BBIT8(bit) \ + BSP_BIT8(7 - (bit)) + +#define BSP_BMSK8(first_bit, last_bit) \ + BSP_MSK8(7 - (last_bit), 7 - (first_bit)) + +#define BSP_BFLD8(val, first_bit, last_bit) \ + BSP_FLD8(val, 7 - (last_bit), 7 - (first_bit)) + +#define BSP_BFLD8GET(reg, first_bit, last_bit) \ + BSP_FLD8GET(reg, 7 - (last_bit), 7 - (first_bit)) + +#define BSP_BFLD8SET(reg, val, first_bit, last_bit) \ + BSP_FLD8SET(reg, val, 7 - (last_bit), 7 - (first_bit)) + +#define BSP_BBIT16(bit) \ + BSP_BIT16(15 - (bit)) + +#define BSP_BMSK16(first_bit, last_bit) \ + BSP_MSK16(15 - (last_bit), 15 - (first_bit)) + +#define BSP_BFLD16(val, first_bit, last_bit) \ + BSP_FLD16(val, 15 - (last_bit), 15 - (first_bit)) + +#define BSP_BFLD16GET(reg, first_bit, last_bit) \ + BSP_FLD16GET(reg, 15 - (last_bit), 15 - (first_bit)) + +#define BSP_BFLD16SET(reg, val, first_bit, last_bit) \ + BSP_FLD16SET(reg, val, 15 - (last_bit), 15 - (first_bit)) + +#define BSP_BBIT32(bit) \ + BSP_BIT32(31 - (bit)) + +#define BSP_BMSK32(first_bit, last_bit) \ + BSP_MSK32(31 - (last_bit), 31 - (first_bit)) + +#define BSP_BFLD32(val, first_bit, last_bit) \ + BSP_FLD32(val, 31 - (last_bit), 31 - (first_bit)) + +#define BSP_BFLD32GET(reg, first_bit, last_bit) \ + BSP_FLD32GET(reg, 31 - (last_bit), 31 - (first_bit)) + +#define BSP_BFLD32SET(reg, val, first_bit, last_bit) \ + BSP_FLD32SET(reg, val, 31 - (last_bit), 31 - (first_bit)) + +#define BSP_BBIT64(bit) \ + BSP_BIT64(63 - (bit)) + +#define BSP_BMSK64(first_bit, last_bit) \ + BSP_MSK64(63 - (last_bit), 63 - (first_bit)) + +#define BSP_BFLD64(val, first_bit, last_bit) \ + BSP_FLD64(val, 63 - (last_bit), 63 - (first_bit)) + +#define BSP_BFLD64GET(reg, first_bit, last_bit) \ + BSP_FLD64GET(reg, 63 - (last_bit), 63 - (first_bit)) + +#define BSP_BFLD64SET(reg, val, first_bit, last_bit) \ + BSP_FLD64SET(reg, val, 63 - (last_bit), 63 - (first_bit)) + +#endif /* LIBCPU_SHARED_UTILITY_H */ diff --git a/bsps/include/bsp/vmeTsi148.h b/bsps/include/bsp/vmeTsi148.h new file mode 100644 index 0000000000..6183940a2d --- /dev/null +++ b/bsps/include/bsp/vmeTsi148.h @@ -0,0 +1,662 @@ +/** + * @file + * + * @ingroup shared_vmetsi148 + * + * @brief Driver for the Tundra Tsi148 pci-vme bridge + */ + +#ifndef VME_TSI148_DRIVER_H +#define VME_TSI148_DRIVER_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include <stdint.h> +#include <bsp/vme_am_defs.h> + + +/** + * @defgroup shared_vmetsi148 VMETSI148 Support + * + * @ingroup shared_vmeuniverse + * + * @brief VMETSI148 Support Package + */ + +/* NOTE: A64 currently not implemented */ + +/* These can be ored with the AM */ + +/* NOTE: unlike the universe, the tsi148 doesn't allow for disabling posted writes ! */ + +#define VME_MODE_PREFETCH_ENABLE VME_AM_IS_MEMORY +#define _LD_VME_MODE_PREFETCHSZ 24 +#define VME_MODE_PREFETCH_SIZE(x) (((x)&3)<<_LD_VME_MODE_PREFETCHSZ) + +/* These bits can be or'ed with the address-modifier when calling + * the 'XlateAddr' routine below to further qualify the + * search criteria. + */ +#define VME_MODE_MATCH_MASK (3<<30) +#define VME_MODE_EXACT_MATCH (2<<30) /* all bits must match */ +#define VME_MODE_AS_MATCH (1<<30) /* only A16/24/32 must match */ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile uint32_t BERegister; /* emphasize contents are big endian */ + +/* + * Scan the PCI busses for the Nth (N=='instance') Tsi148 VME bridge. + * + * RETURNS: + * contents of the IRQ_LINE PCI config register on Success, + * the base address of the Tsi148 register block is stored in + * *pbase. + * -1 on error (no Tsi found, error accessing PCI config space). + * + * SIDE_EFFECTS: PCI busmaster and response to memory addresses is enabled. + */ +int +vmeTsi148FindPciBase(int instance, BERegister **pbase); + +/* Initialize driver for Nth Tsi148 device found. + * This routine does not change any registers but + * just scans the PCI bus for Tsi bridges and initializes + * a driver slot. + * + * RETURNS: 0 on success, nonzero on error (or if no Tsi148 + * device is found). + */ +int +vmeTsi148InitInstance(unsigned instance); + +/* Initialize driver with 1st Tsi148 bridge found + * RETURNS: (see vmeTsi148InitInstance()). + */ +int +vmeTsi148Init(void); + +/* Setup the tsi148 chip, i.e. disable most of its + * mappings, reset interrupts etc. + */ +void +vmeTsi148ResetXX(BERegister *base); + +/* Setup the tsi148 connected to the first driver slot */ +void +vmeTsi148Reset(void); + +/* Pull VME SYSRESET line */ +void +vmeTsi148ResetBusXX(BERegister *base); + +/* Pull VME SYSRESET line of the 1st controller */ +void +vmeTsi148ResetBus(void); + +/* NOTE: all non-'XX' versions of driver entry points which + * have an associated 'XX' entry point operate on the + * device connected to the 1st driver slot. + */ + +/* configure a outbound port + * + * port: port number 0..7 + * + * address_space: vxWorks compliant addressing mode identifier + * (see vme.h). The most important are: + * 0x0d - A32, Sup, Data + * 0x3d - A24, Sup, Data + * 0x2d - A16, Sup, Data + * additionally, the value 0 is accepted; it will + * disable this port. + * vme_address: address on the vme_bus of this port. + * local_address: address on the pci_bus of this port. + * length: size of this port. + * + * NOTE: the addresses and length parameters must meet certain alignment + * requirements (see Tsi148 documentation). + * + * RETURNS: 0 on success, -1 on failure. Error messages printed to stderr. + */ + +int +vmeTsi148OutboundPortCfgXX( + BERegister *base, + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long pci_address, + unsigned long length); + +int +vmeTsi148OutboundPortCfg( + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long pci_address, + unsigned long length); + + +/* configure a VME inbound (PCI master) port */ +int +vmeTsi148InboundPortCfgXX( + BERegister *base, + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long pci_address, + unsigned long length); + +int +vmeTsi148InboundPortCfg( + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long pci_address, + unsigned long length); + +/* Translate an address through the bridge + * + * vmeTsi248XlateAddr(0,0,as,addr,&result) + * yields a VME a address that reflects + * a local memory location as seen from the VME bus through the + * tsi148 VME inbound port. + * + * Likewise does vmeTsi148XlateAddr(1,0,as,addr,&result) + * translate a VME bus addr (backwards, through the VME outbound + * port) to the PCI side of the bridge. + * + * A valid address space modifier must be specified. + * If VME_MODE_EXACT_MATCH is set, all the mode bits must + * match the requested mode. If VME_MODE_EXACT_MATCH is not + * set in the mode word, only the basic mode (address-space, + * sup/usr and pgm/data) is compared. + * + * The 'reverse' parameter may be used to find a reverse + * mapping, i.e. the pci address in a outbound window can be + * found if the respective vme address is known etc. + * + * RETURNS: translated address in *pbusAdrs / *plocalAdrs + * + * 0: success + * -1: address/modifier not found in any bridge port + * -2: invalid modifier + */ + +int +vmeTsi148XlateAddrXX( + BERegister *base, /* TSI 148 base address */ + int outbound, /* look in the outbound windows */ + int reverse, /* reverse mapping; for outbound ports: map local to VME */ + unsigned long as, /* address space */ + unsigned long aIn, /* address to look up */ + unsigned long *paOut/* where to put result */ + ); + +int +vmeTsi148XlateAddr( + int outbound, /* look in the outbound windows */ + int reverse, /* reverse mapping; for outbound: map local to VME */ + unsigned long as, /* address space */ + unsigned long aIn, /* address to look up */ + unsigned long *paOut/* where to put result */ + ); + + +/* avoid pulling stdio.h into this header. + * Applications that want a declaration of the + * following routines should + * #include <stdio.h> + * #define _VME_TSI148_DECLARE_SHOW_ROUTINES + * #include <vmeTsi148.h> + */ +#ifdef _VME_TSI148_DECLARE_SHOW_ROUTINES + +/* Print the current configuration of all outbound ports to + * f (stdout if NULL) + */ + +void +vmeTsi148OutboundPortsShowXX(BERegister *base, FILE *f); + +void +vmeTsi148OutboundPortsShow(FILE *f); + +/* Print the current configuration of all inbound ports to + * f (stdout if NULL) + */ + +void +vmeTsi148InboundPortsShowXX(BERegister *base, FILE *f); + +void +vmeTsi148InboundPortsShow(FILE *f); + +#endif + + +/* Disable all in- or out-bound ports, respectively */ +void +vmeTsi148DisableAllInboundPortsXX(BERegister *base); + +void +vmeTsi148DisableAllInboundPorts(void); + +void +vmeTsi148DisableAllOutboundPortsXX(BERegister *base); + +void +vmeTsi148DisableAllOutboundPorts(void); + +# define TSI_VEAT_VES (1<<31) +# define TSI_VEAT_VEOF (1<<30) +# define TSI_VEAT_VESCL (1<<29) +# define TSI_VEAT_2eOT (1<<21) +# define TSI_VEAT_2eST (1<<20) +# define TSI_VEAT_BERR (1<<19) +# define TSI_VEAT_LWORD (1<<18) +# define TSI_VEAT_WRITE (1<<17) +# define TSI_VEAT_IACK (1<<16) +# define TSI_VEAT_DS1 (1<<15) +# define TSI_VEAT_DS0 (1<<14) +# define TSI_VEAT_AM(v) (((v)>>8)&63) +# define TSI_VEAT_XAM(v) ((v)&255) + +/* Check and clear the error (AKA 'exception') register. + * Note that the Tsi148 does *not* propagate VME bus errors of any kind to + * the PCI status register and hence this routine (or registering an ISR + * to the TSI_VERR_INT_VEC) is the only means for detecting a bus error. + * + * RETURNS: + * 0 if no error has occurred since this routine was last called. + * Contents of the 'VEAT' register (bit definitions as above) + * otherwise. + * If a non-NULL 'paddr' argument is provided then the lower 32-bit + * of the error address is stored in *paddr (only if return value is + * non-zero). + * + * SIDE EFFECTS: this routine clears the error attribute register, allowing + * for future errors to be latched. + */ +unsigned long +vmeTsi148ClearVMEBusErrorsXX(BERegister *base, uint32_t *paddr); + +unsigned long +vmeTsi148ClearVMEBusErrors(uint32_t *paddr); + +/* Map internal register block to VME. + * + * This routine is intended for BSP implementors. The registers must be + * accessible from VME so that the interrupt handler can flush the + * bridge FIFO (see below). + * + * vme_base: VME address where the TSI registers (4k) can be mapped. + * This VME address must fall into a range covered by + * any pre-configured outbound window. + * address_space: The desired VME address space. + * (all of SUP/USR/PGM/DATA are always accepted). + * + * See NOTES [vmeTsi148InstallIrqMgrAlt()] below for further information. + * + * RETURNS: 0 on success, nonzero on error. It is not possible (and results + * in a non-zero return code) to change the CRG VME address after + * initializing the interrupt manager as it uses the CRG. + */ +int +vmeTsi148MapCRGXX(BERegister *base, uint32_t vme_base, uint32_t address_space); + +int +vmeTsi148MapCRG(uint32_t vme_base, uint32_t address_space); + + +/* VME Interrupt Handler functionality */ + +/* we dont use the current RTEMS/BSP interrupt API for the + * following reasons: + * + * - RTEMS/BSP API does not pass an argument to the ISR :-( :-( + * - no separate vector space for VME vectors. Some vectors would + * have to overlap with existing PCI/ISA vectors. + * - RTEMS/BSP API allocates a structure for every possible vector + * - the irq_on(), irq_off() functions add more bloat than helping. + * They are (currently) only used by the framework to disable + * interrupts at the device level before removing a handler + * and to enable interrupts after installing a handler. + * These operations may as well be done by the driver itself. + * + * Hence, we maintain our own (VME) handler table and hook our PCI + * handler into the standard RTEMS/BSP environment. Our handler then + * dispatches VME interrupts. + */ + +typedef void (*VmeTsi148ISR) (void *usrArg, unsigned long vector); + +/* install a handler for a VME vector + * RETURNS 0 on success, nonzero on failure. + */ +int +vmeTsi148InstallISR(unsigned long vector, VmeTsi148ISR handler, void *usrArg); + +/* remove a handler for a VME vector. The vector and usrArg parameters + * must match the respective parameters used when installing the handler. + * RETURNS 0 on success, nonzero on failure. + */ +int +vmeTsi148RemoveISR(unsigned long vector, VmeTsi148ISR handler, void *usrArg); + +/* query for the currently installed ISR and usr parameter at a given vector + * RETURNS: ISR or 0 (vector too big or no ISR installed) + */ +VmeTsi148ISR +vmeTsi148ISRGet(unsigned long vector, void **parg); + +/* utility routines to enable/disable a VME IRQ level + * + * To enable/disable the internal interrupt sources (special vectors above) + * pass a vector argument > 255. + * + * RETURNS 0 on success, nonzero on failure + */ +int +vmeTsi148IntEnable(unsigned int level); + +int +vmeTsi148IntDisable(unsigned int level); + +/* Check if an interrupt level or internal source is enabled: + * + * 'level': VME level 1..7 or internal special vector > 255 + * + * RETURNS: value > 0 if interrupt is currently enabled, + * zero if interrupt is currently disabled, + * -1 on error (invalid argument). + */ + +int +vmeTsi148IntIsEnabled(unsigned int level); + +/* Set IACK width (1,2, or 4 bytes) for a given interrupt level. + * + * 'width' arg may be 0,1,2 or 4. If zero, the currently active + * value is returned but not modified. + * + * RETURNS: old width or -1 if invalid argument. + */ + +int +vmeTsi148SetIackWidth(int level, int width); + +/* Change the routing of IRQ 'level' to 'pin'. + * If the BSP connects more than one of the four + * physical interrupt lines from the tsi148 to + * the board's PIC then you may change the physical + * line a given 'level' is using. By default, + * all 7 VME levels use the first wire (pin==0) and + * all internal sources use the (optional) second + * wire (pin==1) [The driver doesn't support more than + * four wires]. + * This feature is useful if you want to make use of + * different hardware priorities of the PIC. Let's + * say you want to give IRQ level 7 the highest priority. + * You could then give 'pin 0' a higher priority (at the + * PIC) and 'pin 1' a lower priority and issue. + * + * for ( i=1; i<7; i++ ) vmeTsi148IntRoute(i, 1); + * + * PARAMETERS: + * 'level' : VME interrupt level '1..7' or one of + * the internal sources. Pass the internal + * source's vector number (>=256). + * 'pin' : a value of 0 routes the requested IRQ to + * the first line registered with the manager, + * a value of 1 routes it to the second wire + * etc. + * + * RETURNS: 0 on success, nonzero on error (invalid arguments) + * + * NOTES: - DONT change the tsi148 'map' registers + * directly. The driver caches routing internally. + * - support for the extra wires (beyond wire #0) is + * board dependent. If the board only provides + * a single physical wire from the tsi148 to + * the PIC then the feature might not be available. + */ +int +vmeTsi148IntRoute(unsigned int level, unsigned int pin); + +/* Raise a VME Interrupt at 'level' and respond with 'vector' to a + * handler on the VME bus. (The handler could be a different board + * or the tsi148 itself. + * + * Note that you could install a interrupt handler at TSI_VME_SW_IACK_INT_VEC + * to be notified of an IACK cycle having completed. + * + * This routine is mainly FOR TESTING. + * + * NOTES: + * - the VICR register is modified. + * - NO MUTUAL EXCLUSION PROTECTION (reads VICR, modifies then writes back). + * If several users need access to VICR it is their responsibility to serialize access. + * + * Arguments: + * 'level': interrupt level, 1..7 + * 'vector': vector number (0..255) that the tsi148 puts on the bus in response to + * an IACK cycle. + * + * RETURNS: + * 0: Success + * -1: Invalid argument (level not 1..7, vector >= 256) + * -2: Interrupt 'level' already asserted (maybe nobody handles it). + * You can manually clear it be setting the IRQC bit in + * VICR. Make sure really nobody responds to avoid spurious + * interrupts (consult tsi148 docs). + */ + +int +vmeTsi148IntRaiseXX(BERegister *base, int level, unsigned vector); + +int +vmeTsi148IntRaise(int level, unsigned vector); + +/* Loopback test of the VME interrupt subsystem. + * - installs ISRs on 'vector' and on TSI_VME_SW_IACK_INT_VEC + * - asserts VME interrupt 'level' + * - waits for both interrupts: 'ordinary' VME interrupt of 'level' and + * IACK completion interrupt ('special' vector TSI_VME_SW_IACK_INT_VEC). + * + * NOTES: + * - make sure no other handler responds to 'level'. + * - make sure no ISR is installed on both vectors yet. + * - ISRs installed by this routine are removed after completion. + * - no concurrent access protection of all involved resources + * (levels, vectors and registers [see vmeTsi148IntRaise()]) + * is implemented. + * - this routine is intended for TESTING (when implementing new BSPs etc.). + * - one RTEMS message queue is temporarily used (created/deleted). + * + * RETURNS: + * 0: Success. + * -1: Invalid arguments. + * 1: Test failed (outstanding interrupts). + * rtems_status_code: Failed RTEMS directive. + */ + +int +vmeTsi148IntLoopbackTst(int level, unsigned vector); + +/* use these special vectors to connect a handler to the + * tsi148 specific interrupts (such as "DMA done", SW or + * error irqs etc.) + * NOTE: The wrapper clears all status LINT bits (except + * for regular VME irqs). Also note that it is the user's + * responsibility to enable the necessary interrupts in + * LINT_EN + * + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * DO NOT CHANGE THE ORDER OF THESE VECTORS - THE DRIVER + * DEPENDS ON IT + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * + * Deliberately, these vectors match the universe driver's + */ +/* 256 no VOWN interrupt */ +#define TSI_DMA_INT_VEC 257 +#define TSI_LERR_INT_VEC 258 +#define TSI_VERR_INT_VEC 259 +/* 260 is reserved */ +#define TSI_VME_SW_IACK_INT_VEC 261 +/* 262 no PCI SW IRQ */ +#define TSI_SYSFAIL_INT_VEC 263 +#define TSI_ACFAIL_INT_VEC 264 +#define TSI_MBOX0_INT_VEC 265 +#define TSI_MBOX1_INT_VEC 266 +#define TSI_MBOX2_INT_VEC 267 +#define TSI_MBOX3_INT_VEC 268 +#define TSI_LM0_INT_VEC 269 +#define TSI_LM1_INT_VEC 270 +#define TSI_LM2_INT_VEC 271 +#define TSI_LM3_INT_VEC 272 + +/* New vectors; only on TSI148 */ +#define TSI_VIES_INT_VEC 273 +#define TSI_DMA1_INT_VEC 274 + +#define TSI_NUM_INT_VECS 275 + +#ifdef __INSIDE_RTEMS_BSP__ + +#include <stdarg.h> + +/* the tsi148 interrupt handler is capable of routing all sorts of + * (VME) interrupts to 4 different lines (some of) which may be hooked up + * in a (board specific) way to a PIC. + * + * This driver initially supports at most two lines (i.e., if the user + * doesn't re-route anything). By default, it routes the + * 7 VME interrupts to the main line and optionally, it routes the 'special' + * interrupts generated by the tsi148 itself (DMA done, SW irq etc.) + * to a second line. If no second line is available, all IRQs are routed + * to the main line. + * + * The routing of interrupts to the two lines can be modified (using + * the vmeTsi148IntRoute() call - see above - i.e., to make use of + * different hardware priorities and/or more physically available lines. + * + * Because the driver has no way to figure out which lines are actually + * wired to the PIC, this information has to be provided when installing + * the manager. + * + * Hence the manager sets up routing VME interrupts to 1 or 2 tsi148 + * OUTPUTS. However, it must also be told to which PIC INPUTS they + * are wired. + * Optionally, the first PIC input line can be read from PCI config space + * but the second must be passed to this routine. Note that the info read + * from PCI config space is wrong for some boards! + * + * PARAMETERS: + * flags: VMETSI148_IRQ_MGR_FLAG_SHARED: + * use the BSP_install_rtems_shared_irq_handler() instead + * of BSP_install_rtems_irq_handler(). Use this if the PIC + * line is used by other devices, too. + * CAVEAT: shared interrupts need RTEMS workspace, i.e., the + * VME interrupt manager can only be installed + * *after workspace is initialized* if 'shared' is nonzero + * (i.e., *not* from bspstart()). + * + * tsi_pin_0: to which output pin (of the tsi148) should the 7 + * VME irq levels be routed. + * + * pic_pin_0: specifies to which PIC input the 'main' output is + * wired on your board. If passed a value < 0, the driver + * reads this information from PCI config space ("IRQ line"). + * ... : up to three additional tsi_pin/pic_pin pairs can be + * specified if your board provides more physical wires. + * In any case must the varargs list be terminated by '-1'. + * + * RETURNS: 0 on success, -1 on failure. + * + * NOTES: The Tsi148 always does 'posted' writes through a FIFO buffer. + * This effectively makes VME write operations asynchronous + * which can have undesired side-effects. + * In particular, consider the case of an ISR clearing the + * interrupt condition by writing to a CSR. The write operation + * doesn't really do anything but goes into the FIFO and + * the user ISR returns. At this point, the interrupt manager + * may find the IRQ still pending, trying another IACK + * cycle. Because it is probable that at this time the FIFO + * has been flushed and the CSR-write operation been effective, + * the IACK then times out. + * Note that this phenomenon becomes more obvious as CPUs + * become faster. + * + * To avoid this race condition and many VME drivers having + * to be re-written, a VME read (having the desired side-effect + * of flushing the write FIFO) must be issued between the + * user ISR returning and the interrupt manager checking for + * more pending interrupts. + * + * Therefore, the BSP needs to map the Tsi148 register + * block to VME so that a read over VME can be effectuated. + * (In addition to being mapped to VME, the mapped address + * range must be accessible through an outbound window.) + */ + +#define VMETSI148_IRQ_MGR_FLAG_SHARED 1 +int +vmeTsi148InstallIrqMgrAlt(int shared, int tsi_pin0, int pic_pin0, ...); + +int +vmeTsi148InstallIrqMgrVa(int shared, int tsi_pin0, int pic_pin0, va_list ap); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/vmeTsi148DMA.h b/bsps/include/bsp/vmeTsi148DMA.h new file mode 100644 index 0000000000..da7c99302b --- /dev/null +++ b/bsps/include/bsp/vmeTsi148DMA.h @@ -0,0 +1,102 @@ +/** + * @file + * + * @ingroup shared_vmetsi148dma + * + * @brief vmeTsi148DMA Support + */ + +#ifndef VME_TSI148_DMA_H +#define VME_TSI148_DMA_H + +#include <bsp/vmeTsi148.h> + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2006, 2007 + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_vmetsi148dma DMA List + * + * @ingroup shared_vmeuniverse + * + * @brief DMA List access functions for use by bspVmeDmaList + */ + +extern struct VMEDmaListClassRec_ vmeTsi148DmaListClass; + +typedef struct VmeTsi148DmaListDescriptorRec_ *VmeTsi148DmaListDescriptor; + +int +vmeTsi148DmaSetupXX(BERegister *base, int channel, uint32_t mode, uint32_t xfer_mode, void *custom); + +int +vmeTsi148DmaSetup(int channel, uint32_t mode, uint32_t xfer_mode, void *custom); + +int +vmeTsi148DmaListStartXX(BERegister *base, int channel, VmeTsi148DmaListDescriptor d); + +int +vmeTsi148DmaListStart(int channel, VmeTsi148DmaListDescriptor d); + +int +vmeTsi148DmaStartXX(BERegister *base, int channel, uint32_t pci_addr, uint32_t vme_addr, uint32_t n_bytes); + +int +vmeTsi148DmaStart(int channel, uint32_t pci_addr, uint32_t vme_addr, uint32_t n_bytes); + +uint32_t +vmeTsi148DmaStatusXX(BERegister *base, int channel); + +uint32_t +vmeTsi148DmaStatus(int channel); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/vmeUniverse.h b/bsps/include/bsp/vmeUniverse.h new file mode 100644 index 0000000000..7cb9f8d2de --- /dev/null +++ b/bsps/include/bsp/vmeUniverse.h @@ -0,0 +1,1045 @@ +/** + * @file + * + * @ingroup shared_vmeuniverse + * + * @brief Driver for the Tundra Universe II pci-vme bridge + */ + +#ifndef VME_UNIVERSE_UTIL_H +#define VME_UNIVERSE_UTIL_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2000-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +/** + * @defgroup shared_vmeuniverse Register definitions + * + * @ingroup bsp_shared + * + * @brief all registers contents in PCI space are LITTLE ENDIAN + */ + +#ifdef __vxworks +#include <vme.h> +#else + +#include <bsp/vme_am_defs.h> + +#endif + +/* These bits can be or'ed with the address-modifier when calling + * the 'XlateAddr' routine below to further qualify the + * search criteria. + */ +#define VME_MODE_MATCH_MASK (3<<30) +#define VME_MODE_EXACT_MATCH (2<<30) /* all bits must match */ +#define VME_MODE_AS_MATCH (1<<30) /* only A16/24/32 must match */ + + +typedef unsigned long LERegister; /* emphasize contents are little endian */ + +/****** NOTE: USE OF VmeUniverseDMAPacket IS DEPRECATED ********* + ****** USE API IN VMEDMA.h INSTEAD *********/ + +/* NOTE: DMA packet descriptors MUST be 32 byte aligned */ +typedef struct VmeUniverseDMAPacketRec_ { + LERegister dctl __attribute__((aligned(32))); + LERegister dtbc __attribute__((packed)); + LERegister dla __attribute__((packed)); + LERegister dummy1 __attribute__((packed)); + LERegister dva __attribute__((packed)); + LERegister dummy2 __attribute__((packed)); + LERegister dcpp __attribute__((packed)); + LERegister dummy3 __attribute__((packed)); +} VmeUniverseDMAPacketRec, *VmeUniverseDMAPacket; /* DEPRECATED */ + +/* PCI CSR register */ +#define UNIV_REGOFF_PCI_CSR 0x4 +# define UNIV_PCI_CSR_D_PE (1<<31) /* detected parity error; write 1 to clear */ +# define UNIV_PCI_CSR_S_SERR (1<<30) /* SERR (signalled error) asserted; write 1 to clear */ +# define UNIV_PCI_CSR_R_MA (1<<29) /* received master abort; write 1 to clear */ +# define UNIV_PCI_CSR_R_TA (1<<28) /* received target abort; write 1 to clear */ +# define UNIV_PCI_CSR_S_TA (1<<27) /* signalled target abort; write 1 to clear */ +# define UNIV_PCI_CSR_DEVSEL_MASK (3<<25) /* device select timing (RO) */ +# define UNIV_PCI_CSR_DP_D (1<<24) /* data parity error detected; write 1 to clear */ +# define UNIV_PCI_CSR_TFBBC (1<<23) /* target fast back to back capable (RO) */ +# define UNIV_PCI_CSR_MFBBC (1<<9) /* master fast back to back capable (RO) */ +# define UNIV_PCI_CSR_SERR_EN (1<<8) /* enable SERR driver */ +# define UNIV_PCI_CSR_WAIT (1<<7) /* wait cycle control (RO) */ +# define UNIV_PCI_CSR_PERESP (1<<6) /* parity error response enable */ +# define UNIV_PCI_CSR_VGAPS (1<<5) /* VGA palette snoop (RO) */ +# define UNIV_PCI_CSR_MWI_EN (1<<4) /* Memory write and invalidate enable (RO) */ +# define UNIV_PCI_CSR_SC (1<<3) /* special cycles (RO) */ +# define UNIV_PCI_CSR_BM (1<<2) /* master enable (MUST SET TO ENABLE VME SLAVES) */ +# define UNIV_PCI_CSR_MS (1<<1) /* target memory enable */ +# define UNIV_PCI_CSR_IOS (1<<0) /* target IO enable */ + +/* Special cycle (ADOH, RMW) control register */ +#define UNIV_REGOFF_SCYC_CTL 0x170 /* write 0 to disable */ +# define UNIV_SCYC_CTL_LAS_IO (1<<2) /* PCI address space (1: IO, 0: mem) */ +# define UNIV_SCYC_CTL_SCYC_RMW (1<<0) /* do a RMW cycle when reading PCI address */ +# define UNIV_SCYC_CTL_SCYC_ADOH (2<<0) /* do a ADOH cycle when reading/writing PCI address */ + +/* Special cycle address register */ +#define UNIV_REGOFF_SCYC_ADDR 0x174 /* PCI address (must be long word aligned) */ + +/* Special cycle Swap/Compare/Enable */ +#define UNIV_REGOFF_SCYC_EN 0x178 /* mask determining the bits involved in the compare and swap operations for VME RMW cycles */ + +/* Special cycle compare data register */ +#define UNIV_REGOFF_SCYC_CMP 0x17c /* data to compare with word returned from VME RMW read */ + +/* Special cycle swap data register */ +#define UNIV_REGOFF_SCYC_SWP 0x180 /* If enabled bits of CMP match, corresponding SWP bits are written back to VME (under control of EN) */ + +/* PCI miscellaneous register */ +#define UNIV_REGOFF_LMISC 0x184 +# define UNIV_LMISC_CRT_MASK (7<<28) /* Univ. I only, not used on II */ +# define UNIV_LMISC_CRT_INF (0<<28) /* Coupled Request Timeout */ +# define UNIV_LMISC_CRT_128_US (1<<28) /* Coupled Request Timeout */ +# define UNIV_LMISC_CRT_256_US (2<<28) /* Coupled Request Timeout */ +# define UNIV_LMISC_CRT_512_US (3<<28) /* Coupled Request Timeout */ +# define UNIV_LMISC_CRT_1024_US (4<<28) /* Coupled Request Timeout */ +# define UNIV_LMISC_CRT_2048_US (5<<28) /* Coupled Request Timeout */ +# define UNIV_LMISC_CRT_4096_US (6<<28) /* Coupled Request Timeout */ + +# define UNIV_LMISC_CWT_MASK (7<<24) /* coupled window timer */ +# define UNIV_LMISC_CWT_DISABLE 0 /* disabled (release VME after 1 coupled xaction) */ +# define UNIV_LMISC_CWT_16 (1<<24) /* 16 PCI clock cycles */ +# define UNIV_LMISC_CWT_32 (2<<24) /* 32 PCI clock cycles */ +# define UNIV_LMISC_CWT_64 (3<<24) /* 64 PCI clock cycles */ +# define UNIV_LMISC_CWT_128 (4<<24) /* 128 PCI clock cycles */ +# define UNIV_LMISC_CWT_256 (5<<24) /* 256 PCI clock cycles */ +# define UNIV_LMISC_CWT_512 (6<<24) /* 512 PCI clock cycles */ + +/* PCI Command Error Log Register */ +#define UNIV_REGOFF_L_CMDERR 0x18c +# define UNIV_L_CMDERR_CMDERR(reg) (((reg)>>28)&0xf) /* extract PCI cmd error log */ +# define UNIV_L_CMDERR_M_ERR (1<<27) /* multiple errors have occurred */ +# define UNIV_L_CMDERR_L_STAT (1<<23) /* PCI error log status valid (write 1 to clear and enable logging) */ + +/* PCI Address Error Log */ +#define UNIV_REGOFF_LAERR 0x190 /* PCI fault address (if L_CMDERR_L_STAT valid) */ +/* DMA Xfer Control Register */ +#define UNIV_REGOFF_DCTL 0x200 +# define UNIV_DCTL_L2V (1<<31) /* PCI->VME if set */ +# define UNIV_DCTL_VDW_MSK (3<<22) /* VME max. width mask 0x00c00000 */ +# define UNIV_DCTL_VDW_8 (0<<22) /* VME max. width 8 */ +# define UNIV_DCTL_VDW_16 (1<<22) /* VME max. width 16 */ +# define UNIV_DCTL_VDW_32 (2<<22) /* VME max. width 32 */ +# define UNIV_DCTL_VDW_64 (3<<22) /* VME max. width 64 */ +# define UNIV_DCTL_VAS_MSK (7<<16) /* VME AS mask 0x00070000 */ +# define UNIV_DCTL_VAS_A16 (0<<16) /* VME A16 */ +# define UNIV_DCTL_VAS_A24 (1<<16) /* VME A24 */ +# define UNIV_DCTL_VAS_A32 (2<<16) /* VME A32 */ +# define UNIV_DCTL_PGM_MSK (3<<14) /* VME PGM/DATA mask 0x0000c000 */ +# define UNIV_DCTL_PGM (1<<14) /* VME PGM(1)/DATA(0) */ +# define UNIV_DCTL_SUPER_MSK (3<<12) /* VME SUPER/USR mask 0x00003000 */ +# define UNIV_DCTL_SUPER (1<<12) /* VME SUPER(1)/USR(0) */ +# define UNIV_DCTL_NO_VINC (1<<9) /* VME no VME address increment [Universe IIa/b ONLY */ +# define UNIV_DCTL_VCT (1<<8) /* VME enable BLT */ +# define UNIV_DCTL_LD64EN (1<<7) /* PCI 64 enable */ + +/* DMA Xfer byte count register (is updated by DMA) */ +#define UNIV_REGOFF_DTBC 0x204 +/* DMA Xfer local (PCI) address (direction is set in DCTL) */ +#define UNIV_REGOFF_DLA 0x208 +/* DMA Xfer VME address (direction is set in DCTL) + * NOTE: (*UNIV_DVA) & ~7 == (*UNIV_DLA) & ~7 MUST HOLD + */ +#define UNIV_REGOFF_DVA 0x210 + +/* DMA Xfer VME command packet pointer + * NOTE: The address stored here MUST be 32-byte aligned + */ +#define UNIV_REGOFF_DCPP 0x218 +/* these bits are only used in linked lists */ +# define UNIV_DCPP_IMG_NULL (1<<0) /* last packet in list */ +# define UNIV_DCPP_IMG_PROCESSED (1<<1) /* packet processed */ + +/* DMA Xfer General Control/Status register */ +#define UNIV_REGOFF_DGCS 0x220 +# define UNIV_DGCS_GO (1<<31) /* start xfer */ +# define UNIV_DGCS_STOP_REQ (1<<30) /* stop xfer (immediate abort) */ +# define UNIV_DGCS_HALT_REQ (1<<29) /* halt xfer (abort after current packet) */ +# define UNIV_DGCS_CHAIN (1<<27) /* enable linked list mode */ +# define UNIV_DGCS_VON_MSK (7<<20) /* VON mask */ +# define UNIV_DGCS_VON_DONE (0<<20) /* VON counter disabled (do until done) */ +# define UNIV_DGCS_VON_256 (1<<20) /* VON yield bus after 256 bytes */ +# define UNIV_DGCS_VON_512 (2<<20) /* VON yield bus after 512 bytes */ +# define UNIV_DGCS_VON_1024 (3<<20) /* VON yield bus after 1024 bytes */ +# define UNIV_DGCS_VON_2048 (4<<20) /* VON yield bus after 2048 bytes */ +# define UNIV_DGCS_VON_4096 (5<<20) /* VON yield bus after 4096 bytes */ +# define UNIV_DGCS_VON_8192 (6<<20) /* VON yield bus after 8192 bytes */ +# define UNIV_DGCS_VON_16384 (7<<20) /* VON yield bus after 16384 bytes */ +# define UNIV_DGCS_VOFF_MSK (15<<16) /* VOFF mask */ +# define UNIV_DGCS_VOFF_0_US (0<<16) /* re-request VME master after 0 us */ +# define UNIV_DGCS_VOFF_2_US (8<<16) /* re-request VME master after 2 us */ +# define UNIV_DGCS_VOFF_4_US (9<<16) /* re-request VME master after 4 us */ +# define UNIV_DGCS_VOFF_8_US (10<<16)/* re-request VME master after 8 us */ +# define UNIV_DGCS_VOFF_16_US (1<<16) /* re-request VME master after 16 us */ +# define UNIV_DGCS_VOFF_32_US (2<<16) /* re-request VME master after 32 us */ +# define UNIV_DGCS_VOFF_64_US (3<<16) /* re-request VME master after 64 us */ +# define UNIV_DGCS_VOFF_128_US (4<<16) /* re-request VME master after 128 us */ +# define UNIV_DGCS_VOFF_256_US (5<<16) /* re-request VME master after 256 us */ +# define UNIV_DGCS_VOFF_512_US (6<<16) /* re-request VME master after 512 us */ +# define UNIV_DGCS_VOFF_1024_US (7<<16) /* re-request VME master after 1024 us */ +/* Status Bits (write 1 to clear) */ +# define UNIV_DGCS_ACT (1<<15) /* DMA active */ +# define UNIV_DGCS_STOP (1<<14) /* DMA stopped */ +# define UNIV_DGCS_HALT (1<<13) /* DMA halted */ +# define UNIV_DGCS_DONE (1<<11) /* DMA done (OK) */ +# define UNIV_DGCS_LERR (1<<10) /* PCI bus error */ +# define UNIV_DGCS_VERR (1<<9) /* VME bus error */ +# define UNIV_DGCS_P_ERR (1<<8) /* programming protocol error (e.g. PCI master disabled) */ +# define UNIV_DGCS_STATUS_CLEAR\ + (UNIV_DGCS_ACT|UNIV_DGCS_STOP|UNIV_DGCS_HALT|\ + UNIV_DGCS_DONE|UNIV_DGCS_LERR|UNIV_DGCS_VERR|UNIV_DGCS_P_ERR) +# define UNIV_DGCS_P_ERR (1<<8) /* programming protocol error (e.g. PCI master disabled) */ +/* Interrupt Mask Bits */ +# define UNIV_DGCS_INT_STOP (1<<6) /* interrupt when stopped */ +# define UNIV_DGCS_INT_HALT (1<<5) /* interrupt when halted */ +# define UNIV_DGCS_INT_DONE (1<<3) /* interrupt when done */ +# define UNIV_DGCS_INT_LERR (1<<2) /* interrupt on LERR */ +# define UNIV_DGCS_INT_VERR (1<<1) /* interrupt on VERR */ +# define UNIV_DGCS_INT_P_ERR (1<<0) /* interrupt on P_ERR */ +# define UNIV_DGCS_INT_MSK (0x0000006f) /* interrupt mask */ + +/* DMA Linked List Update Enable Register */ +#define UNIV_REGOFF_D_LLUE 0x224 +# define UNIV_D_LLUE_UPDATE (1<<31) + + +/* PCI (local) interrupt enable register */ +#define UNIV_REGOFF_LINT_EN 0x300 +# define UNIV_LINT_EN_LM3 (1<<23) /* location monitor 3 mask */ +# define UNIV_LINT_EN_LM2 (1<<22) /* location monitor 2 mask */ +# define UNIV_LINT_EN_LM1 (1<<21) /* location monitor 1 mask */ +# define UNIV_LINT_EN_LM0 (1<<20) /* location monitor 0 mask */ +# define UNIV_LINT_EN_MBOX3 (1<<19) /* mailbox 3 mask */ +# define UNIV_LINT_EN_MBOX2 (1<<18) /* mailbox 2 mask */ +# define UNIV_LINT_EN_MBOX1 (1<<17) /* mailbox 1 mask */ +# define UNIV_LINT_EN_MBOX0 (1<<16) /* mailbox 0 mask */ +# define UNIV_LINT_EN_ACFAIL (1<<15) /* ACFAIL irq mask */ +# define UNIV_LINT_EN_SYSFAIL (1<<14) /* SYSFAIL irq mask */ +# define UNIV_LINT_EN_SW_INT (1<<13) /* PCI (local) software irq */ +# define UNIV_LINT_EN_SW_IACK (1<<12) /* VME software IACK mask */ +# define UNIV_LINT_EN_VERR (1<<10) /* PCI VERR irq mask */ +# define UNIV_LINT_EN_LERR (1<<9) /* PCI LERR irq mask */ +# define UNIV_LINT_EN_DMA (1<<8) /* PCI DMA irq mask */ +# define UNIV_LINT_EN_VIRQ7 (1<<7) /* VIRQ7 mask (universe does IACK automatically) */ +# define UNIV_LINT_EN_VIRQ6 (1<<6) /* VIRQ6 mask */ +# define UNIV_LINT_EN_VIRQ5 (1<<5) /* VIRQ5 mask */ +# define UNIV_LINT_EN_VIRQ4 (1<<4) /* VIRQ4 mask */ +# define UNIV_LINT_EN_VIRQ3 (1<<3) /* VIRQ3 mask */ +# define UNIV_LINT_EN_VIRQ2 (1<<2) /* VIRQ2 mask */ +# define UNIV_LINT_EN_VIRQ1 (1<<1) /* VIRQ1 mask */ +# define UNIV_LINT_EN_VOWN (1<<0) /* VOWN mask */ + +/* PCI (local) interrupt status register */ +#define UNIV_REGOFF_LINT_STAT 0x304 +# define UNIV_LINT_STAT_LM3 (1<<23) /* location monitor 3 status */ +# define UNIV_LINT_STAT_LM2 (1<<22) /* location monitor 2 status */ +# define UNIV_LINT_STAT_LM1 (1<<21) /* location monitor 1 status */ +# define UNIV_LINT_STAT_LM0 (1<<20) /* location monitor 0 status */ +# define UNIV_LINT_STAT_MBOX3 (1<<19) /* mailbox 3 status */ +# define UNIV_LINT_STAT_MBOX2 (1<<18) /* mailbox 2 status */ +# define UNIV_LINT_STAT_MBOX1 (1<<17) /* mailbox 1 status */ +# define UNIV_LINT_STAT_MBOX0 (1<<16) /* mailbox 0 status */ +# define UNIV_LINT_STAT_ACFAIL (1<<15) /* ACFAIL irq status */ +# define UNIV_LINT_STAT_SYSFAIL (1<<14) /* SYSFAIL irq status */ +# define UNIV_LINT_STAT_SW_INT (1<<13) /* PCI (local) software irq */ +# define UNIV_LINT_STAT_SW_IACK (1<<12) /* VME software IACK status */ +# define UNIV_LINT_STAT_VERR (1<<10) /* PCI VERR irq status */ +# define UNIV_LINT_STAT_LERR (1<<9) /* PCI LERR irq status */ +# define UNIV_LINT_STAT_DMA (1<<8) /* PCI DMA irq status */ +# define UNIV_LINT_STAT_VIRQ7 (1<<7) /* VIRQ7 status */ +# define UNIV_LINT_STAT_VIRQ6 (1<<6) /* VIRQ6 status */ +# define UNIV_LINT_STAT_VIRQ5 (1<<5) /* VIRQ5 status */ +# define UNIV_LINT_STAT_VIRQ4 (1<<4) /* VIRQ4 status */ +# define UNIV_LINT_STAT_VIRQ3 (1<<3) /* VIRQ3 status */ +# define UNIV_LINT_STAT_VIRQ2 (1<<2) /* VIRQ2 status */ +# define UNIV_LINT_STAT_VIRQ1 (1<<1) /* VIRQ1 status */ +# define UNIV_LINT_STAT_VOWN (1<<0) /* VOWN status */ +# define UNIV_LINT_STAT_CLR (0xfff7ff)/* Clear all status bits */ + +/* PCI (local) interrupt map 0 register */ +#define UNIV_REGOFF_LINT_MAP0 0x308 /* mapping of VME IRQ sources to PCI irqs */ +# define UNIV_LINT_MAP0_VIRQ7(lint) (((lint)&0x7)<<(7*4)) +# define UNIV_LINT_MAP0_VIRQ6(lint) (((lint)&0x7)<<(6*4)) +# define UNIV_LINT_MAP0_VIRQ5(lint) (((lint)&0x7)<<(5*4)) +# define UNIV_LINT_MAP0_VIRQ4(lint) (((lint)&0x7)<<(4*4)) +# define UNIV_LINT_MAP0_VIRQ3(lint) (((lint)&0x7)<<(3*4)) +# define UNIV_LINT_MAP0_VIRQ2(lint) (((lint)&0x7)<<(2*4)) +# define UNIV_LINT_MAP0_VIRQ1(lint) (((lint)&0x7)<<(1*4)) +# define UNIV_LINT_MAP0_VOWN(lint) (((lint)&0x7)<<(0*4)) + +#define UNIV_REGOFF_LINT_MAP1 0x30c /* mapping of internal / VME IRQ sources to PCI irqs */ +# define UNIV_LINT_MAP1_ACFAIL(lint) (((lint)&0x7)<<(7*4)) +# define UNIV_LINT_MAP1_SYSFAIL(lint) (((lint)&0x7)<<(6*4)) +# define UNIV_LINT_MAP1_SW_INT(lint) (((lint)&0x7)<<(5*4)) +# define UNIV_LINT_MAP1_SW_IACK(lint) (((lint)&0x7)<<(4*4)) +# define UNIV_LINT_MAP1_VERR(lint) (((lint)&0x7)<<(2*4)) +# define UNIV_LINT_MAP1_LERR(lint) (((lint)&0x7)<<(1*4)) +# define UNIV_LINT_MAP1_DMA(lint) (((lint)&0x7)<<(0*4)) + +/* enabling of generation of VME bus IRQs, TODO */ +#define UNIV_REGOFF_VINT_EN 0x310 +# define UNIV_VINT_EN_DISABLE_ALL 0 +# define UNIV_VINT_EN_SWINT (1<<12) +# define UNIV_VINT_EN_SWINT_LVL(l) (1<<(((l)&7)+24)) /* universe II only */ + + +/* status of generation of VME bus IRQs */ +#define UNIV_REGOFF_VINT_STAT 0x314 +# define UNIV_VINT_STAT_LINT(lint) (1<<((lint)&7)) +# define UNIV_VINT_STAT_LINT_MASK (0xff) +# define UNIV_VINT_STAT_CLR (0xfe0f17ff) +# define UNIV_VINT_STAT_SWINT(l) (1<<(((l)&7)+24)) + +#define UNIV_REGOFF_VINT_MAP0 0x318 /* VME destination of PCI IRQ source, TODO */ + +#define UNIV_REGOFF_VINT_MAP1 0x31c /* VME destination of PCI IRQ source, TODO */ +# define UNIV_VINT_MAP1_SWINT(level) (((level)&0x7)<<16) + +/* NOTE: The universe seems to always set LSB (which has a special purpose in + * the STATID register: enable raising a SW_INT on IACK) on the + * vector it puts out on the bus... + */ +#define UNIV_REGOFF_VINT_STATID 0x320 /* our status/id response to IACK, TODO */ +# define UNIV_VINT_STATID(id) ((id)<<24) + +#define UNIV_REGOFF_VIRQ1_STATID 0x324 /* status/id of VME IRQ level 1 */ +#define UNIV_REGOFF_VIRQ2_STATID 0x328 /* status/id of VME IRQ level 2 */ +#define UNIV_REGOFF_VIRQ3_STATID 0x32c /* status/id of VME IRQ level 3 */ +#define UNIV_REGOFF_VIRQ4_STATID 0x330 /* status/id of VME IRQ level 4 */ +#define UNIV_REGOFF_VIRQ5_STATID 0x334 /* status/id of VME IRQ level 5 */ +#define UNIV_REGOFF_VIRQ6_STATID 0x338 /* status/id of VME IRQ level 6 */ +#define UNIV_REGOFF_VIRQ7_STATID 0x33c /* status/id of VME IRQ level 7 */ +# define UNIV_VIRQ_ERR (1<<8) /* set if universe encountered a bus error when doing IACK */ +# define UNIV_VIRQ_STATID_MASK (0xff) + +#define UNIV_REGOFF_LINT_MAP2 0x340 /* mapping of internal sources to PCI irqs */ +# define UNIV_LINT_MAP2_LM3(lint) (((lint)&0x7)<<7*4) /* location monitor 3 */ +# define UNIV_LINT_MAP2_LM2(lint) (((lint)&0x7)<<6*4) /* location monitor 2 */ +# define UNIV_LINT_MAP2_LM1(lint) (((lint)&0x7)<<5*4) /* location monitor 1 */ +# define UNIV_LINT_MAP2_LM0(lint) (((lint)&0x7)<<4*4) /* location monitor 0 */ +# define UNIV_LINT_MAP2_MBOX3(lint) (((lint)&0x7)<<3*4) /* mailbox 3 */ +# define UNIV_LINT_MAP2_MBOX2(lint) (((lint)&0x7)<<2*4) /* mailbox 2 */ +# define UNIV_LINT_MAP2_MBOX1(lint) (((lint)&0x7)<<1*4) /* mailbox 1 */ +# define UNIV_LINT_MAP2_MBOX0(lint) (((lint)&0x7)<<0*4) /* mailbox 0 */ + +#define UNIV_REGOFF_VINT_MAP2 0x344 /* mapping of internal sources to VME irqs */ +# define UNIV_VINT_MAP2_MBOX3(vint) (((vint)&0x7)<<3*4) /* mailbox 3 */ +# define UNIV_VINT_MAP2_MBOX2(vint) (((vint)&0x7)<<2*4) /* mailbox 2 */ +# define UNIV_VINT_MAP2_MBOX1(vint) (((vint)&0x7)<<1*4) /* mailbox 1 */ +# define UNIV_VINT_MAP2_MBOX0(vint) (((vint)&0x7)<<0*4) /* mailbox 0 */ + +#define UNIV_REGOFF_MBOX0 0x348 /* mailbox 0 */ +#define UNIV_REGOFF_MBOX1 0x34c /* mailbox 1 */ +#define UNIV_REGOFF_MBOX2 0x350 /* mailbox 2 */ +#define UNIV_REGOFF_MBOX3 0x354 /* mailbox 3 */ + +#define UNIV_REGOFF_SEMA0 0x358 /* semaphore 0 */ +#define UNIV_REGOFF_SEMA1 0x35c /* semaphore 0 */ +/* TODO define semaphore register bits */ + +#define UNIV_REGOFF_MAST_CTL 0x400 /* master control register */ +# define UNIV_MAST_CTL_MAXRTRY(val) (((val)&0xf)<<7*4) /* max # of pci master retries */ +# define UNIV_MAST_CTL_PWON(val) (((val)&0xf)<<6*4) /* posted write xfer count */ +# define UNIV_MAST_CTL_VRL(val) (((val)&0x3)<<22) /* VME bus request level */ +# define UNIV_MAST_CTL_VRM (1<<21) /* bus request mode (demand = 0, fair = 1) */ +# define UNIV_MAST_CTL_VREL (1<<20) /* bus release mode (when done = 0, on request = 1) */ +# define UNIV_MAST_CTL_VOWN (1<<19) /* bus ownership (release = 0, acquire/hold = 1) */ +# define UNIV_MAST_CTL_VOWN_ACK (1<<18) /* bus ownership (not owned = 0, acquired/held = 1) */ +# define UNIV_MAST_CTL_PABS(val) (((val)&0x3)<<3*4) /* PCI aligned burst size (32,64,128 byte / 0x3 is reserved) */ +# define UNIV_MAST_CTL_BUS_NO(val) (((val)&0xff)<<0*4) /* PCI bus number */ + +#define UNIV_REGOFF_MISC_CTL 0x404 /* misc control register */ +# define UNIV_MISC_CTL_VBTO(val) (((val)&0x7)<<7*4) /* VME bus timeout (0=disable, 16*2^(val-1) us) */ +# define UNIV_MISC_CTL_VARB (1<<26) /* VME bus arbitration mode (0=round robin, 1= priority) */ +# define UNIV_MISC_CTL_VARBTO(val) (((val)&0x3)<<6*4) /* arbitration time out: disable, 16us, 256us, reserved */ +# define UNIV_MISC_CTL_SW_LRST (1<<23) /* software PCI reset */ +# define UNIV_MISC_CTL_SW_SYSRST (1<<22) /* software VME reset */ +# define UNIV_MISC_CTL_BI (1<<20) /* BI mode */ +# define UNIV_MISC_CTL_ENGBI (1<<19) /* enable global BI mode initiator */ +# define UNIV_MISC_CTL_SYSCON (1<<17) /* (R/W) 1:universe is system controller */ +# define UNIV_MISC_CTL_V64AUTO (1<<16) /* (R/W) 1:initiate VME64 auto id slave participation */ + +/* U2SPEC described in VGM manual */ +/* NOTE: the Joerger vtr10012_8 needs the timing to be tweaked!!!! READt27 must be _no_delay_ + */ +#define UNIV_REGOFF_U2SPEC 0x4fc +# define UNIV_U2SPEC_DTKFLTR (1<<12) /* DTAck filter: 0: slow, better filter; 1: fast, poorer filter */ +# define UNIV_U2SPEC_MASt11 (1<<10) /* Master parameter t11 (DS hi time during BLT and MBLTs) */ +# define UNIV_U2SPEC_READt27_DEFAULT (0<<8) /* VME master parameter t27: (latch data after DTAck + 25ns) */ +# define UNIV_U2SPEC_READt27_FAST (1<<8) /* VME master parameter t27: (latch data faster than 25ns) */ +# define UNIV_U2SPEC_READt27_NODELAY (2<<8) /* VME master parameter t27: (latch data without any delay) */ +# define UNIV_U2SPEC_POSt28_FAST (1<<2) /* VME slave parameter t28: (faster time of DS to DTAck for posted write) */ +# define UNIV_U2SPEC_PREt28_FAST (1<<0) /* VME slave parameter t28: (faster time of DS to DTAck for prefetch read) */ + +/* Location Monitor control register */ +#define UNIV_REGOFF_LM_CTL 0xf64 +# define UNIV_LM_CTL_EN (1<<31) /* image enable */ +# define UNIV_LM_CTL_PGM (1<<23) /* program AM */ +# define UNIV_LM_CTL_DATA (1<<22) /* data AM */ +# define UNIV_LM_CTL_SUPER (1<<21) /* supervisor AM */ +# define UNIV_LM_CTL_USER (1<<20) /* user AM */ +# define UNIV_LM_CTL_VAS_A16 (0<<16) /* A16 */ +# define UNIV_LM_CTL_VAS_A24 (1<<16) /* A16 */ +# define UNIV_LM_CTL_VAS_A32 (2<<16) /* A16 */ + +/* Location Monitor base address */ +#define UNIV_REGOFF_LM_BS 0xf68 + +/* VMEbus register access image control register */ +#define UNIV_REGOFF_VRAI_CTL 0xf70 +# define UNIV_VRAI_CTL_EN (1<<31) /* image enable */ +# define UNIV_VRAI_CTL_PGM (1<<23) /* program AM */ +# define UNIV_VRAI_CTL_DATA (1<<22) /* data AM */ +# define UNIV_VRAI_CTL_SUPER (1<<21) /* supervisor AM */ +# define UNIV_VRAI_CTL_USER (1<<20) /* user AM */ +# define UNIV_VRAI_CTL_VAS_A16 (0<<16) /* A16 */ +# define UNIV_VRAI_CTL_VAS_A24 (1<<16) /* A14 */ +# define UNIV_VRAI_CTL_VAS_A32 (2<<16) /* A32 */ +# define UNIV_VRAI_CTL_VAS_MSK (3<<16) + +/* VMEbus register acces image base address register */ +#define UNIV_REGOFF_VRAI_BS 0xf74 + +/* VMEbus CSR control register */ +#define UNIV_REGOFF_VCSR_CTL 0xf80 +# define UNIV_VCSR_CTL_EN (1<<31) /* image enable */ +# define UNIV_VCSR_CTL_LAS_PCI_MEM (0<<0) /* pci mem space */ +# define UNIV_VCSR_CTL_LAS_PCI_IO (1<<0) /* pci IO space */ +# define UNIV_VCSR_CTL_LAS_PCI_CFG (2<<0) /* pci config space */ + +/* VMEbus CSR translation offset */ +#define UNIV_REGOFF_VCSR_TO 0xf84 + +/* VMEbus AM code error log */ +#define UNIV_REGOFF_V_AMERR 0xf88 +# define UNIV_V_AMERR_AMERR(reg) (((reg)>>26)&0x3f) /* extract error log code */ +# define UNIV_V_AMERR_IACK (1<<25) /* VMEbus IACK signal */ +# define UNIV_V_AMERR_M_ERR (1<<24) /* multiple errors occurred */ +# define UNIV_V_AMERR_V_STAT (1<<23) /* log status valid (write 1 to clear) */ + +/* VMEbus address error log */ +#define UNIV_REGOFF_VAERR 0xf8c /* address of fault address (if MERR_V_STAT valid) */ + +/* VMEbus CSR bit clear register */ +#define UNIV_REGOFF_VCSR_CLR 0xff4 +# define UNIV_VCSR_CLR_RESET (1<<31) /* read/negate LRST (can only be written from VME bus */ +# define UNIV_VCSR_CLR_SYSFAIL (1<<30) /* read/negate SYSFAIL */ +# define UNIV_VCSR_CLR_FAIL (1<<29) /* read: board has failed */ + +/* VMEbus CSR bit set register */ +#define UNIV_REGOFF_VCSR_SET (0xff8) +# define UNIV_VCSR_SET_RESET (1<<31) /* read/assert LRST (can only be written from VME bus */ +# define UNIV_VCSR_SET_SYSFAIL (1<<30) /* read/assert SYSFAIL */ +# define UNIV_VCSR_SET_FAIL (1<<29) /* read: board has failed */ + +/* VMEbus CSR base address register */ +#define UNIV_REGOFF_VCSR_BS 0xffc +#define UNIV_VCSR_BS_MASK (0xf8000000) + +/* offset of universe registers in VME-CSR slot */ +#define UNIV_CSR_OFFSET 0x7f000 + +#ifdef __cplusplus +extern "C" { +#endif + +/* base address and IRQ line of 1st universe bridge + * NOTE: vmeUniverseInit() must be called before + * these may be used. + */ +extern volatile LERegister *vmeUniverse0BaseAddr; +extern int vmeUniverse0PciIrqLine; + + +/* Initialize the driver */ +int +vmeUniverseInit(void); + +/* setup the universe chip, i.e. disable most of its + * mappings, reset interrupts etc. + */ +void +vmeUniverseReset(void); + +/* avoid pulling stdio.h into this header. + * Applications that want a declaration of the + * following routines should + * #include <stdio.h> + * #define _VME_UNIVERSE_DECLARE_SHOW_ROUTINES + * #include <vmeUniverse.h> + */ +/* print the current configuration of all master ports to + * f (stderr if NULL) + */ +void +vmeUniverseMasterPortsShow(FILE *f); + +/* print the current configuration of all slave ports to + * f (stderr if NULL) + */ +void +vmeUniverseSlavePortsShow(FILE *f); + +/* disable all master or slave ports, respectively */ +void +vmeUniverseDisableAllMasters(void); + +void +vmeUniverseDisableAllSlaves(void); + +/* configure a master port + * + * port: port number 0..3 (0..7 for a UniverseII) + * + * address_space: vxWorks compliant addressing mode identifier + * (see vme.h). The most important are: + * 0x0d - A32, Sup, Data + * 0x3d - A24, Sup, Data + * 0x2d - A16, Sup, Data + * additionally, the value 0 is accepted; it will + * disable this port. + * vme_address: address on the vme_bus of this port. + * local_address: address on the pci_bus of this port. + * length: size of this port. + * + * NOTE: the addresses and length parameters must be aligned on a + * 2^16 byte (0x10000) boundary, except for port 4 (only available + * on a UniverseII), where the alignment can be 4k (4096). + * + * RETURNS: 0 on success, -1 on failure. Error messages printed to stderr. + */ + +int +vmeUniverseMasterPortCfg( + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long local_address, + unsigned long length); + +/* translate an address through the bridge + * + * vmeUniverseXlateAddr(0,0,as,addr,&result) + * yields a VME a address that reflects + * a local memory location as seen from the VME bus through the universe + * VME slave. + * + * likewise does vmeUniverseXlateAddr(1,0,as,addr,&result) + * translate a VME bus addr (through the VME master) to the + * PCI side of the bridge. + * + * a valid address space modifier must be specified. + * + * The 'reverse' parameter may be used to find a reverse + * mapping, i.e. the pci address in a master window can be + * found if the respective vme address is known etc. + * + * RETURNS: translated address in *pbusAdrs / *plocalAdrs + * + * 0: success + * -1: address/modifier not found in any bridge port + * -2: invalid modifier + */ +int +vmeUniverseXlateAddr( + int master, /* look in the master windows */ + int reverse, /* reverse mapping; for masters: map local to VME */ + unsigned long as, /* address space */ + unsigned long addr, /* address to look up */ + unsigned long *paOut/* where to put result */ + ); + +/* configure a VME slave (PCI master) port */ +int +vmeUniverseSlavePortCfg( + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long local_address, + unsigned long length); + +/****** NOTE: USE OF vmeUniverseStartDMA IS DEPRECATED ********* + ****** USE API IN VMEDMA.h/vmeUniverseDMA.h INSTEAD *********/ + +/* start a (direct, not linked) DMA transfer + * + * NOTE: DCTL and DGCS must be set up + * prior to calling this routine + */ +int +vmeUniverseStartDMA( + unsigned long local_addr, + unsigned long vme_addr, + unsigned long count); /* DEPRECATED */ + +int +vmeUniverseStartDMAXX( + volatile LERegister *ubase, + unsigned long local_addr, + unsigned long vme_addr, + unsigned long count); /* DEPRECATED */ + + +/* read a register in PCI memory space + * (offset being one of the declared constants) + */ +unsigned long +vmeUniverseReadReg(unsigned long offset); + +/* write a register in PCI memory space */ +void +vmeUniverseWriteReg(unsigned long value, unsigned long offset); + +/* convert an array of unsigned long values to LE (as needed + * when the universe reads e.g. DMA descriptors from PCI) + */ +void +vmeUniverseCvtToLE(unsigned long *ptr, unsigned long num); + +/* reset the VME bus */ +void +vmeUniverseResetBus(void); + +/* The ...XX routines take the universe base address as an additional + * argument - this allows for programming secondary devices. + */ + +unsigned long +vmeUniverseReadRegXX(volatile LERegister *ubase, unsigned long offset); + +void +vmeUniverseWriteRegXX(volatile LERegister *ubase, unsigned long value, unsigned long offset); + +int +vmeUniverseXlateAddrXX( + volatile LERegister *ubase, + int master, + int reverse, + unsigned long as, + unsigned long addr, + unsigned long *paOut + ); + +int +vmeUniverseMasterPortCfgXX( + volatile LERegister *ubase, + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long local_address, + unsigned long length); + +int +vmeUniverseSlavePortCfgXX( + volatile LERegister *ubase, + unsigned long port, + unsigned long address_space, + unsigned long vme_address, + unsigned long local_address, + unsigned long length); + +void +vmeUniverseDisableAllMastersXX(volatile LERegister *ubase); + +void +vmeUniverseDisableAllSlavesXX(volatile LERegister *ubase); + +/* print the current configuration of all master ports to + * f (stderr if NULL) + */ +void +vmeUniverseMasterPortsShowXX( + volatile LERegister *ubase,FILE *f); + +/* print the current configuration of all slave ports to + * f (stderr if NULL) + */ +void +vmeUniverseSlavePortsShowXX( + volatile LERegister *ubase,FILE *f); + +/* Raise a VME Interrupt at 'level' and respond with 'vector' to a + * handler on the VME bus. (The handler could be a different board + * or the universe itself - [only works with universe II]). + * + * Note that you could install a interrupt handler at UNIV_VME_SW_IACK_INT_VEC + * to be notified of an IACK cycle having completed. + * + * This routine is mainly FOR TESTING. + * + * NOTES: + * - several registers are modified: the vector is written to VINT_STATID + * and (universe 1 chip only) the level is written to the SW_INT bits + * int VINT_MAP1 + * - NO MUTUAL EXCLUSION PROTECTION (reads VINT_EN, modifies then writes back). + * If several users need access to VINT_EN and/or VINT_STATID (and VINT_MAP1 + * on the universe 1) it is their responsibility to serialize access. + * + * Arguments: + * 'level': interrupt level, 1..7 + * 'vector': vector number (0..254) that the universe puts on the bus in response to + * an IACK cycle. NOTE: the vector number *must be even* (hardware restriction + * of the universe -- it always clears the LSB when the interrupter is + * a software interrupt). + * + * RETURNS: + * 0: Success + * -1: Invalid argument (level not 1..7, vector odd or >= 256) + * -2: Interrupt 'level' already asserted (maybe nobody handles it). + * You can manually clear it be writing the respective bit in + * VINT_STAT. Make sure really nobody responds to avoid spurious + * interrupts (consult universe docs). + */ + +int +vmeUniverseIntRaiseXX(volatile LERegister *base, int level, unsigned vector); + +int +vmeUniverseIntRaise(int level, unsigned vector); + +/* Map internal register block to VME. + * + * This routine is intended for BSP implementors. The registers can be + * made accessible from VME so that the interrupt handler can flush the + * bridge FIFO (see below). The preferred method is by accessing VME CSR, + * though, if these are mapped [and the BSP provides an outbound window]. + * On the universe we can also disable posted writes in the 'ordinary' + * outbound windows. + * + * vme_base: VME address where the universe registers (4k) can be mapped. + * This VME address must fall into a range covered by + * any pre-configured outbound window. + * address_space: The desired VME address space. + * (all of SUP/USR/PGM/DATA are always accepted). + * + * See NOTES [vmeUniverseInstallIrqMgrAlt()] below for further information. + * + * RETURNS: 0 on success, nonzero on error. It is not possible (and results + * in a non-zero return code) to change the CRG VME address after + * initializing the interrupt manager as it uses the CRG. + */ +int +vmeUniverseMapCRGXX(volatile LERegister *base, unsigned long vme_base, unsigned long address_space); + +int +vmeUniverseMapCRG(unsigned long vme_base, unsigned long address_space); + + +#ifdef __rtems__ + +/* VME Interrupt Handler functionality */ + +/* we dont use the current RTEMS/BSP interrupt API for the + * following reasons: + * + * - RTEMS/BSP API does not pass an argument to the ISR :-( :-( + * - no separate vector space for VME vectors. Some vectors would + * have to overlap with existing PCI/ISA vectors. + * - RTEMS/BSP API allocates a structure for every possible vector + * - the irq_on(), irq_off() functions add more bloat than helping. + * They are (currently) only used by the framework to disable + * interrupts at the device level before removing a handler + * and to enable interrupts after installing a handler. + * These operations may as well be done by the driver itself. + * + * Hence, we maintain our own (VME) handler table and hook our PCI + * handler into the standard RTEMS/BSP environment. Our handler then + * dispatches VME interrupts. + */ + +typedef void (*VmeUniverseISR) (void *usrArg, unsigned long vector); + +/* use these special vectors to connect a handler to the + * universe specific interrupts (such as "DMA done", + * VOWN, error irqs etc.) + * NOTE: The wrapper clears all status LINT bits (except + * for regular VME irqs). Also note that it is the user's + * responsibility to enable the necessary interrupts in + * LINT_EN + * + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * DO NOT CHANGE THE ORDER OF THESE VECTORS - THE DRIVER + * DEPENDS ON IT + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * + */ +#define UNIV_VOWN_INT_VEC 256 +#define UNIV_DMA_INT_VEC 257 +#define UNIV_LERR_INT_VEC 258 +#define UNIV_VERR_INT_VEC 259 +/* 260 is reserved */ +#define UNIV_VME_SW_IACK_INT_VEC 261 +#define UNIV_PCI_SW_INT_VEC 262 +#define UNIV_SYSFAIL_INT_VEC 263 +#define UNIV_ACFAIL_INT_VEC 264 +#define UNIV_MBOX0_INT_VEC 265 +#define UNIV_MBOX1_INT_VEC 266 +#define UNIV_MBOX2_INT_VEC 267 +#define UNIV_MBOX3_INT_VEC 268 +#define UNIV_LM0_INT_VEC 269 +#define UNIV_LM1_INT_VEC 270 +#define UNIV_LM2_INT_VEC 271 +#define UNIV_LM3_INT_VEC 272 + +#define UNIV_NUM_INT_VECS 273 + + +/* install a handler for a VME vector + * RETURNS 0 on success, nonzero on failure. + */ +int +vmeUniverseInstallISR(unsigned long vector, VmeUniverseISR handler, void *usrArg); + +/* remove a handler for a VME vector. The vector and usrArg parameters + * must match the respective parameters used when installing the handler. + * RETURNS 0 on success, nonzero on failure. + */ +int +vmeUniverseRemoveISR(unsigned long vector, VmeUniverseISR handler, void *usrArg); + +/* query for the currently installed ISR and usr parameter at a given vector + * RETURNS: ISR or 0 (vector too big or no ISR installed) + */ +VmeUniverseISR +vmeUniverseISRGet(unsigned long vector, void **parg); + +/* utility routines to enable/disable a VME IRQ level. + * + * To enable/disable the internal interrupt sources (special vectors above) + * pass a vector argument > 255. + * + * RETURNS 0 on success, nonzero on failure + */ +int +vmeUniverseIntEnable(unsigned int level); +int +vmeUniverseIntDisable(unsigned int level); + +/* Check if an interrupt level or internal source is enabled: + * + * 'level': VME level 1..7 or internal special vector > 255 + * + * RETURNS: value > 0 if interrupt is currently enabled, + * zero if interrupt is currently disabled, + * -1 on error (invalid argument). + */ +int +vmeUniverseIntIsEnabled(unsigned int level); + + +/* Change the routing of IRQ 'level' to 'pin'. + * If the BSP connects more than one of the eight + * physical interrupt lines from the universe to + * the board's PIC then you may change the physical + * line a given 'level' is using. By default, + * all 7 VME levels use the first wire (pin==0) and + * all internal sources use the (optional) second + * wire (pin==1). + * This feature is useful if you want to make use of + * different hardware priorities of the PIC. Let's + * say you want to give IRQ level 7 the highest priority. + * You could then give 'pin 0' a higher priority (at the + * PIC) and 'pin 1' a lower priority and issue. + * + * for ( i=1; i<7; i++ ) vmeUniverseIntRoute(i, 1); + * + * PARAMETERS: + * 'level' : VME interrupt level '1..7' or one of + * the internal sources. Pass the internal + * source's vector number (>=256). + * 'pin' : a value of 0 routes the requested IRQ to + * the first line registered with the manager + * (vmeIrqUnivOut parameter), a value of 1 + * routes it to the alternate wire + * (specialIrqUnivOut) + * RETURNS: 0 on success, nonzero on error (invalid arguments) + * + * NOTES: - DONT change the universe 'map' registers + * directly. The driver caches routing internally. + * - support for the 'specialIrqUnivOut' wire is + * board dependent. If the board only provides + * a single physical wire from the universe to + * the PIC then the feature might not be available. + */ +int +vmeUniverseIntRoute(unsigned int level, unsigned int pin); + +/* Loopback test of the VME interrupt subsystem. + * - installs ISRs on 'vector' and on UNIV_VME_SW_IACK_INT_VEC + * - asserts VME interrupt 'level' + * - waits for both interrupts: 'ordinary' VME interrupt of 'level' and + * IACK completion interrupt ('special' vector UNIV_VME_SW_IACK_INT_VEC). + * + * NOTES: + * - make sure no other handler responds to 'level'. + * - make sure no ISR is installed on both vectors yet. + * - ISRs installed by this routine are removed after completion. + * - no concurrent access protection of all involved resources + * (levels, vectors and registers [see vmeUniverseIntRaise()]) + * is implemented. + * - this routine is intended for TESTING (when implementing new BSPs etc.). + * - one RTEMS message queue is temporarily used (created/deleted). + * - the universe 1 always yields a zero vector (VIRQx_STATID) in response + * to a self-generated VME interrupt. As a workaround, the routine + * only accepts a zero vector when running on a universe 1. + * + * RETURNS: + * 0: Success. + * -1: Invalid arguments. + * 1: Test failed (outstanding interrupts). + * rtems_status_code: Failed RTEMS directive. + */ +int +vmeUniverseIntLoopbackTst(int level, unsigned vector); + + +/* the universe interrupt handler is capable of routing all sorts of + * (VME) interrupts to 8 different lines (some of) which may be hooked up + * in a (board specific) way to a PIC. + * + * This driver only supports at most two lines. By default, it routes the + * 7 VME interrupts to the main line and optionally, it routes the 'special' + * interrupts generated by the universe itself (DMA done, VOWN etc.) + * to a second line. If no second line is available, all IRQs are routed + * to the main line. + * + * The routing of interrupts to the two lines can be modified (using + * the vmeUniverseIntRoute() call - see above - i.e., to make use of + * different hardware priorities of the two pins. + * + * Because the driver has no way to figure out which lines are actually + * wired to the PIC, this information has to be provided when installing + * the manager. + * + * Hence the manager sets up routing VME interrupts to 1 or 2 universe + * OUTPUTS. However, it must also be told to which PIC INPUTS they + * are wired. + * Optionally, the first PIC input line can be read from PCI config space + * but the second must be passed to this routine. Note that the info read + * from PCI config space is wrong for many boards! + * + * PARAMETERS: + * vmeIrqUnivOut: to which output pin (of the universe) should the 7 + * VME irq levels be routed. + * vmeIrqPicLine: specifies to which PIC input the 'main' output is + * wired. If passed a value < 0, the driver reads this + * information from PCI config space ("IRQ line"). + * specialIrqUnivOut: to which output pin (of the universe) should the + * internally irqs be routed. Use 'vmeIRQunivOut' + * if < 0. + * specialIrqPicLine: specifies to which PIC input the 'special' output + * pin is wired. The wiring of the 'vmeIRQunivOut' to + * the PIC is determined by reading PCI config space. + * + * RETURNS: 0 on success, -1 on failure. + * + */ + +/* This routine is outside of the __INSIDE_RTEMS_BSP__ test for bwrds compatibility ONLY */ +int +vmeUniverseInstallIrqMgr(int vmeIrqUnivOut, + int vmeIrqPicLine, + int specialIrqUnivOut, + int specialIrqPicLine); + + +#if defined(__INSIDE_RTEMS_BSP__) +#include <stdarg.h> + +/* up to 4 universe outputs are now supported by this alternate + * entry point. + * Terminate the vararg list (uni_pin/pic_pin pairs) with a + * '-1' uni_pin. + * E.g., the old interface is now just a wrapper to + * vmeUniverseInstallIrqMgrAlt(0, vmeUnivOut, vmePicLint, specUnivOut, specPicLine, -1); + * + * The 'IRQ_MGR_SHARED' flag uses the BSP_install_rtems_shared_irq_handler() + * API. CAVEAT: shared interrupts need RTEMS workspace, i.e., the + * VME interrupt manager can only be installed *after workspace is initialized* + * if 'shared' is nonzero (i.e., *not* from bspstart()). + * + * If 'PW_WORKAROUND' flag is set then the interrupt manager will try to + * find a way to access the control registers from VME so that the universe's + * posted write FIFO can be flushed after the user ISR returns: + * + * The installation routine looks first for CSR registers in CSR space (this + * requires: + * - a VME64 crate with autoid or geographical addressing + * - the firmware or BSP to figure out the slot number and program the CSR base + * in the universe. + * - the BSP to open an outbound window to CSR space. + * + * If CSR registers cannot be found then the installation routine looks for CRG registers: + * - BSP must map CRG on VME + * - CRG must be visible in outbound window + * CAVEAT: multiple boards with same BSP on single backplane must not map their CRG + * to the same address! + */ + +#define VMEUNIVERSE_IRQ_MGR_FLAG_SHARED 1 /* use shared interrupts */ +#define VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND 2 /* use shared interrupts */ + +int +vmeUniverseInstallIrqMgrAlt(int flags, int uni_pin0, int pic_pin0, ...); + +int +vmeUniverseInstallIrqMgrVa(int flags, int uni_pin0, int pic_pin0, va_list ap); + +#endif /* __INSIDE_RTEMS_BSP__ */ +#endif /* __rtems__ */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/vmeUniverseDMA.h b/bsps/include/bsp/vmeUniverseDMA.h new file mode 100644 index 0000000000..d0a3d6f0e7 --- /dev/null +++ b/bsps/include/bsp/vmeUniverseDMA.h @@ -0,0 +1,95 @@ +/** + * @file + * + * @ingroup shared_vmeuniversedma + * + * @brief vmeUniverseDMA Support + */ + +#ifndef VME_UNIVERSE_DMA_H +#define VME_UNIVERSE_DMA_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2006, 2007 + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ +#include <bsp/vmeUniverse.h> +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_vmeuniversedma vmeUniverseDMA Support + * + * @ingroup shared_vmeuniverse + * + * @brief vmeUniverseDMA Support Package + */ + +extern struct VMEDmaListClassRec_ vmeUniverseDmaListClass; + +int +vmeUniverseDmaSetupXX(volatile LERegister *base, int channel, uint32_t mode, uint32_t xfer_mode, void *custom); + +int +vmeUniverseDmaSetup(int channel, uint32_t mode, uint32_t xfer_mode, void *custom); + +int +vmeUniverseDmaStartXX(volatile LERegister *base, int channel, uint32_t pci_addr, uint32_t vme_addr, uint32_t n_bytes); + +int +vmeUniverseDmaStart(int channel, uint32_t pci_addr, uint32_t vme_addr, uint32_t n_bytes); + +uint32_t +vmeUniverseDmaStatusXX(volatile LERegister *base, int channel); + +uint32_t +vmeUniverseDmaStatus(int channel); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/bsp/vme_am_defs.h b/bsps/include/bsp/vme_am_defs.h new file mode 100644 index 0000000000..efa28b3aa0 --- /dev/null +++ b/bsps/include/bsp/vme_am_defs.h @@ -0,0 +1,198 @@ +/** + * @file + * + * @ingroup shared_vmeamdefs + * + * @brief vxworks compatible addressing modes + */ + +#ifndef VME_AM_DEFINITIONS_H +#define VME_AM_DEFINITIONS_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2002-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +/** + * @defgroup shared_vmeamdefs VME_AM_DEFS + * + * @ingroup shared_vmeuniverse + * + * @brief 64-bit *addresses* are not supported [data are]. + */ + +#ifndef VME_AM_STD_SUP_BLT +#define VME_AM_STD_SUP_BLT 0x3f +#endif +#ifndef VME_AM_STD_SUP_ASCENDING +#define VME_AM_STD_SUP_ASCENDING 0x3f +#endif +#ifndef VME_AM_STD_SUP_PGM +#define VME_AM_STD_SUP_PGM 0x3e +#endif +#ifndef VME_AM_STD_SUP_MBLT +#define VME_AM_STD_SUP_MBLT 0x3c +#endif +#ifndef VME_AM_STD_USR_BLT +#define VME_AM_STD_USR_BLT 0x3b +#endif +#ifndef VME_AM_STD_USR_ASCENDING +#define VME_AM_STD_USR_ASCENDING 0x3b +#endif +#ifndef VME_AM_STD_USR_PGM +#define VME_AM_STD_USR_PGM 0x3a +#endif +#ifndef VME_AM_STD_SUP_DATA +#define VME_AM_STD_SUP_DATA 0x3d +#endif +#ifndef VME_AM_STD_USR_DATA +#define VME_AM_STD_USR_DATA 0x39 +#endif +#ifndef VME_AM_STD_USR_MBLT +#define VME_AM_STD_USR_MBLT 0x38 +#endif +#ifndef VME_AM_EXT_SUP_BLT +#define VME_AM_EXT_SUP_BLT 0x0f +#endif +#ifndef VME_AM_EXT_SUP_ASCENDING +#define VME_AM_EXT_SUP_ASCENDING 0x0f +#endif +#ifndef VME_AM_EXT_SUP_PGM +#define VME_AM_EXT_SUP_PGM 0x0e +#endif +#ifndef VME_AM_EXT_SUP_DATA +#define VME_AM_EXT_SUP_DATA 0x0d +#endif +#ifndef VME_AM_EXT_SUP_MBLT +#define VME_AM_EXT_SUP_MBLT 0x0c +#endif +#ifndef VME_AM_EXT_USR_BLT +#define VME_AM_EXT_USR_BLT 0x0b +#endif +#ifndef VME_AM_EXT_USR_ASCENDING +#define VME_AM_EXT_USR_ASCENDING 0x0b +#endif +#ifndef VME_AM_EXT_USR_PGM +#define VME_AM_EXT_USR_PGM 0x0a +#endif +#ifndef VME_AM_EXT_USR_DATA +#define VME_AM_EXT_USR_DATA 0x09 +#endif +#ifndef VME_AM_EXT_USR_MBLT +#define VME_AM_EXT_USR_MBLT 0x08 +#endif +#ifndef VME_AM_2eVME_6U +#define VME_AM_2eVME_6U 0x20 +#endif +#ifndef VME_AM_2eVME_3U +#define VME_AM_2eVME_3U 0x21 +#endif +#ifndef VME_AM_CSR +#define VME_AM_CSR 0x2f +#endif +#ifndef VME_AM_SUP_SHORT_IO +#define VME_AM_SUP_SHORT_IO 0x2d +#endif +#ifndef VME_AM_USR_SHORT_IO +#define VME_AM_USR_SHORT_IO 0x29 +#endif +#ifndef VME_AM_IS_SHORT +#define VME_AM_IS_SHORT(a) (((a) & 0x30) == 0x20) +#endif +#ifndef VME_AM_IS_STD +#define VME_AM_IS_STD(a) (((a) & 0x30) == 0x30) +#endif +#ifndef VME_AM_IS_EXT +#define VME_AM_IS_EXT(a) (((a) & 0x30) == 0x00) +#endif +#ifndef VME_AM_IS_SUP +#define VME_AM_IS_SUP(a) ((a) & 4) +#endif + +/* Mask for standard address modifiers */ + +#ifndef VME_AM_MASK +#define VME_AM_MASK 0x3f +#endif + +/* Hint that a window is mapping memory; the + * driver may assume it to be safe to enable decoupled + * cycles, caching and the like... + */ +#ifndef VME_AM_IS_MEMORY +#define VME_AM_IS_MEMORY (1<<8) +#endif + +/* I don't know AMs for 2eSST so we use some extra bits; + * HOWEVER: these are just qualifiers to the VME_AM_2eVME_xx modes + * i.e., if you want 2eSST you must also select 2eVME... + */ + +/* 2eSST broadcast; you still need to set one of the speed bits */ +#define VME_AM_2eSST_BCST (1<<9) +/* Low speed (driver specific) */ +#define VME_AM_2eSST_LO (1<<10) +/* Mid speed (driver specific) */ +#define VME_AM_2eSST_MID (2<<10) +/* High speed (driver specific) */ +#define VME_AM_2eSST_HI (3<<10) + +#define VME_AM_IS_2eSST(am) ((am) & (3<<10)) + +/* Use 8/16/32-bit transfers for coupled- or BLT cycles + * (MBLT, 2exxx are probably always 64-bit) + */ +#define VME_MODE_DBW_MSK (3<<12) +#define VME_MODE_DBW8 (1<<12) +#define VME_MODE_DBW16 (2<<12) +#define VME_MODE_DBW32 (3<<12) + +/* Unused Flags 1<<14 .. 1<<23 are reserved + * + * (20-23 used by DMA API). + * Flags 1<<24 .. 1<<31 are for driver specific options + */ + + +#endif diff --git a/bsps/include/libchip/am29lv160.h b/bsps/include/libchip/am29lv160.h new file mode 100644 index 0000000000..49d8e248ac --- /dev/null +++ b/bsps/include/libchip/am29lv160.h @@ -0,0 +1,55 @@ +/* + * RTEMS Project (http://www.rtems.org/) + * + * Copyright 2007 Chris Johns (chrisj@rtems.org) + */ + +/** + * Flash Disk Device Driver. + * + * Am29LV160D 16 Megabit (2M x 8bit) 3.0 Volt-only + * Boot Sctor Flash Memory. + */ + +#if !defined (_RTEMS_AM29LV160_H_) +#define _RTEMS_AM29LV160_H_ + +#include <rtems/flashdisk.h> + +/** + * The segments in the AM29LV160 top boot block device. + */ +#define rtems_am29lv160t_segment_count (4) +extern const rtems_fdisk_segment_desc rtems_am29lv160t_segments[4]; + +/** + * The segments in the AM29LV160 bottom boot block device. + */ +#define rtems_am29lv160b_segment_count (4) +extern const rtems_fdisk_segment_desc rtems_am29lv160b_segments[4]; + +/** + * The segments in the AM29LV160 top boot block device. + */ +extern const rtems_fdisk_driver_handlers rtems_am29lv160_handlers; + +/** + * The device configuration. + */ +typedef struct rtems_am29lv160_config +{ + int bus_8bit; + void* base; +} rtems_am29lv160_config; + +/** + * External reference to the configuration. + */ +extern const rtems_am29lv160_config rtems_am29lv160_configuration[]; + +/** + * External reference to the configuration size + */ +extern uint32_t rtems_am29lv160_configuration_size; + +#endif diff --git a/bsps/include/libchip/ata.h b/bsps/include/libchip/ata.h new file mode 100644 index 0000000000..66cc46747d --- /dev/null +++ b/bsps/include/libchip/ata.h @@ -0,0 +1,50 @@ +/* + * ata.h + * + * ATA RTEMS driver header file. This file should be included from an + * application. + * + * Copyright (C) 2002 OKTET Ltd., St.-Petersburg, Russia + * Author: Eugeny S. Mints <Eugeny.Mints@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __ATA_H__ +#define __ATA_H__ + +#include <rtems.h> +#include <sys/ioctl.h> + +#include <rtems/blkdev.h> + +#ifdef __cplusplus +extern "C" { +#endif + +rtems_device_driver rtems_ata_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *args); + +#define ATA_DRIVER_TABLE_ENTRY \ + {rtems_ata_initialize, RTEMS_GENERIC_BLOCK_DEVICE_DRIVER_ENTRIES} + +/* ATA IOCTL request codes */ +#define ATAIO_SET_MULTIPLE_MODE _IO('A', 1) + +/* + * ATA driver configuration parameters + * FIXME: should be configured more easy... + */ +#define ATA_DRIVER_MESSAGE_QUEUE_SIZE 50 +#define ATA_DRIVER_TASK_STACK_SIZE 16*1024 +#define ATA_DRIVER_TASK_DEFAULT_PRIORITY 140 + extern rtems_task_priority rtems_ata_driver_task_priority; +#ifdef __cplusplus +} +#endif + + +#endif /* __ATA_H__ */ diff --git a/bsps/include/libchip/ata_internal.h b/bsps/include/libchip/ata_internal.h new file mode 100644 index 0000000000..985b6f597c --- /dev/null +++ b/bsps/include/libchip/ata_internal.h @@ -0,0 +1,323 @@ +/* + * ata_internal.h + * + * ATA RTEMS driver internal header file + * + * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia + * Authors: Eugeny S. Mints <Eugeny.Mints@oktet.ru> + * Alexandra Kossovsky <sasha@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ +#ifndef __ATA_INTERNAL_H__ +#define __ATA_INTERNAL_H__ + +#include <sys/param.h> +#include <sys/endian.h> +#include <rtems.h> +#include <sys/types.h> +#include <rtems/libio.h> +#include <stdlib.h> + +#include <rtems/blkdev.h> +#include <rtems/diskdevs.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Conversion from and to little-endian byte order. (no-op on i386/i486) + * + * Naming: Ca_b_c, where a: F = from, T = to, b: LE = little-endian, + * BE = big-endian, c: W = word (16 bits), L = longword (32 bits) + */ +#define CF_LE_W(v) le16toh(v) +#define CF_LE_L(v) le32toh(v) +#define CT_LE_W(v) htole16(v) +#define CT_LE_L(v) htole32(v) + +#define ATA_UNDEFINED_VALUE (-1) + +/* Sector size for all ATA devices */ +#define ATA_SECTOR_SIZE 512 + + +#define ATA_MAX_CMD_REG_OFFSET 8 + + +/* ATA Commands */ + +/* Types of ATA commands */ +#define ATA_COMMAND_TYPE_NON_DATA 0 +#define ATA_COMMAND_TYPE_PIO_IN 1 +#define ATA_COMMAND_TYPE_PIO_OUT 2 +#define ATA_COMMAND_TYPE_DMA 3 + +/* ATA commands opcodes */ +/* + * Commands present in both ATA-2 and ATA-4 specs. + * Some commands have two values in ATA-2, + * in such case value from ATA-4 used. + * Some commands have slightly different names in these specifications, + * so names from ATA-4 are used. + */ +#define ATA_COMMAND_NOP 0x00 +#define ATA_COMMAND_READ_SECTORS 0x20 +#define ATA_COMMAND_WRITE_SECTORS 0x30 +#define ATA_COMMAND_READ_VERIFY_SECTORS 0x40 +#define ATA_COMMAND_SEEK 0x70 /* or 0x7. */ +#define ATA_COMMAND_EXECUTE_DEVICE_DIAGNOSTIC 0x90 +#define ATA_COMMAND_INITIALIZE_DEVICE_PARAMETERS 0x91 +#define ATA_COMMAND_DOWNLOAD_MICROCODE 0x92 +#define ATA_COMMAND_READ_MULTIPLE 0xc4 +#define ATA_COMMAND_WRITE_MULTIPLE 0xc5 +#define ATA_COMMAND_SET_MULTIPLE_MODE 0xc6 +#define ATA_COMMAND_READ_DMA 0xc8 +#define ATA_COMMAND_WRITE_DMA 0xca +#define ATA_COMMAND_STANDBY_IMMEDIATE 0xe0 /* or 0x94 */ +#define ATA_COMMAND_IDLE_IMMEDIATE 0xe1 /* or 0x95 */ +#define ATA_COMMAND_STANDBY 0xe2 /* or 0x96 */ +#define ATA_COMMAND_IDLE 0xe3 /* or 0x97 */ +#define ATA_COMMAND_READ_BUFFER 0xe4 +#define ATA_COMMAND_CHECK_POWER_MODE 0xe5 /* or 0x98 in ATA-2 */ +#define ATA_COMMAND_SLEEP 0xe6 /* or 0x99 */ +#define ATA_COMMAND_WRITE_BUFFER 0xe8 +#define ATA_COMMAND_IDENTIFY_DEVICE 0xec +#define ATA_COMMAND_SET_FEATURES 0xef + +/* Commands present in both ATA-2 and ATA-4 specs: removable media */ +#define ATA_COMMAND_MEDIA_LOCK 0xde +#define ATA_COMMAND_MEDIA_UNLOCK 0xdf +#define ATA_COMMAND_MEDIA_EJECT 0xed + + +/* Commands present in ATA-2, but not in ATA-4 (not used) */ +#define ATA_COMMAND_RECALIBRATE 0x10 /* or 0x1. */ +#define ATA_COMMAND_READ_SECTOR_NON_RETRY 0x21 +#define ATA_COMMAND_READ_LONG_RETRY 0x22 +#define ATA_COMMAND_READ_LONG_NON_RETRY 0x23 +#define ATA_COMMAND_WRITE_SECTOR_NON_RETRY 0x31 +#define ATA_COMMAND_WRITE_LONG_RETRY 0x32 +#define ATA_COMMAND_WRITE_LONG_NON_RETRY 0x33 +#define ATA_COMMAND_WRITE_VERIFY 0x3c +#define ATA_COMMAND_READ_VERIFY_SECTOR_NON_RETRY 0x41 +#define ATA_COMMAND_FORMAT_TRACK 0x50 +#define ATA_COMMAND_READ_DMA_NON_RETRY 0xc9 +#define ATA_COMMAND_WRITE_DMA_NON_RETRY 0xcb +#define ATA_COMMAND_ACKNOWLEGE_MEDIA_CHANGE 0xdb +#define ATA_COMMAND_BOOT_POST_BOOT 0xdc +#define ATA_COMMAND_BOOT_PRE_BOOT 0xdd +#define ATA_COMMAND_WRITE_SAME 0xe9 + +/* Commands from ATA-4 specification: CFA feature set */ +#define ATA_COMMAND_CFA_REQUEST_EXTENDED_ERROR_CODE 0x03 +#define ATA_COMMAND_CFA_WRITE_SECTORS_WITHOUT_ERASE 0x38 +#define ATA_COMMAND_CFA_TRANSLATE_SECTOR 0x87 +#define ATA_COMMAND_CFA_ERASE_SECTORS 0xc0 +#define ATA_COMMAND_CFA_WRITE_MULTIPLE_WITHOUT_ERASE 0xcd + +/* Commands from ATA-4 specification: commands to use with PACKET command */ +#define ATA_COMMAND_DEVICE_RESET 0x08 +#define ATA_COMMAND_PACKET 0xa0 +#define ATA_COMMAND_IDENTIFY_PACKET_DEVICE 0xa1 +#define ATA_COMMAND_SERVICE 0xa2 + +/* Commands from ATA-4 specification: SECURITY commands */ +#define ATA_COMMAND_SECURITY_SET_PASSWORD 0xf1 +#define ATA_COMMAND_SECURITY_UNLOCK 0xf2 +#define ATA_COMMAND_SECURITY_ERASE_PREPARE 0xf3 +#define ATA_COMMAND_SECURITY_ERASE_UNIT 0xf4 +#define ATA_COMMAND_SECURITY_FREEZE_LOCK 0xf5 +#define ATA_COMMAND_SECURITY_DISABLE_PASSWORD 0xf6 + +/* Commands from ATA-4 specification: other commands */ +#define ATA_COMMAND_SMART 0xb0 +#define ATA_COMMAND_READ_DMA_QUEUED 0xc7 +#define ATA_COMMAND_WRITE_DMA_QUEUED 0xcc +#define ATA_COMMAND_GET_MEDIA_STATUS 0xda +#define ATA_COMMAND_FLUSH_CACHE 0xe7 +#define ATA_COMMAND_READ_NATIVE_MAX_ADDRESS 0xf8 +#define ATA_COMMAND_SET_MAX_ADDRESS 0xf9 + +#define ATA_REGISTERS_VALUE(reg) (1 << (reg)) + +/* ATA IDENTIFY DEVICE command words and bits */ +#define ATA_IDENT_WORD_RW_MULT 47 +#define ATA_IDENT_WORD_CAPABILITIES 49 +#define ATA_IDENT_WORD_FIELD_VALIDITY 53 +#define ATA_IDENT_WORD_NUM_OF_CURR_LOG_CLNDS 54 +#define ATA_IDENT_WORD_NUM_OF_CURR_LOG_HEADS 55 +#define ATA_IDENT_WORD_NUM_OF_CURR_LOG_SECS 56 +#define ATA_IDENT_WORD_MULT_SECS 59 +#define ATA_IDENT_WORD_NUM_OF_USR_SECS0 60 +#define ATA_IDENT_WORD_NUM_OF_USR_SECS1 61 +#define ATA_IDENT_WORD_PIO_SPPRTD 64 + +#define ATA_IDENT_BIT_VALID 0x02 + +/* + * It is OR for all ATA_REGISTERS_VALUE(reg), where reg is neccessary + * for setting block position + */ +#define ATA_REGISTERS_POSITION 0xfc + +#define ATA_MINOR_NUM_RESERVED_PER_ATA_DEVICE 64 + +#define ATA_MAX_RTEMS_INT_VEC_NUMBER 255 + +#define ATA_MAX_NAME_LENGTH 10 + +/* diagnostic codes */ +#define ATA_DEV0_PASSED_DEV1_PASSED_OR_NOT_PRSNT 0x01 +#define ATA_DEV0_PASSED_DEV1_FAILED 0x81 +#define ATA_DEV1_PASSED_DEV0_FAILED 0x80 + +/* + * Obtain ata device parameters by controller minor number and device number + */ +#define ATA_DEV_INFO(controller_minor, dev) \ + ata_ide_ctrls[controller_minor].device[dev] + +/* ATA RTEMS driver internal data stuctures */ + +/* Command block registers */ +typedef struct ata_registers_s { + uint16_t regs[8]; /* command block registers */ + uint16_t to_read; /* mask: which ata registers should be read */ + uint16_t to_write; /* mask: which ata registers should be written */ +} ata_registers_t; + +/* ATA request */ +typedef struct ata_req_s { + rtems_chain_node link; /* link in requests chain */ + char type; /* request type */ + ata_registers_t regs; /* ATA command */ + uint32_t cnt; /* Number of sectors to be exchanged */ + uint32_t cbuf; /* number of current buffer from breq in use */ + uint32_t pos; /* current position in 'cbuf' */ + rtems_blkdev_request *breq; /* blkdev_request which corresponds to the + * ata request + */ + rtems_id sema; /* semaphore which is used if synchronous + * processing of the ata request is required + */ + rtems_status_code status; /* status of ata request processing */ + int info; /* device info code */ +} ata_req_t; + +/* call callback provided by block device request if it is defined */ +#define ATA_EXEC_CALLBACK(areq, status) \ + do {\ + if ((areq)->breq != NULL) \ + rtems_blkdev_request_done((areq)->breq, status); \ + } while (0) + +/* ATA RTEMS driver events types */ +typedef enum ata_msg_type_s { + ATA_MSG_GEN_EVT = 1, /* general event */ + ATA_MSG_SUCCESS_EVT, /* success event */ + ATA_MSG_ERROR_EVT, /* error event */ + ATA_MSG_PROCESS_NEXT_EVT /* process next request event */ +} ata_msg_type_t; + +/* ATA RTEMS driver message */ +typedef struct ata_queue_msg_s { + ata_msg_type_t type; /* message type */ + rtems_device_minor_number ctrl_minor; /* IDE controller minor number */ + int error; /* error code */ +} ata_queue_msg_t; + +/* macros for messages processing */ +#define ATA_FILL_MSG(msg, evt_type, ctrl, err)\ + do {\ + msg.type = evt_type;\ + msg.ctrl_minor = ctrl;\ + msg.error = err;\ + } while (0) + +#define ATA_SEND_EVT(msg, type, ctrl, err)\ + do {\ + rtems_status_code rc;\ + ATA_FILL_MSG(msg, type, ctrl, err);\ + rc = rtems_message_queue_send(ata_queue_id, &msg,\ + sizeof(ata_queue_msg_t));\ + if (rc != RTEMS_SUCCESSFUL)\ + rtems_fatal_error_occurred(RTEMS_INTERNAL_ERROR);\ + } while (0) + +/* + * Array of such structures is indexed by interrupt vecotrs and used for + * mapping of IDE controllers and interrupt vectors + */ +typedef struct ata_int_st_s { + rtems_chain_node link; + rtems_device_minor_number ctrl_minor; +} ata_int_st_t; + +/* + * Mapping of rtems ATA devices to the following pairs: + * (IDE controller number served the device, device number on the controller) + */ +typedef struct ata_ide_dev_s { + int ctrl_minor;/* minor number of IDE controller served rtems ATA device */ + int device; /* device number on IDE controller (0 or 1) */ +} ata_ide_dev_t; + +/* + * ATA device description + */ +typedef struct ata_dev_s { + int8_t present; /* 1 -- present, 0 -- not present, */ + /* -1 -- non-initialized */ + uint16_t cylinders; + uint16_t heads; + uint16_t sectors; + uint32_t lba_sectors; /* for small disk */ + /* == cylinders * heads * sectors */ + + uint8_t lba_avaible; /* 0 - CHS mode, 1 - LBA mode */ + + uint16_t modes_available; /* OR of values for this modes */ + uint16_t mode_active; +} ata_dev_t; + +/* + * This structure describes controller state, devices configuration on the + * controller and chain of ATA requests to the controller. Array of such + * structures is indexed by controller minor number + */ +typedef struct ata_ide_ctrl_s { + bool present; /* controller state */ + ata_dev_t device[2]; /* ata diveces description */ + rtems_chain_control reqs; /* requests chain */ +} ata_ide_ctrl_t; + +/* Block device request with a single buffer provided */ +typedef struct blkdev_request1 { + rtems_blkdev_request req; + rtems_blkdev_sg_buffer sg[1]; +} blkdev_request1; + +void ata_breq_init(blkdev_request1 *breq, uint16_t *sector_buffer); + +rtems_status_code ata_identify_device( + rtems_device_minor_number ctrl_minor, + int dev, + uint16_t *sector_buffer, + ata_dev_t *device_entry +); + +void ata_process_request_on_init_phase( + rtems_device_minor_number ctrl_minor, + ata_req_t *areq +); + +#ifdef __cplusplus +} +#endif + +#endif /* __ATA_INTERNAL_H__ */ diff --git a/bsps/include/libchip/cs8900.h b/bsps/include/libchip/cs8900.h new file mode 100644 index 0000000000..79c943842d --- /dev/null +++ b/bsps/include/libchip/cs8900.h @@ -0,0 +1,761 @@ +/* + ------------------------------------------------------------------------ + + Copyright Cybertec Pty Ltd, 2000 + All rights reserved Cybertec Pty Ltd, 2000 + + Port to the DIMM PC copyright (c) 2004 Angelo Fraietta + This project has been assisted by the Commonwealth Government + through the Australia Council, its arts funding and advisory body. + + COPYRIGHT (c) 1989-1998. + On-Line Applications Research Corporation (OAR). + + The license and distribution terms for this file may be + found in the file LICENSE in this distribution or at + http://www.rtems.org/license/LICENSE. + + ------------------------------------------------------------------------ + + CS8900 RTEMS driver. + + This is a generic driver that requires a BSP backend. The BSP backend + provides the glue to the specific bus for the target hardware. It has + been tested with Coldfire processors, and the PC. These targets have + completely different bus, byte order and interrupt structures. + + An example BSP backend is provided in the pci386 BSP. + + The BSP provides the following functions: + + cs8900_io_set_reg + cs8900_io_get_reg + cs8900_mem_set_reg + cs8900_mem_get_reg + cs8900_put_data_block + cs8900_get_data_block + cs8900_tx_load + cs8900_attach_interrupt + cs8900_detach_interrupt + + The header file provides documentation for these functions. There + are four types of functions. + + The I/O set/get functions access the CS8900 I/O registers via the + I/O Mode. For example on a PC with an ISA bus you would use the + IA32 in/out port instructions. The cs8900_device structure passed + to these functions provide these functions with the I/O base + address. The BSP must provide these functions. + + The Memory set/get functions access the CS8900 internal registers + and frame buffers directly from a 4K byte block of host memory. + Memory mode provides a faster access to the CS8900. The cs8900_device + structure passed to these functions provides the memory base + address. The BSP needs to provide these functions but they do not + need to be implemented if the mem_base field is set to 0. The + driver will use I/O mode only. + + The Block transfer functions are used to read or write a block + of memory from the CS8900. This saves the driver making a number + of small calls. The BSP driver must know if I/O or Memory mode + can be used. + + The final group of functions is to handle interrupts. The BSP + must take care of save and restoring any interrupt state + information. + + The BSP declares a 'cs8900_device' structure for each device being + attached to the networking stack. It also creates a + 'struct rtems_bsdnet_ifconfig' which is used to attach the interface + to the networking stack. The following code declares the BSD config: + + static cs8900_device cs8900; + + static struct rtems_bsdnet_ifconfig cs8900_ifconfig = + { + "cs0", + cs8900_driver_attach, + NULL, + NULL, + NULL, + NULL, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 + }; + + The device linked to the BSD config structure with: + + cs8900_ifconfig.drv_ctrl = &cs8900; + + If you have a specific hardware address you should point the BSD + config structure to that address. If you do not the driver will read + the MAC address from the CS8900. This assumes the CS8900 has read + the address from an external EEPROM or has been setup by a BIOS or + boot monitor. For EEPROM less you need to supply the MAC address. + + Set the I/O and Memory base addresses. If the Memory base address + is 0 the driver will use I/O mode only. A typical initialisation + looks like: + + printf ("RTEMS BSD Network initialisation.\n"); + rtems_bsdnet_initialize_network (); + + #define ETHERNET_IO_BASE 0x300 + #define ETHERNET_MEM_BASE 0 + #define ETHERNET_IRQ_LEVEL 0 + + cs8900_device *cs = &cs8900; + + memset (cs, 0, sizeof (cs8900_device)); + + cs->dev = 0; + cs->io_base = ETHERNET_IO_BASE; + cs->mem_base = ETHERNET_MEM_BASE; + cs->irq_level = ETHERNET_IRQ_LEVEL; + cs->rx_queue_size = 30; + + cs8900_ifconfig.drv_ctrl = &cs8900; + + printf ("CS8900 initialisation\n"); + + rtems_bsdnet_attach (&cs8900_ifconfig); + + flags = IFF_UP; + if (rtems_bsdnet_ifconfig (cs8900_ifconfig.name, + SIOCSIFFLAGS, + &flags) < 0) + { + printf ("error: can't bring up %s: %s\n", + cs8900_ifconfig.name, strerror (errno)); + return; + } + + rtems_bsdnet_do_bootp_and_rootfs (); + + The IRQ level is the one documented in the CS8900 datasheet and below + in the CS8900 device structure. You need to map your target IRQ to the + CS8900 in the BSP driver. + + */ + +#if !defined(_CS8900_H_) +#define _CS8900_H_ + +#include <rtems.h> +#include <rtems/error.h> +#include <rtems/rtems_bsdnet.h> + +#include <sys/param.h> +#include <sys/mbuf.h> +#include <sys/socket.h> +#include <sys/sockio.h> + +#include <net/if.h> + +#include <netinet/in.h> +#include <netinet/if_ether.h> + +/* #include <target.h> what does this provide? joel to chris */ + +#define ET_MINLEN 60 + +/* + * CS8900 device register definitions + */ + +/* + * Crystal ESIA product id. + */ + +#define CS8900_ESIA_ID (0x630e) + +/* + * IO Registers. + */ + +#define CS8900_IO_RX_TX_DATA_PORT0 (0x0000) +#define CS8900_IO_TX_TX_DATA_PORT1 (0x0002) +#define CS8900_IO_TxCMD (0x0004) +#define CS8900_IO_TxLength (0x0006) +#define CS8900_IO_ISQ (0x0008) +#define CS8900_IO_PACKET_PAGE_PTR (0x000a) +#define CS8900_IO_PP_DATA_PORT0 (0x000c) +#define CS8900_IO_PP_DATA_PORT1 (0x000e) + +/* + * Packet Page Registers. + */ + +/* + * Bus Interface Registers. + */ + +#define CS8900_PP_PROD_ID (0x0000) +#define CS8900_PP_IO_BASE (0x0020) +#define CS8900_PP_INT (0x0022) +#define CS8900_PP_DMA_CHANNEL (0x0024) +#define CS8900_PP_DMA_SOF (0x0026) +#define CS8900_PP_DMA_FRM_CNT (0x0028) +#define CS8900_PP_DMA_RX_BCNT (0x002a) +#define CS8900_PP_MEM_BASE (0x002c) +#define CS8900_PP_BPROM_BASE (0x0030) +#define CS8900_PP_BPROM_AMASK (0x0034) +#define CS8900_PP_EEPROM_CMD (0x0040) +#define CS8900_PP_EEPROM_DATA (0x0042) +#define CS8900_PP_RX_FRAME_BCNT (0x0050) + +/* + * Configuration and Control Registers. + */ + +#define CS8900_PP_RxCFG (0x0102) +#define CS8900_PP_RxCTL (0x0104) +#define CS8900_PP_TxCFG (0x0106) +#define CS8900_PP_TxCMD_READ (0x0108) +#define CS8900_PP_BufCFG (0x010a) +#define CS8900_PP_LineCFG (0x0112) +#define CS8900_PP_SelfCTL (0x0114) +#define CS8900_PP_BusCTL (0x0116) +#define CS8900_PP_TestCTL (0x0118) + +/* + * Status and Event Registers. + */ + +#define CS8900_PP_ISQ (0x0120) +#define CS8900_PP_RxEvent (0x0124) +#define CS8900_PP_TxEvent (0x0128) +#define CS8900_PP_BufEvent (0x012c) +#define CS8900_PP_RxMISS (0x0130) +#define CS8900_PP_TxCol (0x0132) +#define CS8900_PP_LineST (0x0134) +#define CS8900_PP_SelfST (0x0136) +#define CS8900_PP_BusST (0x0138) +#define CS8900_PP_TDR (0x013c) + +/* + * Initiate Transmit Registers. + */ + +#define CS8900_PP_TxCMD (0x0144) +#define CS8900_PP_TxLength (0x0146) + +/* + * Address Filter Registers. + */ + +#define CS8900_PP_LAF (0x0150) +#define CS8900_PP_IA (0x0158) + +/* + * Frame Location. + */ + +#define CS8900_PP_RxStatus (0x0400) +#define CS8900_PP_RxLength (0x0402) +#define CS8900_PP_RxFrameLoc (0x0404) +#define CS8900_PP_TxFrameLoc (0x0a00) + +/* + * Bit Definitions of Registers. + */ + +/* + * IO Packet Page Pointer. + */ + +#define CS8900_PPP_AUTO_INCREMENT (0x8000) + +/* + * Reg 3. Receiver Configuration. + */ + +#define CS8900_RX_CONFIG_SKIP_1 (1 << 6) +#define CS8900_RX_CONFIG_STREAM_ENABLE (1 << 7) +#define CS8900_RX_CONFIG_RX_OK (1 << 8) +#define CS8900_RX_CONFIG_RX_DMA (1 << 9) +#define CS8900_RX_CONFIG_RX_AUTO_DMA (1 << 10) +#define CS8900_RX_CONFIG_BUFFER_CRC (1 << 11) +#define CS8900_RX_CONFIG_CRC_ERROR (1 << 12) +#define CS8900_RX_CONFIG_RUNT (1 << 13) +#define CS8900_RX_CONFIG_EXTRA_DATA (1 << 14) + +/* + * Reg 4. Receiver Event. + */ + +#define CS8900_RX_EVENT_HASH_IA_MATCH (1 << 6) +#define CS8900_RX_EVENT_DRIBBLE_BITS (1 << 7) +#define CS8900_RX_EVENT_RX_OK (1 << 8) +#define CS8900_RX_EVENT_HASHED (1 << 9) +#define CS8900_RX_EVENT_IA (1 << 10) +#define CS8900_RX_EVENT_BROADCAST (1 << 11) +#define CS8900_RX_EVENT_CRC_ERROR (1 << 12) +#define CS8900_RX_EVENT_RUNT (1 << 13) +#define CS8900_RX_EVENT_EXTRA_DATA (1 << 14) + +/* + * Reg 5. Receiver Control. + */ + +#define CS8900_RX_CTRL_HASH_IA_MATCH (1 << 6) +#define CS8900_RX_CTRL_PROMISCUOUS (1 << 7) +#define CS8900_RX_CTRL_RX_OK (1 << 8) +#define CS8900_RX_CTRL_MULTICAST (1 << 9) +#define CS8900_RX_CTRL_INDIVIDUAL (1 << 10) +#define CS8900_RX_CTRL_BROADCAST (1 << 11) +#define CS8900_RX_CTRL_CRC_ERROR (1 << 12) +#define CS8900_RX_CTRL_RUNT (1 << 13) +#define CS8900_RX_CTRL_EXTRA_DATA (1 << 14) + +/* + * Reg 7. Transmit Configuration. + */ + +#define CS8900_TX_CONFIG_LOSS_OF_CARRIER (1 << 6) +#define CS8900_TX_CONFIG_SQ_ERROR (1 << 7) +#define CS8900_TX_CONFIG_TX_OK (1 << 8) +#define CS8900_TX_CONFIG_OUT_OF_WINDOW (1 << 9) +#define CS8900_TX_CONFIG_JABBER (1 << 10) +#define CS8900_TX_CONFIG_ANY_COLLISION (1 << 11) +#define CS8900_TX_CONFIG_16_COLLISION (1 << 15) + +/* + * Reg 8. Transmit Event. + */ + +#define CS8900_TX_EVENT_LOSS_OF_CARRIER (1 << 6) +#define CS8900_TX_EVENT_SQ_ERROR (1 << 7) +#define CS8900_TX_EVENT_TX_OK (1 << 8) +#define CS8900_TX_EVENT_OUT_OF_WINDOW (1 << 9) +#define CS8900_TX_EVENT_JABBER (1 << 10) +#define CS8900_TX_EVENT_16_COLLISIONS (1 << 15) + +/* + * Reg 9. Transmit Command Status. + */ + +#define CS8900_TX_CMD_STATUS_TX_START_5 (0 << 6) +#define CS8900_TX_CMD_STATUS_TX_START_381 (1 << 6) +#define CS8900_TX_CMD_STATUS_TX_START_1021 (2 << 6) +#define CS8900_TX_CMD_STATUS_TX_START_ENTIRE (3 << 6) +#define CS8900_TX_CMD_STATUS_FORCE (1 << 8) +#define CS8900_TX_CMD_STATUS_ONE_COLLISION (1 << 9) +#define CS8900_TX_CMD_STATUS_INHIBIT_CRC (1 << 12) +#define CS8900_TX_CMD_STATUS_TX_PAD_DISABLED (1 << 13) + +/* + * Reg B. Buffer Configuration. + */ + +#define CS8900_BUFFER_CONFIG_SW_INT (1 << 6) +#define CS8900_BUFFER_CONFIG_RX_DMA_DONE (1 << 7) +#define CS8900_BUFFER_CONFIG_RDY_FOR_TX (1 << 8) +#define CS8900_BUFFER_CONFIG_TX_UNDERRUN (1 << 9) +#define CS8900_BUFFER_CONFIG_RX_MISSED (1 << 10) +#define CS8900_BUFFER_CONFIG_RX_128_BYTES (1 << 11) +#define CS8900_BUFFER_CONFIG_TX_COL_OVF (1 << 12) +#define CS8900_BUFFER_CONFIG_RX_MISSED_OVF (1 << 13) +#define CS8900_BUFFER_CONFIG_RX_DEST_MATCH (1 << 15) + +/* + * Reg C. Buffer Event. + */ + +#define CS8900_BUFFER_EVENT_SW_INT (1 << 6) +#define CS8900_BUFFER_EVENT_RX_DMA_DONE (1 << 7) +#define CS8900_BUFFER_EVENT_RDY_FOR_TX (1 << 8) +#define CS8900_BUFFER_EVENT_TX_UNDERRUN (1 << 9) +#define CS8900_BUFFER_EVENT_RX_MISSED (1 << 10) +#define CS8900_BUFFER_EVENT_RX_128_BYTES (1 << 11) +#define CS8900_BUFFER_EVENT_RX_DEST_MATCH (1 << 15) + +/* + * Reg 13. Line Control. + */ + +#define CS8900_LINE_CTRL_RX_ON (1 << 6) +#define CS8900_LINE_CTRL_TX_ON (1 << 7) +#define CS8900_LINE_CTRL_AUI (1 << 8) +#define CS8900_LINE_CTRL_10BASET (0 << 9) +#define CS8900_LINE_CTRL_AUTO_AUI_10BASET (1 << 9) +#define CS8900_LINE_CTRL_MOD_BACKOFF (1 << 11) +#define CS8900_LINE_CTRL_POLARITY_DISABLED (1 << 12) +#define CS8900_LINE_CTRL_2_PART_DEF_DISABLED (1 << 13) +#define CS8900_LINE_CTRL_LO_RX_SQUELCH (1 << 14) + +/* + * Reg 14. Line Status. + */ + +#define CS8900_LINE_STATUS_LINK_OK (1 << 7) +#define CS8900_LINE_STATUS_AUI (1 << 8) +#define CS8900_LINE_STATUS_10_BASE_T (1 << 9) +#define CS8900_LINE_STATUS_POLARITY_OK (1 << 12) +#define CS8900_LINE_STATUS_CRS (1 << 14) + +/* + * Reg 15. Self Control. + */ + +#define CS8900_SELF_CTRL_RESET (1 << 6) +#define CS8900_SELF_CTRL_SW_SUSPEND (1 << 8) +#define CS8900_SELF_CTRL_HW_SLEEP (1 << 9) +#define CS8900_SELF_CTRL_HW_STANDBY (1 << 10) +#define CS8900_SELF_CTRL_HC0E (1 << 12) +#define CS8900_SELF_CTRL_HC1E (1 << 13) +#define CS8900_SELF_CTRL_HCB0 (1 << 14) +#define CS8900_SELF_CTRL_HCB1 (1 << 15) + +/* + * Reg 16. Self Status. + */ + +#define CS8900_SELF_STATUS_3_3_V (1 << 6) +#define CS8900_SELF_STATUS_INITD (1 << 7) +#define CS8900_SELF_STATUS_SIBUST (1 << 8) +#define CS8900_SELF_STATUS_EEPROM_PRESENT (1 << 9) +#define CS8900_SELF_STATUS_EEPROM_OK (1 << 10) +#define CS8900_SELF_STATUS_EL_PRESENT (1 << 11) +#define CS8900_SELF_STATUS_EE_SIZE (1 << 12) + +/* + * Reg 17. Bus Control. + */ + +#define CS8900_BUS_CTRL_RESET_RX_DMA (1 << 6) +#define CS8900_BUS_CTRL_USE_SA (1 << 9) +#define CS8900_BUS_CTRL_MEMORY_ENABLE (1 << 10) +#define CS8900_BUS_CTRL_DMA_BURST (1 << 11) +#define CS8900_BUS_CTRL_IOCHRDYE (1 << 12) +#define CS8900_BUS_CTRL_RX_DMA_SIZE (1 << 13) +#define CS8900_BUS_CTRL_ENABLE_INT (1 << 15) + +/* + * Reg 18. Bus Status. + */ + +#define CS8900_BUS_STATUS_TX_BID_ERROR (1 << 7) +#define CS8900_BUS_STATUS_RDY_FOR_TX_NOW (1 << 8) + +/* + * Trace for debugging the isq processing. Define to 1 to enable. + */ +#define CS8900_TRACE 0 +#define CS8900_TRACE_SIZE (400) + +/* + * The default receive queue size. If the BSP sets this field to + * 0 this default is used. + */ +#define CS8900_RX_QUEUE_SIZE (30) + +/* + * Stats, more for debugging than anything else. + */ + +typedef struct +{ + unsigned long rx_packets; /* total packets received */ + unsigned long tx_packets; /* total packets transmitted */ + unsigned long rx_bytes; /* total bytes received */ + unsigned long tx_bytes; /* total bytes transmitted */ + unsigned long rx_interrupts; /* total number of rx interrupts */ + unsigned long tx_interrupts; /* total number of tx interrupts */ + + /* detailed rx errors: */ + unsigned long rx_dropped; /* no mbufs in queue */ + unsigned long rx_no_mbufs; /* no mbufs */ + unsigned long rx_no_clusters; /* no clusters */ + unsigned long rx_oversize_errors; + unsigned long rx_crc_errors; /* recved pkt with crc error */ + unsigned long rx_runt_errors; + unsigned long rx_missed_errors; /* receiver missed packet */ + + /* detailed tx errors */ + unsigned long tx_ok; + unsigned long tx_collisions; + unsigned long tx_bid_errors; + unsigned long tx_wait_for_rdy4tx; + unsigned long tx_rdy4tx; + unsigned long tx_underrun_errors; + unsigned long tx_dropped; + unsigned long tx_resends; + + /* interrupt watch dog */ + unsigned long int_swint_req; + unsigned long int_swint_res; + unsigned long int_lockup; + + unsigned long interrupts; + +} eth_statistics; + +/* + * CS8900 device structure + */ + +typedef struct +{ + /* + * Device number. + */ + + int dev; + + /* + * Memory base addresses. Making mem_base 0 forces the + * driver to perform only I/O space accesses. + */ + + unsigned long io_base; + unsigned long mem_base; + + /* + * The IRQ level as defined in the datasheet for the CS8900. + * + * ISA BUS Pin Value + * IRQ10 INTRQ0 0 + * IRQ11 INTRQ1 1 + * IRQ12 INTRQ2 2 + * IRQ5 INTRQ3 3 + */ + + int irq_level; + + /* + * The MAC address. + */ + + unsigned char mac_address[6]; + + /* + * The bsdnet information structure. + */ + + struct arpcom arpcom; + + /* + * Driver state and resources. + */ + + int accept_bcast; + int tx_active; + + rtems_id rx_task; + rtems_id tx_task; + + /* + * The queues. FIXME : these should be changed to be mbuf lists. + */ + + struct mbuf *rx_ready_head; + struct mbuf *rx_ready_tail; + int rx_ready_len; + + struct mbuf *rx_loaded_head; + struct mbuf *rx_loaded_tail; + int rx_loaded_len; + + /* + * Number of mbufs queued for the interrupt handler to + * loop reading. + */ + + int rx_queue_size; + +#if CS8900_TRACE + unsigned short trace_key[CS8900_TRACE_SIZE]; + unsigned long trace_var[CS8900_TRACE_SIZE]; + unsigned long trace_time[CS8900_TRACE_SIZE]; + int trace_in; +#endif + + /** + * Standard(!) ethernet statistics + */ + + eth_statistics eth_stats; + +} cs8900_device; + +/* + * Link active returns the state of the PHY. + * + * @param cs Pointer to the device structure. + */ + +int cs8900_link_active (cs8900_device *cs); + +/** + * The RTEMS network stack driver attach function that is loaded into the + * the rtems_bsdnet_ifconfig struct. The network stack will call this + * function when attaching the driver. The BSP must load the 'drv_ctrl' + * field of the structure before calling the 'rtems_bsdnet_attach' + * function. + * + * @param config The RTEMS BSD config structure. + * + * @param attaching True is the stack is attaching the interface. + * + * @retval int Set to 1 if the device has attached. + */ + +int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, + int attaching); + +/** + * The BSP specific interrupt wrapper calls this function when a device + * interrupt occurs. + * + * @param v The RTEMS vector number that generated the interrupt. + * + * @param cs Pointer to the device structure passed to the interrupt + * catch function provided by the BSP. + * + * @retval rtems_isr The standard ISR return type. + */ + +rtems_isr cs8900_interrupt (rtems_vector_number v, void *cs); + +/** + * Get the MAC address for the interface. + * + * @param cs Pointer to the device structure. + * + * @param mac_address Pointer to the memory to load the MAC address. This + * is a 6 byte buffer so do not exceeed the bounds. + */ + +void cs8900_get_mac_addr (cs8900_device *cs, unsigned char *mac_address); + +/** + * Catch the device interrupt. When the interrupt is called call the + * function 'cs8900_interrupt'. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + */ + +void cs8900_attach_interrupt (cs8900_device *cs); + +/** + * Detach the device interrupt. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + */ + +void cs8900_detach_interrupt (cs8900_device *cs); + +/** + * Write to an IO space register. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param reg Register offset from the IO base. + * + * @param data The data to be written to the register. + */ + +void cs8900_io_set_reg (cs8900_device *cs, + unsigned short reg, unsigned short data); + +/** + * Read an IO space register. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param reg Register offset from the IO base. + * + * @retval unsigned short The register data. + */ + +unsigned short cs8900_io_get_reg (cs8900_device *cs, unsigned short reg); + +/** + * Write to a memory space register. Will only be called is the mem_base + * field of the 'cs' struct is not 0. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param reg Register offset from the memory base. + * + * @param data The data to be written to the register. + */ + +void cs8900_mem_set_reg (cs8900_device *cs, + unsigned long reg, unsigned short data); + +/** + * Read a memory space register. Will only be called is the mem_base + * field of the 'cs' struct is not 0. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param reg Register offset from the IO base. + * + * @retval unsigned short The register data. + */ + +unsigned short cs8900_mem_get_reg (cs8900_device *cs, unsigned long reg); + +/** + * Write a block of data to the interface. The BSP codes if this is an IO or + * memory space write. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param len The length of data to write. + * + * @param data Pointer to the data to be written. + */ + +void cs8900_put_data_block (cs8900_device *cs, int len, unsigned char *data); + +/** + * Read a block of data from the interface. The BSP codes if this is an IO or + * memory space write. The read must not be longer than the MTU size. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param data Pointer to the buffer where the data is to be written. + * + * @retval unsigned short The number of bytes read from the device. + */ + +unsigned short cs8900_get_data_block (cs8900_device *cs, unsigned char *data); + +/** + * Load a mbuf chain to the device ready for tranmission. + * + * BSP to provide this function. + * + * @param cs Pointer to the device structure. + * + * @param m Pointer to the head of an mbuf chain. + */ + +void cs8900_tx_load (cs8900_device *cs, struct mbuf *m); + +#endif diff --git a/bsps/include/libchip/disp_hcms29xx.h b/bsps/include/libchip/disp_hcms29xx.h new file mode 100644 index 0000000000..84b74b6910 --- /dev/null +++ b/bsps/include/libchip/disp_hcms29xx.h @@ -0,0 +1,156 @@ +/*===============================================================*\ +| Project: display driver for HCMS29xx | ++-----------------------------------------------------------------+ +| File: disp_hcms29xx.h | ++-----------------------------------------------------------------+ +| Copyright (c) 2008 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| http://www.rtems.org/license/LICENSE. | ++-----------------------------------------------------------------+ +| this file declares the SPI based driver for a HCMS29xx 4 digit | +| alphanumeric LED display | +\*===============================================================*/ + +#ifndef _DISP_HCMS29XX_H +#define _DISP_HCMS29XX_H +#include <rtems.h> +#include <time.h> + +#ifdef __cplusplus +extern "C" { +#endif +#define DISP_HCMS29XX_TEXT_CNT (128) + + typedef struct { + rtems_device_minor_number minor; /* minor device number */ + /* + * in the disp_buffer, the string to be displayed is placed + */ + char disp_buffer[DISP_HCMS29XX_TEXT_CNT]; + int disp_buf_cnt; /* number of valid chars in disp_buffer */ + /* + * in the trns buffer the string is transfered to display task + */ + char trns_buffer[DISP_HCMS29XX_TEXT_CNT]; + /* + * in the dev_buffer, characters will be accumulated before display... + */ + char dev_buffer[DISP_HCMS29XX_TEXT_CNT]; + int dev_buf_cnt; /* number of valid chars in dev_buffer */ + + rtems_id trns_sema_id; /* ID of disp trns buffer sema */ + rtems_id task_id; /* ID of disp task */ + bool rotate; /* FLAG: display is upside down */ + } spi_disp_hcms29xx_param_t; + + typedef struct { + rtems_libi2c_drv_t libi2c_drv_entry; + spi_disp_hcms29xx_param_t disp_param; + } disp_hcms29xx_drv_t; + /* + * pass this descriptor pointer to rtems_libi2c_register_drv + */ + extern rtems_libi2c_drv_t *disp_hcms29xx_driver_descriptor; + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_device_driver disp_hcms29xx_dev_initialize + ( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| prepare the display device driver to accept write calls | +| register device with its name | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_device_driver disp_hcms29xx_dev_open +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| open the display device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_device_driver disp_hcms29xx_dev_write +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| write to display device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_device_driver disp_hcms29xx_dev_close +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| close the display device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +#define DISP_HCMS29XX_DRIVER { \ + disp_hcms29xx_dev_initialize, \ + disp_hcms29xx_dev_open, \ + NULL, \ + disp_hcms29xx_dev_write, \ + NULL, \ + disp_hcms29xx_dev_close} + + +#ifdef __cplusplus +} +#endif + +#endif /* _DISP_HCMS29XX_H */ diff --git a/bsps/include/libchip/ds1375-rtc.h b/bsps/include/libchip/ds1375-rtc.h new file mode 100644 index 0000000000..a5be96293f --- /dev/null +++ b/bsps/include/libchip/ds1375-rtc.h @@ -0,0 +1,99 @@ +#ifndef DS1375_I2C_RTC_H +#define DS1375_I2C_RTC_H + +/* Driver for the Maxim 1375 i2c RTC (TOD only; very simple...) */ + +/* + * Authorship + * ---------- + * This software was created by + * + * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include <rtems.h> +#include <libchip/rtc.h> +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +extern rtc_fns rtc_ds1375_fns; + +bool +rtc_ds1375_device_probe( int minor ); + +uint32_t +rtc_ds1375_get_register( uintptr_t port, uint8_t reg ); + +void +rtc_ds1375_set_register( uintptr_t port, uint8_t reg, uint32_t value ); + +/* + * BSP must supply string constant argument 'i2cname' which matches + * the registered device name of the raw i2c device (created with mknod). + * E.g., "/dev/i2c.ds1375-raw" + * + * NOTE: The i2c bus driver must already be up and 'i2cname' already + * be available when this ENTRY is registered or initialized. + * + * If you want to allow applications to add the RTC driver to + * the configuration table then the i2c subsystem must be + * initialized by the BSP from the predriver_hook. + */ +#define DS1375_RTC_TBL_ENTRY(i2cname) \ +{ \ + sDeviceName: "/dev/rtc", \ + deviceType: RTC_CUSTOM, \ + pDeviceFns: &rtc_ds1375_fns, \ + deviceProbe: rtc_ds1375_device_probe, \ + ulCtrlPort1: (uintptr_t)(i2cname), \ + ulDataPort: 0, \ + getRegister: rtc_ds1375_get_register, \ + setRegister: rtc_ds1375_set_register, \ +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/libchip/greth.h b/bsps/include/libchip/greth.h new file mode 100644 index 0000000000..c6e000dbd3 --- /dev/null +++ b/bsps/include/libchip/greth.h @@ -0,0 +1,152 @@ +/* + * Gaisler Research ethernet MAC driver + * adapted from Opencores driver by Marko Isomaki + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + + +#ifndef _GR_ETH_ +#define _GR_ETH_ + + +/* Configuration Information */ + +typedef struct { + void *base_address; + rtems_vector_number vector; + uint32_t txd_count; + uint32_t rxd_count; +} greth_configuration_t; + +/* Ethernet configuration registers */ + +typedef struct _greth_regs { + volatile uint32_t ctrl; /* Ctrl Register */ + volatile uint32_t status; /* Status Register */ + volatile uint32_t mac_addr_msb; /* Bit 47-32 of MAC address */ + volatile uint32_t mac_addr_lsb; /* Bit 31-0 of MAC address */ + volatile uint32_t mdio_ctrl; /* MDIO control and status */ + volatile uint32_t txdesc; /* Transmit descriptor pointer */ + volatile uint32_t rxdesc; /* Receive descriptor pointer */ +} greth_regs; + +#define GRETH_TOTAL_BD 128 +#define GRETH_MAXBUF_LEN 1520 + +/* Tx BD */ +#define GRETH_TXD_ENABLE 0x0800 /* Tx BD Enable */ +#define GRETH_TXD_WRAP 0x1000 /* Tx BD Wrap (last BD) */ +#define GRETH_TXD_IRQ 0x2000 /* Tx BD IRQ Enable */ +#define GRETH_TXD_MORE 0x20000 /* Tx BD More (more descs for packet) */ +#define GRETH_TXD_IPCS 0x40000 /* Tx BD insert ip chksum */ +#define GRETH_TXD_TCPCS 0x80000 /* Tx BD insert tcp chksum */ +#define GRETH_TXD_UDPCS 0x100000 /* Tx BD insert udp chksum */ + +#define GRETH_TXD_UNDERRUN 0x4000 /* Tx BD Underrun Status */ +#define GRETH_TXD_RETLIM 0x8000 /* Tx BD Retransmission Limit Status */ +#define GRETH_TXD_LATECOL 0x10000 /* Tx BD Late Collision */ + +#define GRETH_TXD_STATS (GRETH_TXD_UNDERRUN | \ + GRETH_TXD_RETLIM | \ + GRETH_TXD_LATECOL) + +#define GRETH_TXD_CS (GRETH_TXD_IPCS | \ + GRETH_TXD_TCPCS | \ + GRETH_TXD_UDPCS) + +/* Rx BD */ +#define GRETH_RXD_ENABLE 0x0800 /* Rx BD Enable */ +#define GRETH_RXD_WRAP 0x1000 /* Rx BD Wrap (last BD) */ +#define GRETH_RXD_IRQ 0x2000 /* Rx BD IRQ Enable */ + +#define GRETH_RXD_DRIBBLE 0x4000 /* Rx BD Dribble Nibble Status */ +#define GRETH_RXD_TOOLONG 0x8000 /* Rx BD Too Long Status */ +#define GRETH_RXD_CRCERR 0x10000 /* Rx BD CRC Error Status */ +#define GRETH_RXD_OVERRUN 0x20000 /* Rx BD Overrun Status */ +#define GRETH_RXD_LENERR 0x40000 /* Rx BD Length Error */ +#define GRETH_RXD_ID 0x40000 /* Rx BD IP Detected */ +#define GRETH_RXD_IR 0x40000 /* Rx BD IP Chksum Error */ +#define GRETH_RXD_UD 0x40000 /* Rx BD UDP Detected*/ +#define GRETH_RXD_UR 0x40000 /* Rx BD UDP Chksum Error */ +#define GRETH_RXD_TD 0x40000 /* Rx BD TCP Detected */ +#define GRETH_RXD_TR 0x40000 /* Rx BD TCP Chksum Error */ + + +#define GRETH_RXD_STATS (GRETH_RXD_OVERRUN | \ + GRETH_RXD_DRIBBLE | \ + GRETH_RXD_TOOLONG | \ + GRETH_RXD_CRCERR) + +/* CTRL Register */ +#define GRETH_CTRL_TXEN 0x00000001 /* Transmit Enable */ +#define GRETH_CTRL_RXEN 0x00000002 /* Receive Enable */ +#define GRETH_CTRL_TXIRQ 0x00000004 /* Transmit Enable */ +#define GRETH_CTRL_RXIRQ 0x00000008 /* Receive Enable */ +#define GRETH_CTRL_FULLD 0x00000010 /* Full Duplex */ +#define GRETH_CTRL_PRO 0x00000020 /* Promiscuous (receive all) */ +#define GRETH_CTRL_RST 0x00000040 /* Reset MAC */ + +/* Status Register */ +#define GRETH_STATUS_RXERR 0x00000001 /* Receive Error */ +#define GRETH_STATUS_TXERR 0x00000002 /* Transmit Error IRQ */ +#define GRETH_STATUS_RXIRQ 0x00000004 /* Receive Frame IRQ */ +#define GRETH_STATUS_TXIRQ 0x00000008 /* Transmit Error IRQ */ +#define GRETH_STATUS_RXAHBERR 0x00000010 /* Receiver AHB Error */ +#define GRETH_STATUS_TXAHBERR 0x00000020 /* Transmitter AHB Error */ + +/* MDIO Control */ +#define GRETH_MDIO_WRITE 0x00000001 /* MDIO Write */ +#define GRETH_MDIO_READ 0x00000002 /* MDIO Read */ +#define GRETH_MDIO_LINKFAIL 0x00000004 /* MDIO Link failed */ +#define GRETH_MDIO_BUSY 0x00000008 /* MDIO Link Busy */ +#define GRETH_MDIO_REGADR 0x000007C0 /* Register Address */ +#define GRETH_MDIO_PHYADR 0x0000F800 /* PHY address */ +#define GRETH_MDIO_DATA 0xFFFF0000 /* MDIO DATA */ + + +/* MII registers */ +#define GRETH_MII_EXTADV_1000FD 0x00000200 +#define GRETH_MII_EXTADV_1000HD 0x00000100 +#define GRETH_MII_EXTPRT_1000FD 0x00000800 +#define GRETH_MII_EXTPRT_1000HD 0x00000400 + +#define GRETH_MII_100T4 0x00000200 +#define GRETH_MII_100TXFD 0x00000100 +#define GRETH_MII_100TXHD 0x00000080 +#define GRETH_MII_10FD 0x00000040 +#define GRETH_MII_10HD 0x00000020 + + + +/* Attach routine */ + +int rtems_greth_driver_attach ( + struct rtems_bsdnet_ifconfig *config, + greth_configuration_t *chip +); + +/* PHY data */ +struct phy_device_info +{ + int vendor; + int device; + int rev; + + int adv; + int part; + + int extadv; + int extpart; +}; + +/* +#ifdef CPU_U32_FIX +void ipalign(struct mbuf *m); +#endif + +*/ +#endif + diff --git a/bsps/include/libchip/i2c-2b-eeprom.h b/bsps/include/libchip/i2c-2b-eeprom.h new file mode 100644 index 0000000000..93730d1e3b --- /dev/null +++ b/bsps/include/libchip/i2c-2b-eeprom.h @@ -0,0 +1,74 @@ +#ifndef I2C_2B_EEPROM_DRIVER_H +#define I2C_2B_EEPROM_DRIVER_H + +/* Trivial i2c driver for reading and writing "2-byte eeproms". + * On 'open' the file-pointer is reset to 0, subsequent + * read/write operations slurp/write data from there... + */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2005, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + + +#include <rtems.h> +#include <rtems/libi2c.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* pass one of these to rtems_libi2c_register_drv() */ + +/* These ops provide no write access */ +extern rtems_libi2c_drv_t *i2c_2b_eeprom_ro_driver_descriptor; + +/* Use these for writing and reading */ +extern rtems_libi2c_drv_t *i2c_2b_eeprom_driver_descriptor; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/libchip/i2c-ds1621.h b/bsps/include/libchip/i2c-ds1621.h new file mode 100644 index 0000000000..64df69f465 --- /dev/null +++ b/bsps/include/libchip/i2c-ds1621.h @@ -0,0 +1,81 @@ +#ifndef I2C_DS_1621_DRIVER_H +#define I2C_DS_1621_DRIVER_H + +/* Trivial i2c driver for the maxim DS1621 temperature sensor; + * just implements reading constant conversions with 8-bit + * resolution. + * Demonstrates the implementation of a i2c high-level driver. + */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2005, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#define DS1621_CMD_READ_TEMP 0xaa +#define DS1621_CMD_CSR_ACCESS 0xac +#define DS1621_CMD_START_CONV 0xee + +/* CSR bits */ +#define DS1621_CSR_DONE (1<<7) +#define DS1621_CSR_TEMP_HI (1<<6) /* T >= hi register */ +#define DS1621_CSR_TEMP_LO (1<<5) /* T <= lo register */ +#define DS1621_CSR_NVMEM_BSY (1<<4) /* non-volatile memory busy */ +#define DS1621_CSR_OUT_POL (1<<1) /* Thermostat output active polarity */ +#define DS1621_CSR_1SHOT (1<<0) /* Oneshot mode */ + +#include <rtems.h> +#include <rtems/libi2c.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* for registration with libi2c */ +extern rtems_libi2c_drv_t *i2c_ds1621_driver_descriptor; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/libchip/i2c-sc620.h b/bsps/include/libchip/i2c-sc620.h new file mode 100644 index 0000000000..27721b91c3 --- /dev/null +++ b/bsps/include/libchip/i2c-sc620.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef I2C_SC620_H +#define I2C_SC620_H + +#include <rtems/libi2c.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief I2C driver for SEMTECH SC620 octal LED driver. + * + * A write() must use two character buffer. The buffer[0] value specifies the + * register and the buffer[1] value specifies the register data. + * + * A read() must use a one character buffer. The buffer[0] value specifies the + * register on function entry. The buffer[0] value contains the register value + * after a successful operation. + */ +extern rtems_libi2c_drv_t i2c_sc620_driver; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* I2C_SC620_H */ diff --git a/bsps/include/libchip/i82586var.h b/bsps/include/libchip/i82586var.h new file mode 100644 index 0000000000..c9421a6732 --- /dev/null +++ b/bsps/include/libchip/i82586var.h @@ -0,0 +1,319 @@ +/* $NetBSD: i82586var.h,v 1.15 2001/01/22 22:28:45 bjh21 Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Paul Kranenburg and Charles M. Hannum. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/*- + * Copyright (c) 1992, 1993, University of Vermont and State + * Agricultural College. + * Copyright (c) 1992, 1993, Garrett A. Wollman. + * + * Portions: + * Copyright (c) 1994, 1995, Rafal K. Boni + * Copyright (c) 1990, 1991, William F. Jolitz + * Copyright (c) 1990, The Regents of the University of California + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of Vermont + * and State Agricultural College and Garrett A. Wollman, by William F. + * Jolitz, and by the University of California, Berkeley, Lawrence + * Berkeley Laboratory, and its contributors. + * 4. Neither the names of the Universities nor the names of the authors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR AUTHORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Intel 82586 Ethernet chip + * Register, bit, and structure definitions. + * + * Original StarLAN driver written by Garrett Wollman with reference to the + * Clarkson Packet Driver code for this chip written by Russ Nelson and others. + * + * BPF support code taken from hpdev/if_le.c, supplied with tcpdump. + * + * 3C507 support is loosely based on code donated to NetBSD by Rafal Boni. + * + * Majorly cleaned up and 3C507 code merged by Charles Hannum. + * + * Converted to SUN ie driver by Charles D. Cranor, + * October 1994, January 1995. + * This sun version based on i386 version 1.30. + */ + +#ifndef I82586_DEBUG +#define I82586_DEBUG 0 +#endif + +/* Debug elements */ +#define IED_RINT 0x01 +#define IED_TINT 0x02 +#define IED_RNR 0x04 +#define IED_CNA 0x08 +#define IED_READFRAME 0x10 +#define IED_ENQ 0x20 +#define IED_XMIT 0x40 +#define IED_ALL 0x7f + +#define B_PER_F 3 /* recv buffers per frame */ +#define IE_RBUF_SIZE 256 /* size of each receive buffer; + MUST BE POWER OF TWO */ +#define NTXBUF 2 /* number of transmit commands */ +#define IE_TBUF_SIZE ETHER_MAX_LEN /* length of transmit buffer */ + +#define IE_MAXMCAST (IE_TBUF_SIZE/6)/* must fit in transmit buffer */ + + +#define INTR_ENTER 0 /* intr hook called on ISR entry */ +#define INTR_EXIT 1 /* intr hook called on ISR exit */ +#define INTR_LOOP 2 /* intr hook called on ISR loop */ +#define INTR_ACK 3 /* intr hook called on ie_ack */ + +#define CHIP_PROBE 0 /* reset called from chip probe */ +#define CARD_RESET 1 /* reset called from card reset */ + +#if I82586_DEBUG +#define I82586_INTS_REQ 0 +#define I82586_INTS_IN 1 +#define I82586_INTS_LOOPS 2 +#define I82586_INTS_OUT 3 +#define I82586_RX_INT 4 +#define I82586_RX_DROP 5 +#define I82586_RX_ERR 6 +#define I82586_RX_OK 7 +#define I82586_RX_START 8 +#define I82586_START_TX 9 +#define I82586_TX_START 10 +#define I82586_TX_INT 11 +#define I82586_TX_REQ 12 +#define I82586_TX_EVT 13 +#define I82586_TX_EMIT 14 +#define I82586_TX_BAD 15 +#define I82586_TX_ACTIVE 16 +#define I82586_TRACE_CNT 17 + +#define I82586_TRACE_FLOW (10000) +#endif + +/* + * Ethernet status, per interface. + * + * The chip uses two types of pointers: 16 bit and 24 bit + * 24 bit pointers cover the board's memory. + * 16 bit pointers are offsets from the ISCP's `ie_base' + * + * The board's memory is represented by the bus handle `bh'. The MI + * i82586 driver deals exclusively with offsets relative to the + * board memory bus handle. The `ie_softc' fields below that are marked + * `MD' are in the domain of the front-end driver; they opaque to the + * MI driver part. + * + * The front-end is required to manage the SCP and ISCP structures. i.e. + * allocate room for them on the board's memory, and arrange to point the + * chip at the SCB stucture, the offset of which is passed to the MI + * driver in `sc_scb'. + * + * The following functions provide the glue necessary to deal with + * host and bus idiosyncracies: + * + * hwreset - board reset + * hwinit - board initialization + * chan_attn - get chip to look at prepared commands + * intrhook - board dependent interrupt processing + * + * All of the following shared-memory access function use an offset + * relative to the bus handle to indicate the shared memory location. + * The bus_{read/write}N function take or return offset into the + * shared memory in the host's byte-order. + * + * memcopyin - copy device memory: board to KVA + * memcopyout - copy device memory: KVA to board + * bus_read16 - read a 16-bit i82586 pointer + `offset' argument will be 16-bit aligned + * bus_write16 - write a 16-bit i82586 pointer + `offset' argument will be 16-bit aligned + * bus_write24 - write a 24-bit i82586 pointer + `offset' argument will be 32-bit aligned + * bus_barrier - perform a bus barrier operation, forcing + all outstanding reads/writes to complete + * + */ + +struct ie_softc { + struct arpcom arpcom; + + /* + * For RTEMS we run the tx and rx handlers under a task due to the + * network semaphore stuff. + */ + + rtems_id intr_task; + rtems_id tx_task; + + void *sc_iobase; /* (MD) KVA of base of 24 bit addr space */ + void *sc_maddr; /* (MD) KVA of base of chip's RAM + (16bit addr space) */ + u_int sc_msize; /* (MD) how much RAM we have/use */ + + /* Bus glue */ + void (*hwreset) (struct ie_softc *, int); + void (*hwinit) (struct ie_softc *); + void (*chan_attn) (struct ie_softc *, int); + int (*intrhook) (struct ie_softc *, int where); + + void (*memcopyin) (struct ie_softc *, void *, int, size_t); + void (*memcopyout) (struct ie_softc *, const void *, + int, size_t); + u_int16_t (*ie_bus_read16) (struct ie_softc *, int offset); + void (*ie_bus_write16) (struct ie_softc *, int offset, + u_int16_t value); + void (*ie_bus_write24) (struct ie_softc *, int offset, + int addr); + void (*ie_bus_barrier) (struct ie_softc *, int offset, + int length, int flags); + + /* Media management */ + int (*sc_mediachange) (struct ie_softc *); + /* card dependent media change */ + void (*sc_mediastatus) (struct ie_softc *, struct ifmediareq *); + /* card dependent media status */ + + /* + * Offsets (relative to bus handle) of the i82586 SYSTEM structures. + */ + int scp; /* Offset to the SCP (set by front-end) */ + int iscp; /* Offset to the ISCP (set by front-end) */ + int scb; /* Offset to SCB (set by front-end) */ + + /* + * Offset and size of a block of board memory where the buffers + * are to be allocated from (initialized by front-end). + */ + int buf_area; /* Start of descriptors and buffers */ + int buf_area_sz; /* Size of above */ + + /* + * The buffers & descriptors (recv and xmit) + */ + int rframes; /* Offset to `nrxbuf' frame descriptors */ + int rbds; /* Offset to `nrxbuf' buffer descriptors */ + int rbufs; /* Offset to `nrxbuf' receive buffers */ +#define IE_RBUF_ADDR(sc, i) (sc->rbufs + ((i) * IE_RBUF_SIZE)) + int rfhead, rftail; + int rbhead, rbtail; + int nframes; /* number of frames in use */ + int nrxbuf; /* number of recv buffs in use */ + int rnr_expect; /* XXX - expect a RCVR not ready interrupt */ + + int nop_cmds; /* Offset to NTXBUF no-op commands */ + int xmit_cmds; /* Offset to NTXBUF transmit commands */ + int xbds; /* Offset to NTXBUF buffer descriptors */ + int xbufs; /* Offset to NTXBUF transmit buffers */ +#define IE_XBUF_ADDR(sc, i) (sc->xbufs + ((i) * IE_TBUF_SIZE)) + + int xchead, xctail; + int xmit_busy; + int do_xmitnopchain; /* Controls use of xmit NOP chains */ + int xmit_req; + + /* Multicast addresses */ + char *mcast_addrs; /* Current MC filter addresses */ + int mcast_addrs_size; /* Current size of MC buffer */ + int mcast_count; /* Current # of addrs in buffer */ + int want_mcsetup; /* run mcsetup at next opportunity */ + + int promisc; /* are we in promisc mode? */ + int async_cmd_inprogress; /* we didn't wait for 586 to accept + a command */ + +#if I82586_DEBUG +#define I82586_TRACE(s, e, d) \ +do { rtems_interrupt_level level; rtems_interrupt_disable (level); \ + (s)->trace_flow[(s)->trace_flow_in++] = (e); \ + (s)->trace_flow[(s)->trace_flow_in++] = (unsigned int)(d); \ + if ((s)->trace_flow_in >= I82586_TRACE_FLOW) { \ + (s)->trace_flow_in = 0; \ + (s)->trace_flow_wrap = 1; \ + } \ + rtems_interrupt_enable (level); \ + } while (0) + + int sc_debug; + unsigned int trace_flow[I82586_TRACE_FLOW * 2]; + unsigned int trace_flow_wrap; +#endif + unsigned int trace_flow_in; +}; + +/* Exported functions */ +rtems_isr i82586_intr (rtems_vector_number , void *); +int i82586_proberam (struct ie_softc *); +int i82586_attach (struct rtems_bsdnet_ifconfig *config, int attaching); + +/* Shortcut macros to optional (driver uses default if unspecified) callbacks */ +#define xIE_BUS_BARRIER(sc, offset, length, flags) \ +do { \ + if ((sc)->ie_bus_barrier) \ + ((sc)->ie_bus_barrier)((sc), (offset), (length), (flags));\ + else \ + bus_space_barrier((sc)->bt, (sc)->bh, (offset), (length), \ + (flags)); \ +} while (0) + +#define IE_BUS_BARRIER(sc, offset, length, flags) diff --git a/bsps/include/libchip/icm7170.h b/bsps/include/libchip/icm7170.h new file mode 100644 index 0000000000..6b95c905a4 --- /dev/null +++ b/bsps/include/libchip/icm7170.h @@ -0,0 +1,97 @@ +/* + * This file contains the definitions for the following real-time clocks: + * + * + Harris Semiconduction ICM7170 + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __LIBCHIP_ICM7170_h +#define __LIBCHIP_ICM7170_h + +/* + * Register indices + */ + +#define ICM7170_CONTROL 0x11 + + +#define ICM7170_COUNTER_HUNDREDTHS 0x00 +#define ICM7170_HOUR 0x01 +#define ICM7170_MINUTE 0x02 +#define ICM7170_SECOND 0x03 +#define ICM7170_MONTH 0x04 +#define ICM7170_DATE 0x05 +#define ICM7170_YEAR 0x06 +#define ICM7170_DAY_OF_WEEK 0x07 + +/* + * Configuration information in the parameters field + */ + +#define ICM7170_AT_32_KHZ 0x00 +#define ICM7170_AT_1_MHZ 0x01 +#define ICM7170_AT_2_MHZ 0x02 +#define ICM7170_AT_4_MHZ 0x03 + +/* + * Driver function table + */ + +extern rtc_fns icm7170_fns; + +/* + * Default register access routines + */ + +uint32_t icm7170_get_register( /* registers are at 1 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void icm7170_set_register( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +uint32_t icm7170_get_register_2( /* registers are at 2 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void icm7170_set_register_2( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +uint32_t icm7170_get_register_4( /* registers are at 4 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void icm7170_set_register_4( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +uint32_t icm7170_get_register_8( /* registers are at 8 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void icm7170_set_register_8( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +#endif +/* end of include file */ diff --git a/bsps/include/libchip/ide_ctrl.h b/bsps/include/libchip/ide_ctrl.h new file mode 100644 index 0000000000..de32e4bed9 --- /dev/null +++ b/bsps/include/libchip/ide_ctrl.h @@ -0,0 +1,35 @@ +/* + * ide_ctrl.h + * + * This file describes the IDE controller driver for all boards. + * + * Copyright (C) 2002 OKTET Ltd., St.-Petersburg, Russia + * Author: Eugeny S. Mints <Eugeny.Mints@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __IDE_CTRL_H__ +#define __IDE_CTRL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +rtems_device_driver ide_controller_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *args); + + +#define IDE_CONTROLLER_DRIVER_TABLE_ENTRY \ + {ide_controller_initialize, NULL, NULL, NULL, NULL, NULL} + + +#ifdef __cplusplus +} +#endif + + +#endif /* __IDE_CTRL_H__ */ diff --git a/bsps/include/libchip/ide_ctrl_cfg.h b/bsps/include/libchip/ide_ctrl_cfg.h new file mode 100644 index 0000000000..3339a28d2b --- /dev/null +++ b/bsps/include/libchip/ide_ctrl_cfg.h @@ -0,0 +1,123 @@ +/* + * ide_ctrl_cfg.h + * + * LibChip library IDE controller header file - structures used for + * configuration and plugin interface definition. + * + * Copyright (C) 2002 OKTET Ltd., St.-Petersburg, Russia + * Author: Eugeny S. Mints <Eugeny.Mints@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __IDE_CTRL_CFG_H__ +#define __IDE_CTRL_CFG_H__ + +#include <rtems/blkdev.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Avaible drivers for IDE controllers + */ +typedef enum { + IDE_STD, + IDE_CUSTOM /* BSP specific driver */ +} ide_ctrl_devs_t; + +/* ATA modes: bit masks used in ctrl_config_io_speed call */ +#define ATA_MODES_PIO3 0x001 +#define ATA_MODES_PIO4 0x002 + +#define ATA_MODES_PIO 0x003 + +#define ATA_MODES_DMA0 0x004 +#define ATA_MODES_DMA1 0x008 +#define ATA_MODES_DMA2 0x010 + +#define ATA_MODES_UDMA0 0x020 +#define ATA_MODES_UDMA1 0x040 +#define ATA_MODES_UDMA2 0x080 +#define ATA_MODES_UDMA3 0x100 +#define ATA_MODES_UDMA4 0x200 +#define ATA_MODES_UDMA5 0x400 + +#define ATA_MODES_UDMA 0x7e0 +#define ATA_MODES_DMA 0x7fc + + +/* + * Each driver for a particular controller have to provide following + * functions in such a structure. The only field which should not be NULL + * is contInit. + */ +typedef struct ide_ctrl_fns_s { + bool (*ctrl_probe)(int minor); /* probe routine */ + void (*ctrl_initialize)(int minor); + int (*ctrl_control)(int minor, uint32_t command, + void *arg); + /* + * Functions which allow read/write registers of a particular controller. + * (these functions may be used from ide_controller_read_register, + * ide_controller_write_register) + */ + void (*ctrl_reg_read)(int minor, int regist, uint16_t *value); + void (*ctrl_reg_write)(int minor, int regist, uint16_t value); + + /* + * The function allows to escape overhead for read/write register + * functions calls + */ + void (*ctrl_read_block)(int minor, uint32_t block_size, + rtems_blkdev_sg_buffer *bufs, uint32_t *cbuf, + uint32_t *pos); + void (*ctrl_write_block)(int minor, uint32_t block_size, + rtems_blkdev_sg_buffer *bufs, uint32_t *cbuf, + uint32_t *pos); + + rtems_status_code (*ctrl_config_io_speed)(int minor, + uint16_t modes_available); +} ide_ctrl_fns_t; + +/* + * IDE Controller configuration. Table of such configurations is provided + * by BSP + */ +typedef struct ide_controller_bsp_table_s { + char *name; /* device name */ + ide_ctrl_devs_t type; /* chip type */ + ide_ctrl_fns_t *fns; /* pointer to the set of driver routines */ + bool (*probe)(int minor); /* general probe routine */ + uint8_t status; /* initialized/non initialized. Should be set + * to zero by static initialization + */ + uint32_t port1; /* port number for the port of the device */ + bool int_driven; /* interrupt/poll driven */ + rtems_vector_number int_vec; /* the interrupt vector of the device */ + void *params; /* contains either device specific data or a + * pointer to s device specific information + * table + */ +} ide_controller_bsp_table_t; + +/* IDE controllers Table */ +extern ide_controller_bsp_table_t IDE_Controller_Table[]; + +/* Number of rows in IDE_Controller_Table */ +extern unsigned long IDE_Controller_Count; + + +#define IDE_CTRL_MAX_MINOR_NUMBER 4 + +#define IDE_CTRL_NON_INITIALIZED 0 +#define IDE_CTRL_INITIALIZED 1 + +#ifdef __cplusplus +} +#endif + + +#endif /* __IDE_CTRL_CFG_H__ */ diff --git a/bsps/include/libchip/ide_ctrl_io.h b/bsps/include/libchip/ide_ctrl_io.h new file mode 100644 index 0000000000..9534b0e88f --- /dev/null +++ b/bsps/include/libchip/ide_ctrl_io.h @@ -0,0 +1,186 @@ +/* + * ide_ctrl_io.h + * + * LibChip library IDE controller header file - IO operations defined for + * IDE controllers. + * + * Copyright (C) 2002 OKTET Ltd., St.-Petersburg, Russia + * Author: Eugeny S. Mints <Eugeny.Mints@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef __IDE_CTRL_IO_H__ +#define __IDE_CTRL_IO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems/blkdev.h> + +/* Command Block Registers */ +#define IDE_REGISTER_DATA 0 +#define IDE_REGISTER_ERROR 1 +#define IDE_REGISTER_FEATURES IDE_REGISTER_ERROR +#define IDE_REGISTER_SECTOR_COUNT 2 +#define IDE_REGISTER_SECTOR_NUMBER 3 +#define IDE_REGISTER_LBA0 IDE_REGISTER_SECTOR_NUMBER +#define IDE_REGISTER_CYLINDER_LOW 4 +#define IDE_REGISTER_LBA1 IDE_REGISTER_CYLINDER_LOW +#define IDE_REGISTER_CYLINDER_HIGH 5 +#define IDE_REGISTER_LBA2 IDE_REGISTER_CYLINDER_HIGH +#define IDE_REGISTER_DEVICE_HEAD 6 +#define IDE_REGISTER_LBA3 IDE_REGISTER_DEVICE_HEAD +#define IDE_REGISTER_STATUS 7 +#define IDE_REGISTER_COMMAND IDE_REGISTER_STATUS + +/* Control Block Registers */ +#define IDE_REGISTER_ALTERNATE_STATUS 6 +#define IDE_REGISTER_DEVICE_CONTROL IDE_REGISTER_ALTERNATE_STATUS + +/* offsets used to access registers */ +#define IDE_REGISTER_DEVICE_CONTROL_OFFSET 8 +#define IDE_REGISTER_ALTERNATE_STATUS_OFFSET IDE_REGISTER_DEVICE_CONTROL_OFFSET +#define IDE_REGISTER_DATA_BYTE 9 +#define IDE_REGISTER_DATA_WORD 10 + +/* + * Registers bits + */ +#define IDE_REGISTER_STATUS_BSY 0x80 /* Busy bit */ +#define IDE_REGISTER_STATUS_DRDY 0x40 /* Device ready */ +#define IDE_REGISTER_STATUS_DF 0x20 /* Device fault */ +#define IDE_REGISTER_STATUS_DSC 0x10 /* Device seek complete-- */ + /* obsolete */ +#define IDE_REGISTER_STATUS_DRQ 0x08 /* Data request */ +#define IDE_REGISTER_STATUS_CORR 0x04 /* Corrected data-- */ + /* vendor specific--obsolete */ +#define IDE_REGISTER_STATUS_IDX 0x02 /* Index-- */ + /* vendor specific--obsolete */ +#define IDE_REGISTER_STATUS_ERR 0x01 /* Error */ + +#define IDE_REGISTER_DEVICE_CONTROL_SRST 0x04 /* Host software reset bit */ +#define IDE_REGISTER_DEVICE_CONTROL_nIEN 0x02 /* Negated interrupt enable */ + +#define IDE_REGISTER_DEVICE_HEAD_L 0x40 /* LBA mode bit */ +#define IDE_REGISTER_DEVICE_HEAD_DEV 0x10 /* Device0/Device1 bit */ +#define IDE_REGISTER_DEVICE_HEAD_DEV_POS 4 /* Dev0/Dev1 bit position */ +#define IDE_REGISTER_DEVICE_HEAD_HS 0x0f /* Head/LBA24_27 bits */ +#define IDE_REGISTER_LBA3_L 0x40 +#define IDE_REGISTER_LBA3_DEV 0x10 +#define IDE_REGISTER_LBA3_LBA 0x0f + +#define IDE_REGISTER_ERROR_ICRC (1 << 7) /* Interface CRC error on */ + /* UDMA data transfer */ +#define IDE_REGISTER_ERROR_UNC (1 << 6) /* Uncorrectable data error */ +#if CCJ_COULD_NOT_FIND_THIS_ERROR +#define IDE_REGISTER_ERROR_WP (1 << 6) /* Write protect */ +#endif +#define IDE_REGISTER_ERROR_MC (1 << 5) /* Media changed */ +#define IDE_REGISTER_ERROR_IDNF (1 << 4) /* Sector ID not found */ +#define IDE_REGISTER_ERROR_MCR (1 << 3) /* Media change requested */ + /* obsolette */ +#define IDE_REGISTER_ERROR_ABRT (1 << 2) /* Aborted command */ +#define IDE_REGISTER_ERROR_NM (1 << 1) /* No media, End of Media. */ +#define IDE_REGISTER_ERROR_AMNF (1 << 0) /* Address mark not found */ + /* --obsolette in ATA-4 */ +#define IDE_REGISTER_ERROR_MED (1 << 0) /* Media error is detected */ + +/* + * ide_controller_read_data_block -- + * Read data block via controller's data register + * + * PARAMETERS: + * minor - minor number of controller + * block_size - number of bytes to read + * bufs - set of buffers to store data + * cbuf - number of current buffer from the set + * pos - position inside current buffer 'cbuf' + * + * RETURNS: + * NONE + */ +void +ide_controller_read_data_block(rtems_device_minor_number minor, + uint32_t block_size, + rtems_blkdev_sg_buffer *bufs, + uint32_t *cbuf, + uint32_t *pos); + +/* + * ide_controller_write_data_block -- + * Write data block via controller's data register + * + * PARAMETERS: + * minor - minor number of controller + * block_size - number of bytes to write + * bufs - set of buffers which store data + * cbuf - number of current buffer from the set + * pos - position inside current buffer 'cbuf' + * + * RETURNS: + * NONE + */ +void +ide_controller_write_data_block(rtems_device_minor_number minor, + uint32_t block_size, + rtems_blkdev_sg_buffer *bufs, + uint32_t *cbuf, + uint32_t *pos); + +/* + * ide_controller_read_register -- + * Read controller's register + * + * PARAMETERS: + * minor - minor number of controller + * reg - register to read + * value - placeholder for result + * + * RETURNS + * NONE + */ +void +ide_controller_read_register(rtems_device_minor_number minor, + int reg, + uint16_t *value); + +/* + * ide_controller_write_register -- + * Write controller's register + * + * PARAMETERS: + * minor - minor number of controller + * reg - register to write + * value - value to write + * + * RETURNS: + * NONE + */ +void +ide_controller_write_register(rtems_device_minor_number minor, + int reg, uint16_t value); + +/* + * ide_controller_config_io_speed -- + * Set controller's speed of IO operations + * + * PARAMETERS: + * minor - minor number of controller + * modes_available - speeds available + * + * RETURNS: + * RTEMS_SUCCESSFUL on success, or error code if + * error occured + */ +rtems_status_code +ide_controller_config_io_speed(int minor, uint16_t modes_available); + +#ifdef __cplusplus +} +#endif + + +#endif /* __IDE_CTRL_IO_H__ */ diff --git a/bsps/include/libchip/if_dcreg.h b/bsps/include/libchip/if_dcreg.h new file mode 100644 index 0000000000..07395c1884 --- /dev/null +++ b/bsps/include/libchip/if_dcreg.h @@ -0,0 +1,1120 @@ +/* + * Copyright (c) 1997, 1998, 1999 + * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/pci/if_dcreg.h,v 1.4.2.21 2003/02/12 22:19:34 mbr Exp $ + */ + +/* + * 21143 and clone common register definitions. + */ + +#define DC_BUSCTL 0x00 /* bus control */ +#define DC_TXSTART 0x08 /* tx start demand */ +#define DC_RXSTART 0x10 /* rx start demand */ +#define DC_RXADDR 0x18 /* rx descriptor list start addr */ +#define DC_TXADDR 0x20 /* tx descriptor list start addr */ +#define DC_ISR 0x28 /* interrupt status register */ +#define DC_NETCFG 0x30 /* network config register */ +#define DC_IMR 0x38 /* interrupt mask */ +#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ +#define DC_SIO 0x48 /* MII and ROM/EEPROM access */ +#define DC_ROM 0x50 /* ROM programming address */ +#define DC_TIMER 0x58 /* general timer */ +#define DC_10BTSTAT 0x60 /* SIA status */ +#define DC_SIARESET 0x68 /* SIA connectivity */ +#define DC_10BTCTRL 0x70 /* SIA transmit and receive */ +#define DC_WATCHDOG 0x78 /* SIA and general purpose port */ + +/* + * There are two general 'types' of MX chips that we need to be + * concerned with. One is the original 98713, which has its internal + * NWAY support controlled via the MDIO bits in the serial I/O + * register. The other is everything else (from the 98713A on up), + * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, + * just like the 21143. This type setting also governs which of the + * 'magic' numbers we write to CSR16. The PNIC II falls into the + * 98713A/98715/98715A/98725 category. + */ +#define DC_TYPE_98713 0x1 +#define DC_TYPE_98713A 0x2 +#define DC_TYPE_987x5 0x3 + +/* Other type of supported chips. */ +#define DC_TYPE_21143 0x4 /* Intel 21143 */ +#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ +#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ +#define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */ +#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ +#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ +#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ +#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */ + +#define DC_IS_MACRONIX(x) \ + (x->dc_type == DC_TYPE_98713 || \ + x->dc_type == DC_TYPE_98713A || \ + x->dc_type == DC_TYPE_987x5) + +#define DC_IS_ADMTEK(x) \ + (x->dc_type == DC_TYPE_AL981 || \ + x->dc_type == DC_TYPE_AN985) + +#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) +#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) +#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) +#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985) +#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) +#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) +#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) +#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT) + +/* MII/symbol mode port types */ +#define DC_PMODE_MII 0x1 +#define DC_PMODE_SYM 0x2 +#define DC_PMODE_SIA 0x3 + +/* + * Bus control bits. + */ +#define DC_BUSCTL_RESET 0x00000001 +#define DC_BUSCTL_ARBITRATION 0x00000002 +#define DC_BUSCTL_SKIPLEN 0x0000007C +#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 +#define DC_BUSCTL_BURSTLEN 0x00003F00 +#define DC_BUSCTL_CACHEALIGN 0x0000C000 +#define DC_BUSCTL_TXPOLL 0x000E0000 +#define DC_BUSCTL_DBO 0x00100000 +#define DC_BUSCTL_MRME 0x00200000 +#define DC_BUSCTL_MRLE 0x00800000 +#define DC_BUSCTL_MWIE 0x01000000 +#define DC_BUSCTL_ONNOW_ENB 0x04000000 + +#define DC_SKIPLEN_1LONG 0x00000004 +#define DC_SKIPLEN_2LONG 0x00000008 +#define DC_SKIPLEN_3LONG 0x00000010 +#define DC_SKIPLEN_4LONG 0x00000020 +#define DC_SKIPLEN_5LONG 0x00000040 + +#define DC_CACHEALIGN_NONE 0x00000000 +#define DC_CACHEALIGN_8LONG 0x00004000 +#define DC_CACHEALIGN_16LONG 0x00008000 +#define DC_CACHEALIGN_32LONG 0x0000C000 + +#define DC_BURSTLEN_USECA 0x00000000 +#define DC_BURSTLEN_1LONG 0x00000100 +#define DC_BURSTLEN_2LONG 0x00000200 +#define DC_BURSTLEN_4LONG 0x00000400 +#define DC_BURSTLEN_8LONG 0x00000800 +#define DC_BURSTLEN_16LONG 0x00001000 +#define DC_BURSTLEN_32LONG 0x00002000 + +#define DC_TXPOLL_OFF 0x00000000 +#define DC_TXPOLL_1 0x00020000 +#define DC_TXPOLL_2 0x00040000 +#define DC_TXPOLL_3 0x00060000 +#define DC_TXPOLL_4 0x00080000 +#define DC_TXPOLL_5 0x000A0000 +#define DC_TXPOLL_6 0x000C0000 +#define DC_TXPOLL_7 0x000E0000 + +/* + * Interrupt status bits. + */ +#define DC_ISR_TX_OK 0x00000001 +#define DC_ISR_TX_IDLE 0x00000002 +#define DC_ISR_TX_NOBUF 0x00000004 +#define DC_ISR_TX_JABBERTIMEO 0x00000008 +#define DC_ISR_LINKGOOD 0x00000010 +#define DC_ISR_TX_UNDERRUN 0x00000020 +#define DC_ISR_RX_OK 0x00000040 +#define DC_ISR_RX_NOBUF 0x00000080 +#define DC_ISR_RX_READ 0x00000100 +#define DC_ISR_RX_WATDOGTIMEO 0x00000200 +#define DC_ISR_TX_EARLY 0x00000400 +#define DC_ISR_TIMER_EXPIRED 0x00000800 +#define DC_ISR_LINKFAIL 0x00001000 +#define DC_ISR_BUS_ERR 0x00002000 +#define DC_ISR_RX_EARLY 0x00004000 +#define DC_ISR_ABNORMAL 0x00008000 +#define DC_ISR_NORMAL 0x00010000 +#define DC_ISR_RX_STATE 0x000E0000 +#define DC_ISR_TX_STATE 0x00700000 +#define DC_ISR_BUSERRTYPE 0x03800000 +#define DC_ISR_100MBPSLINK 0x08000000 +#define DC_ISR_MAGICKPACK 0x10000000 + +#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ +#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ +#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ +#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ +#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ +#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ +#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ +#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ + +#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ +#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ +#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ +#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ +#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ +#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ +#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ +#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ + +/* + * Network config bits. + */ +#define DC_NETCFG_RX_HASHPERF 0x00000001 +#define DC_NETCFG_RX_ON 0x00000002 +#define DC_NETCFG_RX_HASHONLY 0x00000004 +#define DC_NETCFG_RX_BADFRAMES 0x00000008 +#define DC_NETCFG_RX_INVFILT 0x00000010 +#define DC_NETCFG_BACKOFFCNT 0x00000020 +#define DC_NETCFG_RX_PROMISC 0x00000040 +#define DC_NETCFG_RX_ALLMULTI 0x00000080 +#define DC_NETCFG_FULLDUPLEX 0x00000200 +#define DC_NETCFG_LOOPBACK 0x00000C00 +#define DC_NETCFG_FORCECOLL 0x00001000 +#define DC_NETCFG_TX_ON 0x00002000 +#define DC_NETCFG_TX_THRESH 0x0000C000 +#define DC_NETCFG_TX_BACKOFF 0x00020000 +#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ +#define DC_NETCFG_HEARTBEAT 0x00080000 +#define DC_NETCFG_STORENFWD 0x00200000 +#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ +#define DC_NETCFG_PCS 0x00800000 +#define DC_NETCFG_SCRAMBLER 0x01000000 +#define DC_NETCFG_NO_RXCRC 0x02000000 +#define DC_NETCFG_RX_ALL 0x40000000 +#define DC_NETCFG_CAPEFFECT 0x80000000 + +#define DC_OPMODE_NORM 0x00000000 +#define DC_OPMODE_INTLOOP 0x00000400 +#define DC_OPMODE_EXTLOOP 0x00000800 + +#if 0 +#define DC_TXTHRESH_72BYTES 0x00000000 +#define DC_TXTHRESH_96BYTES 0x00004000 +#define DC_TXTHRESH_128BYTES 0x00008000 +#define DC_TXTHRESH_160BYTES 0x0000C000 +#endif + +#define DC_TXTHRESH_MIN 0x00000000 +#define DC_TXTHRESH_INC 0x00004000 +#define DC_TXTHRESH_MAX 0x0000C000 + + +/* + * Interrupt mask bits. + */ +#define DC_IMR_TX_OK 0x00000001 +#define DC_IMR_TX_IDLE 0x00000002 +#define DC_IMR_TX_NOBUF 0x00000004 +#define DC_IMR_TX_JABBERTIMEO 0x00000008 +#define DC_IMR_LINKGOOD 0x00000010 +#define DC_IMR_TX_UNDERRUN 0x00000020 +#define DC_IMR_RX_OK 0x00000040 +#define DC_IMR_RX_NOBUF 0x00000080 +#define DC_IMR_RX_READ 0x00000100 +#define DC_IMR_RX_WATDOGTIMEO 0x00000200 +#define DC_IMR_TX_EARLY 0x00000400 +#define DC_IMR_TIMER_EXPIRED 0x00000800 +#define DC_IMR_LINKFAIL 0x00001000 +#define DC_IMR_BUS_ERR 0x00002000 +#define DC_IMR_RX_EARLY 0x00004000 +#define DC_IMR_ABNORMAL 0x00008000 +#define DC_IMR_NORMAL 0x00010000 +#define DC_IMR_100MBPSLINK 0x08000000 +#define DC_IMR_MAGICKPACK 0x10000000 + +#define DC_INTRS \ + (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ + DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ + DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) +/* + * Serial I/O (EEPROM/ROM) bits. + */ +#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ +#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ +#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ +#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ +#define DC_SIO_ROMDATA4 0x00000010 +#define DC_SIO_ROMDATA5 0x00000020 +#define DC_SIO_ROMDATA6 0x00000040 +#define DC_SIO_ROMDATA7 0x00000080 +#define DC_SIO_EESEL 0x00000800 +#define DC_SIO_ROMSEL 0x00001000 +#define DC_SIO_ROMCTL_WRITE 0x00002000 +#define DC_SIO_ROMCTL_READ 0x00004000 +#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ +#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ +#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ +#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ + +#define DC_EECMD_WRITE 0x140 +#define DC_EECMD_READ 0x180 +#define DC_EECMD_ERASE 0x1c0 + +#define DC_EE_NODEADDR_OFFSET 0x70 +#define DC_EE_NODEADDR 10 + +/* + * General purpose timer register + */ +#define DC_TIMER_VALUE 0x0000FFFF +#define DC_TIMER_CONTINUOUS 0x00010000 + +/* + * 10baseT status register + */ +#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ +#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ +#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ +#define DC_TSTAT_AUTOPOLARITY 0x00000008 +#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ +#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ +#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ +#define DC_TSTAT_REMFAULT 0x00000800 +#define DC_TSTAT_ANEGSTAT 0x00007000 +#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ +#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ + +#define DC_ASTAT_DISABLE 0x00000000 +#define DC_ASTAT_TXDISABLE 0x00001000 +#define DC_ASTAT_ABDETECT 0x00002000 +#define DC_ASTAT_ACKDETECT 0x00003000 +#define DC_ASTAT_CMPACKDETECT 0x00004000 +#define DC_ASTAT_AUTONEGCMP 0x00005000 +#define DC_ASTAT_LINKCHECK 0x00006000 + +/* + * PHY reset register + */ +#define DC_SIA_RESET 0x00000001 +#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ + +/* + * 10baseT control register + */ +#define DC_TCTL_ENCODER_ENB 0x00000001 +#define DC_TCTL_LOOPBACK 0x00000002 +#define DC_TCTL_DRIVER_ENB 0x00000004 +#define DC_TCTL_LNKPULSE_ENB 0x00000008 +#define DC_TCTL_HALFDUPLEX 0x00000040 +#define DC_TCTL_AUTONEGENBL 0x00000080 +#define DC_TCTL_RX_SQUELCH 0x00000100 +#define DC_TCTL_COLL_SQUELCH 0x00000200 +#define DC_TCTL_COLL_DETECT 0x00000400 +#define DC_TCTL_SQE_ENB 0x00000800 +#define DC_TCTL_LINKTEST 0x00001000 +#define DC_TCTL_AUTOPOLARITY 0x00002000 +#define DC_TCTL_SET_POL_PLUS 0x00004000 +#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ +#define DC_TCTL_100BTXHALF 0x00010000 +#define DC_TCTL_100BTXFULL 0x00020000 +#define DC_TCTL_100BT4 0x00040000 + +/* + * Watchdog timer register + */ +#define DC_WDOG_JABBERDIS 0x00000001 +#define DC_WDOG_HOSTUNJAB 0x00000002 +#define DC_WDOG_JABBERCLK 0x00000004 +#define DC_WDOG_RXWDOGDIS 0x00000010 +#define DC_WDOG_RXWDOGCLK 0x00000020 +#define DC_WDOG_MUSTBEZERO 0x00000100 +#define DC_WDOG_AUIBNC 0x00100000 +#define DC_WDOG_ACTIVITY 0x00200000 +#define DC_WDOG_RX_MATCH 0x00400000 +#define DC_WDOG_LINK 0x00800000 +#define DC_WDOG_CTLWREN 0x08000000 + +/* + * Size of a setup frame. + */ +#define DC_SFRAME_LEN 192 + +/* + * 21x4x TX/RX list structure. + */ + +struct dc_desc { + u_int32_t dc_status; + u_int32_t dc_ctl; + u_int32_t dc_ptr1; + u_int32_t dc_ptr2; +}; + +#define dc_data dc_ptr1 +#define dc_next dc_ptr2 + +#define DC_RXSTAT_FIFOOFLOW 0x00000001 +#define DC_RXSTAT_CRCERR 0x00000002 +#define DC_RXSTAT_DRIBBLE 0x00000004 +#define DC_RXSTAT_MIIERE 0x00000008 +#define DC_RXSTAT_WATCHDOG 0x00000010 +#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ +#define DC_RXSTAT_COLLSEEN 0x00000040 +#define DC_RXSTAT_GIANT 0x00000080 +#define DC_RXSTAT_LASTFRAG 0x00000100 +#define DC_RXSTAT_FIRSTFRAG 0x00000200 +#define DC_RXSTAT_MULTICAST 0x00000400 +#define DC_RXSTAT_RUNT 0x00000800 +#define DC_RXSTAT_RXTYPE 0x00003000 +#define DC_RXSTAT_DE 0x00004000 +#define DC_RXSTAT_RXERR 0x00008000 +#define DC_RXSTAT_RXLEN 0x3FFF0000 +#define DC_RXSTAT_OWN 0x80000000 + +#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) +#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) + +#define DC_RXCTL_BUFLEN1 0x00000FFF +#define DC_RXCTL_BUFLEN2 0x00FFF000 +#define DC_RXCTL_RLINK 0x01000000 +#define DC_RXCTL_RLAST 0x02000000 + +#define DC_TXSTAT_DEFER 0x00000001 +#define DC_TXSTAT_UNDERRUN 0x00000002 +#define DC_TXSTAT_LINKFAIL 0x00000003 +#define DC_TXSTAT_COLLCNT 0x00000078 +#define DC_TXSTAT_SQE 0x00000080 +#define DC_TXSTAT_EXCESSCOLL 0x00000100 +#define DC_TXSTAT_LATECOLL 0x00000200 +#define DC_TXSTAT_NOCARRIER 0x00000400 +#define DC_TXSTAT_CARRLOST 0x00000800 +#define DC_TXSTAT_JABTIMEO 0x00004000 +#define DC_TXSTAT_ERRSUM 0x00008000 +#define DC_TXSTAT_OWN 0x80000000 + +#define DC_TXCTL_BUFLEN1 0x000007FF +#define DC_TXCTL_BUFLEN2 0x003FF800 +#define DC_TXCTL_FILTTYPE0 0x00400000 +#define DC_TXCTL_PAD 0x00800000 +#define DC_TXCTL_TLINK 0x01000000 +#define DC_TXCTL_TLAST 0x02000000 +#define DC_TXCTL_NOCRC 0x04000000 +#define DC_TXCTL_SETUP 0x08000000 +#define DC_TXCTL_FILTTYPE1 0x10000000 +#define DC_TXCTL_FIRSTFRAG 0x20000000 +#define DC_TXCTL_LASTFRAG 0x40000000 +#define DC_TXCTL_FINT 0x80000000 + +#define DC_FILTER_PERFECT 0x00000000 +#define DC_FILTER_HASHPERF 0x00400000 +#define DC_FILTER_INVERSE 0x10000000 +#define DC_FILTER_HASHONLY 0x10400000 + +#define DC_MAXFRAGS 16 +#ifdef DEVICE_POLLING +#define DC_RX_LIST_CNT 192 +#else +#define DC_RX_LIST_CNT 64 +#endif +#define DC_TX_LIST_CNT 256 +#define DC_MIN_FRAMELEN 60 +#define DC_RXLEN 1536 + +#define DC_INC(x, y) (x) = (x + 1) % y + +struct dc_list_data { + struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; + struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; +}; + +struct dc_chain_data { + struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; + struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; + u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)]; + u_int8_t dc_pad[DC_MIN_FRAMELEN]; + int dc_tx_prod; + int dc_tx_cons; + int dc_tx_cnt; + int dc_rx_prod; +}; + +struct dc_mediainfo { + int dc_media; + u_int8_t *dc_gp_ptr; + u_int8_t dc_gp_len; + u_int8_t *dc_reset_ptr; + u_int8_t dc_reset_len; + struct dc_mediainfo *dc_next; +}; + + +struct dc_type { + u_int16_t dc_vid; + u_int16_t dc_did; + char *dc_name; + int dc_devsig; + int dc_bus; + int dc_dev; + int dc_fun; +}; + +struct dc_mii_frame { + u_int8_t mii_stdelim; + u_int8_t mii_opcode; + u_int8_t mii_phyaddr; + u_int8_t mii_regaddr; + u_int8_t mii_turnaround; + u_int16_t mii_data; +}; + +/* + * MII constants + */ +#define DC_MII_STARTDELIM 0x01 +#define DC_MII_READOP 0x02 +#define DC_MII_WRITEOP 0x01 +#define DC_MII_TURNAROUND 0x02 + + +/* + * Registers specific to clone devices. + * This mainly relates to RX filter programming: not all 21x4x clones + * use the standard DEC filter programming mechanism. + */ + +/* + * ADMtek specific registers and constants for the AL981 and AN985. + * The AN985 doesn't use the magic PHY registers. + */ +#define DC_AL_CR 0x88 /* command register */ +#define DC_AL_PAR0 0xA4 /* station address */ +#define DC_AL_PAR1 0xA8 /* station address */ +#define DC_AL_MAR0 0xAC /* multicast hash filter */ +#define DC_AL_MAR1 0xB0 /* multicast hash filter */ +#define DC_AL_BMCR 0xB4 /* built in PHY control */ +#define DC_AL_BMSR 0xB8 /* built in PHY status */ +#define DC_AL_VENID 0xBC /* built in PHY ID0 */ +#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ +#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ +#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ +#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ + +#define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */ +#define DC_ADMTEK_PHYADDR 0x1 +#define DC_AL_EE_NODEADDR 4 +/* End of ADMtek specific registers */ + +/* + * ASIX specific registers. + */ +#define DC_AX_FILTIDX 0x68 /* RX filter index */ +#define DC_AX_FILTDATA 0x70 /* RX filter data */ + +/* + * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). + */ +#define DC_AX_NETCFG_RX_BROAD 0x00000100 + +/* + * RX Filter Index Register values + */ +#define DC_AX_FILTIDX_PAR0 0x00000000 +#define DC_AX_FILTIDX_PAR1 0x00000001 +#define DC_AX_FILTIDX_MAR0 0x00000002 +#define DC_AX_FILTIDX_MAR1 0x00000003 +/* End of ASIX specific registers */ + +/* + * Macronix specific registers. The Macronix chips have a special + * register for reading the NWAY status, which we don't use, plus + * a magic packet register, which we need to tweak a bit per the + * Macronix application notes. + */ +#define DC_MX_MAGICPACKET 0x80 +#define DC_MX_NWAYSTAT 0xA0 + +/* + * Magic packet register + */ +#define DC_MX_MPACK_DISABLE 0x00400000 + +/* + * NWAY status register. + */ +#define DC_MX_NWAY_10BTHALF 0x08000000 +#define DC_MX_NWAY_10BTFULL 0x10000000 +#define DC_MX_NWAY_100BTHALF 0x20000000 +#define DC_MX_NWAY_100BTFULL 0x40000000 +#define DC_MX_NWAY_100BT4 0x80000000 + +/* + * These are magic values that must be written into CSR16 + * (DC_MX_MAGICPACKET) in order to put the chip into proper + * operating mode. The magic numbers are documented in the + * Macronix 98715 application notes. + */ +#define DC_MX_MAGIC_98713 0x0F370000 +#define DC_MX_MAGIC_98713A 0x0B3C0000 +#define DC_MX_MAGIC_98715 0x0B3C0000 +#define DC_MX_MAGIC_98725 0x0B3C0000 +/* End of Macronix specific registers */ + +/* + * PNIC 82c168/82c169 specific registers. + * The PNIC has its own special NWAY support, which doesn't work, + * and shortcut ways of reading the EEPROM and MII bus. + */ +#define DC_PN_GPIO 0x60 /* general purpose pins control */ +#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ +#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ +#define DC_PN_MII 0xA0 /* MII access register */ +#define DC_PN_NWAY 0xB8 /* Internal NWAY register */ + +/* Serial I/O EEPROM register */ +#define DC_PN_SIOCTL_DATA 0x0000003F +#define DC_PN_SIOCTL_OPCODE 0x00000300 +#define DC_PN_SIOCTL_BUSY 0x80000000 + +#define DC_PN_EEOPCODE_ERASE 0x00000300 +#define DC_PN_EEOPCODE_READ 0x00000600 +#define DC_PN_EEOPCODE_WRITE 0x00000100 + +/* + * The first two general purpose pins control speed selection and + * 100Mbps loopback on the 82c168 chip. The control bits should always + * be set (to make the data pins outputs) and the speed selction and + * loopback bits set accordingly when changing media. Physically, this + * will set the state of a relay mounted on the card. + */ +#define DC_PN_GPIO_DATA0 0x000000001 +#define DC_PN_GPIO_DATA1 0x000000002 +#define DC_PN_GPIO_DATA2 0x000000004 +#define DC_PN_GPIO_DATA3 0x000000008 +#define DC_PN_GPIO_CTL0 0x000000010 +#define DC_PN_GPIO_CTL1 0x000000020 +#define DC_PN_GPIO_CTL2 0x000000040 +#define DC_PN_GPIO_CTL3 0x000000080 +#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ +#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ +#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 +#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 +#define DC_PN_GPIO_SETBIT(sc, r) \ + DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) +#define DC_PN_GPIO_CLRBIT(sc, r) \ + { \ + DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ + DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ + } + +/* shortcut MII access register */ +#define DC_PN_MII_DATA 0x0000FFFF +#define DC_PN_MII_RESERVER 0x00020000 +#define DC_PN_MII_REGADDR 0x007C0000 +#define DC_PN_MII_PHYADDR 0x0F800000 +#define DC_PN_MII_OPCODE 0x30000000 +#define DC_PN_MII_BUSY 0x80000000 + +#define DC_PN_MIIOPCODE_READ 0x60020000 +#define DC_PN_MIIOPCODE_WRITE 0x50020000 + +/* Internal NWAY bits */ +#define DC_PN_NWAY_RESET 0x00000001 /* reset */ +#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ +#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ +#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ +#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ +#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ +#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ +#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ +#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ +#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ +#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ +#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ +#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ +#define DC_PN_NWAY_CAP10HDX 0x00002000 +#define DC_PN_NWAY_CAP10FDX 0x00004000 +#define DC_PN_NWAY_CAP100FDX 0x00008000 +#define DC_PN_NWAY_CAP100HDX 0x00010000 +#define DC_PN_NWAY_CAP100T4 0x00020000 +#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ +#define DC_PN_NWAY_REMFAULT 0x04000000 +#define DC_PN_NWAY_LPAR10HDX 0x08000000 +#define DC_PN_NWAY_LPAR10FDX 0x10000000 +#define DC_PN_NWAY_LPAR100FDX 0x20000000 +#define DC_PN_NWAY_LPAR100HDX 0x40000000 +#define DC_PN_NWAY_LPAR100T4 0x80000000 + +/* End of PNIC specific registers */ + +/* + * CONEXANT specific registers. + */ + +#define DC_CONEXANT_PHYADDR 0x1 +#define DC_CONEXANT_EE_NODEADDR 0x19A + +/* End of CONEXANT specific registers */ + + +struct dc_softc { + struct arpcom arpcom; /* interface info */ + rtems_irq_connect_data irqInfo; + volatile u_int32_t membase; + rtems_id daemontid; +#if 0 + bus_space_handle_t dc_bhandle; /* bus space handle */ + bus_space_tag_t dc_btag; /* bus space tag */ + void *dc_intrhand; + struct resource *dc_irq; + struct resource *dc_res; +#endif + struct dc_type *dc_info; /* adapter info */ +/* device_t dc_miibus; */ + u_int8_t dc_unit; /* interface number */ + char *dc_name; + u_int8_t dc_type; + u_int8_t dc_pmode; + u_int8_t dc_link; + u_int8_t dc_cachesize; + int dc_romwidth; + int dc_pnic_rx_bug_save; + unsigned char *dc_pnic_rx_buf; + int dc_if_flags; + int dc_if_media; + u_int32_t dc_flags; + u_int32_t dc_txthresh; + u_int8_t *dc_srom; + struct dc_mediainfo *dc_mi; +/* + struct callout_handle dc_stat_ch; +*/ + struct dc_list_data *dc_ldata; + struct dc_chain_data dc_cdata; +#ifdef __alpha__ + int dc_srm_media; +#endif +#ifdef DEVICE_POLLING + int rxcycles; /* ... when polling */ +#endif + int suspended; /* 0 = normal 1 = suspended */ + + u_int32_t saved_maps[5]; /* pci data */ + u_int32_t saved_biosaddr; + u_int8_t saved_intline; + u_int8_t saved_cachelnsz; + u_int8_t saved_lattimer; +}; + +#define DC_TX_POLL 0x00000001 +#define DC_TX_COALESCE 0x00000002 +#define DC_TX_ADMTEK_WAR 0x00000004 +#define DC_TX_USE_TX_INTR 0x00000008 +#define DC_RX_FILTER_TULIP 0x00000010 +#define DC_TX_INTR_FIRSTFRAG 0x00000020 +#define DC_PNIC_RX_BUG_WAR 0x00000040 +#define DC_TX_FIXED_RING 0x00000080 +#define DC_TX_STORENFWD 0x00000100 +#define DC_REDUCED_MII_POLL 0x00000200 +#define DC_TX_INTR_ALWAYS 0x00000400 +#define DC_21143_NWAY 0x00000800 +#define DC_128BIT_HASH 0x00001000 +#define DC_64BIT_HASH 0x00002000 +#define DC_TULIP_LEDS 0x00004000 +#define DC_TX_ONE 0x00008000 + +/* + * register space access macros + */ +#define _readl_(addr) (*(volatile unsigned int *)((void *)(addr))) +#define _writel_(b, addr) (*(volatile unsigned int *)((void *)(addr)) = (b)) + +#define CSR_READ_4(sc, reg) _readl_(((sc->membase)+(reg))) +#define CSR_WRITE_4(sc, reg, val) _writel_(val, ((sc->membase)+(reg))) + + + + + + +#define DC_TIMEOUT 1000 +#define ETHER_ALIGN 2 + +/* + * General constants that are fun to know. + */ + +/* + * DEC PCI vendor ID + */ +#define DC_VENDORID_DEC 0x1011 + +/* + * DEC/Intel 21143 PCI device ID + */ +#define DC_DEVICEID_21143 0x0019 + +/* + * Macronix PCI vendor ID + */ +#define DC_VENDORID_MX 0x10D9 + +/* + * Macronix PMAC device IDs. + */ +#define DC_DEVICEID_98713 0x0512 +#define DC_DEVICEID_987x5 0x0531 +#define DC_DEVICEID_98727 0x0532 +#define DC_DEVICEID_98732 0x0532 + +/* Macronix PCI revision codes. */ +#define DC_REVISION_98713 0x00 +#define DC_REVISION_98713A 0x10 +#define DC_REVISION_98715 0x20 +#define DC_REVISION_98715AEC_C 0x25 +#define DC_REVISION_98725 0x30 + +/* + * Compex PCI vendor ID. + */ +#define DC_VENDORID_CP 0x11F6 + +/* + * Compex PMAC PCI device IDs. + */ +#define DC_DEVICEID_98713_CP 0x9881 + +/* + * Lite-On PNIC PCI vendor ID + */ +#define DC_VENDORID_LO 0x11AD + +/* + * 82c168/82c169 PNIC device IDs. Both chips have the same device + * ID but different revisions. Revision 0x10 is the 82c168, and + * 0x20 is the 82c169. + */ +#define DC_DEVICEID_82C168 0x0002 + +#define DC_REVISION_82C168 0x10 +#define DC_REVISION_82C169 0x20 + +/* + * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A + * with wake on lan/magic packet support. + */ +#define DC_DEVICEID_82C115 0xc115 + +/* + * Davicom vendor ID. + */ +#define DC_VENDORID_DAVICOM 0x1282 + +/* + * Davicom device IDs. + */ +#define DC_DEVICEID_DM9009 0x9009 +#define DC_DEVICEID_DM9100 0x9100 +#define DC_DEVICEID_DM9102 0x9102 + +/* + * The DM9102A has the same PCI device ID as the DM9102, + * but a higher revision code. + */ +#define DC_REVISION_DM9102 0x10 +#define DC_REVISION_DM9102A 0x30 + +/* + * ADMtek vendor ID. + */ +#define DC_VENDORID_ADMTEK 0x1317 + +/* + * ADMtek device IDs. + */ +#define DC_DEVICEID_AL981 0x0981 +#define DC_DEVICEID_AN985 0x0985 + +/* + * ASIX vendor ID. + */ +#define DC_VENDORID_ASIX 0x125B + +/* + * ASIX device IDs. + */ +#define DC_DEVICEID_AX88140A 0x1400 + +/* + * The ASIX AX88140 and ASIX AX88141 have the same vendor and + * device IDs but different revision values. + */ +#define DC_REVISION_88140 0x00 +#define DC_REVISION_88141 0x10 + +/* + * Accton vendor ID. + */ +#define DC_VENDORID_ACCTON 0x1113 + +/* + * Accton device IDs. + */ +#define DC_DEVICEID_EN1217 0x1217 +#define DC_DEVICEID_EN2242 0x1216 + +/* + * Conexant vendor ID. + */ +#define DC_VENDORID_CONEXANT 0x14f1 + +/* + * Conexant device IDs. + */ +#define DC_DEVICEID_RS7112 0x1803 + +/* + * PCI low memory base and low I/O base register, and + * other PCI registers. + */ + +#define DC_PCI_CFID 0x00 /* Id */ +#define DC_PCI_CFCS 0x04 /* Command and status */ +#define DC_PCI_CFRV 0x08 /* Revision */ +#define DC_PCI_CFLT 0x0C /* Latency timer */ +#define DC_PCI_CFBIO 0x10 /* Base I/O address */ +#define DC_PCI_CFBMA 0x14 /* Base memory address */ +#define DC_PCI_CCIS 0x28 /* Card info struct */ +#define DC_PCI_CSID 0x2C /* Subsystem ID */ +#define DC_PCI_CBER 0x30 /* Expansion ROM base address */ +#define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */ +#define DC_PCI_CFIT 0x3C /* Interrupt */ +#define DC_PCI_CFDD 0x40 /* Device and driver area */ +#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ +#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ +#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ +#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ +#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ +#define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */ +#define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */ + +/* PCI ID register */ +#define DC_CFID_VENDOR 0x0000FFFF +#define DC_CFID_DEVICE 0xFFFF0000 + +/* PCI command/status register */ +#define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */ +#define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */ +#define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */ +#define DC_CFCS_MWI_ENB 0x00000010 /* mem write and inval enable */ +#define DC_CFCS_PARITYERR_ENB 0x00000040 /* parity error enable */ +#define DC_CFCS_SYSERR_ENB 0x00000100 /* system error enable */ +#define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */ +#define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */ +#define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */ +#define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */ +#define DC_CFCS_TGTABRT 0x10000000 /* received target abort */ +#define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */ +#define DC_CFCS_SYSERR 0x40000000 /* asserted system error */ +#define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */ + +/* PCI revision register */ +#define DC_CFRV_STEPPING 0x0000000F +#define DC_CFRV_REVISION 0x000000F0 +#define DC_CFRV_SUBCLASS 0x00FF0000 +#define DC_CFRV_BASECLASS 0xFF000000 + +#define DC_21143_PB_REV 0x00000030 +#define DC_21143_TB_REV 0x00000030 +#define DC_21143_PC_REV 0x00000030 +#define DC_21143_TC_REV 0x00000030 +#define DC_21143_PD_REV 0x00000041 +#define DC_21143_TD_REV 0x00000041 + +/* PCI latency timer register */ +#define DC_CFLT_CACHELINESIZE 0x000000FF +#define DC_CFLT_LATENCYTIMER 0x0000FF00 + +/* PCI subsystem ID register */ +#define DC_CSID_VENDOR 0x0000FFFF +#define DC_CSID_DEVICE 0xFFFF0000 + +/* PCI cababilities pointer */ +#define DC_CCAP_OFFSET 0x000000FF + +/* PCI interrupt config register */ +#define DC_CFIT_INTLINE 0x000000FF +#define DC_CFIT_INTPIN 0x0000FF00 +#define DC_CFIT_MIN_GNT 0x00FF0000 +#define DC_CFIT_MAX_LAT 0xFF000000 + +/* PCI capability register */ +#define DC_CCID_CAPID 0x000000FF +#define DC_CCID_NEXTPTR 0x0000FF00 +#define DC_CCID_PM_VERS 0x00070000 +#define DC_CCID_PME_CLK 0x00080000 +#define DC_CCID_DVSPEC_INT 0x00200000 +#define DC_CCID_STATE_D1 0x02000000 +#define DC_CCID_STATE_D2 0x04000000 +#define DC_CCID_PME_D0 0x08000000 +#define DC_CCID_PME_D1 0x10000000 +#define DC_CCID_PME_D2 0x20000000 +#define DC_CCID_PME_D3HOT 0x40000000 +#define DC_CCID_PME_D3COLD 0x80000000 + +/* PCI power management control/status register */ +#define DC_CPMC_STATE 0x00000003 +#define DC_CPMC_PME_ENB 0x00000100 +#define DC_CPMC_PME_STS 0x00008000 + +#define DC_PSTATE_D0 0x0 +#define DC_PSTATE_D1 0x1 +#define DC_PSTATE_D2 0x2 +#define DC_PSTATE_D3 0x3 + +/* Device specific region */ +/* Configuration and driver area */ +#define DC_CFDD_DRVUSE 0x0000FFFF +#define DC_CFDD_SNOOZE_MODE 0x40000000 +#define DC_CFDD_SLEEP_MODE 0x80000000 + +/* Configuration wake-up command register */ +#define DC_CWUC_MUST_BE_ZERO 0x00000001 +#define DC_CWUC_SECUREON_ENB 0x00000002 +#define DC_CWUC_FORCE_WUL 0x00000004 +#define DC_CWUC_BNC_ABILITY 0x00000008 +#define DC_CWUC_AUI_ABILITY 0x00000010 +#define DC_CWUC_TP10_ABILITY 0x00000020 +#define DC_CWUC_MII_ABILITY 0x00000040 +#define DC_CWUC_SYM_ABILITY 0x00000080 +#define DC_CWUC_LOCK 0x00000100 + +/* + * SROM nonsense. + */ + +#define DC_IB_CTLRCNT 0x13 +#define DC_IB_LEAF0_CNUM 0x1A +#define DC_IB_LEAF0_OFFSET 0x1B + +struct dc_info_leaf { + u_int16_t dc_conntype; + u_int8_t dc_blkcnt; + u_int8_t dc_rsvd; + u_int16_t dc_infoblk; +}; + +#define DC_CTYPE_10BT 0x0000 +#define DC_CTYPE_10BT_NWAY 0x0100 +#define DC_CTYPE_10BT_FDX 0x0204 +#define DC_CTYPE_10B2 0x0001 +#define DC_CTYPE_10B5 0x0002 +#define DC_CTYPE_100BT 0x0003 +#define DC_CTYPE_100BT_FDX 0x0205 +#define DC_CTYPE_100T4 0x0006 +#define DC_CTYPE_100FX 0x0007 +#define DC_CTYPE_100FX_FDX 0x0208 +#define DC_CTYPE_MII_10BT 0x0009 +#define DC_CTYPE_MII_10BT_FDX 0x020A +#define DC_CTYPE_MII_100BT 0x000D +#define DC_CTYPE_MII_100BT_FDX 0x020E +#define DC_CTYPE_MII_100T4 0x000F +#define DC_CTYPE_MII_100FX 0x0010 +#define DC_CTYPE_MII_100FX_FDX 0x0211 +#define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 +#define DC_CTYPE_PUP_AUTOSENSE 0x8800 +#define DC_CTYPE_NOMEDIA 0xFFFF + +#define DC_EBLOCK_SIA 0x0002 +#define DC_EBLOCK_MII 0x0003 +#define DC_EBLOCK_SYM 0x0004 +#define DC_EBLOCK_RESET 0x0005 +#define DC_EBLOCK_PHY_SHUTDOWN 0x0006 + +struct dc_leaf_hdr { + u_int16_t dc_mtype; + u_int8_t dc_mcnt; + u_int8_t dc_rsvd; +}; + +struct dc_eblock_hdr { + u_int8_t dc_len; + u_int8_t dc_type; +}; + +struct dc_eblock_sia { + struct dc_eblock_hdr dc_sia_hdr; + u_int8_t dc_sia_code; + u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ + u_int8_t dc_sia_gpio_ctl[2]; + u_int8_t dc_sia_gpio_dat[2]; +}; + +#define DC_SIA_CODE_10BT 0x00 +#define DC_SIA_CODE_10B2 0x01 +#define DC_SIA_CODE_10B5 0x02 +#define DC_SIA_CODE_10BT_FDX 0x04 +#define DC_SIA_CODE_EXT 0x40 + +/* + * Note that the first word in the gpr and reset + * sequences is always a control word. + */ +struct dc_eblock_mii { + struct dc_eblock_hdr dc_mii_hdr; + u_int8_t dc_mii_phynum; + u_int8_t dc_gpr_len; +/* u_int16_t dc_gpr_dat[n]; */ +/* u_int8_t dc_reset_len; */ +/* u_int16_t dc_reset_dat[n]; */ +/* There are other fields after these, but we don't + * care about them since they can be determined by looking + * at the PHY. + */ +}; + +struct dc_eblock_sym { + struct dc_eblock_hdr dc_sym_hdr; + u_int8_t dc_sym_code; + u_int8_t dc_sym_gpio_ctl[2]; + u_int8_t dc_sym_gpio_dat[2]; + u_int8_t dc_sym_cmd[2]; +}; + +#define DC_SYM_CODE_100BT 0x03 +#define DC_SYM_CODE_100BT_FDX 0x05 +#define DC_SYM_CODE_100T4 0x06 +#define DC_SYM_CODE_100FX 0x07 +#define DC_SYM_CODE_100FX_FDX 0x08 + +struct dc_eblock_reset { + struct dc_eblock_hdr dc_reset_hdr; + u_int8_t dc_reset_len; +/* u_int16_t dc_reset_dat[n]; */ +}; + +#ifdef __alpha__ +#undef vtophys +#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) +#endif diff --git a/bsps/include/libchip/if_fxpvar.h b/bsps/include/libchip/if_fxpvar.h new file mode 100644 index 0000000000..f29f52c080 --- /dev/null +++ b/bsps/include/libchip/if_fxpvar.h @@ -0,0 +1,203 @@ +/* + * Copyright (c) 1995, David Greenman + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/fxp/if_fxpvar.h,v 1.17.2.3 2001/06/08 20:36:58 jlemon Exp $ + */ + +/* + * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast + * Ethernet driver + */ + +/* + * Number of transmit control blocks. This determines the number + * of transmit buffers that can be chained in the CB list. + * This must be a power of two. + */ +#define FXP_NTXCB 128 + +/* + * Number of completed TX commands at which point an interrupt + * will be generated to garbage collect the attached buffers. + * Must be at least one less than FXP_NTXCB, and should be + * enough less so that the transmitter doesn't becomes idle + * during the buffer rundown (which would reduce performance). + */ +#define FXP_CXINT_THRESH 120 + +/* + * TxCB list index mask. This is used to do list wrap-around. + */ +#define FXP_TXCB_MASK (FXP_NTXCB - 1) + +/* + * Number of receive frame area buffers. These are large so chose + * wisely. + */ +#if 0 +#define FXP_NRFABUFS 64 +#else +#define FXP_NRFABUFS 16 +#endif +/* + * Maximum number of seconds that the receiver can be idle before we + * assume it's dead and attempt to reset it by reprogramming the + * multicast filter. This is part of a work-around for a bug in the + * NIC. See fxp_stats_update(). + */ +#define FXP_MAX_RX_IDLE 15 + +#if __FreeBSD_version < 500000 +#define FXP_LOCK(_sc) +#define FXP_UNLOCK(_sc) +#define mtx_init(a, b, c) +#define mtx_destroy(a) +struct mtx { int dummy; }; +#else +#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) +#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) +#endif + +#ifdef __alpha__ +#undef vtophys +#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va)) +#endif /* __alpha__ */ + +/* + * NOTE: Elements are ordered for optimal cacheline behavior, and NOT + * for functional grouping. + */ +struct fxp_softc { + struct arpcom arpcom; /* per-interface network data */ +#ifdef NOTUSED + struct resource *mem; /* resource descriptor for registers */ + int rtp; /* register resource type */ + int rgd; /* register descriptor in use */ + struct resource *irq; /* resource descriptor for interrupt */ +#endif + void *ih; /* interrupt handler cookie */ + struct mtx sc_mtx; +#ifdef NOTUSED /* change for RTEMS */ + bus_space_tag_t sc_st; /* bus space tag */ + bus_space_handle_t sc_sh; /* bus space handle */ +#else + unsigned char pci_bus; /* RTEMS PCI bus number */ + unsigned char pci_dev; /* RTEMS PCI slot/device number */ + unsigned char pci_fun; /* RTEMS PCI function number */ + bool pci_regs_are_io; /* RTEMS dev regs are I/O mapped */ + u_int32_t pci_regs_base; /* RTEMS i386 register base */ + rtems_id daemonTid; /* Task ID of deamon */ + rtems_vector_number irq_num; + +#endif + struct mbuf *rfa_headm; /* first mbuf in receive frame area */ + struct mbuf *rfa_tailm; /* last mbuf in receive frame area */ + struct fxp_cb_tx *cbl_first; /* first active TxCB in list */ + int tx_queued; /* # of active TxCB's */ + int need_mcsetup; /* multicast filter needs programming */ + struct fxp_cb_tx *cbl_last; /* last active TxCB in list */ + struct fxp_stats *fxp_stats; /* Pointer to interface stats */ + int rx_idle_secs; /* # of seconds RX has been idle */ + enum {fxp_timeout_stopped,fxp_timeout_running,fxp_timeout_stop_rq} + stat_ch; /* status of status updater */ + struct fxp_cb_tx *cbl_base; /* base of TxCB list */ + struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */ +#ifdef NOTUSED + struct ifmedia sc_media; /* media information */ + device_t miibus; + device_t dev; +#endif + int eeprom_size; /* size of serial EEPROM */ + int suspended; /* 0 = normal 1 = suspended (APM) */ + int cu_resume_bug; + int chip; + int flags; + u_int32_t saved_maps[5]; /* pci data */ + u_int32_t saved_biosaddr; + u_int8_t saved_intline; + u_int8_t saved_cachelnsz; + u_int8_t saved_lattimer; +}; + +#define FXP_CHIP_82557 1 /* 82557 chip type */ + +#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */ +#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */ +#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */ +#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */ +#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */ +#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */ +#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */ +#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */ + +/* Macros to ease CSR access. */ +#if 0 +#define CSR_READ_1(sc, reg) \ + bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) +#define CSR_READ_2(sc, reg) \ + bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) +#define CSR_READ_4(sc, reg) \ + bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) +#define CSR_WRITE_1(sc, reg, val) \ + bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) +#define CSR_WRITE_2(sc, reg, val) \ + bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) +#define CSR_WRITE_4(sc, reg, val) \ + bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) +#else +#define CSR_READ_1(sc, reg) fxp_csr_read_1(sc,reg) +#define CSR_READ_2(sc, reg) fxp_csr_read_2(sc,reg) +#define CSR_READ_4(sc, reg) fxp_csr_read_4(sc,reg) + +#define CSR_WRITE_1(sc, reg, val) \ + do { \ + if ((sc)->pci_regs_are_io) \ + outport_byte((sc)->pci_regs_base+(reg),val); \ + else \ + *((volatile u_int8_t*)((sc)->pci_regs_base)+(reg)) = val; \ + }while (0) + +#define CSR_WRITE_2(sc, reg, val) \ + do { \ + if ((sc)->pci_regs_are_io) \ + outport_word((sc)->pci_regs_base+(reg),val); \ + else \ + *((volatile u_int16_t*)((u_int8_t*)((sc)->pci_regs_base)+(reg))) = val; \ + }while (0) + +#define CSR_WRITE_4(sc, reg, val) \ + do { \ + if ((sc)->pci_regs_are_io) \ + outport_long((sc)->pci_regs_base+(reg),val); \ + else \ + *((volatile u_int32_t*)((u_int8_t*)((sc)->pci_regs_base)+(reg))) = val; \ + }while (0) + +#endif + +#define sc_if arpcom.ac_if + +#define FXP_UNIT(_sc) (_sc)->arpcom.ac_if.if_unit diff --git a/bsps/include/libchip/m48t08.h b/bsps/include/libchip/m48t08.h new file mode 100644 index 0000000000..3c46d384d5 --- /dev/null +++ b/bsps/include/libchip/m48t08.h @@ -0,0 +1,87 @@ +/* + * This file contains the definitions for the following real-time clocks: + * + * + Mostek M48T08 + * + Mostek M48T18 + * + Dallas Semiconductor DS1643 + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __LIBCHIP_M48T08_h +#define __LIBCHIP_M48T08_h + +/* + * Register indices + */ + +#define M48T08_CONTROL 0 +#define M48T08_SECOND 1 +#define M48T08_MINUTE 2 +#define M48T08_HOUR 3 +#define M48T08_DAY_OF_WEEK 4 +#define M48T08_DATE 5 +#define M48T08_MONTH 6 +#define M48T08_YEAR 7 + +/* + * Driver function table + */ + +extern rtc_fns m48t08_fns; + +/* + * Default register access routines + */ + +uint32_t m48t08_get_register( /* registers are at 1 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void m48t08_set_register( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +uint32_t m48t08_get_register_2( /* registers are at 2 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void m48t08_set_register_2( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +uint32_t m48t08_get_register_4( /* registers are at 4 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void m48t08_set_register_4( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +uint32_t m48t08_get_register_8( /* registers are at 8 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void m48t08_set_register_8( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +#endif +/* end of include file */ diff --git a/bsps/include/libchip/mc146818a.h b/bsps/include/libchip/mc146818a.h new file mode 100644 index 0000000000..4eb5af04d7 --- /dev/null +++ b/bsps/include/libchip/mc146818a.h @@ -0,0 +1,68 @@ +/* + * This file contains the definitions for the following real-time clocks: + * + * + Motorola MC146818A + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __LIBCHIP_MC146818A_h +#define __LIBCHIP_MC146818A_h + +/* + * Register addresses within chip + */ +#define MC146818A_SEC 0x00 /* seconds */ +#define MC146818A_SECALRM 0x01 /* seconds alarm */ +#define MC146818A_MIN 0x02 /* minutes */ +#define MC146818A_MINALRM 0x03 /* minutes alarm */ +#define MC146818A_HRS 0x04 /* hours */ +#define MC146818A_HRSALRM 0x05 /* hours alarm */ +#define MC146818A_WDAY 0x06 /* week day */ +#define MC146818A_DAY 0x07 /* day of month */ +#define MC146818A_MONTH 0x08 /* month of year */ +#define MC146818A_YEAR 0x09 /* month of year */ + +#define MC146818A_STATUSA 0x0a /* status register A */ +#define MC146818ASA_TUP 0x80 /* time update in progress */ +#define MC146818ASA_DIVIDER 0x20 /* divider for 32768 crystal */ +#define MC146818ASA_1024 0x06 /* divide to 1024 Hz */ + +#define MC146818A_STATUSB 0x0b /* status register B */ +#define MC146818ASB_DST 0x01 /* Daylight Savings Time */ +#define MC146818ASB_24HR 0x02 /* 0 = 12 hours, 1 = 24 hours */ +#define MC146818ASB_HALT 0x80 /* stop clock updates */ + +#define MC146818A_STATUSD 0x0d /* status register D */ +#define MC146818ASD_PWR 0x80 /* clock lost power */ + + +/* + * Driver function table + */ +extern rtc_fns mc146818a_fns; +bool mc146818a_probe( + int minor +); + +/* + * Default register access routines + */ +uint32_t mc146818a_get_register( + uintptr_t ulCtrlPort, + uint8_t ucRegNum +); + +void mc146818a_set_register( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint32_t ucData +); + +#endif +/* end of include file */ diff --git a/bsps/include/libchip/mc68681.h b/bsps/include/libchip/mc68681.h new file mode 100644 index 0000000000..e498a41b30 --- /dev/null +++ b/bsps/include/libchip/mc68681.h @@ -0,0 +1,122 @@ +/* + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MC68681_H_ +#define _MC68681_H_ + +#include <rtems/termiostypes.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * These are just used in the interface between this driver and + * the read/write register routines when accessing the first + * control port. + */ + +#define MC68681_STATUS 1 +#define MC68681_RX_BUFFER 3 + +#define MC68681_MODE 0 +#define MC68681_CLOCK_SELECT 1 +#define MC68681_COMMAND 2 +#define MC68681_TX_BUFFER 3 + +/* + * Data Port bit map configuration + * + * D0 : Baud Rate Set Selection + * D1 - D2 : Extended Baud Rate Setting + */ + +#define MC68681_DATA_BAUD_RATE_SET_1 0 /* ACR[7] = 0 */ +#define MC68681_DATA_BAUD_RATE_SET_2 1 /* ACR[7] = 1 */ + +#define MC68681_XBRG_IGNORED (0 << 1) +#define MC68681_XBRG_ENABLED (1 << 1) +#define MC68681_XBRG_DISABLED (2 << 1) +#define MC68681_XBRG_MASK (3 << 1) + +/* + * Custom baud rate table information + */ + +typedef unsigned char mc68681_baud_t; +typedef mc68681_baud_t mc68681_baud_table_t[RTEMS_TERMIOS_NUMBER_BAUD_RATES]; + +#define MC68681_BAUD_NOT_VALID 0xFF + +extern mc68681_baud_t + mc68681_baud_rate_table[4][RTEMS_TERMIOS_NUMBER_BAUD_RATES]; + + +/* + * Driver function table + */ + +extern const console_fns mc68681_fns; +extern const console_fns mc68681_fns_polled; + +/* + * Default register access routines + */ + +uint8_t mc68681_get_register( /* registers are at 1 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void mc68681_set_register( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint8_t ucData +); + +uint8_t mc68681_get_register_2( /* registers are at 2 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void mc68681_set_register_2( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint8_t ucData +); + +uint8_t mc68681_get_register_4( /* registers are at 4 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void mc68681_set_register_4( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint8_t ucData +); + +uint8_t mc68681_get_register_8( /* registers are at 8 byte boundaries */ + uintptr_t ulCtrlPort, /* and accessed as bytes */ + uint8_t ucRegNum +); + +void mc68681_set_register_8( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint8_t ucData +); + + +#ifdef __cplusplus +} +#endif + +#endif /* _MC68681_H_ */ diff --git a/bsps/include/libchip/ns16550.h b/bsps/include/libchip/ns16550.h new file mode 100644 index 0000000000..4f1b98bf0b --- /dev/null +++ b/bsps/include/libchip/ns16550.h @@ -0,0 +1,99 @@ +/** + * @file + * + */ + +/* + * COPYRIGHT (c) 1998 by Radstone Technology + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _NS16550_H_ +#define _NS16550_H_ + +#include <rtems/termiostypes.h> +#include <libchip/serial.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Driver function table + */ + +extern const console_fns ns16550_fns; +extern const console_fns ns16550_fns_polled; + +/* + * Flow control function tables + */ + +extern const console_flow ns16550_flow_RTSCTS; +extern const console_flow ns16550_flow_DTRCTS; + +/* + * Helpers for printk + */ +void ns16550_outch_polled(console_tbl *c, char out); +int ns16550_inch_polled(console_tbl *c); + +/* Alternative NS16550 driver using the Termios device context */ + +typedef uint8_t (*ns16550_get_reg)(uintptr_t port, uint8_t reg); + +typedef void (*ns16550_set_reg)(uintptr_t port, uint8_t reg, uint8_t value); + +typedef struct { + rtems_termios_device_context base; + ns16550_get_reg get_reg; + ns16550_set_reg set_reg; + uintptr_t port; + rtems_vector_number irq; + uint32_t clock; + uint32_t initial_baud; + bool has_fractional_divider_register; + uint8_t modem_control; + uint8_t line_control; + uint32_t baud_divisor; + size_t out_total; + size_t out_remaining; + size_t out_current; + const char *out_buf; + rtems_termios_tty *tty; +} ns16550_context; + +extern const rtems_termios_device_handler ns16550_handler_interrupt; +extern const rtems_termios_device_handler ns16550_handler_polled; +extern const rtems_termios_device_handler ns16550_handler_task; + +extern const rtems_termios_device_flow ns16550_flow_rtscts; +extern const rtems_termios_device_flow ns16550_flow_dtrcts; + +void ns16550_polled_putchar(rtems_termios_device_context *base, char out); + +int ns16550_polled_getchar(rtems_termios_device_context *base); + +bool ns16550_probe(rtems_termios_device_context *base); + +#ifdef __cplusplus +} +#endif + +#endif /* _NS16550_H_ */ diff --git a/bsps/include/libchip/ns16550_p.h b/bsps/include/libchip/ns16550_p.h new file mode 100755 index 0000000000..e3d0eba557 --- /dev/null +++ b/bsps/include/libchip/ns16550_p.h @@ -0,0 +1,142 @@ +/** + * @file + * + */ + +/* + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _NS16550_P_H_ +#define _NS16550_P_H_ + +#ifndef ASM +#include <libchip/serial.h> +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Define NS16550_STATIC to nothing while debugging so the entry points + * will show up in the symbol table. + */ + +#define NS16550_STATIC static + +#define NS16550_RECEIVE_BUFFER 0 +#define NS16550_TRANSMIT_BUFFER 0 +#define NS16550_DIVISOR_LATCH_L 0 +#define NS16550_INTERRUPT_ENABLE 1 +#define NS16550_DIVISOR_LATCH_M 1 +#define NS16550_INTERRUPT_ID 2 +#define NS16550_FIFO_CONTROL 2 +#define NS16550_LINE_CONTROL 3 +#define NS16550_MODEM_CONTROL 4 +#define NS16550_LINE_STATUS 5 +#define NS16550_MODEM_STATUS 6 +#define NS16550_SCRATCH_PAD 7 +#define NS16550_FRACTIONAL_DIVIDER 10 + +/* + * Define serial port interrupt enable register structure. + */ + +#define SP_INT_RX_ENABLE 0x01 +#define SP_INT_TX_ENABLE 0x02 +#define SP_INT_LS_ENABLE 0x04 +#define SP_INT_MS_ENABLE 0x08 + +#define NS16550_ENABLE_ALL_INTR (SP_INT_RX_ENABLE | SP_INT_TX_ENABLE) +#define NS16550_DISABLE_ALL_INTR 0x00 +#define NS16550_ENABLE_ALL_INTR_EXCEPT_TX (SP_INT_RX_ENABLE) + +/* + * Define serial port interrupt ID register structure. + */ + +#define SP_IID_0 0x01 +#define SP_IID_1 0x02 +#define SP_IID_2 0x04 +#define SP_IID_3 0x08 + +/* + * Define serial port fifo control register structure. + */ + +#define SP_FIFO_ENABLE 0x01 +#define SP_FIFO_RXRST 0x02 +#define SP_FIFO_TXRST 0x04 +#define SP_FIFO_DMA 0x08 +#define SP_FIFO_RXLEVEL 0xc0 + +#define SP_FIFO_SIZE 16 + +/* + * Define serial port line control register structure. + */ + +#define SP_LINE_SIZE 0x03 +#define SP_LINE_STOP 0x04 +#define SP_LINE_PAR 0x08 +#define SP_LINE_ODD 0x10 +#define SP_LINE_STICK 0x20 +#define SP_LINE_BREAK 0x40 +#define SP_LINE_DLAB 0x80 + +/* + * Line status register character size definitions. + */ + +#define FIVE_BITS 0x0 /* five bits per character */ +#define SIX_BITS 0x1 /* six bits per character */ +#define SEVEN_BITS 0x2 /* seven bits per character */ +#define EIGHT_BITS 0x3 /* eight bits per character */ + +/* + * Define serial port modem control register structure. + */ + +#define SP_MODEM_DTR 0x01 +#define SP_MODEM_RTS 0x02 +#define SP_MODEM_IRQ 0x08 +#define SP_MODEM_LOOP 0x10 +#define SP_MODEM_DIV4 0x80 + +/* + * Define serial port line status register structure. + */ + +#define SP_LSR_RDY 0x01 +#define SP_LSR_EOVRUN 0x02 +#define SP_LSR_EPAR 0x04 +#define SP_LSR_EFRAME 0x08 +#define SP_LSR_BREAK 0x10 +#define SP_LSR_THOLD 0x20 +#define SP_LSR_TX 0x40 +#define SP_LSR_EFIFO 0x80 + +#ifdef __cplusplus +} +#endif + +#endif /* _NS16550_P_H_ */ diff --git a/bsps/include/libchip/open_eth.h b/bsps/include/libchip/open_eth.h new file mode 100644 index 0000000000..66a5204230 --- /dev/null +++ b/bsps/include/libchip/open_eth.h @@ -0,0 +1,173 @@ +/* Opencores ethernet MAC driver */ +/* adapted from linux driver by Jiri Gaisler */ + +#ifndef _OPEN_ETH_ +#define _OPEN_ETH_ + + +/* Configuration Information */ + +typedef struct { + void *base_address; + uint32_t vector; + uint32_t txd_count; + uint32_t rxd_count; + uint32_t en100MHz; +} open_eth_configuration_t; + + +/* Ethernet buffer descriptor */ + +typedef struct _oeth_rxtxdesc { + volatile uint32_t len_status; /* Length and status */ + volatile uint32_t *addr; /* Buffer pointer */ +} oeth_rxtxdesc; + +/* Ethernet configuration registers */ + +typedef struct _oeth_regs { + volatile uint32_t moder; /* Mode Register */ + volatile uint32_t int_src; /* Interrupt Source Register */ + volatile uint32_t int_mask; /* Interrupt Mask Register */ + volatile uint32_t ipgt; /* Back to Bak Inter Packet Gap Register */ + volatile uint32_t ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */ + volatile uint32_t ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */ + volatile uint32_t packet_len; /* Packet Length Register (min. and max.) */ + volatile uint32_t collconf; /* Collision and Retry Configuration Register */ + volatile uint32_t tx_bd_num; /* Transmit Buffer Descriptor Number Register */ + volatile uint32_t ctrlmoder; /* Control Module Mode Register */ + volatile uint32_t miimoder; /* MII Mode Register */ + volatile uint32_t miicommand; /* MII Command Register */ + volatile uint32_t miiaddress; /* MII Address Register */ + volatile uint32_t miitx_data; /* MII Transmit Data Register */ + volatile uint32_t miirx_data; /* MII Receive Data Register */ + volatile uint32_t miistatus; /* MII Status Register */ + volatile uint32_t mac_addr0; /* MAC Individual Address Register 0 */ + volatile uint32_t mac_addr1; /* MAC Individual Address Register 1 */ + volatile uint32_t hash_addr0; /* Hash Register 0 */ + volatile uint32_t hash_addr1; /* Hash Register 1 */ + volatile uint32_t txctrl; /* Transmitter control register */ + uint32_t empty[235]; /* Unused space */ + oeth_rxtxdesc xd[128]; /* TX & RX descriptors */ +} oeth_regs; + +#define OETH_TOTAL_BD 128 +#define OETH_MAXBUF_LEN 0x610 + +/* Tx BD */ +#define OETH_TX_BD_READY 0x8000 /* Tx BD Ready */ +#define OETH_TX_BD_IRQ 0x4000 /* Tx BD IRQ Enable */ +#define OETH_TX_BD_WRAP 0x2000 /* Tx BD Wrap (last BD) */ +#define OETH_TX_BD_PAD 0x1000 /* Tx BD Pad Enable */ +#define OETH_TX_BD_CRC 0x0800 /* Tx BD CRC Enable */ + +#define OETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */ +#define OETH_TX_BD_RETRY 0x00F0 /* Tx BD Retry Status */ +#define OETH_TX_BD_RETLIM 0x0008 /* Tx BD Retransmission Limit Status */ +#define OETH_TX_BD_LATECOL 0x0004 /* Tx BD Late Collision Status */ +#define OETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */ +#define OETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */ +#define OETH_TX_BD_STATS (OETH_TX_BD_UNDERRUN | \ + OETH_TX_BD_RETRY | \ + OETH_TX_BD_RETLIM | \ + OETH_TX_BD_LATECOL | \ + OETH_TX_BD_DEFER | \ + OETH_TX_BD_CARRIER) + +/* Rx BD */ +#define OETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */ +#define OETH_RX_BD_IRQ 0x4000 /* Rx BD IRQ Enable */ +#define OETH_RX_BD_WRAP 0x2000 /* Rx BD Wrap (last BD) */ + +#define OETH_RX_BD_MISS 0x0080 /* Rx BD Miss Status */ +#define OETH_RX_BD_OVERRUN 0x0040 /* Rx BD Overrun Status */ +#define OETH_RX_BD_INVSIMB 0x0020 /* Rx BD Invalid Symbol Status */ +#define OETH_RX_BD_DRIBBLE 0x0010 /* Rx BD Dribble Nibble Status */ +#define OETH_RX_BD_TOOLONG 0x0008 /* Rx BD Too Long Status */ +#define OETH_RX_BD_SHORT 0x0004 /* Rx BD Too Short Frame Status */ +#define OETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */ +#define OETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */ +#define OETH_RX_BD_STATS (OETH_RX_BD_MISS | \ + OETH_RX_BD_OVERRUN | \ + OETH_RX_BD_INVSIMB | \ + OETH_RX_BD_DRIBBLE | \ + OETH_RX_BD_TOOLONG | \ + OETH_RX_BD_SHORT | \ + OETH_RX_BD_CRCERR | \ + OETH_RX_BD_LATECOL) + +/* MODER Register */ +#define OETH_MODER_RXEN 0x00000001 /* Receive Enable */ +#define OETH_MODER_TXEN 0x00000002 /* Transmit Enable */ +#define OETH_MODER_NOPRE 0x00000004 /* No Preamble */ +#define OETH_MODER_BRO 0x00000008 /* Reject Broadcast */ +#define OETH_MODER_IAM 0x00000010 /* Use Individual Hash */ +#define OETH_MODER_PRO 0x00000020 /* Promiscuous (receive all) */ +#define OETH_MODER_IFG 0x00000040 /* Min. IFG not required */ +#define OETH_MODER_LOOPBCK 0x00000080 /* Loop Back */ +#define OETH_MODER_NOBCKOF 0x00000100 /* No Backoff */ +#define OETH_MODER_EXDFREN 0x00000200 /* Excess Defer */ +#define OETH_MODER_FULLD 0x00000400 /* Full Duplex */ +#define OETH_MODER_RST 0x00000800 /* Reset MAC */ +#define OETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */ +#define OETH_MODER_CRCEN 0x00002000 /* CRC Enable */ +#define OETH_MODER_HUGEN 0x00004000 /* Huge Enable */ +#define OETH_MODER_PAD 0x00008000 /* Pad Enable */ +#define OETH_MODER_RECSMALL 0x00010000 /* Receive Small */ + +/* Interrupt Source Register */ +#define OETH_INT_TXB 0x00000001 /* Transmit Buffer IRQ */ +#define OETH_INT_TXE 0x00000002 /* Transmit Error IRQ */ +#define OETH_INT_RXF 0x00000004 /* Receive Frame IRQ */ +#define OETH_INT_RXE 0x00000008 /* Receive Error IRQ */ +#define OETH_INT_BUSY 0x00000010 /* Busy IRQ */ +#define OETH_INT_TXC 0x00000020 /* Transmit Control Frame IRQ */ +#define OETH_INT_RXC 0x00000040 /* Received Control Frame IRQ */ + +/* Interrupt Mask Register */ +#define OETH_INT_MASK_TXB 0x00000001 /* Transmit Buffer IRQ Mask */ +#define OETH_INT_MASK_TXE 0x00000002 /* Transmit Error IRQ Mask */ +#define OETH_INT_MASK_RXF 0x00000004 /* Receive Frame IRQ Mask */ +#define OETH_INT_MASK_RXE 0x00000008 /* Receive Error IRQ Mask */ +#define OETH_INT_MASK_BUSY 0x00000010 /* Busy IRQ Mask */ +#define OETH_INT_MASK_TXC 0x00000020 /* Transmit Control Frame IRQ Mask */ +#define OETH_INT_MASK_RXC 0x00000040 /* Received Control Frame IRQ Mask */ + +/* Control Module Mode Register */ +#define OETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */ +#define OETH_CTRLMODER_RXFLOW 0x00000002 /* Receive Control Flow Enable */ +#define OETH_CTRLMODER_TXFLOW 0x00000004 /* Transmit Control Flow Enable */ + +/* MII Mode Register */ +#define OETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */ +#define OETH_MIIMODER_NOPRE 0x00000100 /* No Preamble */ +#define OETH_MIIMODER_RST 0x00000200 /* MIIM Reset */ + +/* MII Command Register */ +#define OETH_MIICOMMAND_SCANSTAT 0x00000001 /* Scan Status */ +#define OETH_MIICOMMAND_RSTAT 0x00000002 /* Read Status */ +#define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */ + +/* MII Address Register */ +#define OETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */ +#define OETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */ + +/* MII Status Register */ +#define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */ +#define OETH_MIISTATUS_BUSY 0x00000002 /* MII Busy */ +#define OETH_MIISTATUS_NVALID 0x00000004 /* Data in MII Status Register is invalid */ + +/* Attatch routine */ + +int rtems_open_eth_driver_attach ( + struct rtems_bsdnet_ifconfig *config, + open_eth_configuration_t *chip +); + +/* +#ifdef CPU_U32_FIX +void ipalign(struct mbuf *m); +#endif + +*/ +#endif /* _OPEN_ETH_ */ diff --git a/bsps/include/libchip/rtc.h b/bsps/include/libchip/rtc.h new file mode 100644 index 0000000000..49dd51c2e2 --- /dev/null +++ b/bsps/include/libchip/rtc.h @@ -0,0 +1,80 @@ +/* + * This file contains the Real-Time Clock definitions. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __LIBCHIP_RTC_h +#define __LIBCHIP_RTC_h + +#include <stdbool.h> +#include <stdint.h> + +#include <rtems.h> + +/* + * Types for get and set register routines + */ + +typedef uint32_t (*getRegister_f)(uintptr_t port, uint8_t reg); +typedef void (*setRegister_f)(uintptr_t port, uint8_t reg, uint32_t value); + +typedef struct _rtc_fns { + void (*deviceInitialize)(int minor); + int (*deviceGetTime)(int minor, rtems_time_of_day *time); + int (*deviceSetTime)(int minor, const rtems_time_of_day *time); +} rtc_fns; + +typedef enum { + RTC_M48T08, /* SGS-Thomsom M48T08 or M48T18 */ + RTC_ICM7170, /* Harris ICM-7170 */ + RTC_CUSTOM, /* BSP specific driver */ + RTC_MC146818A /* Motorola MC146818A */ +} rtc_devs; + +/* + * Each field is interpreted thus: + * + * sDeviceName This is the name of the device. + * + * deviceType This indicates the chip type. + * + * pDeviceFns This is a pointer to the set of driver routines to use. + * + * pDeviceParams This contains either device specific data or a pointer to a + * device specific information table. + * + * ulCtrlPort1 This is the primary control port number for the device. + * + * ulDataPort This is the port number for the data port of the device + * + * getRegister This is the routine used to read register values. + * + * setRegister This is the routine used to write register values. + */ + +typedef struct _rtc_tbl { + const char *sDeviceName; + rtc_devs deviceType; + const rtc_fns *pDeviceFns; + bool (*deviceProbe)(int minor); + void *pDeviceParams; + uintptr_t ulCtrlPort1; + uintptr_t ulDataPort; + getRegister_f getRegister; + setRegister_f setRegister; +} rtc_tbl; + +extern rtc_tbl RTC_Table[]; +extern size_t RTC_Count; + + +extern bool rtc_probe( int minor ); + +#endif +/* end of include file */ diff --git a/bsps/include/libchip/serial.h b/bsps/include/libchip/serial.h new file mode 100644 index 0000000000..49a7bebdca --- /dev/null +++ b/bsps/include/libchip/serial.h @@ -0,0 +1,235 @@ +/** + * @file + * + * @brief The generic libchip serial driver interface + */ + + +/* + * This file contains the TTY driver table definition + * + * This driver uses the termios pseudo driver. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __LIBCHIP_SERIAL_h +#define __LIBCHIP_SERIAL_h + +#include <termios.h> + +#include <rtems.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Types for get and set register routines + */ + +/** + * @typedef getRegister_f + * + * This type function provides a hook for the bsp specific method + * that gets register data from the given port and register. + */ +typedef uint8_t (*getRegister_f)(uintptr_t port, uint8_t reg); + +/** + * @typedef setData_f + * + * This type function provides a hook for the bsp specific method + * that sets register data from the given port and register to the + * given value. + */ +typedef void (*setRegister_f)(uintptr_t port, uint8_t reg, uint8_t value); + +/** + * @typedef getData_f + * + * This type function provides a hook for the bsp specific method + * that gets data from the specified port. + */ +typedef uint8_t (*getData_f)(uintptr_t port); + +/** + * @typedef setData_f + * + * This type function provides a hook for the bsp specific method + * that writes value to the specified port. + */ +typedef void (*setData_f)(uintptr_t port, uint8_t value); + +/** + * @typedef _console_fns + * + * This type definition provides a structure of functions each + * methood provides an interfce to the serial por to do a specific + * function. + */ +typedef struct _console_fns { + bool (*deviceProbe)(int minor); + int (*deviceFirstOpen)(int major, int minor, void *arg); + int (*deviceLastClose)(int major, int minor, void *arg); + int (*deviceRead)(int minor); + ssize_t (*deviceWrite)(int minor, const char *buf, size_t len); + void (*deviceInitialize)(int minor); + void (*deviceWritePolled)(int minor, char cChar); + int (*deviceSetAttributes)(int minor, const struct termios *t); + bool deviceOutputUsesInterrupts; +} console_fns; + +/** + * @typedef _console_flow + * + * This type definition provides a structure of functions + * that provide flow control for the transmit buffer. + */ +typedef struct _console_flow { + int (*deviceStopRemoteTx)(int minor); + int (*deviceStartRemoteTx)(int minor); +} console_flow; + + +/** + * This type defination provides an enumerated type of all + * supported libchip console drivers. + */ +typedef enum { + SERIAL_MC68681, /* Motorola MC68681 or Exar 88681 */ + SERIAL_NS16550, /* National Semiconductor NS16550 */ + SERIAL_NS16550_WITH_FDR, /* National Semiconductor NS16550 + with Fractional Divider Register (FDR) */ + SERIAL_Z85C30, /* Zilog Z85C30 */ + SERIAL_CUSTOM /* BSP specific driver */ +} console_devs; + +/** + * This type defination provides an structure that is used to + * uniquely identify a specific serial port. + */ +typedef struct _console_tbl { + /** This is the name of the device. */ + const char *sDeviceName; + /** This indicates the chip type. It is especially important when + * multiple devices share the same interrupt vector and must be + * distinguished. + */ + console_devs deviceType; + /** pDeviceFns This is a pointer to the set of driver routines to use. */ + const console_fns *pDeviceFns; + /** This value is passed to the serial device driver for use. In termios + * itself the number is ignored. + */ + bool (*deviceProbe)(int minor); + /** This is a pointer to the set of flow control routines to + * use. Serial device drivers will typically supply RTSCTS + * and DTRCTS handshake routines for DCE to DCE communication, + * however for DCE to DTE communication, no such routines + * should be necessary as RTS will be driven automatically + * when the transmitter is active. + */ + const console_flow *pDeviceFlow; + /** The high water mark in the input buffer is set to the buffer + * size less ulMargin. Once this level is reached, the driver's + * flow control routine used to stop the remote transmitter will + * be called. This figure should be greater than or equal to + * the number of stages of FIFO between the transmitter and + * receiver. + * + * @note At the current time, this parameter is hard coded + * in termios and this number is ignored. + */ + uint32_t ulMargin; + /** After the high water mark specified by ulMargin has been + * reached, the driver's routine to re-start the remote + * transmitter will be called once the level in the input + * buffer has fallen by ulHysteresis bytes. + * + * @note At the current time, this parameter is hard coded in termios. + */ + uint32_t ulHysteresis; + /** This contains either device specific data or a pointer to a + * device specific structure containing additional information + * not provided in this table. + */ + void *pDeviceParams; + /** This is the primary control port number for the device. This + * may be used to specify different instances of the same device type. + */ + uint32_t ulCtrlPort1; + /** This is the secondary control port number, of use when a given + * device has more than one available channel. + */ + uint32_t ulCtrlPort2; + /** This is the port number for the data port of the device */ + uint32_t ulDataPort; + /** This is the routine used to read register values. */ + getRegister_f getRegister; + /** This is the routine used to write register values. */ + setRegister_f setRegister; + /** This is the routine used to read the data register (RX). */ + getData_f getData; + /* This is the routine used to write the data register (TX). */ + setData_f setData; + /** This is the baud rate clock speed.*/ + uint32_t ulClock; + /** This encodes the interrupt vector of the device. */ + unsigned int ulIntVector; +} console_tbl; + +/** + * This type defination provides data for the console port. + */ +typedef struct _console_data { + void *termios_data; + volatile bool bActive; + /** This field may be used for any purpose required by the driver */ + void *pDeviceContext; +} console_data; + +/** + * This is a dynamically sized set of tables containing the serial + * port information. + */ +extern console_tbl **Console_Port_Tbl; +/** + * This is the number of serial ports defined in the Console_Port_Tbl. + */ +extern unsigned long Console_Port_Count; + +/** + * The statically configured serial port information tables which + * are used to initially populate the dynamic tables. + */ +extern console_tbl Console_Configuration_Ports[]; +/** + * The number of serial ports defined in Console_Configuration_Ports + * */ +extern unsigned long Console_Configuration_Count; + +/** + * This is an array of per port information. + */ +extern console_data *Console_Port_Data; + +extern rtems_device_minor_number Console_Port_Minor; + +/** + * @brief Selects the minor number of the console device. + * + * @see Console_Port_Minor. + */ +void bsp_console_select(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/libchip/sersupp.h b/bsps/include/libchip/sersupp.h new file mode 100644 index 0000000000..6d24d25b61 --- /dev/null +++ b/bsps/include/libchip/sersupp.h @@ -0,0 +1,19 @@ +#ifndef __LIBCHIP_SERIAL_SUPPORT_h +#define __LIBCHIP_SERIAL_SUPPORT_h + +#include <rtems/termiostypes.h> + +#ifdef __cplusplus +extern "C" { +#endif + +bool libchip_serial_default_probe( + int minor +); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/include/libchip/smc91111.h b/bsps/include/libchip/smc91111.h new file mode 100644 index 0000000000..7ec83716d0 --- /dev/null +++ b/bsps/include/libchip/smc91111.h @@ -0,0 +1,558 @@ +#ifndef _SMC91111_H_ +#define _SMC91111_H_ + +#include <libchip/smc91111exp.h> +#include <rtems/bspIo.h> + +#define LAN91CXX_TCR 0x00 +#define LAN91CXX_EPH_STATUS 0x01 +#define LAN91CXX_RCR 0x02 +#define LAN91CXX_COUNTER 0x03 +#define LAN91CXX_MIR 0x04 +#define LAN91CXX_MCR 0x05 /* Other than 91C111*/ +#define LAN91CXX_RPCR 0x05 /* 91C111 only*/ +#define LAN91CXX_RESERVED_0 0x06 +#define LAN91CXX_BS 0x07 +#define LAN91CXX_CONFIG 0x08 +#define LAN91CXX_BASE_REG 0x09 +#define LAN91CXX_IA01 0x0a +#define LAN91CXX_IA23 0x0b +#define LAN91CXX_IA45 0x0c +#define LAN91CXX_GENERAL 0x0d /* 91C96 - was "RESERVED_1" for others*/ +#define LAN91CXX_CONTROL 0x0e +#define LAN91CXX_BS2 0x0f +#define LAN91CXX_MMU_COMMAND 0x10 +#define LAN91CXX_PNR 0x11 +#define LAN91CXX_FIFO_PORTS 0x12 +#define LAN91CXX_POINTER 0x13 +#define LAN91CXX_DATA_HIGH 0x14 +#define LAN91CXX_DATA 0x15 +#define LAN91CXX_INTERRUPT 0x16 +#define LAN91CXX_BS3 0x17 +#define LAN91CXX_MT01 0x18 +#define LAN91CXX_MT23 0x19 +#define LAN91CXX_MT45 0x1a +#define LAN91CXX_MT67 0x1b +#define LAN91CXX_MGMT 0x1c +#define LAN91CXX_REVISION 0x1d +#define LAN91CXX_ERCV 0x1e +#define LAN91CXX_BS4 0x1f + +#define LAN91CXX_RCR_SOFT_RST 0x8000 /* soft reset*/ +#define LAN91CXX_RCR_FILT_CAR 0x4000 /* filter carrier*/ +#define LAN91CXX_RCR_ABORT_ENB 0x2000 /* abort on collision*/ +#define LAN91CXX_RCR_STRIP_CRC 0x0200 /* strip CRC*/ +#define LAN91CXX_RCR_RXEN 0x0100 /* enable RX*/ +#define LAN91CXX_RCR_ALMUL 0x0004 /* receive all muticasts*/ +#define LAN91CXX_RCR_PRMS 0x0002 /* promiscuous*/ +#define LAN91CXX_RCR_RX_ABORT 0x0001 /* set when abort due to long frame*/ + +#define LAN91CXX_TCR_SWFDUP 0x8000 /* Switched Full Duplex mode*/ +#define LAN91CXX_TCR_ETEN_TYPE 0x4000 /* ETEN type (91C96) 0 <=> like a 91C94*/ +#define LAN91CXX_TCR_EPH_LOOP 0x2000 /* loopback mode*/ +#define LAN91CXX_TCR_STP_SQET 0x1000 /* Stop transmission on SQET error*/ +#define LAN91CXX_TCR_FDUPLX 0x0800 /* full duplex*/ +#define LAN91CXX_TCR_MON_CSN 0x0400 /* monitor carrier during tx (91C96)*/ +#define LAN91CXX_TCR_NOCRC 0x0100 /* does not append CRC to frames*/ +#define LAN91CXX_TCR_PAD_EN 0x0080 /* pads frames with 00 to min length*/ +#define LAN91CXX_TCR_FORCOL 0x0004 /* force collision*/ +#define LAN91CXX_TCR_LLOOP 0x0002 /* local loopback (91C96)*/ +#define LAN91CXX_TCR_TXENA 0x0001 /* enable*/ + +#define LAN91CXX_POINTER_RCV 0x8000 +#define LAN91CXX_POINTER_AUTO_INCR 0x4000 +#define LAN91CXX_POINTER_READ 0x2000 +#define LAN91CXX_POINTER_ETEN 0x1000 +#define LAN91CXX_POINTER_NOT_EMPTY 0x0800 + + +#define LAN91CXX_INTERRUPT_TX_IDLE_M 0x8000 /* (91C96)*/ +#define LAN91CXX_INTERRUPT_ERCV_INT_M 0x4000 +#define LAN91CXX_INTERRUPT_EPH_INT_M 0x2000 +#define LAN91CXX_INTERRUPT_RX_OVRN_INT_M 0x1000 +#define LAN91CXX_INTERRUPT_ALLOC_INT_M 0x0800 +#define LAN91CXX_INTERRUPT_TX_EMPTY_INT_M 0x0400 +#define LAN91CXX_INTERRUPT_TX_INT_M 0x0200 +#define LAN91CXX_INTERRUPT_RCV_INT_M 0x0100 +#define LAN91CXX_INTERRUPT_TX_IDLE 0x0080 /* (91C96)*/ +#define LAN91CXX_INTERRUPT_ERCV_INT 0x0040 /* also ack*/ +#define LAN91CXX_INTERRUPT_EPH_INT 0x0020 +#define LAN91CXX_INTERRUPT_RX_OVRN_INT 0x0010 /* also ack*/ +#define LAN91CXX_INTERRUPT_ALLOC_INT 0x0008 +#define LAN91CXX_INTERRUPT_TX_EMPTY_INT 0x0004 /* also ack*/ +#define LAN91CXX_INTERRUPT_TX_INT 0x0002 /* also ack*/ +#define LAN91CXX_INTERRUPT_RCV_INT 0x0001 + +#define LAN91CXX_INTERRUPT_TX_SET 0x0006 /* TX_EMPTY + TX*/ +#define LAN91CXX_INTERRUPT_TX_SET_ACK 0x0004 /* TX_EMPTY and not plain TX*/ +#define LAN91CXX_INTERRUPT_TX_FIFO_ACK 0x0002 /* TX alone*/ +#define LAN91CXX_INTERRUPT_TX_SET_M 0x0600 /* TX_EMPTY + TX*/ + +#define LAN91CXX_CONTROL_RCV_BAD 0x4000 +#define LAN91CXX_CONTROL_AUTO_RELEASE 0x0800 +#define LAN91CXX_CONTROL_LE_ENABLE 0x0080 +#define LAN91CXX_CONTROL_CR_ENABLE 0x0040 +#define LAN91CXX_CONTROL_TE_ENABLE 0x0020 + +/* These are for setting the MAC address in the 91C96 serial EEPROM*/ +#define LAN91CXX_CONTROL_EEPROM_SELECT 0x0004 +#define LAN91CXX_CONTROL_RELOAD 0x0002 +#define LAN91CXX_CONTROL_STORE 0x0001 +#define LAN91CXX_CONTROL_EEPROM_BUSY 0x0003 +#define LAN91CXX_ESA_EEPROM_OFFSET 0x0020 + +#define LAN91CXX_STATUS_TX_UNRN 0x8000 +#define LAN91CXX_STATUS_LINK_OK 0x4000 +#define LAN91CXX_STATUS_CTR_ROL 0x1000 +#define LAN91CXX_STATUS_EXC_DEF 0x0800 +#define LAN91CXX_STATUS_LOST_CARR 0x0400 +#define LAN91CXX_STATUS_LATCOL 0x0200 +#define LAN91CXX_STATUS_WAKEUP 0x0100 +#define LAN91CXX_STATUS_TX_DEFR 0x0080 +#define LAN91CXX_STATUS_LTX_BRD 0x0040 +#define LAN91CXX_STATUS_SQET 0x0020 +#define LAN91CXX_STATUS_16COL 0x0010 +#define LAN91CXX_STATUS_LTX_MULT 0x0008 +#define LAN91CXX_STATUS_MUL_COL 0x0004 +#define LAN91CXX_STATUS_SNGL_COL 0x0002 +#define LAN91CXX_STATUS_TX_SUC 0x0001 + +#define LAN91CXX_MMU_COMMAND_BUSY 0x0001 + +#define LAN91CXX_MMU_noop 0x0000 +#define LAN91CXX_MMU_alloc_for_tx 0x0020 +#define LAN91CXX_MMU_reset_mmu 0x0040 +#define LAN91CXX_MMU_rem_rx_frame 0x0060 +#define LAN91CXX_MMU_rem_tx_frame 0x0070 /* (91C96) only when TX stopped*/ +#define LAN91CXX_MMU_remrel_rx_frame 0x0080 +#define LAN91CXX_MMU_rel_packet 0x00a0 +#define LAN91CXX_MMU_enq_packet 0x00c0 +#define LAN91CXX_MMU_reset_tx_fifo 0x00e0 + +#define LAN91CXX_CONTROLBYTE_CRC 0x1000 +#define LAN91CXX_CONTROLBYTE_ODD 0x2000 +#define LAN91CXX_CONTROLBYTE_RX 0x4000 + +#define LAN91CXX_RX_STATUS_ALIGNERR 0x8000 +#define LAN91CXX_RX_STATUS_BCAST 0x4000 +#define LAN91CXX_RX_STATUS_BADCRC 0x2000 +#define LAN91CXX_RX_STATUS_ODDFRM 0x1000 +#define LAN91CXX_RX_STATUS_TOOLONG 0x0800 +#define LAN91CXX_RX_STATUS_TOOSHORT 0x0400 +#define LAN91CXX_RX_STATUS_HASHVALMASK 0x007e /* MASK*/ +#define LAN91CXX_RX_STATUS_MCAST 0x0001 +#define LAN91CXX_RX_STATUS_BAD \ + (LAN91CXX_RX_STATUS_ALIGNERR | \ + LAN91CXX_RX_STATUS_BADCRC | \ + LAN91CXX_RX_STATUS_TOOLONG | \ + LAN91CXX_RX_STATUS_TOOSHORT) + +#define LAN91CXX_RX_STATUS_IS_ODD(__cpd,__stat) ((__stat) & LAN91CXX_RX_STATUS_ODDFRM) +#define LAN91CXX_CONTROLBYTE_IS_ODD(__cpd,__val) ((__val) & LAN91CXX_CONTROLBYTE_ODD) + +/* Attribute memory registers in PCMCIA mode*/ +#define LAN91CXX_ECOR 0x8000 +#define LAN91CXX_ECOR_RESET (1<<7) +#define LAN91CXX_ECOR_LEVIRQ (1<<6) +#define LAN91CXX_ECOR_ATTWR (1<<2) +#define LAN91CXX_ECOR_ENABLE (1<<0) + +#define LAN91CXX_ECSR 0x8002 +#define LAN91CXX_ECSR_IOIS8 (1<<5) +#define LAN91CXX_ECSR_PWRDWN (1<<2) +#define LAN91CXX_ECSR_INTR (1<<1) + +/* These are for manipulating the MII interface*/ +#define LAN91CXX_MGMT_MDO 0x0001 +#define LAN91CXX_MGMT_MDI 0x0002 +#define LAN91CXX_MGMT_MCLK 0x0004 +#define LAN91CXX_MGMT_MDOE 0x0008 + +/* Internal PHY registers (91c111)*/ +#define LAN91CXX_PHY_CTRL 0 +#define LAN91CXX_PHY_STAT 1 +#define LAN91CXX_PHY_ID1 2 +#define LAN91CXX_PHY_ID2 3 +#define LAN91CXX_PHY_AUTO_AD 4 +#define LAN91CXX_PHY_AUTO_CAP 5 +#define LAN91CXX_PHY_CONFIG1 16 +#define LAN91CXX_PHY_CONFIG2 17 +#define LAN91CXX_PHY_STATUS_OUT 18 +#define LAN91CXX_PHY_MASK 19 + +/* PHY control bits*/ +#define LAN91CXX_PHY_CTRL_COLTST (1 << 7) +#define LAN91CXX_PHY_CTRL_DPLX (1 << 8) +#define LAN91CXX_PHY_CTRL_ANEG_RST (1 << 9) +#define LAN91CXX_PHY_CTRL_MII_DIS (1 << 10) +#define LAN91CXX_PHY_CTRL_PDN (1 << 11) +#define LAN91CXX_PHY_CTRL_ANEG_EN (1 << 12) +#define LAN91CXX_PHY_CTRL_SPEED (1 << 13) +#define LAN91CXX_PHY_CTRL_LPBK (1 << 14) +#define LAN91CXX_PHY_CTRL_RST (1 << 15) + +/* PHY Configuration Register 1 */ +#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ +#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ +#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ +#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ +#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ +#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ +#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ +#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ +#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ +#define PHY_CFG1_TLVL_MASK 0x003C +#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ + +/* PHY Configuration Register 2 */ +#define PHY_CFG2_REG 0x11 +#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ +#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ +#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ +#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ + +/* PHY Status Output (and Interrupt status) Register */ +#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ +#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ +#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ +#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ +#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ +#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ +#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ +#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ +#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ +#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ +#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ + +/* PHY Interrupt/Status Mask Register */ +#define PHY_MASK_REG 0x13 /* Interrupt Mask */ + +#define LAN91CXX_RPCR_LEDA_LINK (0 << 2) +#define LAN91CXX_RPCR_LEDA_TXRX (4 << 2) +#define LAN91CXX_RPCR_LEDA_RX (6 << 2) +#define LAN91CXX_RPCR_LEDA_TX (7 << 2) +#define LAN91CXX_RPCR_LEDB_LINK (0 << 5) +#define LAN91CXX_RPCR_LEDB_TXRX (4 << 5) +#define LAN91CXX_RPCR_LEDB_RX (6 << 5) +#define LAN91CXX_RPCR_LEDB_TX (7 << 5) +#define LAN91CXX_RPCR_ANEG (1 << 11) +#define LAN91CXX_RPCR_DPLX (1 << 12) +#define LAN91CXX_RPCR_SPEED (1 << 13) + +/* PHY Control Register */ +#define PHY_CNTL_REG 0x00 +#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ +#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ +#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ +#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ +#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ +#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ +#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ +#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ +#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ + +/* PHY Status Register */ +#define PHY_STAT_REG 0x01 +#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ +#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ +#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ +#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ +#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ +#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ +#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ +#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ +#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ +#define PHY_STAT_LINK 0x0004 /* 1=valid link */ +#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ +#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ +#define PHY_STAT_RESERVED 0x0780 /* Reserved bits mask. */ + +/* PHY Identifier Registers */ +#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ +#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ + +/* PHY Auto-Negotiation Advertisement Register */ +#define PHY_AD_REG 0x04 +#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ +#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ +#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ +#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ +#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ +#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ +#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ +#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ +#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ + + +static int debugflag_out = 0; + +#define dbc_printf(lvl,format, args...) do { \ + if (!debugflag_out) { \ + if (lvl & DEBUG) { \ + printk(format,##args); \ + } \ + } \ +} while(0) + +#define db64_printf(format, args...) dbc_printf(64,format,##args); +#define db16_printf(format, args...) dbc_printf(16,format,##args); +#define db9_printf(format, args...) dbc_printf(9,format,##args); +#define db4_printf(format, args...) dbc_printf(4,format,##args); +#define db2_printf(format, args...) dbc_printf(2,format,##args); +#define db1_printf(format, args...) dbc_printf(1,format,##args); +#define db_printf(format, args...) dbc_printf(0xffff,format,##args); + +#if DEBUG & 1 +#define DEBUG_FUNCTION() do { db_printf("# %s\n", __FUNCTION__); } while (0) +#else +#define DEBUG_FUNCTION() do {} while(0) +#endif + + +/* ------------------------------------------------------------------------*/ + +struct smsc_lan91cxx_stats { + unsigned int tx_good ; + unsigned int tx_max_collisions ; + unsigned int tx_late_collisions ; + unsigned int tx_underrun ; + unsigned int tx_carrier_loss ; + unsigned int tx_deferred ; + unsigned int tx_sqetesterrors ; + unsigned int tx_single_collisions; + unsigned int tx_mult_collisions ; + unsigned int tx_total_collisions ; + unsigned int rx_good ; + unsigned int rx_crc_errors ; + unsigned int rx_align_errors ; + unsigned int rx_resource_errors ; + unsigned int rx_overrun_errors ; + unsigned int rx_collisions ; + unsigned int rx_short_frames ; + unsigned int rx_too_long_frames ; + unsigned int rx_symbol_errors ; + unsigned int interrupts ; + unsigned int rx_count ; + unsigned int rx_deliver ; + unsigned int rx_resource ; + unsigned int rx_restart ; + unsigned int tx_count ; + unsigned int tx_complete ; + unsigned int tx_dropped ; +}; +#define INCR_STAT(c,n) (((c)->stats.n)++) + +struct lan91cxx_priv_data; + +typedef struct lan91cxx_priv_data { + + /* frontend */ + struct arpcom arpcom; + rtems_id rxDaemonTid; + rtems_id txDaemonTid; + + scmv91111_configuration_t config; + + /* backend */ + int rpc_cur_mode; + int autoneg_active; + int phyaddr; + unsigned int lastPhy18; + + int txbusy; /* A packet has been sent*/ + unsigned long txkey; /* Used to ack when packet sent*/ + unsigned short* base; /* Base I/O address of controller*/ + /* (as it comes out of reset)*/ + int interrupt; /* Interrupt vector used by controller*/ + unsigned char enaddr[6]; /* Controller ESA*/ + /* Function to configure the ESA - may fetch ESA from EPROM or */ + /* RedBoot config option. Use of the 'config_enaddr()' function*/ + /* is depreciated in favor of the 'provide_esa()' function and*/ + /* 'hardwired_esa' boolean*/ + void (*config_enaddr)(struct lan91cxx_priv_data* cpd); + int hardwired_esa; + int txpacket; + int rxpacket; + int within_send; + int c111_reva; /* true if this is a revA LAN91C111*/ + struct smsc_lan91cxx_stats stats; +} lan91cxx_priv_data; + +/* ------------------------------------------------------------------------*/ + +#ifdef LAN91CXX_32BIT_RX +typedef unsigned int rxd_t; +#else +typedef unsigned short rxd_t; +#endif + +typedef struct _debug_regs_pair { + int reg; char *name; struct _debug_regs_pair *bits; +} debug_regs_pair; + +static debug_regs_pair debug_regs[] = { + {LAN91CXX_TCR , "LAN91CXX_TCR" ,0}, + {LAN91CXX_EPH_STATUS , "LAN91CXX_EPH_STATUS",0}, + {LAN91CXX_RCR , "LAN91CXX_RCR" ,0}, + {LAN91CXX_COUNTER , "LAN91CXX_COUNTER" ,0}, + {LAN91CXX_MIR , "LAN91CXX_MIR" ,0}, + {LAN91CXX_MCR , "LAN91CXX_MCR" ,0}, + {LAN91CXX_RPCR , "LAN91CXX_RPCR" ,0}, + {LAN91CXX_RESERVED_0 , "LAN91CXX_RESERVED_0",0}, + {LAN91CXX_BS , "LAN91CXX_BS" ,0}, + {LAN91CXX_CONFIG , "LAN91CXX_CONFIG" ,0}, + {LAN91CXX_BASE_REG , "LAN91CXX_BASE_REG" ,0}, + {LAN91CXX_IA01 , "LAN91CXX_IA01" ,0}, + {LAN91CXX_IA23 , "LAN91CXX_IA23" ,0}, + {LAN91CXX_IA45 , "LAN91CXX_IA45" ,0}, + {LAN91CXX_GENERAL , "LAN91CXX_GENERAL" ,0}, + {LAN91CXX_CONTROL , "LAN91CXX_CONTROL" ,0}, + {LAN91CXX_BS2 , "LAN91CXX_BS2" ,0}, + {LAN91CXX_MMU_COMMAND, "LAN91CXX_MMU_COMMAND",0}, + {LAN91CXX_PNR , "LAN91CXX_PNR" ,0}, + {LAN91CXX_FIFO_PORTS , "LAN91CXX_FIFO_PORTS" ,0}, + {LAN91CXX_POINTER , "LAN91CXX_POINTER" ,0}, + {LAN91CXX_DATA_HIGH , "LAN91CXX_DATA_HIGH" ,0}, + {LAN91CXX_DATA , "LAN91CXX_DATA" ,0}, + {LAN91CXX_INTERRUPT , "LAN91CXX_INTERRUPT" ,0}, + {LAN91CXX_BS3 , "LAN91CXX_BS3" ,0}, + {LAN91CXX_MT01 , "LAN91CXX_MT01" ,0}, + {LAN91CXX_MT23 , "LAN91CXX_MT23" ,0}, + {LAN91CXX_MT45 , "LAN91CXX_MT45" ,0}, + {LAN91CXX_MT67 , "LAN91CXX_MT67" ,0}, +/*{LAN91CXX_MGMT , "LAN91CXX_MGMT" ,0}, */ + {LAN91CXX_REVISION , "LAN91CXX_REVISION" ,0}, + {LAN91CXX_ERCV , "LAN91CXX_ERCV" ,0}, + {LAN91CXX_BS4 , "LAN91CXX_BS4" ,0}, + + + + {-1,0} +}; + +static char *dbg_prefix = ""; + +#ifndef SMSC_PLATFORM_DEFINED_GET_REG +static __inline__ unsigned short +get_reg(struct lan91cxx_priv_data *cpd, int regno) +{ + unsigned short val; debug_regs_pair *dbg = debug_regs; int c; + uint32_t Irql; + + /*rtems_interrupt_disable(Irql);*/ + + HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS), CYG_CPU_TO_LE16(regno>>3)); + HAL_READ_UINT16(cpd->base+((regno&0x7)), val); + val = CYG_LE16_TO_CPU(val); + + /*rtems_interrupt_enable(Irql);*/ + +#if DEBUG & 32 + while ((c = dbg->reg) != -1) { + if (c == regno) { + db_printf("%sread reg [%d:%x] -> 0x%04x (%-20s)\n", dbg_prefix, regno>>3,(regno&0x7)*2, val, dbg->name); + break; + } + dbg++; + } +#else + db2_printf("%sread reg %d:%x -> 0x%04x\n", dbg_prefix, regno>>3,(regno&0x7)*2, val); +#endif + + return val; +} +#endif /* SMSC_PLATFORM_DEFINED_GET_REG*/ + +#ifndef SMSC_PLATFORM_DEFINED_PUT_REG +static __inline__ void +put_reg(struct lan91cxx_priv_data *cpd, int regno, unsigned short val) +{ + debug_regs_pair *dbg = debug_regs; int c; + uint32_t Irql; + +#if DEBUG & 32 + while ((c = dbg->reg) != -1) { + if (c == regno) { + db_printf("%swrite reg [%d:%x] <- 0x%04x (%-20s)\n", dbg_prefix, regno>>3, (regno&0x07)*2, val, dbg->name); + break; + } + dbg++; + } +#else + db2_printf("%swrite reg %d:%x <- 0x%04x\n", dbg_prefix, regno>>3,(regno&0x7)*2, val); +#endif + + /*rtems_interrupt_disable(Irql);*/ + + HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS), CYG_CPU_TO_LE16(regno>>3)); + HAL_WRITE_UINT16(cpd->base+((regno&0x7)), CYG_CPU_TO_LE16(val)); + + /*rtems_interrupt_enable(Irql);*/ + +} +#endif /* SMSC_PLATFORM_DEFINED_PUT_REG*/ + +#ifndef SMSC_PLATFORM_DEFINED_PUT_DATA +/* ------------------------------------------------------------------------*/ +/* Assumes bank2 has been selected*/ +static __inline__ void +put_data(struct lan91cxx_priv_data *cpd, unsigned short val) +{ + db2_printf("%s[wdata] <- 0x%04x\n", dbg_prefix, val); + + HAL_WRITE_UINT16(cpd->base+((LAN91CXX_DATA & 0x7)), val); + +} + +/* Assumes bank2 has been selected*/ +static __inline__ void +put_data8(struct lan91cxx_priv_data *cpd, unsigned char val) +{ + db2_printf("%s[bdata] <- 0x%02x\n", dbg_prefix, val); + + HAL_WRITE_UINT8(((unsigned char *)(cpd->base+((LAN91CXX_DATA & 0x7))))+1, val); + +} + +#endif /* SMSC_PLATFORM_DEFINED_PUT_DATA*/ + +#ifndef SMSC_PLATFORM_DEFINED_GET_DATA +/* Assumes bank2 has been selected*/ +static __inline__ rxd_t +get_data(struct lan91cxx_priv_data *cpd) +{ + rxd_t val; + +#ifdef LAN91CXX_32BIT_RX + HAL_READ_UINT32(cpd->base+((LAN91CXX_DATA_HIGH & 0x7)), val); +#else + HAL_READ_UINT16(cpd->base+((LAN91CXX_DATA & 0x7)), val); +#endif + + db2_printf("%s[rdata] -> 0x%08x\n", dbg_prefix, val); + return val; +} +#endif /* SMSC_PLATFORM_DEFINED_GET_DATA*/ + +/* ------------------------------------------------------------------------*/ +/* Read the bank register (this one is bank-independent)*/ +#ifndef SMSC_PLATFORM_DEFINED_GET_BANKSEL +static __inline__ unsigned short +get_banksel(struct lan91cxx_priv_data *cpd) +{ + unsigned short val; + + HAL_READ_UINT16(cpd->base+(LAN91CXX_BS), val); + val = CYG_LE16_TO_CPU(val); + db2_printf("read bank sel val 0x%04x\n", val); + return val; +} +#endif + + + + + +#endif /* _SMC_91111_H_ */ + + diff --git a/bsps/include/libchip/smc91111exp.h b/bsps/include/libchip/smc91111exp.h new file mode 100644 index 0000000000..08e086d9e7 --- /dev/null +++ b/bsps/include/libchip/smc91111exp.h @@ -0,0 +1,26 @@ +#ifndef _SMC91111_EXP_H_ +#define _SMC91111_EXP_H_ + +#include <bsp.h> + +typedef struct scmv91111_configuration { + void *baseaddr; + rtems_vector_number vector; + unsigned int pio; + unsigned int ctl_rspeed; + unsigned int ctl_rfduplx; + unsigned int ctl_autoneg; +#ifdef BSP_FEATURE_IRQ_EXTENSION + const char * info; + rtems_option options; + rtems_interrupt_handler interrupt_wrapper; + void * arg; +#endif +} scmv91111_configuration_t; + +int _rtems_smc91111_driver_attach (struct rtems_bsdnet_ifconfig *config, + scmv91111_configuration_t * scm_config); + +#endif /* _SMC_91111_EXP_H_ */ + + diff --git a/bsps/include/libchip/sonic.h b/bsps/include/libchip/sonic.h new file mode 100644 index 0000000000..fe119ff20a --- /dev/null +++ b/bsps/include/libchip/sonic.h @@ -0,0 +1,458 @@ +/* + * RTEMS NETWORK DRIVER FOR NATIONAL DP83932 `SONIC' + * SYSTEMS-ORIENTED NETWORK INTERFACE CONTROLLER + * + * REUSABLE CHIP DRIVER CONFIGURATION + * + * References: + * + * 1) DP83932C-20/25/33 MHz SONIC(TM) Systems-Oriented Network Interface + * Controller data sheet. TL/F/10492, RRD-B30M105, National Semiconductor, + * 1995. + * + * 2) Software Driver Programmer's Guide for the DP83932 SONIC(TM), + * Application Note 746, Wesley Lee and Mike Lui, TL/F/11140, + * RRD-B30M75, National Semiconductor, March, 1991. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _SONIC_DP83932_ +#define _SONIC_DP83932_ + + + /* + * Debug levels + * + */ + +#define SONIC_DEBUG_NONE 0x0000 +#define SONIC_DEBUG_ALL 0xFFFF +#define SONIC_DEBUG_PRINT_REGISTERS 0x0001 +#define SONIC_DEBUG_MEMORY 0x0002 +#define SONIC_DEBUG_MEMORY_ALLOCATE 0x0004 +#define SONIC_DEBUG_MEMORY_DESCRIPTORS 0x0008 +#define SONIC_DEBUG_FRAGMENTS 0x0008 +#define SONIC_DEBUG_CAM 0x0010 +#define SONIC_DEBUG_DESCRIPTORS 0x0020 +#define SONIC_DEBUG_ERRORS 0x0040 +#define SONIC_DEBUG_DUMP_TX_MBUFS 0x0080 +#define SONIC_DEBUG_DUMP_RX_MBUFS 0x0100 + +#define SONIC_DEBUG_DUMP_MBUFS \ + (SONIC_DEBUG_DUMP_TX_MBUFS|SONIC_DEBUG_DUMP_RX_MBUFS) + +#define SONIC_DEBUG (SONIC_DEBUG_NONE) +/* +#define SONIC_DEBUG (SONIC_DEBUG_ERRORS | SONIC_DEBUG_PRINT_REGISTERS |\ + SONIC_DEBUG_DESCRIPTORS) +*/ + +/* + ((SONIC_DEBUG_ALL) & ~(SONIC_DEBUG_PRINT_REGISTERS|SONIC_DEBUG_DUMP_MBUFS)) + ((SONIC_DEBUG_ALL) & ~(SONIC_DEBUG_DUMP_MBUFS)) +*/ + +#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS) +extern char SONIC_Reg_name[64][6]; +#endif + + +/* + * Configuration Information + */ + +typedef void (*sonic_write_register_t)( + void *base, + uint32_t regno, + uint32_t value +); + +typedef uint32_t (*sonic_read_register_t)( + void *base, + uint32_t regno +); + +typedef struct { + void *base_address; + uint32_t vector; + uint32_t dcr_value; + uint32_t dc2_value; + uint32_t tda_count; + uint32_t rda_count; + sonic_write_register_t write_register; + sonic_read_register_t read_register; +} sonic_configuration_t; + +/* + ****************************************************************** + * * + * Device Registers * + * * + ****************************************************************** + */ +#define SONIC_REG_CR 0x00 /* Command */ +#define SONIC_REG_DCR 0x01 /* Data configuration */ +#define SONIC_REG_RCR 0x02 /* Receive control */ +#define SONIC_REG_TCR 0x03 /* Transmit control */ +#define SONIC_REG_IMR 0x04 /* Interrupt mask */ +#define SONIC_REG_ISR 0x05 /* Interrupt status */ +#define SONIC_REG_UTDA 0x06 /* Upper transmit descriptor address */ +#define SONIC_REG_CTDA 0x07 /* Current transmit descriptor address */ +#define SONIC_REG_URDA 0x0D /* Upper receive descriptor address */ +#define SONIC_REG_CRDA 0x0E /* Current receive descriptor address */ +#define SONIC_REG_EOBC 0x13 /* End of buffer word count */ +#define SONIC_REG_URRA 0x14 /* Upper receive resource */ +#define SONIC_REG_RSA 0x15 /* Resource start address */ +#define SONIC_REG_REA 0x16 /* Resource end address */ +#define SONIC_REG_RRP 0x17 /* Resouce read pointer */ +#define SONIC_REG_RWP 0x18 /* Resouce write pointer */ +#define SONIC_REG_CEP 0x21 /* CAM entry pointer */ +#define SONIC_REG_CAP2 0x22 /* CAM address port 2 */ +#define SONIC_REG_CAP1 0x23 /* CAM address port 1 */ +#define SONIC_REG_CAP0 0x24 /* CAM address port 0 */ +#define SONIC_REG_CE 0x25 /* CAM enable */ +#define SONIC_REG_CDP 0x26 /* CAM descriptor pointer */ +#define SONIC_REG_CDC 0x27 /* CAM descriptor count */ +#define SONIC_REG_SR 0x28 /* Silicon revision */ +#define SONIC_REG_WT0 0x29 /* Watchdog timer 0 */ +#define SONIC_REG_WT1 0x2A /* Watchdog timer 1 */ +#define SONIC_REG_RSC 0x2B /* Receive sequence counter */ +#define SONIC_REG_CRCT 0x2C /* CRC error tally */ +#define SONIC_REG_FAET 0x2D /* FAE tally */ +#define SONIC_REG_MPT 0x2E /* Missed packet tally */ +#define SONIC_REG_MDT 0x2F /* TX Maximum Deferral */ +#define SONIC_REG_DCR2 0x3F /* Data configuration 2 */ + +/* + * Command register + */ +#define CR_LCAM 0x0200 +#define CR_RRRA 0x0100 +#define CR_RST 0x0080 +#define CR_ST 0x0020 +#define CR_STP 0x0010 +#define CR_RXEN 0x0008 +#define CR_RXDIS 0x0004 +#define CR_TXP 0x0002 +#define CR_HTX 0x0001 + +/* + * Data configuration register + */ +#define DCR_EXBUS 0x8000 +#define DCR_LBR 0x2000 +#define DCR_PO1 0x1000 +#define DCR_PO0 0x0800 +#define DCR_SBUS 0x0400 +#define DCR_USR1 0x0200 +#define DCR_USR0 0x0100 +#define DCR_WC1 0x0080 +#define DCR_WC0 0x0040 +#define DCR_DW 0x0020 +#define DCR_BMS 0x0010 +#define DCR_RFT1 0x0008 +#define DCR_RFT0 0x0004 +#define DCR_TFT1 0x0002 +#define DCR_TFT0 0x0001 + +/* data configuration register aliases */ +#define DCR_SYNC DCR_SBUS /* synchronous (memory cycle 2 clocks) */ +#define DCR_ASYNC 0 /* asynchronous (memory cycle 3 clocks) */ + +#define DCR_WAIT0 0 /* 0 wait states added */ +#define DCR_WAIT1 DCR_WC0 /* 1 wait state added */ +#define DCR_WAIT2 DCR_WC1 /* 2 wait states added */ +#define DCR_WAIT3 (DCR_WC1|DCR_WC0) /* 3 wait states added */ + +#define DCR_DW16 0 /* use 16-bit DMA accesses */ +#define DCR_DW32 DCR_DW /* use 32-bit DMA accesses */ + +#define DCR_DMAEF 0 /* DMA until TX/RX FIFO has emptied/filled */ +#define DCR_DMABLOCK DCR_BMS /* DMA until RX/TX threshold crossed */ + +#define DCR_RFT4 0 /* receive threshold 4 bytes */ +#define DCR_RFT8 DCR_RFT0 /* receive threshold 8 bytes */ +#define DCR_RFT16 DCR_RFT1 /* receive threshold 16 bytes */ +#define DCR_RFT24 (DCR_RFT1|DCR_RFT0) /* receive threshold 24 bytes */ + +#define DCR_TFT8 0 /* transmit threshold 8 bytes */ +#define DCR_TFT16 DCR_TFT0 /* transmit threshold 16 bytes */ +#define DCR_TFT24 DCR_TFT1 /* transmit threshold 24 bytes */ +#define DCR_TFT28 (DCR_TFT1|DCR_TFT0) /* transmit threshold 28 bytes */ + +/* + * Receive control register + */ +#define RCR_ERR 0x8000 +#define RCR_RNT 0x4000 +#define RCR_BRD 0x2000 +#define RCR_PRO 0x1000 +#define RCR_AMC 0x0800 +#define RCR_LB1 0x0400 +#define RCR_LB0 0x0200 +#define RCR_MC 0x0100 +#define RCR_BC 0x0080 +#define RCR_LPKT 0x0040 +#define RCR_CRS 0x0020 +#define RCR_COL 0x0010 +#define RCR_CRCR 0x0008 +#define RCR_FAER 0x0004 +#define RCR_LBK 0x0002 +#define RCR_PRX 0x0001 + +/* + * Transmit control register + */ +#define TCR_PINT 0x8000 +#define TCR_POWC 0x4000 +#define TCR_CRCI 0x2000 +#define TCR_EXDIS 0x1000 +#define TCR_EXD 0x0400 +#define TCR_DEF 0x0200 +#define TCR_NCRS 0x0100 +#define TCR_CRSL 0x0080 +#define TCR_EXC 0x0040 +#define TCR_OWC 0x0020 +#define TCR_PMB 0x0008 +#define TCR_FU 0x0004 +#define TCR_BCM 0x0002 +#define TCR_PTX 0x0001 + +/* + * Interrupt mask register + */ +#define IMR_BREN 0x4000 +#define IMR_HBLEN 0x2000 +#define IMR_LCDEN 0x1000 +#define IMR_PINTEN 0x0800 +#define IMR_PRXEN 0x0400 +#define IMR_PTXEN 0x0200 +#define IMR_TXEREN 0x0100 +#define IMR_TCEN 0x0080 +#define IMR_RDEEN 0x0040 +#define IMR_RBEEN 0x0020 +#define IMR_RBAEEN 0x0010 +#define IMR_CRCEN 0x0008 +#define IMR_FAEEN 0x0004 +#define IMR_MPEN 0x0002 +#define IMR_RFOEN 0x0001 + +/* + * Interrupt status register + */ +#define ISR_BR 0x4000 +#define ISR_HBL 0x2000 +#define ISR_LCD 0x1000 +#define ISR_PINT 0x0800 +#define ISR_PKTRX 0x0400 +#define ISR_TXDN 0x0200 +#define ISR_TXER 0x0100 +#define ISR_TC 0x0080 +#define ISR_RDE 0x0040 +#define ISR_RBE 0x0020 +#define ISR_RBAE 0x0010 +#define ISR_CRC 0x0008 +#define ISR_FAE 0x0004 +#define ISR_MP 0x0002 +#define ISR_RFO 0x0001 + +/* + * Data configuration register 2 + */ +#define DCR2_EXPO3 0x8000 +#define DCR2_EXPO2 0x4000 +#define DCR2_EXPO1 0x2000 +#define DCR2_EXPO0 0x1000 +#define DCR2_HBDIS 0x0800 +#define DCR2_PH 0x0010 +#define DCR2_PCM 0x0004 +#define DCR2_PCNM 0x0002 +#define DCR2_RJCM 0x0001 + +/* + * Known values for the Silicon Revision Register. + * Note that DP83934 has revision 5 and seems to work. + */ + +#define SONIC_REVISION_B 4 +#define SONIC_REVISION_DP83934 5 +#define SONIC_REVISION_C 6 + +/* + ****************************************************************** + * * + * Transmit Buffer Management * + * * + ****************************************************************** + */ + +/* + * Transmit descriptor area entry. + * There is one transmit descriptor for each packet to be transmitted. + * Statically reserve space for up to MAXIMUM_FRAGS_PER_PACKET fragments + * per descriptor. + */ +#define MAXIMUM_FRAGS_PER_DESCRIPTOR 6 +struct TransmitDescriptor { + uint32_t status; + uint32_t pkt_config; + uint32_t pkt_size; + uint32_t frag_count; + + /* + * Packet fragment pointers + */ + struct TransmitDescriptorFragLink { + uint32_t frag_lsw; /* LSW of fragment address */ +#define frag_link frag_lsw + uint32_t frag_msw; /* MSW of fragment address */ + uint32_t frag_size; + } frag[MAXIMUM_FRAGS_PER_DESCRIPTOR]; + + /* + * Space for link if all fragment pointers are used. + */ + uint32_t link_pad; + + /* + * Extra RTEMS stuff + */ + struct TransmitDescriptor *next; /* Circularly-linked list */ + struct mbuf *mbufp; /* First mbuf in packet */ + volatile uint32_t *linkp; /* Pointer to un[xxx].link */ +}; +typedef struct TransmitDescriptor TransmitDescriptor_t; +typedef volatile TransmitDescriptor_t *TransmitDescriptorPointer_t; + +/* + * Transmit Configuration. + * For standard Ethernet transmission, all bits in the transmit + * configuration field are set to 0. + */ +#define TDA_CONFIG_PINT 0x8000 +#define TDA_CONFIG_POWC 0x4000 +#define TDA_CONFIG_CRCI 0x2000 +#define TDA_CONFIG_EXDIS 0x1000 + +/* + * Transmit status + */ +#define TDA_STATUS_COLLISION_MASK 0xF800 +#define TDA_STATUS_COLLISION_SHIFT 11 +#define TDA_STATUS_EXD 0x0400 +#define TDA_STATUS_DEF 0x0200 +#define TDA_STATUS_NCRS 0x0100 +#define TDA_STATUS_CRSL 0x0080 +#define TDA_STATUS_EXC 0x0040 +#define TDA_STATUS_OWC 0x0020 +#define TDA_STATUS_PMB 0x0008 +#define TDA_STATUS_FU 0x0004 +#define TDA_STATUS_BCM 0x0002 +#define TDA_STATUS_PTX 0x0001 + +#define TDA_LINK_EOL 0x0001 +#define TDA_LINK_EOL_MASK 0xFFFE + + + +/* + ****************************************************************** + * * + * Receive Buffer Management * + * * + ****************************************************************** + */ + +/* + * Receive resource area entry. + * There is one receive resource entry for each receive buffer area (RBA). + * This driver allows only one packet per receive buffer area, so one + * receive resource entry corresponds to one correctly-received packet. + */ +struct ReceiveResource { + uint32_t buff_ptr_lsw; /* LSW of RBA address */ + uint32_t buff_ptr_msw; /* MSW of RBA address */ + uint32_t buff_wc_lsw; /* LSW of RBA size (16-bit words) */ + uint32_t buff_wc_msw; /* MSW of RBA size (16-bit words) */ +}; +typedef struct ReceiveResource ReceiveResource_t; +typedef volatile ReceiveResource_t *ReceiveResourcePointer_t; + +/* + * Receive descriptor area entry. + * There is one receive descriptor for each packet received. + */ +struct ReceiveDescriptor { + uint32_t status; + uint32_t byte_count; + uint32_t pkt_lsw; /* LSW of packet address */ + uint32_t pkt_msw; /* MSW of packet address */ + uint32_t seq_no; + uint32_t link; + uint32_t in_use; + + /* + * Extra RTEMS stuff + */ + volatile struct ReceiveDescriptor *next; /* Circularly-linked list */ + struct mbuf *mbufp; /* First mbuf in packet */ +}; +typedef struct ReceiveDescriptor ReceiveDescriptor_t; +typedef volatile ReceiveDescriptor_t *ReceiveDescriptorPointer_t; + +typedef struct { + uint32_t cep; /* CAM Entry Pointer */ + uint32_t cap0; /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */ + uint32_t cap1; /* CAM Address Port 1 xx-xx-YY-YY-xxxx */ + uint32_t cap2; /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */ + uint32_t ce; +} CamDescriptor_t; + +typedef volatile CamDescriptor_t *CamDescriptorPointer_t; + +/* + * Receive status + */ +#define RDA_STATUS_ERR 0x8800 +#define RDA_STATUS_RNT 0x4000 +#define RDA_STATUS_BRD 0x2000 +#define RDA_STATUS_PRO 0x1000 +#define RDA_STATUS_AMC 0x0800 +#define RDA_STATUS_LB1 0x0400 +#define RDA_STATUS_LB0 0x0200 +#define RDA_STATUS_MC 0x0100 +#define RDA_STATUS_BC 0x0080 +#define RDA_STATUS_LPKT 0x0040 +#define RDA_STATUS_CRS 0x0020 +#define RDA_STATUS_COL 0x0010 +#define RDA_STATUS_CRCR 0x0008 +#define RDA_STATUS_FAER 0x0004 +#define RDA_STATUS_LBK 0x0002 +#define RDA_STATUS_PRX 0x0001 + +#define RDA_LINK_EOL 0x0001 +#define RDA_LINK_EOL_MASK 0xFFFE +#define RDA_IN_USE 0x0000 /* SONIC has finished with the packet */ + /* and the driver can process it */ +#define RDA_FREE 0xFFFF /* SONIC can use it */ + +/* + * Attach routine + */ + +int rtems_sonic_driver_attach ( + struct rtems_bsdnet_ifconfig *config, + sonic_configuration_t *chip +); + +#ifdef CPU_U32_FIX +void ipalign(struct mbuf *m); +#endif + +#endif /* _SONIC_DP83932_ */ diff --git a/bsps/include/libchip/spi-flash-m25p40.h b/bsps/include/libchip/spi-flash-m25p40.h new file mode 100644 index 0000000000..2009b6fed3 --- /dev/null +++ b/bsps/include/libchip/spi-flash-m25p40.h @@ -0,0 +1,44 @@ +/*===============================================================*\ +| Project: SPI driver for M25P40 like spi flash device | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +\*===============================================================*/ +/* + * FIXME: currently, this driver only supports read/write accesses + * erase accesses are to be completed + */ + + +#ifndef _LIBCHIP_SPI_FLASH_M25P40_H +#define _LIBCHIP_SPI_FLASH_M25P40_H + +#include <libchip/spi-memdrv.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * pass one of these descriptor pointers to rtems_libi2c_register_drv + */ +extern rtems_libi2c_drv_t *spi_flash_m25p40_rw_driver_descriptor; + +extern rtems_libi2c_drv_t *spi_flash_m25p40_ro_driver_descriptor; + +#ifdef __cplusplus +} +#endif + +#endif /* _LIBCHIP_SPI_FLASH_M25P40_H */ diff --git a/bsps/include/libchip/spi-fram-fm25l256.h b/bsps/include/libchip/spi-fram-fm25l256.h new file mode 100644 index 0000000000..a2167a3074 --- /dev/null +++ b/bsps/include/libchip/spi-fram-fm25l256.h @@ -0,0 +1,44 @@ +/*===============================================================*\ +| Project: SPI driver for FM25L256 like spi fram device | ++-----------------------------------------------------------------+ +| Copyright (c) 2008 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +\*===============================================================*/ +/* + * FIXME: currently, this driver only supports read/write accesses + * erase accesses are to be completed + */ + + +#ifndef _LIBCHIP_SPI_FRAM_FM25L256_H +#define _LIBCHIP_SPI_FRAM_FM25L256_H + +#include <libchip/spi-memdrv.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * pass one of these descriptor pointers to rtems_libi2c_register_drv + */ +extern rtems_libi2c_drv_t *spi_fram_fm25l256_rw_driver_descriptor; + +extern rtems_libi2c_drv_t *spi_fram_fm25l256_ro_driver_descriptor; + +#ifdef __cplusplus +} +#endif + +#endif /* _LIBCHIP_SPI_FRAM_FM25L256_H */ diff --git a/bsps/include/libchip/spi-memdrv.h b/bsps/include/libchip/spi-memdrv.h new file mode 100644 index 0000000000..ed4aa55b6f --- /dev/null +++ b/bsps/include/libchip/spi-memdrv.h @@ -0,0 +1,90 @@ +/*===============================================================*\ +| Project: SPI driver for spi memory devices | ++-----------------------------------------------------------------+ +| Copyright (c) 2008 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +\*===============================================================*/ + + +#ifndef _LIBCHIP_SPI_MEMDRV_H +#define _LIBCHIP_SPI_MEMDRV_H + +#include <rtems/libi2c.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code spi_memdrv_write +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| write a block of data to memory | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, /* major device number */ + rtems_device_major_number minor, /* minor device number */ + void *arg /* ptr to write argument struct */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code spi_memdrv_read +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| read a block of data from memory | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, /* major device number */ + rtems_device_major_number minor, /* minor device number */ + void *arg /* ptr to read argument struct */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ + + typedef struct { + uint32_t baudrate; /* tfr rate, bits per second */ + bool erase_before_program; + uint32_t empty_state; /* value of erased cells */ + uint32_t page_size; /* programming page size in byte */ + uint32_t sector_size; /* erase sector size in byte */ + uint32_t mem_size; /* total capacity in byte */ + } spi_memdrv_param_t; + + typedef struct { + rtems_libi2c_drv_t libi2c_drv_entry; /* general i2c/spi params */ + spi_memdrv_param_t spi_memdrv_param; /* private parameters */ + } spi_memdrv_t; + + extern rtems_driver_address_table spi_memdrv_rw_ops; + extern rtems_driver_address_table spi_memdrv_ro_ops; + +#ifdef __cplusplus +} +#endif + +#endif /* _LIBCHIP_SPI_MEMDRV_H */ diff --git a/bsps/include/libchip/spi-sd-card.h b/bsps/include/libchip/spi-sd-card.h new file mode 100644 index 0000000000..77e905a155 --- /dev/null +++ b/bsps/include/libchip/spi-sd-card.h @@ -0,0 +1,86 @@ +/** + * @file + * + * @brief SD Card LibI2C driver. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBI2C_SD_CARD_H +#define LIBI2C_SD_CARD_H + +#include <stdint.h> +#include <stdbool.h> + +#include <rtems/libi2c.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define SD_CARD_IDLE_TOKEN 0xff + +/** + * 1 idle token before command + * 6 bytes for the command + * 1 to 8 bytes for response start (N_CR) + * 1 to 2 bytes for response + * 1 idle token after command (minimum N_RC) + */ +#define SD_CARD_COMMAND_SIZE 18 + +#define SD_CARD_TRANSFER_MODE_DEFAULT { .baudrate = 400000, .bits_per_char = 8, .lsb_first = FALSE, .clock_inv = FALSE, .clock_phs = FALSE, .idle_char = SD_CARD_IDLE_TOKEN } + +#define SD_CARD_COMMAND_DEFAULT { \ + SD_CARD_IDLE_TOKEN, \ + 0x40, 0, 0, 0, 0, 0x95, \ + SD_CARD_IDLE_TOKEN, SD_CARD_IDLE_TOKEN, \ + SD_CARD_IDLE_TOKEN, SD_CARD_IDLE_TOKEN, \ + SD_CARD_IDLE_TOKEN, SD_CARD_IDLE_TOKEN, \ + SD_CARD_IDLE_TOKEN, SD_CARD_IDLE_TOKEN, \ + SD_CARD_IDLE_TOKEN, SD_CARD_IDLE_TOKEN, \ + SD_CARD_IDLE_TOKEN \ +} + +/* Default speed = 400kbps, default timeout = 100ms, n_ac_max is in bytes */ +#define SD_CARD_N_AC_MAX_DEFAULT 5000 + +typedef struct { + const char *device_name; + rtems_device_minor_number bus; + rtems_libi2c_tfr_mode_t transfer_mode; + uint8_t command [SD_CARD_COMMAND_SIZE]; + uint8_t response [SD_CARD_COMMAND_SIZE]; + int response_index; + uint32_t n_ac_max; + uint32_t block_number; + uint32_t block_size; + uint32_t block_size_shift; + bool busy; + bool verbose; + bool schedule_if_busy; + uint32_t retries; +} sd_card_driver_entry; + +extern sd_card_driver_entry sd_card_driver_table []; + +extern size_t sd_card_driver_table_size; + +rtems_status_code sd_card_register( void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBI2C_SD_CARD_H */ diff --git a/bsps/include/libchip/wd80x3.h b/bsps/include/libchip/wd80x3.h new file mode 100644 index 0000000000..b4aa12e735 --- /dev/null +++ b/bsps/include/libchip/wd80x3.h @@ -0,0 +1,139 @@ +/** + * @file + * + * @ingroup i386_pc386 + * + * @brief DP8390 Ethernet controller definitions. + */ + +/* + * Information about the DP8390 Ethernet controller. + */ + +#ifndef __BSP_WD80x3_h +#define __BSP_WD80x3_h + +/* Register descriptions */ +/* Controller DP8390. */ + +#define DATAPORT 0x10 /* Port Window. */ +#define RESET 0x1f /* Issue a read for reset */ +#define W83CREG 0x00 /* I/O port definition */ +#define ADDROM 0x08 + +/* page 0 read or read/write registers */ + +#define CMDR 0x00+RO +#define CLDA0 0x01+RO /* current local dma addr 0 for read */ +#define CLDA1 0x02+RO /* current local dma addr 1 for read */ +#define BNRY 0x03+RO /* boundary reg for rd and wr */ +#define TSR 0x04+RO /* tx status reg for rd */ +#define NCR 0x05+RO /* number of collision reg for rd */ +#define FIFO 0x06+RO /* FIFO for rd */ +#define ISR 0x07+RO /* interrupt status reg for rd and wr */ +#define CRDA0 0x08+RO /* current remote dma address 0 for rd */ +#define CRDA1 0x09+RO /* current remote dma address 1 for rd */ +#define RSR 0x0C+RO /* rx status reg for rd */ +#define CNTR0 0x0D+RO /* tally cnt 0 for frm alg err for rd */ +#define CNTR1 RO+0x0E /* tally cnt 1 for crc err for rd */ +#define CNTR2 0x0F+RO /* tally cnt 2 for missed pkt for rd */ + +/* page 0 write registers */ + +#define PSTART 0x01+RO /* page start register */ +#define PSTOP 0x02+RO /* page stop register */ +#define TPSR 0x04+RO /* tx start page start reg */ +#define TBCR0 0x05+RO /* tx byte count 0 reg */ +#define TBCR1 0x06+RO /* tx byte count 1 reg */ +#define RSAR0 0x08+RO /* remote start address reg 0 */ +#define RSAR1 0x09+RO /* remote start address reg 1 */ +#define RBCR0 0x0A+RO /* remote byte count reg 0 */ +#define RBCR1 0x0B+RO /* remote byte count reg 1 */ +#define RCR 0x0C+RO /* rx configuration reg */ +#define TCR 0x0D+RO /* tx configuration reg */ +#define DCR RO+0x0E /* data configuration reg */ +#define IMR 0x0F+RO /* interrupt mask reg */ + +/* page 1 registers */ + +#define PAR 0x01+RO /* physical addr reg base for rd and wr */ +#define CURR 0x07+RO /* current page reg for rd and wr */ +#define MAR 0x08+RO /* multicast addr reg base fro rd and WR */ +#define MARsize 8 /* size of multicast addr space */ + +/*-----W83CREG command bits-----*/ +#define MSK_RESET 0x80 /* W83CREG masks */ +#define MSK_ENASH 0x40 +#define MSK_DECOD 0x3F /* memory decode bits, corresponding */ + /* to SA 18-13. SA 19 assumed to be 1 */ + +/*-----CMDR command bits-----*/ +#define MSK_STP 0x01 /* stop the chip */ +#define MSK_STA 0x02 /* start the chip */ +#define MSK_TXP 0x04 /* initial txing of a frm */ +#define MSK_RRE 0x08 /* remote read */ +#define MSK_RWR 0x10 /* remote write */ +#define MSK_RD2 0x20 /* no DMA used */ +#define MSK_PG0 0x00 /* select register page 0 */ +#define MSK_PG1 0x40 /* select register page 1 */ +#define MSK_PG2 0x80 /* select register page 2 */ + +/*-----ISR and TSR status bits-----*/ +#define MSK_PRX 0x01 /* rx with no error */ +#define MSK_PTX 0x02 /* tx with no error */ +#define MSK_RXE 0x04 /* rx with error */ +#define MSK_TXE 0x08 /* tx with error */ +#define MSK_OVW 0x10 /* overwrite warning */ +#define MSK_CNT 0x20 /* MSB of one of the tally counters is set */ +#define MSK_RDC 0x40 /* remote dma completed */ +#define MSK_RST 0x80 /* reset state indicator */ + +/*-----DCR command bits-----*/ +#define MSK_WTS 0x01 /* word transfer mode selection */ +#define MSK_BOS 0x02 /* byte order selection */ +#define MSK_LAS 0x04 /* long addr selection */ +#define MSK_BMS 0x08 /* burst mode selection */ +#define MSK_ARM 0x10 /* autoinitialize remote */ +#define MSK_FT00 0x00 /* burst lrngth selection */ +#define MSK_FT01 0x20 /* burst lrngth selection */ +#define MSK_FT10 0x40 /* burst lrngth selection */ +#define MSK_FT11 0x60 /* burst lrngth selection */ + +/*-----RCR command bits-----*/ +#define MSK_SEP 0x01 /* save error pkts */ +#define MSK_AR 0x02 /* accept runt pkt */ +#define MSK_AB 0x04 /* 8390 RCR */ +#define MSK_AM 0x08 /* accept multicast */ +#define MSK_PRO 0x10 /* accept all pkt with physical adr */ +#define MSK_MON 0x20 /* monitor mode */ + +/*-----TCR command bits-----*/ +#define MSK_CRC 0x01 /* inhibit CRC, do not append crc */ +#define MSK_LOOP 0x02 /* set loopback mode */ +#define MSK_BCST 0x04 /* Accept broadcasts */ +#define MSK_LB01 0x06 /* encoded loopback control */ +#define MSK_ATD 0x08 /* auto tx disable */ +#define MSK_OFST 0x10 /* collision offset enable */ + +/*-----receive status bits-----*/ +#define SMK_PRX 0x01 /* rx without error */ +#define SMK_CRC 0x02 /* CRC error */ +#define SMK_FAE 0x04 /* frame alignment error */ +#define SMK_FO 0x08 /* FIFO overrun */ +#define SMK_MPA 0x10 /* missed pkt */ +#define SMK_PHY 0x20 /* physical/multicase address */ +#define SMK_DIS 0x40 /* receiver disable. set in monitor mode */ +#define SMK_DEF 0x80 /* deferring */ + +/*-----transmit status bits-----*/ +#define SMK_PTX 0x01 /* tx without error */ +#define SMK_DFR 0x02 /* non deferred tx */ +#define SMK_COL 0x04 /* tx collided */ +#define SMK_ABT 0x08 /* tx abort because of excessive collisions */ +#define SMK_CRS 0x10 /* carrier sense lost */ +#define SMK_FU 0x20 /* FIFO underrun */ +#define SMK_CDH 0x40 /* collision detect heartbeat */ +#define SMK_OWC 0x80 /* out of window collision */ + +#endif +/* end of include */ diff --git a/bsps/include/libchip/z85c30.h b/bsps/include/libchip/z85c30.h new file mode 100644 index 0000000000..656d50ea1c --- /dev/null +++ b/bsps/include/libchip/z85c30.h @@ -0,0 +1,83 @@ +/** + * @file + * + * This include file contains all console driver definitions for the + * Zilog z85c30. + */ + +/* + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __Z85C30_H +#define __Z85C30_H + +#include <stdint.h> + +#include <libchip/serial.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Driver function table + */ + +extern const console_fns z85c30_fns; +extern const console_fns z85c30_fns_polled; + +/* + * Flow control function tables + */ + +extern const console_flow z85c30_flow_RTSCTS; +extern const console_flow z85c30_flow_DTRCTS; + +/* + * Default register access routines + */ + +uint8_t z85c30_get_register( /* registers are byte-wide */ + uintptr_t ulCtrlPort, + uint8_t ucRegNum +); + +void z85c30_set_register( + uintptr_t ulCtrlPort, + uint8_t ucRegNum, + uint8_t ucData +); + +uint8_t z85c30_get_data( + uint32_t ulDataPort +); + +void z85c30_set_data( + uint32_t ulDataPort, + uint8_t ucData +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/mpci.h b/bsps/include/mpci.h new file mode 100644 index 0000000000..cc7c5826de --- /dev/null +++ b/bsps/include/mpci.h @@ -0,0 +1,56 @@ +/* mpci.h + * + * This include file contains all the renaming necessary to + * have an application use the Shared Memory Driver as its + * sole mechanism for MPCI. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __SHM_MPCI_h +#define __SHM_MPCI_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include <shm_driver.h> + +#define MPCI_Initialization( _configuration ) \ + Shm_Initialization( _configuration ) + +#define MPCI_Get_packet( _the_packet ) \ + Shm_Get_packet( _the_packet ) + +#define MPCI_Return_packet( _the_packet ) \ + Shm_Return_packet( _the_packet ) + +#define MPCI_Receive_packet( _the_packet ) \ + Shm_Receive_packet( _the_packet ) + +#define MPCI_Send_packet( _destination, _the_packet ) \ + Shm_Send_packet( _destination, _the_packet ) + +/* Unnecessary... mapped in shm_driver.h +#define MPCI_Fatal( _the_error ) \ + Shm_Fatal( _the_error ) +*/ + +#define MPCI_Enable_statistics() + +#define MPCI_Print_statistics() \ + Shm_Print_statistics() + +/* no need to rename the MPCI_Table either */ + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/include/rtems/umon.h b/bsps/include/rtems/umon.h new file mode 100644 index 0000000000..d25a7818dd --- /dev/null +++ b/bsps/include/rtems/umon.h @@ -0,0 +1,68 @@ +/* + * umon.h - RTEMS specific interface to MicroMonitor. + * + * COPYRIGHT (c) 1989-2009. + * On-Line Applications Research Corporation (OAR). + * + * Modified by Fernando Nicodemos <fgnicodemos@terra.com.br> + * from NCB - Sistemas Embarcados Ltda. (Brazil) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. +*/ + +#ifndef __rtems_umon_h +#define __rtems_umon_h + +#include <umon/monlib.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Connect RTEMS Application to MicroMonitor + * + * RTEMS uMonitor wrapper for monConnect(). This will deal with the + * getting MONCOMPTR as well as providing the locking routines. + */ +void rtems_umon_connect(void); + +/** + * @brief Obtain BSP specific pointer to MicroMonitor + * + * BSP specific routine to help when calling monConnect(). This + * returns the value known to uMon as MONCOMPTR. + * + * @return This method returns the address of the base area of MicroMonitor. + */ +void *rtems_bsp_get_umon_monptr(void); + +/** + * @brief Initialize the TFS-RTEMS file system + * + * This method initializes and mounts the TFS-RTEMS file system. + * + * @param[in] path is the mount point + * + * @return This method returns 0 on success. + */ +int rtems_initialize_tfs_filesystem( + const char *path +); + +/** + * @brief Read from MicroMonitor Port + * + * This method reads a character from the MicroMonitor console. + * + * @return This method returns a character. + */ +int umoncons_poll_read(int minor); + +#ifdef __cplusplus +} +#endif + +#endif /* __rtems_umon_h */ diff --git a/bsps/include/rtems/zilog/z8036.h b/bsps/include/rtems/zilog/z8036.h new file mode 100644 index 0000000000..fea1493905 --- /dev/null +++ b/bsps/include/rtems/zilog/z8036.h @@ -0,0 +1,106 @@ +/** + * @file + * + * @brief Zilog Z8036 Counter/Timer/IO Chip + * + * This include file defines information related to a Zilog Z8036 + * Counter/Timer/IO Chip. It is a memory mapped part. + * + * @note This file shares as much as possible with the include file + * for the Z8536 via z8x36.h. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_ZILOG_Z8036_H +#define _RTEMS_ZILOG_Z8036_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* macros */ + +#define Z8036( ptr ) ((volatile struct z8036_map *)(ptr)) + +#define Z8x36_STATE0 ( z8036 ) \ + { /*char *garbage = *(Z8036(z8036))->???; */ } + + +#define Z8x36_WRITE( z8036, reg, data ) \ + (Z8036(z8036))->reg = (data) + + +#define Z8x36_READ( z8036, reg, data ) \ + (Z8036(z8036))->reg = (data) + +/* structures */ + +struct z8036_map { +/* MAIN CONTROL REGISTERS (0x00-0x07) */ + uint8_t MASTER_INTR; /* Master Interrupt Ctl Reg */ + uint8_t MASTER_CFG; /* Master Configuration Ctl Reg */ + uint8_t PORTA_VECTOR; /* Port A - Interrupt Vector */ + uint8_t PORTB_VECTOR; /* Port B - Interrupt Vector */ + uint8_t CNT_TMR_VECTOR; /* Counter/Timer Interrupt Vector */ + uint8_t PORTC_DATA_POLARITY; /* Port C - Data Path Polarity */ + uint8_t PORTC_DIRECTION; /* Port C - Data Direction */ + uint8_t PORTC_SPECIAL_IO_CTL; /* Port C - Special IO Control */ +/* MOST OFTEN ACCESSED REGISTERS (0x08 - 0x0f) */ + uint8_t PORTA_CMD_STATUS; /* Port A - Command Status Reg */ + uint8_t PORTB_CMD_STATUS; /* Port B - Command Status Reg */ + uint8_t CT1_CMD_STATUS; /* Ctr/Timer 1 - Command Status Reg */ + uint8_t CT2_CMD_STATUS; /* Ctr/Timer 2 - Command Status Reg */ + uint8_t CT3_CMD_STATUS; /* Ctr/Timer 3 - Command Status Reg */ + uint8_t PORTA_DATA; /* Port A - Data */ + uint8_t PORTB_DATA; /* Port B - Data */ + uint8_t PORTC_DATA; /* Port C - Data */ +/* COUNTER/TIMER RELATED REGISTERS (0x10-0x1f) */ + uint8_t CT1_CUR_CNT_MSB; /* Ctr/Timer 1 - Current Count (MSB) */ + uint8_t CT1_CUR_CNT_LSB; /* Ctr/Timer 1 - Current Count (LSB) */ + uint8_t CT2_CUR_CNT_MSB; /* Ctr/Timer 2 - Current Count (MSB) */ + uint8_t CT2_CUR_CNT_LSB; /* Ctr/Timer 2 - Current Count (LSB) */ + uint8_t CT3_CUR_CNT_MSB; /* Ctr/Timer 3 - Current Count (MSB) */ + uint8_t CT3_CUR_CNT_LSB; /* Ctr/Timer 3 - Current Count (LSB) */ + uint8_t CT1_TIME_CONST_MSB; /* Ctr/Timer 1 - Time Constant (MSB) */ + uint8_t CT1_TIME_CONST_LSB; /* Ctr/Timer 1 - Time Constant (LSB) */ + uint8_t CT2_TIME_CONST_MSB; /* Ctr/Timer 2 - Time Constant (MSB) */ + uint8_t CT2_TIME_CONST_LSB; /* Ctr/Timer 2 - Time Constant (LSB) */ + uint8_t CT3_TIME_CONST_MSB; /* Ctr/Timer 3 - Time Constant (MSB) */ + uint8_t CT3_TIME_CONST_LSB; /* Ctr/Timer 3 - Time Constant (LSB) */ + uint8_t CT1_MODE_SPEC; /* Ctr/Timer 1 - Mode Specification */ + uint8_t CT2_MODE_SPEC; /* Ctr/Timer 2 - Mode Specification */ + uint8_t CT3_MODE_SPEC; /* Ctr/Timer 3 - Mode Specification */ + uint8_t CURRENT_VECTOR; /* Current Vector */ +/* PORT A SPECIFICATION REGISTERS (0x20 -0x27) */ + uint8_t PORTA_MODE; /* Port A - Mode Specification */ + uint8_t PORTA_HANDSHAKE; /* Port A - Handshake Specification */ + uint8_t PORTA_DATA_POLARITY; /* Port A - Data Path Polarity */ + uint8_t PORTA_DIRECTION; /* Port A - Data Direction */ + uint8_t PORTA_SPECIAL_IO_CTL; /* Port A - Special IO Control */ + uint8_t PORTA_PATT_POLARITY; /* Port A - Pattern Polarity */ + uint8_t PORTA_PATT_TRANS; /* Port A - Pattern Transition */ + uint8_t PORTA_PATT_MASK; /* Port A - Pattern Mask */ +/* PORT B SPECIFICATION REGISTERS (0x28-0x2f) */ + uint8_t PORTB_MODE; /* Port B - Mode Specification */ + uint8_t PORTB_HANDSHAKE; /* Port B - Handshake Specification */ + uint8_t PORTB_DATA_POLARITY; /* Port B - Data Path Polarity */ + uint8_t PORTB_DIRECTION; /* Port B - Data Direction */ + uint8_t PORTB_SPECIAL_IO_CTL; /* Port B - Special IO Control */ + uint8_t PORTB_PATT_POLARITY; /* Port B - Pattern Polarity */ + uint8_t PORTB_PATT_TRANS; /* Port B - Pattern Transition */ + uint8_t PORTB_PATT_MASK; /* Port B - Pattern Mask */ +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/rtems/zilog/z8530.h b/bsps/include/rtems/zilog/z8530.h new file mode 100644 index 0000000000..161b9a022c --- /dev/null +++ b/bsps/include/rtems/zilog/z8530.h @@ -0,0 +1,97 @@ +/** + * @file + * + * @brief Information Related to a Zilog Z8530 SCC Chip + * + * This include file defines information related to a Zilog Z8530 + * SCC Chip. It is a IO mapped part. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_ZILOG_Z8530_H +#define _RTEMS_ZILOG_Z8530_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* macros */ + +#define VOL8( ptr ) ((volatile uint8_t *)(ptr)) + +#define Z8x30_STATE0 ( z8530 ) \ + { char *garbage; \ + (garbage) = *(VOL8(z8530)) \ + } + +#define Z8x30_WRITE_CONTROL( z8530, reg, data ) \ + *(VOL8(z8530)) = (reg); \ + *(VOL8(z8530)) = (data) + +#define Z8x30_READ_CONTROL( z8530, reg, data ) \ + *(VOL8(z8530)) = (reg); \ + (data) = *(VOL8(z8530)) + +#define Z8x30_WRITE_DATA( z8530, data ) \ + *(VOL8(z8530)) = (data); + +#define Z8x30_READ_DATA( z8530, data ) \ + (data) = *(VOL8(z8530)); + + +/* RR_0 Bit Definitions */ + +#define RR_0_TX_BUFFER_EMPTY 0x04 +#define RR_0_RX_DATA_AVAILABLE 0x01 + +/* read registers */ + +#define RR_0 0x00 +#define RR_1 0x01 +#define RR_2 0x02 +#define RR_3 0x03 +#define RR_4 0x04 +#define RR_5 0x05 +#define RR_6 0x06 +#define RR_7 0x07 +#define RR_8 0x08 +#define RR_9 0x09 +#define RR_10 0x0A +#define RR_11 0x0B +#define RR_12 0x0C +#define RR_13 0x0D +#define RR_14 0x0E +#define RR_15 0x0F + +/* write registers */ + +#define WR_0 0x00 +#define WR_1 0x01 +#define WR_2 0x02 +#define WR_3 0x03 +#define WR_4 0x04 +#define WR_5 0x05 +#define WR_6 0x06 +#define WR_7 0x07 +#define WR_8 0x08 +#define WR_9 0x09 +#define WR_10 0x0A +#define WR_11 0x0B +#define WR_12 0x0C +#define WR_13 0x0D +#define WR_14 0x0E +#define WR_15 0x0F + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/include/shm_driver.h b/bsps/include/shm_driver.h new file mode 100644 index 0000000000..cb94cec0cb --- /dev/null +++ b/bsps/include/shm_driver.h @@ -0,0 +1,542 @@ +/* shm_driver.h + * + * This include file contains all the constants, structures, + * and global variables for this RTEMS based shared memory + * communications interface driver. + * + * Processor board dependencies are in other files. + * + * COPYRIGHT (c) 1989-2007. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __SHM_h +#define __SHM_h + +#include <rtems/clockdrv.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* The information contained in the Node Status, Locked Queue, and + * Envelope Control Blocks must be maintained in a NEUTRAL format. + * Currently the neutral format may be selected as big or little + * endian by simply defining either NEUTRAL_BIG or NEUTRAL_LITTLE. + * + * It is CRITICAL to note that the neutral format can ONLY be + * changed by modifying this file and recompiling the ENTIRE + * SHM driver including ALL target specific support files. + * + * The following table details the memory contents for the endian + * field of the Node Status Control Block in the various + * data format configurations (data is in hexadecimal): + * + * NEUTRAL NATIVE BYTE 0 BYTE 1 BYTE 2 BYTE 3 + * ======= ====== ====== ====== ====== ====== + * BIG BIG 00 00 00 01 + * BIG LITTLE 10 00 00 00 + * LITTLE BIG 01 00 00 00 + * LITTLE LITTLE 00 00 00 10 + * + * + * NOTE: XXX + * PORTABILITY OF LOCKING INSTRUCTIONS + * =================================== + * The locking mechanism described below is not + * general enough. Where the hardware supports + * it we should use "atomic swap" instructions + * so the values in the lock can be tailored to + * support a CPU with only weak atomic memory + * instructions. There are combinations of + * CPUs with inflexible atomic memory instructions + * which appear to be incompatible. For example, + * the SPARClite instruction uses a byte which is + * 0xFF when locked. The PA-RISC uses 1 to indicate + * locked and 0 when unlocked. These CPUs appear to + * have incompatible lock instructions. But + * they could be used in a heterogenous system + * with does not mix SPARCs and PA-RISCs. For + * example, the i386 and SPARC or i386 and SPARC + * could work together. The bottom line is that + * not every CPU will work together using this + * locking scheme. There are supposed to be + * algorithms to do this without hardware assist + * and one of these should be incorporated into + * the shared memory driver. + * + * The most flexible scheme using the instructions + * of the various CPUs for efficiency would be to use + * "atomic swaps" wherever possible. Make the lock + * and unlock configurable much like BIG vs LITTLE + * endian use of shared memory is now. The values + * of the lock could then reflect the "worst" + * CPU in a system. This still results in mixes + * of CPUs which are incompatible. + * + * The current locking mechanism is based upon the MC68020 + * "tas" instruction which is atomic. All ports to other CPUs + * comply with the restrictive placement of lock bit by this + * instruction. The lock bit is the most significant bit in a + * big-endian uint32_t . On other processors, the lock is + * typically implemented via an atomic swap or atomic modify + * bits type instruction. + */ + +#define NEUTRAL_BIG + +#ifdef NEUTRAL_BIG +#define SHM_BIG 0x00000001 +#define SHM_LITTLE 0x10000000 +#endif + +#ifdef NEUTRAL_LITTLE +#define SHM_BIG 0x01000000 +#define SHM_LITTLE 0x00000010 +#endif + +/* + * The following are the values used to fill in the lock field. Some CPUs + * are able to write only a single value into field. By making the + * lock and unlock values configurable, CPUs which support "atomic swap" + * instructions can generally be made to work in any heterogeneous + * configuration. However, it is possible for two CPUs to be incompatible + * in regards to the lock field values. This occurs when two CPUs + * which write only a single value to the field are used in a system + * but the two CPUs write different incompatible values. + * + * NOTE: The following is a first attempt at defining values which + * have a chance at working together. The m68k should use + * chk2 instead of tas to be less restrictive. Target endian + * problems (like the Force CPU386 which has (broken) big endian + * view of the VMEbus address space) are not addressed yet. + */ + +#if defined(__mc68000__) +#define SHM_LOCK_VALUE 0x80000000 +#define SHM_UNLOCK_VALUE 0 +#define SHM_LOCK_VALUE 0x80000000 +#define SHM_UNLOCK_VALUE 0 +#elif defined(__i386__) +#define SHM_LOCK_VALUE 0x80000000 +#define SHM_UNLOCK_VALUE 0 +#elif defined(__mips__) +#define SHM_LOCK_VALUE 0x80000000 +#define SHM_UNLOCK_VALUE 0 +#elif defined(__hppa__) +#define SHM_LOCK_VALUE 0 +#define SHM_UNLOCK_VALUE 1 +#elif defined(__PPC__) +#define SHM_LOCK_VALUE 1 +#define SHM_UNLOCK_VALUE 0 +#elif defined(__unix__) +#define SHM_LOCK_VALUE 0 +#define SHM_UNLOCK_VALUE 1 +#elif defined(_AM29K) +#define SHM_LOCK_VALUE 0 +#define SHM_UNLOCK_VALUE 1 +#elif defined(__nios2__) +#define SHM_LOCK_VALUE 1 +#define SHM_UNLOCK_VALUE 0 +#elif defined(__sparc__) +#define SHM_LOCK_VALUE 1 +#define SHM_UNLOCK_VALUE 0 +#elif defined(no_cpu) /* for this values are irrelevant */ +#define SHM_LOCK_VALUE 1 +#define SHM_UNLOCK_VALUE 0 +#else +#error "shm_driver.h - no SHM_LOCK_VALUE defined for this CPU architecture" +#endif + +#define Shm_Convert( value ) \ + ((Shm_Configuration->convert) ? \ + (*Shm_Configuration->convert)(value) : (value)) + +/* constants */ + +#define SHM_MASTER 1 /* master initialization node */ +#define SHM_FIRST_NODE 1 + +/* size constants */ + +#define KILOBYTE (1024) +#define MEGABYTE (1024*1024) + +/* inter-node interrupt values */ + +#define NO_INTERRUPT 0 /* used for polled nodes */ +#define BYTE 1 +#define WORD 2 +#define LONG 4 + +/* operational mode constants -- used in SHM Configuration Table */ +#define POLLED_MODE 0 +#define INTR_MODE 1 + +/* error codes */ + +#define NO_ERROR 0 +#define SHM_NO_FREE_PKTS 0xf0000 + +/* null pointers of different types */ + +#define NULL_ENV_CB ((Shm_Envelope_control *) 0) +#define NULL_CONVERT 0 + +/* + * size of stuff before preamble in envelope. + * It must be a constant since we will use it to generate MAX_PACKET_SIZE + */ + +#define SHM_ENVELOPE_PREFIX_OVERHEAD (4 * sizeof(vol_u32)) + +/* + * The following is adjusted so envelopes are MAX_ENVELOPE_SIZE bytes long. + * It must be >= RTEMS_MINIMUM_PACKET_SIZE in mppkt.h. + */ + +#ifndef MAX_ENVELOPE_SIZE +#define MAX_ENVELOPE_SIZE 0x180 +#endif + +#define MAX_PACKET_SIZE (MAX_ENVELOPE_SIZE - \ + SHM_ENVELOPE_PREFIX_OVERHEAD + \ + sizeof(Shm_Envelope_preamble) + \ + sizeof(Shm_Envelope_postamble)) + + +/* constants pertinent to Locked Queue routines */ + +#define LQ_UNLOCKED SHM_UNLOCK_VALUE +#define LQ_LOCKED SHM_LOCK_VALUE + +/* constants related to the Free Envelope Pool */ + +#define FREE_ENV_POOL 0 +#define FREE_ENV_CB (&Shm_Locked_queues[ FREE_ENV_POOL ]) + +/* The following are important when dealing with + * the shared memory communications interface area. + * + * NOTE: The starting address and length of the shared memory + * is defined in a system dependent file. + */ + +#define START_NS_CBS ((void *)Shm_Configuration->base) +#define START_LQ_CBS ((START_NS_CBS) + \ + ( (sizeof (Shm_Node_status_control)) * (SHM_MAXIMUM_NODES + 1) ) ) +#define START_ENVELOPES ( ((void *) START_LQ_CBS) + \ + ( (sizeof (Shm_Locked_queue_Control)) * (SHM_MAXIMUM_NODES + 1) ) ) +#define END_SHMCI_AREA ( (void *) START_ENVELOPES + \ + ( (sizeof (Shm_Envelope_control)) * Shm_Maximum_envelopes ) ) +#define END_SHARED_MEM (START_NS_CBS+Shm_Configuration->length) + +/* macros */ + +#define Shm_Is_master_node() \ + ( SHM_MASTER ==_Configuration_MP_table-> node ) + +#define Shm_Free_envelope( ecb ) \ + Shm_Locked_queue_Add( FREE_ENV_CB, (ecb) ) +#define Shm_Allocate_envelope() \ + Shm_Locked_queue_Get(FREE_ENV_CB) + +#define Shm_Initialize_receive_queue(node) \ + Shm_Locked_queue_Initialize( &Shm_Locked_queues[node], node ) + +#define Shm_Append_to_receive_queue(node, ecb) \ + Shm_Locked_queue_Add( &Shm_Locked_queues[node], (ecb) ) + +#define Shm_Envelope_control_to_packet_prefix_pointer(ecb) \ + ((void *)(ecb)->packet) + +#define Shm_Packet_prefix_to_envelope_control_pointer( pkt ) \ + ((Shm_Envelope_control *)((uint8_t*)(pkt) - \ + (sizeof(Shm_Envelope_preamble) + SHM_ENVELOPE_PREFIX_OVERHEAD))) + +#define Shm_Build_preamble(ecb, node) \ + (ecb)->Preamble.endian = Shm_Configuration->format + +#define Shm_Build_postamble( ecb ) + +/* volatile types */ + +typedef volatile uint8_t vol_u8; +typedef volatile uint32_t vol_u32; + +/* shm control information */ + +struct shm_info { + vol_u32 not_currently_used_0; + vol_u32 not_currently_used_1; + vol_u32 not_currently_used_2; + vol_u32 not_currently_used_3; +}; + +typedef struct { + /*byte start_of_text;*/ + vol_u32 endian; + vol_u32 not_currently_used_0; + vol_u32 not_currently_used_1; + vol_u32 not_currently_used_2; +} Shm_Envelope_preamble; + +typedef struct { +} Shm_Envelope_postamble; + +/* WARNING! If you change this structure, don't forget to change + * SHM_ENVELOPE_PREFIX_OVERHEAD and + * Shm_Packet_prefix_to_envelope_control_pointer() above. + */ + +/* This comment block describes the contents of each field + * of the Envelope Control Block: + * + * next - The index of the next envelope on this queue. + * queue - The index of the queue this envelope is on. + * index - The index of this envelope. + * Preamble - Generic packet preamble. One day this structure + * could be enhanced to contain routing information. + * packet - RTEMS MPCI packet. Untouched by SHM Driver + * other than copying and format conversion as + * documented in the RTEMS User's Guide. + * Postamble - Generic packet postamble. One day this structure + * could be enhanced to contain checksum information. + */ + +typedef struct { + vol_u32 next; /* next envelope on queue */ + vol_u32 queue; /* queue on which this resides */ + vol_u32 index; /* index into array of envelopes*/ + vol_u32 pad0; /* insure the next one is aligned */ + Shm_Envelope_preamble Preamble; /* header information */ + vol_u8 packet[MAX_PACKET_SIZE]; /* RTEMS INFO */ + Shm_Envelope_postamble Postamble;/* trailer information */ +} Shm_Envelope_control; + +/* This comment block describes the contents of each field + * of the Locked Queue Control Block: + * + * lock - Lock used to insure mutually exclusive access. + * front - Index of first envelope on queue. This field + * is used to remove head of queue (receive). + * rear - Index of last envelope on queue. This field + * is used to add evelope to queue (send). + * owner - The node number of the recipient (owning) node. + * RTEMS does not use the node number zero (0). + * The zero node is used by the SHM Driver for the + * Free Envelope Queue shared by all nodes. + */ + +typedef struct { + vol_u32 lock; /* lock field for this queue */ + vol_u32 front; /* first envelope on queue */ + vol_u32 rear; /* last envelope on queue */ + vol_u32 owner; /* receiving (i.e. owning) node */ +} Shm_Locked_queue_Control; + +/* This comment block describes the contents of each field + * of the Node Status Control Block: + * + * status - Node status. Current values are Pending Initialization, + * Initialization Complete, and Active Node. Other values + * could be added to enhance fault tolerance. + * error - Zero if the node has not failed. Otherwise, + * this field contains a status indicating the + * failure reason. + * int_address, int_value, and int_length + * - These field are the Interrupt Information table + * for this node in neutral format. This is how + * each node knows how to generate interrupts. + */ + +typedef struct { + vol_u32 status; /* node status information */ + vol_u32 error; /* fatal error code */ + vol_u32 int_address; /* write here for interrupt */ + vol_u32 int_value; /* this value causes interrupt */ + vol_u32 int_length; /* for this length (0,1,2,4) */ + vol_u32 not_currently_used_0; + vol_u32 not_currently_used_1; + vol_u32 not_currently_used_2; +} Shm_Node_status_control; + +/* This comment block describes the contents of each field + * of the Interrupt Information Table. This table describes + * how another node can generate an interrupt to this node. + * This information is target board dependent. If the + * SHM Driver is in POLLED_MODE, then all fields should + * be initialized to NO_INTERRUPT. + * + * address - The address to which another node should + * write to cause an interrupt. + * value - The value which must be written + * length - The size of the value to write. Valid + * values are BYTE, WORD, and LONG. + * + * NOTE: The Node Status Control Block contains this + * information in neutral format and not in a + * structure to avoid potential alignment problems. + */ + +typedef struct { + vol_u32 *address; /* write here for interrupt */ + vol_u32 value; /* this value causes interrupt */ + vol_u32 length; /* for this length (0,1,2,4) */ +} Shm_Interrupt_information; + +/* SHM Configuration Table + * + * This comment block describes the contents of each field + * of the SHM Configuration Table. + * + * base - The base address of the shared memory. This + * address may be specific to this node. + * length - The length of the shared memory in bytes. + * format - The natural format for uint32_t 's in the + * shared memory. Valid values are currently + * only SHM_LITTLE and SHM_BIG. + * convert - The address of the routine which converts + * between neutral and local format. + * poll_intr - The operational mode of the driver. Some + * target boards may not provide hardware for + * an interprocessor interrupt. If POLLED_MODE + * is selected, the SHM driver will use a + * Classiv API Timer instance to poll for + * incoming packets. Throughput is dependent + * on the time between clock interrupts. + * Valid values are POLLED_MODE and INTR_MODE. + * cause_intr - This is the address of the routine used to + * write to a particular address and cause an + * interrupt on another node. This routine + * may need to be target dependent if something + * other than a normal write from C does not work. + * Intr - This structure describes the operation required + * to cause an interrupt to this node. The actual + * contents of this structure are described above. + */ + +struct shm_config_info { + vol_u32 *base; /* base address of SHM */ + vol_u32 length; /* length (in bytes) of SHM */ + vol_u32 format; /* SHM is big or little endian */ + uint32_t (*convert)( uint32_t );/* neutral conversion routine */ + vol_u32 poll_intr;/* POLLED or INTR driven mode */ + void (*cause_intr)( uint32_t); + Shm_Interrupt_information Intr; /* cause intr information */ +}; + +typedef struct shm_config_info shm_config_table; + +#define SHM_MAXIMUM_NODES Multiprocessing_configuration.maximum_nodes + +/* global variables */ + +#ifdef _SHM_INIT +#define SHM_EXTERN +#else +#define SHM_EXTERN extern +#endif + +SHM_EXTERN shm_config_table *Shm_Configuration; +SHM_EXTERN Shm_Interrupt_information *Shm_Interrupt_table; +SHM_EXTERN Shm_Node_status_control *Shm_Node_statuses; +SHM_EXTERN Shm_Locked_queue_Control *Shm_Locked_queues; +SHM_EXTERN Shm_Envelope_control *Shm_Envelopes; +SHM_EXTERN uint32_t Shm_Receive_message_count; +SHM_EXTERN uint32_t Shm_Null_message_count; +SHM_EXTERN uint32_t Shm_Interrupt_count; +SHM_EXTERN Shm_Locked_queue_Control *Shm_Local_receive_queue; +SHM_EXTERN Shm_Node_status_control *Shm_Local_node_status; +SHM_EXTERN uint32_t Shm_isrstat; + /* reported by shmdr */ + +SHM_EXTERN uint32_t Shm_Pending_initialization; +SHM_EXTERN uint32_t Shm_Initialization_complete; +SHM_EXTERN uint32_t Shm_Active_node; + +SHM_EXTERN uint32_t Shm_Maximum_envelopes; + +SHM_EXTERN uint32_t Shm_Locked_queue_End_of_list; +SHM_EXTERN uint32_t Shm_Locked_queue_Not_on_list; + +/* functions */ + +/* locked queue routines */ +void Shm_Locked_queue_Add( + Shm_Locked_queue_Control *, Shm_Envelope_control * ); +Shm_Envelope_control *Shm_Locked_queue_Get( Shm_Locked_queue_Control * ); +void Shm_Locked_queue_Initialize( + Shm_Locked_queue_Control *, uint32_t); + /* Shm_Initialize_lock is CPU dependent */ + /* Shm_Lock is CPU dependent */ + /* Shm_Unlock is CPU dependent */ + +/* portable routines */ +void Init_env_pool( void ); +void Shm_Print_statistics( void ); +void MPCI_Fatal( rtems_fatal_source, bool, rtems_fatal_code ); +rtems_task Shm_Cause_interrupt( uint32_t ); +void Shm_install_timer( void ); +void Shm_Convert_packet( rtems_packet_prefix * ); + +/* CPU specific routines are inlined in shmcpu.h */ + +/* target specific routines */ +void *Shm_Convert_address( void * ); +void Shm_Get_configuration( uint32_t, shm_config_table ** ); +void Shm_isr( void ); +void Shm_setvec( void ); + +void Shm_Initialize_lock( Shm_Locked_queue_Control * ); +void Shm_Lock( Shm_Locked_queue_Control * ); +void Shm_Unlock( Shm_Locked_queue_Control * ); + +/* MPCI entry points */ +rtems_mpci_entry Shm_Get_packet( + rtems_packet_prefix ** +); + +rtems_mpci_entry Shm_Initialization( void ); + +rtems_mpci_entry Shm_Receive_packet( + rtems_packet_prefix ** +); + +rtems_mpci_entry Shm_Return_packet( + rtems_packet_prefix * +); + +rtems_mpci_entry Shm_Send_packet( + uint32_t, + rtems_packet_prefix * +); + +extern rtems_mpci_table MPCI_table; + +#ifdef _SHM_INIT + +/* multiprocessor communications interface (MPCI) table */ + +rtems_mpci_table MPCI_table = { + 100000, /* default timeout value in ticks */ + MAX_PACKET_SIZE, /* maximum packet size */ + Shm_Initialization, /* initialization procedure */ + Shm_Get_packet, /* get packet procedure */ + Shm_Return_packet, /* return packet procedure */ + Shm_Send_packet, /* packet send procedure */ + Shm_Receive_packet /* packet receive procedure */ +}; + +#endif + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/include/umon/cli.h b/bsps/include/umon/cli.h new file mode 100644 index 0000000000..0e1689db26 --- /dev/null +++ b/bsps/include/umon/cli.h @@ -0,0 +1,147 @@ +/** + * @file + * + * @ingroup shared_cli + * + * @brief Header file for Command Line Interface related stuff + */ + +/* Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/ + * which includes this notice: + * + ************************************************************************** + * General notice: + * This code is part of a boot-monitor package developed as a generic base + * platform for embedded system designs. As such, it is likely to be + * distributed to various projects beyond the control of the original + * author. Please notify the author of any enhancements made or bugs found + * so that all may benefit from the changes. In addition, notification back + * to the author will allow the new user to pick up changes that may have + * been made by other users after this version of the code was distributed. + * + * Note1: the majority of this code was edited with 4-space tabs. + * Note2: as more and more contributions are accepted, the term "author" + * is becoming a mis-representation of credit. + * + * Original author: Ed Sutter + * Email: esutter@alcatel-lucent.com + * Phone: 908-582-2351 + ************************************************************************** + * + * Ed Sutter has been informed that this code is being used in RTEMS. + * + * This code was reformatted by Joel Sherrill from OAR Corporation and + * Fernando Nicodemos <fgnicodemos@terra.com.br> from NCB - Sistemas + * Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding + * standards and to eliminate C++ style comments. + */ + +#ifndef _cli_h +#define _cli_h + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_cli Command table structure + * + * @ingroup shared_umon + * + * @brief Command table structure used by the monitor: + */ + +struct monCommand { + char *name; /* Name of command seen by user. */ + int (*func)(int,char **); /* Called when command is invoked. */ + char **helptxt; /* Help text (see notes below). */ + long flags; /* Single-bit flags for various uses */ + /* (see the CMDFLAG_XXX macros). */ +}; + +#ifdef __cplusplus +} +#endif + +/* Bits currently assigned to command flags used in the monCommand + * structure... + */ +#define CMDFLAG_NOMONRC 1 + +/* Maximum size of a command line: + */ +#ifndef CMDLINESIZE +#define CMDLINESIZE 128 +#endif + +/* Maximum number of arguments in a command line: + */ +#define ARGCNT 24 + +/* Definitions for docommand() return values: + * + * Note that the CMD_SUCCESS, CMD_FAILURE and CMD_PARAM_ERROR are return + * values used by the local command code also. The remaining errors + * (CMD_LINE_ERROR, CMD_ULVL_DENIED and CMD_NOT_FOUND) are used only by + # the docommand() function. + * + * CMD_SUCCESS: + * Everything worked ok. + * CMD_FAILURE: + * Command parameters were valid, but command itself failed for some other + * reason. The docommand() function does not print a message here, it + * is assumed that the error message was printed by the local function. + * CMD_PARAM_ERROR: + * Command line did not parse properly. Control was passed to a + * local command function, but argument syntax caused it to choke. + * In this case docommand() will print out the generic CLI syntax error + * message. + * CMD_LINE_ERROR: + * Command line itself was invalid. Too many args, invalid shell var + * syntax, etc.. Somekind of command line error prior to checking for + * the command name-to-function match. + * CMD_ULVL_DENIED: + * Command's user level is higher than current user level, so access + * is denied. + * CMD_NOT_FOUND: + * Since these same return values are used for each command function + * plus the docommand() function, this error indicates that docommand() + * could not even find the command in the command table. + * CMD_MONRC_DENIED: + * The command cannot execute because it is considered illegal + * when run from within the monrc file. + */ +#define CMD_SUCCESS 0 +#define CMD_FAILURE -1 +#define CMD_PARAM_ERROR -2 +#define CMD_LINE_ERROR -3 +#define CMD_ULVL_DENIED -4 +#define CMD_NOT_FOUND -5 +#define CMD_MONRC_DENIED -6 + +/* Notes on help text array: + * The monitor's CLI processor assumes that every command's help text + * array abides by a few basic rules... + * First of all, it assumes that every array has AT LEAST two strings. + * The first string in the array of strings is assumed to be a one-line + * abstract describing the command. + * The second string in the array of strings is assumed to be a usage + * message that describes the syntax of the arguments needed by the command. + * If this second string is an empty string (""), the docommand() prints out + * a generic usage string indicating that there are no options or arguements + * to apply to the command. + * All remaining lines are formatted based on the needs of the individual + * command and the final string is a null pointer to let the CLI processor + * know where the end is. + * Following is an example help text array... + * + * char *HelpHelp[] = { + * "Display command set", + * "-[d] [commandname]", + * "Options:", + * " -d list commands and descriptions", + * 0, + * }; + * + */ +#endif diff --git a/bsps/include/umon/monlib.h b/bsps/include/umon/monlib.h new file mode 100644 index 0000000000..efbfc93d59 --- /dev/null +++ b/bsps/include/umon/monlib.h @@ -0,0 +1,265 @@ +/** + * @file + * + * @ingroup shared_monlib + * + * @brief Used by both the monitor and the application that + * may reside on top of the monitor + */ + +/* Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/ + * which includes this notice: + * + ************************************************************************** + * General notice: + * This code is part of a boot-monitor package developed as a generic base + * platform for embedded system designs. As such, it is likely to be + * distributed to various projects beyond the control of the original + * author. Please notify the author of any enhancements made or bugs found + * so that all may benefit from the changes. In addition, notification back + * to the author will allow the new user to pick up changes that may have + * been made by other users after this version of the code was distributed. + * + * Note1: the majority of this code was edited with 4-space tabs. + * Note2: as more and more contributions are accepted, the term "author" + * is becoming a mis-representation of credit. + * + * Original author: Ed Sutter + * Email: esutter@alcatel-lucent.com + * Phone: 908-582-2351 + ************************************************************************** + * + * Ed Sutter has been informed that this code is being used in RTEMS. + * + * This code was reformatted by Joel Sherrill from OAR Corporation and + * Fernando Nicodemos <fgnicodemos@terra.com.br> from NCB - Sistemas + * Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding + * standards and to eliminate C++ style comments. + */ + +#ifndef _MONLIB_H_ +#define _MONLIB_H_ + +#include <umon/tfs.h> +#include <umon/cli.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup shared_monlib MONLIB Support + * + * @ingroup shared_umon + * + * @brief MONLIB Support Package + */ + +extern int monConnect(int (*monptr)(int,void *,void *,void *), + void (*lock)(void),void (*unlock)(void)); +extern void mon_getargv(int *argc,char ***argv); +extern void mon_intsrestore(unsigned long oldval); +extern void mon_appexit(int exit_value); +extern void mon_free(char *buffer); +extern void mon_profiler(void *pdata); +extern void mon_bbc(char *filename, int linenum); +extern void mon_warmstart(unsigned long mask); +extern void mon_delay(long msec); +extern void mon_printpkt(char *buf, int size, int incoming); +extern void mon_printmem(char *mem, int size, int ascii); + + +extern int mon_com(int cmd,void *arg1,void *arg2,void *arg3); +extern int mon_timer(int cmd, void * arg); +extern int mon_setenv(char *varname,char *value); +extern int mon_putchar(char c); +extern int mon_getchar(void); +extern int mon_gotachar(void); +extern int mon_getbytes(char *buf,int count,int block); +extern int mon_restart(int restart_value); +extern int mon_tfsinit(void); +extern int mon_tfsunlink(char *filename); +extern int mon_tfslink(char *source, char *target); +extern int mon_tfsrun(char **arglist,int verbosity); +extern int mon_tfsfstat(char *filename,struct tfshdr *tfp); +extern int mon_tfseof(int file_descriptor); +extern int mon_tfstruncate(int file_descriptor,long length); +extern int mon_tfsread(int file_descriptor,char *buffer,int size); +extern int mon_tfswrite(int file_descriptor,char *buffer,int size); +extern int mon_tfsopen(char *filename,long mode,char *buffer); +extern int mon_tfsclose(int file_descriptor,char *info); +extern int mon_tfsseek(int file_descriptor,int offset,int whence); +extern int mon_tfsgetline(int file_descriptor,char *buffer,int bufsize); +extern int mon_tfsipmod(char *name,char *buffer,int offset,int size); +extern int mon_addcommand(struct monCommand *command_list,char *); +extern int mon_docommand(char *cmdline,int verbosity); +extern int mon_getline(char *buffer,int max,int ledit); +extern int mon_decompress(char *src,int srcsize,char *dest); +extern int mon_heapextend(char *base,int size); +extern int mon_pcicfgwrite(int interface,int bus,int dev,int func,int reg, + unsigned long val); +extern int mon_tfsadd(char *filename, char *info, char *flags, + unsigned char *src, int size); +extern int mon_i2cwrite(int interface, int bigaddr, unsigned char *data, + int len); +extern int mon_i2cread(int interface, int bigaddr, unsigned char *data, + int len); +extern int mon_sendenetpkt(char *pkt, int len); +extern int mon_recvenetpkt(char *pkt, int len); +extern int mon_flashoverride(void *flashinfo, int get, int bank); +extern int mon_flasherase(int snum); +extern int mon_flashwrite(char *dest,char *src, int bytecnt); +extern int mon_flashinfo(int snum,int *size, char **base); +extern int mon_watchdog(void); +extern int mon_timeofday(int cmd, void *arg); + +extern char *mon_getsym(char *symname, char *buf, int bufsize); +extern char *mon_getenv(char *varname); +extern char *mon_getenvp(void); +extern char *mon_version(void); +#ifdef MALLOC_DEBUG +extern char *mon_malloc(int size,char *file, int line); +extern char *mon_realloc(char *buf,int size,char *file, int line); +#else +extern char *mon_malloc(int size); +extern char *mon_realloc(char *buf,int size); +#endif + +extern long mon_tfsctrl(int command,long arg1,long arg2); +extern long mon_tfstell(int file_descriptor); +extern long mon_portcmd(int cmd, void *arg); + +extern unsigned short mon_xcrc16(char *buffer,long length); + +extern unsigned long mon_intsoff(void); + +extern unsigned long mon_pcicfgread(int interface,int bus,int dev, + int func,int reg); + +extern unsigned long mon_pcictrl(int interface, int cmd, + unsigned long arg1, unsigned long arg2); + +extern unsigned long mon_i2cctrl(int interface, int cmd, + unsigned long arg1, unsigned long arg2); + +extern unsigned long mon_assignhandler(long hnum, + unsigned long arg1,unsigned long arg2); + +extern struct tfshdr *mon_tfsnext(struct tfshdr *tfp); +extern struct tfshdr *mon_tfsstat(char *filename); + +#if SHOWVARARGS +extern void mon_memtrace(char *fmt, ...); +extern int mon_printf(char *fmt, ...); +extern int mon_cprintf(char *fmt, ...); +extern int mon_sprintf(char *,char *fmt, ...); +#else +extern void mon_memtrace(); +extern int mon_printf(); +extern int mon_cprintf(); +extern int mon_sprintf(); +#endif + +#ifdef __cplusplus +} +#endif + + +/* defines used by monConnect(): + */ +#define GETMONFUNC_PUTCHAR 1 +#define GETMONFUNC_GETCHAR 2 +#define GETMONFUNC_GOTACHAR 3 +#define GETMONFUNC_GETBYTES 4 +#define GETMONFUNC_PRINTF 5 +#define GETMONFUNC_CPRINTF 6 +#define GETMONFUNC_SPRINTF 7 +#define GETMONFUNC_RESTART 8 +#define GETMONFUNC_GETENV 9 +#define GETMONFUNC_SETENV 10 +#define GETMONFUNC_TFSINIT 11 +#define GETMONFUNC_TFSADD 12 +#define GETMONFUNC_TFSUNLINK 13 +#define GETMONFUNC_TFSRUN 14 +#define GETMONFUNC_TFSNEXT 15 +#define GETMONFUNC_TFSSTAT 16 +#define GETMONFUNC_TFSREAD 17 +#define GETMONFUNC_TFSWRITE 18 +#define GETMONFUNC_TFSOPEN 19 +#define GETMONFUNC_TFSCLOSE 20 +#define GETMONFUNC_TFSSEEK 21 +#define GETMONFUNC_TFSGETLINE 22 +#define GETMONFUNC_TFSIPMOD 23 +#define GETMONFUNC_TFSCTRL 24 +#define GETMONFUNC_ADDCOMMAND 25 +#define GETMONFUNC_DOCOMMAND 26 +#define GETMONFUNC_GETARGV 27 +#define GETMONFUNC_CRC16 28 +#define GETMONFUNC_CRC32 29 +#define GETMONFUNC_PIOGET 30 /* NA (removed as of 1.0) */ +#define GETMONFUNC_PIOSET 31 /* NA (removed as of 1.0) */ +#define GETMONFUNC_PIOCLR 32 /* NA (removed as of 1.0) */ +#define GETMONFUNC_INTSOFF 33 +#define GETMONFUNC_INTSRESTORE 34 +#define GETMONFUNC_APPEXIT 35 +#define GETMONFUNC_MALLOC 36 +#define GETMONFUNC_FREE 37 +#define GETMONFUNC_GETLINE 38 +#define GETMONFUNC_TFSFSTAT 39 +#define GETMONFUNC_TFSEOF 40 +#define GETMONFUNC_DECOMPRESS 41 +#define GETMONFUNC_TFSTRUNCATE 42 +#define GETMONFUNC_HEAPXTEND 43 +#define GETMONFUNC_PROFILER 44 +#define GETMONFUNC_TFSLINK 45 +#define GETMONFUNC_BBC 46 +#define GETMONFUNC_MEMTRACE 47 +#define GETMONFUNC_TFSTELL 48 +#define GETMONFUNC_VERSION 49 +#define GETMONFUNC_WARMSTART 50 +#define GETMONFUNC_PCICFGREAD 51 +#define GETMONFUNC_PCICFGWRITE 52 +#define GETMONFUNC_PCICONTROL 53 +#define GETMONFUNC_I2CREAD 54 +#define GETMONFUNC_I2CWRITE 55 +#define GETMONFUNC_I2CCONTROL 56 +#define GETMONFUNC_MONDELAY 57 +#define GETMONFUNC_GETENVP 58 +#define GETMONFUNC_REALLOC 59 +#define GETMONFUNC_SENDENETPKT 60 +#define GETMONFUNC_RECVENETPKT 61 +#define GETMONFUNC_GETSYM 62 +#define GETMONFUNC_PRINTPKT 63 +#define GETMONFUNC_FLASHWRITE 64 +#define GETMONFUNC_FLASHERASE 65 +#define GETMONFUNC_FLASHINFO 66 +#define GETMONFUNC_ASSIGNHDLR 67 +#define GETMONFUNC_WATCHDOG 68 +#define GETMONFUNC_PRINTMEM 69 +#define GETMONFUNC_PORTCMD 70 +#define GETMONFUNC_TIMEOFDAY 71 +#define GETMONFUNC_TIMER 72 +#define GETMONFUNC_FLASHOVRRD 73 + +#define CACHEFTYPE_DFLUSH 200 +#define CACHEFTYPE_IINVALIDATE 201 + +#define CHARFUNC_PUTCHAR 300 +#define CHARFUNC_GETCHAR 301 +#define CHARFUNC_GOTACHAR 302 +#define CHARFUNC_RAWMODEON 303 +#define CHARFUNC_RAWMODEOFF 304 + +#define ASSIGNFUNC_GETUSERLEVEL 400 + + +/* Defines used by mon_warmstart(): + */ +#define WARMSTART_IOINIT 0x00000001 +#define WARMSTART_BSSINIT 0x00000002 +#define WARMSTART_RUNMONRC 0x00000004 +#define WARMSTART_MONHEADER 0x00000008 +#define WARMSTART_TFSAUTOBOOT 0x00000010 +#define WARMSTART_BOARDINFO 0x00000020 +#define WARMSTART_ALL 0xffffffff +#endif diff --git a/bsps/include/umon/tfs.h b/bsps/include/umon/tfs.h new file mode 100644 index 0000000000..258288bd14 --- /dev/null +++ b/bsps/include/umon/tfs.h @@ -0,0 +1,214 @@ +/** + * @file + * + * @ingroup shared_tfs + * + * @brief Header file for TFS transactions, used by both application and + * monnitor. + */ + +/* Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/ + * which includes this notice: + * + ************************************************************************** + * General notice: + * This code is part of a boot-monitor package developed as a generic base + * platform for embedded system designs. As such, it is likely to be + * distributed to various projects beyond the control of the original + * author. Please notify the author of any enhancements made or bugs found + * so that all may benefit from the changes. In addition, notification back + * to the author will allow the new user to pick up changes that may have + * been made by other users after this version of the code was distributed. + * + * Note1: the majority of this code was edited with 4-space tabs. + * Note2: as more and more contributions are accepted, the term "author" + * is becoming a mis-representation of credit. + * + * Original author: Ed Sutter + * Email: esutter@alcatel-lucent.com + * Phone: 908-582-2351 + ************************************************************************** + * + * Ed Sutter has been informed that this code is being used in RTEMS. + * + * This code was reformatted by Joel Sherrill from OAR Corporation and + * Fernando Nicodemos <fgnicodemos@terra.com.br> from NCB - Sistemas + * Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding + * standards and to eliminate C++ style comments. + */ + +#ifndef _tfs_h +#define _tfs_h + +/** + * @defgroup shared_tfs TFS Support + * + * @ingroup shared_umon + * + * @brief TFS Support Package + */ + +#define TFSINFOSIZE 23 /* Max size of info string (mod4-1). */ + +#ifndef TFSNAMESIZE /* This specifies the maximum size of a file */ +#define TFSNAMESIZE 23 /* name that can be used in TFS. */ +#endif /* This MUST be some value mod4 - 1. */ + +#ifndef TFS_CHANGELOG_FILE /* Information used for change-log */ +#define TFS_CHANGELOG_SIZE 0 /* facility within tfs. */ +#define TFS_CHANGELOG_FILE ".tfschlog" +#endif + +#ifndef SYMFILE /* This specifies the default filename */ +#define SYMFILE "symtbl" /* used by the monitor for the symbol */ +#endif /* table. */ + +#define MINUSRLEVEL 0 /* Minimum user level supported. */ +#define MAXUSRLEVEL 3 /* Maximum user level supported. */ + +#ifndef TFS_RESERVED +#define TFS_RESERVED 4 /* Number of "reserved" entries (ulong) */ +#endif /* in the TFS header. */ + + +/* Flags: */ +#define TFS_EXEC 0x00000001 /* 'e': Executable script. */ +#define TFS_BRUN 0x00000002 /* 'b': To be executed at boot. */ +#define TFS_QRYBRUN 0x00000004 /* 'B': To be executed at boot if */ + /* query passes. */ +#define TFS_SYMLINK 0x00000008 /* 'l': Symbolic link file. */ +#define TFS_EBIN 0x00000010 /* 'E': Executable binary (coff/elf/a.out). */ +#define TFS_CPRS 0x00000040 /* 'c': File is compressed. */ +#define TFS_IPMOD 0x00000080 /* 'i': File is in-place modifiable. */ +#define TFS_UNREAD 0x00000100 /* 'u': File is not even readable if the */ + /* user-level requirement is not met; */ + /* else, it is read-only. */ +#define TFS_ULVLMSK 0x00000600 /* User level mask defines 4 access levels: */ +#define TFS_ULVL0 0x00000000 /* '0' level 0 */ +#define TFS_ULVL1 0x00000200 /* '1' level 1 */ +#define TFS_ULVL2 0x00000400 /* '2' level 2 */ +#define TFS_ULVL3 0x00000600 /* '3' level 3 */ +#define TFS_NSTALE 0x00000800 /* File is NOT stale, invisible to user. + * When this bit is clear, the file is + * considered stale (see notes in tfsadd()). + * See notes in tfsclose() for this. + */ +#define TFS_ACTIVE 0x00008000 /* Used to indicate that file is not deleted. */ + +#define TFS_ULVLMAX TFS_ULVL3 +#define TFS_USRLVL(f) ((f->flags & TFS_ULVLMSK) >> 9) + +/* Open modes */ +#define TFS_RDONLY 0x00010000 /* File is opened for reading. */ +#define TFS_CREATE 0x00020000 /* File is to be created. Error if file */ + /* with the same name already exists. */ +#define TFS_APPEND 0x00040000 /* Append to existing file. If OR'ed */ + /* with TFS_CREATE, then create if */ + /* necessary. */ +#define TFS_ALLFFS 0x00080000 /* File is created with all FFs. */ +#define TFS_CREATERM 0x00100000 /* File is to be created. If file with */ + /* same name already exists, then allow */ + /* tfsadd() to remove it if necessary. */ + +/* The function tfsrunrc() will search through the current file set and */ +/* if the file defined by TFS_RCFILE exists, it will be executed. */ +/* If this file exists, it will NOT be run by tfsrunboot(). */ +#define TFS_RCFILE "monrc" + +/* Requests that can be made to tfsctrl(): */ +#define TFS_ERRMSG 1 +#define TFS_MEMUSE 2 +#define TFS_MEMDEAD 3 +#define TFS_DEFRAG 4 +#define TFS_TELL 5 +#define TFS_UNOPEN 7 +#define TFS_FATOB 8 +#define TFS_FBTOA 9 +#define TFS_MEMAVAIL 10 +#define TFS_TIMEFUNCS 11 +#define TFS_DOCOMMAND 12 +#define TFS_INITDEV 13 +#define TFS_CHECKDEV 14 +#define TFS_DEFRAGDEV 15 +#define TFS_DEFRAGOFF 16 +#define TFS_DEFRAGON 17 +#define TFS_HEADROOM 18 +#define TFS_FCOUNT 19 + +/* struct tfshdr: + * It is in FLASH as part of the file system to record the attributes of + * the file at the time of creation. + */ +struct tfshdr { + unsigned short hdrsize; /* Size of this header. */ + unsigned short hdrvrsn; /* Header version #. */ + long filsize; /* Size of the file. */ + long flags; /* Flags describing the file. */ + unsigned long filcrc; /* 32 bit CRC of file. */ + unsigned long hdrcrc; /* 32 bit CRC of the header. */ + unsigned long modtime; /* Time when file was last modified. */ + struct tfshdr *next; /* Pointer to next file in list. */ + char name[TFSNAMESIZE+1]; /* Name of file. */ + char info[TFSINFOSIZE+1]; /* Miscellaneous info field. */ +#if TFS_RESERVED + unsigned long rsvd[TFS_RESERVED]; +#endif +}; + +#define TFSHDRSIZ sizeof(struct tfshdr) + +/* TFS error returns. */ +#define TFS_OKAY 0 +#define TFSERR_NOFILE -1 +#define TFSERR_NOSLOT -2 +#define TFSERR_EOF -3 +#define TFSERR_BADARG -4 +#define TFSERR_NOTEXEC -5 +#define TFSERR_BADCRC -6 +#define TFSERR_FILEEXISTS -7 +#define TFSERR_FLASHFAILURE -8 +#define TFSERR_WRITEMAX -9 +#define TFSERR_RDONLY -10 +#define TFSERR_BADFD -11 +#define TFSERR_BADHDR -12 +#define TFSERR_CORRUPT -13 +#define TFSERR_MEMFAIL -14 +#define TFSERR_NOTIPMOD -16 +#define TFSERR_MUTEXFAILURE -17 +#define TFSERR_FLASHFULL -18 +#define TFSERR_USERDENIED -19 +#define TFSERR_NAMETOOBIG -20 +#define TFSERR_FILEINUSE -21 +#define TFSERR_NOTCPRS -22 +#define TFSERR_NOTAVAILABLE -23 +#define TFSERR_BADFLAG -24 +#define TFSERR_CLEANOFF -25 +#define TFSERR_FLAKEYSOURCE -26 +#define TFSERR_BADEXTENSION -27 +#define TFSERR_MIN -100 + +/* TFS seek options. */ +#define TFS_BEGIN 1 +#define TFS_CURRENT 2 +#define TFS_END 3 + +/* Macros: */ +#define TFS_DELETED(fp) (!((fp)->flags & TFS_ACTIVE)) +#define TFS_FILEEXISTS(fp) ((fp)->flags & TFS_ACTIVE) +#define TFS_ISCPRS(fp) ((fp)->flags & TFS_CPRS) +#define TFS_ISEXEC(fp) ((fp)->flags & TFS_EXEC) +#define TFS_ISBOOT(fp) ((fp)->flags & TFS_BRUN) +#define TFS_ISLINK(fp) ((fp)->flags & TFS_SYMLINK) +#define TFS_STALE(fp) (!((fp)->flags & TFS_NSTALE)) +#define TFS_FLAGS(fp) ((fp)->flags) +#define TFS_NAME(fp) ((fp)->name) +#define TFS_SIZE(fp) ((fp)->filsize) +#define TFS_TIME(fp) ((fp)->modtime) +#define TFS_INFO(fp) ((fp)->info) +#define TFS_NEXT(fp) ((fp)->next) +#define TFS_CRC(fp) ((fp)->filcrc) +#define TFS_ENTRY(fp) ((fp)->entry) +#define TFS_BASE(fp) ((char *)(fp)+(fp)->hdrsize) + +typedef struct tfshdr TFILE; +#endif |