summaryrefslogtreecommitdiffstats
path: root/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
diff options
context:
space:
mode:
authorRalf Corsepius <ralf.corsepius@rtems.org>2004-04-21 10:43:04 +0000
committerRalf Corsepius <ralf.corsepius@rtems.org>2004-04-21 10:43:04 +0000
commit6128a4aa5e791ed4e0a655bfd346a52d92da7883 (patch)
treeaf53ca3f67ce405b6fbc6c98399c8e0c87e01a9e /c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
parent2004-04-20 Ralf Corsepius <ralf_corsepius@rtems.org> (diff)
downloadrtems-6128a4aa5e791ed4e0a655bfd346a52d92da7883.tar.bz2
Remove stray white spaces.
Diffstat (limited to 'c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c')
-rw-r--r--c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c b/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
index e5d1fcce1b..3f016c3612 100644
--- a/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
@@ -1,6 +1,6 @@
/* Hwr_init.c
*
- * $Id:
+ * $Id:
*/
#include <bsp.h>
@@ -75,22 +75,22 @@ typedef struct {
void init_RTC()
{
volatile Harris_RTC *the_RTC;
-
+
the_RTC = (volatile Harris_RTC *)SCORE603E_RTC_ADDRESS;
the_RTC->command_register = 0x0;
}
void init_PCI()
-{
+{
#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
uint32_t value;
/*
- * NOTE: Accessing any memory location not mapped by the BAT
- * registers will cause a TLB miss exception.
- * Set the DBAT1 to be configured for 256M of PCI MEM
- * at 0xC0000000 with Write-through and Guarded Attributed and
+ * NOTE: Accessing any memory location not mapped by the BAT
+ * registers will cause a TLB miss exception.
+ * Set the DBAT1 to be configured for 256M of PCI MEM
+ * at 0xC0000000 with Write-through and Guarded Attributed and
* read/write access allowed
*/
@@ -118,10 +118,10 @@ void init_PCI()
#if (0)
/*
- * NOTE: Accessing any memory location not mapped by the BAT
- * registers will cause a TLB miss exception.
- * Set the DBAT3 to be configured for 256M of PCI MEM
- * at 0xC0000000 with Write-through and Guarded Attributed and
+ * NOTE: Accessing any memory location not mapped by the BAT
+ * registers will cause a TLB miss exception.
+ * Set the DBAT3 to be configured for 256M of PCI MEM
+ * at 0xC0000000 with Write-through and Guarded Attributed and
* read/write access allowed
*/
@@ -192,7 +192,7 @@ void data_cache_enable ()
uint32_t value;
/*
- * enable data cache
+ * enable data cache
*/
PPC_Get_HID0( value );