Remove stray white spaces.

24 files changed, 392 insertions, 392 deletions

diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c
index 9a3f6b79d4..feb01efb96 100644
--- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c
+++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c
@@ -37,7 +37,7 @@ void PCI_bus_delay ()
 void PCI_bus_write(
   volatile uint32_t         * _addr,                  /* IN */
   uint32_t         _data                              /* IN */
-) 
+)
 {
   _data = Convert_Endian_32( _data );
   *_addr = _data;
@@ -48,7 +48,7 @@ uint32_t         PCI_bus_read(
 )
 {
   uint32_t         data;
- 
+
   data = *_addr;
   data = Convert_Endian_32( data );
   return data;
@@ -68,7 +68,7 @@ uint32_t         Read_pci_device_register(
    * Write the PCI configuration address
    */
    PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address );
-  
+
   /*
    *  Delay needed when running out of DRAM
    */
@@ -78,20 +78,20 @@ uint32_t         Read_pci_device_register(
    * read data
    */
   data = PCI_bus_read( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_DATA );
-  
+
   return data;
 }
 
 void  Write_pci_device_register(
   uint32_t         address,
-  uint32_t         data 
+  uint32_t         data
 )
 {
   /*
    * Write the PCI configuration address
    */
    PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address );
-  
+
   /*
    *  Delay needed when running out of DRAM
    */
diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h
index 16d2bbfc6f..78f0e71973 100644
--- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h
+++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h
@@ -10,7 +10,7 @@
  *  the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  $Id: 
+ *  $Id:
  */
 #ifndef __PCI_h
 #define __PCI_h
@@ -20,12 +20,12 @@
  */
 
 void PCI_bus_write(
-  volatile uint32_t         * _addr, 
-  uint32_t         _data 
-); 
+  volatile uint32_t         * _addr,
+  uint32_t         _data
+);
 
 uint32_t         PCI_bus_read(
-  volatile uint32_t         *  _addr 
+  volatile uint32_t         *  _addr
 );
 
 uint32_t         Read_pci_device_register(
@@ -34,7 +34,7 @@ uint32_t         Read_pci_device_register(
 
 void  Write_pci_device_register(
   uint32_t         address,
-  uint32_t         data 
+  uint32_t         data
 );
 
 #endif
diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c
index 8b1cfa0958..c04c288c69 100644
--- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c
+++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c
@@ -22,7 +22,7 @@ unsigned int SCORE603e_FLASH_Disable(
 )
 {
   uint8_t         value;
- 
+
   value = *SCORE603E_BOARD_CTRL_REG;
   value = value | (~SCORE603E_BRD_FLASH_DISABLE_MASK);
   *SCORE603E_BOARD_CTRL_REG = value;
@@ -32,7 +32,7 @@ unsigned int SCORE603e_FLASH_Disable(
 
 unsigned int SCORE603e_FLASH_verify_enable()
 {
-  volatile uint8_t         *Ctrl_Status_Register = 
+  volatile uint8_t         *Ctrl_Status_Register =
            (void *)SCORE603E_BOARD_CTRL_REG;
   uint8_t          ctrl_value;
   uint32_t         pci_value;
diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c
index eccf81476b..fda1760b0e 100644
--- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c
+++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c
@@ -97,9 +97,9 @@ typedef struct {
   uint32_t         V6_STATID;              /* 0x80030338 */
   uint32_t         V7_STATID;              /* 0x8003033C */
   uint32_t         Buf_0x80030340[ 0x30 ]; /* 0x80030340 */
-  uint32_t         MAST_CTL;               /* 0x80030400 */ 
-  uint32_t         MISC_CTL;               /* 0x80030404 */ 
-  uint32_t         MISC_STAT;              /* 0x80030408 */ 
+  uint32_t         MAST_CTL;               /* 0x80030400 */
+  uint32_t         MISC_CTL;               /* 0x80030404 */
+  uint32_t         MISC_STAT;              /* 0x80030408 */
   uint32_t         USER_AM;                /* 0x8003040C */
   uint32_t         Buf_0x80030410[ 0x2bc ];/* 0x80030410 */
   uint32_t         VSI0_CTL;               /* 0x80030F00 */
@@ -135,7 +135,7 @@ typedef struct {
   uint32_t         VCSR_BS;                /* 0x80030FFC */
 } Universe_Memory;
 
-volatile Universe_Memory *UNIVERSE = 
+volatile Universe_Memory *UNIVERSE =
                          (volatile Universe_Memory *)SCORE603E_UNIVERSE_BASE;
 
 
@@ -160,21 +160,21 @@ void initialize_universe()
 #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
   volatile uint32_t         universe_temp_value;
 #endif
- 
+
   /*
    * Read the VME jumper location to determine the VME base address
    */
-  jumper_selection = PCI_bus_read( 
+  jumper_selection = PCI_bus_read(
                      (volatile uint32_t*)SCORE603E_VME_JUMPER_ADDR );
   jumper_selection = (jumper_selection >> 3) & 0x1f;
 
   /*
-   * Verify the UNIVERSE CHIP ID 
+   * Verify the UNIVERSE CHIP ID
    */
    pci_id = Read_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE );
 
-   /* 
-    * compare to known ID 
+   /*
+    * compare to known ID
     */
    if (pci_id !=  SCORE603E_UNIVERSE_CHIP_ID ){
      DEBUG_puts ("Invalid SCORE603E_UNIVERSE_CHIP_ID: ");
@@ -197,14 +197,14 @@ void initialize_universe()
     */
    Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x4, 0x2800007 );
 
-   /* 
+   /*
     * Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register
     */
-   PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 );   
+   PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 );
 
    /*
     * Set the VMEbus Master Control register with retry forever, 256 bytes
-    * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes 
+    * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes
     * aligned burst size and PCI bus number to be zero
     */
    PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 );
@@ -213,17 +213,17 @@ void initialize_universe()
     * VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data
     * width, A32 VMEbus Address Space, AM code to be data, none-privilleged,
     * single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable
-    PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 );   
+    PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 );
     */
-   
+
    PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );
    PCI_bus_write( &UNIVERSE->LSI0_BS,  0x04000000 );
    PCI_bus_write( &UNIVERSE->LSI0_BD,  0x05000000 );
    PCI_bus_write( &UNIVERSE->LSI0_TO,  0x7C000000 );
 
-   /* 
+   /*
     * Remove the Universe from VMEbus BI-Mode (bus-isolation).  Once out of
-    * BI-Mode VMEbus accesses can be made. 
+    * BI-Mode VMEbus accesses can be made.
     */
 
    universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL );
@@ -232,7 +232,7 @@ void initialize_universe()
      PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value | ~0xFF0FFFFF));
 
 #elif (SCORE603E_USE_DINK)
-   /* 
+   /*
     * Do not modify the DINK setup of the universe chip.
     */
 
@@ -249,22 +249,22 @@ void initialize_universe()
  *       Slave Image 0 registers.
  */
 void set_vme_base_address (
-  uint32_t         base_address 
+  uint32_t         base_address
 )
-{  
+{
   volatile uint32_t         temp;
 
   /*
    * Calculate the current size of the Slave VME image 0
    */
-  temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) - 
+  temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) -
           ( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000);
 
   /*
-   * Set the VMEbus Slave Image 0 Base Address to be 
+   * Set the VMEbus Slave Image 0 Base Address to be
    * the specifed base address on VSI0_BS register.
    */
-   PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) );   
+   PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) );
 
   /*
    * Update the VMEbus Slave Image 0 Bound Address.
@@ -282,7 +282,7 @@ void set_vme_base_address (
  * Gets the VME base address
  */
 uint32_t         get_vme_base_address ()
-{  
+{
   volatile uint32_t         temp;
 
   temp = PCI_bus_read( &UNIVERSE->VSI0_BS );
@@ -304,15 +304,15 @@ uint32_t         get_vme_slave_size()
  * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF)
  */
 void set_vme_slave_size (uint32_t         size)
-{  
+{
   volatile uint32_t         temp;
 
-  if (size<0) 
+  if (size<0)
     size = 0;
-  
-  if (size > 0x17FFFFF) 
+
+  if (size > 0x17FFFFF)
     size = 0x17FFFFF;
-   
+
   /*
    * Read the VME slave image base address
    */
diff --git a/c/src/lib/libbsp/powerpc/score603e/clock/clock.c b/c/src/lib/libbsp/powerpc/score603e/clock/clock.c
index ce299f3ba1..7d768acea7 100644
--- a/c/src/lib/libbsp/powerpc/score603e/clock/clock.c
+++ b/c/src/lib/libbsp/powerpc/score603e/clock/clock.c
@@ -43,11 +43,11 @@ uint32_t         Clock_Decrementer_value;
 rtems_isr_entry  Old_ticker;
 
 void Clock_exit( void );
- 
+
 /*
  * These are set by clock driver during its init
  */
- 
+
 rtems_device_major_number rtems_clock_major = ~0;
 rtems_device_minor_number rtems_clock_minor;
 
@@ -139,11 +139,11 @@ void Install_clock(
 
 void Clock_exit( void )
 {
-  /* nothing to do */; 
+  /* nothing to do */;
 
   /* do not restore old vector */
 }
- 
+
 /*
  *  Clock_initialize
  *
@@ -170,17 +170,17 @@ rtems_device_driver Clock_initialize(
                        (BSP_Configuration.microseconds_per_tick / 1000);
 
   Install_clock( (rtems_isr_entry) Clock_isr );
- 
+
   /*
    * make major/minor avail to others such as shared memory driver
    */
- 
+
   rtems_clock_major = major;
   rtems_clock_minor = minor;
- 
+
   return RTEMS_SUCCESSFUL;
 }
- 
+
 /*
  *  Clock_control
  *
@@ -205,15 +205,15 @@ rtems_device_driver Clock_control(
 {
     uint32_t         isrlevel;
     rtems_libio_ioctl_args_t *args = pargp;
- 
+
     if (args == 0)
         goto done;
- 
+
     /*
      * This is hokey, but until we get a defined interface
      * to do this, it will just be this simple...
      */
- 
+
     if (args->command == rtems_build_name('I', 'S', 'R', ' '))
     {
         Clock_isr( CLOCK_VECTOR, pargp );
@@ -224,7 +224,7 @@ rtems_device_driver Clock_control(
        (void) set_vector( args->buffer, CLOCK_VECTOR, 1 );
       rtems_interrupt_enable( isrlevel );
     }
- 
+
 done:
     return RTEMS_SUCCESSFUL;
 }
diff --git a/c/src/lib/libbsp/powerpc/score603e/console/85c30.c b/c/src/lib/libbsp/powerpc/score603e/console/85c30.c
index ed5592e6b1..0bad370f35 100644
--- a/c/src/lib/libbsp/powerpc/score603e/console/85c30.c
+++ b/c/src/lib/libbsp/powerpc/score603e/console/85c30.c
@@ -1,5 +1,5 @@
 /*
- *  This file contains the console driver chip level routines for the 
+ *  This file contains the console driver chip level routines for the
  *  z85c30 chip.
  *
  *  Currently only polled mode is supported.
@@ -11,7 +11,7 @@
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  $Id: 
+ *  $Id:
  */
 
 #include <rtems.h>
@@ -42,19 +42,19 @@ typedef struct {
 } char_size_info;
 
 static const char_size_info Char_size_85c30[] = {
-  { Z8530_READ_CHARACTER_BITS_8, Z8530_WRITE_CHARACTER_BITS_8, 0xFF }, 
-  { Z8530_READ_CHARACTER_BITS_7, Z8530_WRITE_CHARACTER_BITS_7, 0x7F }, 
-  { Z8530_READ_CHARACTER_BITS_6, Z8530_WRITE_CHARACTER_BITS_6, 0x3F }, 
+  { Z8530_READ_CHARACTER_BITS_8, Z8530_WRITE_CHARACTER_BITS_8, 0xFF },
+  { Z8530_READ_CHARACTER_BITS_7, Z8530_WRITE_CHARACTER_BITS_7, 0x7F },
+  { Z8530_READ_CHARACTER_BITS_6, Z8530_WRITE_CHARACTER_BITS_6, 0x3F },
   { Z8530_READ_CHARACTER_BITS_5, Z8530_WRITE_CHARACTER_BITS_5, 0x1F }
 };
 
-static const unsigned char Clock_speed_85c30[] = { 
+static const unsigned char Clock_speed_85c30[] = {
   Z8530_x1_CLOCK, Z8530_x16_CLOCK, Z8530_x32_CLOCK,  Z8530_x64_CLOCK };
 
-static const unsigned char Stop_bit_85c30[] = { 
+static const unsigned char Stop_bit_85c30[] = {
   Z8530_STOP_BITS_1, Z8530_STOP_BITS_1_AND_A_HALF, Z8530_STOP_BITS_2 };
 
-static const unsigned char Parity_85c30[] = { 
+static const unsigned char Parity_85c30[] = {
   Z8530_PARITY_NONE, Z8530_PARITY_ODD, Z8530_PARITY_EVEN };
 
 
@@ -64,19 +64,19 @@ static const unsigned char Parity_85c30[] = {
  *
  * Read a Z85c30 register
  */
-static unsigned char Read_85c30_register( 
+static unsigned char Read_85c30_register(
   volatile unsigned char *csr,                        /* IN  */
   unsigned char  register_number                      /* IN  */
 )
 {
   unsigned char Data;
- 
-  *csr = register_number; 
+
+  *csr = register_number;
 
   rtems_bsp_delay_in_bus_cycles( 40 );
 
   Data = *csr;
-  
+
   rtems_bsp_delay_in_bus_cycles( 40 );
 
   return Data;
@@ -118,7 +118,7 @@ void Reset_85c30_chip(
   Write_85c30_register( ctrl_0, 0x09, 0x80 );
   Write_85c30_register( ctrl_1, 0x09, 0x40 );
 }
- 
+
 
 /* PAGE
  *
@@ -138,7 +138,7 @@ void initialize_85c30_port(
   Setup = Port->Protocol;
   ctrl  = Port->ctrl;
 
-  baud_constant = _Score603e_Z8530_Baud( Port->Chip->clock_frequency, 
+  baud_constant = _Score603e_Z8530_Baud( Port->Chip->clock_frequency,
     Port->Chip->clock_x, Setup->baud_rate );
 
   /*
@@ -244,13 +244,13 @@ void initialize_85c30_port(
   value = 0x8a;
   value = value |  Char_size_85c30[ Setup->write_char_bits ].write_setup;
   Write_85c30_register( ctrl, 0x05, value );
- 
+
   /*
    * Reset Tx UNDERRUN/EOM LATCH and ERROR
-   * via register 0 
+   * via register 0
    */
    Write_85c30_register( ctrl, 0x00, 0xf0 );
- 
+
 #if CONSOLE_USE_INTERRUPTS
   /*
    *  Set Write Register 1 to interrupt on Rx characters or special condition.
@@ -311,7 +311,7 @@ void outbyte_polled_85c30(
 {
   unsigned char       z8530_status;
   uint32_t            isrlevel;
- 
+
   rtems_interrupt_disable( isrlevel );
 
   /*
@@ -324,7 +324,7 @@ void outbyte_polled_85c30(
   /*
    * Write the character.
    */
-  Write_85c30_register( csr, DATA_REGISTER, (unsigned char) ch ); 
+  Write_85c30_register( csr, DATA_REGISTER, (unsigned char) ch );
 
   rtems_interrupt_enable( isrlevel );
 }
@@ -336,7 +336,7 @@ void outbyte_polled_85c30(
  *  This routine polls for a character.
  */
 
-int inbyte_nonblocking_85c30(   
+int inbyte_nonblocking_85c30(
   const Port_85C30_info      *Port
 )
 {
@@ -352,7 +352,7 @@ int inbyte_nonblocking_85c30(
   z8530_status = Read_85c30_register( csr, STATUS_REGISTER );
   if ( !Z8530_Status_Is_RX_character_available( z8530_status ) )
     return -1;
-  
+
   /*
    * Return the character read.
    */
@@ -396,7 +396,7 @@ rtems_isr ISR_85c30_Async(
   if ( Z8530_Status_Is_RX_character_available( status ) ) {
     data = Read_85c30_register( Port->ctrl, DATA_REGISTER );
     data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value;
-    
+
     rtems_termios_enqueue_raw_characters( Port->Protocol->console_termios_data,
        &data, 1 );
     did_something = TRUE;
diff --git a/c/src/lib/libbsp/powerpc/score603e/console/85c30.h b/c/src/lib/libbsp/powerpc/score603e/console/85c30.h
index 4a1e482a06..121d641994 100644
--- a/c/src/lib/libbsp/powerpc/score603e/console/85c30.h
+++ b/c/src/lib/libbsp/powerpc/score603e/console/85c30.h
@@ -1,6 +1,6 @@
 /*  85c30.h
  *
- *  This include file contains z85c30 chip information. 
+ *  This include file contains z85c30 chip information.
  *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
@@ -9,7 +9,7 @@
  *  the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  $Id: 
+ *  $Id:
  */
 
 #ifndef __85c30_H
@@ -18,7 +18,7 @@
 /*
  * Clock Speed Definations
  */
- 
+
 #define Z8530_x1_CLOCK                        0x00
 #define Z8530_x16_CLOCK                       0x40
 #define Z8530_x32_CLOCK                       0x80
diff --git a/c/src/lib/libbsp/powerpc/score603e/console/console.c b/c/src/lib/libbsp/powerpc/score603e/console/console.c
index 5391eeca47..78cf33c9e0 100644
--- a/c/src/lib/libbsp/powerpc/score603e/console/console.c
+++ b/c/src/lib/libbsp/powerpc/score603e/console/console.c
@@ -24,8 +24,8 @@
 
 #if (1)
 /*
- * The Port Used for the Console interface is based upon which 
- * debugger is being used.  The SDS debugger uses a binary 
+ * The Port Used for the Console interface is based upon which
+ * debugger is being used.  The SDS debugger uses a binary
  * interface on port 0 as part of the debugger.  Thus port 0 can
  * not be used as the console port for the SDS debugger.
  */
@@ -58,7 +58,7 @@ int USE_FOR_CONSOLE = USE_FOR_CONSOLE_DEF;
  *
  *  Console Device Driver Entry Points
  */
- 
+
 /* PAGE
  *
  *  DEBUG_puts
@@ -89,7 +89,7 @@ void DEBUG_puts(
 
   /* should disable interrupts here */
 
-  for ( s = string ; *s ; s++ ) 
+  for ( s = string ; *s ; s++ )
     outbyte_polled_85c30( csr, *s );
 
   outbyte_polled_85c30( csr, '\r' );
@@ -100,28 +100,28 @@ void DEBUG_puts(
 
 /* PAGE
  *
- *  console_inbyte_nonblocking 
+ *  console_inbyte_nonblocking
  *
  *  Console Termios polling input entry point.
  */
 
-int console_inbyte_nonblocking( 
-  int minor 
+int console_inbyte_nonblocking(
+  int minor
 )
 {
   int                       port = minor;
 
-  /* 
-   * verify port Number 
+  /*
+   * verify port Number
    */
   assert ( port < NUM_Z85C30_PORTS );
- 
+
   /*
    * return a character from the 85c30 port.
    */
   return inbyte_nonblocking_85c30( &Ports_85C30[ port ] );
 }
- 
+
 rtems_device_driver console_close(
   rtems_device_major_number major,
   rtems_device_minor_number minor,
@@ -130,7 +130,7 @@ rtems_device_driver console_close(
 {
   return rtems_termios_close (arg);
 }
- 
+
 rtems_device_driver console_read(
   rtems_device_major_number major,
   rtems_device_minor_number minor,
@@ -139,7 +139,7 @@ rtems_device_driver console_read(
 {
   return rtems_termios_read (arg);
 }
- 
+
 rtems_device_driver console_write(
   rtems_device_major_number major,
   rtems_device_minor_number minor,
@@ -148,7 +148,7 @@ rtems_device_driver console_write(
 {
   return rtems_termios_write (arg);
 }
- 
+
 rtems_device_driver console_control(
   rtems_device_major_number major,
   rtems_device_minor_number minor,
@@ -171,7 +171,7 @@ rtems_isr console_isr(
 )
 {
   int  i;
-  
+
   for (i=0; i < NUM_Z85C30_PORTS; i++){
       ISR_85c30_Async( &Ports_85C30[i] );
 
@@ -180,7 +180,7 @@ rtems_isr console_isr(
       ISR_85c30_Async( &Ports_85C30[i] );
     }
 #endif
-  }  
+  }
 }
 
 void console_exit()
@@ -190,12 +190,12 @@ void console_exit()
   uint32_t         ch;
 
   for ( i=0 ; i < NUM_Z85C30_PORTS ; i++ ) {
-    
+
     buffer = &( Ports_85C30[i].Protocol->TX_Buffer);
 
     while ( !Ring_buffer_Is_empty( buffer ) ) {
       Ring_buffer_Remove_character( buffer, ch );
-      outbyte_polled_85c30( Ports_85C30[i].ctrl, ch ); 
+      outbyte_polled_85c30( Ports_85C30[i].ctrl, ch );
     }
   }
 }
@@ -205,7 +205,7 @@ void console_initialize_interrupts( void )
   volatile Ring_buffer_t     *buffer;
   Console_Protocol  *protocol;
   int               i;
-  
+
   for ( i=0 ; i < NUM_Z85C30_PORTS ; i++ ) {
     protocol = Ports_85C30[i].Protocol;
 
@@ -217,15 +217,15 @@ void console_initialize_interrupts( void )
     protocol->Is_TX_active = FALSE;
   }
 
-  /* 
+  /*
    * Connect each vector to the interupt service routine.
    */
   for (i=0; i < NUM_Z85C30_CHIPS; i++)
     set_vector( console_isr, Chips_85C30[i].vector, 1 );
-  
+
 
   atexit( console_exit );
-   
+
 }
 void console_outbyte_interrupts(
   const Port_85C30_info *Port,
@@ -282,7 +282,7 @@ rtems_device_driver console_initialize(
    * Force to perform a hardware reset w/o
    * Master interrupt enable via register 9
    */
-  
+
   for (port=0; port<NUM_Z85C30_PORTS; port++){
     p0 = port;
     port++;
@@ -290,7 +290,7 @@ rtems_device_driver console_initialize(
     Reset_85c30_chip( Ports_85C30[p0].ctrl, Ports_85C30[p1].ctrl );
   }
 #else
-  /* TEMP - To see if this makes a diff with the new ports. 
+  /* TEMP - To see if this makes a diff with the new ports.
    *        Never reset chip 1 when using the chip as a monitor
    */
   for (port=2; port<NUM_Z85C30_PORTS; port++){
@@ -301,7 +301,7 @@ rtems_device_driver console_initialize(
   }
 #endif
 
-  /* 
+  /*
    * Initialize each port.
    * Note:  the ports are numbered such that 0,1 are on the first chip
    *        2,3 are on the second ....
@@ -327,16 +327,16 @@ rtems_device_driver console_initialize(
  *
  */
 int console_write_support(
-  int   minor, 
-  const char *buf, 
+  int   minor,
+  const char *buf,
   int   len)
 {
   int nwrite = 0;
   volatile uint8_t         *csr;
   int                       port = minor;
 
-  /* 
-   * verify port Number 
+  /*
+   * verify port Number
    */
   assert ( port < NUM_Z85C30_PORTS );
 
@@ -453,7 +453,7 @@ void console_outbyte_interrupts(
   uint32_t            isrlevel;
 
   protocol = Port->Protocol;
-  
+
   /*
    *  If this is the first character then we need to prime the pump
    */
@@ -469,7 +469,7 @@ void console_outbyte_interrupts(
   }
 
   while ( Ring_buffer_Is_full( &protocol->TX_Buffer ) );
- 
+
   Ring_buffer_Add_character( &protocol->TX_Buffer, ch );
 }
 
diff --git a/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h b/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h
index 65a7100676..7e20003b41 100644
--- a/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h
+++ b/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h
@@ -9,7 +9,7 @@
  *  the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  $Id: 
+ *  $Id:
  */
 
 #ifndef __CONSOLEBSP_H
@@ -25,12 +25,12 @@ extern "C" {
 
 /*
  *
- * Note:  The Ports are numbered 0..NUM_Z85C30_CHIPS with port 0 and 1 
- *        being on the first chip, and ports 2 and 3 being on the 
+ * Note:  The Ports are numbered 0..NUM_Z85C30_CHIPS with port 0 and 1
+ *        being on the first chip, and ports 2 and 3 being on the
  *        second chip...
  */
 
- 
+
 /*
  * Z85c30 configuration informaiton.
  */
@@ -60,7 +60,7 @@ typedef enum {
 typedef enum {
   CONSOLE_PARITY_NONE,
   CONSOLE_PARITY_ODD,
-  CONSOLE_PARITY_EVEN,  
+  CONSOLE_PARITY_EVEN,
 } CONSOLE_Parity;
 
 typedef enum {
@@ -72,7 +72,7 @@ typedef enum {
 
 typedef struct {
   uint32_t                baud_rate;         /* baud rate value */
-  CONSOLE_Stop_bits        stop_bits;         
+  CONSOLE_Stop_bits        stop_bits;
   CONSOLE_Parity           parity;
   CONSOLE_Character_bits   read_char_bits;
   CONSOLE_Character_bits   write_char_bits;
@@ -83,7 +83,7 @@ typedef struct {
   void          *console_termios_data;
 #endif
 
-} Console_Protocol; 
+} Console_Protocol;
 
 
 /*
@@ -112,7 +112,7 @@ typedef struct {
 } Port_85C30_info;
 
 /*
- * Console port chip configuration tables. 
+ * Console port chip configuration tables.
  */
 extern Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ];
 extern const Port_85C30_info Ports_85C30 [ NUM_Z85C30_PORTS ];
@@ -130,7 +130,7 @@ void outbyte_polled_85c30(
   char ch
 );
 
-int inbyte_nonblocking_85c30(   
+int inbyte_nonblocking_85c30(
   const Port_85C30_info      *Port
 );
 
diff --git a/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c b/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c
index a7b5e8dfea..2212260e0c 100644
--- a/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c
+++ b/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c
@@ -1,5 +1,5 @@
  /*
- *  This file contains the table for the z85c30 port 
+ *  This file contains the table for the z85c30 port
  *  used by the console driver.
  *
  *  COPYRIGHT (c) 1989-1997.
@@ -9,7 +9,7 @@
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  $Id: 
+ *  $Id:
  */
 
 #include "consolebsp.h"
@@ -17,9 +17,9 @@
 
 #define CONSOLE_DEFAULT_BAUD_RATE            9600
 #define CONSOLE_DEFAULT_BAUD_CONSTANT        Score603e_Z8530_Chip0_Baud(9600)
-                                             
-#define CONSOLE_DEFAULT_STOP_BITS            CONSOLE_STOP_BITS_1    
-#define CONSOLE_DEFAULT_PARITY               CONSOLE_PARITY_NONE          
+
+#define CONSOLE_DEFAULT_STOP_BITS            CONSOLE_STOP_BITS_1
+#define CONSOLE_DEFAULT_PARITY               CONSOLE_PARITY_NONE
 #define CONSOLE_DEFAULT_READ_CHARACTER_BITS  CONSOLE_CHARACTER_BITS_8
 #define CONSOLE_DEFAULT_WRITE_CHARACTER_BITS CONSOLE_CHARACTER_BITS_8
 #define CONSOLE_DEFAULT_CONSOLE_CLOCK        CONSOLE_x16_CLOCK
@@ -34,7 +34,7 @@
 /*
  * Tables of information necessary to use the console 85c30 routines.
  */
-Console_Protocol Protocols_85c30 [ NUM_Z85C30_PORTS ] = 
+Console_Protocol Protocols_85c30 [ NUM_Z85C30_PORTS ] =
 {
   DEFAULT_PROTOCOL,
   DEFAULT_PROTOCOL,
@@ -64,8 +64,8 @@ Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ] =
     SCORE603E_85C30_0_CLOCK,
     SCORE603E_85C30_0_CLOCK_X,
     CONSOLE_DEFAULT_CONSOLE_CLOCK
-  }, 
-  { 
+  },
+  {
     SCORE603E_85C30_1_IRQ,
     SCORE603E_85C30_1_CLOCK,
     SCORE603E_85C30_1_CLOCK_X,
@@ -73,25 +73,25 @@ Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ] =
   },
 
 #if (HAS_PMC_PSC8)
-  { 
+  {
     SCORE603E_85C30_2_IRQ,
     SCORE603E_85C30_2_CLOCK,
     SCORE603E_85C30_2_CLOCK_X,
     CONSOLE_DEFAULT_CONSOLE_CLOCK
   },
-  { 
+  {
     SCORE603E_85C30_3_IRQ,
     SCORE603E_85C30_3_CLOCK,
     SCORE603E_85C30_3_CLOCK_X,
     CONSOLE_DEFAULT_CONSOLE_CLOCK
   },
-  { 
+  {
     SCORE603E_85C30_4_IRQ,
     SCORE603E_85C30_4_CLOCK,
     SCORE603E_85C30_4_CLOCK_X,
     CONSOLE_DEFAULT_CONSOLE_CLOCK
   },
-  { 
+  {
     SCORE603E_85C30_5_IRQ,
     SCORE603E_85C30_5_CLOCK,
     SCORE603E_85C30_5_CLOCK_X,
@@ -106,91 +106,91 @@ Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ] =
  * See consolebsp.h for the Port_85C30_info structure defination.
  */
 const Port_85C30_info Ports_85C30 [ NUM_Z85C30_PORTS ] = {
-  { 
-    (volatile unsigned char *) SCORE603E_85C30_CTRL_0,  
+  {
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_0,
     (volatile unsigned char *) SCORE603E_85C30_DATA_0,
     0x00,
     &Protocols_85c30[0],
-    &Chips_85C30[0], 
+    &Chips_85C30[0],
   },
-  {  
-    (volatile unsigned char *) SCORE603E_85C30_CTRL_1,  
-    (volatile unsigned char *) SCORE603E_85C30_DATA_1, 
+  {
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_1,
+    (volatile unsigned char *) SCORE603E_85C30_DATA_1,
     0x01,
     &Protocols_85c30[1],
-    &Chips_85C30[0], 
+    &Chips_85C30[0],
   },
-  {  
-    (volatile unsigned char *) SCORE603E_85C30_CTRL_2,  
+  {
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_2,
     (volatile unsigned char *) SCORE603E_85C30_DATA_2,
     0x02,
     &Protocols_85c30[2],
-    &Chips_85C30[1], 
+    &Chips_85C30[1],
   },
-  {  
-    (volatile unsigned char *) SCORE603E_85C30_CTRL_3, 
+  {
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_3,
     (volatile unsigned char *) SCORE603E_85C30_DATA_3,
     0x03,
     &Protocols_85c30[3],
-    &Chips_85C30[1], 
+    &Chips_85C30[1],
  },
 
 #if (HAS_PMC_PSC8)
-  {  
-    (volatile unsigned char *) SCORE603E_85C30_CTRL_4, 
+  {
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_4,
     (volatile unsigned char *) SCORE603E_85C30_DATA_4,
     0x04,
     &Protocols_85c30[4],
-    &Chips_85C30[2], 
+    &Chips_85C30[2],
  },
- {  
-    (volatile unsigned char *) SCORE603E_85C30_CTRL_5, 
+ {
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_5,
     (volatile unsigned char *) SCORE603E_85C30_DATA_5,
     0x05,
     &Protocols_85c30[5],
-    &Chips_85C30[2], 
+    &Chips_85C30[2],
  },
- {  
-    (volatile unsigned char *) SCORE603E_85C30_CTRL_6, 
+ {
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_6,
     (volatile unsigned char *) SCORE603E_85C30_DATA_6,
     0x06,
     &Protocols_85c30[6],
-    &Chips_85C30[3], 
+    &Chips_85C30[3],
  },
- {  
-    (volatile unsigned char *) SCORE603E_85C30_CTRL_7, 
+ {
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_7,
     (volatile unsigned char *) SCORE603E_85C30_DATA_7,
     0x07,
     &Protocols_85c30[7],
-    &Chips_85C30[3], 
+    &Chips_85C30[3],
  },
- {  
-    (volatile unsigned char *) SCORE603E_85C30_CTRL_8, 
+ {
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_8,
     (volatile unsigned char *) SCORE603E_85C30_DATA_8,
     0x08,
     &Protocols_85c30[8],
-    &Chips_85C30[4], 
+    &Chips_85C30[4],
  },
- {  
-    (volatile unsigned char *) SCORE603E_85C30_CTRL_9, 
+ {
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_9,
     (volatile unsigned char *) SCORE603E_85C30_DATA_9,
     0x09,
     &Protocols_85c30[9],
-    &Chips_85C30[4], 
+    &Chips_85C30[4],
  },
- {  
-    (volatile unsigned char *) SCORE603E_85C30_CTRL_10, 
+ {
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_10,
     (volatile unsigned char *) SCORE603E_85C30_DATA_10,
     0x0a,
     &Protocols_85c30[10],
-    &Chips_85C30[5], 
+    &Chips_85C30[5],
  },
- {  
-    (volatile unsigned char *) SCORE603E_85C30_CTRL_11, 
+ {
+    (volatile unsigned char *) SCORE603E_85C30_CTRL_11,
     (volatile unsigned char *) SCORE603E_85C30_DATA_11,
     0x0b,
     &Protocols_85c30[11],
-    &Chips_85C30[5], 
+    &Chips_85C30[5],
  },
 #endif
 };
diff --git a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h
index 51930235db..12ba21e3c7 100644
--- a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h
+++ b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h
@@ -33,7 +33,7 @@ extern "C" {
 #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4)
 #endif
 #define CONFIGURE_INTERRUPT_STACK_MEMORY  (12 * 1024)
-  
+
 #ifdef ASM
 /* Definition of where to store registers in alignment handler */
 #define ALIGN_REGS 0x0140
@@ -61,11 +61,11 @@ extern "C" {
 
 #define Score603e_Z8530_Chip1_Baud( _value ) \
   _Score603e_Z8530_Baud( SCORE603E_85C30_1_CLOCK, \
-     SCORE603E_85C30_1_CLOCK_X, _value ) 
+     SCORE603E_85C30_1_CLOCK_X, _value )
 
 #define Score603e_Z8530_Chip0_Baud( _value ) \
   _Score603e_Z8530_Baud( SCORE603E_85C30_0_CLOCK, \
-     SCORE603E_85C30_0_CLOCK_X, _value ) 
+     SCORE603E_85C30_0_CLOCK_X, _value )
 
 #define Initialize_Board_ctrl_register()                         \
   *SCORE603E_BOARD_CTRL_REG = (*SCORE603E_BOARD_CTRL_REG |       \
@@ -119,15 +119,15 @@ extern "C" {
 /*
  *  Device Driver Table Entries
  */
- 
+
 /*
  * NOTE: Use the standard Console driver entry
  */
- 
+
 /*
  * NOTE: Use the standard Clock driver entry
  */
- 
+
 
 /*
  *  Information placed in the linkcmds file.
@@ -149,7 +149,7 @@ extern int   end;        /* last address in the program */
 /*
  * How many libio files we want
  */
- 
+
 #define BSP_LIBIO_MAX_FDS       20
 
 /* functions */
@@ -169,13 +169,13 @@ rtems_isr_entry set_vector(                    /* returns old vector */
  */
 rtems_isr bsp_stub_handler(
    rtems_vector_number trap
-); 
+);
 rtems_isr bsp_spurious_handler(
    rtems_vector_number trap
 );
 void bsp_spurious_initialize();
 
-/* 
+/*
  * genvec.c
  */
 rtems_isr_entry  set_EE_vector(
@@ -217,7 +217,7 @@ void set_irq_mask(
 
 uint16_t         get_irq_mask();
 
-void unmask_irq( 
+void unmask_irq(
   uint16_t         irq_idx
 );
 
diff --git a/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h b/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h
index 17d70815dc..90a1847ce4 100644
--- a/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h
+++ b/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h
@@ -82,8 +82,8 @@ extern "C" {
 #define CALLING_OVERHEAD_SEMAPHORE_CREATE          0
 #define CALLING_OVERHEAD_SEMAPHORE_IDENT           0
 #define CALLING_OVERHEAD_SEMAPHORE_DELETE          0
-#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN          0 
-#define CALLING_OVERHEAD_SEMAPHORE_RELEASE         0 
+#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN          0
+#define CALLING_OVERHEAD_SEMAPHORE_RELEASE         0
 #define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE      0
 #define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT       0
 #define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE      0
@@ -109,8 +109,8 @@ extern "C" {
 #define CALLING_OVERHEAD_REGION_RETURN_SEGMENT     0
 #define CALLING_OVERHEAD_PORT_CREATE               0
 #define CALLING_OVERHEAD_PORT_IDENT                0
-#define CALLING_OVERHEAD_PORT_DELETE               0 
-#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 
+#define CALLING_OVERHEAD_PORT_DELETE               0
+#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0
 #define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0
 
 #define CALLING_OVERHEAD_IO_INITIALIZE             0
diff --git a/c/src/lib/libbsp/powerpc/score603e/include/gen2.h b/c/src/lib/libbsp/powerpc/score603e/include/gen2.h
index 2be08e07e4..64d9c10ba5 100644
--- a/c/src/lib/libbsp/powerpc/score603e/include/gen2.h
+++ b/c/src/lib/libbsp/powerpc/score603e/include/gen2.h
@@ -9,7 +9,7 @@
  *  the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  $Id: 
+ *  $Id:
  */
 
 #ifndef __SCORE_GENERATION_2_h
@@ -24,11 +24,11 @@ extern "C" {
 /*
  * ISA/PCI I/O space.
  */
-#define SCORE603E_VME_JUMPER_ADDR      0x00e20000       
+#define SCORE603E_VME_JUMPER_ADDR      0x00e20000
 #define SCORE603E_FLASH_BASE_ADDR      0x04000000
 #define SCORE603E_ISA_PCI_IO_BASE      0x80000000
-#define SCORE603E_TIMER_PORT_C         0xfd000000       
-#define SCORE603E_TIMER_INT_ACK        0xfd000000       
+#define SCORE603E_TIMER_PORT_C         0xfd000000
+#define SCORE603E_TIMER_INT_ACK        0xfd000000
 #define SCORE603E_TIMER_PORT_B         0xfd000008
 #define SCORE603E_TIMER_PORT_A         0xfd000004
 
@@ -45,7 +45,7 @@ extern "C" {
 #define SCORE603E_85C30_DATA_3         ((volatile uint8_t*)0xfe20000c)
 
 /*
- * PSC8 - PMC Card 
+ * PSC8 - PMC Card
  */
 #define SCORE603E_PCI_CONFIGURATION_BASE   0x80800000
 #define SCORE603E_PMC_BASE                 SCORE603E_PCI_CONFIGURATION_BASE
@@ -55,7 +55,7 @@ extern "C" {
 
 #define SCORE603E_PCI_DEVICE_ADDRESS( _offset) \
          ((volatile uint32_t*)( SCORE603E_PCI_PMC_DEVICE_BASE + _offset ))
-  
+
 
 #define SCORE603E_PMC_SERIAL_ADDRESS( _offset )    \
         ((volatile uint8_t*)(SCORE603E_PCI_REGISTER_BASE + _offset))
@@ -63,29 +63,29 @@ extern "C" {
 /*
  * PMC serial channels - (4-7: 232 and 8-11: 422)
  */
-#define SCORE603E_85C30_CTRL_4        SCORE603E_PMC_SERIAL_ADDRESS(0x200020) 
-#define SCORE603E_85C30_DATA_4        SCORE603E_PMC_SERIAL_ADDRESS(0x200024) 
-#define SCORE603E_85C30_CTRL_5        SCORE603E_PMC_SERIAL_ADDRESS(0x200028) 
-#define SCORE603E_85C30_DATA_5        SCORE603E_PMC_SERIAL_ADDRESS(0x20002c) 
-#define SCORE603E_85C30_CTRL_6        SCORE603E_PMC_SERIAL_ADDRESS(0x200030) 
-#define SCORE603E_85C30_DATA_6        SCORE603E_PMC_SERIAL_ADDRESS(0x200034) 
-#define SCORE603E_85C30_CTRL_7        SCORE603E_PMC_SERIAL_ADDRESS(0x200038) 
-#define SCORE603E_85C30_DATA_7        SCORE603E_PMC_SERIAL_ADDRESS(0x20003c) 
-#define SCORE603E_85C30_CTRL_8        SCORE603E_PMC_SERIAL_ADDRESS(0x200000) 
-#define SCORE603E_85C30_DATA_8        SCORE603E_PMC_SERIAL_ADDRESS(0x200004) 
-#define SCORE603E_85C30_CTRL_9        SCORE603E_PMC_SERIAL_ADDRESS(0x200008) 
-#define SCORE603E_85C30_DATA_9        SCORE603E_PMC_SERIAL_ADDRESS(0x20000c) 
-#define SCORE603E_85C30_CTRL_10       SCORE603E_PMC_SERIAL_ADDRESS(0x200010) 
-#define SCORE603E_85C30_DATA_10       SCORE603E_PMC_SERIAL_ADDRESS(0x200014) 
-#define SCORE603E_85C30_CTRL_11       SCORE603E_PMC_SERIAL_ADDRESS(0x200018) 
-#define SCORE603E_85C30_DATA_11       SCORE603E_PMC_SERIAL_ADDRESS(0x20001c) 
+#define SCORE603E_85C30_CTRL_4        SCORE603E_PMC_SERIAL_ADDRESS(0x200020)
+#define SCORE603E_85C30_DATA_4        SCORE603E_PMC_SERIAL_ADDRESS(0x200024)
+#define SCORE603E_85C30_CTRL_5        SCORE603E_PMC_SERIAL_ADDRESS(0x200028)
+#define SCORE603E_85C30_DATA_5        SCORE603E_PMC_SERIAL_ADDRESS(0x20002c)
+#define SCORE603E_85C30_CTRL_6        SCORE603E_PMC_SERIAL_ADDRESS(0x200030)
+#define SCORE603E_85C30_DATA_6        SCORE603E_PMC_SERIAL_ADDRESS(0x200034)
+#define SCORE603E_85C30_CTRL_7        SCORE603E_PMC_SERIAL_ADDRESS(0x200038)
+#define SCORE603E_85C30_DATA_7        SCORE603E_PMC_SERIAL_ADDRESS(0x20003c)
+#define SCORE603E_85C30_CTRL_8        SCORE603E_PMC_SERIAL_ADDRESS(0x200000)
+#define SCORE603E_85C30_DATA_8        SCORE603E_PMC_SERIAL_ADDRESS(0x200004)
+#define SCORE603E_85C30_CTRL_9        SCORE603E_PMC_SERIAL_ADDRESS(0x200008)
+#define SCORE603E_85C30_DATA_9        SCORE603E_PMC_SERIAL_ADDRESS(0x20000c)
+#define SCORE603E_85C30_CTRL_10       SCORE603E_PMC_SERIAL_ADDRESS(0x200010)
+#define SCORE603E_85C30_DATA_10       SCORE603E_PMC_SERIAL_ADDRESS(0x200014)
+#define SCORE603E_85C30_CTRL_11       SCORE603E_PMC_SERIAL_ADDRESS(0x200018)
+#define SCORE603E_85C30_DATA_11       SCORE603E_PMC_SERIAL_ADDRESS(0x20001c)
 
 #define SCORE603E_PCI_IO_CFG_ADDR      0x80000cf8
 #define SCORE603E_PCI_IO_CFG_DATA      0x80000cfc
 
 #define SCORE603E_UNIVERSE_BASE        0x80030000
 #define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000
-#define SCORE603E_PCI_MEM_BASE         0xc0000000       
+#define SCORE603E_PCI_MEM_BASE         0xc0000000
 #define SCORE603E_NVRAM_BASE           0xfd100000
 #define SCORE603E_RTC_ADDRESS          ((volatile unsigned char *)0xfd180000)
 #define SCORE603E_JP1_JP2_PROM_BASE    0xfff00000
@@ -106,7 +106,7 @@ extern "C" {
 
 /*
  *  Definations for the ICM 1770 RTC chip
- */ 
+ */
     /*
      * These values are programed into a register and must not be changed.
      */
@@ -115,25 +115,25 @@ extern "C" {
 #define ICM1770_CRYSTAL_FREQ_2M       0x02
 #define ICM1770_CRYSTAL_FREQ_4M       0x03
 
-#define SCORE_RTC_FREQUENCY           ICM1770_CRYSTAL_FREQ_32K 
+#define SCORE_RTC_FREQUENCY           ICM1770_CRYSTAL_FREQ_32K
 
 /*
  *  Z85C30 Definations for the 423 interface.
  */
 #define SCORE603E_85C30_0_CLOCK     14745600  /* 10,000,000 ?10->14.5 */
-#define SCORE603E_85C30_0_CLOCK_X       16 
+#define SCORE603E_85C30_0_CLOCK_X       16
 
 /*
  *  Z85C30 Definations for the 422 interface.
  */
 #define SCORE603E_85C30_1_CLOCK     16000000  /* 10,000,000 ?10->14.5 */
-#define SCORE603E_85C30_1_CLOCK_X       16    
+#define SCORE603E_85C30_1_CLOCK_X       16
 
 /*
  *  Z85C30 Definations for the PMC serial chips
  */
 #define SCORE603E_85C30_PMC_CLOCK     16000000  /* 10,000,000 ?10->14.5 */
-#define SCORE603E_85C30_PMC_CLOCK_X       16    
+#define SCORE603E_85C30_PMC_CLOCK_X       16
 
 #define SCORE603E_85C30_2_CLOCK       SCORE603E_85C30_PMC_CLOCK
 #define SCORE603E_85C30_3_CLOCK       SCORE603E_85C30_PMC_CLOCK
@@ -156,7 +156,7 @@ extern "C" {
 #define SCORE603E_FPGA_IRQ_INPUT    ((volatile uint16_t*)0xfd00004c)
 
 /*
- * The PMC status word is at the PMC base address 
+ * The PMC status word is at the PMC base address
  */
 #define SCORE603E_PMC_STATUS_ADDRESS  (SCORE603E_PMC_SERIAL_ADDRESS (0))
 #define Is_PMC_85C30_4_IRQ( _status ) (_status & 0x80)    /* SCC 422-1 */
@@ -167,17 +167,17 @@ extern "C" {
 #define SCORE603E_PMC_CONTROL_ADDRESS    SCORE603E_PMC_SERIAL_ADDRESS(0x100000)
 #define SCORE603E_PMC_SCC_232_LOOPBACK (_word) (_word|0x20)
 
-#define PMC_SET_232_LOOPBACK(_word)   (_word | 0x02)   
-#define PMC_CLEAR_232_LOOPBACK(_word) (_word & 0xfd)   
-#define PMC_SET_422_LOOPBACK(_word)   (_word | 0x01)   
-#define PMC_CLEAR_422_LOOPBACK(_word) (_word & 0xfe) 
-  
+#define PMC_SET_232_LOOPBACK(_word)   (_word | 0x02)
+#define PMC_CLEAR_232_LOOPBACK(_word) (_word & 0xfd)
+#define PMC_SET_422_LOOPBACK(_word)   (_word | 0x01)
+#define PMC_CLEAR_422_LOOPBACK(_word) (_word & 0xfe)
+
 
 /*
  *  Score603e Interupt Definations.
  */
 
-/* 
+/*
  * First Score Unique IRQ
  */
 #define Score_IRQ_First ( PPC_IRQ_LAST +  1 )
@@ -202,25 +202,25 @@ extern "C" {
 #define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
 #define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
 
-#define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00    
-#define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01    
-#define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02    
-#define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03    
-#define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04    
-#define SCORE603E_RTC_IRQ              SCORE603E_IRQ05    
-#define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06    
-#define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07    
-#define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08    
-#define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09     
-#define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10      
-#define SCORE603E_1553_IRQ             SCORE603E_IRQ11    
-#define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12    
-#define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13    
-#define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14    
-#define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15    
-
-/* 
- * The Score FPGA maps all interrupts comming from the PMC card to 
+#define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
+#define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
+#define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
+#define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
+#define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
+#define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
+#define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
+#define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
+#define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
+#define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
+#define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
+#define SCORE603E_1553_IRQ             SCORE603E_IRQ11
+#define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
+#define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
+#define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
+#define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
+
+/*
+ * The Score FPGA maps all interrupts comming from the PMC card to
  * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
  * read to indicate which interrupt was chained to the FPGA.
  */
@@ -239,7 +239,7 @@ extern "C" {
 
 #define MAX_BOARD_IRQS                 SCORE603E_IRQ19
 
- 
+
 /*
  *  BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer
  *  driver.
@@ -250,7 +250,7 @@ extern "C" {
 #define BSP_TIMER_LEAST_VALID    1  /* Don't trust a value lower than this */
 
 /*
- *  Convert decrement value to tenths of microsecnds (used by 
+ *  Convert decrement value to tenths of microsecnds (used by
  *  shared timer driver).
  *
  *    + CPU has a 66.67 Mhz bus,
diff --git a/c/src/lib/libbsp/powerpc/score603e/start/start.S b/c/src/lib/libbsp/powerpc/score603e/start/start.S
index 24b511282f..ae5fac1808 100644
--- a/c/src/lib/libbsp/powerpc/score603e/start/start.S
+++ b/c/src/lib/libbsp/powerpc/score603e/start/start.S
@@ -66,7 +66,7 @@ past_constants:
 	mr      r4,r5
 	ori     r4,r4,0x0000            /* 0x2030  */
         mtmsr   r4
-	
+
         /* The first generation board needed initialization here but the */
         /* second does not. */
 
diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c b/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c
index 59d7168b42..e1b0091355 100644
--- a/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c
@@ -7,7 +7,7 @@
  *  the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  $Id: 
+ *  $Id:
  */
 
 #include <bsp.h>
@@ -63,7 +63,7 @@ uint16_t         get_irq_mask()
   return value;
 }
 
-void unmask_irq( 
+void unmask_irq(
   uint16_t         irq_idx
 )
 {
@@ -85,7 +85,7 @@ void unmask_irq(
   }
 #endif
 
-  value &= (~(0x1 << mask_idx)); 
+  value &= (~(0x1 << mask_idx));
   set_irq_mask( value );
 }
 
@@ -111,7 +111,7 @@ void init_irq_data_register()
 
 uint16_t         read_and_clear_PMC_irq(
   uint16_t            irq
-) 
+)
 {
   uint16_t            status_word = irq;
 
@@ -155,7 +155,7 @@ uint16_t         read_and_clear_irq()
   irq = (*SCORE603E_FPGA_VECT_DATA);
 
   if ((irq & 0xffff0) != 0x10) {
-    DEBUG_puts( "ERROR:: no irq data\n");    
+    DEBUG_puts( "ERROR:: no irq data\n");
     return (irq | 0x80);
   }
 
diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c b/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
index e5d1fcce1b..3f016c3612 100644
--- a/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
@@ -1,6 +1,6 @@
 /*  Hwr_init.c
  *
- *  $Id: 
+ *  $Id:
  */
 
 #include <bsp.h>
@@ -75,22 +75,22 @@ typedef struct {
 void init_RTC()
 {
   volatile Harris_RTC *the_RTC;
-  
+
   the_RTC = (volatile Harris_RTC *)SCORE603E_RTC_ADDRESS;
 
   the_RTC->command_register = 0x0;
 }
 
 void init_PCI()
-{  
+{
 #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
   uint32_t         value;
 
  /*
-  * NOTE:  Accessing any memory location not mapped by the BAT 
-  * registers will cause a TLB miss exception.   
-  * Set the DBAT1 to be configured for 256M of PCI MEM 
-  * at 0xC0000000 with Write-through and Guarded Attributed and 
+  * NOTE:  Accessing any memory location not mapped by the BAT
+  * registers will cause a TLB miss exception.
+  * Set the DBAT1 to be configured for 256M of PCI MEM
+  * at 0xC0000000 with Write-through and Guarded Attributed and
   * read/write access allowed
   */
 
@@ -118,10 +118,10 @@ void init_PCI()
 
 #if (0)
  /*
-  * NOTE:  Accessing any memory location not mapped by the BAT 
-  * registers will cause a TLB miss exception.   
-  * Set the DBAT3 to be configured for 256M of PCI MEM 
-  * at 0xC0000000 with Write-through and Guarded Attributed and 
+  * NOTE:  Accessing any memory location not mapped by the BAT
+  * registers will cause a TLB miss exception.
+  * Set the DBAT3 to be configured for 256M of PCI MEM
+  * at 0xC0000000 with Write-through and Guarded Attributed and
   * read/write access allowed
   */
 
@@ -192,7 +192,7 @@ void data_cache_enable ()
   uint32_t         value;
 
   /*
-   * enable data cache 
+   * enable data cache
    */
 
   PPC_Get_HID0( value );
diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c b/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
index 11603b0c95..b3b2c22607 100644
--- a/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
@@ -12,7 +12,7 @@
  *  the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  $Id: 
+ *  $Id:
  */
 
 #include <string.h>
@@ -25,7 +25,7 @@
  *  The original table from the application and our copy of it with
  *  some changes.
  */
- 
+
 extern rtems_configuration_table  Configuration;
 rtems_configuration_table         BSP_Configuration;
 rtems_cpu_table                   Cpu_table;
@@ -71,7 +71,7 @@ void bsp_pretasking_hook(void)
  *  bsp_predriver_hook
  *
  *  Before drivers are setup initialize interupt vectors.
- */ 
+ */
 
 void init_RTC();
 void initialize_PMC();
@@ -88,13 +88,13 @@ void bsp_predriver_hook(void)
   initialize_PMC();
 #endif
 
- /* 
+ /*
   * Initialize Bsp General purpose vector table.
   */
  initialize_external_exception_vector();
 
 #if (0)
-  /* 
+  /*
    * XXX - Modify this to write a 48000000 (loop to self) command
    *       to each interrupt location.  This is better for debug.
    */
@@ -167,7 +167,7 @@ void initialize_PMC() {
  *
  *  Standard post driver hook plus some BSP specific stuff.
  */
- 
+
 void SCORE603e_bsp_postdriver_hook(void)
 {
   extern void Init_EE_mask_init(void);
@@ -205,27 +205,27 @@ void bsp_start( void )
   );
 
   /*
-   *  There are multiple ROM monitors available for this board.  
+   *  There are multiple ROM monitors available for this board.
    */
 #if (SCORE603E_USE_SDS)
 
-  /* 
+  /*
    * Write instruction for Unconditional Branch to ROM vector.
    */
-    
-   Code = 0x4bf00002;          
-   for (Address = 0x100; Address <= 0xe00; Address += 0x100) { 
+
+   Code = 0x4bf00002;
+   for (Address = 0x100; Address <= 0xe00; Address += 0x100) {
      A_Vector = (uint32_t*)Address;
      Code = 0x4bf00002 + Address;
      *A_Vector = Code;
    }
-    
-   for (Address = 0x1000; Address <= 0x1400; Address += 0x100) { 
+
+   for (Address = 0x1000; Address <= 0x1400; Address += 0x100) {
      A_Vector = (uint32_t*)Address;
      Code = 0x4bf00002 + Address;
      *A_Vector = Code;
    }
-   
+
   Cpu_table.exceptions_in_RAM = TRUE;
   msr_value = 0x2030;
 
@@ -263,7 +263,7 @@ void bsp_start( void )
    *  not malloc'ed.  It is just "pulled from the air".
    */
 
-  work_space_start = 
+  work_space_start =
     (unsigned char *)&RAM_END - BSP_Configuration.work_space_size;
 
   if ( work_space_start <= (unsigned char *)&end ) {
@@ -287,7 +287,7 @@ void bsp_start( void )
   Cpu_table.idle_task_stack_size = (3 * STACK_MINIMUM_SIZE);
 
 #if ( PPC_USE_DATA_CACHE )
-  instruction_cache_enable (); 
+  instruction_cache_enable ();
   data_cache_enable ();
 #endif
 }
diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c b/c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c
index a97444c865..b1e59ed579 100644
--- a/c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c
@@ -20,8 +20,8 @@
 #include <stdio.h> /* for sprintf */
 
 
-/* 
- * Proto types for this file                                          
+/*
+ * Proto types for this file
  */
 
 rtems_isr external_exception_ISR (
@@ -31,8 +31,8 @@ rtems_isr external_exception_ISR (
 #define   NUM_LIRQ_HANDLERS   20
 #define   NUM_LIRQ            ( MAX_BOARD_IRQS - PPC_IRQ_LAST )
 
-/* 
- * Structure to for one of possible multiple interrupt handlers for 
+/*
+ * Structure to for one of possible multiple interrupt handlers for
  * a given interrupt.
  */
 typedef struct
@@ -47,7 +47,7 @@ typedef struct
  *        handlers at a later time.
  */
   EE_ISR_Type       ISR_Nodes [NUM_LIRQ_HANDLERS];
-  uint16_t          Nodes_Used; 
+  uint16_t          Nodes_Used;
   Chain_Control     ISR_Array  [NUM_LIRQ];
 
 /* XXX */
@@ -67,14 +67,14 @@ void initialize_external_exception_vector ()
 
   for (i=0; i <NUM_LIRQ; i++)
     Chain_Initialize_empty( &ISR_Array[i] );
-  
+
   init_irq_data_register();
-   
-  /*  
-   * Install external_exception_ISR () as the handler for 
+
+  /*
+   * Install external_exception_ISR () as the handler for
    *  the General Purpose Interrupt.
    */
-  status = rtems_interrupt_catch( external_exception_ISR, 
+  status = rtems_interrupt_catch( external_exception_ISR,
            PPC_IRQ_EXTERNAL, (rtems_isr_entry *) &previous_isr );
 }
 
@@ -83,7 +83,7 @@ void Init_EE_mask_init() {
 }
 
 /*
- *  This routine installs one of multiple ISRs for the general purpose 
+ *  This routine installs one of multiple ISRs for the general purpose
  *  inerrupt.
  */
 rtems_isr_entry  set_EE_vector(
@@ -93,9 +93,9 @@ rtems_isr_entry  set_EE_vector(
 {
   uint16_t         vec_idx  = vector - Score_IRQ_First;
   uint32_t         index;
-  
+
   assert  (Nodes_Used < NUM_LIRQ_HANDLERS);
-   
+
   /*
    *  If we have already installed this handler for this vector, then
    *  just reset it.
@@ -110,15 +110,15 @@ rtems_isr_entry  set_EE_vector(
   /*
    *  Doing things in this order makes them more atomic
    */
-  
-  Nodes_Used++; 
+
+  Nodes_Used++;
 
   index = Nodes_Used - 1;
 
   ISR_Nodes[index].handler = handler;
   ISR_Nodes[index].vector  = vector;
 
-  /* printf( "Vector Index: %04x, Vector: %d (%x)\n", 
+  /* printf( "Vector Index: %04x, Vector: %d (%x)\n",
           vec_idx, vector, vector); */
 
   Chain_Append( &ISR_Array[vec_idx], &ISR_Nodes[index].Node );
@@ -131,13 +131,13 @@ rtems_isr_entry  set_EE_vector(
   return NULL;
 }
 
-/* 
+/*
  * This interrupt service routine is called for an External Exception.
  */
 rtems_isr external_exception_ISR (
   rtems_vector_number   vector             /* IN  */
 )
-{ 
+{
  uint16_t            index;
  EE_ISR_Type         *node;
  uint16_t            value;
@@ -167,7 +167,7 @@ rtems_isr external_exception_ISR (
         node = (EE_ISR_Type *)(ISR_Array[ index ].first);
 
         if ( _Chain_Is_tail( &ISR_Array[ index ], (void *)node ) ) {
-          sprintf(err_msg,"ERROR:: check %d interrupt %02d has no isr\n", 
+          sprintf(err_msg,"ERROR:: check %d interrupt %02d has no isr\n",
                   check_irq, index);
           DEBUG_puts( err_msg);
           value = get_irq_mask();
@@ -183,7 +183,7 @@ rtems_isr external_exception_ISR (
   }
   else
 #endif
-  { 
+  {
     node = (EE_ISR_Type *)(ISR_Array[ index ].first);
     if ( _Chain_Is_tail( &ISR_Array[ index ], (void *)node ) ) {
       sprintf(err_msg,"ERROR:: interrupt %02x has no isr\n", index);
diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/setvec.c b/c/src/lib/libbsp/powerpc/score603e/startup/setvec.c
index 24bb18922e..b10521f05e 100644
--- a/c/src/lib/libbsp/powerpc/score603e/startup/setvec.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/setvec.c
@@ -36,7 +36,7 @@
  *  the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  $Id: 
+ *  $Id:
  */
 
 #include <rtems.h>
@@ -44,8 +44,8 @@
 
 
 /*
- *  This routine installs vector number vector. 
- *  
+ *  This routine installs vector number vector.
+ *
  */
 rtems_isr_entry set_vector(                    /* returns old vector */
   rtems_isr_entry     handler,                  /* isr routine        */
@@ -57,7 +57,7 @@ rtems_isr_entry set_vector(                    /* returns old vector */
   rtems_status_code status;
 
 
-  /* 
+  /*
    * vectors greater than PPC603e_IRQ_LAST are handled by the General purpose
    * interupt handler.
    */
diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/spurious.c b/c/src/lib/libbsp/powerpc/score603e/startup/spurious.c
index a3b87f600b..59d5ba2949 100644
--- a/c/src/lib/libbsp/powerpc/score603e/startup/spurious.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/spurious.c
@@ -1,11 +1,11 @@
 /*
  *  Score603e Spurious Trap Handler
  *
- *  This is just enough of a trap handler to let us know what 
+ *  This is just enough of a trap handler to let us know what
  *  the likely source of the trap was.
  *
- *  Developed as part of the port of RTEMS to the ERC32 implementation 
- *  of the SPARC by On-Line Applications Research Corporation (OAR) 
+ *  Developed as part of the port of RTEMS to the ERC32 implementation
+ *  of the SPARC by On-Line Applications Research Corporation (OAR)
  *  under contract to the European Space Agency (ESA).
  *
  *  COPYRIGHT (c) 1995. European Space Agency.
@@ -82,9 +82,9 @@ rtems_isr bsp_spurious_handler(
       break;
 
 #if defined(ppc403)
-#error "Please fill in names. "                                  
+#error "Please fill in names. "
     case PPC_IRQ_CRIT :
-      DEBUG_puts( "\nTrap: Critical Error ");     
+      DEBUG_puts( "\nTrap: Critical Error ");
       break;
     case PPC_IRQ_PIT:
       DEBUG_puts( "\nTrap: 0x01000" );
@@ -100,13 +100,13 @@ rtems_isr bsp_spurious_handler(
       break;
 
 #elif defined(ppc601)
-#error "Please fill in names. "                                  
+#error "Please fill in names. "
     case PPC_IRQ_TRACE    :
       DEBUG_puts( "\nTrap: 0x02000" );
       break;
 
 #elif defined(ppc603)
-#error "Please fill in names. "                                  
+#error "Please fill in names. "
     case PPC_IRQ_TRANS_MISS :
       DEBUG_puts( "\nTrap: 0x1000" );
       break;
@@ -141,7 +141,7 @@ rtems_isr bsp_spurious_handler(
       break;
 
 #elif defined(mpc604)
-#error "Please fill in names. "                                  
+#error "Please fill in names. "
     case PPC_IRQ_ADDR_BRK:
       DEBUG_puts( "0x1300" );
       break;
@@ -179,7 +179,7 @@ void bsp_spurious_initialize()
       ;
       /* set_vector( bsp_stub_handler, trap, 1 ); */
     else
-      set_vector( bsp_spurious_handler, trap,  1 ); 
+      set_vector( bsp_spurious_handler, trap,  1 );
   }
 }
 
diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c b/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c
index 441c98a224..8e2f334881 100644
--- a/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c
@@ -9,7 +9,7 @@
  *  the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  $Id: 
+ *  $Id:
  */
 
 #include <rtems.h>
diff --git a/c/src/lib/libbsp/powerpc/score603e/timer/timer.c b/c/src/lib/libbsp/powerpc/score603e/timer/timer.c
index 6e7548d909..81a6b18de7 100644
--- a/c/src/lib/libbsp/powerpc/score603e/timer/timer.c
+++ b/c/src/lib/libbsp/powerpc/score603e/timer/timer.c
@@ -26,7 +26,7 @@ uint64_t         Timer_driver_Start_time;
 rtems_boolean Timer_driver_Find_average_overhead;
 
 /*
- * Timer_initialize 
+ * Timer_initialize
  */
 
 void Timer_initialize()
diff --git a/c/src/lib/libbsp/powerpc/score603e/tod/tod.c b/c/src/lib/libbsp/powerpc/score603e/tod/tod.c
index 234d46243b..a21140105d 100644
--- a/c/src/lib/libbsp/powerpc/score603e/tod/tod.c
+++ b/c/src/lib/libbsp/powerpc/score603e/tod/tod.c
@@ -1,14 +1,14 @@
 /*
- * Real Time Clock (Harris ICM7170) for RTEMS 
+ * Real Time Clock (Harris ICM7170) for RTEMS
  *
- *  This part is found on the second generation of this board. 
+ *  This part is found on the second generation of this board.
  *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
  *  $Id$
- */ 
+ */
 
 #include <rtems.h>
 #include <tod.h>
@@ -74,7 +74,7 @@ int checkRealTime()
 }
 
 /*
- *  These routines are ICM7170 should be in 
+ *  These routines are ICM7170 should be in
  *  a separate support library.
  * XXX Make static
  */
@@ -113,13 +113,13 @@ void ICM7170_GetTOD(
   if (init ) {
     ICM7170_SetField( imc1770_regs,  0x11, (0x0c | icm1770_freq) );
     init = FALSE;
-  } 
+  }
 
   /* Latch times */
   /* rtc_tod->ticks  = */
-  
+
   usec = ICM7170_GetField( imc1770_regs, 0x00 );
-   
+
   year = ICM7170_GetField( imc1770_regs, 0x06 );
   if ( year >= 88 )
     year += 1900;
@@ -151,7 +151,7 @@ void ICM7170_SetTOD(
     year -= 2000;
   else
     year -= 1900;
-  
+
   ICM7170_SetField( imc1770_regs, 0x11, (0x04 |icm1770_freq ) );
 
   ICM7170_SetField( imc1770_regs, 0x06, year );
@@ -162,8 +162,8 @@ void ICM7170_SetTOD(
   ICM7170_SetField( imc1770_regs, 0x03, rtc_tod->second );
 
   /*
-   * I don't know which day of week is 
-   *  
+   * I don't know which day of week is
+   *
    */
   ICM7170_SetField( imc1770_regs, 0x07, 1 );
 
diff --git a/c/src/lib/libbsp/powerpc/score603e/vectors/vectors.S b/c/src/lib/libbsp/powerpc/score603e/vectors/vectors.S
index 14ed3c50fe..fc6a0f1e37 100644
--- a/c/src/lib/libbsp/powerpc/score603e/vectors/vectors.S
+++ b/c/src/lib/libbsp/powerpc/score603e/vectors/vectors.S
@@ -1,6 +1,6 @@
 /*  vectors.s	1.1 - 95/12/04
  *
- *  This file contains the assembly code for the PowerPC 
+ *  This file contains the assembly code for the PowerPC
  *  interrupt veneers for RTEMS.
  *
  */
@@ -64,101 +64,101 @@
 
 	PUBLIC_VAR (__vectors)
 SYM (__vectors):
-	
+
   /* Decrementer interrupt */
-	.org    reset_vector - file_base    
-	ba  0x00100  
-	ba  0xfff00100  
-	ba  0xfff00100  
+	.org    reset_vector - file_base
+	ba  0x00100
+	ba  0xfff00100
+	ba  0xfff00100
 	ba  0xfff00100
-	  
-	.org    mach_vector - file_base  
+
+	.org    mach_vector - file_base
 	ba  0x00200
 	ba  0xfff00200
 	ba  0xfff00200
 	ba  0xfff00200
-	
-	.org    prot_vector - file_base  
+
+	.org    prot_vector - file_base
 	ba  0x00300
 	ba  0xfff00300
 	ba  0xfff00300
 	ba  0xfff00300
-	
-	.org    isi_vector - file_base  
+
+	.org    isi_vector - file_base
 	ba  0x00400
 	ba  0xfff00400
 	ba  0xfff00400
 	ba  0xfff00400
-		
-	.org    ext_vector - file_base    
-	ba  0x0500  
-	ba  0xfff00500  
-	ba  0xfff00500  
-	ba  0xfff00500  
-	
-	.org    align_vector - file_base    
-	ba  0x00600  
-	ba  0xfff00600  
-	ba  0xfff00600  
-	ba  0xfff00600  
-	
-	.org    prog_vector - file_base    
-	ba  0x00700  
-	ba  0xfff00700  
-	ba  0xfff00700  
-	ba  0xfff00700  
-
-	.org    float_vector - file_base  
+
+	.org    ext_vector - file_base
+	ba  0x0500
+	ba  0xfff00500
+	ba  0xfff00500
+	ba  0xfff00500
+
+	.org    align_vector - file_base
+	ba  0x00600
+	ba  0xfff00600
+	ba  0xfff00600
+	ba  0xfff00600
+
+	.org    prog_vector - file_base
+	ba  0x00700
+	ba  0xfff00700
+	ba  0xfff00700
+	ba  0xfff00700
+
+	.org    float_vector - file_base
 	ba  0x00800
 	ba  0xfff00800
 	ba  0xfff00800
 	ba  0xfff00800
 
-	.org    dec_vector - file_base  
+	.org    dec_vector - file_base
 	rfi
 	ba  0xfff00900
 	ba  0xfff00900
 	ba  0xfff00900
-	
-	.org    sys_vector - file_base    
-	ba  0x0c00  
-	ba  0xfff00C00  
-	ba  0xfff00C00  
-	ba  0xfff00C00  
-		
-	.org    trace_vector - file_base  
-	ba  0x0d00  
-	ba  0xfff00d00  
-	ba  0xfff00d00  
-	ba  0xfff00d00  
-	
-	.org    itm_vector - file_base    
-	ba  0x01000  
-	ba  0xfff01000  
-	ba  0xfff01000  
-	ba  0xfff01000  
-	
-	.org    dltm_vector - file_base    
-	ba  0x01100  
-	ba  0xfff01100  
-	ba  0xfff01100  
-	ba  0xfff01100  
-	
-	.org    dstm_vector - file_base    
-	ba  0x1200  
-	ba  0xfff01200  
-	ba  0xfff01200  
-	ba  0xfff01200  
-	
-	.org    addr_vector - file_base    
-	ba  0x1300  
-	ba  0xfff01300  
-	ba  0xfff01300  
-	ba  0xfff01300  
-	
-	.org    sysmgmt_vector - file_base    
-	ba  0x1400  
-	ba  0xfff01400  
-	ba  0xfff01400  
-	ba  0xfff01400  
+
+	.org    sys_vector - file_base
+	ba  0x0c00
+	ba  0xfff00C00
+	ba  0xfff00C00
+	ba  0xfff00C00
+
+	.org    trace_vector - file_base
+	ba  0x0d00
+	ba  0xfff00d00
+	ba  0xfff00d00
+	ba  0xfff00d00
+
+	.org    itm_vector - file_base
+	ba  0x01000
+	ba  0xfff01000
+	ba  0xfff01000
+	ba  0xfff01000
+
+	.org    dltm_vector - file_base
+	ba  0x01100
+	ba  0xfff01100
+	ba  0xfff01100
+	ba  0xfff01100
+
+	.org    dstm_vector - file_base
+	ba  0x1200
+	ba  0xfff01200
+	ba  0xfff01200
+	ba  0xfff01200
+
+	.org    addr_vector - file_base
+	ba  0x1300
+	ba  0xfff01300
+	ba  0xfff01300
+	ba  0xfff01300
+
+	.org    sysmgmt_vector - file_base
+	ba  0x1400
+	ba  0xfff01400
+	ba  0xfff01400
+	ba  0xfff01400
 #endif