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* bsps/powerpc: Move exceptions support to bspsSebastian Huber2018-03-191-1114/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* powerpc: AltiVec and FPU context supportSebastian Huber2015-01-131-2/+245
| | | | | | | | | | | Add AltiVec and FPU support to the Context_Control in case we use the e6500 multilib. Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add non-volatile AltiVec and FPU context to Context_Control. Add save/restore of non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore of volatile AltiVec and FPU context to the exception code. Adjust data cache optimizations for the new context and cache line size.
* Revert "bsps/powerpc: Fix potential relocation truncation"Sebastian Huber2014-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d9ff8b3e687a0ec56cac6463ba01ba7775eccd41. It is not that simple: https://sourceware.org/ml/binutils/2014-06/msg00062.html On Fri, Jun 06, 2014 at 01:31:48PM +0200, Sebastian Huber wrote: > On 2014-06-06 13:23, Sebastian Huber wrote: > >Ok, so this "cmplwi cr0, rX, ppc_exc_lock_std@sdarel" is illegal, > >since > >ppc_exc_lock_std@sdarel is signed and the immediate is unsigned > >16-bit? The > >assembler doesn't issue a warning about this. > > > >Exists there a way to rescue this cmplwi hack without relaxing the > >overflow > >checks? > > Hm, sorry, it was surprisingly simple. This works: > > "cmplwi cr0, rX, ppc_exc_lock_std@sdarel@l" > > I was not aware that you can add several @ in a row. That is the wrong thing to use here. sdarel@l translates to a VLE reloc which applies to a split 16-bit field in VLE insns. You want cmpwi cr0, rX, ppc_exc_lock_std@sdarel to properly compare a 16-bit signed number from sym@sdarel. Note that the assembler does error if you write something like cmplwi 3,-30000 or cmpwi 3,40000 so what the linker is now doing is extending this behaviour to link time.
* bsps/powerpc: Fix potential relocation truncationSebastian Huber2014-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | See also https://sourceware.org/ml/binutils/2014-06/msg00059.html On Fri, Jun 06, 2014 at 11:01:10AM +0200, Sebastian Huber wrote: > I performed a git bisect and found this: > > 93d1b056cb396d6468781fe0e40dd769891bed32 is the first bad commit > commit 93d1b056cb396d6468781fe0e40dd769891bed32 > Author: Alan Modra <amodra@gmail.com> > Date: Tue May 20 11:42:42 2014 +0930 > > Rewrite ppc32 backend .sdata and .sdata2 handling Hmm, I'm surprised that your git bisect found this patch. Was _SDA_BASE_ set differently before this? > 0x00000000000dfc00 _SDA_BASE_ > 0x00000000000d7f78 ppc_exc_lock_std > 4b8: 28 05 00 00 cmplwi r5,0 > 4ba: R_PPC_SDAREL16 ppc_exc_lock_std ppc_exc_lock_std@sdarel will be calculating 0xd7f78 - 0xdfc00 which is 0xf...fff8378, and that falls foul of commit 86c9573369616e7437481b6e5533aef3a435cdcf Author: Alan Modra <amodra@gmail.com> Date: Sat Mar 8 13:05:06 2014 +1030 Better overflow checking for powerpc32 relocations cmplwi has an *unsigned* 16-bit field, and we now check the overflow properly. I wonder how many more of these we'll hit, and whether the uproar will be enough that I'll be forced to relax the checks?
* bsps/powerpc: Per-CPU thread dispatch disableSebastian Huber2013-08-091-10/+11
| | | | Interrupt support for per-CPU thread dispatch disable level.
* bsps/powerpc: Add PPC_EXC_CONFIG_BOOKE_ONLYSebastian Huber2012-12-031-0/+20
| | | | | | | In combination with the PPC_EXC_CONFIG_USE_FIXED_HANDLER option this removes all dependencies on valid read-write data. The exception handling must be statically configured and all components reside in read-only sections.
* bsps/powerpc: Add PPC_EXC_CONFIG_USE_FIXED_HANDLERSebastian Huber2012-12-031-1/+10
| | | | | | | | | In case a BSP enables this option, then fixed high level exception handler will be used. For normal asynchronous exceptions this is bsp_interrupt_dispatch() and for other exceptions this is the handler from the read-only ppc_exc_handler_table. The global handler is C_exception_handler(). This avoids some dependencies on valid read-write data.
* 2011-07-21 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-07-211-0/+40
| | | | | | | | | | | | PR 1799/bsps * new-exceptions/bspsupport/ppc_exc_async_normal.S: New file. * new-exceptions/cpu.c, new-exceptions/cpu_asm.S, new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/ppc_exc_global_handler.c, new-exceptions/bspsupport/ppc_exc_prologue.c, new-exceptions/bspsupport/vectors.h: Added support for SPE. * configure.ac, preinstall.am, Makefile.am: Added support for qoriq BSPs.
* 2011-01-31 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-01-311-5/+15
| | | | | | | | | * new-exceptions/bspsupport/ppc_exc.S, new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/ppc_exc_naked.S, new-exceptions/bspsupport/ppc_exc_prologue.c: Branch targets are now global for all minimal prologues. Generate branch instruction in minimal prologues.
* 2010-06-29 Jennifer Averett <Jennifer.Averett@OARcorp.com>Jennifer Averett2010-06-291-0/+1
| | | | | * new-exceptions/bspsupport/ppc_exc_asm_macros.h: Added include of bspopts to resolve compilation problem.
* 2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-06-291-4/+6
| | | | | | | | | | | PR 1573/cpukit * mpc5xx/irq/irq.c, mpc5xx/irq/irq_asm.S, new-exceptions/bspsupport/ppc_exc.S, new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/ppc_exc_hdl.c: Add a per cpu data structure which contains the information required by RTEMS for each CPU core. This encapsulates information such as thread executing, heir, idle and dispatch needed.
* 2009-12-01 Till Straumann <strauman@slac.stanford.edu>Till Straumann2009-12-021-0/+28
| | | | | | | | | * new-exceptions/cpu.c, new-exceptions/cpu_asm.S, new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/ppc_exc_initialize.c, new-exceptions/bspsupport/vectors.h: Added AltiVec support (save/restore volatile vregs across exceptions).
* Whitespace removal.Ralf Corsepius2009-11-301-10/+10
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* Update for exception support changes.Thomas Doerfler2009-10-231-4/+1
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* 2008-07-16 Till Straumann <strauman@slac.stanford.edu>Till Straumann2008-07-161-10/+26
| | | | | | | | | * new-exceptions/bspsupport/ppc_exc_asm_macros.h: Added a test to TEST_LOCK_crit so that a context switch is always prevented if MSR_CE is not set in the interrupt mask. (Support mode where the user wants to leave MSR_CE always enabled but abstains from calling OS primitives from the exception handler.)
* adapted powerpc exception codeThomas Doerfler2008-07-111-333/+581
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* 2008-07-10 Till Straumann <strauman@slac.stanford.edu>Till Straumann2008-07-101-7/+41
| | | | | | | | | | | | | | | | | | | | | | | | | * new-exceptions/bspsupport/ppc_exc_asm_macros.S, new-exceptions/bspsupport/ppc_exc_bspsupp.h, new-exceptions/bspsupport/ppc_exc_hdl.c, new-exceptions/bspsupport/vectors_init.c: fixed and enabled stack-switching algorithm which figures out if we already run on the ISR stack rather than relying on the _ISR_Nest_level. Added 'ppc_exc_crit_always_enabled' variable which defines the semantics of critical interrupts. Added a test to TEST_LOCK_crit so that calling ppc_exc_wrapup() (and possibly the dispatcher) is always skipped if the BSP/user wants to leave critical interrupts always enabled (at the expense of having no OS support). changed TEST_LOCK_mchk so that asynchronous machine-check handlers never call ppc_exc_wrapup() (and the dispatcher). We don't want to disable MSR_ME ever (to avoid checkstops) and hence asynchronous MEs must not use OS services anyways. added and commented new variables 'ppc_exc_intr_stack_size' 'ppc_exc_crit_always_enabled'.
* 2008-03-13 Till Straumann <strauman@slac.stanford.edu>Till Straumann2008-03-131-24/+211
| | | | | | | | | | | | | | | * new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/ppc_exc.S, new-exceptions/bspsupport/README, new-exceptions/bspsupport/ppc_exc_hdl.c: Thomas Doerfler clarified (thanks!) that raising an exception and executing the 1st instruction is not an atomical operation. I added a fix to the code that checks if a lower-priority interrupt is under way: we now not only test if the 'lock' variable was set but also check if the interrupted PC points to the 'write lock' instruction. Added more comments and updated README.
* 2008-03-11 Till Straumann <strauman@slac.stanford.edu>Till Straumann2008-03-121-1/+1
| | | | | | * new-exceptions/bspsupport/ppc_exc_asm_macros.h: bugfix; need to crand not cror when testing lower priority locks during machine-check handling.
* 2008-03-05 Till Straumann <strauman@slac.stanford.edu>Till Straumann2008-03-061-1/+1
| | | | | * new-exceptions/bspsupport/ppc_exc_asm_macros.h: bugfix; need to andc with irq mask when disabling interrupts.
* 2007-12-08 Till Straumann <strauman@slac.stanford.edu>Till Straumann2007-12-081-0/+278
* new-exceptions/bspsupport/, new-exceptions/bspsupport/ppc_exc.S, new-exceptions/bspsupport/ppc_exc_test.c, new-exceptions/bspsupport/vectors.h, new-exceptions/bspsupport/vectors_init.c, new-exceptions/bspsupport/irq.c, new-exceptions/bspsupport/ppc_exc_bspsupp.h, new-exceptions/bspsupport/ppc_exc_hdl.c, new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/nested_irq_test.c: New files. Added 'middleware' code for helping BSPs implement exception and interrupt handling and implementing the 'new' RTEMS IRQ API (which I personally dislike).
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