diff options
author | Till Straumann <strauman@slac.stanford.edu> | 2009-12-02 01:41:57 +0000 |
---|---|---|
committer | Till Straumann <strauman@slac.stanford.edu> | 2009-12-02 01:41:57 +0000 |
commit | c7f8408d31287d45ee722bd941a8057c67e7f274 (patch) | |
tree | bb52c0e1184a42a570e0bab6f109763b0d25bbab /c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h | |
parent | 2009-12-01 Till Straumann <strauman@slac.stanford.edu> (diff) | |
download | rtems-c7f8408d31287d45ee722bd941a8057c67e7f274.tar.bz2 |
2009-12-01 Till Straumann <strauman@slac.stanford.edu>
* new-exceptions/cpu.c, new-exceptions/cpu_asm.S,
new-exceptions/bspsupport/ppc_exc_asm_macros.h,
new-exceptions/bspsupport/ppc_exc_initialize.c,
new-exceptions/bspsupport/vectors.h:
Added AltiVec support (save/restore volatile vregs
across exceptions).
Diffstat (limited to 'c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h')
-rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h index 98ac23f347..28dd4aad64 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h @@ -520,6 +520,27 @@ wrap_disable_thread_dispatching_done_\_FLVR: wrap_change_msr_done_\_FLVR: +#ifdef __ALTIVEC__ + LA SCRATCH_REGISTER_0, _CPU_save_altivec_volatile + mtctr SCRATCH_REGISTER_0 + addi r3, FRAME_REGISTER, EXC_VEC_OFFSET + bctrl + /* + * Establish defaults for vrsave and vscr + */ + li SCRATCH_REGISTER_0, 0 + mtvrsave SCRATCH_REGISTER_0 + /* + * Use java/c9x mode; clear saturation bit + */ + vxor 0, 0, 0 + mtvscr 0 + /* + * Reload VECTOR_REGISTER + */ + lwz VECTOR_REGISTER, EXCEPTION_NUMBER_OFFSET(FRAME_REGISTER) +#endif + /* * Call high level exception handler */ @@ -619,6 +640,13 @@ wrap_handler_done_\_FLVR: wrap_thread_dispatching_done_\_FLVR: +#ifdef __ALTIVEC__ + LA SCRATCH_REGISTER_0, _CPU_load_altivec_volatile + mtctr SCRATCH_REGISTER_0 + addi r3, FRAME_REGISTER, EXC_VEC_OFFSET + bctrl +#endif + /* Restore MSR? */ bne CR_MSR, wrap_restore_msr_\_FLVR |