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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2010-06-29 00:39:39 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2010-06-29 00:39:39 +0000 |
| commit | 5048a0a0b81736fcb6c2bce16633db0e362fbc78 (patch) | |
| tree | 74a457c5c0b04b8804ffcf8783ed6598e014ce45 /c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h | |
| parent | 2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com> (diff) | |
| download | rtems-5048a0a0b81736fcb6c2bce16633db0e362fbc78.tar.bz2 | |
2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>
PR 1573/cpukit
* mpc5xx/irq/irq.c, mpc5xx/irq/irq_asm.S,
new-exceptions/bspsupport/ppc_exc.S,
new-exceptions/bspsupport/ppc_exc_asm_macros.h,
new-exceptions/bspsupport/ppc_exc_hdl.c: Add a per cpu data structure
which contains the information required by RTEMS for each CPU core.
This encapsulates information such as thread executing, heir, idle
and dispatch needed.
Diffstat (limited to 'c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h index 28dd4aad64..c823f51f21 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h @@ -422,11 +422,12 @@ wrap_no_save_frame_register_\_FLVR: */ /* Increment ISR nest level and thread dispatch disable level */ - lwz SCRATCH_REGISTER_0, _ISR_Nest_level@sdarel(r13) + lis SCRATCH_REGISTER_2, ISR_NEST_LEVEL@ha + lwz SCRATCH_REGISTER_0, ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2) lwz SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level@sdarel(r13) addi SCRATCH_REGISTER_0, SCRATCH_REGISTER_0, 1 addi SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, 1 - stw SCRATCH_REGISTER_0, _ISR_Nest_level@sdarel(r13) + stw SCRATCH_REGISTER_0, ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2) stw SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level@sdarel(r13) /* @@ -612,11 +613,12 @@ wrap_handler_done_\_FLVR: */ /* Decrement ISR nest level and thread dispatch disable level */ - lwz SCRATCH_REGISTER_0, _ISR_Nest_level@sdarel(r13) + lis SCRATCH_REGISTER_2, ISR_NEST_LEVEL@ha + lwz SCRATCH_REGISTER_0, ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2) lwz SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level@sdarel(r13) subi SCRATCH_REGISTER_0, SCRATCH_REGISTER_0, 1 subic. SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, 1 - stw SCRATCH_REGISTER_0, _ISR_Nest_level@sdarel(r13) + stw SCRATCH_REGISTER_0, ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2) stw SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level@sdarel(r13) /* Branch to skip thread dispatching */ |