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Simple Instruction Simulator
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Age
Files
Lines
*
Add basic DSU support present on GR712RC
HEAD
master
Sebastian Huber
2023-09-29
1
-0
/
+1
*
Add -extirq option to support simulating the UT700
Sebastian Huber
2022-10-26
1
-2
/
+3
*
Support extended interrupts
2.29
Sebastian Huber
2021-08-04
1
-0
/
+3
*
Added support for RISCV32 systems with CLINT/PLIC
Jiri Gaisler
2020-12-15
1
-2
/
+2
*
Make grlib IP cores more modular and move them to grlib.c
Jiri Gaisler
2020-12-01
1
-1017
/
+51
*
Add networking support using host tap device
2.23
Jiri Gaisler
2020-10-28
1
-7
/
+13
*
Fix incorrect operation on big-endian hosts
Jiri Gaisler
2020-02-29
1
-3
/
+3
*
Remove unused variable xcpu
Jiri Gaisler
2019-11-08
1
-5
/
+4
*
Fix typo that caused cygwin build error
Jiri Gaisler
2019-11-02
1
-1
/
+1
*
Fix C formatting with indent
Jiri Gaisler
2019-06-11
1
-107
/
+122
*
Avoid array out of bounds warning on RISC-V
Jiri Gaisler
2019-06-11
1
-1
/
+1
*
Silence warnings when compiled with LLVM
Jiri Gaisler
2019-06-11
1
-7
/
+8
*
Made L1 cache optional through --enable-l1cache
Jiri Gaisler
2019-05-28
1
-22
/
+71
*
Standalone sis - initial commit
Jiri Gaisler
2019-05-14
1
-0
/
+1151