| Commit message (Collapse) | Author | Age | Files | Lines |
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QEMU is known to fail certain tests intermittently due to clock tick
delivery issues. This defines those tests as intermittent for BSPs
intended to run on QEMU alone.
Updates #4922
Updates #4072
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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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Updates #4705
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Most BSPs which used the stubbed benachmark timer provide a CPU counter.
All BSPs provide at least a stub CPU counter. Simply use the benchmark
timer implementation using the CPU counter.
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ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
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Update #4267.
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Use the Python sorted() function to sort the "source" lists.
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This avoids a function call overhead in the interrupt dispatching.
Update #4202.
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This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64
code.
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This UART driver is now needed for BSPs other than ARM.
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Update #3818.
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