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* bsps/arm: Fix CMSIS v5 install files listChris Johns2023-07-251-3/+4
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* Update company nameSebastian Huber2023-05-201-1/+1
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* irq/arm-gicv3.h: Customize CPU Interface initSebastian Huber2022-07-121-1/+0
| | | | | | | Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1 enable registers. This fixes the build for the AArch32 target. Add BSP options which define the initial values of CPU Interface registers.
* build: Add cppflags, cflags, cxxflags to groupsSebastian Huber2022-07-041-0/+3
| | | | | | | Propagate the group defined cppflags, cflags, and cxxflags from parent groups to child items through the build item context. Update #4670.
* bsps/arm: fix installation of core_cm4.hKarel Gardas2022-06-101-0/+1
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* bsps: Add <dev/irq/arm-gicv3.h>Sebastian Huber2022-04-061-0/+1
| | | | | | | | Separate the Interrupt Manager implementation from the generic Arm GICv3 support. Move parts of the Arm GICv3 support into a new header file. This helps to support systems with a clustered structure in which multiple GICv3 instances are present. For example, two clusters of two Cortex-R52 cores where each cluster has a dedicated GICv3 instance.
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-231-0/+1
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
* bsps/arm: Set VBAR in start.SSebastian Huber2020-12-231-1/+0
| | | | | | | | | | Set the VBAR to the vector table in the start section before bsp_start_hook_0() is called to earlier handle exceptions in RTEMS. Set the VBAR to the normal vector table in start.S for the main processor. Secondary processors set it in bsp_start_hook_0(). Update #4202.
* bsps: Move zynq-uart to bsps/sharedKinsey Moore2020-12-021-2/+0
| | | | | This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to accomodate use by AArch64 BSPs.
* bsps: Break out AArch32 GICv3 supportKinsey Moore2020-10-051-4/+6
| | | | | This breaks out AArch32-specific code so that the shared GICv3 code can be reused by other architectures.
* Move ARM PL011 UART driverKinsey Moore2020-10-051-2/+0
| | | | This UART driver is now needed for BSPs other than ARM.
* build: Alternative build system based on wafSebastian Huber2020-09-141-0/+62
Update #3818.
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