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* arm: Remove use of proc_ptrSebastian Huber2018-11-123-14/+16
| | | | Update #3585.
* no_cpu: Remove use of proc_ptrSebastian Huber2018-11-122-24/+35
| | | | Update #3585.
* x86_64: Remove duplicate _CPU_Thread_Idle_body()Sebastian Huber2018-11-121-5/+0
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* m32c: Remove this targetSebastian Huber2018-11-1213-1605/+0
| | | | Update #3599.
* h8300: Remove left over filesSebastian Huber2018-11-082-61/+0
| | | | Update #2452.
* score: Remove _ISR_Dispatch()Sebastian Huber2018-11-089-136/+14
| | | | | | | | This function was only used on some m68k variants. On these m68k variants there is no need to use a global symbol. Use a local label instead. Remove _ISR_Dispatch() from the architecture-independent layer.
* score: Rename interrupt stack symbolsSebastian Huber2018-11-081-1/+1
| | | | | | | | | | | | | Rename * _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin, * _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and * _Configuration_Interrupt_stack_size in _ISR_Stack_size. Move definitions to <rtems/score/isr.h>. The new names are considerable shorter and in the right namespace. Update #3459.
* build: Include header.am in cpukit/Makefile.amSebastian Huber2018-10-1040-363/+148
| | | | | Include all cpukit/*/header.am files in cpukit/Makefile.am. This gets rid of all subtree Makefile.am and the sudirs hack.
* build: Remove local.amSebastian Huber2018-10-101-1/+0
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* build: Merge score/cpu/*/Makefile.amSebastian Huber2018-10-1019-271/+0
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* build: Remove specialized CPPFLAGSSebastian Huber2018-10-0917-20/+0
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* score: Remove CPU_PROVIDES_IDLE_THREAD_BODYSebastian Huber2018-10-0533-482/+52
| | | | | | | Remove the CPU_PROVIDES_IDLE_THREAD_BODY option to avoid unnecessary conditional compilation. Close #3539.
* Rename files to make them unique within cpukitSebastian Huber2018-10-042-1/+1
| | | | This allows to build librtemscpu.a in one rush in the future.
* Use rtems_task_exit()Sebastian Huber2018-10-021-1/+1
| | | | | Update #3530. Update #3533.
* sparc: clang AS does no accept UNIMP without argumentDaniel Hellstrom2018-09-201-1/+1
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* sparc: Remove sequence that could trigger B2BST errataDaniel Cederman2018-09-201-2/+0
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* sparc: Return to previous section type when done with .data._SPARC_CounterDaniel Cederman2018-09-201-0/+1
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* powerpc: Fix _CPU_Counter_read() for MPC860Sebastian Huber2018-09-171-0/+2
| | | | | The mpc860 is a RTEMS-specific multilib define, see GCC "gcc/config/rs6000/rtems.h".
* rtems/score/epiphany-utility.h: Fix not a prototype warningJoel Sherrill2018-08-291-1/+1
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* score/cpu/bfin/cpu.c: Fix _CPU_Thread_Idle_body() prototypeJoel Sherrill2018-08-291-1/+1
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* sparc: Restore npc when returning from the syscall_lazy_fp_switch trapDaniel Cederman2018-08-241-1/+1
| | | | | If the floating point trap occurred in a delay slot it is not certain that npc will be equal to pc + 4.
* bsps/x86_64: Add APIC timer based clock driverAmaan Cheval2018-08-131-0/+23
| | | | | | | | | The APIC timer is calibrated by running the i8254 PIT for a fraction of a second (determined by PIT_CALIBRATE_DIVIDER) and counting how many times the APIC counter has ticked. The calibration can be run multiple times (determined by APIC_TIMER_NUM_CALIBRATIONS) and averaged out. Updates #2898.
* bsps/x86_64: Add support for RTEMS interruptsAmaan Cheval2018-08-136-33/+250
| | | | Updates #2898.
* bsps/x86_64: Add paging support with 1GiB super pagesAmaan Cheval2018-08-131-0/+13
| | | | Updates #2898.
* bsps/x86_64: Reorganize header files and compile-optionsAmaan Cheval2018-08-137-22/+81
| | | | Updates #2898.
* score: Remove CPU_PARTITION_ALIGNMENTSebastian Huber2018-08-0219-216/+0
| | | | | | | | | | | | | | Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment requirement is defined by the use of Chain_Node (consisting of two pointers) to manage the free chain of partitions. It seems that previously the condition CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node) was true on all CPU ports. Now, we need an additional check. Update #3482.
* riscv: Fix CPU_ALIGNMENTSebastian Huber2018-08-021-1/+3
| | | | Update #3433.
* riscv: Rework CPU counter supportSebastian Huber2018-07-274-5/+91
| | | | Update #3433.
* riscv: Add CLINT and PLIC supportSebastian Huber2018-07-251-5/+45
| | | | | | The CLINT and PLIC need some per-processor state. Update #3433.
* riscv: Use wfi instruction for idle taskSebastian Huber2018-07-252-12/+3
| | | | Update #3433.
* riscv: Rework exception handlingSebastian Huber2018-07-256-144/+54
| | | | | | | | | | | Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() functions. Applications can install an exception handler via the fatal error handler to handle synchronous exceptions. Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must be provided by the BSP. Update #3433.
* riscv: New CPU_Exception_frameSebastian Huber2018-07-254-64/+203
| | | | | | | Use the CPU_Interrupt_frame for the volatile context. Add non-volatile registers and extra state on top of it. Update #3433.
* riscv: Add exception codesSebastian Huber2018-07-251-0/+39
| | | | Update #3433.
* powerpc: Fix _CPU_Instruction_illegal()Sebastian Huber2018-07-251-1/+1
| | | | | Apparently the .word assembler directive is not the right thing on this target.
* score: Add _CPU_Instruction_illegal()Sebastian Huber2018-07-2319-0/+100
| | | | | | | | On some architectures/simulators it is difficult to provoke an exception with misaligned or illegal data loads. Use an illegal instruction instead. Update #3433.
* score: Add _CPU_Instruction_no_operation()Sebastian Huber2018-07-2019-0/+100
| | | | | This helps to reduce the use of architecture-specific defines throughout the code base.
* score: Move context validation declarationsSebastian Huber2018-07-2038-203/+199
| | | | | | | The context validation support functions _CPU_Context_validate() and _CPU_Context_volatile_clobber() are used only by one test program (spcontext01). Move the function declarations to the CPU port implementation header file.
* score: Remove obsolete CPU port definesSebastian Huber2018-07-203-34/+0
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* x86_64/console: Add NS16550 polled console driverAmaan Cheval2018-07-112-0/+17
| | | | | | This addition allows us to successfully run the sample hello.exe test. Updates #2898.
* bsp/x86_64: Minimal bootable BSPAmaan Cheval2018-07-1111-0/+893
| | | | | | | | | | | | | | | | Current state: - Basic context initialization and switching code. - Stubbed console (empty functions). - Mostly functional linker script (may need tweaks if we ever want to move away from the large code model (see: CPU_CFLAGS). - Fully functional boot, by using FreeBSD's bootloader to load RTEMS's ELF for UEFI-awareness. In short, the current state with this commit lets us boot, go through the system initialization functions, and then call user application's Init task too. Updates #2898.
* riscv: Add LADDR assembler defineSebastian Huber2018-07-062-2/+12
| | | | | | | An address must be loaded to a register according to the code model. Add LADDR define for use in assembler code. Update #3433.
* riscv: Implement CPU counterSebastian Huber2018-07-062-2/+16
| | | | Update #3433.
* riscv: Clear reservationsSebastian Huber2018-07-055-6/+25
| | | | | | | See also RISC-V User-Level ISA V2.3, comment in section 8.2 "Load-Reserved/Store-Conditional Instructions". Update #3433.
* riscv: Fix fcsr initializationSebastian Huber2018-07-022-1/+19
| | | | Update #3433.
* riscv: Fix SMP context switch supportSebastian Huber2018-06-291-2/+2
| | | | Update #3433.
* riscv: Add SMP context switch supportSebastian Huber2018-06-291-0/+47
| | | | Update #3433.
* riscv: Add floating-point supportSebastian Huber2018-06-298-50/+538
| | | | Update #3433.
* riscv: Fix global constructionSebastian Huber2018-06-291-4/+5
| | | | Update #3433.
* riscv: Add TLS supportSebastian Huber2018-06-292-0/+9
| | | | Update #3433.
* riscv: Remove dead codeSebastian Huber2018-06-291-41/+1
| | | | Update #3433.
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