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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-03 09:54:47 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-05 07:12:24 +0200 |
| commit | e755782bde234350c6263f893b1c4e8d30bb0a53 (patch) | |
| tree | 996842ed7493ec8423822b9a49ea58cd26d6dc03 /cpukit/score/cpu | |
| parent | posix: Check for new <pthread.h> prototypes (diff) | |
| download | rtems-e755782bde234350c6263f893b1c4e8d30bb0a53.tar.bz2 | |
riscv: Clear reservations
See also RISC-V User-Level ISA V2.3, comment in section 8.2
"Load-Reserved/Store-Conditional Instructions".
Update #3433.
Diffstat (limited to 'cpukit/score/cpu')
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/asm.h | 10 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 6 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 11 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-switch.S | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-exception-handler.S | 2 |
5 files changed, 25 insertions, 6 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/asm.h b/cpukit/score/cpu/riscv/include/rtems/asm.h index 259fe3de2c..c3be827be0 100644 --- a/cpukit/score/cpu/riscv/include/rtems/asm.h +++ b/cpukit/score/cpu/riscv/include/rtems/asm.h @@ -171,4 +171,14 @@ #endif .endm +.macro CLEAR_RESERVATIONS REG +#ifdef __riscv_atomic + /* + * Clear reservations, see also RISC-V User-Level ISA V2.3, comment in + * section 8.2 "Load-Reserved/Store-Conditional Instructions". + */ + sc.w zero, zero, (\REG) +#endif +.endm + #endif diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 2220161c9e..e79ce25510 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -64,8 +64,6 @@ extern "C" { #define CPU_LITTLE_ENDIAN TRUE #define CPU_MODES_INTERRUPT_MASK 0x0000000000000001 -#define CPU_PER_CPU_CONTROL_SIZE 0 - #define CPU_CACHE_LINE_BYTES 64 #if __riscv_xlen == 32 @@ -224,10 +222,6 @@ extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) RTEMS_NO_RETURN; #define CPU_MAXIMUM_PROCESSORS 32 -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - typedef uint16_t Priority_bit_map_Word; typedef struct { diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index 9c50be89dd..54c5cf1b79 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -34,7 +34,11 @@ #include <rtems/score/cpu.h> +#ifdef __riscv_atomic +#define CPU_PER_CPU_CONTROL_SIZE 16 +#else #define CPU_PER_CPU_CONTROL_SIZE 0 +#endif #ifdef RTEMS_SMP #define RISCV_CONTEXT_IS_EXECUTING 0 @@ -286,6 +290,13 @@ typedef struct { uintptr_t a1; } RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame; +#ifdef __riscv_atomic +typedef struct { + uint64_t clear_reservations; + uint32_t reserved_for_alignment_of_interrupt_frame[ 2 ]; +} CPU_Per_CPU_control; +#endif + static inline uint32_t _RISCV_Read_FCSR( void ) { uint32_t fcsr; diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S index 6643f21ee9..96c117b3de 100644 --- a/cpukit/score/cpu/riscv/riscv-context-switch.S +++ b/cpukit/score/cpu/riscv/riscv-context-switch.S @@ -136,6 +136,8 @@ SYM(_CPU_Context_switch): sw a3, PER_CPU_ISR_DISPATCH_DISABLE(a2) + CLEAR_RESERVATIONS a2 + ret SYM(_CPU_Context_restore): diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S index b15bab49c7..05bad455ac 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-handler.S +++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S @@ -115,6 +115,8 @@ SYM(ISR_Handler): sw t2, PER_CPU_ISR_NEST_LEVEL(s0) sw t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) + CLEAR_RESERVATIONS s0 + /* Keep sp (Exception frame address) in s1 */ mv s1, sp |