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author | Amaan Cheval <amaan.cheval@gmail.com> | 2018-08-13 16:25:34 +0530 |
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committer | Joel Sherrill <joel@rtems.org> | 2018-08-13 10:48:20 -0500 |
commit | bc7313134f8192214cf74116c0b54d3eb6081fcf (patch) | |
tree | 77479c6478f98046f00a5f2817494fa2e682baf5 /cpukit/score/cpu | |
parent | bsps/x86_64: Add support for RTEMS interrupts (diff) | |
download | rtems-bc7313134f8192214cf74116c0b54d3eb6081fcf.tar.bz2 |
bsps/x86_64: Add APIC timer based clock driver
The APIC timer is calibrated by running the i8254 PIT for a fraction of a
second (determined by PIT_CALIBRATE_DIVIDER) and counting how many times the
APIC counter has ticked. The calibration can be run multiple times (determined
by APIC_TIMER_NUM_CALIBRATIONS) and averaged out.
Updates #2898.
Diffstat (limited to 'cpukit/score/cpu')
-rw-r--r-- | cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h index 09807f1489..4ad50b9f42 100644 --- a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h +++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h @@ -67,6 +67,21 @@ RTEMS_INLINE_ROUTINE void cpuid( : "a" (code) ); } +RTEMS_INLINE_ROUTINE uint64_t rdmsr(uint32_t msr) +{ + uint32_t low, high; + __asm__ volatile ( "rdmsr" : + "=a" (low), "=d" (high) : + "c" (msr) ); + return low | (uint64_t) high << 32; +} + +RTEMS_INLINE_ROUTINE void wrmsr(uint32_t msr, uint32_t low, uint32_t high) +{ + __asm__ volatile ( "wrmsr" : : + "a" (low), "d" (high), "c" (msr) ); +} + RTEMS_INLINE_ROUTINE void amd64_enable_interrupts(void) { __asm__ volatile ( "sti" ); @@ -76,6 +91,14 @@ RTEMS_INLINE_ROUTINE void amd64_disable_interrupts(void) { __asm__ volatile ( "cli" ); } + +RTEMS_INLINE_ROUTINE void stub_io_wait(void) +{ + /* XXX: This likely won't be required on any modern boards, but this function + * exists so it's easier to find all the places it may be used. + */ +} + #endif /* !ASM */ #endif |