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* sparc: Optimize _ISR_Handler()Sebastian Huber2016-11-281-0/+3
| | | | | | Use _Thread_Do_dispatch() instead of _Thread_Dispatch(). Restore the PSR[EF] state of the interrupted context via new system call syscall_irqdis_fp in case floating-point support is enabled.
* score: Robust thread dispatchSebastian Huber2016-11-231-0/+2
| | | | | | | | | | | | On SMP configurations, it is a fatal error to call blocking operating system with interrupts disabled, since this prevents delivery of inter-processor interrupts. This could lead to executing threads which are not allowed to execute resulting in undefined behaviour. The ARM Cortex-M port has a similar problem, since the interrupt state is not a part of the thread context. Update #2811.
* score: Add _ISR_Is_enabled()Sebastian Huber2016-11-181-0/+8
| | | | | | | In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates a level parameter and returns a boolean value. Update #2811.
* sparc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-182-22/+5
| | | | Update #2751.
* score: Add Per_CPU_Control::Interrupt_frameSebastian Huber2016-11-181-5/+0
| | | | Update #2809.
* sparc: Move CPU_Interrupt_frame related definesSebastian Huber2016-11-185-54/+58
| | | | | | Move CPU_Interrupt_frame related defines to <rtems/score/cpuimpl.h>. Update #2809.
* sparc: Rename CPU_Minimum_stack_frameSebastian Huber2016-11-184-26/+26
| | | | | | | | Rename SPARC-specific CPU_Minimum_stack_frame to SPARC_Minimum_stack_frame. Rename SPARC-specific CPU_MINIMUM_STACK_FRAME_SIZE to SPARC_MINIMUM_STACK_FRAME_SIZE. Update #2809.
* rtems: Conditionally define rtems_interrupt_frameSebastian Huber2016-11-181-1/+1
| | | | Update #2808.
* score: Move CPU_PER_CPU_CONTROL_SIZESebastian Huber2016-11-182-42/+43
| | | | | Move CPU_PER_CPU_CONTROL_SIZE and the optional CPU_Per_CPU_control to <rtems/score/cpuimpl.h> to hide it from <rtems.h>.
* score: Remove obsolete definesSebastian Huber2016-11-181-10/+0
| | | | The thread dispatch inline option is no longer used.
* score: Move _CPU_Get_current_per_CPU_control()Sebastian Huber2016-11-102-9/+9
| | | | | Move _CPU_Get_current_per_CPU_control() from <rtems/score/cpu.h> to <rtems/score/cpuimpl.h>.
* sparc: Provide _CPU_Get_thread_executing()Sebastian Huber2016-11-071-0/+4
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* score: Add <rtems/score/cpuimpl.h>Sebastian Huber2016-11-073-0/+35
| | | | | | The aim of this file is to encapsulate CPU port implementation details. This helps to hide implementation details from <rtems.h> which indirectly includes <rtems/score/cpu.h>.
* sparc: Optimize CPU counter supportSebastian Huber2016-06-225-38/+98
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* sparc: Rework CPU counter supportSebastian Huber2016-06-214-26/+88
| | | | | Rework CPU counter support to enable use of the GR740 up-counter via %asr22 and %asr23.
* score: Simplify priority bit map implementationSebastian Huber2016-06-081-9/+0
| | | | | | | | | | The priority bit map can deal with a maximum of 256 priority values ranging from 0 to 255. Consistently use an unsigned int for computation, due to the usual integer promotion rules. Make Priority_bit_map_Word definition architecture-independent and define it to uint16_t. This was already the case for all architectures except PowerPC. Adjust the PowerPC bitmap support accordingly.
* score: Delete CPU_USE_GENERIC_BITFIELD_DATASebastian Huber2016-06-081-6/+0
| | | | | | Rename __log2table into _Bitfield_Leading_zeros since it acually returns the count of leading zeros of an 8-bit integer. The value for zero is a bit odd. Provide it unconditionally.
* score: Add libatomic supportSebastian Huber2016-05-302-212/+0
| | | | Close #2695.
* score: Rename _ISR_Disable_without_giant()Sebastian Huber2016-05-201-2/+2
| | | | | | | | | Rename _ISR_Disable_without_giant() into _ISR_Local_disable(). Rename _ISR_Enable_without_giant() into _ISR_Local_enable(). This is a preparation to remove the Giant lock. Update #2555.
* score: Add CPU_MAXIMUM_PROCESSORSSebastian Huber2016-03-041-0/+2
| | | | Maximum number of processors of all systems supported by this CPU port.
* sparc: Avoid SCORE_EXTERNSebastian Huber2016-02-172-1/+5
| | | | Update #2559.
* sparc: Adjust CPU_CACHE_LINE_BYTES for LEON3Sebastian Huber2016-01-261-2/+2
| | | | Fix for commit a8865f8b415788c4e9bb7f68e38d41aec0e485db.
* score: Introduce CPU_CACHE_LINE_BYTESSebastian Huber2016-01-261-11/+4
| | | | | Add CPU_CACHE_LINE_BYTES for the maximum cache line size in bytes. The actual processor may use no cache or a smaller cache line size.
* sparc: No explicit align of _CPU_Null_fp_contextSebastian Huber2016-01-261-1/+1
| | | | This structure is not performance critical.
* score: Delete obsolete CPU_TIMESTAMP_* definesSebastian Huber2016-01-251-2/+0
| | | | Update #2271.
* sparc: Simplify _CPU_Get_current_per_CPU_control()Sebastian Huber2015-12-101-1/+1
| | | | | | | Drop the superfluous parenthesis since this confuses the C++ compiler of some GCC versions. See also https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67064
* sparc: Fix context switch on SMPDaniel Cederman2015-11-161-0/+3
| | | | | | | | | | | | | | | | We must not load registers (e.g. PSR) from the heir context area before the heir stopped execution. With this patch the write to PSR is divided into two steps. We first update the current window pointer and then we restore the status registers and enable traps. This allows us to move the first write to PSR to be before the write to WIM, as there is now no risk that we get an interrupt where the CWP and WIM would be inconsistent. We only need to make sure that we do not use any of the non-global registers or instructions that affects CWP for three instructions after the write. In the earlier code the non-global %o1 register was used right after the write to PSR, which required the use of three nop:s.
* basedefs.h: Add and use RTEMS_NO_RETURNSebastian Huber2015-10-262-3/+3
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* score: Fix atomic compare exchangeSebastian Huber2015-09-251-2/+6
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* sparc: Add SPARC_USE_SAFE_FP_SUPPORTSebastian Huber2015-06-093-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | The SPARC ABI is a bit special with respect to the floating point context. The complete floating point context is volatile. Thus from an ABI point of view nothing needs to be saved and restored during a context switch. Instead the floating point context must be saved and restored during interrupt processing. Historically the deferred floating point switch is used for SPARC and the complete floating point context is saved and restored during a context switch to the new floating point unit owner. This is a bit dangerous since post-switch actions (e.g. signal handlers) and context switch extensions may silently corrupt the floating point context. The floating point unit is disabled for interrupt handlers. Thus in case an interrupt handler uses the floating point unit then this will result in a trap. On SMP configurations the deferred floating point switch is not supported in principle. So use here a safe floating point support. Safe means that the volatile floating point context is saved and restored around a thread dispatch issued during interrupt processing. Thus post-switch actions and context switch extensions may safely use the floating point unit. Update #2270.
* sparc: Disable FPU in interrupt contextAlexander Krutwig2015-05-302-1/+32
| | | | Update #2270.
* sparc: Remove superfluous FP enableSebastian Huber2015-05-302-22/+7
| | | | | | | The FP context save/restore makes only sense in the context of FP threads. Update #2270.
* sparc: Avoid new window for FP save/restoreSebastian Huber2015-05-301-54/+48
| | | | Update #2270.
* sparc: Improve _CPU_Context_validate()Alexander Krutwig2015-05-291-46/+49
| | | | | | | Write the pattern only once to the entry register window and the floating point registers. Update #2270.
* sparc: Add static assertionSebastian Huber2015-05-261-0/+5
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* sparc: Delete unused CONTEXT_CONTROL_SIZESebastian Huber2015-05-261-3/+0
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* sparc: Delete unused ISF_STACK_FRAME_OFFSETSebastian Huber2015-05-261-2/+0
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* sparc: Add static offset assertionsSebastian Huber2015-05-261-0/+32
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* sparc: Add support for sptests/spcontext01Alexander Krutwig2015-05-214-10/+528
| | | | | | Implement _CPU_Context_validate() and _CPU_Context_volatile_clobber(). Update #2270.
* sparc: Ensure interrupt service after ISR enableSebastian Huber2015-03-251-1/+8
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* cpukit: add and use CPU_Uint32ptr typeGedare Bloom2015-03-161-0/+3
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* score: Delete unused CPU_UNROLL_ENQUEUE_PRIORITYSebastian Huber2015-03-051-16/+0
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* score: Add _CPU_SMP_Prepare_start_multitasking()Sebastian Huber2015-02-171-6/+2
| | | | Update #2268.
* SPARC: optimize IRQ enable & disableDaniel Hellstrom2014-12-041-2/+16
| | | | | | | | | | | | | | | | * Coding style cleanups. * Use OS reserved trap 0x89 for IRQ Disable * Use OS reserved trap 0x8A for IRQ Enable * Add to SPARC CPU supplement documentation This will result in faster Disable/Enable code since the system trap handler does not need to decode which function the user wants. Besides the IRQ disable/enabled can now be inline which avoids the caller to take into account that o0-o7+g1-g4 registers are destroyed by trap handler. It was also possible to reduce the interrupt trap handler by five instructions due to this.
* SPARC: Fatal_halt use source and exit codesDaniel Hellstrom2014-10-061-8/+2
| | | | | | | | | | | | | | | The Fatal_halt handler now have two options, either halt as before or enter system error state to return to debugger or simulator. The exit-code is now also propagated to the debugger which is very useful for testing. The CPU_Fatal_halt handler was split up into two, since the only the LEON3 support the CPU power down. The LEON3 halt now uses the power-down instruction to save CPU power. This doesn't stop a potential watch-dog timer from expiring.
* sparc: Add commentSebastian Huber2014-09-181-0/+5
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* score: Rename _BSP_Exception_frame_print()Sebastian Huber2014-09-111-8/+1
| | | | | Rename _BSP_Exception_frame_print() to _CPU_Exception_frame_print() to be in line with other CPU port functions.
* Let CPU/BSP Fatal handler have access to sourceDaniel Hellstrom2014-09-101-1/+1
| | | | | | | | | Without the source the error code does not say that much. Let it be up to the CPU/BSP to determine the error code reported on fatal shutdown. This patch does not change the current behaviour, just adds the option to handle the source of the fatal halt.
* score: Define _CPU_Start_multitasking only for LEON SPARC, not SPARC in generalDaniel Cederman2014-09-011-2/+4
| | | | | Rename _BSP_Start_multitasking to _LEON3_Start_multitasking to show that it is LEON specific
* score/sparc: Add comment on icache flush after trap table updateDaniel Cederman2014-08-221-3/+14
| | | | | | | | | | | Changes to the trap table might be missed by other cores. If the system state is up, the other cores can be notified using SMP messages that they need to flush their icache. If the up state has not been reached there is no need to notify other cores. They will do an automatic flush of the icache just after entering the up state, but before enabling interrupts. Cache invalidation is required for both single and multiprocessor systems.
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